From 77afc75f69940eba90bc4f33ab046bf547910e2f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sun, 9 Aug 2020 17:17:00 +0200 Subject: oss-fuzz/build: remove LIB_FUZZING_ENGINE Meson build scripts will only include qemu-fuzz-TARGET rules if configured with --enable-fuzzing, and that takes care of adding -fsanitize=fuzzer. Therefore we can just specify the configure option and stop modifying the CFLAGS and CONFIG_FUZZ options in the "make" invocation. Signed-off-by: Paolo Bonzini --- scripts/oss-fuzz/build.sh | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/scripts/oss-fuzz/build.sh b/scripts/oss-fuzz/build.sh index a07b3022e8..52430cb620 100755 --- a/scripts/oss-fuzz/build.sh +++ b/scripts/oss-fuzz/build.sh @@ -20,7 +20,7 @@ # e.g. # $CXX $CXXFLAGS -std=c++11 -Iinclude \ # /path/to/name_of_fuzzer.cc -o $OUT/name_of_fuzzer \ -# $LIB_FUZZING_ENGINE /path/to/library.a +# -fsanitize=fuzzer /path/to/library.a fatal () { echo "Error : ${*}, exiting." @@ -54,10 +54,6 @@ mkdir -p $OSS_FUZZ_BUILD_DIR || fatal "mkdir $OSS_FUZZ_BUILD_DIR failed" cd $OSS_FUZZ_BUILD_DIR || fatal "cd $OSS_FUZZ_BUILD_DIR failed" -if [ -z ${LIB_FUZZING_ENGINE+x} ]; then - LIB_FUZZING_ENGINE="-fsanitize=fuzzer" -fi - if [ -z ${OUT+x} ]; then DEST_DIR=$(realpath "./DEST_DIR") else @@ -67,14 +63,12 @@ fi mkdir -p "$DEST_DIR/lib/" # Copy the shared libraries here # Build once to get the list of dynamic lib paths, and copy them over -../configure --disable-werror --cc="$CC" --cxx="$CXX" \ +../configure --disable-werror --cc="$CC" --cxx="$CXX" --enable-fuzzing \ --extra-cflags="$EXTRA_CFLAGS" --target-list="i386-softmmu" -if ! make CONFIG_FUZZ=y CFLAGS="$LIB_FUZZING_ENGINE" "-j$(nproc)" \ - i386-softmmu/fuzz; then +if ! make "-j$(nproc)" i386-softmmu/fuzz; then fatal "Build failed. Please specify a compiler with fuzzing support"\ - "using the \$CC and \$CXX environemnt variables, or specify a"\ - "\$LIB_FUZZING_ENGINE compatible with your compiler"\ + "using the \$CC and \$CXX environemnt variables"\ "\nFor example: CC=clang CXX=clang++ $0" fi @@ -87,7 +81,7 @@ rm ./i386-softmmu/qemu-fuzz-i386 ../configure --bindir="$DEST_DIR" --datadir="$DEST_DIR/data/" --disable-werror \ --cc="$CC" --cxx="$CXX" --extra-cflags="$EXTRA_CFLAGS" \ --extra-ldflags="-Wl,-rpath,'\$\$ORIGIN/lib'" -make CONFIG_FUZZ=y CFLAGS="$LIB_FUZZING_ENGINE" "-j$(nproc)" i386-softmmu/fuzz +make "-j$(nproc)" i386-softmmu/fuzz # Copy over the datadir cp -r ../pc-bios/ "$DEST_DIR/pc-bios" -- cgit v1.2.3-55-g7522 From bf708f3c4a0633625acdff63ddcceeb717333d5b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 8 Oct 2019 19:27:24 +0400 Subject: optionrom: simplify Makefile Make it independent from the rules.mak, and clean up to use pattern rules. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- pc-bios/optionrom/Makefile | 67 ++++++++++++++++++++++++++++------------------ 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/pc-bios/optionrom/Makefile b/pc-bios/optionrom/Makefile index e33a24da0d..51cb6ca9d8 100644 --- a/pc-bios/optionrom/Makefile +++ b/pc-bios/optionrom/Makefile @@ -1,13 +1,16 @@ -all: build-all +CURRENT_MAKEFILE := $(realpath $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) +SRC_DIR := $(dir $(CURRENT_MAKEFILE)) +TOPSRC_DIR := $(SRC_DIR)/../.. +VPATH = $(SRC_DIR) + +all: multiboot.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin # Dummy command so that make thinks it has done something @true include ../../config-host.mak -include $(SRC_PATH)/rules.mak - -$(call set-vpath, $(SRC_PATH)/pc-bios/optionrom) -.PHONY : all clean build-all +quiet-command = $(if $(V),$1,$(if $(2),@printf " %-7s %s\n" $2 $3 && $1, @$1)) +cc-option = $(if $(shell $(CC) $1 -S -o /dev/null -xc /dev/null >/dev/null 2>&1 && echo OK), $1, $2) # Compiling with no optimization creates ROMs that are too large ifeq ($(lastword $(filter -O%, -O0 $(CFLAGS))),-O0) @@ -15,48 +18,60 @@ override CFLAGS += -O2 endif override CFLAGS += -march=i486 -# Drop -fstack-protector and the like -QEMU_CFLAGS := $(filter -W%, $(QEMU_CFLAGS)) $(CFLAGS_NOPIE) -ffreestanding -QEMU_CFLAGS += $(call cc-option, $(QEMU_CFLAGS), -fno-stack-protector) -QEMU_CFLAGS += $(call cc-option, $(QEMU_CFLAGS), -m16) -ifeq ($(filter -m16, $(QEMU_CFLAGS)),) +# Flags for dependency generation +override CPPFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d + +override CFLAGS += $(filter -W%, $(QEMU_CFLAGS)) +override CFLAGS += $(CFLAGS_NOPIE) -ffreestanding -I$(TOPSRC_DIR)/include +override CFLAGS += $(call cc-option, -fno-stack-protector) +override CFLAGS += $(call cc-option, -m16) + +ifeq ($(filter -m16, $(CFLAGS)),) # Attempt to work around compilers that lack -m16 (GCC <= 4.8, clang <= ??) # On GCC we add -fno-toplevel-reorder to keep the order of asm blocks with # respect to the rest of the code. clang does not have -fno-toplevel-reorder, # but it places all asm blocks at the beginning and we're relying on it for # the option ROM header. So just force clang not to use the integrated # assembler, which doesn't support .code16gcc. -QEMU_CFLAGS += $(call cc-option, $(QEMU_CFLAGS), -fno-toplevel-reorder) -QEMU_CFLAGS += $(call cc-option, $(QEMU_CFLAGS), -no-integrated-as) -QEMU_CFLAGS += -m32 -include $(SRC_PATH)/pc-bios/optionrom/code16gcc.h +override CFLAGS += $(call cc-option, -fno-toplevel-reorder) +override CFLAGS += $(call cc-option, -no-integrated-as) +override CFLAGS += -m32 -include $(SRC_DIR)/code16gcc.h endif -QEMU_INCLUDES += -I$(SRC_PATH) - Wa = -Wa, -ASFLAGS += -32 -QEMU_CFLAGS += $(call cc-c-option, $(QEMU_CFLAGS), $(Wa)-32) +override ASFLAGS += -32 +override CFLAGS += $(call cc-option, $(Wa)-32) -build-all: multiboot.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin -# suppress auto-removal of intermediate files -.SECONDARY: +LD_I386_EMULATION ?= elf_i386 +override LDFLAGS = -m $(LD_I386_EMULATION) -T $(SRC_DIR)/flat.lds +override LDFLAGS += $(LDFLAGS_NOPIE) +all: multiboot.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin pvh.bin + +pvh.img: pvh.o pvh_main.o %.o: %.S - $(call quiet-command,$(CPP) $(QEMU_INCLUDES) $(QEMU_DGFLAGS) -c -o - $< | $(AS) $(ASFLAGS) -o $@,"AS","$(TARGET_DIR)$@") + $(call quiet-command,$(CPP) $(CPPFLAGS) -c -o - $< | $(AS) $(ASFLAGS) -o $@,"AS","$@") -pvh.img: pvh.o pvh_main.o - $(call quiet-command,$(LD) $(LDFLAGS_NOPIE) -m $(LD_I386_EMULATION) -T $(SRC_PATH)/pc-bios/optionrom/flat.lds -s -o $@ $^,"BUILD","$(TARGET_DIR)$@") +%.o: %.c + $(call quiet-command,$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@,"CC","$@") %.img: %.o - $(call quiet-command,$(LD) $(LDFLAGS_NOPIE) -m $(LD_I386_EMULATION) -T $(SRC_PATH)/pc-bios/optionrom/flat.lds -s -o $@ $<,"BUILD","$(TARGET_DIR)$@") + $(call quiet-command,$(LD) $(LDFLAGS) -s -o $@ $^,"BUILD","$@") %.raw: %.img - $(call quiet-command,$(OBJCOPY) -O binary -j .text $< $@,"BUILD","$(TARGET_DIR)$@") + $(call quiet-command,$(OBJCOPY) -O binary -j .text $< $@,"BUILD","$@") %.bin: %.raw - $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/signrom.py $< $@,"SIGN","$(TARGET_DIR)$@") + $(call quiet-command,$(PYTHON) $(TOPSRC_DIR)/scripts/signrom.py $< $@,"SIGN","$@") + +include $(wildcard *.d) clean: rm -f *.o *.d *.raw *.img *.bin *~ + +# suppress auto-removal of intermediate files +.SECONDARY: + +.PHONY: all clean -- cgit v1.2.3-55-g7522 From 22fb2ab096ff55672ef9f43e37ed510b14dc5b79 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 7 Aug 2020 16:14:52 +0200 Subject: pc-bios/s390-ccw: do not use rules.mak Signed-off-by: Paolo Bonzini --- pc-bios/s390-ccw/Makefile | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/pc-bios/s390-ccw/Makefile b/pc-bios/s390-ccw/Makefile index 50bc880272..cc0f77baa6 100644 --- a/pc-bios/s390-ccw/Makefile +++ b/pc-bios/s390-ccw/Makefile @@ -3,10 +3,26 @@ all: build-all @true include ../../config-host.mak -include $(SRC_PATH)/rules.mak +quiet-command = $(if $(V),$1,$(if $(2),@printf " %-7s %s\n" $2 $3 && $1, @$1)) +cc-option = $(if $(shell $(CC) $1 -S -o /dev/null -xc /dev/null > /dev/null \ + 2>&1 && echo OK), $1, $2) + +VPATH_SUFFIXES = %.c %.h %.S %.m %.mak %.sh %.rc Kconfig% %.json.in +set-vpath = $(if $1,$(foreach PATTERN,$(VPATH_SUFFIXES),$(eval vpath $(PATTERN) $1))) $(call set-vpath, $(SRC_PATH)/pc-bios/s390-ccw) +# Flags for dependency generation +QEMU_DGFLAGS = -MMD -MP -MT $@ -MF $(@D)/$(*F).d + +%.o: %.c + $(call quiet-command,$(CC) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) \ + -c -o $@ $<,"CC","$(TARGET_DIR)$@") + +%.o: %.S + $(call quiet-command,$(CCAS) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) \ + -c -o $@ $<,"CCAS","$(TARGET_DIR)$@") + .PHONY : all clean build-all OBJECTS = start.o main.o bootmap.o jump2ipl.o sclp.o menu.o \ -- cgit v1.2.3-55-g7522 From 243af0225ab37c642d73e4002b233af728119f72 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Feb 2020 12:20:10 +0100 Subject: trace: switch position of headers to what Meson requires Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$( --- .gitignore | 1 - Makefile | 46 +++++++++++++++++++------------- Makefile.objs | 1 - accel/kvm/trace.h | 1 + accel/tcg/cputlb.c | 2 +- accel/tcg/trace.h | 1 + accel/tcg/user-exec.c | 2 +- audio/trace.h | 1 + authz/trace.h | 1 + backends/tpm/trace.h | 1 + backends/trace.h | 1 + block/trace.h | 1 + chardev/trace.h | 1 + crypto/trace.h | 1 + dma-helpers.c | 2 +- exec.c | 2 +- gdbstub.c | 2 +- hw/9pfs/trace.h | 1 + hw/acpi/trace.h | 1 + hw/alpha/trace.h | 1 + hw/arm/trace.h | 1 + hw/audio/trace.h | 1 + hw/block/dataplane/trace.h | 1 + hw/block/trace.h | 1 + hw/char/trace.h | 1 + hw/core/cpu.c | 2 +- hw/core/trace.h | 1 + hw/display/trace.h | 1 + hw/dma/trace.h | 1 + hw/gpio/trace.h | 1 + hw/hppa/trace.h | 1 + hw/hyperv/trace.h | 1 + hw/i2c/trace.h | 1 + hw/i386/trace.h | 1 + hw/i386/xen/trace.h | 1 + hw/ide/trace.h | 1 + hw/input/trace.h | 1 + hw/intc/trace.h | 1 + hw/isa/trace.h | 1 + hw/mem/trace.h | 1 + hw/mips/trace.h | 1 + hw/misc/macio/trace.h | 1 + hw/misc/trace.h | 1 + hw/net/trace.h | 1 + hw/nvram/trace.h | 1 + hw/pci-host/trace.h | 1 + hw/pci/trace.h | 1 + hw/ppc/trace.h | 1 + hw/rdma/trace.h | 1 + hw/rdma/vmw/trace.h | 1 + hw/riscv/trace.h | 1 + hw/rtc/trace.h | 1 + hw/s390x/trace.h | 1 + hw/scsi/trace.h | 1 + hw/sd/trace.h | 1 + hw/sparc/trace.h | 1 + hw/sparc64/trace.h | 1 + hw/ssi/trace.h | 1 + hw/timer/trace.h | 1 + hw/tpm/trace.h | 1 + hw/usb/trace.h | 1 + hw/vfio/trace.h | 1 + hw/virtio/trace.h | 1 + hw/watchdog/trace.h | 1 + hw/xen/trace.h | 1 + include/user/syscall-trace.h | 2 +- io/trace.h | 1 + job-qmp.c | 2 +- job.c | 2 +- linux-user/trace.h | 1 + migration/trace.h | 1 + monitor/trace.h | 1 + nbd/trace.h | 1 + net/trace.h | 1 + qapi/trace.h | 1 + qom/trace.h | 1 + scripts/tracetool/format/c.py | 5 +--- scripts/tracetool/format/tcg_h.py | 2 +- scripts/tracetool/format/tcg_helper_c.py | 2 +- scsi/trace.h | 1 + softmmu/balloon.c | 2 +- softmmu/ioport.c | 2 +- softmmu/memory.c | 2 +- softmmu/vl.c | 2 +- target/arm/trace.h | 1 + target/hppa/trace.h | 1 + target/i386/trace.h | 1 + target/mips/trace.h | 1 + target/ppc/trace.h | 1 + target/riscv/trace.h | 1 + target/s390x/trace.h | 1 + target/sparc/trace.h | 1 + trace/control-target.c | 2 +- trace/control.c | 2 +- ui/trace.h | 1 + util/trace.h | 1 + 96 files changed, 121 insertions(+), 41 deletions(-) create mode 100644 accel/kvm/trace.h create mode 100644 accel/tcg/trace.h create mode 100644 audio/trace.h create mode 100644 authz/trace.h create mode 100644 backends/tpm/trace.h create mode 100644 backends/trace.h create mode 100644 block/trace.h create mode 100644 chardev/trace.h create mode 100644 crypto/trace.h create mode 100644 hw/9pfs/trace.h create mode 100644 hw/acpi/trace.h create mode 100644 hw/alpha/trace.h create mode 100644 hw/arm/trace.h create mode 100644 hw/audio/trace.h create mode 100644 hw/block/dataplane/trace.h create mode 100644 hw/block/trace.h create mode 100644 hw/char/trace.h create mode 100644 hw/core/trace.h create mode 100644 hw/display/trace.h create mode 100644 hw/dma/trace.h create mode 100644 hw/gpio/trace.h create mode 100644 hw/hppa/trace.h create mode 100644 hw/hyperv/trace.h create mode 100644 hw/i2c/trace.h create mode 100644 hw/i386/trace.h create mode 100644 hw/i386/xen/trace.h create mode 100644 hw/ide/trace.h create mode 100644 hw/input/trace.h create mode 100644 hw/intc/trace.h create mode 100644 hw/isa/trace.h create mode 100644 hw/mem/trace.h create mode 100644 hw/mips/trace.h create mode 100644 hw/misc/macio/trace.h create mode 100644 hw/misc/trace.h create mode 100644 hw/net/trace.h create mode 100644 hw/nvram/trace.h create mode 100644 hw/pci-host/trace.h create mode 100644 hw/pci/trace.h create mode 100644 hw/ppc/trace.h create mode 100644 hw/rdma/trace.h create mode 100644 hw/rdma/vmw/trace.h create mode 100644 hw/riscv/trace.h create mode 100644 hw/rtc/trace.h create mode 100644 hw/s390x/trace.h create mode 100644 hw/scsi/trace.h create mode 100644 hw/sd/trace.h create mode 100644 hw/sparc/trace.h create mode 100644 hw/sparc64/trace.h create mode 100644 hw/ssi/trace.h create mode 100644 hw/timer/trace.h create mode 100644 hw/tpm/trace.h create mode 100644 hw/usb/trace.h create mode 100644 hw/vfio/trace.h create mode 100644 hw/virtio/trace.h create mode 100644 hw/watchdog/trace.h create mode 100644 hw/xen/trace.h create mode 100644 io/trace.h create mode 100644 linux-user/trace.h create mode 100644 migration/trace.h create mode 100644 monitor/trace.h create mode 100644 nbd/trace.h create mode 100644 net/trace.h create mode 100644 qapi/trace.h create mode 100644 qom/trace.h create mode 100644 scsi/trace.h create mode 100644 target/arm/trace.h create mode 100644 target/hppa/trace.h create mode 100644 target/i386/trace.h create mode 100644 target/mips/trace.h create mode 100644 target/ppc/trace.h create mode 100644 target/riscv/trace.h create mode 100644 target/s390x/trace.h create mode 100644 target/sparc/trace.h create mode 100644 ui/trace.h create mode 100644 util/trace.h diff --git a/.gitignore b/.gitignore index 2992d15931..656e39050b 100644 --- a/.gitignore +++ b/.gitignore @@ -146,7 +146,6 @@ docker-src.* *~ *.ast_raw *.depend_raw -trace.h trace.c trace-ust.h trace-ust.h diff --git a/Makefile b/Makefile index 13dd708c4a..00cadebf99 100644 --- a/Makefile +++ b/Makefile @@ -159,8 +159,8 @@ generated-files-$(CONFIG_TRACE_UST) += trace-ust-all.c generated-files-y += module_block.h -TRACE_HEADERS = trace-root.h $(trace-events-subdirs:%=%/trace.h) -TRACE_SOURCES = trace-root.c $(trace-events-subdirs:%=%/trace.c) +TRACE_HEADERS = trace/trace-root.h +TRACE_SOURCES = trace/trace-root.c TRACE_DTRACE = ifdef CONFIG_TRACE_DTRACE TRACE_HEADERS += trace-dtrace-root.h $(trace-events-subdirs:%=%/trace-dtrace.h) @@ -170,33 +170,37 @@ ifdef CONFIG_TRACE_UST TRACE_HEADERS += trace-ust-root.h $(trace-events-subdirs:%=%/trace-ust.h) endif -generated-files-y += $(TRACE_HEADERS) -generated-files-y += $(TRACE_SOURCES) generated-files-y += $(BUILD_DIR)/trace-events-all generated-files-y += .git-submodule-status trace-group-name = $(shell dirname $1 | sed -e 's/[^a-zA-Z0-9]/_/g') +trace-group-suffix = $(shell echo $1 | sed -e 's/[^a-zA-Z0-9]/_/g') tracetool-y = $(SRC_PATH)/scripts/tracetool.py tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") -%/trace.h: %/trace.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -%/trace.h-timestamp: $(SRC_PATH)/%/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +define __trace_rules +TRACE_HEADERS += trace/trace-$2.h +TRACE_SOURCES += trace/trace-$2.c +trace-obj-y += trace/trace-$2.o +trace/trace-$2.h: trace/trace-$2.h-timestamp + @cmp $$< $$@ >/dev/null 2>&1 || cp $$< $$@ +trace/trace-$2.h-timestamp: $(SRC_PATH)/$1/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak $(call quiet-command,$(TRACETOOL) \ - --group=$(call trace-group-name,$@) \ + --group=$2 \ --format=h \ --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") + $$< > $$@,"GEN","$$(@:%-timestamp=%)") -%/trace.c: %/trace.c-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -%/trace.c-timestamp: $(SRC_PATH)/%/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/trace-$2.c: trace/trace-$2.c-timestamp + @cmp $$< $$@ >/dev/null 2>&1 || cp $$< $$@ +trace/trace-$2.c-timestamp: $(SRC_PATH)/$1/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak $(call quiet-command,$(TRACETOOL) \ - --group=$(call trace-group-name,$@) \ + --group=$2 \ --format=c \ --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") + $$< > $$@,"GEN","$$(@:%-timestamp=%)") +endef %/trace-ust.h: %/trace-ust.h-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ @@ -222,18 +226,18 @@ tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") %/trace-dtrace.o: %/trace-dtrace.dtrace $(tracetool-y) -trace-root.h: trace-root.h-timestamp +trace/trace-root.h: trace/trace-root.h-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-root.h-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/trace-root.h-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak $(call quiet-command,$(TRACETOOL) \ --group=root \ --format=h \ --backends=$(TRACE_BACKENDS) \ $< > $@,"GEN","$(@:%-timestamp=%)") -trace-root.c: trace-root.c-timestamp +trace/trace-root.c: trace/trace-root.c-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-root.c-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/trace-root.c-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak $(call quiet-command,$(TRACETOOL) \ --group=root \ --format=c \ @@ -477,6 +481,12 @@ dummy := $(call unnest-vars,, \ common-obj-m \ trace-obj-y) +dummy := $(foreach DIR,$(trace-events-subdirs),$(eval $(call __trace_rules,$(DIR),$(call trace-group-suffix,$(DIR))))) + +generated-files-y += $(TRACE_HEADERS) +generated-files-y += $(TRACE_SOURCES) + + include $(SRC_PATH)/tests/Makefile.include all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all modules $(vhost-user-json-y) diff --git a/Makefile.objs b/Makefile.objs index d22b3b45d7..3823463c23 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -209,7 +209,6 @@ trace-events-subdirs += util trace-events-files = $(SRC_PATH)/trace-events $(trace-events-subdirs:%=$(SRC_PATH)/%/trace-events) trace-obj-y = trace-root.o -trace-obj-y += $(trace-events-subdirs:%=%/trace.o) trace-obj-$(CONFIG_TRACE_UST) += trace-ust-all.o trace-obj-$(CONFIG_TRACE_DTRACE) += trace-dtrace-root.o trace-obj-$(CONFIG_TRACE_DTRACE) += $(trace-events-subdirs:%=%/trace-dtrace.o) diff --git a/accel/kvm/trace.h b/accel/kvm/trace.h new file mode 100644 index 0000000000..67c935a6f7 --- /dev/null +++ b/accel/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-accel_kvm.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5698292749..5349ee6b0e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -34,7 +34,7 @@ #include "qemu/atomic.h" #include "qemu/atomic128.h" #include "translate-all.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "trace/mem.h" #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" diff --git a/accel/tcg/trace.h b/accel/tcg/trace.h new file mode 100644 index 0000000000..db61fad3c6 --- /dev/null +++ b/accel/tcg/trace.h @@ -0,0 +1 @@ +#include "trace/trace-accel_tcg.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d8b027f8c1..1d34c57ff5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,7 +26,7 @@ #include "translate-all.h" #include "exec/helper-proto.h" #include "qemu/atomic128.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "trace/mem.h" #undef EAX diff --git a/audio/trace.h b/audio/trace.h new file mode 100644 index 0000000000..4072a11b0f --- /dev/null +++ b/audio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-audio.h" diff --git a/authz/trace.h b/authz/trace.h new file mode 100644 index 0000000000..3176c127f7 --- /dev/null +++ b/authz/trace.h @@ -0,0 +1 @@ +#include "trace/trace-authz.h" diff --git a/backends/tpm/trace.h b/backends/tpm/trace.h new file mode 100644 index 0000000000..40c4729884 --- /dev/null +++ b/backends/tpm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-backends_tpm.h" diff --git a/backends/trace.h b/backends/trace.h new file mode 100644 index 0000000000..77fe57f36c --- /dev/null +++ b/backends/trace.h @@ -0,0 +1 @@ +#include "trace/trace-backends.h" diff --git a/block/trace.h b/block/trace.h new file mode 100644 index 0000000000..3a436e6c7f --- /dev/null +++ b/block/trace.h @@ -0,0 +1 @@ +#include "trace/trace-block.h" diff --git a/chardev/trace.h b/chardev/trace.h new file mode 100644 index 0000000000..eb4f9027a1 --- /dev/null +++ b/chardev/trace.h @@ -0,0 +1 @@ +#include "trace/trace-chardev.h" diff --git a/crypto/trace.h b/crypto/trace.h new file mode 100644 index 0000000000..a9af0f315c --- /dev/null +++ b/crypto/trace.h @@ -0,0 +1 @@ +#include "trace/trace-crypto.h" diff --git a/dma-helpers.c b/dma-helpers.c index 2a77b5a9cb..41ef24a63b 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "sysemu/block-backend.h" #include "sysemu/dma.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "qemu/thread.h" #include "qemu/main-loop.h" #include "sysemu/cpus.h" diff --git a/exec.c b/exec.c index 6f381f98e2..8047bf2ff9 100644 --- a/exec.c +++ b/exec.c @@ -50,7 +50,7 @@ #include "sysemu/hw_accel.h" #include "exec/address-spaces.h" #include "sysemu/xen-mapcache.h" -#include "trace-root.h" +#include "trace/trace-root.h" #ifdef CONFIG_FALLOCATE_PUNCH_HOLE #include diff --git a/gdbstub.c b/gdbstub.c index f3a318cd7f..9dfb6e4142 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -30,7 +30,7 @@ #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/module.h" -#include "trace-root.h" +#include "trace/trace-root.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" #else diff --git a/hw/9pfs/trace.h b/hw/9pfs/trace.h new file mode 100644 index 0000000000..6104fe2a77 --- /dev/null +++ b/hw/9pfs/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_9pfs.h" diff --git a/hw/acpi/trace.h b/hw/acpi/trace.h new file mode 100644 index 0000000000..a7f7da7009 --- /dev/null +++ b/hw/acpi/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_acpi.h" diff --git a/hw/alpha/trace.h b/hw/alpha/trace.h new file mode 100644 index 0000000000..20fe698191 --- /dev/null +++ b/hw/alpha/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_alpha.h" diff --git a/hw/arm/trace.h b/hw/arm/trace.h new file mode 100644 index 0000000000..91337aa6b0 --- /dev/null +++ b/hw/arm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_arm.h" diff --git a/hw/audio/trace.h b/hw/audio/trace.h new file mode 100644 index 0000000000..5c7516a4d1 --- /dev/null +++ b/hw/audio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_audio.h" diff --git a/hw/block/dataplane/trace.h b/hw/block/dataplane/trace.h new file mode 100644 index 0000000000..240cc59834 --- /dev/null +++ b/hw/block/dataplane/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_block_dataplane.h" diff --git a/hw/block/trace.h b/hw/block/trace.h new file mode 100644 index 0000000000..cde210ae69 --- /dev/null +++ b/hw/block/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_block.h" diff --git a/hw/char/trace.h b/hw/char/trace.h new file mode 100644 index 0000000000..c2df66af2e --- /dev/null +++ b/hw/char/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_char.h" diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 594441a150..22bc3f974a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -31,7 +31,7 @@ #include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "qemu/plugin.h" CPUInterruptHandler cpu_interrupt_handler; diff --git a/hw/core/trace.h b/hw/core/trace.h new file mode 100644 index 0000000000..23dfd61c49 --- /dev/null +++ b/hw/core/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_core.h" diff --git a/hw/display/trace.h b/hw/display/trace.h new file mode 100644 index 0000000000..4ed0e9165b --- /dev/null +++ b/hw/display/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_display.h" diff --git a/hw/dma/trace.h b/hw/dma/trace.h new file mode 100644 index 0000000000..4bcb28b47c --- /dev/null +++ b/hw/dma/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_dma.h" diff --git a/hw/gpio/trace.h b/hw/gpio/trace.h new file mode 100644 index 0000000000..8b139071bc --- /dev/null +++ b/hw/gpio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_gpio.h" diff --git a/hw/hppa/trace.h b/hw/hppa/trace.h new file mode 100644 index 0000000000..4e8b52dc28 --- /dev/null +++ b/hw/hppa/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_hppa.h" diff --git a/hw/hyperv/trace.h b/hw/hyperv/trace.h new file mode 100644 index 0000000000..7f2a88881b --- /dev/null +++ b/hw/hyperv/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_hyperv.h" diff --git a/hw/i2c/trace.h b/hw/i2c/trace.h new file mode 100644 index 0000000000..4843a8d544 --- /dev/null +++ b/hw/i2c/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_i2c.h" diff --git a/hw/i386/trace.h b/hw/i386/trace.h new file mode 100644 index 0000000000..37a9f67e5d --- /dev/null +++ b/hw/i386/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_i386.h" diff --git a/hw/i386/xen/trace.h b/hw/i386/xen/trace.h new file mode 100644 index 0000000000..a02bf755dc --- /dev/null +++ b/hw/i386/xen/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_i386_xen.h" diff --git a/hw/ide/trace.h b/hw/ide/trace.h new file mode 100644 index 0000000000..e060e0aef1 --- /dev/null +++ b/hw/ide/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_ide.h" diff --git a/hw/input/trace.h b/hw/input/trace.h new file mode 100644 index 0000000000..d1cc5d924c --- /dev/null +++ b/hw/input/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_input.h" diff --git a/hw/intc/trace.h b/hw/intc/trace.h new file mode 100644 index 0000000000..02394aea20 --- /dev/null +++ b/hw/intc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_intc.h" diff --git a/hw/isa/trace.h b/hw/isa/trace.h new file mode 100644 index 0000000000..501205cfc1 --- /dev/null +++ b/hw/isa/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_isa.h" diff --git a/hw/mem/trace.h b/hw/mem/trace.h new file mode 100644 index 0000000000..2f2c945407 --- /dev/null +++ b/hw/mem/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_mem.h" diff --git a/hw/mips/trace.h b/hw/mips/trace.h new file mode 100644 index 0000000000..8d1fd7c9e2 --- /dev/null +++ b/hw/mips/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_mips.h" diff --git a/hw/misc/macio/trace.h b/hw/misc/macio/trace.h new file mode 100644 index 0000000000..34a3cf1b42 --- /dev/null +++ b/hw/misc/macio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_misc_macio.h" diff --git a/hw/misc/trace.h b/hw/misc/trace.h new file mode 100644 index 0000000000..1ab6923d11 --- /dev/null +++ b/hw/misc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_misc.h" diff --git a/hw/net/trace.h b/hw/net/trace.h new file mode 100644 index 0000000000..93249af0ac --- /dev/null +++ b/hw/net/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_net.h" diff --git a/hw/nvram/trace.h b/hw/nvram/trace.h new file mode 100644 index 0000000000..88fa900ad3 --- /dev/null +++ b/hw/nvram/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_nvram.h" diff --git a/hw/pci-host/trace.h b/hw/pci-host/trace.h new file mode 100644 index 0000000000..93ec814a73 --- /dev/null +++ b/hw/pci-host/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_pci_host.h" diff --git a/hw/pci/trace.h b/hw/pci/trace.h new file mode 100644 index 0000000000..3dd773e22a --- /dev/null +++ b/hw/pci/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_pci.h" diff --git a/hw/ppc/trace.h b/hw/ppc/trace.h new file mode 100644 index 0000000000..87c4198e61 --- /dev/null +++ b/hw/ppc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_ppc.h" diff --git a/hw/rdma/trace.h b/hw/rdma/trace.h new file mode 100644 index 0000000000..b3fa8ebc51 --- /dev/null +++ b/hw/rdma/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_rdma.h" diff --git a/hw/rdma/vmw/trace.h b/hw/rdma/vmw/trace.h new file mode 100644 index 0000000000..3ebc9fb7ad --- /dev/null +++ b/hw/rdma/vmw/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_rdma_vmw.h" diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h new file mode 100644 index 0000000000..8c0e3ca1f3 --- /dev/null +++ b/hw/riscv/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_riscv.h" diff --git a/hw/rtc/trace.h b/hw/rtc/trace.h new file mode 100644 index 0000000000..cfd5d6ee62 --- /dev/null +++ b/hw/rtc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_rtc.h" diff --git a/hw/s390x/trace.h b/hw/s390x/trace.h new file mode 100644 index 0000000000..d6568b3648 --- /dev/null +++ b/hw/s390x/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_s390x.h" diff --git a/hw/scsi/trace.h b/hw/scsi/trace.h new file mode 100644 index 0000000000..4ce2673582 --- /dev/null +++ b/hw/scsi/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_scsi.h" diff --git a/hw/sd/trace.h b/hw/sd/trace.h new file mode 100644 index 0000000000..f3d0c58563 --- /dev/null +++ b/hw/sd/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_sd.h" diff --git a/hw/sparc/trace.h b/hw/sparc/trace.h new file mode 100644 index 0000000000..625d60ca70 --- /dev/null +++ b/hw/sparc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_sparc.h" diff --git a/hw/sparc64/trace.h b/hw/sparc64/trace.h new file mode 100644 index 0000000000..b6ef6e611d --- /dev/null +++ b/hw/sparc64/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_sparc64.h" diff --git a/hw/ssi/trace.h b/hw/ssi/trace.h new file mode 100644 index 0000000000..0c1de2679e --- /dev/null +++ b/hw/ssi/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_ssi.h" diff --git a/hw/timer/trace.h b/hw/timer/trace.h new file mode 100644 index 0000000000..5f72c441b0 --- /dev/null +++ b/hw/timer/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_timer.h" diff --git a/hw/tpm/trace.h b/hw/tpm/trace.h new file mode 100644 index 0000000000..9827c128aa --- /dev/null +++ b/hw/tpm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_tpm.h" diff --git a/hw/usb/trace.h b/hw/usb/trace.h new file mode 100644 index 0000000000..f3962f2baf --- /dev/null +++ b/hw/usb/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_usb.h" diff --git a/hw/vfio/trace.h b/hw/vfio/trace.h new file mode 100644 index 0000000000..5a343aa59c --- /dev/null +++ b/hw/vfio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_vfio.h" diff --git a/hw/virtio/trace.h b/hw/virtio/trace.h new file mode 100644 index 0000000000..5d7097061b --- /dev/null +++ b/hw/virtio/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_virtio.h" diff --git a/hw/watchdog/trace.h b/hw/watchdog/trace.h new file mode 100644 index 0000000000..5d8495752b --- /dev/null +++ b/hw/watchdog/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_watchdog.h" diff --git a/hw/xen/trace.h b/hw/xen/trace.h new file mode 100644 index 0000000000..adba31a136 --- /dev/null +++ b/hw/xen/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_xen.h" diff --git a/include/user/syscall-trace.h b/include/user/syscall-trace.h index 79fd3e5aa9..42e3b48b03 100644 --- a/include/user/syscall-trace.h +++ b/include/user/syscall-trace.h @@ -10,7 +10,7 @@ #ifndef _SYSCALL_TRACE_H_ #define _SYSCALL_TRACE_H_ -#include "trace-root.h" +#include "trace/trace-root.h" /* * These helpers just provide a common place for the various diff --git a/io/trace.h b/io/trace.h new file mode 100644 index 0000000000..92d63a5bfc --- /dev/null +++ b/io/trace.h @@ -0,0 +1 @@ +#include "trace/trace-io.h" diff --git a/job-qmp.c b/job-qmp.c index f9a58832e1..645601b2cc 100644 --- a/job-qmp.c +++ b/job-qmp.c @@ -27,7 +27,7 @@ #include "qemu/job.h" #include "qapi/qapi-commands-job.h" #include "qapi/error.h" -#include "trace-root.h" +#include "trace/trace-root.h" /* Get a job using its ID and acquire its AioContext */ static Job *find_job(const char *id, AioContext **aio_context, Error **errp) diff --git a/job.c b/job.c index 53be57a3a0..8fecf38960 100644 --- a/job.c +++ b/job.c @@ -29,7 +29,7 @@ #include "qemu/id.h" #include "qemu/main-loop.h" #include "block/aio-wait.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "qapi/qapi-events-job.h" static QLIST_HEAD(, Job) jobs = QLIST_HEAD_INITIALIZER(jobs); diff --git a/linux-user/trace.h b/linux-user/trace.h new file mode 100644 index 0000000000..05518e4694 --- /dev/null +++ b/linux-user/trace.h @@ -0,0 +1 @@ +#include "trace/trace-linux_user.h" diff --git a/migration/trace.h b/migration/trace.h new file mode 100644 index 0000000000..e1a0f4fb74 --- /dev/null +++ b/migration/trace.h @@ -0,0 +1 @@ +#include "trace/trace-migration.h" diff --git a/monitor/trace.h b/monitor/trace.h new file mode 100644 index 0000000000..f216e31be5 --- /dev/null +++ b/monitor/trace.h @@ -0,0 +1 @@ +#include "trace/trace-monitor.h" diff --git a/nbd/trace.h b/nbd/trace.h new file mode 100644 index 0000000000..233d08fdd1 --- /dev/null +++ b/nbd/trace.h @@ -0,0 +1 @@ +#include "trace/trace-nbd.h" diff --git a/net/trace.h b/net/trace.h new file mode 100644 index 0000000000..18d42c29b6 --- /dev/null +++ b/net/trace.h @@ -0,0 +1 @@ +#include "trace/trace-net.h" diff --git a/qapi/trace.h b/qapi/trace.h new file mode 100644 index 0000000000..5c3fb674d8 --- /dev/null +++ b/qapi/trace.h @@ -0,0 +1 @@ +#include "trace/trace-qapi.h" diff --git a/qom/trace.h b/qom/trace.h new file mode 100644 index 0000000000..f2895e699b --- /dev/null +++ b/qom/trace.h @@ -0,0 +1 @@ +#include "trace/trace-qom.h" diff --git a/scripts/tracetool/format/c.py b/scripts/tracetool/format/c.py index 23d82ea861..c390c1844a 100644 --- a/scripts/tracetool/format/c.py +++ b/scripts/tracetool/format/c.py @@ -19,10 +19,7 @@ def generate(events, backend, group): active_events = [e for e in events if "disable" not in e.properties] - if group == "root": - header = "trace-root.h" - else: - header = "trace.h" + header = "trace-" + group + ".h" out('/* This file is autogenerated by tracetool, do not edit. */', '', diff --git a/scripts/tracetool/format/tcg_h.py b/scripts/tracetool/format/tcg_h.py index 33cf6a31b3..4d84440aff 100644 --- a/scripts/tracetool/format/tcg_h.py +++ b/scripts/tracetool/format/tcg_h.py @@ -28,7 +28,7 @@ def vcpu_transform_args(args): def generate(events, backend, group): if group == "root": - header = "trace-root.h" + header = "trace/trace-root.h" else: header = "trace.h" diff --git a/scripts/tracetool/format/tcg_helper_c.py b/scripts/tracetool/format/tcg_helper_c.py index 2db6317f3c..72576e67d1 100644 --- a/scripts/tracetool/format/tcg_helper_c.py +++ b/scripts/tracetool/format/tcg_helper_c.py @@ -41,7 +41,7 @@ def vcpu_transform_args(args, mode): def generate(events, backend, group): if group == "root": - header = "trace-root.h" + header = "trace/trace-root.h" else: header = "trace.h" diff --git a/scsi/trace.h b/scsi/trace.h new file mode 100644 index 0000000000..3e4d89a3a5 --- /dev/null +++ b/scsi/trace.h @@ -0,0 +1 @@ +#include "trace/trace-scsi.h" diff --git a/softmmu/balloon.c b/softmmu/balloon.c index 354408c6ea..b89646f85d 100644 --- a/softmmu/balloon.c +++ b/softmmu/balloon.c @@ -28,7 +28,7 @@ #include "qemu/atomic.h" #include "sysemu/kvm.h" #include "sysemu/balloon.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "qapi/error.h" #include "qapi/qapi-commands-misc.h" #include "qapi/qmp/qerror.h" diff --git a/softmmu/ioport.c b/softmmu/ioport.c index 04e360e79a..a799697c5d 100644 --- a/softmmu/ioport.c +++ b/softmmu/ioport.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/ioport.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "exec/memory.h" #include "exec/address-spaces.h" diff --git a/softmmu/memory.c b/softmmu/memory.c index af25987518..70b93104e8 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -24,7 +24,7 @@ #include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "qom/object.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "exec/memory-internal.h" #include "exec/ram_addr.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 4eb9d1f7fd..0cc86b0766 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -90,7 +90,7 @@ #include "disas/disas.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "trace/control.h" #include "qemu/plugin.h" #include "qemu/queue.h" diff --git a/target/arm/trace.h b/target/arm/trace.h new file mode 100644 index 0000000000..60372d8e26 --- /dev/null +++ b/target/arm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_arm.h" diff --git a/target/hppa/trace.h b/target/hppa/trace.h new file mode 100644 index 0000000000..810cc09692 --- /dev/null +++ b/target/hppa/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_hppa.h" diff --git a/target/i386/trace.h b/target/i386/trace.h new file mode 100644 index 0000000000..781e8ec55c --- /dev/null +++ b/target/i386/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386.h" diff --git a/target/mips/trace.h b/target/mips/trace.h new file mode 100644 index 0000000000..f25b88ca6f --- /dev/null +++ b/target/mips/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_mips.h" diff --git a/target/ppc/trace.h b/target/ppc/trace.h new file mode 100644 index 0000000000..a9e8962828 --- /dev/null +++ b/target/ppc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_ppc.h" diff --git a/target/riscv/trace.h b/target/riscv/trace.h new file mode 100644 index 0000000000..03a89fcd9b --- /dev/null +++ b/target/riscv/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_riscv.h" diff --git a/target/s390x/trace.h b/target/s390x/trace.h new file mode 100644 index 0000000000..d7d59d4aba --- /dev/null +++ b/target/s390x/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_s390x.h" diff --git a/target/sparc/trace.h b/target/sparc/trace.h new file mode 100644 index 0000000000..3b2f5a8e29 --- /dev/null +++ b/target/sparc/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_sparc.h" diff --git a/trace/control-target.c b/trace/control-target.c index ceb55c70ce..e293eeed7c 100644 --- a/trace/control-target.c +++ b/trace/control-target.c @@ -9,7 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "trace-root.h" +#include "trace/trace-root.h" #include "trace/control.h" diff --git a/trace/control.c b/trace/control.c index 6558b5c906..c63a4de732 100644 --- a/trace/control.c +++ b/trace/control.c @@ -27,7 +27,7 @@ #include "qemu/error-report.h" #include "qemu/config-file.h" #include "monitor/monitor.h" -#include "trace-root.h" +#include "trace/trace-root.h" int trace_events_enabled_count; diff --git a/ui/trace.h b/ui/trace.h new file mode 100644 index 0000000000..a89d769623 --- /dev/null +++ b/ui/trace.h @@ -0,0 +1 @@ +#include "trace/trace-ui.h" diff --git a/util/trace.h b/util/trace.h new file mode 100644 index 0000000000..86ff7a390c --- /dev/null +++ b/util/trace.h @@ -0,0 +1 @@ +#include "trace/trace-util.h" -- cgit v1.2.3-55-g7522 From 139c1837db7eaee53e1c441629b5bcc159e1deb0 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Feb 2020 12:41:01 +0100 Subject: meson: rename included C source files to .c.inc With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini --- .editorconfig | 3 +- .gitignore | 4 +- Makefile | 36 +- accel/tcg/atomic_common.c.inc | 54 + accel/tcg/atomic_common.inc.c | 54 - accel/tcg/cputlb.c | 2 +- accel/tcg/user-exec.c | 2 +- contrib/gitdm/filetypes.txt | 2 +- exec.c | 4 +- fpu/softfloat-specialize.c.inc | 1083 + fpu/softfloat-specialize.inc.c | 1083 - fpu/softfloat.c | 2 +- include/tcg/tcg.h | 2 +- memory_ldst.c.inc | 529 + memory_ldst.inc.c | 529 - scripts/clean-includes | 2 +- target/arm/Makefile.objs | 40 +- target/arm/translate-neon.c.inc | 4161 ++ target/arm/translate-neon.inc.c | 4161 -- target/arm/translate-sve.c | 2 +- target/arm/translate-vfp.c.inc | 2865 ++ target/arm/translate-vfp.inc.c | 2865 -- target/arm/translate.c | 12 +- target/avr/Makefile.objs | 4 +- target/avr/disas.c | 2 +- target/avr/translate.c | 2 +- target/cris/translate.c | 2 +- target/cris/translate_v10.c.inc | 1312 + target/cris/translate_v10.inc.c | 1312 - target/hppa/Makefile.objs | 4 +- target/hppa/translate.c | 2 +- target/mips/translate.c | 2 +- target/mips/translate_init.c.inc | 1047 + target/mips/translate_init.inc.c | 1047 - target/openrisc/Makefile.objs | 6 +- target/openrisc/disas.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/int_helper.c | 2 +- target/ppc/mfrom_table.c.inc | 78 + target/ppc/mfrom_table.inc.c | 78 - target/ppc/translate.c | 22 +- target/ppc/translate/dfp-impl.c.inc | 232 + target/ppc/translate/dfp-impl.inc.c | 232 - target/ppc/translate/dfp-ops.c.inc | 165 + target/ppc/translate/dfp-ops.inc.c | 165 - target/ppc/translate/fp-impl.c.inc | 1495 + target/ppc/translate/fp-impl.inc.c | 1495 - target/ppc/translate/fp-ops.c.inc | 119 + target/ppc/translate/fp-ops.inc.c | 119 - target/ppc/translate/spe-impl.c.inc | 1221 + target/ppc/translate/spe-impl.inc.c | 1221 - target/ppc/translate/spe-ops.c.inc | 105 + target/ppc/translate/spe-ops.inc.c | 105 - target/ppc/translate/vmx-impl.c.inc | 1571 + target/ppc/translate/vmx-impl.inc.c | 1571 - target/ppc/translate/vmx-ops.c.inc | 301 + target/ppc/translate/vmx-ops.inc.c | 301 - target/ppc/translate/vsx-impl.c.inc | 2055 + target/ppc/translate/vsx-impl.inc.c | 2055 - target/ppc/translate/vsx-ops.c.inc | 401 + target/ppc/translate/vsx-ops.inc.c | 401 - target/ppc/translate_init.c.inc | 10956 +++++ target/ppc/translate_init.inc.c | 10956 ----- target/riscv/Makefile.objs | 8 +- target/riscv/insn_trans/trans_privileged.c.inc | 97 + target/riscv/insn_trans/trans_privileged.inc.c | 97 - target/riscv/insn_trans/trans_rva.c.inc | 224 + target/riscv/insn_trans/trans_rva.inc.c | 224 - target/riscv/insn_trans/trans_rvd.c.inc | 441 + target/riscv/insn_trans/trans_rvd.inc.c | 441 - target/riscv/insn_trans/trans_rvf.c.inc | 451 + target/riscv/insn_trans/trans_rvf.inc.c | 451 - target/riscv/insn_trans/trans_rvh.c.inc | 37 + target/riscv/insn_trans/trans_rvh.inc.c | 37 - target/riscv/insn_trans/trans_rvi.c.inc | 577 + target/riscv/insn_trans/trans_rvi.inc.c | 577 - target/riscv/insn_trans/trans_rvm.c.inc | 120 + target/riscv/insn_trans/trans_rvm.inc.c | 120 - target/riscv/insn_trans/trans_rvv.c.inc | 2902 ++ target/riscv/insn_trans/trans_rvv.inc.c | 2902 -- target/riscv/translate.c | 20 +- target/rx/Makefile.objs | 6 +- target/rx/disas.c | 2 +- target/rx/translate.c | 2 +- target/s390x/translate.c | 2 +- target/s390x/translate_vx.c.inc | 2718 ++ target/s390x/translate_vx.inc.c | 2718 -- target/xtensa/core-dc232b.c | 4 +- target/xtensa/core-dc232b/gdb-config.c.inc | 262 + target/xtensa/core-dc232b/gdb-config.inc.c | 262 - target/xtensa/core-dc232b/xtensa-modules.c.inc | 14078 ++++++ target/xtensa/core-dc232b/xtensa-modules.inc.c | 14078 ------ target/xtensa/core-dc233c.c | 4 +- target/xtensa/core-dc233c/gdb-config.c.inc | 146 + target/xtensa/core-dc233c/gdb-config.inc.c | 146 - target/xtensa/core-dc233c/xtensa-modules.c.inc | 15205 +++++++ target/xtensa/core-dc233c/xtensa-modules.inc.c | 15205 ------- target/xtensa/core-de212.c | 4 +- target/xtensa/core-de212/gdb-config.c.inc | 198 + target/xtensa/core-de212/gdb-config.inc.c | 198 - target/xtensa/core-de212/xtensa-modules.c.inc | 14543 ++++++ target/xtensa/core-de212/xtensa-modules.inc.c | 14543 ------ target/xtensa/core-fsf.c | 2 +- target/xtensa/core-fsf/xtensa-modules.c.inc | 9826 ++++ target/xtensa/core-fsf/xtensa-modules.inc.c | 9826 ---- target/xtensa/core-sample_controller.c | 4 +- .../xtensa/core-sample_controller/gdb-config.c.inc | 141 + .../xtensa/core-sample_controller/gdb-config.inc.c | 141 - .../core-sample_controller/xtensa-modules.c.inc | 11366 +++++ .../core-sample_controller/xtensa-modules.inc.c | 11366 ----- target/xtensa/core-test_kc705_be.c | 4 +- target/xtensa/core-test_kc705_be/gdb-config.c.inc | 259 + target/xtensa/core-test_kc705_be/gdb-config.inc.c | 259 - .../xtensa/core-test_kc705_be/xtensa-modules.c.inc | 45117 +++++++++++++++++++ .../xtensa/core-test_kc705_be/xtensa-modules.inc.c | 45117 ------------------- target/xtensa/core-test_mmuhifi_c3.c | 4 +- .../xtensa/core-test_mmuhifi_c3/gdb-config.c.inc | 220 + .../xtensa/core-test_mmuhifi_c3/gdb-config.inc.c | 220 - .../core-test_mmuhifi_c3/xtensa-modules.c.inc | 36387 +++++++++++++++ .../core-test_mmuhifi_c3/xtensa-modules.inc.c | 36387 --------------- target/xtensa/import_core.sh | 8 +- tcg/README | 2 +- tcg/aarch64/tcg-target.c.inc | 2973 ++ tcg/aarch64/tcg-target.inc.c | 2973 -- tcg/arm/tcg-target.c.inc | 2362 + tcg/arm/tcg-target.inc.c | 2362 - tcg/i386/tcg-target.c.inc | 4016 ++ tcg/i386/tcg-target.inc.c | 4016 -- tcg/mips/tcg-target.c.inc | 2711 ++ tcg/mips/tcg-target.inc.c | 2711 -- tcg/ppc/tcg-target.c.inc | 3884 ++ tcg/ppc/tcg-target.inc.c | 3884 -- tcg/riscv/tcg-target.c.inc | 1915 + tcg/riscv/tcg-target.inc.c | 1915 - tcg/s390/tcg-target.c.inc | 2630 ++ tcg/s390/tcg-target.inc.c | 2630 -- tcg/sparc/tcg-target.c.inc | 1868 + tcg/sparc/tcg-target.inc.c | 1868 - tcg/tcg-ldst.c.inc | 78 + tcg/tcg-ldst.inc.c | 78 - tcg/tcg-pool.c.inc | 158 + tcg/tcg-pool.inc.c | 158 - tcg/tcg.c | 6 +- tcg/tci/README | 4 +- tcg/tci/tcg-target.c.inc | 896 + tcg/tci/tcg-target.inc.c | 896 - tests/fp/fp-test.c | 2 +- tests/fp/wrap.c.inc | 654 + tests/fp/wrap.inc.c | 654 - ui/input-keymap.c | 34 +- ui/vnc-enc-zrle.c | 22 +- ui/vnc-enc-zrle.c.inc | 263 + ui/vnc-enc-zrle.inc.c | 263 - 153 files changed, 209628 insertions(+), 209627 deletions(-) create mode 100644 accel/tcg/atomic_common.c.inc delete mode 100644 accel/tcg/atomic_common.inc.c create mode 100644 fpu/softfloat-specialize.c.inc delete mode 100644 fpu/softfloat-specialize.inc.c create mode 100644 memory_ldst.c.inc delete mode 100644 memory_ldst.inc.c create mode 100644 target/arm/translate-neon.c.inc delete mode 100644 target/arm/translate-neon.inc.c create mode 100644 target/arm/translate-vfp.c.inc delete mode 100644 target/arm/translate-vfp.inc.c create mode 100644 target/cris/translate_v10.c.inc delete mode 100644 target/cris/translate_v10.inc.c create mode 100644 target/mips/translate_init.c.inc delete mode 100644 target/mips/translate_init.inc.c create mode 100644 target/ppc/mfrom_table.c.inc delete mode 100644 target/ppc/mfrom_table.inc.c create mode 100644 target/ppc/translate/dfp-impl.c.inc delete mode 100644 target/ppc/translate/dfp-impl.inc.c create mode 100644 target/ppc/translate/dfp-ops.c.inc delete mode 100644 target/ppc/translate/dfp-ops.inc.c create mode 100644 target/ppc/translate/fp-impl.c.inc delete mode 100644 target/ppc/translate/fp-impl.inc.c create mode 100644 target/ppc/translate/fp-ops.c.inc delete mode 100644 target/ppc/translate/fp-ops.inc.c create mode 100644 target/ppc/translate/spe-impl.c.inc delete mode 100644 target/ppc/translate/spe-impl.inc.c create mode 100644 target/ppc/translate/spe-ops.c.inc delete mode 100644 target/ppc/translate/spe-ops.inc.c create mode 100644 target/ppc/translate/vmx-impl.c.inc delete mode 100644 target/ppc/translate/vmx-impl.inc.c create mode 100644 target/ppc/translate/vmx-ops.c.inc delete mode 100644 target/ppc/translate/vmx-ops.inc.c create mode 100644 target/ppc/translate/vsx-impl.c.inc delete mode 100644 target/ppc/translate/vsx-impl.inc.c create mode 100644 target/ppc/translate/vsx-ops.c.inc delete mode 100644 target/ppc/translate/vsx-ops.inc.c create mode 100644 target/ppc/translate_init.c.inc delete mode 100644 target/ppc/translate_init.inc.c create mode 100644 target/riscv/insn_trans/trans_privileged.c.inc delete mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.c.inc delete mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvh.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvh.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvm.inc.c create mode 100644 target/riscv/insn_trans/trans_rvv.c.inc delete mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/s390x/translate_vx.c.inc delete mode 100644 target/s390x/translate_vx.inc.c create mode 100644 target/xtensa/core-dc232b/gdb-config.c.inc delete mode 100644 target/xtensa/core-dc232b/gdb-config.inc.c create mode 100644 target/xtensa/core-dc232b/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-dc232b/xtensa-modules.inc.c create mode 100644 target/xtensa/core-dc233c/gdb-config.c.inc delete mode 100644 target/xtensa/core-dc233c/gdb-config.inc.c create mode 100644 target/xtensa/core-dc233c/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-dc233c/xtensa-modules.inc.c create mode 100644 target/xtensa/core-de212/gdb-config.c.inc delete mode 100644 target/xtensa/core-de212/gdb-config.inc.c create mode 100644 target/xtensa/core-de212/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-de212/xtensa-modules.inc.c create mode 100644 target/xtensa/core-fsf/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-fsf/xtensa-modules.inc.c create mode 100644 target/xtensa/core-sample_controller/gdb-config.c.inc delete mode 100644 target/xtensa/core-sample_controller/gdb-config.inc.c create mode 100644 target/xtensa/core-sample_controller/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-sample_controller/xtensa-modules.inc.c create mode 100644 target/xtensa/core-test_kc705_be/gdb-config.c.inc delete mode 100644 target/xtensa/core-test_kc705_be/gdb-config.inc.c create mode 100644 target/xtensa/core-test_kc705_be/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-test_kc705_be/xtensa-modules.inc.c create mode 100644 target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc delete mode 100644 target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c create mode 100644 target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc delete mode 100644 target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c create mode 100644 tcg/aarch64/tcg-target.c.inc delete mode 100644 tcg/aarch64/tcg-target.inc.c create mode 100644 tcg/arm/tcg-target.c.inc delete mode 100644 tcg/arm/tcg-target.inc.c create mode 100644 tcg/i386/tcg-target.c.inc delete mode 100644 tcg/i386/tcg-target.inc.c create mode 100644 tcg/mips/tcg-target.c.inc delete mode 100644 tcg/mips/tcg-target.inc.c create mode 100644 tcg/ppc/tcg-target.c.inc delete mode 100644 tcg/ppc/tcg-target.inc.c create mode 100644 tcg/riscv/tcg-target.c.inc delete mode 100644 tcg/riscv/tcg-target.inc.c create mode 100644 tcg/s390/tcg-target.c.inc delete mode 100644 tcg/s390/tcg-target.inc.c create mode 100644 tcg/sparc/tcg-target.c.inc delete mode 100644 tcg/sparc/tcg-target.inc.c create mode 100644 tcg/tcg-ldst.c.inc delete mode 100644 tcg/tcg-ldst.inc.c create mode 100644 tcg/tcg-pool.c.inc delete mode 100644 tcg/tcg-pool.inc.c create mode 100644 tcg/tci/tcg-target.c.inc delete mode 100644 tcg/tci/tcg-target.inc.c create mode 100644 tests/fp/wrap.c.inc delete mode 100644 tests/fp/wrap.inc.c create mode 100644 ui/vnc-enc-zrle.c.inc delete mode 100644 ui/vnc-enc-zrle.inc.c diff --git a/.editorconfig b/.editorconfig index a001f340bd..22681d91c6 100644 --- a/.editorconfig +++ b/.editorconfig @@ -22,9 +22,10 @@ indent_style = tab indent_size = 8 file_type_emacs = makefile -[*.{c,h}] +[*.{c,h,c.inc,h.inc}] indent_style = space indent_size = 4 +file_type_emacs = c [*.sh] indent_style = space diff --git a/.gitignore b/.gitignore index 656e39050b..f8b3cd6fd5 100644 --- a/.gitignore +++ b/.gitignore @@ -18,7 +18,7 @@ /ui/shader/texture-blit-frag.h /ui/shader/texture-blit-vert.h /ui/shader/texture-blit-flip-vert.h -/ui/input-keymap-*.c +/ui/input-keymap-*.c.inc *-timestamp /*-softmmu /*-darwin-user @@ -161,4 +161,4 @@ trace-dtrace-root.h trace-dtrace-root.dtrace trace-ust-all.h trace-ust-all.c -/target/arm/decode-sve.inc.c +/target/arm/decode-sve.c.inc diff --git a/Makefile b/Makefile index 00cadebf99..5596482dbd 100644 --- a/Makefile +++ b/Makefile @@ -289,28 +289,28 @@ KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv KEYCODEMAP_FILES = \ - ui/input-keymap-atset1-to-qcode.c \ - ui/input-keymap-linux-to-qcode.c \ - ui/input-keymap-qcode-to-atset1.c \ - ui/input-keymap-qcode-to-atset2.c \ - ui/input-keymap-qcode-to-atset3.c \ - ui/input-keymap-qcode-to-linux.c \ - ui/input-keymap-qcode-to-qnum.c \ - ui/input-keymap-qcode-to-sun.c \ - ui/input-keymap-qnum-to-qcode.c \ - ui/input-keymap-usb-to-qcode.c \ - ui/input-keymap-win32-to-qcode.c \ - ui/input-keymap-x11-to-qcode.c \ - ui/input-keymap-xorgevdev-to-qcode.c \ - ui/input-keymap-xorgkbd-to-qcode.c \ - ui/input-keymap-xorgxquartz-to-qcode.c \ - ui/input-keymap-xorgxwin-to-qcode.c \ - ui/input-keymap-osx-to-qcode.c \ + ui/input-keymap-atset1-to-qcode.c.inc \ + ui/input-keymap-linux-to-qcode.c.inc \ + ui/input-keymap-qcode-to-atset1.c.inc \ + ui/input-keymap-qcode-to-atset2.c.inc \ + ui/input-keymap-qcode-to-atset3.c.inc \ + ui/input-keymap-qcode-to-linux.c.inc \ + ui/input-keymap-qcode-to-qnum.c.inc \ + ui/input-keymap-qcode-to-sun.c.inc \ + ui/input-keymap-qnum-to-qcode.c.inc \ + ui/input-keymap-usb-to-qcode.c.inc \ + ui/input-keymap-win32-to-qcode.c.inc \ + ui/input-keymap-x11-to-qcode.c.inc \ + ui/input-keymap-xorgevdev-to-qcode.c.inc \ + ui/input-keymap-xorgkbd-to-qcode.c.inc \ + ui/input-keymap-xorgxquartz-to-qcode.c.inc \ + ui/input-keymap-xorgxwin-to-qcode.c.inc \ + ui/input-keymap-osx-to-qcode.c.inc \ $(NULL) generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES) -ui/input-keymap-%.c: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs +ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs $(call quiet-command,\ stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \ test -e $(KEYCODEMAP_GEN) && \ diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc new file mode 100644 index 0000000000..344525b0bb --- /dev/null +++ b/accel/tcg/atomic_common.c.inc @@ -0,0 +1,54 @@ +/* + * Common Atomic Helper Functions + * + * This file should be included before the various instantiations of + * the atomic_template.h helpers. + * + * Copyright (c) 2019 Linaro + * Written by Alex Bennée + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +static inline +void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info) +{ + CPUState *cpu = env_cpu(env); + + trace_guest_mem_before_exec(cpu, addr, info); + trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); +} + +static inline void +atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info) +{ + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST); +} + +static inline +void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info) +{ + trace_guest_mem_before_exec(env_cpu(env), addr, info); +} + +static inline +void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info) +{ + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); +} + +static inline +void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info) +{ + trace_guest_mem_before_exec(env_cpu(env), addr, info); +} + +static inline +void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info) +{ + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); +} diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.inc.c deleted file mode 100644 index 344525b0bb..0000000000 --- a/accel/tcg/atomic_common.inc.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Common Atomic Helper Functions - * - * This file should be included before the various instantiations of - * the atomic_template.h helpers. - * - * Copyright (c) 2019 Linaro - * Written by Alex Bennée - * - * SPDX-License-Identifier: GPL-2.0-or-later - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -static inline -void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info) -{ - CPUState *cpu = env_cpu(env); - - trace_guest_mem_before_exec(cpu, addr, info); - trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); -} - -static inline void -atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST); -} - -static inline -void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info) -{ - trace_guest_mem_before_exec(env_cpu(env), addr, info); -} - -static inline -void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); -} - -static inline -void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info) -{ - trace_guest_mem_before_exec(env_cpu(env), addr, info); -} - -static inline -void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); -} diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5349ee6b0e..2d48281942 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2354,7 +2354,7 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val) #define ATOMIC_MMU_CLEANUP #define ATOMIC_MMU_IDX get_mmuidx(oi) -#include "atomic_common.inc.c" +#include "atomic_common.c.inc" #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1d34c57ff5..bb039eb32d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1189,7 +1189,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define EXTRA_ARGS -#include "atomic_common.inc.c" +#include "atomic_common.c.inc" #define DATA_SIZE 1 #include "atomic_template.h" diff --git a/contrib/gitdm/filetypes.txt b/contrib/gitdm/filetypes.txt index 2d5002fea0..9e9c505205 100644 --- a/contrib/gitdm/filetypes.txt +++ b/contrib/gitdm/filetypes.txt @@ -42,7 +42,7 @@ order build,interface,tests,code,documentation,devel-doc,blobs # (most common languages first # filetype code \.c$ # C -filetype code \.inc.c$ # C +filetype code \.c.inc$ # C filetype code \.C$ # C++ filetype code \.cpp$ # C++ filetype code \.c\+\+$ # C++ diff --git a/exec.c b/exec.c index 8047bf2ff9..7683afb6a8 100644 --- a/exec.c +++ b/exec.c @@ -3659,7 +3659,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len, #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) #define RCU_READ_LOCK(...) rcu_read_lock() #define RCU_READ_UNLOCK(...) rcu_read_unlock() -#include "memory_ldst.inc.c" +#include "memory_ldst.c.inc" int64_t address_space_cache_init(MemoryRegionCache *cache, AddressSpace *as, @@ -3795,7 +3795,7 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) #define RCU_READ_LOCK() ((void)0) #define RCU_READ_UNLOCK() ((void)0) -#include "memory_ldst.inc.c" +#include "memory_ldst.c.inc" /* virtual memory access for debug (includes writing to ROM) */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc new file mode 100644 index 0000000000..034d18199c --- /dev/null +++ b/fpu/softfloat-specialize.c.inc @@ -0,0 +1,1083 @@ +/* + * QEMU float support + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +/* +=============================================================================== +This C source fragment is part of the SoftFloat IEC/IEEE Floating-point +Arithmetic Package, Release 2a. + +Written by John R. Hauser. This work was made possible in part by the +International Computer Science Institute, located at Suite 600, 1947 Center +Street, Berkeley, California 94704. Funding was partially provided by the +National Science Foundation under grant MIP-9311980. The original version +of this code was written as part of a project to build a fixed-point vector +processor in collaboration with the University of California at Berkeley, +overseen by Profs. Nelson Morgan and John Wawrzynek. More information +is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ +arithmetic/SoftFloat.html'. + +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort +has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT +TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO +PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY +AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. + +Derivative works are acceptable, even for commercial purposes, so long as +(1) they include prominent notice that the work is derivative, and (2) they +include prominent notice akin to these four paragraphs for those parts of +this code that are retained. + +=============================================================================== +*/ + +/* BSD licensing: + * Copyright (c) 2006, Fabrice Bellard + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Portions of this work are licensed under the terms of the GNU GPL, + * version 2 or later. See the COPYING file in the top-level directory. + */ + +/* Define for architectures which deviate from IEEE in not supporting + * signaling NaNs (so all NaNs are treated as quiet). + */ +#if defined(TARGET_XTENSA) +#define NO_SIGNALING_NANS 1 +#endif + +/* Define how the architecture discriminates signaling NaNs. + * This done with the most significant bit of the fraction. + * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 + * the msb must be zero. MIPS is (so far) unique in supporting both the + * 2008 revision and backward compatibility with their original choice. + * Thus for MIPS we must make the choice at runtime. + */ +static inline bool snan_bit_is_one(float_status *status) +{ +#if defined(TARGET_MIPS) + return status->snan_bit_is_one; +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) + return 1; +#else + return 0; +#endif +} + +/*---------------------------------------------------------------------------- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*----------------------------------------------------------------------------*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == snan_bit_is_one(status); +#endif +} + +/*---------------------------------------------------------------------------- +| The pattern for a default generated deconstructed floating-point NaN. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign = 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + /* !snan_bit_is_one, set all bits */ + frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + || defined(TARGET_MICROBLAZE) + /* !snan_bit_is_one, set sign and msb */ + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; +#elif defined(TARGET_HPPA) + /* snan_bit_is_one, set msb-1. */ + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. I cannot find documentation + * for Unicore32; the choice from the original commit is unchanged. + * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, + * do not have floating-point. + */ + if (snan_bit_is_one(status)) { + /* set all bits other than msb */ + frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { + /* set msb */ + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + + return (FloatParts) { + .cls = float_class_qnan, + .sign = sign, + .exp = INT_MAX, + .frac = frac + }; +} + +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (snan_bit_is_one(status)) { + return parts_default_nan(status); + } else { + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls = float_class_qnan; + return a; +} + +/*---------------------------------------------------------------------------- +| The pattern for a default generated extended double-precision NaN. +*----------------------------------------------------------------------------*/ +floatx80 floatx80_default_nan(float_status *status) +{ + floatx80 r; + + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); +#if defined(TARGET_M68K) + r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); + r.high = 0x7FFF; +#else + /* X86 */ + r.low = UINT64_C(0xC000000000000000); + r.high = 0xFFFF; +#endif + return r; +} + +/*---------------------------------------------------------------------------- +| The pattern for a default generated extended double-precision inf. +*----------------------------------------------------------------------------*/ + +#define floatx80_infinity_high 0x7FFF +#if defined(TARGET_M68K) +#define floatx80_infinity_low UINT64_C(0x0000000000000000) +#else +#define floatx80_infinity_low UINT64_C(0x8000000000000000) +#endif + +const floatx80 floatx80_infinity + = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); + +/*---------------------------------------------------------------------------- +| Raises the exceptions specified by `flags'. Floating-point traps can be +| defined here if desired. It is currently not possible for such a trap +| to substitute a result value. If traps are not implemented, this routine +| should be simply `float_exception_flags |= flags;'. +*----------------------------------------------------------------------------*/ + +void float_raise(uint8_t flags, float_status *status) +{ + status->float_exception_flags |= flags; +} + +/*---------------------------------------------------------------------------- +| Internal canonical NaN format. +*----------------------------------------------------------------------------*/ +typedef struct { + bool sign; + uint64_t high, low; +} commonNaNT; + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float16_is_quiet_nan(float16 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else + uint16_t a = float16_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + } else { + return ((a >> 9) & 0x3F) == 0x3F; + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is a signaling +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float16_is_signaling_nan(float16 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return 0; +#else + uint16_t a = float16_val(a_); + if (snan_bit_is_one(status)) { + return ((a >> 9) & 0x3F) == 0x3F; + } else { + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the single-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float32_is_quiet_nan(float32 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else + uint32_t a = float32_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + } else { + return ((uint32_t)(a << 1) >= 0xFF800000); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the single-precision floating-point value `a' is a signaling +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float32_is_signaling_nan(float32 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return 0; +#else + uint32_t a = float32_val(a_); + if (snan_bit_is_one(status)) { + return ((uint32_t)(a << 1) >= 0xFF800000); + } else { + return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the single-precision floating-point NaN +| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ + +static commonNaNT float32ToCommonNaN(float32 a, float_status *status) +{ + commonNaNT z; + + if (float32_is_signaling_nan(a, status)) { + float_raise(float_flag_invalid, status); + } + z.sign = float32_val(a) >> 31; + z.low = 0; + z.high = ((uint64_t)float32_val(a)) << 41; + return z; +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the canonical NaN `a' to the single- +| precision floating-point format. +*----------------------------------------------------------------------------*/ + +static float32 commonNaNToFloat32(commonNaNT a, float_status *status) +{ + uint32_t mantissa = a.high >> 41; + + if (status->default_nan_mode) { + return float32_default_nan(status); + } + + if (mantissa) { + return make_float32( + (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); + } else { + return float32_default_nan(status); + } +} + +/*---------------------------------------------------------------------------- +| Select which NaN to propagate for a two-input operation. +| IEEE754 doesn't specify all the details of this, so the +| algorithm is target-specific. +| The routine is passed various bits of information about the +| two NaNs and should return 0 to select NaN a and 1 for NaN b. +| Note that signalling NaNs are always squashed to quiet NaNs +| by the caller, by calling floatXX_silence_nan() before +| returning them. +| +| aIsLargerSignificand is only valid if both a and b are NaNs +| of some kind, and is true if a has the larger significand, +| or if both a and b have the same significand but a is +| positive but b is negative. It is only needed for the x87 +| tie-break rule. +*----------------------------------------------------------------------------*/ + +static int pickNaN(FloatClass a_cls, FloatClass b_cls, + bool aIsLargerSignificand) +{ +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) + /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take + * the first of: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always quietened before returning it. + */ + /* According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always silenced before returning it. + */ + if (is_snan(a_cls)) { + return 0; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_qnan(a_cls)) { + return 0; + } else { + return 1; + } +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) + /* PowerPC propagation rules: + * 1. A if it sNaN or qNaN + * 2. B if it sNaN or qNaN + * A signaling NaN is always silenced before returning it. + */ + /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL + * 3.4 FLOATING-POINT INSTRUCTION DETAILS + * If either operand, but not both operands, of an operation is a + * nonsignaling NaN, then that NaN is returned as the result. If both + * operands are nonsignaling NaNs, then the destination operand + * nonsignaling NaN is returned as the result. + * If either operand to an operation is a signaling NaN (SNaN), then the + * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit + * is set in the FPCR ENABLE byte, then the exception is taken and the + * destination is not modified. If the SNaN exception enable bit is not + * set, setting the SNaN bit in the operand to a one converts the SNaN to + * a nonsignaling NaN. The operation then continues as described in the + * preceding paragraph for nonsignaling NaNs. + */ + if (is_nan(a_cls)) { + return 0; + } else { + return 1; + } +#else + /* This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { + return aIsLargerSignificand ? 0 : 1; + } + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { + return 0; + } else { + return aIsLargerSignificand ? 0 : 1; + } + } else { + return 1; + } +#endif +} + +/*---------------------------------------------------------------------------- +| Select which NaN to propagate for a three-input operation. +| For the moment we assume that no CPU needs the 'larger significand' +| information. +| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN +*----------------------------------------------------------------------------*/ +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, + bool infzero, float_status *status) +{ +#if defined(TARGET_ARM) + /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns + * the default NaN + */ + if (infzero && is_qnan(c_cls)) { + float_raise(float_flag_invalid, status); + return 3; + } + + /* This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. + */ + if (is_snan(c_cls)) { + return 2; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_qnan(c_cls)) { + return 2; + } else if (is_qnan(a_cls)) { + return 0; + } else { + return 1; + } +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + if (infzero) { + float_raise(float_flag_invalid, status); + return 3; + } + /* Prefer sNaN over qNaN, in the a, b, c order. */ + if (is_snan(a_cls)) { + return 0; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_snan(c_cls)) { + return 2; + } else if (is_qnan(a_cls)) { + return 0; + } else if (is_qnan(b_cls)) { + return 1; + } else { + return 2; + } + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + if (infzero) { + float_raise(float_flag_invalid, status); + return 2; + } + /* Prefer sNaN over qNaN, in the c, a, b order. */ + if (is_snan(c_cls)) { + return 2; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_qnan(c_cls)) { + return 2; + } else if (is_qnan(a_cls)) { + return 0; + } else { + return 1; + } + } +#elif defined(TARGET_PPC) + /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + if (infzero) { + float_raise(float_flag_invalid, status); + return 2; + } + + /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + if (is_nan(a_cls)) { + return 0; + } else if (is_nan(c_cls)) { + return 2; + } else { + return 1; + } +#else + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { + return 0; + } else if (is_nan(b_cls)) { + return 1; + } else { + return 2; + } +#endif +} + +/*---------------------------------------------------------------------------- +| Takes two single-precision floating-point values `a' and `b', one of which +| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) +{ + bool aIsLargerSignificand; + uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + av = float32_val(a); + bv = float32_val(b); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return float32_default_nan(status); + } + + if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { + aIsLargerSignificand = 0; + } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (av < bv) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { + return float32_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return float32_silence_nan(a, status); + } + return a; + } +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the double-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float64_is_quiet_nan(float64 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else + uint64_t a = float64_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 51) & 0xFFF) == 0xFFE) + && (a & 0x0007FFFFFFFFFFFFULL); + } else { + return ((a << 1) >= 0xFFF0000000000000ULL); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the double-precision floating-point value `a' is a signaling +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float64_is_signaling_nan(float64 a_, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return 0; +#else + uint64_t a = float64_val(a_); + if (snan_bit_is_one(status)) { + return ((a << 1) >= 0xFFF0000000000000ULL); + } else { + return (((a >> 51) & 0xFFF) == 0xFFE) + && (a & UINT64_C(0x0007FFFFFFFFFFFF)); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the double-precision floating-point NaN +| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ + +static commonNaNT float64ToCommonNaN(float64 a, float_status *status) +{ + commonNaNT z; + + if (float64_is_signaling_nan(a, status)) { + float_raise(float_flag_invalid, status); + } + z.sign = float64_val(a) >> 63; + z.low = 0; + z.high = float64_val(a) << 12; + return z; +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the canonical NaN `a' to the double- +| precision floating-point format. +*----------------------------------------------------------------------------*/ + +static float64 commonNaNToFloat64(commonNaNT a, float_status *status) +{ + uint64_t mantissa = a.high >> 12; + + if (status->default_nan_mode) { + return float64_default_nan(status); + } + + if (mantissa) { + return make_float64( + (((uint64_t) a.sign) << 63) + | UINT64_C(0x7FF0000000000000) + | (a.high >> 12)); + } else { + return float64_default_nan(status); + } +} + +/*---------------------------------------------------------------------------- +| Takes two double-precision floating-point values `a' and `b', one of which +| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) +{ + bool aIsLargerSignificand; + uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + av = float64_val(a); + bv = float64_val(b); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return float64_default_nan(status); + } + + if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { + aIsLargerSignificand = 0; + } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (av < bv) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { + return float64_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return float64_silence_nan(a, status); + } + return a; + } +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the extended double-precision floating-point value `a' is a +| quiet NaN; otherwise returns 0. This slightly differs from the same +| function for other types as floatx80 has an explicit bit. +*----------------------------------------------------------------------------*/ + +int floatx80_is_quiet_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else + if (snan_bit_is_one(status)) { + uint64_t aLow; + + aLow = a.low & ~0x4000000000000000ULL; + return ((a.high & 0x7FFF) == 0x7FFF) + && (aLow << 1) + && (a.low == aLow); + } else { + return ((a.high & 0x7FFF) == 0x7FFF) + && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the extended double-precision floating-point value `a' is a +| signaling NaN; otherwise returns 0. This slightly differs from the same +| function for other types as floatx80 has an explicit bit. +*----------------------------------------------------------------------------*/ + +int floatx80_is_signaling_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return 0; +#else + if (snan_bit_is_one(status)) { + return ((a.high & 0x7FFF) == 0x7FFF) + && ((a.low << 1) >= 0x8000000000000000ULL); + } else { + uint64_t aLow; + + aLow = a.low & ~UINT64_C(0x4000000000000000); + return ((a.high & 0x7FFF) == 0x7FFF) + && (uint64_t)(aLow << 1) + && (a.low == aLow); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the extended double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ + /* None of the targets that have snan_bit_is_one use floatx80. */ + assert(!snan_bit_is_one(status)); + a.low |= UINT64_C(0xC000000000000000); + return a; +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the extended double-precision floating- +| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the +| invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) +{ + floatx80 dflt; + commonNaNT z; + + if (floatx80_is_signaling_nan(a, status)) { + float_raise(float_flag_invalid, status); + } + if (a.low >> 63) { + z.sign = a.high >> 15; + z.low = 0; + z.high = a.low << 1; + } else { + dflt = floatx80_default_nan(status); + z.sign = dflt.high >> 15; + z.low = 0; + z.high = dflt.low << 1; + } + return z; +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the canonical NaN `a' to the extended +| double-precision floating-point format. +*----------------------------------------------------------------------------*/ + +static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) +{ + floatx80 z; + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + if (a.high >> 1) { + z.low = UINT64_C(0x8000000000000000) | a.high >> 1; + z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; + } else { + z = floatx80_default_nan(status); + } + return z; +} + +/*---------------------------------------------------------------------------- +| Takes two extended double-precision floating-point values `a' and `b', one +| of which is a NaN, and returns the appropriate NaN result. If either `a' or +| `b' is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) +{ + bool aIsLargerSignificand; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + if (a.low < b.low) { + aIsLargerSignificand = 0; + } else if (b.low < a.low) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { + return floatx80_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return floatx80_silence_nan(a, status); + } + return a; + } +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the quadruple-precision floating-point value `a' is a quiet +| NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float128_is_quiet_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else + if (snan_bit_is_one(status)) { + return (((a.high >> 47) & 0xFFFF) == 0xFFFE) + && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); + } else { + return ((a.high << 1) >= 0xFFFF000000000000ULL) + && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the quadruple-precision floating-point value `a' is a +| signaling NaN; otherwise returns 0. +*----------------------------------------------------------------------------*/ + +bool float128_is_signaling_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return 0; +#else + if (snan_bit_is_one(status)) { + return ((a.high << 1) >= 0xFFFF000000000000ULL) + && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + } else { + return (((a.high >> 47) & 0xFFFF) == 0xFFFE) + && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (snan_bit_is_one(status)) { + return float128_default_nan(status); + } else { + a.high |= UINT64_C(0x0000800000000000); + return a; + } +#endif +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the quadruple-precision floating-point NaN +| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ + +static commonNaNT float128ToCommonNaN(float128 a, float_status *status) +{ + commonNaNT z; + + if (float128_is_signaling_nan(a, status)) { + float_raise(float_flag_invalid, status); + } + z.sign = a.high >> 63; + shortShift128Left(a.high, a.low, 16, &z.high, &z.low); + return z; +} + +/*---------------------------------------------------------------------------- +| Returns the result of converting the canonical NaN `a' to the quadruple- +| precision floating-point format. +*----------------------------------------------------------------------------*/ + +static float128 commonNaNToFloat128(commonNaNT a, float_status *status) +{ + float128 z; + + if (status->default_nan_mode) { + return float128_default_nan(status); + } + + shift128Right(a.high, a.low, 16, &z.high, &z.low); + z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); + return z; +} + +/*---------------------------------------------------------------------------- +| Takes two quadruple-precision floating-point values `a' and `b', one of +| which is a NaN, and returns the appropriate NaN result. If either `a' or +| `b' is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static float128 propagateFloat128NaN(float128 a, float128 b, + float_status *status) +{ + bool aIsLargerSignificand; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return float128_default_nan(status); + } + + if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { + aIsLargerSignificand = 0; + } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { + return float128_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return float128_silence_nan(a, status); + } + return a; + } +} diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c deleted file mode 100644 index 034d18199c..0000000000 --- a/fpu/softfloat-specialize.inc.c +++ /dev/null @@ -1,1083 +0,0 @@ -/* - * QEMU float support - * - * The code in this source file is derived from release 2a of the SoftFloat - * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and - * some later contributions) are provided under that license, as detailed below. - * It has subsequently been modified by contributors to the QEMU Project, - * so some portions are provided under: - * the SoftFloat-2a license - * the BSD license - * GPL-v2-or-later - * - * Any future contributions to this file after December 1st 2014 will be - * taken to be licensed under the Softfloat-2a license unless specifically - * indicated otherwise. - */ - -/* -=============================================================================== -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point -Arithmetic Package, Release 2a. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort -has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT -TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO -PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY -AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) they include prominent notice that the work is derivative, and (2) they -include prominent notice akin to these four paragraphs for those parts of -this code that are retained. - -=============================================================================== -*/ - -/* BSD licensing: - * Copyright (c) 2006, Fabrice Bellard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Portions of this work are licensed under the terms of the GNU GPL, - * version 2 or later. See the COPYING file in the top-level directory. - */ - -/* Define for architectures which deviate from IEEE in not supporting - * signaling NaNs (so all NaNs are treated as quiet). - */ -#if defined(TARGET_XTENSA) -#define NO_SIGNALING_NANS 1 -#endif - -/* Define how the architecture discriminates signaling NaNs. - * This done with the most significant bit of the fraction. - * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 - * the msb must be zero. MIPS is (so far) unique in supporting both the - * 2008 revision and backward compatibility with their original choice. - * Thus for MIPS we must make the choice at runtime. - */ -static inline bool snan_bit_is_one(float_status *status) -{ -#if defined(TARGET_MIPS) - return status->snan_bit_is_one; -#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) - return 1; -#else - return 0; -#endif -} - -/*---------------------------------------------------------------------------- -| For the deconstructed floating-point with fraction FRAC, return true -| if the fraction represents a signalling NaN; otherwise false. -*----------------------------------------------------------------------------*/ - -static bool parts_is_snan_frac(uint64_t frac, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return false; -#else - bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb == snan_bit_is_one(status); -#endif -} - -/*---------------------------------------------------------------------------- -| The pattern for a default generated deconstructed floating-point NaN. -*----------------------------------------------------------------------------*/ - -static FloatParts parts_default_nan(float_status *status) -{ - bool sign = 0; - uint64_t frac; - -#if defined(TARGET_SPARC) || defined(TARGET_M68K) - /* !snan_bit_is_one, set all bits */ - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ - || defined(TARGET_MICROBLAZE) - /* !snan_bit_is_one, set sign and msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; -#elif defined(TARGET_HPPA) - /* snan_bit_is_one, set msb-1. */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); -#else - /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. I cannot find documentation - * for Unicore32; the choice from the original commit is unchanged. - * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* set all bits other than msb */ - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; - } else { - /* set msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } -#endif - - return (FloatParts) { - .cls = float_class_qnan, - .sign = sign, - .exp = INT_MAX, - .frac = frac - }; -} - -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the deconstructed -| floating-point parts. -*----------------------------------------------------------------------------*/ - -static FloatParts parts_silence_nan(FloatParts a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#elif defined(TARGET_HPPA) - a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); - a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); -#else - if (snan_bit_is_one(status)) { - return parts_default_nan(status); - } else { - a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } -#endif - a.cls = float_class_qnan; - return a; -} - -/*---------------------------------------------------------------------------- -| The pattern for a default generated extended double-precision NaN. -*----------------------------------------------------------------------------*/ -floatx80 floatx80_default_nan(float_status *status) -{ - floatx80 r; - - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); -#if defined(TARGET_M68K) - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); - r.high = 0x7FFF; -#else - /* X86 */ - r.low = UINT64_C(0xC000000000000000); - r.high = 0xFFFF; -#endif - return r; -} - -/*---------------------------------------------------------------------------- -| The pattern for a default generated extended double-precision inf. -*----------------------------------------------------------------------------*/ - -#define floatx80_infinity_high 0x7FFF -#if defined(TARGET_M68K) -#define floatx80_infinity_low UINT64_C(0x0000000000000000) -#else -#define floatx80_infinity_low UINT64_C(0x8000000000000000) -#endif - -const floatx80 floatx80_infinity - = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); - -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `float_exception_flags |= flags;'. -*----------------------------------------------------------------------------*/ - -void float_raise(uint8_t flags, float_status *status) -{ - status->float_exception_flags |= flags; -} - -/*---------------------------------------------------------------------------- -| Internal canonical NaN format. -*----------------------------------------------------------------------------*/ -typedef struct { - bool sign; - uint64_t high, low; -} commonNaNT; - -/*---------------------------------------------------------------------------- -| Returns 1 if the half-precision floating-point value `a' is a quiet -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float16_is_quiet_nan(float16 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return float16_is_any_nan(a_); -#else - uint16_t a = float16_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); - } else { - return ((a >> 9) & 0x3F) == 0x3F; - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the half-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float16_is_signaling_nan(float16 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint16_t a = float16_val(a_); - if (snan_bit_is_one(status)) { - return ((a >> 9) & 0x3F) == 0x3F; - } else { - return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a quiet -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float32_is_quiet_nan(float32 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return float32_is_any_nan(a_); -#else - uint32_t a = float32_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); - } else { - return ((uint32_t)(a << 1) >= 0xFF800000); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float32_is_signaling_nan(float32 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint32_t a = float32_val(a_); - if (snan_bit_is_one(status)) { - return ((uint32_t)(a << 1) >= 0xFF800000); - } else { - return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float32ToCommonNaN(float32 a, float_status *status) -{ - commonNaNT z; - - if (float32_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float32_val(a) >> 31; - z.low = 0; - z.high = ((uint64_t)float32_val(a)) << 41; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the single- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float32 commonNaNToFloat32(commonNaNT a, float_status *status) -{ - uint32_t mantissa = a.high >> 41; - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if (mantissa) { - return make_float32( - (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); - } else { - return float32_default_nan(status); - } -} - -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a two-input operation. -| IEEE754 doesn't specify all the details of this, so the -| algorithm is target-specific. -| The routine is passed various bits of information about the -| two NaNs and should return 0 to select NaN a and 1 for NaN b. -| Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_silence_nan() before -| returning them. -| -| aIsLargerSignificand is only valid if both a and b are NaNs -| of some kind, and is true if a has the larger significand, -| or if both a and b have the same significand but a is -| positive but b is negative. It is only needed for the x87 -| tie-break rule. -*----------------------------------------------------------------------------*/ - -static int pickNaN(FloatClass a_cls, FloatClass b_cls, - bool aIsLargerSignificand) -{ -#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) - /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take - * the first of: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always quietened before returning it. - */ - /* According to MIPS specifications, if one of the two operands is - * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_silence_nan(). For qNaN inputs the specifications - * says: "When possible, this QNaN result is one of the operand QNaN - * values." In practice it seems that most implementations choose - * the first operand if both operands are qNaN. In short this gives - * the following rules: - * 1. A if it is signaling - * 2. B if it is signaling - * 3. A (quiet) - * 4. B (quiet) - * A signaling NaN is always silenced before returning it. - */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) - /* PowerPC propagation rules: - * 1. A if it sNaN or qNaN - * 2. B if it sNaN or qNaN - * A signaling NaN is always silenced before returning it. - */ - /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL - * 3.4 FLOATING-POINT INSTRUCTION DETAILS - * If either operand, but not both operands, of an operation is a - * nonsignaling NaN, then that NaN is returned as the result. If both - * operands are nonsignaling NaNs, then the destination operand - * nonsignaling NaN is returned as the result. - * If either operand to an operation is a signaling NaN (SNaN), then the - * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit - * is set in the FPCR ENABLE byte, then the exception is taken and the - * destination is not modified. If the SNaN exception enable bit is not - * set, setting the SNaN bit in the operand to a one converts the SNaN to - * a nonsignaling NaN. The operation then continues as described in the - * preceding paragraph for nonsignaling NaNs. - */ - if (is_nan(a_cls)) { - return 0; - } else { - return 1; - } -#else - /* This implements x87 NaN propagation rules: - * SNaN + QNaN => return the QNaN - * two SNaNs => return the one with the larger significand, silenced - * two QNaNs => return the one with the larger significand - * SNaN and a non-NaN => return the SNaN, silenced - * QNaN and a non-NaN => return the QNaN - * - * If we get down to comparing significands and they are the same, - * return the NaN with the positive sign bit (if any). - */ - if (is_snan(a_cls)) { - if (is_snan(b_cls)) { - return aIsLargerSignificand ? 0 : 1; - } - return is_qnan(b_cls) ? 1 : 0; - } else if (is_qnan(a_cls)) { - if (is_snan(b_cls) || !is_qnan(b_cls)) { - return 0; - } else { - return aIsLargerSignificand ? 0 : 1; - } - } else { - return 1; - } -#endif -} - -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a three-input operation. -| For the moment we assume that no CPU needs the 'larger significand' -| information. -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN -*----------------------------------------------------------------------------*/ -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, float_status *status) -{ -#if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid, status); - return 3; - } - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } -#elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - float_raise(float_flag_invalid, status); - return 3; - } - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - if (infzero) { - float_raise(float_flag_invalid, status); - return 2; - } - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - } -#elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - if (infzero) { - float_raise(float_flag_invalid, status); - return 2; - } - - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } -#else - /* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; - } else { - return 2; - } -#endif -} - -/*---------------------------------------------------------------------------- -| Takes two single-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) -{ - bool aIsLargerSignificand; - uint32_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float32_is_any_nan(a) - ? float_class_normal - : float32_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float32_is_any_nan(b) - ? float_class_normal - : float32_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av = float32_val(a); - bv = float32_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { - aIsLargerSignificand = 0; - } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { - if (is_snan(b_cls)) { - return float32_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float32_silence_nan(a, status); - } - return a; - } -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a quiet -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float64_is_quiet_nan(float64 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return float64_is_any_nan(a_); -#else - uint64_t a = float64_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 51) & 0xFFF) == 0xFFE) - && (a & 0x0007FFFFFFFFFFFFULL); - } else { - return ((a << 1) >= 0xFFF0000000000000ULL); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float64_is_signaling_nan(float64 a_, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint64_t a = float64_val(a_); - if (snan_bit_is_one(status)) { - return ((a << 1) >= 0xFFF0000000000000ULL); - } else { - return (((a >> 51) & 0xFFF) == 0xFFE) - && (a & UINT64_C(0x0007FFFFFFFFFFFF)); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float64ToCommonNaN(float64 a, float_status *status) -{ - commonNaNT z; - - if (float64_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float64_val(a) >> 63; - z.low = 0; - z.high = float64_val(a) << 12; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the double- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float64 commonNaNToFloat64(commonNaNT a, float_status *status) -{ - uint64_t mantissa = a.high >> 12; - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if (mantissa) { - return make_float64( - (((uint64_t) a.sign) << 63) - | UINT64_C(0x7FF0000000000000) - | (a.high >> 12)); - } else { - return float64_default_nan(status); - } -} - -/*---------------------------------------------------------------------------- -| Takes two double-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) -{ - bool aIsLargerSignificand; - uint64_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float64_is_any_nan(a) - ? float_class_normal - : float64_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float64_is_any_nan(b) - ? float_class_normal - : float64_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av = float64_val(a); - bv = float64_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { - aIsLargerSignificand = 0; - } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { - if (is_snan(b_cls)) { - return float64_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float64_silence_nan(a, status); - } - return a; - } -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the extended double-precision floating-point value `a' is a -| quiet NaN; otherwise returns 0. This slightly differs from the same -| function for other types as floatx80 has an explicit bit. -*----------------------------------------------------------------------------*/ - -int floatx80_is_quiet_nan(floatx80 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return floatx80_is_any_nan(a); -#else - if (snan_bit_is_one(status)) { - uint64_t aLow; - - aLow = a.low & ~0x4000000000000000ULL; - return ((a.high & 0x7FFF) == 0x7FFF) - && (aLow << 1) - && (a.low == aLow); - } else { - return ((a.high & 0x7FFF) == 0x7FFF) - && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the extended double-precision floating-point value `a' is a -| signaling NaN; otherwise returns 0. This slightly differs from the same -| function for other types as floatx80 has an explicit bit. -*----------------------------------------------------------------------------*/ - -int floatx80_is_signaling_nan(floatx80 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return 0; -#else - if (snan_bit_is_one(status)) { - return ((a.high & 0x7FFF) == 0x7FFF) - && ((a.low << 1) >= 0x8000000000000000ULL); - } else { - uint64_t aLow; - - aLow = a.low & ~UINT64_C(0x4000000000000000); - return ((a.high & 0x7FFF) == 0x7FFF) - && (uint64_t)(aLow << 1) - && (a.low == aLow); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the extended double-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_silence_nan(floatx80 a, float_status *status) -{ - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); - a.low |= UINT64_C(0xC000000000000000); - return a; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) -{ - floatx80 dflt; - commonNaNT z; - - if (floatx80_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - if (a.low >> 63) { - z.sign = a.high >> 15; - z.low = 0; - z.high = a.low << 1; - } else { - dflt = floatx80_default_nan(status); - z.sign = dflt.high >> 15; - z.low = 0; - z.high = dflt.low << 1; - } - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the extended -| double-precision floating-point format. -*----------------------------------------------------------------------------*/ - -static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) -{ - floatx80 z; - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.high >> 1) { - z.low = UINT64_C(0x8000000000000000) | a.high >> 1; - z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; - } else { - z = floatx80_default_nan(status); - } - return z; -} - -/*---------------------------------------------------------------------------- -| Takes two extended double-precision floating-point values `a' and `b', one -| of which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a quiet -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float128_is_quiet_nan(float128 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return float128_is_any_nan(a); -#else - if (snan_bit_is_one(status)) { - return (((a.high >> 47) & 0xFFFF) == 0xFFFE) - && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); - } else { - return ((a.high << 1) >= 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a -| signaling NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -bool float128_is_signaling_nan(float128 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - return 0; -#else - if (snan_bit_is_one(status)) { - return ((a.high << 1) >= 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); - } else { - return (((a.high >> 47) & 0xFFFF) == 0xFFFE) - && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the quadruple-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -float128 float128_silence_nan(float128 a, float_status *status) -{ -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return float128_default_nan(status); - } else { - a.high |= UINT64_C(0x0000800000000000); - return a; - } -#endif -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float128ToCommonNaN(float128 a, float_status *status) -{ - commonNaNT z; - - if (float128_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = a.high >> 63; - shortShift128Left(a.high, a.low, 16, &z.high, &z.low); - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the quadruple- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float128 commonNaNToFloat128(commonNaNT a, float_status *status) -{ - float128 z; - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - shift128Right(a.high, a.low, 16, &z.high, &z.low); - z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); - return z; -} - -/*---------------------------------------------------------------------------- -| Takes two quadruple-precision floating-point values `a' and `b', one of -| which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float128 propagateFloat128NaN(float128 a, float128 b, - float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float128_is_any_nan(a) - ? float_class_normal - : float128_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float128_is_any_nan(b) - ? float_class_normal - : float128_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { - aIsLargerSignificand = 0; - } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { - if (is_snan(b_cls)) { - return float128_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float128_silence_nan(a, status); - } - return a; - } -} diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 79be4f5840..5dce791eb6 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -621,7 +621,7 @@ static inline float64 float64_pack_raw(FloatParts p) | are propagated from function inputs to output. These details are target- | specific. *----------------------------------------------------------------------------*/ -#include "softfloat-specialize.inc.c" +#include "softfloat-specialize.c.inc" /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e63450a893..d40c925d04 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -636,7 +636,7 @@ struct TCGContext { /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ - /* These structures are private to tcg-target.inc.c. */ + /* These structures are private to tcg-target.c.inc. */ #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; #endif diff --git a/memory_ldst.c.inc b/memory_ldst.c.inc new file mode 100644 index 0000000000..c54aee4a95 --- /dev/null +++ b/memory_ldst.c.inc @@ -0,0 +1,529 @@ +/* + * Physical memory access templates + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2015 Linaro, Inc. + * Copyright (c) 2016 Red Hat, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* warning: addr must be aligned */ +static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, + enum device_endian endian) +{ + uint8_t *ptr; + uint64_t val; + MemoryRegion *mr; + hwaddr l = 4; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); + if (l < 4 || !memory_access_is_direct(mr, false)) { + release_lock |= prepare_mmio_access(mr); + + /* I/O case */ + r = memory_region_dispatch_read(mr, addr1, &val, + MO_32 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + val = ldl_le_p(ptr); + break; + case DEVICE_BIG_ENDIAN: + val = ldl_be_p(ptr); + break; + default: + val = ldl_p(ptr); + break; + } + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); + return val; +} + +uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + +/* warning: addr must be aligned */ +static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, + enum device_endian endian) +{ + uint8_t *ptr; + uint64_t val; + MemoryRegion *mr; + hwaddr l = 8; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); + if (l < 8 || !memory_access_is_direct(mr, false)) { + release_lock |= prepare_mmio_access(mr); + + /* I/O case */ + r = memory_region_dispatch_read(mr, addr1, &val, + MO_64 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + val = ldq_le_p(ptr); + break; + case DEVICE_BIG_ENDIAN: + val = ldq_be_p(ptr); + break; + default: + val = ldq_p(ptr); + break; + } + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); + return val; +} + +uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + +uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + uint8_t *ptr; + uint64_t val; + MemoryRegion *mr; + hwaddr l = 1; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); + if (!memory_access_is_direct(mr, false)) { + release_lock |= prepare_mmio_access(mr); + + /* I/O case */ + r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + val = ldub_p(ptr); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); + return val; +} + +/* warning: addr must be aligned */ +static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, + enum device_endian endian) +{ + uint8_t *ptr; + uint64_t val; + MemoryRegion *mr; + hwaddr l = 2; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); + if (l < 2 || !memory_access_is_direct(mr, false)) { + release_lock |= prepare_mmio_access(mr); + + /* I/O case */ + r = memory_region_dispatch_read(mr, addr1, &val, + MO_16 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + val = lduw_le_p(ptr); + break; + case DEVICE_BIG_ENDIAN: + val = lduw_be_p(ptr); + break; + default: + val = lduw_p(ptr); + break; + } + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); + return val; +} + +uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + +/* warning: addr must be aligned. The ram page is not masked as dirty + and the code inside is not invalidated. It is useful if the dirty + bits are used to track modified PTEs */ +void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l = 4; + hwaddr addr1; + MemTxResult r; + uint8_t dirty_log_mask; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 4 || !memory_access_is_direct(mr, true)) { + release_lock |= prepare_mmio_access(mr); + + r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + } else { + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + stl_p(ptr, val); + + dirty_log_mask = memory_region_get_dirty_log_mask(mr); + dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); + cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr, + 4, dirty_log_mask); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); +} + +/* warning: addr must be aligned */ +static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, + MemTxResult *result, enum device_endian endian) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l = 4; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 4 || !memory_access_is_direct(mr, true)) { + release_lock |= prepare_mmio_access(mr); + r = memory_region_dispatch_write(mr, addr1, val, + MO_32 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + stl_le_p(ptr, val); + break; + case DEVICE_BIG_ENDIAN: + stl_be_p(ptr, val); + break; + default: + stl_p(ptr, val); + break; + } + invalidate_and_set_dirty(mr, addr1, 4); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); +} + +void glue(address_space_stl, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, + result, DEVICE_NATIVE_ENDIAN); +} + +void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, + result, DEVICE_LITTLE_ENDIAN); +} + +void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, + result, DEVICE_BIG_ENDIAN); +} + +void glue(address_space_stb, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l = 1; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); + if (!memory_access_is_direct(mr, true)) { + release_lock |= prepare_mmio_access(mr); + r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + stb_p(ptr, val); + invalidate_and_set_dirty(mr, addr1, 1); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); +} + +/* warning: addr must be aligned */ +static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, + MemTxResult *result, enum device_endian endian) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l = 2; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 2 || !memory_access_is_direct(mr, true)) { + release_lock |= prepare_mmio_access(mr); + r = memory_region_dispatch_write(mr, addr1, val, + MO_16 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + stw_le_p(ptr, val); + break; + case DEVICE_BIG_ENDIAN: + stw_be_p(ptr, val); + break; + default: + stw_p(ptr, val); + break; + } + invalidate_and_set_dirty(mr, addr1, 2); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); +} + +void glue(address_space_stw, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + +static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, + MemTxResult *result, enum device_endian endian) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l = 8; + hwaddr addr1; + MemTxResult r; + bool release_lock = false; + + RCU_READ_LOCK(); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 8 || !memory_access_is_direct(mr, true)) { + release_lock |= prepare_mmio_access(mr); + r = memory_region_dispatch_write(mr, addr1, val, + MO_64 | devend_memop(endian), attrs); + } else { + /* RAM case */ + ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + switch (endian) { + case DEVICE_LITTLE_ENDIAN: + stq_le_p(ptr, val); + break; + case DEVICE_BIG_ENDIAN: + stq_be_p(ptr, val); + break; + default: + stq_p(ptr, val); + break; + } + invalidate_and_set_dirty(mr, addr1, 8); + r = MEMTX_OK; + } + if (result) { + *result = r; + } + if (release_lock) { + qemu_mutex_unlock_iothread(); + } + RCU_READ_UNLOCK(); +} + +void glue(address_space_stq, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) +{ + glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + +#undef ARG1_DECL +#undef ARG1 +#undef SUFFIX +#undef TRANSLATE +#undef RCU_READ_LOCK +#undef RCU_READ_UNLOCK diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c deleted file mode 100644 index c54aee4a95..0000000000 --- a/memory_ldst.inc.c +++ /dev/null @@ -1,529 +0,0 @@ -/* - * Physical memory access templates - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2015 Linaro, Inc. - * Copyright (c) 2016 Red Hat, Inc. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -/* warning: addr must be aligned */ -static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) -{ - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l = 4; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 4 || !memory_access_is_direct(mr, false)) { - release_lock |= prepare_mmio_access(mr); - - /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, - MO_32 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - val = ldl_le_p(ptr); - break; - case DEVICE_BIG_ENDIAN: - val = ldl_be_p(ptr); - break; - default: - val = ldl_p(ptr); - break; - } - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); - return val; -} - -uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_NATIVE_ENDIAN); -} - -uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_LITTLE_ENDIAN); -} - -uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_BIG_ENDIAN); -} - -/* warning: addr must be aligned */ -static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) -{ - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l = 8; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 8 || !memory_access_is_direct(mr, false)) { - release_lock |= prepare_mmio_access(mr); - - /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, - MO_64 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - val = ldq_le_p(ptr); - break; - case DEVICE_BIG_ENDIAN: - val = ldq_be_p(ptr); - break; - default: - val = ldq_p(ptr); - break; - } - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); - return val; -} - -uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_NATIVE_ENDIAN); -} - -uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_LITTLE_ENDIAN); -} - -uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_BIG_ENDIAN); -} - -uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l = 1; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false, attrs); - if (!memory_access_is_direct(mr, false)) { - release_lock |= prepare_mmio_access(mr); - - /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - val = ldub_p(ptr); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); - return val; -} - -/* warning: addr must be aligned */ -static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) -{ - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l = 2; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 2 || !memory_access_is_direct(mr, false)) { - release_lock |= prepare_mmio_access(mr); - - /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, - MO_16 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - val = lduw_le_p(ptr); - break; - case DEVICE_BIG_ENDIAN: - val = lduw_be_p(ptr); - break; - default: - val = lduw_p(ptr); - break; - } - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); - return val; -} - -uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_NATIVE_ENDIAN); -} - -uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_LITTLE_ENDIAN); -} - -uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result, - DEVICE_BIG_ENDIAN); -} - -/* warning: addr must be aligned. The ram page is not masked as dirty - and the code inside is not invalidated. It is useful if the dirty - bits are used to track modified PTEs */ -void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l = 4; - hwaddr addr1; - MemTxResult r; - uint8_t dirty_log_mask; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 4 || !memory_access_is_direct(mr, true)) { - release_lock |= prepare_mmio_access(mr); - - r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); - } else { - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - stl_p(ptr, val); - - dirty_log_mask = memory_region_get_dirty_log_mask(mr); - dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); - cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr, - 4, dirty_log_mask); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); -} - -/* warning: addr must be aligned */ -static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) -{ - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l = 4; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 4 || !memory_access_is_direct(mr, true)) { - release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, - MO_32 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stl_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stl_be_p(ptr, val); - break; - default: - stl_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 4); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); -} - -void glue(address_space_stl, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_NATIVE_ENDIAN); -} - -void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_LITTLE_ENDIAN); -} - -void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_BIG_ENDIAN); -} - -void glue(address_space_stb, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l = 1; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true, attrs); - if (!memory_access_is_direct(mr, true)) { - release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - stb_p(ptr, val); - invalidate_and_set_dirty(mr, addr1, 1); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); -} - -/* warning: addr must be aligned */ -static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) -{ - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l = 2; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 2 || !memory_access_is_direct(mr, true)) { - release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, - MO_16 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stw_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stw_be_p(ptr, val); - break; - default: - stw_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 2); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); -} - -void glue(address_space_stw, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_NATIVE_ENDIAN); -} - -void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_LITTLE_ENDIAN); -} - -void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_BIG_ENDIAN); -} - -static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) -{ - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l = 8; - hwaddr addr1; - MemTxResult r; - bool release_lock = false; - - RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 8 || !memory_access_is_direct(mr, true)) { - release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, - MO_64 | devend_memop(endian), attrs); - } else { - /* RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stq_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stq_be_p(ptr, val); - break; - default: - stq_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 8); - r = MEMTX_OK; - } - if (result) { - *result = r; - } - if (release_lock) { - qemu_mutex_unlock_iothread(); - } - RCU_READ_UNLOCK(); -} - -void glue(address_space_stq, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_NATIVE_ENDIAN); -} - -void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_LITTLE_ENDIAN); -} - -void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) -{ - glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result, - DEVICE_BIG_ENDIAN); -} - -#undef ARG1_DECL -#undef ARG1 -#undef SUFFIX -#undef TRANSLATE -#undef RCU_READ_LOCK -#undef RCU_READ_UNLOCK diff --git a/scripts/clean-includes b/scripts/clean-includes index 795b3bea31..aaa7d4ceb3 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -113,7 +113,7 @@ EOT for f in "$@"; do case "$f" in - *.inc.c) + *.c.inc) # These aren't standalone C source files echo "SKIPPING $f (not a standalone source file)" continue diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index fa39fd7c83..317eed993f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -13,66 +13,66 @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) +target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) +target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) +target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) +target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) +target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE) +target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) +target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) +target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) +target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) +target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) -target/arm/translate-sve.o: target/arm/decode-sve.inc.c -target/arm/translate.o: target/arm/decode-neon-shared.inc.c -target/arm/translate.o: target/arm/decode-neon-dp.inc.c -target/arm/translate.o: target/arm/decode-neon-ls.inc.c -target/arm/translate.o: target/arm/decode-vfp.inc.c -target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c -target/arm/translate.o: target/arm/decode-a32.inc.c -target/arm/translate.o: target/arm/decode-a32-uncond.inc.c -target/arm/translate.o: target/arm/decode-t32.inc.c -target/arm/translate.o: target/arm/decode-t16.inc.c +target/arm/translate-sve.o: target/arm/decode-sve.c.inc +target/arm/translate.o: target/arm/decode-neon-shared.c.inc +target/arm/translate.o: target/arm/decode-neon-dp.c.inc +target/arm/translate.o: target/arm/decode-neon-ls.c.inc +target/arm/translate.o: target/arm/decode-vfp.c.inc +target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc +target/arm/translate.o: target/arm/decode-a32.c.inc +target/arm/translate.o: target/arm/decode-a32-uncond.c.inc +target/arm/translate.o: target/arm/decode-t32.c.inc +target/arm/translate.o: target/arm/decode-t16.c.inc obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc new file mode 100644 index 0000000000..8fbe8cef9f --- /dev/null +++ b/target/arm/translate-neon.c.inc @@ -0,0 +1,4161 @@ +/* + * ARM translation: AArch32 Neon instructions + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2005-2007 CodeSourcery + * Copyright (c) 2007 OpenedHand, Ltd. + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * This file is intended to be included from translate.c; it uses + * some macros and definitions provided by that file. + * It might be possible to convert it to a standalone .c file eventually. + */ + +static inline int plus1(DisasContext *s, int x) +{ + return x + 1; +} + +static inline int rsub_64(DisasContext *s, int x) +{ + return 64 - x; +} + +static inline int rsub_32(DisasContext *s, int x) +{ + return 32 - x; +} +static inline int rsub_16(DisasContext *s, int x) +{ + return 16 - x; +} +static inline int rsub_8(DisasContext *s, int x) +{ + return 8 - x; +} + +/* Include the generated Neon decoder */ +#include "decode-neon-dp.c.inc" +#include "decode-neon-ls.c.inc" +#include "decode-neon-shared.c.inc" + +/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, + * where 0 is the least significant end of the register. + */ +static inline long +neon_element_offset(int reg, int element, MemOp size) +{ + int element_size = 1 << size; + int ofs = element * element_size; +#ifdef HOST_WORDS_BIGENDIAN + /* Calculate the offset assuming fully little-endian, + * then XOR to account for the order of the 8-byte units. + */ + if (element_size < 8) { + ofs ^= 8 - element_size; + } +#endif + return neon_reg_offset(reg, 0) + ofs; +} + +static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) +{ + long offset = neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i32(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i32(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) +{ + long offset = neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i64(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i64(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld32u_i64(var, cpu_env, offset); + break; + case MO_Q: + tcg_gen_ld_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) +{ + long offset = neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i32(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i32(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) +{ + long offset = neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i64(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i64(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st32_i64(var, cpu_env, offset); + break; + case MO_64: + tcg_gen_st_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + +static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) +{ + int opr_sz; + TCGv_ptr fpst; + gen_helper_gvec_3_ptr *fn_gvec_ptr; + + if (!dc_isar_feature(aa32_vcma, s) + || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + opr_sz = (1 + a->q) * 8; + fpst = get_fpstatus_ptr(1); + fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + vfp_reg_offset(1, a->vn), + vfp_reg_offset(1, a->vm), + fpst, opr_sz, opr_sz, a->rot, + fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCADD(DisasContext *s, arg_VCADD *a) +{ + int opr_sz; + TCGv_ptr fpst; + gen_helper_gvec_3_ptr *fn_gvec_ptr; + + if (!dc_isar_feature(aa32_vcma, s) + || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + opr_sz = (1 + a->q) * 8; + fpst = get_fpstatus_ptr(1); + fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + vfp_reg_offset(1, a->vn), + vfp_reg_offset(1, a->vm), + fpst, opr_sz, opr_sz, a->rot, + fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VDOT(DisasContext *s, arg_VDOT *a) +{ + int opr_sz; + gen_helper_gvec_3 *fn_gvec; + + if (!dc_isar_feature(aa32_dp, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + opr_sz = (1 + a->q) * 8; + fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; + tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), + vfp_reg_offset(1, a->vn), + vfp_reg_offset(1, a->vm), + opr_sz, opr_sz, 0, fn_gvec); + return true; +} + +static bool trans_VFML(DisasContext *s, arg_VFML *a) +{ + int opr_sz; + + if (!dc_isar_feature(aa32_fhm, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + (a->vd & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + opr_sz = (1 + a->q) * 8; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + vfp_reg_offset(a->q, a->vn), + vfp_reg_offset(a->q, a->vm), + cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */ + gen_helper_gvec_fmlal_a32); + return true; +} + +static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) +{ + gen_helper_gvec_3_ptr *fn_gvec_ptr; + int opr_sz; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_vcma, s)) { + return false; + } + if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vn) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); + opr_sz = (1 + a->q) * 8; + fpst = get_fpstatus_ptr(1); + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + vfp_reg_offset(1, a->vn), + vfp_reg_offset(1, a->vm), + fpst, opr_sz, opr_sz, + (a->index << 2) | a->rot, fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a) +{ + gen_helper_gvec_3 *fn_gvec; + int opr_sz; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_dp, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn) & 0x10)) { + return false; + } + + if ((a->vd | a->vn) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b; + opr_sz = (1 + a->q) * 8; + fpst = get_fpstatus_ptr(1); + tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), + vfp_reg_offset(1, a->vn), + vfp_reg_offset(1, a->rm), + opr_sz, opr_sz, a->index, fn_gvec); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) +{ + int opr_sz; + + if (!dc_isar_feature(aa32_fhm, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + opr_sz = (1 + a->q) * 8; + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), + vfp_reg_offset(a->q, a->vn), + vfp_reg_offset(a->q, a->rm), + cpu_env, opr_sz, opr_sz, + (a->index << 2) | a->s, /* is_2 == 0 */ + gen_helper_gvec_fmlal_idx_a32); + return true; +} + +static struct { + int nregs; + int interleave; + int spacing; +} const neon_ls_element_type[11] = { + {1, 4, 1}, + {1, 4, 2}, + {4, 1, 1}, + {2, 2, 2}, + {1, 3, 1}, + {1, 3, 2}, + {3, 1, 1}, + {1, 1, 1}, + {1, 2, 1}, + {1, 2, 2}, + {2, 1, 1} +}; + +static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn, + int stride) +{ + if (rm != 15) { + TCGv_i32 base; + + base = load_reg(s, rn); + if (rm == 13) { + tcg_gen_addi_i32(base, base, stride); + } else { + TCGv_i32 index; + index = load_reg(s, rm); + tcg_gen_add_i32(base, base, index); + tcg_temp_free_i32(index); + } + store_reg(s, rn, base); + } +} + +static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) +{ + /* Neon load/store multiple structures */ + int nregs, interleave, spacing, reg, n; + MemOp endian = s->be_data; + int mmu_idx = get_mem_index(s); + int size = a->size; + TCGv_i64 tmp64; + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + if (a->itype > 10) { + return false; + } + /* Catch UNDEF cases for bad values of align field */ + switch (a->itype & 0xc) { + case 4: + if (a->align >= 2) { + return false; + } + break; + case 8: + if (a->align == 3) { + return false; + } + break; + default: + break; + } + nregs = neon_ls_element_type[a->itype].nregs; + interleave = neon_ls_element_type[a->itype].interleave; + spacing = neon_ls_element_type[a->itype].spacing; + if (size == 3 && (interleave | spacing) != 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* For our purposes, bytes are always little-endian. */ + if (size == 0) { + endian = MO_LE; + } + /* + * Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + if (interleave == 1 && endian == MO_LE) { + size = 3; + } + tmp64 = tcg_temp_new_i64(); + addr = tcg_temp_new_i32(); + tmp = tcg_const_i32(1 << size); + load_reg_var(s, addr, a->rn); + for (reg = 0; reg < nregs; reg++) { + for (n = 0; n < 8 >> size; n++) { + int xs; + for (xs = 0; xs < interleave; xs++) { + int tt = a->vd + reg + spacing * xs; + + if (a->l) { + gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); + neon_store_element64(tt, n, size, tmp64); + } else { + neon_load_element64(tmp64, tt, n, size); + gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); + } + tcg_gen_add_i32(addr, addr, tmp); + } + } + } + tcg_temp_free_i32(addr); + tcg_temp_free_i32(tmp); + tcg_temp_free_i64(tmp64); + + gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); + return true; +} + +static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) +{ + /* Neon load single structure to all lanes */ + int reg, stride, vec_size; + int vd = a->vd; + int size = a->size; + int nregs = a->n + 1; + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (size == 3) { + if (nregs != 4 || a->a == 0) { + return false; + } + /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ + size = 2; + } + if (nregs == 1 && a->a == 1 && size == 0) { + return false; + } + if (nregs == 3 && a->a == 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * VLD1 to all lanes: T bit indicates how many Dregs to write. + * VLD2/3/4 to all lanes: T bit indicates register stride. + */ + stride = a->t ? 2 : 1; + vec_size = nregs == 1 ? stride * 8 : 8; + + tmp = tcg_temp_new_i32(); + addr = tcg_temp_new_i32(); + load_reg_var(s, addr, a->rn); + for (reg = 0; reg < nregs; reg++) { + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + s->be_data | size); + if ((vd & 1) && vec_size == 16) { + /* + * We cannot write 16 bytes at once because the + * destination is unaligned. + */ + tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + 8, 8, tmp); + tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), + neon_reg_offset(vd, 0), 8, 8); + } else { + tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + vec_size, vec_size, tmp); + } + tcg_gen_addi_i32(addr, addr, 1 << size); + vd += stride; + } + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + + gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs); + + return true; +} + +static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) +{ + /* Neon load/store single structure to one lane */ + int reg; + int nregs = a->n + 1; + int vd = a->vd; + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + /* Catch the UNDEF cases. This is unavoidably a bit messy. */ + switch (nregs) { + case 1: + if (((a->align & (1 << a->size)) != 0) || + (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { + return false; + } + break; + case 3: + if ((a->align & 1) != 0) { + return false; + } + /* fall through */ + case 2: + if (a->size == 2 && (a->align & 2) != 0) { + return false; + } + break; + case 4: + if ((a->size == 2) && ((a->align & 3) == 3)) { + return false; + } + break; + default: + abort(); + } + if ((vd + a->stride * (nregs - 1)) > 31) { + /* + * Attempts to write off the end of the register file are + * UNPREDICTABLE; we choose to UNDEF because otherwise we would + * access off the end of the array that holds the register data. + */ + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i32(); + addr = tcg_temp_new_i32(); + load_reg_var(s, addr, a->rn); + /* + * TODO: if we implemented alignment exceptions, we should check + * addr against the alignment encoded in a->align here. + */ + for (reg = 0; reg < nregs; reg++) { + if (a->l) { + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + s->be_data | a->size); + neon_store_element(vd, a->reg_idx, a->size, tmp); + } else { /* Store */ + neon_load_element(tmp, vd, a->reg_idx, a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + s->be_data | a->size); + } + vd += a->stride; + tcg_gen_addi_i32(addr, addr, 1 << a->size); + } + tcg_temp_free_i32(addr); + tcg_temp_free_i32(tmp); + + gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs); + + return true; +} + +static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) +{ + int vec_size = a->q ? 16 : 8; + int rd_ofs = neon_reg_offset(a->vd, 0); + int rn_ofs = neon_reg_offset(a->vn, 0); + int rm_ofs = neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); + return true; +} + +#define DO_3SAME(INSN, FUNC) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + return do_3same(s, a, FUNC); \ + } + +DO_3SAME(VADD, tcg_gen_gvec_add) +DO_3SAME(VSUB, tcg_gen_gvec_sub) +DO_3SAME(VAND, tcg_gen_gvec_and) +DO_3SAME(VBIC, tcg_gen_gvec_andc) +DO_3SAME(VORR, tcg_gen_gvec_or) +DO_3SAME(VORN, tcg_gen_gvec_orc) +DO_3SAME(VEOR, tcg_gen_gvec_xor) +DO_3SAME(VSHL_S, gen_gvec_sshl) +DO_3SAME(VSHL_U, gen_gvec_ushl) +DO_3SAME(VQADD_S, gen_gvec_sqadd_qc) +DO_3SAME(VQADD_U, gen_gvec_uqadd_qc) +DO_3SAME(VQSUB_S, gen_gvec_sqsub_qc) +DO_3SAME(VQSUB_U, gen_gvec_uqsub_qc) + +/* These insns are all gvec_bitsel but with the inputs in various orders. */ +#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \ + } \ + DO_3SAME(INSN, gen_##INSN##_3s) + +DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs) +DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs) +DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs) + +#define DO_3SAME_NO_SZ_3(INSN, FUNC) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size == 3) { \ + return false; \ + } \ + return do_3same(s, a, FUNC); \ + } + +DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) +DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) +DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) +DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) +DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul) +DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla) +DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls) +DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst) +DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd) +DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba) +DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd) +DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba) + +#define DO_3SAME_CMP(INSN, COND) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \ + } \ + DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s) + +DO_3SAME_CMP(VCGT_S, TCG_COND_GT) +DO_3SAME_CMP(VCGT_U, TCG_COND_GTU) +DO_3SAME_CMP(VCGE_S, TCG_COND_GE) +DO_3SAME_CMP(VCGE_U, TCG_COND_GEU) +DO_3SAME_CMP(VCEQ, TCG_COND_EQ) + +#define WRAP_OOL_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \ + uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \ + { \ + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \ + } + +WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b) + +static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) +{ + if (a->size != 0) { + return false; + } + return do_3same(s, a, gen_VMUL_p_3s); +} + +#define DO_VQRDMLAH(INSN, FUNC) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (!dc_isar_feature(aa32_rdm, s)) { \ + return false; \ + } \ + if (a->size != 1 && a->size != 2) { \ + return false; \ + } \ + return do_3same(s, a, FUNC); \ + } + +DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) +DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) + +#define DO_SHA1(NAME, FUNC) \ + WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ + static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (!dc_isar_feature(aa32_sha1, s)) { \ + return false; \ + } \ + return do_3same(s, a, gen_##NAME##_3s); \ + } + +DO_SHA1(SHA1C, gen_helper_crypto_sha1c) +DO_SHA1(SHA1P, gen_helper_crypto_sha1p) +DO_SHA1(SHA1M, gen_helper_crypto_sha1m) +DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0) + +#define DO_SHA2(NAME, FUNC) \ + WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ + static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (!dc_isar_feature(aa32_sha2, s)) { \ + return false; \ + } \ + return do_3same(s, a, gen_##NAME##_3s); \ + } + +DO_SHA2(SHA256H, gen_helper_crypto_sha256h) +DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2) +DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1) + +#define DO_3SAME_64(INSN, FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 op = { .fni8 = FUNC }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \ + } \ + DO_3SAME(INSN, gen_##INSN##_3s) + +#define DO_3SAME_64_ENV(INSN, FUNC) \ + static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \ + { \ + FUNC(d, cpu_env, n, m); \ + } \ + DO_3SAME_64(INSN, gen_##INSN##_elt) + +DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64) +DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64) +DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64) +DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64) +DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64) +DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) + +#define DO_3SAME_32(INSN, FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[4] = { \ + { .fni4 = gen_helper_neon_##FUNC##8 }, \ + { .fni4 = gen_helper_neon_##FUNC##16 }, \ + { .fni4 = gen_helper_neon_##FUNC##32 }, \ + { 0 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + +/* + * Some helper functions need to be passed the cpu_env. In order + * to use those with the gvec APIs like tcg_gen_gvec_3() we need + * to create wrapper functions whose prototype is a NeonGenTwoOpFn() + * and which call a NeonGenTwoOpEnvFn(). + */ +#define WRAP_ENV_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ + { \ + FUNC(d, cpu_env, n, m); \ + } + +#define DO_3SAME_32_ENV(INSN, FUNC) \ + WRAP_ENV_FN(gen_##INSN##_tramp8, gen_helper_neon_##FUNC##8); \ + WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##16); \ + WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##32); \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[4] = { \ + { .fni4 = gen_##INSN##_tramp8 }, \ + { .fni4 = gen_##INSN##_tramp16 }, \ + { .fni4 = gen_##INSN##_tramp32 }, \ + { 0 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + +DO_3SAME_32(VHADD_S, hadd_s) +DO_3SAME_32(VHADD_U, hadd_u) +DO_3SAME_32(VHSUB_S, hsub_s) +DO_3SAME_32(VHSUB_U, hsub_u) +DO_3SAME_32(VRHADD_S, rhadd_s) +DO_3SAME_32(VRHADD_U, rhadd_u) +DO_3SAME_32(VRSHL_S, rshl_s) +DO_3SAME_32(VRSHL_U, rshl_u) + +DO_3SAME_32_ENV(VQSHL_S, qshl_s) +DO_3SAME_32_ENV(VQSHL_U, qshl_u) +DO_3SAME_32_ENV(VQRSHL_S, qrshl_s) +DO_3SAME_32_ENV(VQRSHL_U, qrshl_u) + +static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) +{ + /* Operations handled pairwise 32 bits at a time */ + TCGv_i32 tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (a->size == 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + assert(a->q == 0); /* enforced by decode patterns */ + + /* + * Note that we have to be careful not to clobber the source operands + * in the "vm == vd" case by storing the result of the first pass too + * early. Since Q is 0 there are always just two passes, so instead + * of a complicated loop over each pass we just unroll. + */ + tmp = neon_load_reg(a->vn, 0); + tmp2 = neon_load_reg(a->vn, 1); + fn(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + + tmp3 = neon_load_reg(a->vm, 0); + tmp2 = neon_load_reg(a->vm, 1); + fn(tmp3, tmp3, tmp2); + tcg_temp_free_i32(tmp2); + + neon_store_reg(a->vd, 0, tmp); + neon_store_reg(a->vd, 1, tmp3); + return true; +} + +#define DO_3SAME_PAIR(INSN, func) \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + static NeonGenTwoOpFn * const fns[] = { \ + gen_helper_neon_##func##8, \ + gen_helper_neon_##func##16, \ + gen_helper_neon_##func##32, \ + }; \ + if (a->size > 2) { \ + return false; \ + } \ + return do_3same_pair(s, a, fns[a->size]); \ + } + +/* 32-bit pairwise ops end up the same as the elementwise versions. */ +#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32 +#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 +#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 +#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 +#define gen_helper_neon_padd_u32 tcg_gen_add_i32 + +DO_3SAME_PAIR(VPMAX_S, pmax_s) +DO_3SAME_PAIR(VPMIN_S, pmin_s) +DO_3SAME_PAIR(VPMAX_U, pmax_u) +DO_3SAME_PAIR(VPMIN_U, pmin_u) +DO_3SAME_PAIR(VPADD, padd_u) + +#define DO_3SAME_VQDMULH(INSN, FUNC) \ + WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \ + WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + static const GVecGen3 ops[2] = { \ + { .fni4 = gen_##INSN##_tramp16 }, \ + { .fni4 = gen_##INSN##_tramp32 }, \ + }; \ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \ + } \ + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 1 && a->size != 2) { \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + +DO_3SAME_VQDMULH(VQDMULH, qdmulh) +DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) + +static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn, + bool reads_vd) +{ + /* + * FP operations handled elementwise 32 bits at a time. + * If reads_vd is true then the old value of Vd will be + * loaded before calling the callback function. This is + * used for multiply-accumulate type operations. + */ + TCGv_i32 tmp, tmp2; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + tmp = neon_load_reg(a->vn, pass); + tmp2 = neon_load_reg(a->vm, pass); + if (reads_vd) { + TCGv_i32 tmp_rd = neon_load_reg(a->vd, pass); + fn(tmp_rd, tmp, tmp2, fpstatus); + neon_store_reg(a->vd, pass, tmp_rd); + tcg_temp_free_i32(tmp); + } else { + fn(tmp, tmp, tmp2, fpstatus); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(tmp2); + } + tcg_temp_free_ptr(fpstatus); + return true; +} + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP_GVEC(INSN,FUNC) \ + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ + uint32_t rn_ofs, uint32_t rm_ofs, \ + uint32_t oprsz, uint32_t maxsz) \ + { \ + TCGv_ptr fpst = get_fpstatus_ptr(1); \ + tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ + oprsz, maxsz, 0, FUNC); \ + tcg_temp_free_ptr(fpst); \ + } \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same(s, a, gen_##INSN##_3s); \ + } + + +DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s) +DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s) +DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s) +DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s) + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP(INSN,FUNC,READS_VD) \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same_fp(s, a, FUNC, READS_VD); \ + } + +DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false) +DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) +DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false) +DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false) +DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false) +DO_3S_FP(VMAX, gen_helper_vfp_maxs, false) +DO_3S_FP(VMIN, gen_helper_vfp_mins, false) + +static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muls(vn, vn, vm, fpstatus); + gen_helper_vfp_adds(vd, vd, vn, fpstatus); +} + +static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muls(vn, vn, vm, fpstatus); + gen_helper_vfp_subs(vd, vd, vn, fpstatus); +} + +DO_3S_FP(VMLA, gen_VMLA_fp_3s, true) +DO_3S_FP(VMLS, gen_VMLS_fp_3s, true) + +static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_helper_vfp_maxnums, false); +} + +static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_helper_vfp_minnums, false); +} + +WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32) + +static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs, + uint32_t rn_ofs, uint32_t rm_ofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp }; + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); +} + +static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same(s, a, gen_VRECPS_fp_3s); +} + +WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32) + +static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs, + uint32_t rn_ofs, uint32_t rm_ofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp }; + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); +} + +static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same(s, a, gen_VRSQRTS_fp_3s); +} + +static void gen_VFMA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); +} + +static bool trans_VFMA_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_VFMA_fp_3s, true); +} + +static void gen_VFMS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, + TCGv_ptr fpstatus) +{ + gen_helper_vfp_negs(vn, vn); + gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); +} + +static bool trans_VFMS_fp_3s(DisasContext *s, arg_3same *a) +{ + if (!dc_isar_feature(aa32_simdfmac, s)) { + return false; + } + + if (a->size != 0) { + /* TODO fp16 support */ + return false; + } + + return do_3same_fp(s, a, gen_VFMS_fp_3s, true); +} + +static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) +{ + /* FP operations handled pairwise 32 bits at a time */ + TCGv_i32 tmp, tmp2, tmp3; + TCGv_ptr fpstatus; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + assert(a->q == 0); /* enforced by decode patterns */ + + /* + * Note that we have to be careful not to clobber the source operands + * in the "vm == vd" case by storing the result of the first pass too + * early. Since Q is 0 there are always just two passes, so instead + * of a complicated loop over each pass we just unroll. + */ + fpstatus = get_fpstatus_ptr(1); + tmp = neon_load_reg(a->vn, 0); + tmp2 = neon_load_reg(a->vn, 1); + fn(tmp, tmp, tmp2, fpstatus); + tcg_temp_free_i32(tmp2); + + tmp3 = neon_load_reg(a->vm, 0); + tmp2 = neon_load_reg(a->vm, 1); + fn(tmp3, tmp3, tmp2, fpstatus); + tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(fpstatus); + + neon_store_reg(a->vd, 0, tmp); + neon_store_reg(a->vd, 1, tmp3); + return true; +} + +/* + * For all the functions using this macro, size == 1 means fp16, + * which is an architecture extension we don't implement yet. + */ +#define DO_3S_FP_PAIR(INSN,FUNC) \ + static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ + { \ + if (a->size != 0) { \ + /* TODO fp16 support */ \ + return false; \ + } \ + return do_3same_fp_pair(s, a, FUNC); \ + } + +DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) +DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) +DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) + +static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) +{ + /* Handle a 2-reg-shift insn which can be vectorized. */ + int vec_size = a->q ? 16 : 8; + int rd_ofs = neon_reg_offset(a->vd, 0); + int rm_ofs = neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); + return true; +} + +#define DO_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_vector_2sh(s, a, FUNC); \ + } \ + +DO_2SH(VSHL, tcg_gen_gvec_shli) +DO_2SH(VSLI, gen_gvec_sli) +DO_2SH(VSRI, gen_gvec_sri) +DO_2SH(VSRA_S, gen_gvec_ssra) +DO_2SH(VSRA_U, gen_gvec_usra) +DO_2SH(VRSHR_S, gen_gvec_srshr) +DO_2SH(VRSHR_U, gen_gvec_urshr) +DO_2SH(VRSRA_S, gen_gvec_srsra) +DO_2SH(VRSRA_U, gen_gvec_ursra) + +static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Signed shift out of range results in all-sign-bits */ + a->shift = MIN(a->shift, (8 << a->size) - 1); + return do_vector_2sh(s, a, tcg_gen_gvec_sari); +} + +static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); +} + +static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + /* Shift out of range is architecturally valid and results in zero. */ + if (a->shift >= (8 << a->size)) { + return do_vector_2sh(s, a, gen_zero_rd_2sh); + } else { + return do_vector_2sh(s, a, tcg_gen_gvec_shri); + } +} + +static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size == 3 case, where the + * function needs to be passed cpu_env. + */ + TCGv_i64 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm = tcg_const_i64(dup_const(a->size, a->shift)); + + for (pass = 0; pass < a->q + 1; pass++) { + TCGv_i64 tmp = tcg_temp_new_i64(); + + neon_load_reg64(tmp, a->vm + pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg64(tmp, a->vd + pass); + tcg_temp_free_i64(tmp); + } + tcg_temp_free_i64(constimm); + return true; +} + +static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpEnvFn *fn) +{ + /* + * 2-reg-and-shift operations, size < 3 case, where the + * helper needs to be passed cpu_env. + */ + TCGv_i32 constimm; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + constimm = tcg_const_i32(dup_const(a->size, a->shift)); + + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vm, pass); + fn(tmp, cpu_env, tmp, constimm); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(constimm); + return true; +} + +#define DO_2SHIFT_ENV(INSN, FUNC) \ + static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ + } \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + static NeonGenTwoOpEnvFn * const fns[] = { \ + gen_helper_neon_##FUNC##8, \ + gen_helper_neon_##FUNC##16, \ + gen_helper_neon_##FUNC##32, \ + }; \ + assert(a->size < ARRAY_SIZE(fns)); \ + return do_2shift_env_32(s, a, fns[a->size]); \ + } + +DO_2SHIFT_ENV(VQSHLU, qshlu_s) +DO_2SHIFT_ENV(VQSHL_U, qshl_u) +DO_2SHIFT_ENV(VQSHL_S, qshl_s) + +static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, + NeonGenTwo64OpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size == 3 case */ + TCGv_i64 constimm, rm1, rm2; + TCGv_i32 rd; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count. + */ + constimm = tcg_const_i64(-a->shift); + rm1 = tcg_temp_new_i64(); + rm2 = tcg_temp_new_i64(); + + /* Load both inputs first to avoid potential overwrite if rm == rd */ + neon_load_reg64(rm1, a->vm); + neon_load_reg64(rm2, a->vm + 1); + + shiftfn(rm1, rm1, constimm); + rd = tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm1); + neon_store_reg(a->vd, 0, rd); + + shiftfn(rm2, rm2, constimm); + rd = tcg_temp_new_i32(); + narrowfn(rd, cpu_env, rm2); + neon_store_reg(a->vd, 1, rd); + + tcg_temp_free_i64(rm1); + tcg_temp_free_i64(rm2); + tcg_temp_free_i64(constimm); + + return true; +} + +static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoOpFn *shiftfn, + NeonGenNarrowEnvFn *narrowfn) +{ + /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ + TCGv_i32 constimm, rm1, rm2, rm3, rm4; + TCGv_i64 rtmp; + uint32_t imm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is always a right shift, and the shiftfn is always a + * left-shift helper, which thus needs the negated shift count + * duplicated into each lane of the immediate value. + */ + if (a->size == 1) { + imm = (uint16_t)(-a->shift); + imm |= imm << 16; + } else { + /* size == 2 */ + imm = -a->shift; + } + constimm = tcg_const_i32(imm); + + /* Load all inputs first to avoid potential overwrite */ + rm1 = neon_load_reg(a->vm, 0); + rm2 = neon_load_reg(a->vm, 1); + rm3 = neon_load_reg(a->vm + 1, 0); + rm4 = neon_load_reg(a->vm + 1, 1); + rtmp = tcg_temp_new_i64(); + + shiftfn(rm1, rm1, constimm); + shiftfn(rm2, rm2, constimm); + + tcg_gen_concat_i32_i64(rtmp, rm1, rm2); + tcg_temp_free_i32(rm2); + + narrowfn(rm1, cpu_env, rtmp); + neon_store_reg(a->vd, 0, rm1); + + shiftfn(rm3, rm3, constimm); + shiftfn(rm4, rm4, constimm); + tcg_temp_free_i32(constimm); + + tcg_gen_concat_i32_i64(rtmp, rm3, rm4); + tcg_temp_free_i32(rm4); + + narrowfn(rm3, cpu_env, rtmp); + tcg_temp_free_i64(rtmp); + neon_store_reg(a->vd, 1, rm3); + return true; +} + +#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ + } +#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ + } + +static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + tcg_gen_extrl_i64_i32(dest, src); +} + +static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u16(dest, src); +} + +static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) +{ + gen_helper_neon_narrow_u8(dest, src); +} + +DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) +DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) +DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) +DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) +DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) + +DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) +DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) +DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8) + +DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32) +DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16) +DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8) +DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) +DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) +DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8) + +DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32) +DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16) +DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8) + +DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) +DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) +DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8) + +DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32) +DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16) +DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8) + +static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenWidenFn *widenfn, bool u) +{ + TCGv_i64 tmp; + TCGv_i32 rm0, rm1; + uint64_t widen_mask = 0; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* + * This is a widen-and-shift operation. The shift is always less + * than the width of the source type, so after widening the input + * vector we can simply shift the whole 64-bit widened register, + * and then clear the potential overflow bits resulting from left + * bits of the narrow input appearing as right bits of the left + * neighbour narrow input. Calculate a mask of bits to clear. + */ + if ((a->shift != 0) && (a->size < 2 || u)) { + int esize = 8 << a->size; + widen_mask = MAKE_64BIT_MASK(0, esize); + widen_mask >>= esize - a->shift; + widen_mask = dup_const(a->size + 1, widen_mask); + } + + rm0 = neon_load_reg(a->vm, 0); + rm1 = neon_load_reg(a->vm, 1); + tmp = tcg_temp_new_i64(); + + widenfn(tmp, rm0); + tcg_temp_free_i32(rm0); + if (a->shift != 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd); + + widenfn(tmp, rm1); + tcg_temp_free_i32(rm1); + if (a->shift != 0) { + tcg_gen_shli_i64(tmp, tmp, a->shift); + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); + } + neon_store_reg64(tmp, a->vd + 1); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], false); +} + +static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + }; + return do_vshll_2sh(s, a, widenfn[a->size], true); +} + +static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, + NeonGenTwoSingleOpFn *fn) +{ + /* FP operations in 2-reg-and-shift group */ + TCGv_i32 tmp, shiftv; + TCGv_ptr fpstatus; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm | a->vd) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpstatus = get_fpstatus_ptr(1); + shiftv = tcg_const_i32(a->shift); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + tmp = neon_load_reg(a->vm, pass); + fn(tmp, tmp, shiftv, fpstatus); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_ptr(fpstatus); + tcg_temp_free_i32(shiftv); + return true; +} + +#define DO_FP_2SH(INSN, FUNC) \ + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ + { \ + return do_fp_2sh(s, a, FUNC); \ + } + +DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) +DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) +DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) +DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) + +static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) +{ + /* + * Expand the encoded constant. + * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. + * We choose to not special-case this and will behave as if a + * valid constant encoding of 0 had been given. + * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. + */ + switch (cmode) { + case 0: case 1: + /* no-op */ + break; + case 2: case 3: + imm <<= 8; + break; + case 4: case 5: + imm <<= 16; + break; + case 6: case 7: + imm <<= 24; + break; + case 8: case 9: + imm |= imm << 16; + break; + case 10: case 11: + imm = (imm << 8) | (imm << 24); + break; + case 12: + imm = (imm << 8) | 0xff; + break; + case 13: + imm = (imm << 16) | 0xffff; + break; + case 14: + if (op) { + /* + * This is the only case where the top and bottom 32 bits + * of the encoded constant differ. + */ + uint64_t imm64 = 0; + int n; + + for (n = 0; n < 8; n++) { + if (imm & (1 << n)) { + imm64 |= (0xffULL << (n * 8)); + } + } + return imm64; + } + imm |= (imm << 8) | (imm << 16) | (imm << 24); + break; + case 15: + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); + break; + } + if (op) { + imm = ~imm; + } + return dup_const(MO_32, imm); +} + +static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, + GVecGen2iFn *fn) +{ + uint64_t imm; + int reg_ofs, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + reg_ofs = neon_reg_offset(a->vd, 0); + vec_size = a->q ? 16 : 8; + imm = asimd_imm_const(a->imm, a->cmode, a->op); + + fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); + return true; +} + +static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); +} + +static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) +{ + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ + GVecGen2iFn *fn; + + if ((a->cmode & 1) && a->cmode < 12) { + /* for op=1, the imm will be inverted, so BIC becomes AND. */ + fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; + } else { + /* There is one unallocated cmode/op combination in this space */ + if (a->cmode == 15 && a->op == 1) { + return false; + } + fn = gen_VMOV_1r; + } + return do_1reg_imm(s, a, fn); +} + +static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, + NeonGenWidenFn *widenfn, + NeonGenTwo64OpFn *opfn, + bool src1_wide) +{ + /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ + TCGv_i64 rn0_64, rn1_64, rm_64; + TCGv_i32 rm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!widenfn || !opfn) { + /* size == 3 case, which is an entirely different insn group */ + return false; + } + + if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rn0_64 = tcg_temp_new_i64(); + rn1_64 = tcg_temp_new_i64(); + rm_64 = tcg_temp_new_i64(); + + if (src1_wide) { + neon_load_reg64(rn0_64, a->vn); + } else { + TCGv_i32 tmp = neon_load_reg(a->vn, 0); + widenfn(rn0_64, tmp); + tcg_temp_free_i32(tmp); + } + rm = neon_load_reg(a->vm, 0); + + widenfn(rm_64, rm); + tcg_temp_free_i32(rm); + opfn(rn0_64, rn0_64, rm_64); + + /* + * Load second pass inputs before storing the first pass result, to + * avoid incorrect results if a narrow input overlaps with the result. + */ + if (src1_wide) { + neon_load_reg64(rn1_64, a->vn + 1); + } else { + TCGv_i32 tmp = neon_load_reg(a->vn, 1); + widenfn(rn1_64, tmp); + tcg_temp_free_i32(tmp); + } + rm = neon_load_reg(a->vm, 1); + + neon_store_reg64(rn0_64, a->vd); + + widenfn(rm_64, rm); + tcg_temp_free_i32(rm); + opfn(rn1_64, rn1_64, rm_64); + neon_store_reg64(rn1_64, a->vd + 1); + + tcg_temp_free_i64(rn0_64); + tcg_temp_free_i64(rn1_64); + tcg_temp_free_i64(rm_64); + + return true; +} + +#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + static NeonGenWidenFn * const widenfn[] = { \ + gen_helper_neon_widen_##S##8, \ + gen_helper_neon_widen_##S##16, \ + tcg_gen_##EXT##_i32_i64, \ + NULL, \ + }; \ + static NeonGenTwo64OpFn * const addfn[] = { \ + gen_helper_neon_##OP##l_u16, \ + gen_helper_neon_##OP##l_u32, \ + tcg_gen_##OP##_i64, \ + NULL, \ + }; \ + return do_prewiden_3d(s, a, widenfn[a->size], \ + addfn[a->size], SRC1WIDE); \ + } + +DO_PREWIDEN(VADDL_S, s, ext, add, false) +DO_PREWIDEN(VADDL_U, u, extu, add, false) +DO_PREWIDEN(VSUBL_S, s, ext, sub, false) +DO_PREWIDEN(VSUBL_U, u, extu, sub, false) +DO_PREWIDEN(VADDW_S, s, ext, add, true) +DO_PREWIDEN(VADDW_U, u, extu, add, true) +DO_PREWIDEN(VSUBW_S, s, ext, sub, true) +DO_PREWIDEN(VSUBW_U, u, extu, sub, true) + +static bool do_narrow_3d(DisasContext *s, arg_3diff *a, + NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) +{ + /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */ + TCGv_i64 rn_64, rm_64; + TCGv_i32 rd0, rd1; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn || !narrowfn) { + /* size == 3 case, which is an entirely different insn group */ + return false; + } + + if ((a->vn | a->vm) & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rn_64 = tcg_temp_new_i64(); + rm_64 = tcg_temp_new_i64(); + rd0 = tcg_temp_new_i32(); + rd1 = tcg_temp_new_i32(); + + neon_load_reg64(rn_64, a->vn); + neon_load_reg64(rm_64, a->vm); + + opfn(rn_64, rn_64, rm_64); + + narrowfn(rd0, rn_64); + + neon_load_reg64(rn_64, a->vn + 1); + neon_load_reg64(rm_64, a->vm + 1); + + opfn(rn_64, rn_64, rm_64); + + narrowfn(rd1, rn_64); + + neon_store_reg(a->vd, 0, rd0); + neon_store_reg(a->vd, 1, rd1); + + tcg_temp_free_i64(rn_64); + tcg_temp_free_i64(rm_64); + + return true; +} + +#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + static NeonGenTwo64OpFn * const addfn[] = { \ + gen_helper_neon_##OP##l_u16, \ + gen_helper_neon_##OP##l_u32, \ + tcg_gen_##OP##_i64, \ + NULL, \ + }; \ + static NeonGenNarrowFn * const narrowfn[] = { \ + gen_helper_neon_##NARROWTYPE##_high_u8, \ + gen_helper_neon_##NARROWTYPE##_high_u16, \ + EXTOP, \ + NULL, \ + }; \ + return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \ + } + +static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn) +{ + tcg_gen_addi_i64(rn, rn, 1u << 31); + tcg_gen_extrh_i64_i32(rd, rn); +} + +DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) +DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) +DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) +DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) + +static bool do_long_3d(DisasContext *s, arg_3diff *a, + NeonGenTwoOpWidenFn *opfn, + NeonGenTwo64OpFn *accfn) +{ + /* + * 3-regs different lengths, long operations. + * These perform an operation on two inputs that returns a double-width + * result, and then possibly perform an accumulation operation of + * that result into the double-width destination. + */ + TCGv_i64 rd0, rd1, tmp; + TCGv_i32 rn, rm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn) { + /* size == 3 case, which is an entirely different insn group */ + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rd0 = tcg_temp_new_i64(); + rd1 = tcg_temp_new_i64(); + + rn = neon_load_reg(a->vn, 0); + rm = neon_load_reg(a->vm, 0); + opfn(rd0, rn, rm); + tcg_temp_free_i32(rn); + tcg_temp_free_i32(rm); + + rn = neon_load_reg(a->vn, 1); + rm = neon_load_reg(a->vm, 1); + opfn(rd1, rn, rm); + tcg_temp_free_i32(rn); + tcg_temp_free_i32(rm); + + /* Don't store results until after all loads: they might overlap */ + if (accfn) { + tmp = tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vd); + accfn(tmp, tmp, rd0); + neon_store_reg64(tmp, a->vd); + neon_load_reg64(tmp, a->vd + 1); + accfn(tmp, tmp, rd1); + neon_store_reg64(tmp, a->vd + 1); + tcg_temp_free_i64(tmp); + } else { + neon_store_reg64(rd0, a->vd); + neon_store_reg64(rd1, a->vd + 1); + } + + tcg_temp_free_i64(rd0); + tcg_temp_free_i64(rd1); + + return true; +} + +static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_abdl_s16, + gen_helper_neon_abdl_s32, + gen_helper_neon_abdl_s64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_abdl_u16, + gen_helper_neon_abdl_u32, + gen_helper_neon_abdl_u64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_abdl_s16, + gen_helper_neon_abdl_s32, + gen_helper_neon_abdl_s64, + NULL, + }; + static NeonGenTwo64OpFn * const addfn[] = { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); +} + +static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_abdl_u16, + gen_helper_neon_abdl_u32, + gen_helper_neon_abdl_u64, + NULL, + }; + static NeonGenTwo64OpFn * const addfn[] = { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], addfn[a->size]); +} + +static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + TCGv_i32 lo = tcg_temp_new_i32(); + TCGv_i32 hi = tcg_temp_new_i32(); + + tcg_gen_muls2_i32(lo, hi, rn, rm); + tcg_gen_concat_i32_i64(rd, lo, hi); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); +} + +static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + TCGv_i32 lo = tcg_temp_new_i32(); + TCGv_i32 hi = tcg_temp_new_i32(); + + tcg_gen_mulu2_i32(lo, hi, rn, rm); + tcg_gen_concat_i32_i64(rd, lo, hi); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); +} + +static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_mull_s8, + gen_helper_neon_mull_s16, + gen_mull_s32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + gen_helper_neon_mull_u8, + gen_helper_neon_mull_u16, + gen_mull_u32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +#define DO_VMLAL(INSN,MULL,ACC) \ + static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ + { \ + static NeonGenTwoOpWidenFn * const opfn[] = { \ + gen_helper_neon_##MULL##8, \ + gen_helper_neon_##MULL##16, \ + gen_##MULL##32, \ + NULL, \ + }; \ + static NeonGenTwo64OpFn * const accfn[] = { \ + gen_helper_neon_##ACC##l_u16, \ + gen_helper_neon_##ACC##l_u32, \ + tcg_gen_##ACC##_i64, \ + NULL, \ + }; \ + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \ + } + +DO_VMLAL(VMLAL_S,mull_s,add) +DO_VMLAL(VMLAL_U,mull_u,add) +DO_VMLAL(VMLSL_S,mull_s,sub) +DO_VMLAL(VMLSL_U,mull_u,sub) + +static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + gen_helper_neon_mull_s16(rd, rn, rm); + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); +} + +static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) +{ + gen_mull_s32(rd, rn, rm); + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); +} + +static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], NULL); +} + +static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); +} + +static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); +} + +static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + NULL, + gen_VQDMLAL_acc_16, + gen_VQDMLAL_acc_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); +} + +static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + gen_helper_neon_negl_u32(rm, rm); + gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); +} + +static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_neg_i64(rm, rm); + gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); +} + +static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + NULL, + gen_VQDMLSL_acc_16, + gen_VQDMLSL_acc_32, + NULL, + }; + + return do_long_3d(s, a, opfn[a->size], accfn[a->size]); +} + +static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) +{ + gen_helper_gvec_3 *fn_gvec; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + switch (a->size) { + case 0: + fn_gvec = gen_helper_neon_pmull_h; + break; + case 2: + if (!dc_isar_feature(aa32_pmull, s)) { + return false; + } + fn_gvec = gen_helper_gvec_pmull_q; + break; + default: + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), + neon_reg_offset(a->vn, 0), + neon_reg_offset(a->vm, 0), + 16, 16, 0, fn_gvec); + return true; +} + +static void gen_neon_dup_low16(TCGv_i32 var) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_ext16u_i32(var, var); + tcg_gen_shli_i32(tmp, var, 16); + tcg_gen_or_i32(var, var, tmp); + tcg_temp_free_i32(tmp); +} + +static void gen_neon_dup_high16(TCGv_i32 var) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(var, var, 0xffff0000); + tcg_gen_shri_i32(tmp, var, 16); + tcg_gen_or_i32(var, var, tmp); + tcg_temp_free_i32(tmp); +} + +static inline TCGv_i32 neon_get_scalar(int size, int reg) +{ + TCGv_i32 tmp; + if (size == 1) { + tmp = neon_load_reg(reg & 7, reg >> 4); + if (reg & 8) { + gen_neon_dup_high16(tmp); + } else { + gen_neon_dup_low16(tmp); + } + } else { + tmp = neon_load_reg(reg & 15, reg >> 4); + } + return tmp; +} + +static bool do_2scalar(DisasContext *s, arg_2scalar *a, + NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn) +{ + /* + * Two registers and a scalar: perform an operation between + * the input elements and the scalar, and then possibly + * perform an accumulation operation of that result into the + * destination. + */ + TCGv_i32 scalar; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn) { + /* Bad size (including size == 3, which is a different insn group) */ + return false; + } + + if (a->q && ((a->vd | a->vn) & 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + scalar = neon_get_scalar(a->size, a->vm); + + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vn, pass); + opfn(tmp, tmp, scalar); + if (accfn) { + TCGv_i32 rd = neon_load_reg(a->vd, pass); + accfn(tmp, rd, tmp); + tcg_temp_free_i32(rd); + } + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_i32(scalar); + return true; +} + +static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + gen_helper_neon_mul_u16, + tcg_gen_mul_i32, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], NULL); +} + +static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + gen_helper_neon_mul_u16, + tcg_gen_mul_i32, + NULL, + }; + static NeonGenTwoOpFn * const accfn[] = { + NULL, + gen_helper_neon_add_u16, + tcg_gen_add_i32, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); +} + +static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + gen_helper_neon_mul_u16, + tcg_gen_mul_i32, + NULL, + }; + static NeonGenTwoOpFn * const accfn[] = { + NULL, + gen_helper_neon_sub_u16, + tcg_gen_sub_i32, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); +} + +/* + * Rather than have a float-specific version of do_2scalar just for + * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into + * a NeonGenTwoOpFn. + */ +#define WRAP_FP_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \ + { \ + TCGv_ptr fpstatus = get_fpstatus_ptr(1); \ + FUNC(rd, rn, rm, fpstatus); \ + tcg_temp_free_ptr(fpstatus); \ + } + +WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls) +WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds) +WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs) + +static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + NULL, /* TODO: fp16 support */ + gen_VMUL_F_mul, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], NULL); +} + +static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + NULL, /* TODO: fp16 support */ + gen_VMUL_F_mul, + NULL, + }; + static NeonGenTwoOpFn * const accfn[] = { + NULL, + NULL, /* TODO: fp16 support */ + gen_VMUL_F_add, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); +} + +static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + NULL, /* TODO: fp16 support */ + gen_VMUL_F_mul, + NULL, + }; + static NeonGenTwoOpFn * const accfn[] = { + NULL, + NULL, /* TODO: fp16 support */ + gen_VMUL_F_sub, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], accfn[a->size]); +} + +WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16) +WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32) +WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16) +WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32) + +static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + gen_VQDMULH_16, + gen_VQDMULH_32, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], NULL); +} + +static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpFn * const opfn[] = { + NULL, + gen_VQRDMULH_16, + gen_VQRDMULH_32, + NULL, + }; + + return do_2scalar(s, a, opfn[a->size], NULL); +} + +static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, + NeonGenThreeOpEnvFn *opfn) +{ + /* + * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn + * performs a kind of fused op-then-accumulate using a helper + * function that takes all of rd, rn and the scalar at once. + */ + TCGv_i32 scalar; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + if (!dc_isar_feature(aa32_rdm, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn) { + /* Bad size (including size == 3, which is a different insn group) */ + return false; + } + + if (a->q && ((a->vd | a->vn) & 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + scalar = neon_get_scalar(a->size, a->vm); + + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 rn = neon_load_reg(a->vn, pass); + TCGv_i32 rd = neon_load_reg(a->vd, pass); + opfn(rd, cpu_env, rn, scalar, rd); + tcg_temp_free_i32(rn); + neon_store_reg(a->vd, pass, rd); + } + tcg_temp_free_i32(scalar); + + return true; +} + +static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenThreeOpEnvFn *opfn[] = { + NULL, + gen_helper_neon_qrdmlah_s16, + gen_helper_neon_qrdmlah_s32, + NULL, + }; + return do_vqrdmlah_2sc(s, a, opfn[a->size]); +} + +static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenThreeOpEnvFn *opfn[] = { + NULL, + gen_helper_neon_qrdmlsh_s16, + gen_helper_neon_qrdmlsh_s32, + NULL, + }; + return do_vqrdmlah_2sc(s, a, opfn[a->size]); +} + +static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, + NeonGenTwoOpWidenFn *opfn, + NeonGenTwo64OpFn *accfn) +{ + /* + * Two registers and a scalar, long operations: perform an + * operation on the input elements and the scalar which produces + * a double-width result, and then possibly perform an accumulation + * operation of that result into the destination. + */ + TCGv_i32 scalar, rn; + TCGv_i64 rn0_64, rn1_64; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!opfn) { + /* Bad size (including size == 3, which is a different insn group) */ + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + scalar = neon_get_scalar(a->size, a->vm); + + /* Load all inputs before writing any outputs, in case of overlap */ + rn = neon_load_reg(a->vn, 0); + rn0_64 = tcg_temp_new_i64(); + opfn(rn0_64, rn, scalar); + tcg_temp_free_i32(rn); + + rn = neon_load_reg(a->vn, 1); + rn1_64 = tcg_temp_new_i64(); + opfn(rn1_64, rn, scalar); + tcg_temp_free_i32(rn); + tcg_temp_free_i32(scalar); + + if (accfn) { + TCGv_i64 t64 = tcg_temp_new_i64(); + neon_load_reg64(t64, a->vd); + accfn(t64, t64, rn0_64); + neon_store_reg64(t64, a->vd); + neon_load_reg64(t64, a->vd + 1); + accfn(t64, t64, rn1_64); + neon_store_reg64(t64, a->vd + 1); + tcg_temp_free_i64(t64); + } else { + neon_store_reg64(rn0_64, a->vd); + neon_store_reg64(rn1_64, a->vd + 1); + } + tcg_temp_free_i64(rn0_64); + tcg_temp_free_i64(rn1_64); + return true; +} + +static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_helper_neon_mull_s16, + gen_mull_s32, + NULL, + }; + + return do_2scalar_long(s, a, opfn[a->size], NULL); +} + +static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_helper_neon_mull_u16, + gen_mull_u32, + NULL, + }; + + return do_2scalar_long(s, a, opfn[a->size], NULL); +} + +#define DO_VMLAL_2SC(INSN, MULL, ACC) \ + static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \ + { \ + static NeonGenTwoOpWidenFn * const opfn[] = { \ + NULL, \ + gen_helper_neon_##MULL##16, \ + gen_##MULL##32, \ + NULL, \ + }; \ + static NeonGenTwo64OpFn * const accfn[] = { \ + NULL, \ + gen_helper_neon_##ACC##l_u32, \ + tcg_gen_##ACC##_i64, \ + NULL, \ + }; \ + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \ + } + +DO_VMLAL_2SC(VMLAL_S, mull_s, add) +DO_VMLAL_2SC(VMLAL_U, mull_u, add) +DO_VMLAL_2SC(VMLSL_S, mull_s, sub) +DO_VMLAL_2SC(VMLSL_U, mull_u, sub) + +static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + + return do_2scalar_long(s, a, opfn[a->size], NULL); +} + +static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + NULL, + gen_VQDMLAL_acc_16, + gen_VQDMLAL_acc_32, + NULL, + }; + + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); +} + +static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a) +{ + static NeonGenTwoOpWidenFn * const opfn[] = { + NULL, + gen_VQDMULL_16, + gen_VQDMULL_32, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + NULL, + gen_VQDMLSL_acc_16, + gen_VQDMLSL_acc_32, + NULL, + }; + + return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); +} + +static bool trans_VEXT(DisasContext *s, arg_VEXT *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if ((a->vn | a->vm | a->vd) & a->q) { + return false; + } + + if (a->imm > 7 && !a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (!a->q) { + /* Extract 64 bits from */ + TCGv_i64 left, right, dest; + + left = tcg_temp_new_i64(); + right = tcg_temp_new_i64(); + dest = tcg_temp_new_i64(); + + neon_load_reg64(right, a->vn); + neon_load_reg64(left, a->vm); + tcg_gen_extract2_i64(dest, right, left, a->imm * 8); + neon_store_reg64(dest, a->vd); + + tcg_temp_free_i64(left); + tcg_temp_free_i64(right); + tcg_temp_free_i64(dest); + } else { + /* Extract 128 bits from */ + TCGv_i64 left, middle, right, destleft, destright; + + left = tcg_temp_new_i64(); + middle = tcg_temp_new_i64(); + right = tcg_temp_new_i64(); + destleft = tcg_temp_new_i64(); + destright = tcg_temp_new_i64(); + + if (a->imm < 8) { + neon_load_reg64(right, a->vn); + neon_load_reg64(middle, a->vn + 1); + tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); + neon_load_reg64(left, a->vm); + tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); + } else { + neon_load_reg64(right, a->vn + 1); + neon_load_reg64(middle, a->vm); + tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); + neon_load_reg64(left, a->vm + 1); + tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); + } + + neon_store_reg64(destright, a->vd); + neon_store_reg64(destleft, a->vd + 1); + + tcg_temp_free_i64(destright); + tcg_temp_free_i64(destleft); + tcg_temp_free_i64(right); + tcg_temp_free_i64(middle); + tcg_temp_free_i64(left); + } + return true; +} + +static bool trans_VTBL(DisasContext *s, arg_VTBL *a) +{ + int n; + TCGv_i32 tmp, tmp2, tmp3, tmp4; + TCGv_ptr ptr1; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + n = a->len + 1; + if ((a->vn + n) > 32) { + /* + * This is UNPREDICTABLE; we choose to UNDEF to avoid the + * helper function running off the end of the register file. + */ + return false; + } + n <<= 3; + if (a->op) { + tmp = neon_load_reg(a->vd, 0); + } else { + tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + } + tmp2 = neon_load_reg(a->vm, 0); + ptr1 = vfp_reg_ptr(true, a->vn); + tmp4 = tcg_const_i32(n); + gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); + tcg_temp_free_i32(tmp); + if (a->op) { + tmp = neon_load_reg(a->vd, 1); + } else { + tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + } + tmp3 = neon_load_reg(a->vm, 1); + gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); + tcg_temp_free_i32(tmp4); + tcg_temp_free_ptr(ptr1); + neon_store_reg(a->vd, 0, tmp2); + neon_store_reg(a->vd, 1, tmp3); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), + neon_element_offset(a->vm, a->index, a->size), + a->q ? 16 : 8, a->q ? 16 : 8); + return true; +} + +static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) +{ + int pass, half; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (a->size == 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { + TCGv_i32 tmp[2]; + + for (half = 0; half < 2; half++) { + tmp[half] = neon_load_reg(a->vm, pass * 2 + half); + switch (a->size) { + case 0: + tcg_gen_bswap32_i32(tmp[half], tmp[half]); + break; + case 1: + gen_swap_half(tmp[half], tmp[half]); + break; + case 2: + break; + default: + g_assert_not_reached(); + } + } + neon_store_reg(a->vd, pass * 2, tmp[1]); + neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); + } + return true; +} + +static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, + NeonGenWidenFn *widenfn, + NeonGenTwo64OpFn *opfn, + NeonGenTwo64OpFn *accfn) +{ + /* + * Pairwise long operations: widen both halves of the pair, + * combine the pairs with the opfn, and then possibly accumulate + * into the destination with the accfn. + */ + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!widenfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass = 0; pass < a->q + 1; pass++) { + TCGv_i32 tmp; + TCGv_i64 rm0_64, rm1_64, rd_64; + + rm0_64 = tcg_temp_new_i64(); + rm1_64 = tcg_temp_new_i64(); + rd_64 = tcg_temp_new_i64(); + tmp = neon_load_reg(a->vm, pass * 2); + widenfn(rm0_64, tmp); + tcg_temp_free_i32(tmp); + tmp = neon_load_reg(a->vm, pass * 2 + 1); + widenfn(rm1_64, tmp); + tcg_temp_free_i32(tmp); + opfn(rd_64, rm0_64, rm1_64); + tcg_temp_free_i64(rm0_64); + tcg_temp_free_i64(rm1_64); + + if (accfn) { + TCGv_i64 tmp64 = tcg_temp_new_i64(); + neon_load_reg64(tmp64, a->vd + pass); + accfn(rd_64, tmp64, rd_64); + tcg_temp_free_i64(tmp64); + } + neon_store_reg64(rd_64, a->vd + pass); + tcg_temp_free_i64(rd_64); + } + return true; +} + +static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] = { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); +} + +static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] = { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); +} + +static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_s8, + gen_helper_neon_widen_s16, + tcg_gen_ext_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] = { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], + accfn[a->size]); +} + +static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) +{ + static NeonGenWidenFn * const widenfn[] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + static NeonGenTwo64OpFn * const opfn[] = { + gen_helper_neon_paddl_u16, + gen_helper_neon_paddl_u32, + tcg_gen_add_i64, + NULL, + }; + static NeonGenTwo64OpFn * const accfn[] = { + gen_helper_neon_addl_u16, + gen_helper_neon_addl_u32, + tcg_gen_add_i64, + NULL, + }; + + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], + accfn[a->size]); +} + +typedef void ZipFn(TCGv_ptr, TCGv_ptr); + +static bool do_zip_uzp(DisasContext *s, arg_2misc *a, + ZipFn *fn) +{ + TCGv_ptr pd, pm; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!fn) { + /* Bad size or size/q combination */ + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + pd = vfp_reg_ptr(true, a->vd); + pm = vfp_reg_ptr(true, a->vm); + fn(pd, pm); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); + return true; +} + +static bool trans_VUZP(DisasContext *s, arg_2misc *a) +{ + static ZipFn * const fn[2][4] = { + { + gen_helper_neon_unzip8, + gen_helper_neon_unzip16, + NULL, + NULL, + }, { + gen_helper_neon_qunzip8, + gen_helper_neon_qunzip16, + gen_helper_neon_qunzip32, + NULL, + } + }; + return do_zip_uzp(s, a, fn[a->q][a->size]); +} + +static bool trans_VZIP(DisasContext *s, arg_2misc *a) +{ + static ZipFn * const fn[2][4] = { + { + gen_helper_neon_zip8, + gen_helper_neon_zip16, + NULL, + NULL, + }, { + gen_helper_neon_qzip8, + gen_helper_neon_qzip16, + gen_helper_neon_qzip32, + NULL, + } + }; + return do_zip_uzp(s, a, fn[a->q][a->size]); +} + +static bool do_vmovn(DisasContext *s, arg_2misc *a, + NeonGenNarrowEnvFn *narrowfn) +{ + TCGv_i64 rm; + TCGv_i32 rd0, rd1; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vm & 1) { + return false; + } + + if (!narrowfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rm = tcg_temp_new_i64(); + rd0 = tcg_temp_new_i32(); + rd1 = tcg_temp_new_i32(); + + neon_load_reg64(rm, a->vm); + narrowfn(rd0, cpu_env, rm); + neon_load_reg64(rm, a->vm + 1); + narrowfn(rd1, cpu_env, rm); + neon_store_reg(a->vd, 0, rd0); + neon_store_reg(a->vd, 1, rd1); + tcg_temp_free_i64(rm); + return true; +} + +#define DO_VMOVN(INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + static NeonGenNarrowEnvFn * const narrowfn[] = { \ + FUNC##8, \ + FUNC##16, \ + FUNC##32, \ + NULL, \ + }; \ + return do_vmovn(s, a, narrowfn[a->size]); \ + } + +DO_VMOVN(VMOVN, gen_neon_narrow_u) +DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) +DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) +DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) + +static bool trans_VSHLL(DisasContext *s, arg_2misc *a) +{ + TCGv_i32 rm0, rm1; + TCGv_i64 rd; + static NeonGenWidenFn * const widenfns[] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + NULL, + }; + NeonGenWidenFn *widenfn = widenfns[a->size]; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->vd & 1) { + return false; + } + + if (!widenfn) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rd = tcg_temp_new_i64(); + + rm0 = neon_load_reg(a->vm, 0); + rm1 = neon_load_reg(a->vm, 1); + + widenfn(rd, rm0); + tcg_gen_shli_i64(rd, rd, 8 << a->size); + neon_store_reg64(rd, a->vd); + widenfn(rd, rm1); + tcg_gen_shli_i64(rd, rd, 8 << a->size); + neon_store_reg64(rd, a->vd + 1); + + tcg_temp_free_i64(rd); + tcg_temp_free_i32(rm0); + tcg_temp_free_i32(rm1); + return true; +} + +static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp, tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vm & 1) || (a->size != 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(true); + ahp = get_ahp_flag(); + tmp = neon_load_reg(a->vm, 0); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp2 = neon_load_reg(a->vm, 1); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_or_i32(tmp2, tmp2, tmp); + tcg_temp_free_i32(tmp); + tmp = neon_load_reg(a->vm, 2); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp3 = neon_load_reg(a->vm, 3); + neon_store_reg(a->vd, 0, tmp2); + gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); + tcg_gen_shli_i32(tmp3, tmp3, 16); + tcg_gen_or_i32(tmp3, tmp3, tmp); + neon_store_reg(a->vd, 1, tmp3); + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp, tmp, tmp2, tmp3; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd & 1) || (a->size != 1)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(true); + ahp = get_ahp_flag(); + tmp3 = tcg_temp_new_i32(); + tmp = neon_load_reg(a->vm, 0); + tmp2 = neon_load_reg(a->vm, 1); + tcg_gen_ext16u_i32(tmp3, tmp); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(a->vd, 0, tmp3); + tcg_gen_shri_i32(tmp, tmp, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); + neon_store_reg(a->vd, 1, tmp); + tmp3 = tcg_temp_new_i32(); + tcg_gen_ext16u_i32(tmp3, tmp2); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(a->vd, 2, tmp3); + tcg_gen_shri_i32(tmp2, tmp2, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); + neon_store_reg(a->vd, 3, tmp2); + tcg_temp_free_i32(ahp); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) +{ + int vec_size = a->q ? 16 : 8; + int rd_ofs = neon_reg_offset(a->vd, 0); + int rm_ofs = neon_reg_offset(a->vm, 0); + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size == 3) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size); + + return true; +} + +#define DO_2MISC_VEC(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_vec(s, a, FN); \ + } + +DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg) +DO_2MISC_VEC(VABS, tcg_gen_gvec_abs) +DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0) +DO_2MISC_VEC(VCGT0, gen_gvec_cgt0) +DO_2MISC_VEC(VCLE0, gen_gvec_cle0) +DO_2MISC_VEC(VCGE0, gen_gvec_cge0) +DO_2MISC_VEC(VCLT0, gen_gvec_clt0) + +static bool trans_VMVN(DisasContext *s, arg_2misc *a) +{ + if (a->size != 0) { + return false; + } + return do_2misc_vec(s, a, tcg_gen_gvec_not); +} + +#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \ + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ + uint32_t rm_ofs, uint32_t oprsz, \ + uint32_t maxsz) \ + { \ + tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \ + DATA, FUNC); \ + } + +#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \ + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ + uint32_t rm_ofs, uint32_t oprsz, \ + uint32_t maxsz) \ + { \ + tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \ + } + +WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0) +WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1) +WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0) +WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1) +WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0) +WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0) +WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0) + +#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \ + return false; \ + } \ + return do_2misc_vec(s, a, gen_##INSN); \ + } + +DO_2M_CRYPTO(AESE, aa32_aes, 0) +DO_2M_CRYPTO(AESD, aa32_aes, 0) +DO_2M_CRYPTO(AESMC, aa32_aes, 0) +DO_2M_CRYPTO(AESIMC, aa32_aes, 0) +DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) +DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) +DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) + +static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) +{ + int pass; + + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!fn) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vm, pass); + fn(tmp, tmp); + neon_store_reg(a->vd, pass, tmp); + } + + return true; +} + +static bool trans_VREV32(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] = { + tcg_gen_bswap32_i32, + gen_swap_half, + NULL, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VREV16(DisasContext *s, arg_2misc *a) +{ + if (a->size != 0) { + return false; + } + return do_2misc(s, a, gen_rev16); +} + +static bool trans_VCLS(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] = { + gen_helper_neon_cls_s8, + gen_helper_neon_cls_s16, + gen_helper_neon_cls_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm) +{ + tcg_gen_clzi_i32(rd, rm, 32); +} + +static bool trans_VCLZ(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] = { + gen_helper_neon_clz_u8, + gen_helper_neon_clz_u16, + do_VCLZ_32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VCNT(DisasContext *s, arg_2misc *a) +{ + if (a->size != 0) { + return false; + } + return do_2misc(s, a, gen_helper_neon_cnt_u8); +} + +static bool trans_VABS_F(DisasContext *s, arg_2misc *a) +{ + if (a->size != 2) { + return false; + } + /* TODO: FP16 : size == 1 */ + return do_2misc(s, a, gen_helper_vfp_abss); +} + +static bool trans_VNEG_F(DisasContext *s, arg_2misc *a) +{ + if (a->size != 2) { + return false; + } + /* TODO: FP16 : size == 1 */ + return do_2misc(s, a, gen_helper_vfp_negs); +} + +static bool trans_VRECPE(DisasContext *s, arg_2misc *a) +{ + if (a->size != 2) { + return false; + } + return do_2misc(s, a, gen_helper_recpe_u32); +} + +static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) +{ + if (a->size != 2) { + return false; + } + return do_2misc(s, a, gen_helper_rsqrte_u32); +} + +#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ + { \ + FUNC(d, cpu_env, m); \ + } + +WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) +WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16) +WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32) +WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8) +WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16) +WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32) + +static bool trans_VQABS(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] = { + gen_VQABS_s8, + gen_VQABS_s16, + gen_VQABS_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool trans_VQNEG(DisasContext *s, arg_2misc *a) +{ + static NeonGenOneOpFn * const fn[] = { + gen_VQNEG_s8, + gen_VQNEG_s16, + gen_VQNEG_s32, + NULL, + }; + return do_2misc(s, a, fn[a->size]); +} + +static bool do_2misc_fp(DisasContext *s, arg_2misc *a, + NeonGenOneSingleOpFn *fn) +{ + int pass; + TCGv_ptr fpst; + + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size != 2) { + /* TODO: FP16 will be the size == 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(1); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vm, pass); + fn(tmp, tmp, fpst); + neon_store_reg(a->vd, pass, tmp); + } + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_2MISC_FP(INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_fp(s, a, FUNC); \ + } + +DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32) +DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32) +DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos) +DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos) +DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs) +DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs) + +static bool trans_VRINTX(DisasContext *s, arg_2misc *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + return do_2misc_fp(s, a, gen_helper_rints_exact); +} + +#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ + { \ + TCGv_i32 zero = tcg_const_i32(0); \ + FUNC(d, m, zero, fpst); \ + tcg_temp_free_i32(zero); \ + } +#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \ + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ + { \ + TCGv_i32 zero = tcg_const_i32(0); \ + FUNC(d, zero, m, fpst); \ + tcg_temp_free_i32(zero); \ + } + +#define DO_FP_CMP0(INSN, FUNC, REV) \ + WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_2misc_fp(s, a, gen_##INSN); \ + } + +DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD) +DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) +DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) +DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) +DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) + +static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode) +{ + /* + * Handle a VRINT* operation by iterating 32 bits at a time, + * with a specified rounding mode in operation. + */ + int pass; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size != 2) { + /* TODO: FP16 will be the size == 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(1); + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vm, pass); + gen_helper_rints(tmp, tmp, fpst); + neon_store_reg(a->vd, pass, tmp); + } + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_VRINT(INSN, RMODE) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_vrint(s, a, RMODE); \ + } + +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) +DO_VRINT(VRINTZ, FPROUNDING_ZERO) +DO_VRINT(VRINTM, FPROUNDING_NEGINF) +DO_VRINT(VRINTP, FPROUNDING_POSINF) + +static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed) +{ + /* + * Handle a VCVT* operation by iterating 32 bits at a time, + * with a specified rounding mode in operation. + */ + int pass; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode, tcg_shift; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size != 2) { + /* TODO: FP16 will be the size == 1 case */ + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(1); + tcg_shift = tcg_const_i32(0); + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + TCGv_i32 tmp = neon_load_reg(a->vm, pass); + if (is_signed) { + gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst); + } else { + gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst); + } + neon_store_reg(a->vd, pass, tmp); + } + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_i32(tcg_shift); + tcg_temp_free_ptr(fpst); + + return true; +} + +#define DO_VCVT(INSN, RMODE, SIGNED) \ + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ + { \ + return do_vcvt(s, a, RMODE, SIGNED); \ + } + +DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false) +DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true) +DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false) +DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true) +DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) +DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) +DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) +DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) + +static bool trans_VSWP(DisasContext *s, arg_2misc *a) +{ + TCGv_i64 rm, rd; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (a->size != 0) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + rm = tcg_temp_new_i64(); + rd = tcg_temp_new_i64(); + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { + neon_load_reg64(rm, a->vm + pass); + neon_load_reg64(rd, a->vd + pass); + neon_store_reg64(rm, a->vd + pass); + neon_store_reg64(rd, a->vm + pass); + } + tcg_temp_free_i64(rm); + tcg_temp_free_i64(rd); + + return true; +} +static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 rd, tmp; + + rd = tcg_temp_new_i32(); + tmp = tcg_temp_new_i32(); + + tcg_gen_shli_i32(rd, t0, 8); + tcg_gen_andi_i32(rd, rd, 0xff00ff00); + tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); + tcg_gen_or_i32(rd, rd, tmp); + + tcg_gen_shri_i32(t1, t1, 8); + tcg_gen_andi_i32(t1, t1, 0x00ff00ff); + tcg_gen_andi_i32(tmp, t0, 0xff00ff00); + tcg_gen_or_i32(t1, t1, tmp); + tcg_gen_mov_i32(t0, rd); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(rd); +} + +static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 rd, tmp; + + rd = tcg_temp_new_i32(); + tmp = tcg_temp_new_i32(); + + tcg_gen_shli_i32(rd, t0, 16); + tcg_gen_andi_i32(tmp, t1, 0xffff); + tcg_gen_or_i32(rd, rd, tmp); + tcg_gen_shri_i32(t1, t1, 16); + tcg_gen_andi_i32(tmp, t0, 0xffff0000); + tcg_gen_or_i32(t1, t1, tmp); + tcg_gen_mov_i32(t0, rd); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(rd); +} + +static bool trans_VTRN(DisasContext *s, arg_2misc *a) +{ + TCGv_i32 tmp, tmp2; + int pass; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vm) & 0x10)) { + return false; + } + + if ((a->vd | a->vm) & a->q) { + return false; + } + + if (a->size == 3) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (a->size == 2) { + for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { + tmp = neon_load_reg(a->vm, pass); + tmp2 = neon_load_reg(a->vd, pass + 1); + neon_store_reg(a->vm, pass, tmp2); + neon_store_reg(a->vd, pass + 1, tmp); + } + } else { + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { + tmp = neon_load_reg(a->vm, pass); + tmp2 = neon_load_reg(a->vd, pass); + if (a->size == 0) { + gen_neon_trn_u8(tmp, tmp2); + } else { + gen_neon_trn_u16(tmp, tmp2); + } + neon_store_reg(a->vm, pass, tmp2); + neon_store_reg(a->vd, pass, tmp); + } + } + return true; +} diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c deleted file mode 100644 index f6cb921573..0000000000 --- a/target/arm/translate-neon.inc.c +++ /dev/null @@ -1,4161 +0,0 @@ -/* - * ARM translation: AArch32 Neon instructions - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2005-2007 CodeSourcery - * Copyright (c) 2007 OpenedHand, Ltd. - * Copyright (c) 2020 Linaro, Ltd. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ - -static inline int plus1(DisasContext *s, int x) -{ - return x + 1; -} - -static inline int rsub_64(DisasContext *s, int x) -{ - return 64 - x; -} - -static inline int rsub_32(DisasContext *s, int x) -{ - return 32 - x; -} -static inline int rsub_16(DisasContext *s, int x) -{ - return 16 - x; -} -static inline int rsub_8(DisasContext *s, int x) -{ - return 8 - x; -} - -/* Include the generated Neon decoder */ -#include "decode-neon-dp.inc.c" -#include "decode-neon-ls.inc.c" -#include "decode-neon-shared.inc.c" - -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, - * where 0 is the least significant end of the register. - */ -static inline long -neon_element_offset(int reg, int element, MemOp size) -{ - int element_size = 1 << size; - int ofs = element * element_size; -#ifdef HOST_WORDS_BIGENDIAN - /* Calculate the offset assuming fully little-endian, - * then XOR to account for the order of the 8-byte units. - */ - if (element_size < 8) { - ofs ^= 8 - element_size; - } -#endif - return neon_reg_offset(reg, 0) + ofs; -} - -static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) -{ - long offset = neon_element_offset(reg, ele, mop & MO_SIZE); - - switch (mop) { - case MO_UB: - tcg_gen_ld8u_i32(var, cpu_env, offset); - break; - case MO_UW: - tcg_gen_ld16u_i32(var, cpu_env, offset); - break; - case MO_UL: - tcg_gen_ld_i32(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) -{ - long offset = neon_element_offset(reg, ele, mop & MO_SIZE); - - switch (mop) { - case MO_UB: - tcg_gen_ld8u_i64(var, cpu_env, offset); - break; - case MO_UW: - tcg_gen_ld16u_i64(var, cpu_env, offset); - break; - case MO_UL: - tcg_gen_ld32u_i64(var, cpu_env, offset); - break; - case MO_Q: - tcg_gen_ld_i64(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) -{ - long offset = neon_element_offset(reg, ele, size); - - switch (size) { - case MO_8: - tcg_gen_st8_i32(var, cpu_env, offset); - break; - case MO_16: - tcg_gen_st16_i32(var, cpu_env, offset); - break; - case MO_32: - tcg_gen_st_i32(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) -{ - long offset = neon_element_offset(reg, ele, size); - - switch (size) { - case MO_8: - tcg_gen_st8_i64(var, cpu_env, offset); - break; - case MO_16: - tcg_gen_st16_i64(var, cpu_env, offset); - break; - case MO_32: - tcg_gen_st32_i64(var, cpu_env, offset); - break; - case MO_64: - tcg_gen_st_i64(var, cpu_env, offset); - break; - default: - g_assert_not_reached(); - } -} - -static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) -{ - int opr_sz; - TCGv_ptr fpst; - gen_helper_gvec_3_ptr *fn_gvec_ptr; - - if (!dc_isar_feature(aa32_vcma, s) - || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - opr_sz = (1 + a->q) * 8; - fpst = get_fpstatus_ptr(1); - fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - fpst, opr_sz, opr_sz, a->rot, - fn_gvec_ptr); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCADD(DisasContext *s, arg_VCADD *a) -{ - int opr_sz; - TCGv_ptr fpst; - gen_helper_gvec_3_ptr *fn_gvec_ptr; - - if (!dc_isar_feature(aa32_vcma, s) - || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - opr_sz = (1 + a->q) * 8; - fpst = get_fpstatus_ptr(1); - fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - fpst, opr_sz, opr_sz, a->rot, - fn_gvec_ptr); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VDOT(DisasContext *s, arg_VDOT *a) -{ - int opr_sz; - gen_helper_gvec_3 *fn_gvec; - - if (!dc_isar_feature(aa32_dp, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - opr_sz = (1 + a->q) * 8; - fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; - tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - opr_sz, opr_sz, 0, fn_gvec); - return true; -} - -static bool trans_VFML(DisasContext *s, arg_VFML *a) -{ - int opr_sz; - - if (!dc_isar_feature(aa32_fhm, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - (a->vd & 0x10)) { - return false; - } - - if (a->vd & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - opr_sz = (1 + a->q) * 8; - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(a->q, a->vn), - vfp_reg_offset(a->q, a->vm), - cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */ - gen_helper_gvec_fmlal_a32); - return true; -} - -static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) -{ - gen_helper_gvec_3_ptr *fn_gvec_ptr; - int opr_sz; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_vcma, s)) { - return false; - } - if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vn) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx - : gen_helper_gvec_fcmlah_idx); - opr_sz = (1 + a->q) * 8; - fpst = get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - fpst, opr_sz, opr_sz, - (a->index << 2) | a->rot, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a) -{ - gen_helper_gvec_3 *fn_gvec; - int opr_sz; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_dp, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn) & 0x10)) { - return false; - } - - if ((a->vd | a->vn) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b; - opr_sz = (1 + a->q) * 8; - fpst = get_fpstatus_ptr(1); - tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->rm), - opr_sz, opr_sz, a->index, fn_gvec); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) -{ - int opr_sz; - - if (!dc_isar_feature(aa32_fhm, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) { - return false; - } - - if (a->vd & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - opr_sz = (1 + a->q) * 8; - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(a->q, a->vn), - vfp_reg_offset(a->q, a->rm), - cpu_env, opr_sz, opr_sz, - (a->index << 2) | a->s, /* is_2 == 0 */ - gen_helper_gvec_fmlal_idx_a32); - return true; -} - -static struct { - int nregs; - int interleave; - int spacing; -} const neon_ls_element_type[11] = { - {1, 4, 1}, - {1, 4, 2}, - {4, 1, 1}, - {2, 2, 2}, - {1, 3, 1}, - {1, 3, 2}, - {3, 1, 1}, - {1, 1, 1}, - {1, 2, 1}, - {1, 2, 2}, - {2, 1, 1} -}; - -static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn, - int stride) -{ - if (rm != 15) { - TCGv_i32 base; - - base = load_reg(s, rn); - if (rm == 13) { - tcg_gen_addi_i32(base, base, stride); - } else { - TCGv_i32 index; - index = load_reg(s, rm); - tcg_gen_add_i32(base, base, index); - tcg_temp_free_i32(index); - } - store_reg(s, rn, base); - } -} - -static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) -{ - /* Neon load/store multiple structures */ - int nregs, interleave, spacing, reg, n; - MemOp endian = s->be_data; - int mmu_idx = get_mem_index(s); - int size = a->size; - TCGv_i64 tmp64; - TCGv_i32 addr, tmp; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - if (a->itype > 10) { - return false; - } - /* Catch UNDEF cases for bad values of align field */ - switch (a->itype & 0xc) { - case 4: - if (a->align >= 2) { - return false; - } - break; - case 8: - if (a->align == 3) { - return false; - } - break; - default: - break; - } - nregs = neon_ls_element_type[a->itype].nregs; - interleave = neon_ls_element_type[a->itype].interleave; - spacing = neon_ls_element_type[a->itype].spacing; - if (size == 3 && (interleave | spacing) != 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* For our purposes, bytes are always little-endian. */ - if (size == 0) { - endian = MO_LE; - } - /* - * Consecutive little-endian elements from a single register - * can be promoted to a larger little-endian operation. - */ - if (interleave == 1 && endian == MO_LE) { - size = 3; - } - tmp64 = tcg_temp_new_i64(); - addr = tcg_temp_new_i32(); - tmp = tcg_const_i32(1 << size); - load_reg_var(s, addr, a->rn); - for (reg = 0; reg < nregs; reg++) { - for (n = 0; n < 8 >> size; n++) { - int xs; - for (xs = 0; xs < interleave; xs++) { - int tt = a->vd + reg + spacing * xs; - - if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); - neon_store_element64(tt, n, size, tmp64); - } else { - neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); - } - tcg_gen_add_i32(addr, addr, tmp); - } - } - } - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - tcg_temp_free_i64(tmp64); - - gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); - return true; -} - -static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) -{ - /* Neon load single structure to all lanes */ - int reg, stride, vec_size; - int vd = a->vd; - int size = a->size; - int nregs = a->n + 1; - TCGv_i32 addr, tmp; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (size == 3) { - if (nregs != 4 || a->a == 0) { - return false; - } - /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ - size = 2; - } - if (nregs == 1 && a->a == 1 && size == 0) { - return false; - } - if (nregs == 3 && a->a == 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * VLD1 to all lanes: T bit indicates how many Dregs to write. - * VLD2/3/4 to all lanes: T bit indicates register stride. - */ - stride = a->t ? 2 : 1; - vec_size = nregs == 1 ? stride * 8 : 8; - - tmp = tcg_temp_new_i32(); - addr = tcg_temp_new_i32(); - load_reg_var(s, addr, a->rn); - for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); - if ((vd & 1) && vec_size == 16) { - /* - * We cannot write 16 bytes at once because the - * destination is unaligned. - */ - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), - 8, 8, tmp); - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), - neon_reg_offset(vd, 0), 8, 8); - } else { - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), - vec_size, vec_size, tmp); - } - tcg_gen_addi_i32(addr, addr, 1 << size); - vd += stride; - } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - - gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs); - - return true; -} - -static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) -{ - /* Neon load/store single structure to one lane */ - int reg; - int nregs = a->n + 1; - int vd = a->vd; - TCGv_i32 addr, tmp; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - /* Catch the UNDEF cases. This is unavoidably a bit messy. */ - switch (nregs) { - case 1: - if (((a->align & (1 << a->size)) != 0) || - (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { - return false; - } - break; - case 3: - if ((a->align & 1) != 0) { - return false; - } - /* fall through */ - case 2: - if (a->size == 2 && (a->align & 2) != 0) { - return false; - } - break; - case 4: - if ((a->size == 2) && ((a->align & 3) == 3)) { - return false; - } - break; - default: - abort(); - } - if ((vd + a->stride * (nregs - 1)) > 31) { - /* - * Attempts to write off the end of the register file are - * UNPREDICTABLE; we choose to UNDEF because otherwise we would - * access off the end of the array that holds the register data. - */ - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i32(); - addr = tcg_temp_new_i32(); - load_reg_var(s, addr, a->rn); - /* - * TODO: if we implemented alignment exceptions, we should check - * addr against the alignment encoded in a->align here. - */ - for (reg = 0; reg < nregs; reg++) { - if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); - neon_store_element(vd, a->reg_idx, a->size, tmp); - } else { /* Store */ - neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); - } - vd += a->stride; - tcg_gen_addi_i32(addr, addr, 1 << a->size); - } - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - - gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs); - - return true; -} - -static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) -{ - int vec_size = a->q ? 16 : 8; - int rd_ofs = neon_reg_offset(a->vd, 0); - int rn_ofs = neon_reg_offset(a->vn, 0); - int rm_ofs = neon_reg_offset(a->vm, 0); - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); - return true; -} - -#define DO_3SAME(INSN, FUNC) \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - return do_3same(s, a, FUNC); \ - } - -DO_3SAME(VADD, tcg_gen_gvec_add) -DO_3SAME(VSUB, tcg_gen_gvec_sub) -DO_3SAME(VAND, tcg_gen_gvec_and) -DO_3SAME(VBIC, tcg_gen_gvec_andc) -DO_3SAME(VORR, tcg_gen_gvec_or) -DO_3SAME(VORN, tcg_gen_gvec_orc) -DO_3SAME(VEOR, tcg_gen_gvec_xor) -DO_3SAME(VSHL_S, gen_gvec_sshl) -DO_3SAME(VSHL_U, gen_gvec_ushl) -DO_3SAME(VQADD_S, gen_gvec_sqadd_qc) -DO_3SAME(VQADD_U, gen_gvec_uqadd_qc) -DO_3SAME(VQSUB_S, gen_gvec_sqsub_qc) -DO_3SAME(VQSUB_U, gen_gvec_uqsub_qc) - -/* These insns are all gvec_bitsel but with the inputs in various orders. */ -#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \ - } \ - DO_3SAME(INSN, gen_##INSN##_3s) - -DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs) -DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs) -DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs) - -#define DO_3SAME_NO_SZ_3(INSN, FUNC) \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size == 3) { \ - return false; \ - } \ - return do_3same(s, a, FUNC); \ - } - -DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) -DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) -DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) -DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) -DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul) -DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla) -DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls) -DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst) -DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd) -DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba) -DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd) -DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba) - -#define DO_3SAME_CMP(INSN, COND) \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \ - } \ - DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s) - -DO_3SAME_CMP(VCGT_S, TCG_COND_GT) -DO_3SAME_CMP(VCGT_U, TCG_COND_GTU) -DO_3SAME_CMP(VCGE_S, TCG_COND_GE) -DO_3SAME_CMP(VCGE_U, TCG_COND_GEU) -DO_3SAME_CMP(VCEQ, TCG_COND_EQ) - -#define WRAP_OOL_FN(WRAPNAME, FUNC) \ - static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \ - uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \ - { \ - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \ - } - -WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b) - -static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) -{ - if (a->size != 0) { - return false; - } - return do_3same(s, a, gen_VMUL_p_3s); -} - -#define DO_VQRDMLAH(INSN, FUNC) \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (!dc_isar_feature(aa32_rdm, s)) { \ - return false; \ - } \ - if (a->size != 1 && a->size != 2) { \ - return false; \ - } \ - return do_3same(s, a, FUNC); \ - } - -DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) -DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) - -#define DO_SHA1(NAME, FUNC) \ - WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ - static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (!dc_isar_feature(aa32_sha1, s)) { \ - return false; \ - } \ - return do_3same(s, a, gen_##NAME##_3s); \ - } - -DO_SHA1(SHA1C, gen_helper_crypto_sha1c) -DO_SHA1(SHA1P, gen_helper_crypto_sha1p) -DO_SHA1(SHA1M, gen_helper_crypto_sha1m) -DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0) - -#define DO_SHA2(NAME, FUNC) \ - WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ - static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (!dc_isar_feature(aa32_sha2, s)) { \ - return false; \ - } \ - return do_3same(s, a, gen_##NAME##_3s); \ - } - -DO_SHA2(SHA256H, gen_helper_crypto_sha256h) -DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2) -DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1) - -#define DO_3SAME_64(INSN, FUNC) \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - static const GVecGen3 op = { .fni8 = FUNC }; \ - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &op); \ - } \ - DO_3SAME(INSN, gen_##INSN##_3s) - -#define DO_3SAME_64_ENV(INSN, FUNC) \ - static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \ - { \ - FUNC(d, cpu_env, n, m); \ - } \ - DO_3SAME_64(INSN, gen_##INSN##_elt) - -DO_3SAME_64(VRSHL_S64, gen_helper_neon_rshl_s64) -DO_3SAME_64(VRSHL_U64, gen_helper_neon_rshl_u64) -DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64) -DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64) -DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64) -DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) - -#define DO_3SAME_32(INSN, FUNC) \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - static const GVecGen3 ops[4] = { \ - { .fni4 = gen_helper_neon_##FUNC##8 }, \ - { .fni4 = gen_helper_neon_##FUNC##16 }, \ - { .fni4 = gen_helper_neon_##FUNC##32 }, \ - { 0 }, \ - }; \ - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ - } \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size > 2) { \ - return false; \ - } \ - return do_3same(s, a, gen_##INSN##_3s); \ - } - -/* - * Some helper functions need to be passed the cpu_env. In order - * to use those with the gvec APIs like tcg_gen_gvec_3() we need - * to create wrapper functions whose prototype is a NeonGenTwoOpFn() - * and which call a NeonGenTwoOpEnvFn(). - */ -#define WRAP_ENV_FN(WRAPNAME, FUNC) \ - static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ - { \ - FUNC(d, cpu_env, n, m); \ - } - -#define DO_3SAME_32_ENV(INSN, FUNC) \ - WRAP_ENV_FN(gen_##INSN##_tramp8, gen_helper_neon_##FUNC##8); \ - WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##16); \ - WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##32); \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - static const GVecGen3 ops[4] = { \ - { .fni4 = gen_##INSN##_tramp8 }, \ - { .fni4 = gen_##INSN##_tramp16 }, \ - { .fni4 = gen_##INSN##_tramp32 }, \ - { 0 }, \ - }; \ - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ - } \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size > 2) { \ - return false; \ - } \ - return do_3same(s, a, gen_##INSN##_3s); \ - } - -DO_3SAME_32(VHADD_S, hadd_s) -DO_3SAME_32(VHADD_U, hadd_u) -DO_3SAME_32(VHSUB_S, hsub_s) -DO_3SAME_32(VHSUB_U, hsub_u) -DO_3SAME_32(VRHADD_S, rhadd_s) -DO_3SAME_32(VRHADD_U, rhadd_u) -DO_3SAME_32(VRSHL_S, rshl_s) -DO_3SAME_32(VRSHL_U, rshl_u) - -DO_3SAME_32_ENV(VQSHL_S, qshl_s) -DO_3SAME_32_ENV(VQSHL_U, qshl_u) -DO_3SAME_32_ENV(VQRSHL_S, qrshl_s) -DO_3SAME_32_ENV(VQRSHL_U, qrshl_u) - -static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) -{ - /* Operations handled pairwise 32 bits at a time */ - TCGv_i32 tmp, tmp2, tmp3; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (a->size == 3) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - assert(a->q == 0); /* enforced by decode patterns */ - - /* - * Note that we have to be careful not to clobber the source operands - * in the "vm == vd" case by storing the result of the first pass too - * early. Since Q is 0 there are always just two passes, so instead - * of a complicated loop over each pass we just unroll. - */ - tmp = neon_load_reg(a->vn, 0); - tmp2 = neon_load_reg(a->vn, 1); - fn(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - - tmp3 = neon_load_reg(a->vm, 0); - tmp2 = neon_load_reg(a->vm, 1); - fn(tmp3, tmp3, tmp2); - tcg_temp_free_i32(tmp2); - - neon_store_reg(a->vd, 0, tmp); - neon_store_reg(a->vd, 1, tmp3); - return true; -} - -#define DO_3SAME_PAIR(INSN, func) \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - static NeonGenTwoOpFn * const fns[] = { \ - gen_helper_neon_##func##8, \ - gen_helper_neon_##func##16, \ - gen_helper_neon_##func##32, \ - }; \ - if (a->size > 2) { \ - return false; \ - } \ - return do_3same_pair(s, a, fns[a->size]); \ - } - -/* 32-bit pairwise ops end up the same as the elementwise versions. */ -#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32 -#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 -#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 -#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 -#define gen_helper_neon_padd_u32 tcg_gen_add_i32 - -DO_3SAME_PAIR(VPMAX_S, pmax_s) -DO_3SAME_PAIR(VPMIN_S, pmin_s) -DO_3SAME_PAIR(VPMAX_U, pmax_u) -DO_3SAME_PAIR(VPMIN_U, pmin_u) -DO_3SAME_PAIR(VPADD, padd_u) - -#define DO_3SAME_VQDMULH(INSN, FUNC) \ - WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \ - WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - static const GVecGen3 ops[2] = { \ - { .fni4 = gen_##INSN##_tramp16 }, \ - { .fni4 = gen_##INSN##_tramp32 }, \ - }; \ - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \ - } \ - static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size != 1 && a->size != 2) { \ - return false; \ - } \ - return do_3same(s, a, gen_##INSN##_3s); \ - } - -DO_3SAME_VQDMULH(VQDMULH, qdmulh) -DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) - -static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn, - bool reads_vd) -{ - /* - * FP operations handled elementwise 32 bits at a time. - * If reads_vd is true then the old value of Vd will be - * loaded before calling the callback function. This is - * used for multiply-accumulate type operations. - */ - TCGv_i32 tmp, tmp2; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - TCGv_ptr fpstatus = get_fpstatus_ptr(1); - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - tmp = neon_load_reg(a->vn, pass); - tmp2 = neon_load_reg(a->vm, pass); - if (reads_vd) { - TCGv_i32 tmp_rd = neon_load_reg(a->vd, pass); - fn(tmp_rd, tmp, tmp2, fpstatus); - neon_store_reg(a->vd, pass, tmp_rd); - tcg_temp_free_i32(tmp); - } else { - fn(tmp, tmp, tmp2, fpstatus); - neon_store_reg(a->vd, pass, tmp); - } - tcg_temp_free_i32(tmp2); - } - tcg_temp_free_ptr(fpstatus); - return true; -} - -/* - * For all the functions using this macro, size == 1 means fp16, - * which is an architecture extension we don't implement yet. - */ -#define DO_3S_FP_GVEC(INSN,FUNC) \ - static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ - uint32_t rn_ofs, uint32_t rm_ofs, \ - uint32_t oprsz, uint32_t maxsz) \ - { \ - TCGv_ptr fpst = get_fpstatus_ptr(1); \ - tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ - oprsz, maxsz, 0, FUNC); \ - tcg_temp_free_ptr(fpst); \ - } \ - static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size != 0) { \ - /* TODO fp16 support */ \ - return false; \ - } \ - return do_3same(s, a, gen_##INSN##_3s); \ - } - - -DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s) -DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s) -DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s) -DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s) - -/* - * For all the functions using this macro, size == 1 means fp16, - * which is an architecture extension we don't implement yet. - */ -#define DO_3S_FP(INSN,FUNC,READS_VD) \ - static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size != 0) { \ - /* TODO fp16 support */ \ - return false; \ - } \ - return do_3same_fp(s, a, FUNC, READS_VD); \ - } - -DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false) -DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) -DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false) -DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false) -DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false) -DO_3S_FP(VMAX, gen_helper_vfp_maxs, false) -DO_3S_FP(VMIN, gen_helper_vfp_mins, false) - -static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, - TCGv_ptr fpstatus) -{ - gen_helper_vfp_muls(vn, vn, vm, fpstatus); - gen_helper_vfp_adds(vd, vd, vn, fpstatus); -} - -static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, - TCGv_ptr fpstatus) -{ - gen_helper_vfp_muls(vn, vn, vm, fpstatus); - gen_helper_vfp_subs(vd, vd, vn, fpstatus); -} - -DO_3S_FP(VMLA, gen_VMLA_fp_3s, true) -DO_3S_FP(VMLS, gen_VMLS_fp_3s, true) - -static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a) -{ - if (!arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same_fp(s, a, gen_helper_vfp_maxnums, false); -} - -static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a) -{ - if (!arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same_fp(s, a, gen_helper_vfp_minnums, false); -} - -WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32) - -static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs, - uint32_t rn_ofs, uint32_t rm_ofs, - uint32_t oprsz, uint32_t maxsz) -{ - static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp }; - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); -} - -static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a) -{ - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same(s, a, gen_VRECPS_fp_3s); -} - -WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32) - -static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs, - uint32_t rn_ofs, uint32_t rm_ofs, - uint32_t oprsz, uint32_t maxsz) -{ - static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp }; - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops); -} - -static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a) -{ - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same(s, a, gen_VRSQRTS_fp_3s); -} - -static void gen_VFMA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, - TCGv_ptr fpstatus) -{ - gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); -} - -static bool trans_VFMA_fp_3s(DisasContext *s, arg_3same *a) -{ - if (!dc_isar_feature(aa32_simdfmac, s)) { - return false; - } - - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same_fp(s, a, gen_VFMA_fp_3s, true); -} - -static void gen_VFMS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, - TCGv_ptr fpstatus) -{ - gen_helper_vfp_negs(vn, vn); - gen_helper_vfp_muladds(vd, vn, vm, vd, fpstatus); -} - -static bool trans_VFMS_fp_3s(DisasContext *s, arg_3same *a) -{ - if (!dc_isar_feature(aa32_simdfmac, s)) { - return false; - } - - if (a->size != 0) { - /* TODO fp16 support */ - return false; - } - - return do_3same_fp(s, a, gen_VFMS_fp_3s, true); -} - -static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) -{ - /* FP operations handled pairwise 32 bits at a time */ - TCGv_i32 tmp, tmp2, tmp3; - TCGv_ptr fpstatus; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - assert(a->q == 0); /* enforced by decode patterns */ - - /* - * Note that we have to be careful not to clobber the source operands - * in the "vm == vd" case by storing the result of the first pass too - * early. Since Q is 0 there are always just two passes, so instead - * of a complicated loop over each pass we just unroll. - */ - fpstatus = get_fpstatus_ptr(1); - tmp = neon_load_reg(a->vn, 0); - tmp2 = neon_load_reg(a->vn, 1); - fn(tmp, tmp, tmp2, fpstatus); - tcg_temp_free_i32(tmp2); - - tmp3 = neon_load_reg(a->vm, 0); - tmp2 = neon_load_reg(a->vm, 1); - fn(tmp3, tmp3, tmp2, fpstatus); - tcg_temp_free_i32(tmp2); - tcg_temp_free_ptr(fpstatus); - - neon_store_reg(a->vd, 0, tmp); - neon_store_reg(a->vd, 1, tmp3); - return true; -} - -/* - * For all the functions using this macro, size == 1 means fp16, - * which is an architecture extension we don't implement yet. - */ -#define DO_3S_FP_PAIR(INSN,FUNC) \ - static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ - { \ - if (a->size != 0) { \ - /* TODO fp16 support */ \ - return false; \ - } \ - return do_3same_fp_pair(s, a, FUNC); \ - } - -DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) -DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) -DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) - -static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) -{ - /* Handle a 2-reg-shift insn which can be vectorized. */ - int vec_size = a->q ? 16 : 8; - int rd_ofs = neon_reg_offset(a->vd, 0); - int rm_ofs = neon_reg_offset(a->vm, 0); - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); - return true; -} - -#define DO_2SH(INSN, FUNC) \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_vector_2sh(s, a, FUNC); \ - } \ - -DO_2SH(VSHL, tcg_gen_gvec_shli) -DO_2SH(VSLI, gen_gvec_sli) -DO_2SH(VSRI, gen_gvec_sri) -DO_2SH(VSRA_S, gen_gvec_ssra) -DO_2SH(VSRA_U, gen_gvec_usra) -DO_2SH(VRSHR_S, gen_gvec_srshr) -DO_2SH(VRSHR_U, gen_gvec_urshr) -DO_2SH(VRSRA_S, gen_gvec_srsra) -DO_2SH(VRSRA_U, gen_gvec_ursra) - -static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) -{ - /* Signed shift out of range results in all-sign-bits */ - a->shift = MIN(a->shift, (8 << a->size) - 1); - return do_vector_2sh(s, a, tcg_gen_gvec_sari); -} - -static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz) -{ - tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); -} - -static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) -{ - /* Shift out of range is architecturally valid and results in zero. */ - if (a->shift >= (8 << a->size)) { - return do_vector_2sh(s, a, gen_zero_rd_2sh); - } else { - return do_vector_2sh(s, a, tcg_gen_gvec_shri); - } -} - -static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, - NeonGenTwo64OpEnvFn *fn) -{ - /* - * 2-reg-and-shift operations, size == 3 case, where the - * function needs to be passed cpu_env. - */ - TCGv_i64 constimm; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - constimm = tcg_const_i64(dup_const(a->size, a->shift)); - - for (pass = 0; pass < a->q + 1; pass++) { - TCGv_i64 tmp = tcg_temp_new_i64(); - - neon_load_reg64(tmp, a->vm + pass); - fn(tmp, cpu_env, tmp, constimm); - neon_store_reg64(tmp, a->vd + pass); - tcg_temp_free_i64(tmp); - } - tcg_temp_free_i64(constimm); - return true; -} - -static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, - NeonGenTwoOpEnvFn *fn) -{ - /* - * 2-reg-and-shift operations, size < 3 case, where the - * helper needs to be passed cpu_env. - */ - TCGv_i32 constimm; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * To avoid excessive duplication of ops we implement shift - * by immediate using the variable shift operations. - */ - constimm = tcg_const_i32(dup_const(a->size, a->shift)); - - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vm, pass); - fn(tmp, cpu_env, tmp, constimm); - neon_store_reg(a->vd, pass, tmp); - } - tcg_temp_free_i32(constimm); - return true; -} - -#define DO_2SHIFT_ENV(INSN, FUNC) \ - static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ - } \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - static NeonGenTwoOpEnvFn * const fns[] = { \ - gen_helper_neon_##FUNC##8, \ - gen_helper_neon_##FUNC##16, \ - gen_helper_neon_##FUNC##32, \ - }; \ - assert(a->size < ARRAY_SIZE(fns)); \ - return do_2shift_env_32(s, a, fns[a->size]); \ - } - -DO_2SHIFT_ENV(VQSHLU, qshlu_s) -DO_2SHIFT_ENV(VQSHL_U, qshl_u) -DO_2SHIFT_ENV(VQSHL_S, qshl_s) - -static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, - NeonGenTwo64OpFn *shiftfn, - NeonGenNarrowEnvFn *narrowfn) -{ - /* 2-reg-and-shift narrowing-shift operations, size == 3 case */ - TCGv_i64 constimm, rm1, rm2; - TCGv_i32 rd; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vm & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * This is always a right shift, and the shiftfn is always a - * left-shift helper, which thus needs the negated shift count. - */ - constimm = tcg_const_i64(-a->shift); - rm1 = tcg_temp_new_i64(); - rm2 = tcg_temp_new_i64(); - - /* Load both inputs first to avoid potential overwrite if rm == rd */ - neon_load_reg64(rm1, a->vm); - neon_load_reg64(rm2, a->vm + 1); - - shiftfn(rm1, rm1, constimm); - rd = tcg_temp_new_i32(); - narrowfn(rd, cpu_env, rm1); - neon_store_reg(a->vd, 0, rd); - - shiftfn(rm2, rm2, constimm); - rd = tcg_temp_new_i32(); - narrowfn(rd, cpu_env, rm2); - neon_store_reg(a->vd, 1, rd); - - tcg_temp_free_i64(rm1); - tcg_temp_free_i64(rm2); - tcg_temp_free_i64(constimm); - - return true; -} - -static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, - NeonGenTwoOpFn *shiftfn, - NeonGenNarrowEnvFn *narrowfn) -{ - /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ - TCGv_i32 constimm, rm1, rm2, rm3, rm4; - TCGv_i64 rtmp; - uint32_t imm; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vm & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * This is always a right shift, and the shiftfn is always a - * left-shift helper, which thus needs the negated shift count - * duplicated into each lane of the immediate value. - */ - if (a->size == 1) { - imm = (uint16_t)(-a->shift); - imm |= imm << 16; - } else { - /* size == 2 */ - imm = -a->shift; - } - constimm = tcg_const_i32(imm); - - /* Load all inputs first to avoid potential overwrite */ - rm1 = neon_load_reg(a->vm, 0); - rm2 = neon_load_reg(a->vm, 1); - rm3 = neon_load_reg(a->vm + 1, 0); - rm4 = neon_load_reg(a->vm + 1, 1); - rtmp = tcg_temp_new_i64(); - - shiftfn(rm1, rm1, constimm); - shiftfn(rm2, rm2, constimm); - - tcg_gen_concat_i32_i64(rtmp, rm1, rm2); - tcg_temp_free_i32(rm2); - - narrowfn(rm1, cpu_env, rtmp); - neon_store_reg(a->vd, 0, rm1); - - shiftfn(rm3, rm3, constimm); - shiftfn(rm4, rm4, constimm); - tcg_temp_free_i32(constimm); - - tcg_gen_concat_i32_i64(rtmp, rm3, rm4); - tcg_temp_free_i32(rm4); - - narrowfn(rm3, cpu_env, rtmp); - tcg_temp_free_i64(rtmp); - neon_store_reg(a->vd, 1, rm3); - return true; -} - -#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ - } -#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ - } - -static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) -{ - tcg_gen_extrl_i64_i32(dest, src); -} - -static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) -{ - gen_helper_neon_narrow_u16(dest, src); -} - -static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) -{ - gen_helper_neon_narrow_u8(dest, src); -} - -DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) -DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) -DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) - -DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) -DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) -DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) - -DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) -DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) -DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8) - -DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32) -DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16) -DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8) -DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) -DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) -DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8) - -DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32) -DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16) -DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8) - -DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) -DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) -DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8) - -DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32) -DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16) -DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8) - -static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, - NeonGenWidenFn *widenfn, bool u) -{ - TCGv_i64 tmp; - TCGv_i32 rm0, rm1; - uint64_t widen_mask = 0; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vd & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* - * This is a widen-and-shift operation. The shift is always less - * than the width of the source type, so after widening the input - * vector we can simply shift the whole 64-bit widened register, - * and then clear the potential overflow bits resulting from left - * bits of the narrow input appearing as right bits of the left - * neighbour narrow input. Calculate a mask of bits to clear. - */ - if ((a->shift != 0) && (a->size < 2 || u)) { - int esize = 8 << a->size; - widen_mask = MAKE_64BIT_MASK(0, esize); - widen_mask >>= esize - a->shift; - widen_mask = dup_const(a->size + 1, widen_mask); - } - - rm0 = neon_load_reg(a->vm, 0); - rm1 = neon_load_reg(a->vm, 1); - tmp = tcg_temp_new_i64(); - - widenfn(tmp, rm0); - tcg_temp_free_i32(rm0); - if (a->shift != 0) { - tcg_gen_shli_i64(tmp, tmp, a->shift); - tcg_gen_andi_i64(tmp, tmp, ~widen_mask); - } - neon_store_reg64(tmp, a->vd); - - widenfn(tmp, rm1); - tcg_temp_free_i32(rm1); - if (a->shift != 0) { - tcg_gen_shli_i64(tmp, tmp, a->shift); - tcg_gen_andi_i64(tmp, tmp, ~widen_mask); - } - neon_store_reg64(tmp, a->vd + 1); - tcg_temp_free_i64(tmp); - return true; -} - -static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_s8, - gen_helper_neon_widen_s16, - tcg_gen_ext_i32_i64, - }; - return do_vshll_2sh(s, a, widenfn[a->size], false); -} - -static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_u8, - gen_helper_neon_widen_u16, - tcg_gen_extu_i32_i64, - }; - return do_vshll_2sh(s, a, widenfn[a->size], true); -} - -static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, - NeonGenTwoSingleOpFn *fn) -{ - /* FP operations in 2-reg-and-shift group */ - TCGv_i32 tmp, shiftv; - TCGv_ptr fpstatus; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm | a->vd) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpstatus = get_fpstatus_ptr(1); - shiftv = tcg_const_i32(a->shift); - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - tmp = neon_load_reg(a->vm, pass); - fn(tmp, tmp, shiftv, fpstatus); - neon_store_reg(a->vd, pass, tmp); - } - tcg_temp_free_ptr(fpstatus); - tcg_temp_free_i32(shiftv); - return true; -} - -#define DO_FP_2SH(INSN, FUNC) \ - static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ - { \ - return do_fp_2sh(s, a, FUNC); \ - } - -DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) -DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) -DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) -DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) - -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) -{ - /* - * Expand the encoded constant. - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. - * We choose to not special-case this and will behave as if a - * valid constant encoding of 0 had been given. - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. - */ - switch (cmode) { - case 0: case 1: - /* no-op */ - break; - case 2: case 3: - imm <<= 8; - break; - case 4: case 5: - imm <<= 16; - break; - case 6: case 7: - imm <<= 24; - break; - case 8: case 9: - imm |= imm << 16; - break; - case 10: case 11: - imm = (imm << 8) | (imm << 24); - break; - case 12: - imm = (imm << 8) | 0xff; - break; - case 13: - imm = (imm << 16) | 0xffff; - break; - case 14: - if (op) { - /* - * This is the only case where the top and bottom 32 bits - * of the encoded constant differ. - */ - uint64_t imm64 = 0; - int n; - - for (n = 0; n < 8; n++) { - if (imm & (1 << n)) { - imm64 |= (0xffULL << (n * 8)); - } - } - return imm64; - } - imm |= (imm << 8) | (imm << 16) | (imm << 24); - break; - case 15: - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); - break; - } - if (op) { - imm = ~imm; - } - return dup_const(MO_32, imm); -} - -static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, - GVecGen2iFn *fn) -{ - uint64_t imm; - int reg_ofs, vec_size; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (a->vd & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - reg_ofs = neon_reg_offset(a->vd, 0); - vec_size = a->q ? 16 : 8; - imm = asimd_imm_const(a->imm, a->cmode, a->op); - - fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); - return true; -} - -static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz) -{ - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); -} - -static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) -{ - /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ - GVecGen2iFn *fn; - - if ((a->cmode & 1) && a->cmode < 12) { - /* for op=1, the imm will be inverted, so BIC becomes AND. */ - fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; - } else { - /* There is one unallocated cmode/op combination in this space */ - if (a->cmode == 15 && a->op == 1) { - return false; - } - fn = gen_VMOV_1r; - } - return do_1reg_imm(s, a, fn); -} - -static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, - NeonGenWidenFn *widenfn, - NeonGenTwo64OpFn *opfn, - bool src1_wide) -{ - /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ - TCGv_i64 rn0_64, rn1_64, rm_64; - TCGv_i32 rm; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!widenfn || !opfn) { - /* size == 3 case, which is an entirely different insn group */ - return false; - } - - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rn0_64 = tcg_temp_new_i64(); - rn1_64 = tcg_temp_new_i64(); - rm_64 = tcg_temp_new_i64(); - - if (src1_wide) { - neon_load_reg64(rn0_64, a->vn); - } else { - TCGv_i32 tmp = neon_load_reg(a->vn, 0); - widenfn(rn0_64, tmp); - tcg_temp_free_i32(tmp); - } - rm = neon_load_reg(a->vm, 0); - - widenfn(rm_64, rm); - tcg_temp_free_i32(rm); - opfn(rn0_64, rn0_64, rm_64); - - /* - * Load second pass inputs before storing the first pass result, to - * avoid incorrect results if a narrow input overlaps with the result. - */ - if (src1_wide) { - neon_load_reg64(rn1_64, a->vn + 1); - } else { - TCGv_i32 tmp = neon_load_reg(a->vn, 1); - widenfn(rn1_64, tmp); - tcg_temp_free_i32(tmp); - } - rm = neon_load_reg(a->vm, 1); - - neon_store_reg64(rn0_64, a->vd); - - widenfn(rm_64, rm); - tcg_temp_free_i32(rm); - opfn(rn1_64, rn1_64, rm_64); - neon_store_reg64(rn1_64, a->vd + 1); - - tcg_temp_free_i64(rn0_64); - tcg_temp_free_i64(rn1_64); - tcg_temp_free_i64(rm_64); - - return true; -} - -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ - static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ - { \ - static NeonGenWidenFn * const widenfn[] = { \ - gen_helper_neon_widen_##S##8, \ - gen_helper_neon_widen_##S##16, \ - tcg_gen_##EXT##_i32_i64, \ - NULL, \ - }; \ - static NeonGenTwo64OpFn * const addfn[] = { \ - gen_helper_neon_##OP##l_u16, \ - gen_helper_neon_##OP##l_u32, \ - tcg_gen_##OP##_i64, \ - NULL, \ - }; \ - return do_prewiden_3d(s, a, widenfn[a->size], \ - addfn[a->size], SRC1WIDE); \ - } - -DO_PREWIDEN(VADDL_S, s, ext, add, false) -DO_PREWIDEN(VADDL_U, u, extu, add, false) -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) -DO_PREWIDEN(VADDW_S, s, ext, add, true) -DO_PREWIDEN(VADDW_U, u, extu, add, true) -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) - -static bool do_narrow_3d(DisasContext *s, arg_3diff *a, - NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) -{ - /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */ - TCGv_i64 rn_64, rm_64; - TCGv_i32 rd0, rd1; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!opfn || !narrowfn) { - /* size == 3 case, which is an entirely different insn group */ - return false; - } - - if ((a->vn | a->vm) & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rn_64 = tcg_temp_new_i64(); - rm_64 = tcg_temp_new_i64(); - rd0 = tcg_temp_new_i32(); - rd1 = tcg_temp_new_i32(); - - neon_load_reg64(rn_64, a->vn); - neon_load_reg64(rm_64, a->vm); - - opfn(rn_64, rn_64, rm_64); - - narrowfn(rd0, rn_64); - - neon_load_reg64(rn_64, a->vn + 1); - neon_load_reg64(rm_64, a->vm + 1); - - opfn(rn_64, rn_64, rm_64); - - narrowfn(rd1, rn_64); - - neon_store_reg(a->vd, 0, rd0); - neon_store_reg(a->vd, 1, rd1); - - tcg_temp_free_i64(rn_64); - tcg_temp_free_i64(rm_64); - - return true; -} - -#define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \ - static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ - { \ - static NeonGenTwo64OpFn * const addfn[] = { \ - gen_helper_neon_##OP##l_u16, \ - gen_helper_neon_##OP##l_u32, \ - tcg_gen_##OP##_i64, \ - NULL, \ - }; \ - static NeonGenNarrowFn * const narrowfn[] = { \ - gen_helper_neon_##NARROWTYPE##_high_u8, \ - gen_helper_neon_##NARROWTYPE##_high_u16, \ - EXTOP, \ - NULL, \ - }; \ - return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \ - } - -static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn) -{ - tcg_gen_addi_i64(rn, rn, 1u << 31); - tcg_gen_extrh_i64_i32(rd, rn); -} - -DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) -DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) -DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) -DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) - -static bool do_long_3d(DisasContext *s, arg_3diff *a, - NeonGenTwoOpWidenFn *opfn, - NeonGenTwo64OpFn *accfn) -{ - /* - * 3-regs different lengths, long operations. - * These perform an operation on two inputs that returns a double-width - * result, and then possibly perform an accumulation operation of - * that result into the double-width destination. - */ - TCGv_i64 rd0, rd1, tmp; - TCGv_i32 rn, rm; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!opfn) { - /* size == 3 case, which is an entirely different insn group */ - return false; - } - - if (a->vd & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rd0 = tcg_temp_new_i64(); - rd1 = tcg_temp_new_i64(); - - rn = neon_load_reg(a->vn, 0); - rm = neon_load_reg(a->vm, 0); - opfn(rd0, rn, rm); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(rm); - - rn = neon_load_reg(a->vn, 1); - rm = neon_load_reg(a->vm, 1); - opfn(rd1, rn, rm); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(rm); - - /* Don't store results until after all loads: they might overlap */ - if (accfn) { - tmp = tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vd); - accfn(tmp, tmp, rd0); - neon_store_reg64(tmp, a->vd); - neon_load_reg64(tmp, a->vd + 1); - accfn(tmp, tmp, rd1); - neon_store_reg64(tmp, a->vd + 1); - tcg_temp_free_i64(tmp); - } else { - neon_store_reg64(rd0, a->vd); - neon_store_reg64(rd1, a->vd + 1); - } - - tcg_temp_free_i64(rd0); - tcg_temp_free_i64(rd1); - - return true; -} - -static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_abdl_s16, - gen_helper_neon_abdl_s32, - gen_helper_neon_abdl_s64, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], NULL); -} - -static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_abdl_u16, - gen_helper_neon_abdl_u32, - gen_helper_neon_abdl_u64, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], NULL); -} - -static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_abdl_s16, - gen_helper_neon_abdl_s32, - gen_helper_neon_abdl_s64, - NULL, - }; - static NeonGenTwo64OpFn * const addfn[] = { - gen_helper_neon_addl_u16, - gen_helper_neon_addl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], addfn[a->size]); -} - -static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_abdl_u16, - gen_helper_neon_abdl_u32, - gen_helper_neon_abdl_u64, - NULL, - }; - static NeonGenTwo64OpFn * const addfn[] = { - gen_helper_neon_addl_u16, - gen_helper_neon_addl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], addfn[a->size]); -} - -static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) -{ - TCGv_i32 lo = tcg_temp_new_i32(); - TCGv_i32 hi = tcg_temp_new_i32(); - - tcg_gen_muls2_i32(lo, hi, rn, rm); - tcg_gen_concat_i32_i64(rd, lo, hi); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); -} - -static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) -{ - TCGv_i32 lo = tcg_temp_new_i32(); - TCGv_i32 hi = tcg_temp_new_i32(); - - tcg_gen_mulu2_i32(lo, hi, rn, rm); - tcg_gen_concat_i32_i64(rd, lo, hi); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); -} - -static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_mull_s8, - gen_helper_neon_mull_s16, - gen_mull_s32, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], NULL); -} - -static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - gen_helper_neon_mull_u8, - gen_helper_neon_mull_u16, - gen_mull_u32, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], NULL); -} - -#define DO_VMLAL(INSN,MULL,ACC) \ - static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ - { \ - static NeonGenTwoOpWidenFn * const opfn[] = { \ - gen_helper_neon_##MULL##8, \ - gen_helper_neon_##MULL##16, \ - gen_##MULL##32, \ - NULL, \ - }; \ - static NeonGenTwo64OpFn * const accfn[] = { \ - gen_helper_neon_##ACC##l_u16, \ - gen_helper_neon_##ACC##l_u32, \ - tcg_gen_##ACC##_i64, \ - NULL, \ - }; \ - return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \ - } - -DO_VMLAL(VMLAL_S,mull_s,add) -DO_VMLAL(VMLAL_U,mull_u,add) -DO_VMLAL(VMLSL_S,mull_s,sub) -DO_VMLAL(VMLSL_U,mull_u,sub) - -static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) -{ - gen_helper_neon_mull_s16(rd, rn, rm); - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); -} - -static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) -{ - gen_mull_s32(rd, rn, rm); - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); -} - -static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], NULL); -} - -static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); -} - -static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); -} - -static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - NULL, - gen_VQDMLAL_acc_16, - gen_VQDMLAL_acc_32, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], accfn[a->size]); -} - -static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - gen_helper_neon_negl_u32(rm, rm); - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); -} - -static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - tcg_gen_neg_i64(rm, rm); - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); -} - -static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - NULL, - gen_VQDMLSL_acc_16, - gen_VQDMLSL_acc_32, - NULL, - }; - - return do_long_3d(s, a, opfn[a->size], accfn[a->size]); -} - -static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) -{ - gen_helper_gvec_3 *fn_gvec; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (a->vd & 1) { - return false; - } - - switch (a->size) { - case 0: - fn_gvec = gen_helper_neon_pmull_h; - break; - case 2: - if (!dc_isar_feature(aa32_pmull, s)) { - return false; - } - fn_gvec = gen_helper_gvec_pmull_q; - break; - default: - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), - neon_reg_offset(a->vn, 0), - neon_reg_offset(a->vm, 0), - 16, 16, 0, fn_gvec); - return true; -} - -static void gen_neon_dup_low16(TCGv_i32 var) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_ext16u_i32(var, var); - tcg_gen_shli_i32(tmp, var, 16); - tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); -} - -static void gen_neon_dup_high16(TCGv_i32 var) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(var, var, 0xffff0000); - tcg_gen_shri_i32(tmp, var, 16); - tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); -} - -static inline TCGv_i32 neon_get_scalar(int size, int reg) -{ - TCGv_i32 tmp; - if (size == 1) { - tmp = neon_load_reg(reg & 7, reg >> 4); - if (reg & 8) { - gen_neon_dup_high16(tmp); - } else { - gen_neon_dup_low16(tmp); - } - } else { - tmp = neon_load_reg(reg & 15, reg >> 4); - } - return tmp; -} - -static bool do_2scalar(DisasContext *s, arg_2scalar *a, - NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn) -{ - /* - * Two registers and a scalar: perform an operation between - * the input elements and the scalar, and then possibly - * perform an accumulation operation of that result into the - * destination. - */ - TCGv_i32 scalar; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!opfn) { - /* Bad size (including size == 3, which is a different insn group) */ - return false; - } - - if (a->q && ((a->vd | a->vn) & 1)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - scalar = neon_get_scalar(a->size, a->vm); - - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vn, pass); - opfn(tmp, tmp, scalar); - if (accfn) { - TCGv_i32 rd = neon_load_reg(a->vd, pass); - accfn(tmp, rd, tmp); - tcg_temp_free_i32(rd); - } - neon_store_reg(a->vd, pass, tmp); - } - tcg_temp_free_i32(scalar); - return true; -} - -static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], NULL); -} - -static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - NULL, - }; - static NeonGenTwoOpFn * const accfn[] = { - NULL, - gen_helper_neon_add_u16, - tcg_gen_add_i32, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], accfn[a->size]); -} - -static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - gen_helper_neon_mul_u16, - tcg_gen_mul_i32, - NULL, - }; - static NeonGenTwoOpFn * const accfn[] = { - NULL, - gen_helper_neon_sub_u16, - tcg_gen_sub_i32, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], accfn[a->size]); -} - -/* - * Rather than have a float-specific version of do_2scalar just for - * three insns, we wrap a NeonGenTwoSingleOpFn to turn it into - * a NeonGenTwoOpFn. - */ -#define WRAP_FP_FN(WRAPNAME, FUNC) \ - static void WRAPNAME(TCGv_i32 rd, TCGv_i32 rn, TCGv_i32 rm) \ - { \ - TCGv_ptr fpstatus = get_fpstatus_ptr(1); \ - FUNC(rd, rn, rm, fpstatus); \ - tcg_temp_free_ptr(fpstatus); \ - } - -WRAP_FP_FN(gen_VMUL_F_mul, gen_helper_vfp_muls) -WRAP_FP_FN(gen_VMUL_F_add, gen_helper_vfp_adds) -WRAP_FP_FN(gen_VMUL_F_sub, gen_helper_vfp_subs) - -static bool trans_VMUL_F_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - NULL, /* TODO: fp16 support */ - gen_VMUL_F_mul, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], NULL); -} - -static bool trans_VMLA_F_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - NULL, /* TODO: fp16 support */ - gen_VMUL_F_mul, - NULL, - }; - static NeonGenTwoOpFn * const accfn[] = { - NULL, - NULL, /* TODO: fp16 support */ - gen_VMUL_F_add, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], accfn[a->size]); -} - -static bool trans_VMLS_F_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - NULL, /* TODO: fp16 support */ - gen_VMUL_F_mul, - NULL, - }; - static NeonGenTwoOpFn * const accfn[] = { - NULL, - NULL, /* TODO: fp16 support */ - gen_VMUL_F_sub, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], accfn[a->size]); -} - -WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16) -WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32) -WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16) -WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32) - -static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - gen_VQDMULH_16, - gen_VQDMULH_32, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], NULL); -} - -static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpFn * const opfn[] = { - NULL, - gen_VQRDMULH_16, - gen_VQRDMULH_32, - NULL, - }; - - return do_2scalar(s, a, opfn[a->size], NULL); -} - -static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, - NeonGenThreeOpEnvFn *opfn) -{ - /* - * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn - * performs a kind of fused op-then-accumulate using a helper - * function that takes all of rd, rn and the scalar at once. - */ - TCGv_i32 scalar; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - if (!dc_isar_feature(aa32_rdm, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!opfn) { - /* Bad size (including size == 3, which is a different insn group) */ - return false; - } - - if (a->q && ((a->vd | a->vn) & 1)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - scalar = neon_get_scalar(a->size, a->vm); - - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 rn = neon_load_reg(a->vn, pass); - TCGv_i32 rd = neon_load_reg(a->vd, pass); - opfn(rd, cpu_env, rn, scalar, rd); - tcg_temp_free_i32(rn); - neon_store_reg(a->vd, pass, rd); - } - tcg_temp_free_i32(scalar); - - return true; -} - -static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenThreeOpEnvFn *opfn[] = { - NULL, - gen_helper_neon_qrdmlah_s16, - gen_helper_neon_qrdmlah_s32, - NULL, - }; - return do_vqrdmlah_2sc(s, a, opfn[a->size]); -} - -static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenThreeOpEnvFn *opfn[] = { - NULL, - gen_helper_neon_qrdmlsh_s16, - gen_helper_neon_qrdmlsh_s32, - NULL, - }; - return do_vqrdmlah_2sc(s, a, opfn[a->size]); -} - -static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, - NeonGenTwoOpWidenFn *opfn, - NeonGenTwo64OpFn *accfn) -{ - /* - * Two registers and a scalar, long operations: perform an - * operation on the input elements and the scalar which produces - * a double-width result, and then possibly perform an accumulation - * operation of that result into the destination. - */ - TCGv_i32 scalar, rn; - TCGv_i64 rn0_64, rn1_64; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!opfn) { - /* Bad size (including size == 3, which is a different insn group) */ - return false; - } - - if (a->vd & 1) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - scalar = neon_get_scalar(a->size, a->vm); - - /* Load all inputs before writing any outputs, in case of overlap */ - rn = neon_load_reg(a->vn, 0); - rn0_64 = tcg_temp_new_i64(); - opfn(rn0_64, rn, scalar); - tcg_temp_free_i32(rn); - - rn = neon_load_reg(a->vn, 1); - rn1_64 = tcg_temp_new_i64(); - opfn(rn1_64, rn, scalar); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(scalar); - - if (accfn) { - TCGv_i64 t64 = tcg_temp_new_i64(); - neon_load_reg64(t64, a->vd); - accfn(t64, t64, rn0_64); - neon_store_reg64(t64, a->vd); - neon_load_reg64(t64, a->vd + 1); - accfn(t64, t64, rn1_64); - neon_store_reg64(t64, a->vd + 1); - tcg_temp_free_i64(t64); - } else { - neon_store_reg64(rn0_64, a->vd); - neon_store_reg64(rn1_64, a->vd + 1); - } - tcg_temp_free_i64(rn0_64); - tcg_temp_free_i64(rn1_64); - return true; -} - -static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_helper_neon_mull_s16, - gen_mull_s32, - NULL, - }; - - return do_2scalar_long(s, a, opfn[a->size], NULL); -} - -static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_helper_neon_mull_u16, - gen_mull_u32, - NULL, - }; - - return do_2scalar_long(s, a, opfn[a->size], NULL); -} - -#define DO_VMLAL_2SC(INSN, MULL, ACC) \ - static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \ - { \ - static NeonGenTwoOpWidenFn * const opfn[] = { \ - NULL, \ - gen_helper_neon_##MULL##16, \ - gen_##MULL##32, \ - NULL, \ - }; \ - static NeonGenTwo64OpFn * const accfn[] = { \ - NULL, \ - gen_helper_neon_##ACC##l_u32, \ - tcg_gen_##ACC##_i64, \ - NULL, \ - }; \ - return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \ - } - -DO_VMLAL_2SC(VMLAL_S, mull_s, add) -DO_VMLAL_2SC(VMLAL_U, mull_u, add) -DO_VMLAL_2SC(VMLSL_S, mull_s, sub) -DO_VMLAL_2SC(VMLSL_U, mull_u, sub) - -static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - - return do_2scalar_long(s, a, opfn[a->size], NULL); -} - -static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - NULL, - gen_VQDMLAL_acc_16, - gen_VQDMLAL_acc_32, - NULL, - }; - - return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); -} - -static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a) -{ - static NeonGenTwoOpWidenFn * const opfn[] = { - NULL, - gen_VQDMULL_16, - gen_VQDMULL_32, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - NULL, - gen_VQDMLSL_acc_16, - gen_VQDMLSL_acc_32, - NULL, - }; - - return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); -} - -static bool trans_VEXT(DisasContext *s, arg_VEXT *a) -{ - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vn | a->vm | a->vd) & a->q) { - return false; - } - - if (a->imm > 7 && !a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (!a->q) { - /* Extract 64 bits from */ - TCGv_i64 left, right, dest; - - left = tcg_temp_new_i64(); - right = tcg_temp_new_i64(); - dest = tcg_temp_new_i64(); - - neon_load_reg64(right, a->vn); - neon_load_reg64(left, a->vm); - tcg_gen_extract2_i64(dest, right, left, a->imm * 8); - neon_store_reg64(dest, a->vd); - - tcg_temp_free_i64(left); - tcg_temp_free_i64(right); - tcg_temp_free_i64(dest); - } else { - /* Extract 128 bits from */ - TCGv_i64 left, middle, right, destleft, destright; - - left = tcg_temp_new_i64(); - middle = tcg_temp_new_i64(); - right = tcg_temp_new_i64(); - destleft = tcg_temp_new_i64(); - destright = tcg_temp_new_i64(); - - if (a->imm < 8) { - neon_load_reg64(right, a->vn); - neon_load_reg64(middle, a->vn + 1); - tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); - neon_load_reg64(left, a->vm); - tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); - } else { - neon_load_reg64(right, a->vn + 1); - neon_load_reg64(middle, a->vm); - tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); - neon_load_reg64(left, a->vm + 1); - tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); - } - - neon_store_reg64(destright, a->vd); - neon_store_reg64(destleft, a->vd + 1); - - tcg_temp_free_i64(destright); - tcg_temp_free_i64(destleft); - tcg_temp_free_i64(right); - tcg_temp_free_i64(middle); - tcg_temp_free_i64(left); - } - return true; -} - -static bool trans_VTBL(DisasContext *s, arg_VTBL *a) -{ - int n; - TCGv_i32 tmp, tmp2, tmp3, tmp4; - TCGv_ptr ptr1; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - n = a->len + 1; - if ((a->vn + n) > 32) { - /* - * This is UNPREDICTABLE; we choose to UNDEF to avoid the - * helper function running off the end of the register file. - */ - return false; - } - n <<= 3; - if (a->op) { - tmp = neon_load_reg(a->vd, 0); - } else { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } - tmp2 = neon_load_reg(a->vm, 0); - ptr1 = vfp_reg_ptr(true, a->vn); - tmp4 = tcg_const_i32(n); - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); - tcg_temp_free_i32(tmp); - if (a->op) { - tmp = neon_load_reg(a->vd, 1); - } else { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } - tmp3 = neon_load_reg(a->vm, 1); - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); - tcg_temp_free_i32(tmp4); - tcg_temp_free_ptr(ptr1); - neon_store_reg(a->vd, 0, tmp2); - neon_store_reg(a->vd, 1, tmp3); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) -{ - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vd & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), - neon_element_offset(a->vm, a->index, a->size), - a->q ? 16 : 8, a->q ? 16 : 8); - return true; -} - -static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) -{ - int pass, half; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (a->size == 3) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { - TCGv_i32 tmp[2]; - - for (half = 0; half < 2; half++) { - tmp[half] = neon_load_reg(a->vm, pass * 2 + half); - switch (a->size) { - case 0: - tcg_gen_bswap32_i32(tmp[half], tmp[half]); - break; - case 1: - gen_swap_half(tmp[half], tmp[half]); - break; - case 2: - break; - default: - g_assert_not_reached(); - } - } - neon_store_reg(a->vd, pass * 2, tmp[1]); - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); - } - return true; -} - -static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, - NeonGenWidenFn *widenfn, - NeonGenTwo64OpFn *opfn, - NeonGenTwo64OpFn *accfn) -{ - /* - * Pairwise long operations: widen both halves of the pair, - * combine the pairs with the opfn, and then possibly accumulate - * into the destination with the accfn. - */ - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!widenfn) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - for (pass = 0; pass < a->q + 1; pass++) { - TCGv_i32 tmp; - TCGv_i64 rm0_64, rm1_64, rd_64; - - rm0_64 = tcg_temp_new_i64(); - rm1_64 = tcg_temp_new_i64(); - rd_64 = tcg_temp_new_i64(); - tmp = neon_load_reg(a->vm, pass * 2); - widenfn(rm0_64, tmp); - tcg_temp_free_i32(tmp); - tmp = neon_load_reg(a->vm, pass * 2 + 1); - widenfn(rm1_64, tmp); - tcg_temp_free_i32(tmp); - opfn(rd_64, rm0_64, rm1_64); - tcg_temp_free_i64(rm0_64); - tcg_temp_free_i64(rm1_64); - - if (accfn) { - TCGv_i64 tmp64 = tcg_temp_new_i64(); - neon_load_reg64(tmp64, a->vd + pass); - accfn(rd_64, tmp64, rd_64); - tcg_temp_free_i64(tmp64); - } - neon_store_reg64(rd_64, a->vd + pass); - tcg_temp_free_i64(rd_64); - } - return true; -} - -static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_s8, - gen_helper_neon_widen_s16, - tcg_gen_ext_i32_i64, - NULL, - }; - static NeonGenTwo64OpFn * const opfn[] = { - gen_helper_neon_paddl_u16, - gen_helper_neon_paddl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); -} - -static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_u8, - gen_helper_neon_widen_u16, - tcg_gen_extu_i32_i64, - NULL, - }; - static NeonGenTwo64OpFn * const opfn[] = { - gen_helper_neon_paddl_u16, - gen_helper_neon_paddl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); -} - -static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_s8, - gen_helper_neon_widen_s16, - tcg_gen_ext_i32_i64, - NULL, - }; - static NeonGenTwo64OpFn * const opfn[] = { - gen_helper_neon_paddl_u16, - gen_helper_neon_paddl_u32, - tcg_gen_add_i64, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - gen_helper_neon_addl_u16, - gen_helper_neon_addl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], - accfn[a->size]); -} - -static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) -{ - static NeonGenWidenFn * const widenfn[] = { - gen_helper_neon_widen_u8, - gen_helper_neon_widen_u16, - tcg_gen_extu_i32_i64, - NULL, - }; - static NeonGenTwo64OpFn * const opfn[] = { - gen_helper_neon_paddl_u16, - gen_helper_neon_paddl_u32, - tcg_gen_add_i64, - NULL, - }; - static NeonGenTwo64OpFn * const accfn[] = { - gen_helper_neon_addl_u16, - gen_helper_neon_addl_u32, - tcg_gen_add_i64, - NULL, - }; - - return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], - accfn[a->size]); -} - -typedef void ZipFn(TCGv_ptr, TCGv_ptr); - -static bool do_zip_uzp(DisasContext *s, arg_2misc *a, - ZipFn *fn) -{ - TCGv_ptr pd, pm; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!fn) { - /* Bad size or size/q combination */ - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - pd = vfp_reg_ptr(true, a->vd); - pm = vfp_reg_ptr(true, a->vm); - fn(pd, pm); - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(pm); - return true; -} - -static bool trans_VUZP(DisasContext *s, arg_2misc *a) -{ - static ZipFn * const fn[2][4] = { - { - gen_helper_neon_unzip8, - gen_helper_neon_unzip16, - NULL, - NULL, - }, { - gen_helper_neon_qunzip8, - gen_helper_neon_qunzip16, - gen_helper_neon_qunzip32, - NULL, - } - }; - return do_zip_uzp(s, a, fn[a->q][a->size]); -} - -static bool trans_VZIP(DisasContext *s, arg_2misc *a) -{ - static ZipFn * const fn[2][4] = { - { - gen_helper_neon_zip8, - gen_helper_neon_zip16, - NULL, - NULL, - }, { - gen_helper_neon_qzip8, - gen_helper_neon_qzip16, - gen_helper_neon_qzip32, - NULL, - } - }; - return do_zip_uzp(s, a, fn[a->q][a->size]); -} - -static bool do_vmovn(DisasContext *s, arg_2misc *a, - NeonGenNarrowEnvFn *narrowfn) -{ - TCGv_i64 rm; - TCGv_i32 rd0, rd1; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vm & 1) { - return false; - } - - if (!narrowfn) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rm = tcg_temp_new_i64(); - rd0 = tcg_temp_new_i32(); - rd1 = tcg_temp_new_i32(); - - neon_load_reg64(rm, a->vm); - narrowfn(rd0, cpu_env, rm); - neon_load_reg64(rm, a->vm + 1); - narrowfn(rd1, cpu_env, rm); - neon_store_reg(a->vd, 0, rd0); - neon_store_reg(a->vd, 1, rd1); - tcg_temp_free_i64(rm); - return true; -} - -#define DO_VMOVN(INSN, FUNC) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - static NeonGenNarrowEnvFn * const narrowfn[] = { \ - FUNC##8, \ - FUNC##16, \ - FUNC##32, \ - NULL, \ - }; \ - return do_vmovn(s, a, narrowfn[a->size]); \ - } - -DO_VMOVN(VMOVN, gen_neon_narrow_u) -DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) -DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) -DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) - -static bool trans_VSHLL(DisasContext *s, arg_2misc *a) -{ - TCGv_i32 rm0, rm1; - TCGv_i64 rd; - static NeonGenWidenFn * const widenfns[] = { - gen_helper_neon_widen_u8, - gen_helper_neon_widen_u16, - tcg_gen_extu_i32_i64, - NULL, - }; - NeonGenWidenFn *widenfn = widenfns[a->size]; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->vd & 1) { - return false; - } - - if (!widenfn) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rd = tcg_temp_new_i64(); - - rm0 = neon_load_reg(a->vm, 0); - rm1 = neon_load_reg(a->vm, 1); - - widenfn(rd, rm0); - tcg_gen_shli_i64(rd, rd, 8 << a->size); - neon_store_reg64(rd, a->vd); - widenfn(rd, rm1); - tcg_gen_shli_i64(rd, rd, 8 << a->size); - neon_store_reg64(rd, a->vd + 1); - - tcg_temp_free_i64(rd); - tcg_temp_free_i32(rm0); - tcg_temp_free_i32(rm1); - return true; -} - -static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp, tmp, tmp2, tmp3; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || - !dc_isar_feature(aa32_fp16_spconv, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vm & 1) || (a->size != 1)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(true); - ahp = get_ahp_flag(); - tmp = neon_load_reg(a->vm, 0); - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp2 = neon_load_reg(a->vm, 1); - gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp2, tmp2, tmp); - tcg_temp_free_i32(tmp); - tmp = neon_load_reg(a->vm, 2); - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp3 = neon_load_reg(a->vm, 3); - neon_store_reg(a->vd, 0, tmp2); - gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); - tcg_gen_shli_i32(tmp3, tmp3, 16); - tcg_gen_or_i32(tmp3, tmp3, tmp); - neon_store_reg(a->vd, 1, tmp3); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - - return true; -} - -static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp, tmp, tmp2, tmp3; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || - !dc_isar_feature(aa32_fp16_spconv, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vd & 1) || (a->size != 1)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(true); - ahp = get_ahp_flag(); - tmp3 = tcg_temp_new_i32(); - tmp = neon_load_reg(a->vm, 0); - tmp2 = neon_load_reg(a->vm, 1); - tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(a->vd, 0, tmp3); - tcg_gen_shri_i32(tmp, tmp, 16); - gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); - neon_store_reg(a->vd, 1, tmp); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(a->vd, 2, tmp3); - tcg_gen_shri_i32(tmp2, tmp2, 16); - gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); - neon_store_reg(a->vd, 3, tmp2); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - - return true; -} - -static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) -{ - int vec_size = a->q ? 16 : 8; - int rd_ofs = neon_reg_offset(a->vd, 0); - int rm_ofs = neon_reg_offset(a->vm, 0); - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->size == 3) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size); - - return true; -} - -#define DO_2MISC_VEC(INSN, FN) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - return do_2misc_vec(s, a, FN); \ - } - -DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg) -DO_2MISC_VEC(VABS, tcg_gen_gvec_abs) -DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0) -DO_2MISC_VEC(VCGT0, gen_gvec_cgt0) -DO_2MISC_VEC(VCLE0, gen_gvec_cle0) -DO_2MISC_VEC(VCGE0, gen_gvec_cge0) -DO_2MISC_VEC(VCLT0, gen_gvec_clt0) - -static bool trans_VMVN(DisasContext *s, arg_2misc *a) -{ - if (a->size != 0) { - return false; - } - return do_2misc_vec(s, a, tcg_gen_gvec_not); -} - -#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \ - static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ - uint32_t rm_ofs, uint32_t oprsz, \ - uint32_t maxsz) \ - { \ - tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \ - DATA, FUNC); \ - } - -#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \ - static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ - uint32_t rm_ofs, uint32_t oprsz, \ - uint32_t maxsz) \ - { \ - tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \ - } - -WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0) -WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1) -WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0) -WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1) -WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0) -WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0) -WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0) - -#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \ - return false; \ - } \ - return do_2misc_vec(s, a, gen_##INSN); \ - } - -DO_2M_CRYPTO(AESE, aa32_aes, 0) -DO_2M_CRYPTO(AESD, aa32_aes, 0) -DO_2M_CRYPTO(AESMC, aa32_aes, 0) -DO_2M_CRYPTO(AESIMC, aa32_aes, 0) -DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) -DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) -DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) - -static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) -{ - int pass; - - /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (!fn) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vm, pass); - fn(tmp, tmp); - neon_store_reg(a->vd, pass, tmp); - } - - return true; -} - -static bool trans_VREV32(DisasContext *s, arg_2misc *a) -{ - static NeonGenOneOpFn * const fn[] = { - tcg_gen_bswap32_i32, - gen_swap_half, - NULL, - NULL, - }; - return do_2misc(s, a, fn[a->size]); -} - -static bool trans_VREV16(DisasContext *s, arg_2misc *a) -{ - if (a->size != 0) { - return false; - } - return do_2misc(s, a, gen_rev16); -} - -static bool trans_VCLS(DisasContext *s, arg_2misc *a) -{ - static NeonGenOneOpFn * const fn[] = { - gen_helper_neon_cls_s8, - gen_helper_neon_cls_s16, - gen_helper_neon_cls_s32, - NULL, - }; - return do_2misc(s, a, fn[a->size]); -} - -static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm) -{ - tcg_gen_clzi_i32(rd, rm, 32); -} - -static bool trans_VCLZ(DisasContext *s, arg_2misc *a) -{ - static NeonGenOneOpFn * const fn[] = { - gen_helper_neon_clz_u8, - gen_helper_neon_clz_u16, - do_VCLZ_32, - NULL, - }; - return do_2misc(s, a, fn[a->size]); -} - -static bool trans_VCNT(DisasContext *s, arg_2misc *a) -{ - if (a->size != 0) { - return false; - } - return do_2misc(s, a, gen_helper_neon_cnt_u8); -} - -static bool trans_VABS_F(DisasContext *s, arg_2misc *a) -{ - if (a->size != 2) { - return false; - } - /* TODO: FP16 : size == 1 */ - return do_2misc(s, a, gen_helper_vfp_abss); -} - -static bool trans_VNEG_F(DisasContext *s, arg_2misc *a) -{ - if (a->size != 2) { - return false; - } - /* TODO: FP16 : size == 1 */ - return do_2misc(s, a, gen_helper_vfp_negs); -} - -static bool trans_VRECPE(DisasContext *s, arg_2misc *a) -{ - if (a->size != 2) { - return false; - } - return do_2misc(s, a, gen_helper_recpe_u32); -} - -static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) -{ - if (a->size != 2) { - return false; - } - return do_2misc(s, a, gen_helper_rsqrte_u32); -} - -#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ - static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ - { \ - FUNC(d, cpu_env, m); \ - } - -WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) -WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16) -WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32) -WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8) -WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16) -WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32) - -static bool trans_VQABS(DisasContext *s, arg_2misc *a) -{ - static NeonGenOneOpFn * const fn[] = { - gen_VQABS_s8, - gen_VQABS_s16, - gen_VQABS_s32, - NULL, - }; - return do_2misc(s, a, fn[a->size]); -} - -static bool trans_VQNEG(DisasContext *s, arg_2misc *a) -{ - static NeonGenOneOpFn * const fn[] = { - gen_VQNEG_s8, - gen_VQNEG_s16, - gen_VQNEG_s32, - NULL, - }; - return do_2misc(s, a, fn[a->size]); -} - -static bool do_2misc_fp(DisasContext *s, arg_2misc *a, - NeonGenOneSingleOpFn *fn) -{ - int pass; - TCGv_ptr fpst; - - /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->size != 2) { - /* TODO: FP16 will be the size == 1 case */ - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(1); - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vm, pass); - fn(tmp, tmp, fpst); - neon_store_reg(a->vd, pass, tmp); - } - tcg_temp_free_ptr(fpst); - - return true; -} - -#define DO_2MISC_FP(INSN, FUNC) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - return do_2misc_fp(s, a, FUNC); \ - } - -DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32) -DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32) -DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos) -DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos) -DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs) -DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs) - -static bool trans_VRINTX(DisasContext *s, arg_2misc *a) -{ - if (!arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - return do_2misc_fp(s, a, gen_helper_rints_exact); -} - -#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \ - static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ - { \ - TCGv_i32 zero = tcg_const_i32(0); \ - FUNC(d, m, zero, fpst); \ - tcg_temp_free_i32(zero); \ - } -#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \ - static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ - { \ - TCGv_i32 zero = tcg_const_i32(0); \ - FUNC(d, zero, m, fpst); \ - tcg_temp_free_i32(zero); \ - } - -#define DO_FP_CMP0(INSN, FUNC, REV) \ - WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - return do_2misc_fp(s, a, gen_##INSN); \ - } - -DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD) -DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) -DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) -DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) -DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) - -static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode) -{ - /* - * Handle a VRINT* operation by iterating 32 bits at a time, - * with a specified rounding mode in operation. - */ - int pass; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->size != 2) { - /* TODO: FP16 will be the size == 1 case */ - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(1); - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vm, pass); - gen_helper_rints(tmp, tmp, fpst); - neon_store_reg(a->vd, pass, tmp); - } - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_ptr(fpst); - - return true; -} - -#define DO_VRINT(INSN, RMODE) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - return do_vrint(s, a, RMODE); \ - } - -DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) -DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) -DO_VRINT(VRINTZ, FPROUNDING_ZERO) -DO_VRINT(VRINTM, FPROUNDING_NEGINF) -DO_VRINT(VRINTP, FPROUNDING_POSINF) - -static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed) -{ - /* - * Handle a VCVT* operation by iterating 32 bits at a time, - * with a specified rounding mode in operation. - */ - int pass; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode, tcg_shift; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->size != 2) { - /* TODO: FP16 will be the size == 1 case */ - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(1); - tcg_shift = tcg_const_i32(0); - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp = neon_load_reg(a->vm, pass); - if (is_signed) { - gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst); - } else { - gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst); - } - neon_store_reg(a->vd, pass, tmp); - } - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_i32(tcg_shift); - tcg_temp_free_ptr(fpst); - - return true; -} - -#define DO_VCVT(INSN, RMODE, SIGNED) \ - static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ - { \ - return do_vcvt(s, a, RMODE, SIGNED); \ - } - -DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false) -DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true) -DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false) -DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true) -DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) -DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) -DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) -DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) - -static bool trans_VSWP(DisasContext *s, arg_2misc *a) -{ - TCGv_i64 rm, rd; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (a->size != 0) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - rm = tcg_temp_new_i64(); - rd = tcg_temp_new_i64(); - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { - neon_load_reg64(rm, a->vm + pass); - neon_load_reg64(rd, a->vd + pass); - neon_store_reg64(rm, a->vd + pass); - neon_store_reg64(rd, a->vm + pass); - } - tcg_temp_free_i64(rm); - tcg_temp_free_i64(rd); - - return true; -} -static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) -{ - TCGv_i32 rd, tmp; - - rd = tcg_temp_new_i32(); - tmp = tcg_temp_new_i32(); - - tcg_gen_shli_i32(rd, t0, 8); - tcg_gen_andi_i32(rd, rd, 0xff00ff00); - tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); - tcg_gen_or_i32(rd, rd, tmp); - - tcg_gen_shri_i32(t1, t1, 8); - tcg_gen_andi_i32(t1, t1, 0x00ff00ff); - tcg_gen_andi_i32(tmp, t0, 0xff00ff00); - tcg_gen_or_i32(t1, t1, tmp); - tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); -} - -static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) -{ - TCGv_i32 rd, tmp; - - rd = tcg_temp_new_i32(); - tmp = tcg_temp_new_i32(); - - tcg_gen_shli_i32(rd, t0, 16); - tcg_gen_andi_i32(tmp, t1, 0xffff); - tcg_gen_or_i32(rd, rd, tmp); - tcg_gen_shri_i32(t1, t1, 16); - tcg_gen_andi_i32(tmp, t0, 0xffff0000); - tcg_gen_or_i32(t1, t1, tmp); - tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); -} - -static bool trans_VTRN(DisasContext *s, arg_2misc *a) -{ - TCGv_i32 tmp, tmp2; - int pass; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vm) & a->q) { - return false; - } - - if (a->size == 3) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (a->size == 2) { - for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { - tmp = neon_load_reg(a->vm, pass); - tmp2 = neon_load_reg(a->vd, pass + 1); - neon_store_reg(a->vm, pass, tmp2); - neon_store_reg(a->vd, pass + 1, tmp); - } - } else { - for (pass = 0; pass < (a->q ? 4 : 2); pass++) { - tmp = neon_load_reg(a->vm, pass); - tmp2 = neon_load_reg(a->vd, pass); - if (a->size == 0) { - gen_neon_trn_u8(tmp, tmp2); - } else { - gen_neon_trn_u16(tmp, tmp2); - } - neon_store_reg(a->vm, pass, tmp2); - neon_store_reg(a->vd, pass, tmp); - } - } - return true; -} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 88a2fb271d..8c7fbbd503 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -100,7 +100,7 @@ static inline int msz_dtype(DisasContext *s, int msz) * Include the generated decoder. */ -#include "decode-sve.inc.c" +#include "decode-sve.c.inc" /* * Implement all of the translator functions referenced by the decoder. diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc new file mode 100644 index 0000000000..2d63fa0d39 --- /dev/null +++ b/target/arm/translate-vfp.c.inc @@ -0,0 +1,2865 @@ +/* + * ARM translation: AArch32 VFP instructions + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2005-2007 CodeSourcery + * Copyright (c) 2007 OpenedHand, Ltd. + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * This file is intended to be included from translate.c; it uses + * some macros and definitions provided by that file. + * It might be possible to convert it to a standalone .c file eventually. + */ + +/* Include the generated VFP decoder */ +#include "decode-vfp.c.inc" +#include "decode-vfp-uncond.c.inc" + +/* + * The imm8 encodes the sign bit, enough bits to represent an exponent in + * the range 01....1xx to 10....0xx, and the most significant 4 bits of + * the mantissa; see VFPExpandImm() in the v8 ARM ARM. + */ +uint64_t vfp_expand_imm(int size, uint8_t imm8) +{ + uint64_t imm; + + switch (size) { + case MO_64: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | + extract32(imm8, 0, 6); + imm <<= 48; + break; + case MO_32: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | + (extract32(imm8, 0, 6) << 3); + imm <<= 16; + break; + case MO_16: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | + (extract32(imm8, 0, 6) << 6); + break; + default: + g_assert_not_reached(); + } + return imm; +} + +/* + * Return the offset of a 16-bit half of the specified VFP single-precision + * register. If top is true, returns the top 16 bits; otherwise the bottom + * 16 bits. + */ +static inline long vfp_f16_offset(unsigned reg, bool top) +{ + long offs = vfp_reg_offset(false, reg); +#ifdef HOST_WORDS_BIGENDIAN + if (!top) { + offs += 2; + } +#else + if (top) { + offs += 2; + } +#endif + return offs; +} + +/* + * Check that VFP access is enabled. If it is, do the necessary + * M-profile lazy-FP handling and then return true. + * If not, emit code to generate an appropriate exception and + * return false. + * The ignore_vfp_enabled argument specifies that we should ignore + * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX + * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns. + */ +static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) +{ + if (s->fp_excp_el) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(), + s->fp_excp_el); + } else { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } + return false; + } + + if (!s->vfp_enabled && !ignore_vfp_enabled) { + assert(!arm_dc_feature(s, ARM_FEATURE_M)); + unallocated_encoding(s); + return false; + } + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* Handle M-profile lazy FP state mechanics */ + + /* Trigger lazy-state preservation if necessary */ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount (and cause + * this to be the last insn in the TB). + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + s->base.is_jmp = DISAS_UPDATE_EXIT; + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact = false; + } + + /* Update ownership of FP context: set FPCCR.S to match current state */ + if (s->v8m_fpccr_s_wrong) { + TCGv_i32 tmp; + + tmp = load_cpu_field(v7m.fpccr[M_REG_S]); + if (s->v8m_secure) { + tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); + } else { + tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); + } + store_cpu_field(tmp, v7m.fpccr[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v8m_fpccr_s_wrong = false; + } + + if (s->v7m_new_fp_ctxt_needed) { + /* + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA + * and the FPSCR. + */ + TCGv_i32 control, fpscr; + uint32_t bits = R_V7M_CONTROL_FPCA_MASK; + + fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + /* + * We don't need to arrange to end the TB, because the only + * parts of FPSCR which we cache in the TB flags are the VECLEN + * and VECSTRIDE, and those don't exist for M-profile. + */ + + if (s->v8m_secure) { + bits |= R_V7M_CONTROL_SFPA_MASK; + } + control = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_ori_i32(control, control, bits); + store_cpu_field(control, v7m.control[M_REG_S]); + /* Don't need to do this for any further FP insns in this TB */ + s->v7m_new_fp_ctxt_needed = false; + } + } + + return true; +} + +/* + * The most usual kind of VFP access check, for everything except + * FMXR/FMRX to the always-available special registers. + */ +static bool vfp_access_check(DisasContext *s) +{ + return full_vfp_access_check(s, false); +} + +static bool trans_VSEL(DisasContext *s, arg_VSEL *a) +{ + uint32_t rd, rn, rm; + bool dp = a->dp; + + if (!dc_isar_feature(aa32_vsel, s)) { + return false; + } + + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { + return false; + } + + rd = a->vd; + rn = a->vn; + rm = a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + if (dp) { + TCGv_i64 frn, frm, dest; + TCGv_i64 tmp, zero, zf, nf, vf; + + zero = tcg_const_i64(0); + + frn = tcg_temp_new_i64(); + frm = tcg_temp_new_i64(); + dest = tcg_temp_new_i64(); + + zf = tcg_temp_new_i64(); + nf = tcg_temp_new_i64(); + vf = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(zf, cpu_ZF); + tcg_gen_ext_i32_i64(nf, cpu_NF); + tcg_gen_ext_i32_i64(vf, cpu_VF); + + neon_load_reg64(frn, rn); + neon_load_reg64(frm, rm); + switch (a->cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, + frn, frm); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i64(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, + frn, frm); + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i64(tmp); + break; + } + neon_store_reg64(dest, rd); + tcg_temp_free_i64(frn); + tcg_temp_free_i64(frm); + tcg_temp_free_i64(dest); + + tcg_temp_free_i64(zf); + tcg_temp_free_i64(nf); + tcg_temp_free_i64(vf); + + tcg_temp_free_i64(zero); + } else { + TCGv_i32 frn, frm, dest; + TCGv_i32 tmp, zero; + + zero = tcg_const_i32(0); + + frn = tcg_temp_new_i32(); + frm = tcg_temp_new_i32(); + dest = tcg_temp_new_i32(); + neon_load_reg32(frn, rn); + neon_load_reg32(frm, rm); + switch (a->cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, + frn, frm); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, + frn, frm); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i32(tmp); + break; + } + neon_store_reg32(dest, rd); + tcg_temp_free_i32(frn); + tcg_temp_free_i32(frm); + tcg_temp_free_i32(dest); + + tcg_temp_free_i32(zero); + } + + return true; +} + +/* + * Table for converting the most common AArch32 encoding of + * rounding mode to arm_fprounding order (which matches the + * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). + */ +static const uint8_t fp_decode_rm[] = { + FPROUNDING_TIEAWAY, + FPROUNDING_TIEEVEN, + FPROUNDING_POSINF, + FPROUNDING_NEGINF, +}; + +static bool trans_VRINT(DisasContext *s, arg_VRINT *a) +{ + uint32_t rd, rm; + bool dp = a->dp; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode; + int rounding = fp_decode_rm[a->rm]; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { + return false; + } + + rd = a->vd; + rm = a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(0); + + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + + if (dp) { + TCGv_i64 tcg_op; + TCGv_i64 tcg_res; + tcg_op = tcg_temp_new_i64(); + tcg_res = tcg_temp_new_i64(); + neon_load_reg64(tcg_op, rm); + gen_helper_rintd(tcg_res, tcg_op, fpst); + neon_store_reg64(tcg_res, rd); + tcg_temp_free_i64(tcg_op); + tcg_temp_free_i64(tcg_res); + } else { + TCGv_i32 tcg_op; + TCGv_i32 tcg_res; + tcg_op = tcg_temp_new_i32(); + tcg_res = tcg_temp_new_i32(); + neon_load_reg32(tcg_op, rm); + gen_helper_rints(tcg_res, tcg_op, fpst); + neon_store_reg32(tcg_res, rd); + tcg_temp_free_i32(tcg_op); + tcg_temp_free_i32(tcg_res); + } + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT(DisasContext *s, arg_VCVT *a) +{ + uint32_t rd, rm; + bool dp = a->dp; + TCGv_ptr fpst; + TCGv_i32 tcg_rmode, tcg_shift; + int rounding = fp_decode_rm[a->rm]; + bool is_signed = a->op; + + if (!dc_isar_feature(aa32_vcvt_dr, s)) { + return false; + } + + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + rd = a->vd; + rm = a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(0); + + tcg_shift = tcg_const_i32(0); + + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + + if (dp) { + TCGv_i64 tcg_double, tcg_res; + TCGv_i32 tcg_tmp; + tcg_double = tcg_temp_new_i64(); + tcg_res = tcg_temp_new_i64(); + tcg_tmp = tcg_temp_new_i32(); + neon_load_reg64(tcg_double, rm); + if (is_signed) { + gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); + } else { + gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); + } + tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); + neon_store_reg32(tcg_tmp, rd); + tcg_temp_free_i32(tcg_tmp); + tcg_temp_free_i64(tcg_res); + tcg_temp_free_i64(tcg_double); + } else { + TCGv_i32 tcg_single, tcg_res; + tcg_single = tcg_temp_new_i32(); + tcg_res = tcg_temp_new_i32(); + neon_load_reg32(tcg_single, rm); + if (is_signed) { + gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); + } else { + gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); + } + neon_store_reg32(tcg_res, rd); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_single); + } + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + + tcg_temp_free_i32(tcg_shift); + + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) +{ + /* VMOV scalar to general purpose register */ + TCGv_i32 tmp; + int pass; + uint32_t offset; + + /* SIZE == 2 is a VFP instruction; otherwise NEON. */ + if (a->size == 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + return false; + } + + offset = a->index << a->size; + pass = extract32(offset, 2, 1); + offset = extract32(offset, 0, 2) * 8; + + if (!vfp_access_check(s)) { + return true; + } + + tmp = neon_load_reg(a->vn, pass); + switch (a->size) { + case 0: + if (offset) { + tcg_gen_shri_i32(tmp, tmp, offset); + } + if (a->u) { + gen_uxtb(tmp); + } else { + gen_sxtb(tmp); + } + break; + case 1: + if (a->u) { + if (offset) { + tcg_gen_shri_i32(tmp, tmp, 16); + } else { + gen_uxth(tmp); + } + } else { + if (offset) { + tcg_gen_sari_i32(tmp, tmp, 16); + } else { + gen_sxth(tmp); + } + } + break; + case 2: + break; + } + store_reg(s, a->rt, tmp); + + return true; +} + +static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) +{ + /* VMOV general purpose register to scalar */ + TCGv_i32 tmp, tmp2; + int pass; + uint32_t offset; + + /* SIZE == 2 is a VFP instruction; otherwise NEON. */ + if (a->size == 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + return false; + } + + offset = a->index << a->size; + pass = extract32(offset, 2, 1); + offset = extract32(offset, 0, 2) * 8; + + if (!vfp_access_check(s)) { + return true; + } + + tmp = load_reg(s, a->rt); + switch (a->size) { + case 0: + tmp2 = neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); + tcg_temp_free_i32(tmp2); + break; + case 1: + tmp2 = neon_load_reg(a->vn, pass); + tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); + tcg_temp_free_i32(tmp2); + break; + case 2: + break; + } + neon_store_reg(a->vn, pass, tmp); + + return true; +} + +static bool trans_VDUP(DisasContext *s, arg_VDUP *a) +{ + /* VDUP (general purpose register) */ + TCGv_i32 tmp; + int size, vec_size; + + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { + return false; + } + + if (a->b && a->e) { + return false; + } + + if (a->q && (a->vn & 1)) { + return false; + } + + vec_size = a->q ? 16 : 8; + if (a->b) { + size = 0; + } else if (a->e) { + size = 1; + } else { + size = 2; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = load_reg(s, a->rt); + tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + vec_size, vec_size, tmp); + tcg_temp_free_i32(tmp); + + return true; +} + +static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) +{ + TCGv_i32 tmp; + bool ignore_vfp_enabled = false; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. + * Accesses to R15 are UNPREDICTABLE; we choose to undef. + * (FPSCR -> r15 is a special case which writes to the PSR flags.) + */ + if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) { + return false; + } + } + + switch (a->reg) { + case ARM_VFP_FPSID: + /* + * VFPv2 allows access to FPSID from userspace; VFPv3 restricts + * all ID registers to privileged access only. + */ + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { + return false; + } + ignore_vfp_enabled = true; + break; + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) { + return false; + } + ignore_vfp_enabled = true; + break; + case ARM_VFP_MVFR2: + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + ignore_vfp_enabled = true; + break; + case ARM_VFP_FPSCR: + break; + case ARM_VFP_FPEXC: + if (IS_USER(s)) { + return false; + } + ignore_vfp_enabled = true; + break; + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + /* Not present in VFPv3 */ + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { + return false; + } + break; + default: + return false; + } + + if (!full_vfp_access_check(s, ignore_vfp_enabled)) { + return true; + } + + if (a->l) { + /* VMRS, move VFP special register to gp register */ + switch (a->reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + case ARM_VFP_FPSID: + if (s->current_el == 1) { + TCGv_i32 tcg_reg, tcg_rt; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + tcg_reg = tcg_const_i32(a->reg); + tcg_rt = tcg_const_i32(a->rt); + gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); + tcg_temp_free_i32(tcg_reg); + tcg_temp_free_i32(tcg_rt); + } + /* fall through */ + case ARM_VFP_FPEXC: + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + tmp = load_cpu_field(vfp.xregs[a->reg]); + break; + case ARM_VFP_FPSCR: + if (a->rt == 15) { + tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + } else { + tmp = tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + } + break; + default: + g_assert_not_reached(); + } + + if (a->rt == 15) { + /* Set the 4 flag bits in the CPSR. */ + gen_set_nzcv(tmp); + tcg_temp_free_i32(tmp); + } else { + store_reg(s, a->rt, tmp); + } + } else { + /* VMSR, move gp register to VFP special register */ + switch (a->reg) { + case ARM_VFP_FPSID: + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + /* Writes are ignored. */ + break; + case ARM_VFP_FPSCR: + tmp = load_reg(s, a->rt); + gen_helper_vfp_set_fpscr(cpu_env, tmp); + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + break; + case ARM_VFP_FPEXC: + /* + * TODO: VFP subarchitecture support. + * For now, keep the EN bit only + */ + tmp = load_reg(s, a->rt); + tcg_gen_andi_i32(tmp, tmp, 1 << 30); + store_cpu_field(tmp, vfp.xregs[a->reg]); + gen_lookup_tb(s); + break; + case ARM_VFP_FPINST: + case ARM_VFP_FPINST2: + tmp = load_reg(s, a->rt); + store_cpu_field(tmp, vfp.xregs[a->reg]); + break; + default: + g_assert_not_reached(); + } + } + + return true; +} + +static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) +{ + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (a->l) { + /* VFP to general purpose register */ + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vn); + if (a->rt == 15) { + /* Set the 4 flag bits in the CPSR. */ + gen_set_nzcv(tmp); + tcg_temp_free_i32(tmp); + } else { + store_reg(s, a->rt, tmp); + } + } else { + /* general purpose register to VFP */ + tmp = load_reg(s, a->rt); + neon_store_reg32(tmp, a->vn); + tcg_temp_free_i32(tmp); + } + + return true; +} + +static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) +{ + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + /* + * VMOV between two general-purpose registers and two single precision + * floating point registers + */ + if (!vfp_access_check(s)) { + return true; + } + + if (a->op) { + /* fpreg to gpreg */ + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + store_reg(s, a->rt, tmp); + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm + 1); + store_reg(s, a->rt2, tmp); + } else { + /* gpreg to fpreg */ + tmp = load_reg(s, a->rt); + neon_store_reg32(tmp, a->vm); + tcg_temp_free_i32(tmp); + tmp = load_reg(s, a->rt2); + neon_store_reg32(tmp, a->vm + 1); + tcg_temp_free_i32(tmp); + } + + return true; +} + +static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) +{ + TCGv_i32 tmp; + + /* + * VMOV between two general-purpose registers and one double precision + * floating point register. Note that this does not require support + * for double precision arithmetic. + */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (a->op) { + /* fpreg to gpreg */ + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm * 2); + store_reg(s, a->rt, tmp); + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm * 2 + 1); + store_reg(s, a->rt2, tmp); + } else { + /* gpreg to fpreg */ + tmp = load_reg(s, a->rt); + neon_store_reg32(tmp, a->vm * 2); + tcg_temp_free_i32(tmp); + tmp = load_reg(s, a->rt2); + neon_store_reg32(tmp, a->vm * 2 + 1); + tcg_temp_free_i32(tmp); + } + + return true; +} + +static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) +{ + uint32_t offset; + TCGv_i32 addr, tmp; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + offset = a->imm << 2; + if (!a->u) { + offset = -offset; + } + + /* For thumb, use of PC is UNPREDICTABLE. */ + addr = add_reg_for_lit(s, a->rn, offset); + tmp = tcg_temp_new_i32(); + if (a->l) { + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd); + } else { + neon_load_reg32(tmp, a->vd); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + + return true; +} + +static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) +{ + uint32_t offset; + TCGv_i32 addr; + TCGv_i64 tmp; + + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + offset = a->imm << 2; + if (!a->u) { + offset = -offset; + } + + /* For thumb, use of PC is UNPREDICTABLE. */ + addr = add_reg_for_lit(s, a->rn, offset); + tmp = tcg_temp_new_i64(); + if (a->l) { + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd); + } else { + neon_load_reg64(tmp, a->vd); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + } + tcg_temp_free_i64(tmp); + tcg_temp_free_i32(addr); + + return true; +} + +static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) +{ + uint32_t offset; + TCGv_i32 addr, tmp; + int i, n; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + n = a->imm; + + if (n == 0 || (a->vd + n) > 32) { + /* + * UNPREDICTABLE cases for bad immediates: we choose to + * UNDEF to avoid generating huge numbers of TCG ops + */ + return false; + } + if (a->rn == 15 && a->w) { + /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* For thumb, use of PC is UNPREDICTABLE. */ + addr = add_reg_for_lit(s, a->rn, 0); + if (a->p) { + /* pre-decrement */ + tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * Here 'addr' is the lowest address we will store to, + * and is either the old SP (if post-increment) or + * the new SP (if pre-decrement). For post-increment + * where the old value is below the limit and the new + * value is above, it is UNKNOWN whether the limit check + * triggers; we choose to trigger. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + offset = 4; + tmp = tcg_temp_new_i32(); + for (i = 0; i < n; i++) { + if (a->l) { + /* load */ + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + neon_store_reg32(tmp, a->vd + i); + } else { + /* store */ + neon_load_reg32(tmp, a->vd + i); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } + tcg_gen_addi_i32(addr, addr, offset); + } + tcg_temp_free_i32(tmp); + if (a->w) { + /* writeback */ + if (a->p) { + offset = -offset * n; + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + + return true; +} + +static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) +{ + uint32_t offset; + TCGv_i32 addr; + TCGv_i64 tmp; + int i, n; + + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + n = a->imm >> 1; + + if (n == 0 || (a->vd + n) > 32 || n > 16) { + /* + * UNPREDICTABLE cases for bad immediates: we choose to + * UNDEF to avoid generating huge numbers of TCG ops + */ + return false; + } + if (a->rn == 15 && a->w) { + /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* For thumb, use of PC is UNPREDICTABLE. */ + addr = add_reg_for_lit(s, a->rn, 0); + if (a->p) { + /* pre-decrement */ + tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * Here 'addr' is the lowest address we will store to, + * and is either the old SP (if post-increment) or + * the new SP (if pre-decrement). For post-increment + * where the old value is below the limit and the new + * value is above, it is UNKNOWN whether the limit check + * triggers; we choose to trigger. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + offset = 8; + tmp = tcg_temp_new_i64(); + for (i = 0; i < n; i++) { + if (a->l) { + /* load */ + gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + neon_store_reg64(tmp, a->vd + i); + } else { + /* store */ + neon_load_reg64(tmp, a->vd + i); + gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + } + tcg_gen_addi_i32(addr, addr, offset); + } + tcg_temp_free_i64(tmp); + if (a->w) { + /* writeback */ + if (a->p) { + offset = -offset * n; + } else if (a->imm & 1) { + offset = 4; + } else { + offset = 0; + } + + if (offset != 0) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + + return true; +} + +/* + * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp(). + * The callback should emit code to write a value to vd. If + * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd + * will contain the old value of the relevant VFP register; + * otherwise it must be written to only. + */ +typedef void VFPGen3OpSPFn(TCGv_i32 vd, + TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst); +typedef void VFPGen3OpDPFn(TCGv_i64 vd, + TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst); + +/* + * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp(). + * The callback should emit code to write a value to vd (which + * should be written to only). + */ +typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); +typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); + +/* + * Return true if the specified S reg is in a scalar bank + * (ie if it is s0..s7) + */ +static inline bool vfp_sreg_is_scalar(int reg) +{ + return (reg & 0x18) == 0; +} + +/* + * Return true if the specified D reg is in a scalar bank + * (ie if it is d0..d3 or d16..d19) + */ +static inline bool vfp_dreg_is_scalar(int reg) +{ + return (reg & 0xc) == 0; +} + +/* + * Advance the S reg number forwards by delta within its bank + * (ie increment the low 3 bits but leave the rest the same) + */ +static inline int vfp_advance_sreg(int reg, int delta) +{ + return ((reg + delta) & 0x7) | (reg & ~0x7); +} + +/* + * Advance the D reg number forwards by delta within its bank + * (ie increment the low 2 bits but leave the rest the same) + */ +static inline int vfp_advance_dreg(int reg, int delta) +{ + return ((reg + delta) & 0x3) | (reg & ~0x3); +} + +/* + * Perform a 3-operand VFP data processing instruction. fn is the + * callback to do the actual operation; this function deals with the + * code to handle looping around for VFP vector processing. + */ +static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, + int vd, int vn, int vm, bool reads_vd) +{ + uint32_t delta_m = 0; + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i32 f0, f1, fd; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_sreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = s->vec_stride + 1; + + if (vfp_sreg_is_scalar(vm)) { + /* mixed scalar/vector */ + delta_m = 0; + } else { + /* vector */ + delta_m = delta_d; + } + } + } + + f0 = tcg_temp_new_i32(); + f1 = tcg_temp_new_i32(); + fd = tcg_temp_new_i32(); + fpst = get_fpstatus_ptr(0); + + neon_load_reg32(f0, vn); + neon_load_reg32(f1, vm); + + for (;;) { + if (reads_vd) { + neon_load_reg32(fd, vd); + } + fn(fd, f0, f1, fpst); + neon_store_reg32(fd, vd); + + if (veclen == 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_sreg(vd, delta_d); + vn = vfp_advance_sreg(vn, delta_d); + neon_load_reg32(f0, vn); + if (delta_m) { + vm = vfp_advance_sreg(vm, delta_m); + neon_load_reg32(f1, vm); + } + } + + tcg_temp_free_i32(f0); + tcg_temp_free_i32(f1); + tcg_temp_free_i32(fd); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, + int vd, int vn, int vm, bool reads_vd) +{ + uint32_t delta_m = 0; + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i64 f0, f1, fd; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_dreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = (s->vec_stride >> 1) + 1; + + if (vfp_dreg_is_scalar(vm)) { + /* mixed scalar/vector */ + delta_m = 0; + } else { + /* vector */ + delta_m = delta_d; + } + } + } + + f0 = tcg_temp_new_i64(); + f1 = tcg_temp_new_i64(); + fd = tcg_temp_new_i64(); + fpst = get_fpstatus_ptr(0); + + neon_load_reg64(f0, vn); + neon_load_reg64(f1, vm); + + for (;;) { + if (reads_vd) { + neon_load_reg64(fd, vd); + } + fn(fd, f0, f1, fpst); + neon_store_reg64(fd, vd); + + if (veclen == 0) { + break; + } + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_dreg(vd, delta_d); + vn = vfp_advance_dreg(vn, delta_d); + neon_load_reg64(f0, vn); + if (delta_m) { + vm = vfp_advance_dreg(vm, delta_m); + neon_load_reg64(f1, vm); + } + } + + tcg_temp_free_i64(f0); + tcg_temp_free_i64(f1); + tcg_temp_free_i64(fd); + tcg_temp_free_ptr(fpst); + + return true; +} + +static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) +{ + uint32_t delta_m = 0; + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i32 f0, fd; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_sreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = s->vec_stride + 1; + + if (vfp_sreg_is_scalar(vm)) { + /* mixed scalar/vector */ + delta_m = 0; + } else { + /* vector */ + delta_m = delta_d; + } + } + } + + f0 = tcg_temp_new_i32(); + fd = tcg_temp_new_i32(); + + neon_load_reg32(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg32(fd, vd); + + if (veclen == 0) { + break; + } + + if (delta_m == 0) { + /* single source one-many */ + while (veclen--) { + vd = vfp_advance_sreg(vd, delta_d); + neon_store_reg32(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_sreg(vd, delta_d); + vm = vfp_advance_sreg(vm, delta_m); + neon_load_reg32(f0, vm); + } + + tcg_temp_free_i32(f0); + tcg_temp_free_i32(fd); + + return true; +} + +static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) +{ + uint32_t delta_m = 0; + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i64 f0, fd; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_dreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = (s->vec_stride >> 1) + 1; + + if (vfp_dreg_is_scalar(vm)) { + /* mixed scalar/vector */ + delta_m = 0; + } else { + /* vector */ + delta_m = delta_d; + } + } + } + + f0 = tcg_temp_new_i64(); + fd = tcg_temp_new_i64(); + + neon_load_reg64(f0, vm); + + for (;;) { + fn(fd, f0); + neon_store_reg64(fd, vd); + + if (veclen == 0) { + break; + } + + if (delta_m == 0) { + /* single source one-many */ + while (veclen--) { + vd = vfp_advance_dreg(vd, delta_d); + neon_store_reg64(fd, vd); + } + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_dreg(vd, delta_d); + vd = vfp_advance_dreg(vm, delta_m); + neon_load_reg64(f0, vm); + } + + tcg_temp_free_i64(f0); + tcg_temp_free_i64(fd); + + return true; +} + +static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* Note that order of inputs to the add matters for NaNs */ + TCGv_i32 tmp = tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a) +{ + return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* Note that order of inputs to the add matters for NaNs */ + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a) +{ + return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true); +} + +static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* + * VMLS: vd = vd + -(vn * vm) + * Note that order of inputs to the add matters for NaNs. + */ + TCGv_i32 tmp = tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(tmp, tmp); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a) +{ + return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* + * VMLS: vd = vd + -(vn * vm) + * Note that order of inputs to the add matters for NaNs. + */ + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(tmp, tmp); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a) +{ + return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* + * VNMLS: -fd + (fn * fm) + * Note that it isn't valid to replace (-A + B) with (B - A) or similar + * plausible looking simplifications because this will give wrong results + * for NaNs. + */ + TCGv_i32 tmp = tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(vd, vd); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* + * VNMLS: -fd + (fn * fm) + * Note that it isn't valid to replace (-A + B) with (B - A) or similar + * plausible looking simplifications because this will give wrong results + * for NaNs. + */ + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(vd, vd); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a) +{ + return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* VNMLA: -fd + -(fn * fm) */ + TCGv_i32 tmp = tcg_temp_new_i32(); + + gen_helper_vfp_muls(tmp, vn, vm, fpst); + gen_helper_vfp_negs(tmp, tmp); + gen_helper_vfp_negs(vd, vd); + gen_helper_vfp_adds(vd, vd, tmp, fpst); + tcg_temp_free_i32(tmp); +} + +static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true); +} + +static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* VNMLA: -fd + (fn * fm) */ + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_helper_vfp_muld(tmp, vn, vm, fpst); + gen_helper_vfp_negd(tmp, tmp); + gen_helper_vfp_negd(vd, vd); + gen_helper_vfp_addd(vd, vd, tmp, fpst); + tcg_temp_free_i64(tmp); +} + +static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a) +{ + return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); +} + +static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false); +} + +static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false); +} + +static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muls(vd, vn, vm, fpst); + gen_helper_vfp_negs(vd, vd); +} + +static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a) +{ + return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false); +} + +static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) +{ + /* VNMUL: -(fn * fm) */ + gen_helper_vfp_muld(vd, vn, vm, fpst); + gen_helper_vfp_negd(vd, vd); +} + +static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a) +{ + return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); +} + +static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false); +} + +static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false); +} + +static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false); +} + +static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false); +} + +static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a) +{ + return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false); +} + +static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a) +{ + return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false); +} + +static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_minnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, + a->vd, a->vn, a->vm, false); +} + +static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) +{ + /* + * VFNMA : fd = muladd(-fd, fn, fm) + * VFNMS : fd = muladd(-fd, -fn, fm) + * VFMA : fd = muladd( fd, fn, fm) + * VFMS : fd = muladd( fd, -fn, fm) + * + * These are fused multiply-add, and must be done as one floating + * point operation with no rounding between the multiplication and + * addition steps. NB that doing the negations here as separate + * steps is correct : an input NaN should come out with its sign + * bit flipped if it is a negated-input. + */ + TCGv_ptr fpst; + TCGv_i32 vn, vm, vd; + + /* + * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* + * In v7A, UNPREDICTABLE with non-zero vector length/stride; from + * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. + */ + if (s->vec_len != 0 || s->vec_stride != 0) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vn = tcg_temp_new_i32(); + vm = tcg_temp_new_i32(); + vd = tcg_temp_new_i32(); + + neon_load_reg32(vn, a->vn); + neon_load_reg32(vm, a->vm); + if (neg_n) { + /* VFNMS, VFMS */ + gen_helper_vfp_negs(vn, vn); + } + neon_load_reg32(vd, a->vd); + if (neg_d) { + /* VFNMA, VFNMS */ + gen_helper_vfp_negs(vd, vd); + } + fpst = get_fpstatus_ptr(0); + gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); + neon_store_reg32(vd, a->vd); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(vn); + tcg_temp_free_i32(vm); + tcg_temp_free_i32(vd); + + return true; +} + +static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) +{ + return do_vfm_sp(s, a, false, false); +} + +static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) +{ + return do_vfm_sp(s, a, true, false); +} + +static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) +{ + return do_vfm_sp(s, a, false, true); +} + +static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) +{ + return do_vfm_sp(s, a, true, true); +} + +static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) +{ + /* + * VFNMA : fd = muladd(-fd, fn, fm) + * VFNMS : fd = muladd(-fd, -fn, fm) + * VFMA : fd = muladd( fd, fn, fm) + * VFMS : fd = muladd( fd, -fn, fm) + * + * These are fused multiply-add, and must be done as one floating + * point operation with no rounding between the multiplication and + * addition steps. NB that doing the negations here as separate + * steps is correct : an input NaN should come out with its sign + * bit flipped if it is a negated-input. + */ + TCGv_ptr fpst; + TCGv_i64 vn, vm, vd; + + /* + * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* + * In v7A, UNPREDICTABLE with non-zero vector length/stride; from + * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. + */ + if (s->vec_len != 0 || s->vec_stride != 0) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vn = tcg_temp_new_i64(); + vm = tcg_temp_new_i64(); + vd = tcg_temp_new_i64(); + + neon_load_reg64(vn, a->vn); + neon_load_reg64(vm, a->vm); + if (neg_n) { + /* VFNMS, VFMS */ + gen_helper_vfp_negd(vn, vn); + } + neon_load_reg64(vd, a->vd); + if (neg_d) { + /* VFNMA, VFNMS */ + gen_helper_vfp_negd(vd, vd); + } + fpst = get_fpstatus_ptr(0); + gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); + neon_store_reg64(vd, a->vd); + + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(vn); + tcg_temp_free_i64(vm); + tcg_temp_free_i64(vd); + + return true; +} + +static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) +{ + return do_vfm_dp(s, a, false, false); +} + +static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) +{ + return do_vfm_dp(s, a, true, false); +} + +static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) +{ + return do_vfm_dp(s, a, false, true); +} + +static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) +{ + return do_vfm_dp(s, a, true, true); +} + +static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) +{ + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i32 fd; + uint32_t vd; + + vd = a->vd; + + if (!dc_isar_feature(aa32_fpsp_v3, s)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_sreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = s->vec_stride + 1; + } + } + + fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); + + for (;;) { + neon_store_reg32(fd, vd); + + if (veclen == 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_sreg(vd, delta_d); + } + + tcg_temp_free_i32(fd); + return true; +} + +static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) +{ + uint32_t delta_d = 0; + int veclen = s->vec_len; + TCGv_i64 fd; + uint32_t vd; + + vd = a->vd; + + if (!dc_isar_feature(aa32_fpdp_v3, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + /* Figure out what type of vector operation this is. */ + if (vfp_dreg_is_scalar(vd)) { + /* scalar */ + veclen = 0; + } else { + delta_d = (s->vec_stride >> 1) + 1; + } + } + + fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); + + for (;;) { + neon_store_reg64(fd, vd); + + if (veclen == 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = vfp_advance_dreg(vd, delta_d); + } + + tcg_temp_free_i64(fd); + return true; +} + +static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a) +{ + return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm); +} + +static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a) +{ + return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm); +} + +static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a) +{ + return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm); +} + +static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) +{ + return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); +} + +static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a) +{ + return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm); +} + +static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) +{ + return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); +} + +static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) +{ + gen_helper_vfp_sqrts(vd, vm, cpu_env); +} + +static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a) +{ + return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm); +} + +static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) +{ + gen_helper_vfp_sqrtd(vd, vm, cpu_env); +} + +static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a) +{ + return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); +} + +static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) +{ + TCGv_i32 vd, vm; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + /* Vm/M bits must be zero for the Z variant */ + if (a->z && a->vm != 0) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd = tcg_temp_new_i32(); + vm = tcg_temp_new_i32(); + + neon_load_reg32(vd, a->vd); + if (a->z) { + tcg_gen_movi_i32(vm, 0); + } else { + neon_load_reg32(vm, a->vm); + } + + if (a->e) { + gen_helper_vfp_cmpes(vd, vm, cpu_env); + } else { + gen_helper_vfp_cmps(vd, vm, cpu_env); + } + + tcg_temp_free_i32(vd); + tcg_temp_free_i32(vm); + + return true; +} + +static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) +{ + TCGv_i64 vd, vm; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* Vm/M bits must be zero for the Z variant */ + if (a->z && a->vm != 0) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd = tcg_temp_new_i64(); + vm = tcg_temp_new_i64(); + + neon_load_reg64(vd, a->vd); + if (a->z) { + tcg_gen_movi_i64(vm, 0); + } else { + neon_load_reg64(vm, a->vm); + } + + if (a->e) { + gen_helper_vfp_cmped(vd, vm, cpu_env); + } else { + gen_helper_vfp_cmpd(vd, vm, cpu_env); + } + + tcg_temp_free_i64(vd); + tcg_temp_free_i64(vm); + + return true; +} + +static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + ahp_mode = get_ahp_flag(); + tmp = tcg_temp_new_i32(); + /* The T bit tells us if we want the low or high 16 bits of Vm */ + tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + TCGv_i64 vd; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + ahp_mode = get_ahp_flag(); + tmp = tcg_temp_new_i32(); + /* The T bit tells us if we want the low or high 16 bits of Vm */ + tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + vd = tcg_temp_new_i64(); + gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + tcg_temp_free_i64(vd); + return true; +} + +static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_fp16_spconv, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + ahp_mode = get_ahp_flag(); + tmp = tcg_temp_new_i32(); + + neon_load_reg32(tmp, a->vm); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); + tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) +{ + TCGv_ptr fpst; + TCGv_i32 ahp_mode; + TCGv_i32 tmp; + TCGv_i64 vm; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + ahp_mode = get_ahp_flag(); + tmp = tcg_temp_new_i32(); + vm = tcg_temp_new_i64(); + + neon_load_reg64(vm, a->vm); + gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); + tcg_temp_free_i64(vm); + tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_temp_free_i32(ahp_mode); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + gen_helper_rints(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + gen_helper_rintd(tmp, tmp, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + TCGv_i32 tcg_rmode; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_rints(tmp, tmp, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + TCGv_i32 tcg_rmode; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_rintd(tmp, tmp, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + tcg_temp_free_i32(tcg_rmode); + return true; +} + +static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) +{ + TCGv_ptr fpst; + TCGv_i32 tmp; + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i32(); + neon_load_reg32(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + gen_helper_rints_exact(tmp, tmp, fpst); + neon_store_reg32(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(tmp); + return true; +} + +static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) +{ + TCGv_ptr fpst; + TCGv_i64 tmp; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_vrint, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + neon_load_reg64(tmp, a->vm); + fpst = get_fpstatus_ptr(false); + gen_helper_rintd_exact(tmp, tmp, fpst); + neon_store_reg64(tmp, a->vd); + tcg_temp_free_ptr(fpst); + tcg_temp_free_i64(tmp); + return true; +} + +static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) +{ + TCGv_i64 vd; + TCGv_i32 vm; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm = tcg_temp_new_i32(); + vd = tcg_temp_new_i64(); + neon_load_reg32(vm, a->vm); + gen_helper_vfp_fcvtds(vd, vm, cpu_env); + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_i64(vd); + return true; +} + +static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) +{ + TCGv_i64 vm; + TCGv_i32 vd; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vd = tcg_temp_new_i32(); + vm = tcg_temp_new_i64(); + neon_load_reg64(vm, a->vm); + gen_helper_vfp_fcvtsd(vd, vm, cpu_env); + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i64(vm); + return true; +} + +static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm = tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + fpst = get_fpstatus_ptr(false); + if (a->s) { + /* i32 -> f32 */ + gen_helper_vfp_sitos(vm, vm, fpst); + } else { + /* u32 -> f32 */ + gen_helper_vfp_uitos(vm, vm, fpst); + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) +{ + TCGv_i32 vm; + TCGv_i64 vd; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm = tcg_temp_new_i32(); + vd = tcg_temp_new_i64(); + neon_load_reg32(vm, a->vm); + fpst = get_fpstatus_ptr(false); + if (a->s) { + /* i32 -> f64 */ + gen_helper_vfp_sitod(vd, vm, fpst); + } else { + /* u32 -> f64 */ + gen_helper_vfp_uitod(vd, vm, fpst); + } + neon_store_reg64(vd, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_i64(vd); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) +{ + TCGv_i32 vd; + TCGv_i64 vm; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + if (!dc_isar_feature(aa32_jscvt, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + vm = tcg_temp_new_i64(); + vd = tcg_temp_new_i32(); + neon_load_reg64(vm, a->vm); + gen_helper_vjcvt(vd, vm, cpu_env); + neon_store_reg32(vd, a->vd); + tcg_temp_free_i64(vm); + tcg_temp_free_i32(vd); + return true; +} + +static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) +{ + TCGv_i32 vd, shift; + TCGv_ptr fpst; + int frac_bits; + + if (!dc_isar_feature(aa32_fpsp_v3, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); + + vd = tcg_temp_new_i32(); + neon_load_reg32(vd, a->vd); + + fpst = get_fpstatus_ptr(false); + shift = tcg_const_i32(frac_bits); + + /* Switch on op:U:sx bits */ + switch (a->opc) { + case 0: + gen_helper_vfp_shtos(vd, vd, shift, fpst); + break; + case 1: + gen_helper_vfp_sltos(vd, vd, shift, fpst); + break; + case 2: + gen_helper_vfp_uhtos(vd, vd, shift, fpst); + break; + case 3: + gen_helper_vfp_ultos(vd, vd, shift, fpst); + break; + case 4: + gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst); + break; + case 5: + gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst); + break; + case 6: + gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst); + break; + case 7: + gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst); + break; + default: + g_assert_not_reached(); + } + + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i32(shift); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) +{ + TCGv_i64 vd; + TCGv_i32 shift; + TCGv_ptr fpst; + int frac_bits; + + if (!dc_isar_feature(aa32_fpdp_v3, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); + + vd = tcg_temp_new_i64(); + neon_load_reg64(vd, a->vd); + + fpst = get_fpstatus_ptr(false); + shift = tcg_const_i32(frac_bits); + + /* Switch on op:U:sx bits */ + switch (a->opc) { + case 0: + gen_helper_vfp_shtod(vd, vd, shift, fpst); + break; + case 1: + gen_helper_vfp_sltod(vd, vd, shift, fpst); + break; + case 2: + gen_helper_vfp_uhtod(vd, vd, shift, fpst); + break; + case 3: + gen_helper_vfp_ultod(vd, vd, shift, fpst); + break; + case 4: + gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst); + break; + case 5: + gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst); + break; + case 6: + gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst); + break; + case 7: + gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst); + break; + default: + g_assert_not_reached(); + } + + neon_store_reg64(vd, a->vd); + tcg_temp_free_i64(vd); + tcg_temp_free_i32(shift); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) +{ + TCGv_i32 vm; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + vm = tcg_temp_new_i32(); + neon_load_reg32(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizs(vm, vm, fpst); + } else { + gen_helper_vfp_tosis(vm, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizs(vm, vm, fpst); + } else { + gen_helper_vfp_touis(vm, vm, fpst); + } + } + neon_store_reg32(vm, a->vd); + tcg_temp_free_i32(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) +{ + TCGv_i32 vd; + TCGv_i64 vm; + TCGv_ptr fpst; + + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(false); + vm = tcg_temp_new_i64(); + vd = tcg_temp_new_i32(); + neon_load_reg64(vm, a->vm); + + if (a->s) { + if (a->rz) { + gen_helper_vfp_tosizd(vd, vm, fpst); + } else { + gen_helper_vfp_tosid(vd, vm, fpst); + } + } else { + if (a->rz) { + gen_helper_vfp_touizd(vd, vm, fpst); + } else { + gen_helper_vfp_touid(vd, vm, fpst); + } + } + neon_store_reg32(vd, a->vd); + tcg_temp_free_i32(vd); + tcg_temp_free_i64(vm); + tcg_temp_free_ptr(fpst); + return true; +} + +/* + * Decode VLLDM and VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that vfp_access_check() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* If not secure, UNDEF. */ + if (!s->v8m_secure) { + return false; + } + /* If no fpu, NOP. */ + if (!dc_isar_feature(aa32_vfp, s)) { + return true; + } + + fptr = load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp = DISAS_UPDATE_EXIT; + return true; +} diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c deleted file mode 100644 index afa8a5f888..0000000000 --- a/target/arm/translate-vfp.inc.c +++ /dev/null @@ -1,2865 +0,0 @@ -/* - * ARM translation: AArch32 VFP instructions - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2005-2007 CodeSourcery - * Copyright (c) 2007 OpenedHand, Ltd. - * Copyright (c) 2019 Linaro, Ltd. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ - -/* Include the generated VFP decoder */ -#include "decode-vfp.inc.c" -#include "decode-vfp-uncond.inc.c" - -/* - * The imm8 encodes the sign bit, enough bits to represent an exponent in - * the range 01....1xx to 10....0xx, and the most significant 4 bits of - * the mantissa; see VFPExpandImm() in the v8 ARM ARM. - */ -uint64_t vfp_expand_imm(int size, uint8_t imm8) -{ - uint64_t imm; - - switch (size) { - case MO_64: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | - extract32(imm8, 0, 6); - imm <<= 48; - break; - case MO_32: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | - (extract32(imm8, 0, 6) << 3); - imm <<= 16; - break; - case MO_16: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | - (extract32(imm8, 0, 6) << 6); - break; - default: - g_assert_not_reached(); - } - return imm; -} - -/* - * Return the offset of a 16-bit half of the specified VFP single-precision - * register. If top is true, returns the top 16 bits; otherwise the bottom - * 16 bits. - */ -static inline long vfp_f16_offset(unsigned reg, bool top) -{ - long offs = vfp_reg_offset(false, reg); -#ifdef HOST_WORDS_BIGENDIAN - if (!top) { - offs += 2; - } -#else - if (top) { - offs += 2; - } -#endif - return offs; -} - -/* - * Check that VFP access is enabled. If it is, do the necessary - * M-profile lazy-FP handling and then return true. - * If not, emit code to generate an appropriate exception and - * return false. - * The ignore_vfp_enabled argument specifies that we should ignore - * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX - * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns. - */ -static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) -{ - if (s->fp_excp_el) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(), - s->fp_excp_el); - } else { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); - } - return false; - } - - if (!s->vfp_enabled && !ignore_vfp_enabled) { - assert(!arm_dc_feature(s, ARM_FEATURE_M)); - unallocated_encoding(s); - return false; - } - - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* Handle M-profile lazy FP state mechanics */ - - /* Trigger lazy-state preservation if necessary */ - if (s->v7m_lspact) { - /* - * Lazy state saving affects external memory and also the NVIC, - * so we must mark it as an IO operation for icount (and cause - * this to be the last insn in the TB). - */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - s->base.is_jmp = DISAS_UPDATE_EXIT; - gen_io_start(); - } - gen_helper_v7m_preserve_fp_state(cpu_env); - /* - * If the preserve_fp_state helper doesn't throw an exception - * then it will clear LSPACT; we don't need to repeat this for - * any further FP insns in this TB. - */ - s->v7m_lspact = false; - } - - /* Update ownership of FP context: set FPCCR.S to match current state */ - if (s->v8m_fpccr_s_wrong) { - TCGv_i32 tmp; - - tmp = load_cpu_field(v7m.fpccr[M_REG_S]); - if (s->v8m_secure) { - tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); - } else { - tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); - } - store_cpu_field(tmp, v7m.fpccr[M_REG_S]); - /* Don't need to do this for any further FP insns in this TB */ - s->v8m_fpccr_s_wrong = false; - } - - if (s->v7m_new_fp_ctxt_needed) { - /* - * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA - * and the FPSCR. - */ - TCGv_i32 control, fpscr; - uint32_t bits = R_V7M_CONTROL_FPCA_MASK; - - fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); - gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(fpscr); - /* - * We don't need to arrange to end the TB, because the only - * parts of FPSCR which we cache in the TB flags are the VECLEN - * and VECSTRIDE, and those don't exist for M-profile. - */ - - if (s->v8m_secure) { - bits |= R_V7M_CONTROL_SFPA_MASK; - } - control = load_cpu_field(v7m.control[M_REG_S]); - tcg_gen_ori_i32(control, control, bits); - store_cpu_field(control, v7m.control[M_REG_S]); - /* Don't need to do this for any further FP insns in this TB */ - s->v7m_new_fp_ctxt_needed = false; - } - } - - return true; -} - -/* - * The most usual kind of VFP access check, for everything except - * FMXR/FMRX to the always-available special registers. - */ -static bool vfp_access_check(DisasContext *s) -{ - return full_vfp_access_check(s, false); -} - -static bool trans_VSEL(DisasContext *s, arg_VSEL *a) -{ - uint32_t rd, rn, rm; - bool dp = a->dp; - - if (!dc_isar_feature(aa32_vsel, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - - rd = a->vd; - rn = a->vn; - rm = a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - if (dp) { - TCGv_i64 frn, frm, dest; - TCGv_i64 tmp, zero, zf, nf, vf; - - zero = tcg_const_i64(0); - - frn = tcg_temp_new_i64(); - frm = tcg_temp_new_i64(); - dest = tcg_temp_new_i64(); - - zf = tcg_temp_new_i64(); - nf = tcg_temp_new_i64(); - vf = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(zf, cpu_ZF); - tcg_gen_ext_i32_i64(nf, cpu_NF); - tcg_gen_ext_i32_i64(vf, cpu_VF); - - neon_load_reg64(frn, rn); - neon_load_reg64(frm, rm); - switch (a->cc) { - case 0: /* eq: Z */ - tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, - frn, frm); - break; - case 1: /* vs: V */ - tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, - frn, frm); - break; - case 2: /* ge: N == V -> N ^ V == 0 */ - tmp = tcg_temp_new_i64(); - tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - frn, frm); - tcg_temp_free_i64(tmp); - break; - case 3: /* gt: !Z && N == V */ - tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, - frn, frm); - tmp = tcg_temp_new_i64(); - tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - dest, frm); - tcg_temp_free_i64(tmp); - break; - } - neon_store_reg64(dest, rd); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - - tcg_temp_free_i64(zf); - tcg_temp_free_i64(nf); - tcg_temp_free_i64(vf); - - tcg_temp_free_i64(zero); - } else { - TCGv_i32 frn, frm, dest; - TCGv_i32 tmp, zero; - - zero = tcg_const_i32(0); - - frn = tcg_temp_new_i32(); - frm = tcg_temp_new_i32(); - dest = tcg_temp_new_i32(); - neon_load_reg32(frn, rn); - neon_load_reg32(frm, rm); - switch (a->cc) { - case 0: /* eq: Z */ - tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, - frn, frm); - break; - case 1: /* vs: V */ - tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, - frn, frm); - break; - case 2: /* ge: N == V -> N ^ V == 0 */ - tmp = tcg_temp_new_i32(); - tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - frn, frm); - tcg_temp_free_i32(tmp); - break; - case 3: /* gt: !Z && N == V */ - tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, - frn, frm); - tmp = tcg_temp_new_i32(); - tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - dest, frm); - tcg_temp_free_i32(tmp); - break; - } - neon_store_reg32(dest, rd); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - - tcg_temp_free_i32(zero); - } - - return true; -} - -/* - * Table for converting the most common AArch32 encoding of - * rounding mode to arm_fprounding order (which matches the - * common AArch64 order); see ARM ARM pseudocode FPDecodeRM(). - */ -static const uint8_t fp_decode_rm[] = { - FPROUNDING_TIEAWAY, - FPROUNDING_TIEEVEN, - FPROUNDING_POSINF, - FPROUNDING_NEGINF, -}; - -static bool trans_VRINT(DisasContext *s, arg_VRINT *a) -{ - uint32_t rd, rm; - bool dp = a->dp; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode; - int rounding = fp_decode_rm[a->rm]; - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { - return false; - } - - rd = a->vd; - rm = a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(0); - - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - - if (dp) { - TCGv_i64 tcg_op; - TCGv_i64 tcg_res; - tcg_op = tcg_temp_new_i64(); - tcg_res = tcg_temp_new_i64(); - neon_load_reg64(tcg_op, rm); - gen_helper_rintd(tcg_res, tcg_op, fpst); - neon_store_reg64(tcg_res, rd); - tcg_temp_free_i64(tcg_op); - tcg_temp_free_i64(tcg_res); - } else { - TCGv_i32 tcg_op; - TCGv_i32 tcg_res; - tcg_op = tcg_temp_new_i32(); - tcg_res = tcg_temp_new_i32(); - neon_load_reg32(tcg_op, rm); - gen_helper_rints(tcg_res, tcg_op, fpst); - neon_store_reg32(tcg_res, rd); - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); - } - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT(DisasContext *s, arg_VCVT *a) -{ - uint32_t rd, rm; - bool dp = a->dp; - TCGv_ptr fpst; - TCGv_i32 tcg_rmode, tcg_shift; - int rounding = fp_decode_rm[a->rm]; - bool is_signed = a->op; - - if (!dc_isar_feature(aa32_vcvt_dr, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - rd = a->vd; - rm = a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(0); - - tcg_shift = tcg_const_i32(0); - - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - - if (dp) { - TCGv_i64 tcg_double, tcg_res; - TCGv_i32 tcg_tmp; - tcg_double = tcg_temp_new_i64(); - tcg_res = tcg_temp_new_i64(); - tcg_tmp = tcg_temp_new_i32(); - neon_load_reg64(tcg_double, rm); - if (is_signed) { - gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); - } else { - gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); - } - tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); - neon_store_reg32(tcg_tmp, rd); - tcg_temp_free_i32(tcg_tmp); - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single, tcg_res; - tcg_single = tcg_temp_new_i32(); - tcg_res = tcg_temp_new_i32(); - neon_load_reg32(tcg_single, rm); - if (is_signed) { - gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst); - } else { - gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); - } - neon_store_reg32(tcg_res, rd); - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_single); - } - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_i32(tcg_shift); - - tcg_temp_free_ptr(fpst); - - return true; -} - -static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) -{ - /* VMOV scalar to general purpose register */ - TCGv_i32 tmp; - int pass; - uint32_t offset; - - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ - if (a->size == 2 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { - return false; - } - - offset = a->index << a->size; - pass = extract32(offset, 2, 1); - offset = extract32(offset, 0, 2) * 8; - - if (!vfp_access_check(s)) { - return true; - } - - tmp = neon_load_reg(a->vn, pass); - switch (a->size) { - case 0: - if (offset) { - tcg_gen_shri_i32(tmp, tmp, offset); - } - if (a->u) { - gen_uxtb(tmp); - } else { - gen_sxtb(tmp); - } - break; - case 1: - if (a->u) { - if (offset) { - tcg_gen_shri_i32(tmp, tmp, 16); - } else { - gen_uxth(tmp); - } - } else { - if (offset) { - tcg_gen_sari_i32(tmp, tmp, 16); - } else { - gen_sxth(tmp); - } - } - break; - case 2: - break; - } - store_reg(s, a->rt, tmp); - - return true; -} - -static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) -{ - /* VMOV general purpose register to scalar */ - TCGv_i32 tmp, tmp2; - int pass; - uint32_t offset; - - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ - if (a->size == 2 - ? !dc_isar_feature(aa32_fpsp_v2, s) - : !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { - return false; - } - - offset = a->index << a->size; - pass = extract32(offset, 2, 1); - offset = extract32(offset, 0, 2) * 8; - - if (!vfp_access_check(s)) { - return true; - } - - tmp = load_reg(s, a->rt); - switch (a->size) { - case 0: - tmp2 = neon_load_reg(a->vn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); - tcg_temp_free_i32(tmp2); - break; - case 1: - tmp2 = neon_load_reg(a->vn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); - tcg_temp_free_i32(tmp2); - break; - case 2: - break; - } - neon_store_reg(a->vn, pass, tmp); - - return true; -} - -static bool trans_VDUP(DisasContext *s, arg_VDUP *a) -{ - /* VDUP (general purpose register) */ - TCGv_i32 tmp; - int size, vec_size; - - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { - return false; - } - - if (a->b && a->e) { - return false; - } - - if (a->q && (a->vn & 1)) { - return false; - } - - vec_size = a->q ? 16 : 8; - if (a->b) { - size = 0; - } else if (a->e) { - size = 1; - } else { - size = 2; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = load_reg(s, a->rt); - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), - vec_size, vec_size, tmp); - tcg_temp_free_i32(tmp); - - return true; -} - -static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) -{ - TCGv_i32 tmp; - bool ignore_vfp_enabled = false; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. - * Accesses to R15 are UNPREDICTABLE; we choose to undef. - * (FPSCR -> r15 is a special case which writes to the PSR flags.) - */ - if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) { - return false; - } - } - - switch (a->reg) { - case ARM_VFP_FPSID: - /* - * VFPv2 allows access to FPSID from userspace; VFPv3 restricts - * all ID registers to privileged access only. - */ - if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { - return false; - } - ignore_vfp_enabled = true; - break; - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) { - return false; - } - ignore_vfp_enabled = true; - break; - case ARM_VFP_MVFR2: - if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - ignore_vfp_enabled = true; - break; - case ARM_VFP_FPSCR: - break; - case ARM_VFP_FPEXC: - if (IS_USER(s)) { - return false; - } - ignore_vfp_enabled = true; - break; - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: - /* Not present in VFPv3 */ - if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { - return false; - } - break; - default: - return false; - } - - if (!full_vfp_access_check(s, ignore_vfp_enabled)) { - return true; - } - - if (a->l) { - /* VMRS, move VFP special register to gp register */ - switch (a->reg) { - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - case ARM_VFP_MVFR2: - case ARM_VFP_FPSID: - if (s->current_el == 1) { - TCGv_i32 tcg_reg, tcg_rt; - - gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); - tcg_reg = tcg_const_i32(a->reg); - tcg_rt = tcg_const_i32(a->rt); - gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); - tcg_temp_free_i32(tcg_reg); - tcg_temp_free_i32(tcg_rt); - } - /* fall through */ - case ARM_VFP_FPEXC: - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: - tmp = load_cpu_field(vfp.xregs[a->reg]); - break; - case ARM_VFP_FPSCR: - if (a->rt == 15) { - tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); - } else { - tmp = tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); - } - break; - default: - g_assert_not_reached(); - } - - if (a->rt == 15) { - /* Set the 4 flag bits in the CPSR. */ - gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); - } else { - store_reg(s, a->rt, tmp); - } - } else { - /* VMSR, move gp register to VFP special register */ - switch (a->reg) { - case ARM_VFP_FPSID: - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - case ARM_VFP_MVFR2: - /* Writes are ignored. */ - break; - case ARM_VFP_FPSCR: - tmp = load_reg(s, a->rt); - gen_helper_vfp_set_fpscr(cpu_env, tmp); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - case ARM_VFP_FPEXC: - /* - * TODO: VFP subarchitecture support. - * For now, keep the EN bit only - */ - tmp = load_reg(s, a->rt); - tcg_gen_andi_i32(tmp, tmp, 1 << 30); - store_cpu_field(tmp, vfp.xregs[a->reg]); - gen_lookup_tb(s); - break; - case ARM_VFP_FPINST: - case ARM_VFP_FPINST2: - tmp = load_reg(s, a->rt); - store_cpu_field(tmp, vfp.xregs[a->reg]); - break; - default: - g_assert_not_reached(); - } - } - - return true; -} - -static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) -{ - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (a->l) { - /* VFP to general purpose register */ - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vn); - if (a->rt == 15) { - /* Set the 4 flag bits in the CPSR. */ - gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); - } else { - store_reg(s, a->rt, tmp); - } - } else { - /* general purpose register to VFP */ - tmp = load_reg(s, a->rt); - neon_store_reg32(tmp, a->vn); - tcg_temp_free_i32(tmp); - } - - return true; -} - -static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) -{ - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - /* - * VMOV between two general-purpose registers and two single precision - * floating point registers - */ - if (!vfp_access_check(s)) { - return true; - } - - if (a->op) { - /* fpreg to gpreg */ - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); - store_reg(s, a->rt, tmp); - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm + 1); - store_reg(s, a->rt2, tmp); - } else { - /* gpreg to fpreg */ - tmp = load_reg(s, a->rt); - neon_store_reg32(tmp, a->vm); - tcg_temp_free_i32(tmp); - tmp = load_reg(s, a->rt2); - neon_store_reg32(tmp, a->vm + 1); - tcg_temp_free_i32(tmp); - } - - return true; -} - -static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) -{ - TCGv_i32 tmp; - - /* - * VMOV between two general-purpose registers and one double precision - * floating point register. Note that this does not require support - * for double precision arithmetic. - */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (a->op) { - /* fpreg to gpreg */ - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm * 2); - store_reg(s, a->rt, tmp); - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm * 2 + 1); - store_reg(s, a->rt2, tmp); - } else { - /* gpreg to fpreg */ - tmp = load_reg(s, a->rt); - neon_store_reg32(tmp, a->vm * 2); - tcg_temp_free_i32(tmp); - tmp = load_reg(s, a->rt2); - neon_store_reg32(tmp, a->vm * 2 + 1); - tcg_temp_free_i32(tmp); - } - - return true; -} - -static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) -{ - uint32_t offset; - TCGv_i32 addr, tmp; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - offset = a->imm << 2; - if (!a->u) { - offset = -offset; - } - - /* For thumb, use of PC is UNPREDICTABLE. */ - addr = add_reg_for_lit(s, a->rn, offset); - tmp = tcg_temp_new_i32(); - if (a->l) { - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg32(tmp, a->vd); - } else { - neon_load_reg32(tmp, a->vd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - - return true; -} - -static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) -{ - uint32_t offset; - TCGv_i32 addr; - TCGv_i64 tmp; - - /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - offset = a->imm << 2; - if (!a->u) { - offset = -offset; - } - - /* For thumb, use of PC is UNPREDICTABLE. */ - addr = add_reg_for_lit(s, a->rn, offset); - tmp = tcg_temp_new_i64(); - if (a->l) { - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); - neon_store_reg64(tmp, a->vd); - } else { - neon_load_reg64(tmp, a->vd); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(addr); - - return true; -} - -static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) -{ - uint32_t offset; - TCGv_i32 addr, tmp; - int i, n; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - n = a->imm; - - if (n == 0 || (a->vd + n) > 32) { - /* - * UNPREDICTABLE cases for bad immediates: we choose to - * UNDEF to avoid generating huge numbers of TCG ops - */ - return false; - } - if (a->rn == 15 && a->w) { - /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* For thumb, use of PC is UNPREDICTABLE. */ - addr = add_reg_for_lit(s, a->rn, 0); - if (a->p) { - /* pre-decrement */ - tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); - } - - if (s->v8m_stackcheck && a->rn == 13 && a->w) { - /* - * Here 'addr' is the lowest address we will store to, - * and is either the old SP (if post-increment) or - * the new SP (if pre-decrement). For post-increment - * where the old value is below the limit and the new - * value is above, it is UNKNOWN whether the limit check - * triggers; we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - offset = 4; - tmp = tcg_temp_new_i32(); - for (i = 0; i < n; i++) { - if (a->l) { - /* load */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg32(tmp, a->vd + i); - } else { - /* store */ - neon_load_reg32(tmp, a->vd + i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } - tcg_gen_addi_i32(addr, addr, offset); - } - tcg_temp_free_i32(tmp); - if (a->w) { - /* writeback */ - if (a->p) { - offset = -offset * n; - tcg_gen_addi_i32(addr, addr, offset); - } - store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); - } - - return true; -} - -static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) -{ - uint32_t offset; - TCGv_i32 addr; - TCGv_i64 tmp; - int i, n; - - /* Note that this does not require support for double arithmetic. */ - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - n = a->imm >> 1; - - if (n == 0 || (a->vd + n) > 32 || n > 16) { - /* - * UNPREDICTABLE cases for bad immediates: we choose to - * UNDEF to avoid generating huge numbers of TCG ops - */ - return false; - } - if (a->rn == 15 && a->w) { - /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* For thumb, use of PC is UNPREDICTABLE. */ - addr = add_reg_for_lit(s, a->rn, 0); - if (a->p) { - /* pre-decrement */ - tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); - } - - if (s->v8m_stackcheck && a->rn == 13 && a->w) { - /* - * Here 'addr' is the lowest address we will store to, - * and is either the old SP (if post-increment) or - * the new SP (if pre-decrement). For post-increment - * where the old value is below the limit and the new - * value is above, it is UNKNOWN whether the limit check - * triggers; we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - offset = 8; - tmp = tcg_temp_new_i64(); - for (i = 0; i < n; i++) { - if (a->l) { - /* load */ - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); - neon_store_reg64(tmp, a->vd + i); - } else { - /* store */ - neon_load_reg64(tmp, a->vd + i); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); - } - tcg_gen_addi_i32(addr, addr, offset); - } - tcg_temp_free_i64(tmp); - if (a->w) { - /* writeback */ - if (a->p) { - offset = -offset * n; - } else if (a->imm & 1) { - offset = 4; - } else { - offset = 0; - } - - if (offset != 0) { - tcg_gen_addi_i32(addr, addr, offset); - } - store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); - } - - return true; -} - -/* - * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp(). - * The callback should emit code to write a value to vd. If - * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd - * will contain the old value of the relevant VFP register; - * otherwise it must be written to only. - */ -typedef void VFPGen3OpSPFn(TCGv_i32 vd, - TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst); -typedef void VFPGen3OpDPFn(TCGv_i64 vd, - TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst); - -/* - * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp(). - * The callback should emit code to write a value to vd (which - * should be written to only). - */ -typedef void VFPGen2OpSPFn(TCGv_i32 vd, TCGv_i32 vm); -typedef void VFPGen2OpDPFn(TCGv_i64 vd, TCGv_i64 vm); - -/* - * Return true if the specified S reg is in a scalar bank - * (ie if it is s0..s7) - */ -static inline bool vfp_sreg_is_scalar(int reg) -{ - return (reg & 0x18) == 0; -} - -/* - * Return true if the specified D reg is in a scalar bank - * (ie if it is d0..d3 or d16..d19) - */ -static inline bool vfp_dreg_is_scalar(int reg) -{ - return (reg & 0xc) == 0; -} - -/* - * Advance the S reg number forwards by delta within its bank - * (ie increment the low 3 bits but leave the rest the same) - */ -static inline int vfp_advance_sreg(int reg, int delta) -{ - return ((reg + delta) & 0x7) | (reg & ~0x7); -} - -/* - * Advance the D reg number forwards by delta within its bank - * (ie increment the low 2 bits but leave the rest the same) - */ -static inline int vfp_advance_dreg(int reg, int delta) -{ - return ((reg + delta) & 0x3) | (reg & ~0x3); -} - -/* - * Perform a 3-operand VFP data processing instruction. fn is the - * callback to do the actual operation; this function deals with the - * code to handle looping around for VFP vector processing. - */ -static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, - int vd, int vn, int vm, bool reads_vd) -{ - uint32_t delta_m = 0; - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i32 f0, f1, fd; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_sreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = s->vec_stride + 1; - - if (vfp_sreg_is_scalar(vm)) { - /* mixed scalar/vector */ - delta_m = 0; - } else { - /* vector */ - delta_m = delta_d; - } - } - } - - f0 = tcg_temp_new_i32(); - f1 = tcg_temp_new_i32(); - fd = tcg_temp_new_i32(); - fpst = get_fpstatus_ptr(0); - - neon_load_reg32(f0, vn); - neon_load_reg32(f1, vm); - - for (;;) { - if (reads_vd) { - neon_load_reg32(fd, vd); - } - fn(fd, f0, f1, fpst); - neon_store_reg32(fd, vd); - - if (veclen == 0) { - break; - } - - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_sreg(vd, delta_d); - vn = vfp_advance_sreg(vn, delta_d); - neon_load_reg32(f0, vn); - if (delta_m) { - vm = vfp_advance_sreg(vm, delta_m); - neon_load_reg32(f1, vm); - } - } - - tcg_temp_free_i32(f0); - tcg_temp_free_i32(f1); - tcg_temp_free_i32(fd); - tcg_temp_free_ptr(fpst); - - return true; -} - -static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, - int vd, int vn, int vm, bool reads_vd) -{ - uint32_t delta_m = 0; - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i64 f0, f1, fd; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_dreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = (s->vec_stride >> 1) + 1; - - if (vfp_dreg_is_scalar(vm)) { - /* mixed scalar/vector */ - delta_m = 0; - } else { - /* vector */ - delta_m = delta_d; - } - } - } - - f0 = tcg_temp_new_i64(); - f1 = tcg_temp_new_i64(); - fd = tcg_temp_new_i64(); - fpst = get_fpstatus_ptr(0); - - neon_load_reg64(f0, vn); - neon_load_reg64(f1, vm); - - for (;;) { - if (reads_vd) { - neon_load_reg64(fd, vd); - } - fn(fd, f0, f1, fpst); - neon_store_reg64(fd, vd); - - if (veclen == 0) { - break; - } - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_dreg(vd, delta_d); - vn = vfp_advance_dreg(vn, delta_d); - neon_load_reg64(f0, vn); - if (delta_m) { - vm = vfp_advance_dreg(vm, delta_m); - neon_load_reg64(f1, vm); - } - } - - tcg_temp_free_i64(f0); - tcg_temp_free_i64(f1); - tcg_temp_free_i64(fd); - tcg_temp_free_ptr(fpst); - - return true; -} - -static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) -{ - uint32_t delta_m = 0; - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i32 f0, fd; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_sreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = s->vec_stride + 1; - - if (vfp_sreg_is_scalar(vm)) { - /* mixed scalar/vector */ - delta_m = 0; - } else { - /* vector */ - delta_m = delta_d; - } - } - } - - f0 = tcg_temp_new_i32(); - fd = tcg_temp_new_i32(); - - neon_load_reg32(f0, vm); - - for (;;) { - fn(fd, f0); - neon_store_reg32(fd, vd); - - if (veclen == 0) { - break; - } - - if (delta_m == 0) { - /* single source one-many */ - while (veclen--) { - vd = vfp_advance_sreg(vd, delta_d); - neon_store_reg32(fd, vd); - } - break; - } - - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_sreg(vd, delta_d); - vm = vfp_advance_sreg(vm, delta_m); - neon_load_reg32(f0, vm); - } - - tcg_temp_free_i32(f0); - tcg_temp_free_i32(fd); - - return true; -} - -static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) -{ - uint32_t delta_m = 0; - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i64 f0, fd; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_dreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = (s->vec_stride >> 1) + 1; - - if (vfp_dreg_is_scalar(vm)) { - /* mixed scalar/vector */ - delta_m = 0; - } else { - /* vector */ - delta_m = delta_d; - } - } - } - - f0 = tcg_temp_new_i64(); - fd = tcg_temp_new_i64(); - - neon_load_reg64(f0, vm); - - for (;;) { - fn(fd, f0); - neon_store_reg64(fd, vd); - - if (veclen == 0) { - break; - } - - if (delta_m == 0) { - /* single source one-many */ - while (veclen--) { - vd = vfp_advance_dreg(vd, delta_d); - neon_store_reg64(fd, vd); - } - break; - } - - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_dreg(vd, delta_d); - vd = vfp_advance_dreg(vm, delta_m); - neon_load_reg64(f0, vm); - } - - tcg_temp_free_i64(f0); - tcg_temp_free_i64(fd); - - return true; -} - -static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) -{ - /* Note that order of inputs to the add matters for NaNs */ - TCGv_i32 tmp = tcg_temp_new_i32(); - - gen_helper_vfp_muls(tmp, vn, vm, fpst); - gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); -} - -static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a) -{ - return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true); -} - -static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) -{ - /* Note that order of inputs to the add matters for NaNs */ - TCGv_i64 tmp = tcg_temp_new_i64(); - - gen_helper_vfp_muld(tmp, vn, vm, fpst); - gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); -} - -static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a) -{ - return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true); -} - -static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) -{ - /* - * VMLS: vd = vd + -(vn * vm) - * Note that order of inputs to the add matters for NaNs. - */ - TCGv_i32 tmp = tcg_temp_new_i32(); - - gen_helper_vfp_muls(tmp, vn, vm, fpst); - gen_helper_vfp_negs(tmp, tmp); - gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); -} - -static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a) -{ - return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true); -} - -static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) -{ - /* - * VMLS: vd = vd + -(vn * vm) - * Note that order of inputs to the add matters for NaNs. - */ - TCGv_i64 tmp = tcg_temp_new_i64(); - - gen_helper_vfp_muld(tmp, vn, vm, fpst); - gen_helper_vfp_negd(tmp, tmp); - gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); -} - -static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a) -{ - return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true); -} - -static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) -{ - /* - * VNMLS: -fd + (fn * fm) - * Note that it isn't valid to replace (-A + B) with (B - A) or similar - * plausible looking simplifications because this will give wrong results - * for NaNs. - */ - TCGv_i32 tmp = tcg_temp_new_i32(); - - gen_helper_vfp_muls(tmp, vn, vm, fpst); - gen_helper_vfp_negs(vd, vd); - gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); -} - -static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a) -{ - return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true); -} - -static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) -{ - /* - * VNMLS: -fd + (fn * fm) - * Note that it isn't valid to replace (-A + B) with (B - A) or similar - * plausible looking simplifications because this will give wrong results - * for NaNs. - */ - TCGv_i64 tmp = tcg_temp_new_i64(); - - gen_helper_vfp_muld(tmp, vn, vm, fpst); - gen_helper_vfp_negd(vd, vd); - gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); -} - -static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a) -{ - return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true); -} - -static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) -{ - /* VNMLA: -fd + -(fn * fm) */ - TCGv_i32 tmp = tcg_temp_new_i32(); - - gen_helper_vfp_muls(tmp, vn, vm, fpst); - gen_helper_vfp_negs(tmp, tmp); - gen_helper_vfp_negs(vd, vd); - gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); -} - -static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a) -{ - return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true); -} - -static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) -{ - /* VNMLA: -fd + (fn * fm) */ - TCGv_i64 tmp = tcg_temp_new_i64(); - - gen_helper_vfp_muld(tmp, vn, vm, fpst); - gen_helper_vfp_negd(tmp, tmp); - gen_helper_vfp_negd(vd, vd); - gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); -} - -static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a) -{ - return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); -} - -static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a) -{ - return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false); -} - -static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a) -{ - return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false); -} - -static void gen_VNMUL_sp(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst) -{ - /* VNMUL: -(fn * fm) */ - gen_helper_vfp_muls(vd, vn, vm, fpst); - gen_helper_vfp_negs(vd, vd); -} - -static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a) -{ - return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false); -} - -static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) -{ - /* VNMUL: -(fn * fm) */ - gen_helper_vfp_muld(vd, vn, vm, fpst); - gen_helper_vfp_negd(vd, vd); -} - -static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a) -{ - return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); -} - -static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a) -{ - return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false); -} - -static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a) -{ - return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false); -} - -static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a) -{ - return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false); -} - -static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a) -{ - return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false); -} - -static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a) -{ - return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false); -} - -static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a) -{ - return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false); -} - -static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) -{ - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - return do_vfp_3op_sp(s, gen_helper_vfp_minnums, - a->vd, a->vn, a->vm, false); -} - -static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) -{ - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, - a->vd, a->vn, a->vm, false); -} - -static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) -{ - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, - a->vd, a->vn, a->vm, false); -} - -static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) -{ - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, - a->vd, a->vn, a->vm, false); -} - -static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) -{ - /* - * VFNMA : fd = muladd(-fd, fn, fm) - * VFNMS : fd = muladd(-fd, -fn, fm) - * VFMA : fd = muladd( fd, fn, fm) - * VFMS : fd = muladd( fd, -fn, fm) - * - * These are fused multiply-add, and must be done as one floating - * point operation with no rounding between the multiplication and - * addition steps. NB that doing the negations here as separate - * steps is correct : an input NaN should come out with its sign - * bit flipped if it is a negated-input. - */ - TCGv_ptr fpst; - TCGv_i32 vn, vm, vd; - - /* - * Present in VFPv4 only. - * Note that we can't rely on the SIMDFMAC check alone, because - * in a Neon-no-VFP core that ID register field will be non-zero. - */ - if (!dc_isar_feature(aa32_simdfmac, s) || - !dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - /* - * In v7A, UNPREDICTABLE with non-zero vector length/stride; from - * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. - */ - if (s->vec_len != 0 || s->vec_stride != 0) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vn = tcg_temp_new_i32(); - vm = tcg_temp_new_i32(); - vd = tcg_temp_new_i32(); - - neon_load_reg32(vn, a->vn); - neon_load_reg32(vm, a->vm); - if (neg_n) { - /* VFNMS, VFMS */ - gen_helper_vfp_negs(vn, vn); - } - neon_load_reg32(vd, a->vd); - if (neg_d) { - /* VFNMA, VFNMS */ - gen_helper_vfp_negs(vd, vd); - } - fpst = get_fpstatus_ptr(0); - gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); - neon_store_reg32(vd, a->vd); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(vn); - tcg_temp_free_i32(vm); - tcg_temp_free_i32(vd); - - return true; -} - -static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) -{ - return do_vfm_sp(s, a, false, false); -} - -static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) -{ - return do_vfm_sp(s, a, true, false); -} - -static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) -{ - return do_vfm_sp(s, a, false, true); -} - -static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) -{ - return do_vfm_sp(s, a, true, true); -} - -static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) -{ - /* - * VFNMA : fd = muladd(-fd, fn, fm) - * VFNMS : fd = muladd(-fd, -fn, fm) - * VFMA : fd = muladd( fd, fn, fm) - * VFMS : fd = muladd( fd, -fn, fm) - * - * These are fused multiply-add, and must be done as one floating - * point operation with no rounding between the multiplication and - * addition steps. NB that doing the negations here as separate - * steps is correct : an input NaN should come out with its sign - * bit flipped if it is a negated-input. - */ - TCGv_ptr fpst; - TCGv_i64 vn, vm, vd; - - /* - * Present in VFPv4 only. - * Note that we can't rely on the SIMDFMAC check alone, because - * in a Neon-no-VFP core that ID register field will be non-zero. - */ - if (!dc_isar_feature(aa32_simdfmac, s) || - !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - /* - * In v7A, UNPREDICTABLE with non-zero vector length/stride; from - * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. - */ - if (s->vec_len != 0 || s->vec_stride != 0) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vn = tcg_temp_new_i64(); - vm = tcg_temp_new_i64(); - vd = tcg_temp_new_i64(); - - neon_load_reg64(vn, a->vn); - neon_load_reg64(vm, a->vm); - if (neg_n) { - /* VFNMS, VFMS */ - gen_helper_vfp_negd(vn, vn); - } - neon_load_reg64(vd, a->vd); - if (neg_d) { - /* VFNMA, VFNMS */ - gen_helper_vfp_negd(vd, vd); - } - fpst = get_fpstatus_ptr(0); - gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); - neon_store_reg64(vd, a->vd); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(vn); - tcg_temp_free_i64(vm); - tcg_temp_free_i64(vd); - - return true; -} - -static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) -{ - return do_vfm_dp(s, a, false, false); -} - -static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) -{ - return do_vfm_dp(s, a, true, false); -} - -static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) -{ - return do_vfm_dp(s, a, false, true); -} - -static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) -{ - return do_vfm_dp(s, a, true, true); -} - -static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) -{ - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i32 fd; - uint32_t vd; - - vd = a->vd; - - if (!dc_isar_feature(aa32_fpsp_v3, s)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_sreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = s->vec_stride + 1; - } - } - - fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); - - for (;;) { - neon_store_reg32(fd, vd); - - if (veclen == 0) { - break; - } - - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_sreg(vd, delta_d); - } - - tcg_temp_free_i32(fd); - return true; -} - -static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) -{ - uint32_t delta_d = 0; - int veclen = s->vec_len; - TCGv_i64 fd; - uint32_t vd; - - vd = a->vd; - - if (!dc_isar_feature(aa32_fpdp_v3, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { - return false; - } - - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen != 0 || s->vec_stride != 0)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - if (veclen > 0) { - /* Figure out what type of vector operation this is. */ - if (vfp_dreg_is_scalar(vd)) { - /* scalar */ - veclen = 0; - } else { - delta_d = (s->vec_stride >> 1) + 1; - } - } - - fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); - - for (;;) { - neon_store_reg64(fd, vd); - - if (veclen == 0) { - break; - } - - /* Set up the operands for the next iteration */ - veclen--; - vd = vfp_advance_dreg(vd, delta_d); - } - - tcg_temp_free_i64(fd); - return true; -} - -static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a) -{ - return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm); -} - -static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a) -{ - return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm); -} - -static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a) -{ - return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm); -} - -static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) -{ - return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); -} - -static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a) -{ - return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm); -} - -static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) -{ - return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); -} - -static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) -{ - gen_helper_vfp_sqrts(vd, vm, cpu_env); -} - -static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a) -{ - return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm); -} - -static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) -{ - gen_helper_vfp_sqrtd(vd, vm, cpu_env); -} - -static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a) -{ - return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); -} - -static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) -{ - TCGv_i32 vd, vm; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - /* Vm/M bits must be zero for the Z variant */ - if (a->z && a->vm != 0) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vd = tcg_temp_new_i32(); - vm = tcg_temp_new_i32(); - - neon_load_reg32(vd, a->vd); - if (a->z) { - tcg_gen_movi_i32(vm, 0); - } else { - neon_load_reg32(vm, a->vm); - } - - if (a->e) { - gen_helper_vfp_cmpes(vd, vm, cpu_env); - } else { - gen_helper_vfp_cmps(vd, vm, cpu_env); - } - - tcg_temp_free_i32(vd); - tcg_temp_free_i32(vm); - - return true; -} - -static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) -{ - TCGv_i64 vd, vm; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* Vm/M bits must be zero for the Z variant */ - if (a->z && a->vm != 0) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vd = tcg_temp_new_i64(); - vm = tcg_temp_new_i64(); - - neon_load_reg64(vd, a->vd); - if (a->z) { - tcg_gen_movi_i64(vm, 0); - } else { - neon_load_reg64(vm, a->vm); - } - - if (a->e) { - gen_helper_vfp_cmped(vd, vm, cpu_env); - } else { - gen_helper_vfp_cmpd(vd, vm, cpu_env); - } - - tcg_temp_free_i64(vd); - tcg_temp_free_i64(vm); - - return true; -} - -static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp_mode; - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_fp16_spconv, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - ahp_mode = get_ahp_flag(); - tmp = tcg_temp_new_i32(); - /* The T bit tells us if we want the low or high 16 bits of Vm */ - tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); - gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); - neon_store_reg32(tmp, a->vd); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp_mode; - TCGv_i32 tmp; - TCGv_i64 vd; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_fp16_dpconv, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - ahp_mode = get_ahp_flag(); - tmp = tcg_temp_new_i32(); - /* The T bit tells us if we want the low or high 16 bits of Vm */ - tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); - vd = tcg_temp_new_i64(); - gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); - neon_store_reg64(vd, a->vd); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - tcg_temp_free_i64(vd); - return true; -} - -static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp_mode; - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_fp16_spconv, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - ahp_mode = get_ahp_flag(); - tmp = tcg_temp_new_i32(); - - neon_load_reg32(tmp, a->vm); - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); - tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) -{ - TCGv_ptr fpst; - TCGv_i32 ahp_mode; - TCGv_i32 tmp; - TCGv_i64 vm; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_fp16_dpconv, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - ahp_mode = get_ahp_flag(); - tmp = tcg_temp_new_i32(); - vm = tcg_temp_new_i64(); - - neon_load_reg64(vm, a->vm); - gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); - tcg_temp_free_i64(vm); - tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) -{ - TCGv_ptr fpst; - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - gen_helper_rints(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) -{ - TCGv_ptr fpst; - TCGv_i64 tmp; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - gen_helper_rintd(tmp, tmp, fpst); - neon_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); - return true; -} - -static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) -{ - TCGv_ptr fpst; - TCGv_i32 tmp; - TCGv_i32 tcg_rmode; - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - gen_helper_rints(tmp, tmp, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - neon_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) -{ - TCGv_ptr fpst; - TCGv_i64 tmp; - TCGv_i32 tcg_rmode; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - gen_helper_rintd(tmp, tmp, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - neon_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tcg_rmode); - return true; -} - -static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) -{ - TCGv_ptr fpst; - TCGv_i32 tmp; - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - gen_helper_rints_exact(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - return true; -} - -static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) -{ - TCGv_ptr fpst; - TCGv_i64 tmp; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_vrint, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - tmp = tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); - fpst = get_fpstatus_ptr(false); - gen_helper_rintd_exact(tmp, tmp, fpst); - neon_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); - return true; -} - -static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) -{ - TCGv_i64 vd; - TCGv_i32 vm; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vm = tcg_temp_new_i32(); - vd = tcg_temp_new_i64(); - neon_load_reg32(vm, a->vm); - gen_helper_vfp_fcvtds(vd, vm, cpu_env); - neon_store_reg64(vd, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_i64(vd); - return true; -} - -static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) -{ - TCGv_i64 vm; - TCGv_i32 vd; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vd = tcg_temp_new_i32(); - vm = tcg_temp_new_i64(); - neon_load_reg64(vm, a->vm); - gen_helper_vfp_fcvtsd(vd, vm, cpu_env); - neon_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_i64(vm); - return true; -} - -static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) -{ - TCGv_i32 vm; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vm = tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); - fpst = get_fpstatus_ptr(false); - if (a->s) { - /* i32 -> f32 */ - gen_helper_vfp_sitos(vm, vm, fpst); - } else { - /* u32 -> f32 */ - gen_helper_vfp_uitos(vm, vm, fpst); - } - neon_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) -{ - TCGv_i32 vm; - TCGv_i64 vd; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vm = tcg_temp_new_i32(); - vd = tcg_temp_new_i64(); - neon_load_reg32(vm, a->vm); - fpst = get_fpstatus_ptr(false); - if (a->s) { - /* i32 -> f64 */ - gen_helper_vfp_sitod(vd, vm, fpst); - } else { - /* u32 -> f64 */ - gen_helper_vfp_uitod(vd, vm, fpst); - } - neon_store_reg64(vd, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_i64(vd); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) -{ - TCGv_i32 vd; - TCGv_i64 vm; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!dc_isar_feature(aa32_jscvt, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - vm = tcg_temp_new_i64(); - vd = tcg_temp_new_i32(); - neon_load_reg64(vm, a->vm); - gen_helper_vjcvt(vd, vm, cpu_env); - neon_store_reg32(vd, a->vd); - tcg_temp_free_i64(vm); - tcg_temp_free_i32(vd); - return true; -} - -static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) -{ - TCGv_i32 vd, shift; - TCGv_ptr fpst; - int frac_bits; - - if (!dc_isar_feature(aa32_fpsp_v3, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); - - vd = tcg_temp_new_i32(); - neon_load_reg32(vd, a->vd); - - fpst = get_fpstatus_ptr(false); - shift = tcg_const_i32(frac_bits); - - /* Switch on op:U:sx bits */ - switch (a->opc) { - case 0: - gen_helper_vfp_shtos(vd, vd, shift, fpst); - break; - case 1: - gen_helper_vfp_sltos(vd, vd, shift, fpst); - break; - case 2: - gen_helper_vfp_uhtos(vd, vd, shift, fpst); - break; - case 3: - gen_helper_vfp_ultos(vd, vd, shift, fpst); - break; - case 4: - gen_helper_vfp_toshs_round_to_zero(vd, vd, shift, fpst); - break; - case 5: - gen_helper_vfp_tosls_round_to_zero(vd, vd, shift, fpst); - break; - case 6: - gen_helper_vfp_touhs_round_to_zero(vd, vd, shift, fpst); - break; - case 7: - gen_helper_vfp_touls_round_to_zero(vd, vd, shift, fpst); - break; - default: - g_assert_not_reached(); - } - - neon_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_i32(shift); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) -{ - TCGv_i64 vd; - TCGv_i32 shift; - TCGv_ptr fpst; - int frac_bits; - - if (!dc_isar_feature(aa32_fpdp_v3, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); - - vd = tcg_temp_new_i64(); - neon_load_reg64(vd, a->vd); - - fpst = get_fpstatus_ptr(false); - shift = tcg_const_i32(frac_bits); - - /* Switch on op:U:sx bits */ - switch (a->opc) { - case 0: - gen_helper_vfp_shtod(vd, vd, shift, fpst); - break; - case 1: - gen_helper_vfp_sltod(vd, vd, shift, fpst); - break; - case 2: - gen_helper_vfp_uhtod(vd, vd, shift, fpst); - break; - case 3: - gen_helper_vfp_ultod(vd, vd, shift, fpst); - break; - case 4: - gen_helper_vfp_toshd_round_to_zero(vd, vd, shift, fpst); - break; - case 5: - gen_helper_vfp_tosld_round_to_zero(vd, vd, shift, fpst); - break; - case 6: - gen_helper_vfp_touhd_round_to_zero(vd, vd, shift, fpst); - break; - case 7: - gen_helper_vfp_tould_round_to_zero(vd, vd, shift, fpst); - break; - default: - g_assert_not_reached(); - } - - neon_store_reg64(vd, a->vd); - tcg_temp_free_i64(vd); - tcg_temp_free_i32(shift); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) -{ - TCGv_i32 vm; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - vm = tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); - - if (a->s) { - if (a->rz) { - gen_helper_vfp_tosizs(vm, vm, fpst); - } else { - gen_helper_vfp_tosis(vm, vm, fpst); - } - } else { - if (a->rz) { - gen_helper_vfp_touizs(vm, vm, fpst); - } else { - gen_helper_vfp_touis(vm, vm, fpst); - } - } - neon_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); - return true; -} - -static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) -{ - TCGv_i32 vd; - TCGv_i64 vm; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fpst = get_fpstatus_ptr(false); - vm = tcg_temp_new_i64(); - vd = tcg_temp_new_i32(); - neon_load_reg64(vm, a->vm); - - if (a->s) { - if (a->rz) { - gen_helper_vfp_tosizd(vd, vm, fpst); - } else { - gen_helper_vfp_tosid(vd, vm, fpst); - } - } else { - if (a->rz) { - gen_helper_vfp_touizd(vd, vm, fpst); - } else { - gen_helper_vfp_touid(vd, vm, fpst); - } - } - neon_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_i64(vm); - tcg_temp_free_ptr(fpst); - return true; -} - -/* - * Decode VLLDM and VLSTM are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that vfp_access_check() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ -static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) -{ - TCGv_i32 fptr; - - if (!arm_dc_feature(s, ARM_FEATURE_M) || - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - /* If not secure, UNDEF. */ - if (!s->v8m_secure) { - return false; - } - /* If no fpu, NOP. */ - if (!dc_isar_feature(aa32_vfp, s)) { - return true; - } - - fptr = load_reg(s, a->rn); - if (a->l) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits */ - s->base.is_jmp = DISAS_UPDATE_EXIT; - return true; -} diff --git a/target/arm/translate.c b/target/arm/translate.c index c39a929b93..556588d92f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1176,8 +1176,8 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) /* Include the VFP and Neon decoders */ -#include "translate-vfp.inc.c" -#include "translate-neon.inc.c" +#include "translate-vfp.c.inc" +#include "translate-neon.c.inc" static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { @@ -5217,10 +5217,10 @@ static int t16_pop_list(DisasContext *s, int x) * Include the generated decoders. */ -#include "decode-a32.inc.c" -#include "decode-a32-uncond.inc.c" -#include "decode-t32.inc.c" -#include "decode-t16.inc.c" +#include "decode-a32.c.inc" +#include "decode-a32-uncond.c.inc" +#include "decode-t32.c.inc" +#include "decode-t16.c.inc" /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs index 6e35ba2c5c..fb94a0b069 100644 --- a/target/avr/Makefile.objs +++ b/target/avr/Makefile.objs @@ -21,12 +21,12 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py decode-y = $(SRC_PATH)/target/avr/insn.decode -target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE) +target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \ "GEN", $(TARGET_DIR)$@) -target/avr/translate.o: target/avr/decode_insn.inc.c +target/avr/translate.o: target/avr/decode_insn.c.inc obj-y += translate.o cpu.o helper.o obj-y += gdbstub.o diff --git a/target/avr/disas.c b/target/avr/disas.c index 8e1bac4d76..f15dc7911a 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x) /* Include the auto-generated decoder. */ static bool decode_insn(DisasContext *ctx, uint16_t insn); -#include "decode_insn.inc.c" +#include "decode_insn.c.inc" #define output(mnemonic, format, ...) \ (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \ diff --git a/target/avr/translate.c b/target/avr/translate.c index 648dcd5c3e..9eb14f63f0 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -198,7 +198,7 @@ static bool avr_have_feature(DisasContext *ctx, int feature) } static bool decode_insn(DisasContext *ctx, uint16_t insn); -#include "decode_insn.inc.c" +#include "decode_insn.c.inc" /* * Arithmetic Instructions diff --git a/target/cris/translate.c b/target/cris/translate.c index aaa46b5bca..ee5e359c77 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3037,7 +3037,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) return insn_len; } -#include "translate_v10.inc.c" +#include "translate_v10.c.inc" /* * Delay slots on QEMU/CRIS. diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc new file mode 100644 index 0000000000..ae34a0d1a3 --- /dev/null +++ b/target/cris/translate_v10.c.inc @@ -0,0 +1,1312 @@ +/* + * CRISv10 emulation for qemu: main translation routines. + * + * Copyright (c) 2010 AXIS Communications AB + * Written by Edgar E. Iglesias. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "crisv10-decode.h" + +static const char *regnames_v10[] = +{ + "$r0", "$r1", "$r2", "$r3", + "$r4", "$r5", "$r6", "$r7", + "$r8", "$r9", "$r10", "$r11", + "$r12", "$r13", "$sp", "$pc", +}; + +static const char *pregnames_v10[] = +{ + "$bz", "$vr", "$p2", "$p3", + "$wz", "$ccr", "$p6-prefix", "$mof", + "$dz", "$ibr", "$irp", "$srp", + "$bar", "$dccr", "$brp", "$usp", +}; + +/* We need this table to handle preg-moves with implicit width. */ +static int preg_sizes_v10[] = { + 1, /* bz. */ + 1, /* vr. */ + 1, /* pid. */ + 1, /* srs. */ + 2, /* wz. */ + 2, 2, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, +}; + +static inline int dec10_size(unsigned int size) +{ + size++; + if (size == 3) + size++; + return size; +} + +static inline void cris_illegal_insn(DisasContext *dc) +{ + qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc); + t_gen_raise_exception(EXCP_BREAK); +} + +static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val, + unsigned int size, int mem_index) +{ + TCGLabel *l1 = gen_new_label(); + TCGv taddr = tcg_temp_local_new(); + TCGv tval = tcg_temp_local_new(); + TCGv t1 = tcg_temp_local_new(); + dc->postinc = 0; + cris_evaluate_flags(dc); + + tcg_gen_mov_tl(taddr, addr); + tcg_gen_mov_tl(tval, val); + + /* Store only if F flag isn't set */ + tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); + if (size == 1) { + tcg_gen_qemu_st8(tval, taddr, mem_index); + } else if (size == 2) { + tcg_gen_qemu_st16(tval, taddr, mem_index); + } else { + tcg_gen_qemu_st32(tval, taddr, mem_index); + } + gen_set_label(l1); + tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */ + tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/ + tcg_temp_free(t1); + tcg_temp_free(tval); + tcg_temp_free(taddr); +} + +static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, + unsigned int size) +{ + int mem_index = cpu_mmu_index(&dc->cpu->env, false); + + /* If we get a fault on a delayslot we must keep the jmp state in + the cpu-state to be able to re-execute the jmp. */ + if (dc->delayed_branch == 1) { + cris_store_direct_jmp(dc); + } + + /* Conditional writes. We only support the kind were X is known + at translation time. */ + if (dc->flagx_known && dc->flags_x) { + gen_store_v10_conditional(dc, addr, val, size, mem_index); + return; + } + + if (size == 1) { + tcg_gen_qemu_st8(val, addr, mem_index); + } else if (size == 2) { + tcg_gen_qemu_st16(val, addr, mem_index); + } else { + tcg_gen_qemu_st32(val, addr, mem_index); + } +} + + +/* Prefix flag and register are used to handle the more complex + addressing modes. */ +static void cris_set_prefix(DisasContext *dc) +{ + dc->clear_prefix = 0; + dc->tb_flags |= PFIX_FLAG; + tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG); + + /* prefix insns don't clear the x flag. */ + dc->clear_x = 0; + cris_lock_irq(dc); +} + +static void crisv10_prepare_memaddr(DisasContext *dc, + TCGv addr, unsigned int size) +{ + if (dc->tb_flags & PFIX_FLAG) { + tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]); + } else { + tcg_gen_mov_tl(addr, cpu_R[dc->src]); + } +} + +static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size) +{ + unsigned int insn_len = 0; + + if (dc->tb_flags & PFIX_FLAG) { + if (dc->mode == CRISV10_MODE_AUTOINC) { + tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]); + } + } else { + if (dc->mode == CRISV10_MODE_AUTOINC) { + if (dc->src == 15) { + insn_len += size & ~1; + } else { + tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size); + } + } + } + return insn_len; +} + +static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc, + int s_ext, int memsize, TCGv dst) +{ + unsigned int rs; + uint32_t imm; + int is_imm; + int insn_len = 0; + + rs = dc->src; + is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG); + LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n", + rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG); + + /* Load [$rs] onto T1. */ + if (is_imm) { + if (memsize != 4) { + if (s_ext) { + if (memsize == 1) + imm = cpu_ldsb_code(env, dc->pc + 2); + else + imm = cpu_ldsw_code(env, dc->pc + 2); + } else { + if (memsize == 1) + imm = cpu_ldub_code(env, dc->pc + 2); + else + imm = cpu_lduw_code(env, dc->pc + 2); + } + } else + imm = cpu_ldl_code(env, dc->pc + 2); + + tcg_gen_movi_tl(dst, imm); + + if (dc->mode == CRISV10_MODE_AUTOINC) { + insn_len += memsize; + if (memsize == 1) + insn_len++; + tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); + } + } else { + TCGv addr; + + addr = tcg_temp_new(); + cris_flush_cc_state(dc); + crisv10_prepare_memaddr(dc, addr, memsize); + gen_load(dc, dst, addr, memsize, 0); + if (s_ext) + t_gen_sext(dst, dst, memsize); + else + t_gen_zext(dst, dst, memsize); + insn_len += crisv10_post_memaddr(dc, memsize); + tcg_temp_free(addr); + } + + if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) { + dc->dst = dc->src; + } + return insn_len; +} + +static unsigned int dec10_quick_imm(DisasContext *dc) +{ + int32_t imm, simm; + int op; + + /* sign extend. */ + imm = dc->ir & ((1 << 6) - 1); + simm = (int8_t) (imm << 2); + simm >>= 2; + switch (dc->opcode) { + case CRISV10_QIMM_BDAP_R0: + case CRISV10_QIMM_BDAP_R1: + case CRISV10_QIMM_BDAP_R2: + case CRISV10_QIMM_BDAP_R3: + simm = (int8_t)dc->ir; + LOG_DIS("bdap %d $r%d\n", simm, dc->dst); + LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", + dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); + cris_set_prefix(dc); + if (dc->dst == 15) { + tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm); + } else { + tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); + } + break; + + case CRISV10_QIMM_MOVEQ: + LOG_DIS("moveq %d, $r%d\n", simm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(simm), 4); + break; + case CRISV10_QIMM_CMPQ: + LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(simm), 4); + break; + case CRISV10_QIMM_ADDQ: + LOG_DIS("addq %d, $r%d\n", imm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(imm), 4); + break; + case CRISV10_QIMM_ANDQ: + LOG_DIS("andq %d, $r%d\n", simm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(simm), 4); + break; + case CRISV10_QIMM_ASHQ: + LOG_DIS("ashq %d, $r%d\n", simm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + op = imm & (1 << 5); + imm &= 0x1f; + if (op) { + cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(imm), 4); + } else { + /* BTST */ + cris_update_cc_op(dc, CC_OP_FLAGS, 4); + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], + tcg_const_tl(imm), cpu_PR[PR_CCS]); + } + break; + case CRISV10_QIMM_LSHQ: + LOG_DIS("lshq %d, $r%d\n", simm, dc->dst); + + op = CC_OP_LSL; + if (imm & (1 << 5)) { + op = CC_OP_LSR; + } + imm &= 0x1f; + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, op, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(imm), 4); + break; + case CRISV10_QIMM_SUBQ: + LOG_DIS("subq %d, $r%d\n", imm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(imm), 4); + break; + case CRISV10_QIMM_ORQ: + LOG_DIS("andq %d, $r%d\n", simm, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], + cpu_R[dc->dst], tcg_const_tl(simm), 4); + break; + + case CRISV10_QIMM_BCC_R0: + case CRISV10_QIMM_BCC_R1: + case CRISV10_QIMM_BCC_R2: + case CRISV10_QIMM_BCC_R3: + imm = dc->ir & 0xff; + /* bit 0 is a sign bit. */ + if (imm & 1) { + imm |= 0xffffff00; /* sign extend. */ + imm &= ~1; /* get rid of the sign bit. */ + } + imm += 2; + LOG_DIS("b%s %d\n", cc_name(dc->cond), imm); + + cris_cc_mask(dc, 0); + cris_prepare_cc_branch(dc, imm, dc->cond); + break; + + default: + LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", + dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); + cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n"); + break; + } + return 2; +} + +static unsigned int dec10_setclrf(DisasContext *dc) +{ + uint32_t flags; + unsigned int set = ~dc->opcode & 1; + + flags = EXTRACT_FIELD(dc->ir, 0, 3) + | (EXTRACT_FIELD(dc->ir, 12, 15) << 4); + LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags); + + + if (flags & X_FLAG) { + dc->flagx_known = 1; + if (set) + dc->flags_x = X_FLAG; + else + dc->flags_x = 0; + } + + cris_evaluate_flags (dc); + cris_update_cc_op(dc, CC_OP_FLAGS, 4); + cris_update_cc_x(dc); + tcg_gen_movi_tl(cc_op, dc->cc_op); + + if (set) { + tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); + } else { + tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], + ~(flags|F_FLAG_V10|P_FLAG_V10)); + } + + dc->flags_uptodate = 1; + dc->clear_x = 0; + cris_lock_irq(dc); + return 2; +} + +static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext, + TCGv dd, TCGv ds, TCGv sd, TCGv ss) +{ + if (sext) { + t_gen_sext(dd, sd, size); + t_gen_sext(ds, ss, size); + } else { + t_gen_zext(dd, sd, size); + t_gen_zext(ds, ss, size); + } +} + +static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext) +{ + TCGv t[2]; + + t[0] = tcg_temp_new(); + t[1] = tcg_temp_new(); + dec10_reg_prep_sext(dc, size, sext, + t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); + + if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) { + tcg_gen_andi_tl(t[1], t[1], 63); + } + + assert(dc->dst != 15); + cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); + tcg_temp_free(t[0]); + tcg_temp_free(t[1]); +} + +static void dec10_reg_bound(DisasContext *dc, int size) +{ + TCGv t; + + t = tcg_temp_local_new(); + t_gen_zext(t, cpu_R[dc->src], size); + cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); + tcg_temp_free(t); +} + +static void dec10_reg_mul(DisasContext *dc, int size, int sext) +{ + int op = sext ? CC_OP_MULS : CC_OP_MULU; + TCGv t[2]; + + t[0] = tcg_temp_new(); + t[1] = tcg_temp_new(); + dec10_reg_prep_sext(dc, size, sext, + t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); + + cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); + + tcg_temp_free(t[0]); + tcg_temp_free(t[1]); +} + + +static void dec10_reg_movs(DisasContext *dc) +{ + int size = (dc->size & 1) + 1; + TCGv t; + + LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + + t = tcg_temp_new(); + if (dc->ir & 32) + t_gen_sext(t, cpu_R[dc->src], size); + else + t_gen_zext(t, cpu_R[dc->src], size); + + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); + tcg_temp_free(t); +} + +static void dec10_reg_alux(DisasContext *dc, int op) +{ + int size = (dc->size & 1) + 1; + TCGv t; + + LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + + t = tcg_temp_new(); + if (dc->ir & 32) + t_gen_sext(t, cpu_R[dc->src], size); + else + t_gen_zext(t, cpu_R[dc->src], size); + + cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); + tcg_temp_free(t); +} + +static void dec10_reg_mov_pr(DisasContext *dc) +{ + LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]); + cris_lock_irq(dc); + if (dc->src == 15) { + tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + return; + } + if (dc->dst == PR_CCS) { + cris_evaluate_flags(dc); + } + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], + cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]); +} + +static void dec10_reg_abs(DisasContext *dc) +{ + TCGv t0; + + LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst); + + assert(dc->dst != 15); + t0 = tcg_temp_new(); + tcg_gen_sari_tl(t0, cpu_R[dc->src], 31); + tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); + tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); + + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4); + tcg_temp_free(t0); +} + +static void dec10_reg_swap(DisasContext *dc) +{ + TCGv t0; + + LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + t0 = tcg_temp_new(); + tcg_gen_mov_tl(t0, cpu_R[dc->src]); + if (dc->dst & 8) + tcg_gen_not_tl(t0, t0); + if (dc->dst & 4) + t_gen_swapw(t0, t0); + if (dc->dst & 2) + t_gen_swapb(t0, t0); + if (dc->dst & 1) + t_gen_swapr(t0, t0); + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4); + tcg_temp_free(t0); +} + +static void dec10_reg_scc(DisasContext *dc) +{ + int cond = dc->dst; + + LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src); + + gen_tst_cc(dc, cpu_R[dc->src], cond); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0); + + cris_cc_mask(dc, 0); +} + +static unsigned int dec10_reg(DisasContext *dc) +{ + TCGv t; + unsigned int insn_len = 2; + unsigned int size = dec10_size(dc->size); + unsigned int tmp; + + if (dc->size != 3) { + switch (dc->opcode) { + case CRISV10_REG_MOVE_R: + LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_MOVE, size, 0); + if (dc->dst == 15) { + tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + } + break; + case CRISV10_REG_MOVX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_movs(dc); + break; + case CRISV10_REG_ADDX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alux(dc, CC_OP_ADD); + break; + case CRISV10_REG_SUBX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alux(dc, CC_OP_SUB); + break; + case CRISV10_REG_ADD: + LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_ADD, size, 0); + break; + case CRISV10_REG_SUB: + LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_SUB, size, 0); + break; + case CRISV10_REG_CMP: + LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_CMP, size, 0); + break; + case CRISV10_REG_BOUND: + LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_bound(dc, size); + break; + case CRISV10_REG_AND: + LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_AND, size, 0); + break; + case CRISV10_REG_ADDI: + if (dc->src == 15) { + /* nop. */ + return 2; + } + t = tcg_temp_new(); + LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size); + tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3); + tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); + tcg_temp_free(t); + break; + case CRISV10_REG_LSL: + LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_LSL, size, 0); + break; + case CRISV10_REG_LSR: + LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_LSR, size, 0); + break; + case CRISV10_REG_ASR: + LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_ASR, size, 1); + break; + case CRISV10_REG_OR: + LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_OR, size, 0); + break; + case CRISV10_REG_NEG: + LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_NEG, size, 0); + break; + case CRISV10_REG_BIAP: + LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc, + dc->opcode, dc->src, dc->dst, size); + switch (size) { + case 4: tmp = 2; break; + case 2: tmp = 1; break; + case 1: tmp = 0; break; + default: + cpu_abort(CPU(dc->cpu), "Unhandled BIAP"); + break; + } + + t = tcg_temp_new(); + tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp); + if (dc->src == 15) { + tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1); + } else { + tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); + } + tcg_temp_free(t); + cris_set_prefix(dc); + break; + + default: + LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, + dc->opcode, dc->src, dc->dst); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); + break; + } + } else { + switch (dc->opcode) { + case CRISV10_REG_MOVX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_movs(dc); + break; + case CRISV10_REG_ADDX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alux(dc, CC_OP_ADD); + break; + case CRISV10_REG_SUBX: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alux(dc, CC_OP_SUB); + break; + case CRISV10_REG_MOVE_SPR_R: + cris_evaluate_flags(dc); + cris_cc_mask(dc, 0); + dec10_reg_mov_pr(dc); + break; + case CRISV10_REG_MOVE_R_SPR: + LOG_DIS("move r%d p%d\n", dc->src, dc->dst); + cris_evaluate_flags(dc); + if (dc->src != 11) /* fast for srp. */ + dc->cpustate_changed = 1; + t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]); + break; + case CRISV10_REG_SETF: + case CRISV10_REG_CLEARF: + dec10_setclrf(dc); + break; + case CRISV10_REG_SWAP: + dec10_reg_swap(dc); + break; + case CRISV10_REG_ABS: + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_abs(dc); + break; + case CRISV10_REG_LZ: + LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_LZ, 4, 0); + break; + case CRISV10_REG_XOR: + LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_alu(dc, CC_OP_XOR, 4, 0); + break; + case CRISV10_REG_BTST: + LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + cris_update_cc_op(dc, CC_OP_FLAGS, 4); + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], + cpu_R[dc->src], cpu_PR[PR_CCS]); + break; + case CRISV10_REG_DSTEP: + LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst], + cpu_R[dc->dst], cpu_R[dc->src], 4); + break; + case CRISV10_REG_MSTEP: + LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); + cris_evaluate_flags(dc); + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst], + cpu_R[dc->dst], cpu_R[dc->src], 4); + break; + case CRISV10_REG_SCC: + dec10_reg_scc(dc); + break; + default: + LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, + dc->opcode, dc->src, dc->dst); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); + break; + } + } + return insn_len; +} + +static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc, + unsigned int size) +{ + unsigned int insn_len = 2; + TCGv t; + + LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__, + size, dc->src, dc->dst); + + cris_cc_mask(dc, CC_MASK_NZVC); + t = tcg_temp_new(); + insn_len += dec10_prep_move_m(env, dc, 0, size, t); + cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size); + if (dc->dst == 15) { + tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + return insn_len; + } + + tcg_temp_free(t); + return insn_len; +} + +static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) +{ + unsigned int insn_len = 2; + TCGv addr; + + LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst); + addr = tcg_temp_new(); + crisv10_prepare_memaddr(dc, addr, size); + gen_store_v10(dc, addr, cpu_R[dc->dst], size); + insn_len += crisv10_post_memaddr(dc, size); + + return insn_len; +} + +static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc) +{ + unsigned int insn_len = 2, rd = dc->dst; + TCGv t, addr; + + LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); + cris_lock_irq(dc); + + addr = tcg_temp_new(); + t = tcg_temp_new(); + insn_len += dec10_prep_move_m(env, dc, 0, 4, t); + if (rd == 15) { + tcg_gen_mov_tl(env_btarget, t); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + return insn_len; + } + + tcg_gen_mov_tl(cpu_PR[rd], t); + dc->cpustate_changed = 1; + tcg_temp_free(addr); + tcg_temp_free(t); + return insn_len; +} + +static unsigned int dec10_ind_move_pr_m(DisasContext *dc) +{ + unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst]; + TCGv addr, t0; + + LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); + + addr = tcg_temp_new(); + crisv10_prepare_memaddr(dc, addr, size); + if (dc->dst == PR_CCS) { + t0 = tcg_temp_new(); + cris_evaluate_flags(dc); + tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); + gen_store_v10(dc, addr, t0, size); + tcg_temp_free(t0); + } else { + gen_store_v10(dc, addr, cpu_PR[dc->dst], size); + } + t0 = tcg_temp_new(); + insn_len += crisv10_post_memaddr(dc, size); + cris_lock_irq(dc); + + return insn_len; +} + +static void dec10_movem_r_m(DisasContext *dc) +{ + int i, pfix = dc->tb_flags & PFIX_FLAG; + TCGv addr, t0; + + LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__, + dc->dst, dc->src, dc->postinc, dc->ir); + + addr = tcg_temp_new(); + t0 = tcg_temp_new(); + crisv10_prepare_memaddr(dc, addr, 4); + tcg_gen_mov_tl(t0, addr); + for (i = dc->dst; i >= 0; i--) { + if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) { + gen_store_v10(dc, addr, t0, 4); + } else { + gen_store_v10(dc, addr, cpu_R[i], 4); + } + tcg_gen_addi_tl(addr, addr, 4); + } + + if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { + tcg_gen_mov_tl(cpu_R[dc->src], t0); + } + + if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { + tcg_gen_mov_tl(cpu_R[dc->src], addr); + } + tcg_temp_free(addr); + tcg_temp_free(t0); +} + +static void dec10_movem_m_r(DisasContext *dc) +{ + int i, pfix = dc->tb_flags & PFIX_FLAG; + TCGv addr, t0; + + LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__, + dc->src, dc->dst, dc->postinc, dc->ir); + + addr = tcg_temp_new(); + t0 = tcg_temp_new(); + crisv10_prepare_memaddr(dc, addr, 4); + tcg_gen_mov_tl(t0, addr); + for (i = dc->dst; i >= 0; i--) { + gen_load(dc, cpu_R[i], addr, 4, 0); + tcg_gen_addi_tl(addr, addr, 4); + } + + if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { + tcg_gen_mov_tl(cpu_R[dc->src], t0); + } + + if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { + tcg_gen_mov_tl(cpu_R[dc->src], addr); + } + tcg_temp_free(addr); + tcg_temp_free(t0); +} + +static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc, + int op, unsigned int size) +{ + int insn_len = 0; + int rd = dc->dst; + TCGv t[2]; + + cris_alu_m_alloc_temps(t); + insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); + cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size); + if (dc->dst == 15) { + tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + return insn_len; + } + + cris_alu_m_free_temps(t); + + return insn_len; +} + +static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc, + unsigned int size) +{ + int insn_len = 0; + int rd = dc->dst; + TCGv t; + + t = tcg_temp_local_new(); + insn_len += dec10_prep_move_m(env, dc, 0, size, t); + cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4); + if (dc->dst == 15) { + tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + return insn_len; + } + + tcg_temp_free(t); + return insn_len; +} + +static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op) +{ + unsigned int size = (dc->size & 1) ? 2 : 1; + unsigned int sx = !!(dc->size & 2); + int insn_len = 2; + int rd = dc->dst; + TCGv t; + + LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst); + + t = tcg_temp_new(); + + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_prep_move_m(env, dc, sx, size, t); + cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4); + if (dc->dst == 15) { + tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch = 1; + return insn_len; + } + + tcg_temp_free(t); + return insn_len; +} + +static int dec10_dip(CPUCRISState *env, DisasContext *dc) +{ + int insn_len = 2; + uint32_t imm; + + LOG_DIS("dip pc=%x opcode=%d r%d r%d\n", + dc->pc, dc->opcode, dc->src, dc->dst); + if (dc->src == 15) { + imm = cpu_ldl_code(env, dc->pc + 2); + tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm); + if (dc->postinc) + insn_len += 4; + tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); + } else { + gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0); + if (dc->postinc) + tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4); + } + + cris_set_prefix(dc); + return insn_len; +} + +static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size) +{ + int insn_len = 2; + int rd = dc->dst; + + LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n", + dc->pc, dc->opcode, dc->src, dc->dst, size); + + assert(dc->dst != 15); +#if 0 + /* 8bit embedded offset? */ + if (!dc->postinc && (dc->ir & (1 << 11))) { + int simm = dc->ir & 0xff; + + /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */ + /* sign extended. */ + simm = (int8_t)simm; + + tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); + + cris_set_prefix(dc); + return insn_len; + } +#endif + /* Now the rest of the modes are truly indirect. */ + insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]); + tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]); + cris_set_prefix(dc); + return insn_len; +} + +static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) +{ + unsigned int insn_len = 2; + unsigned int size = dec10_size(dc->size); + uint32_t imm; + int32_t simm; + TCGv t[2]; + + if (dc->size != 3) { + switch (dc->opcode) { + case CRISV10_IND_MOVE_M_R: + return dec10_ind_move_m_r(env, dc, size); + break; + case CRISV10_IND_MOVE_R_M: + return dec10_ind_move_r_m(dc, size); + break; + case CRISV10_IND_CMP: + LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size); + break; + case CRISV10_IND_TEST: + LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst); + + cris_evaluate_flags(dc); + cris_cc_mask(dc, CC_MASK_NZVC); + cris_alu_m_alloc_temps(t); + insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); + tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); + cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], + t[0], tcg_const_tl(0), size); + cris_alu_m_free_temps(t); + break; + case CRISV10_IND_ADD: + LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size); + break; + case CRISV10_IND_SUB: + LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size); + break; + case CRISV10_IND_BOUND: + LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_bound(env, dc, size); + break; + case CRISV10_IND_AND: + LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size); + break; + case CRISV10_IND_OR: + LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size); + break; + case CRISV10_IND_MOVX: + insn_len = dec10_alux_m(env, dc, CC_OP_MOVE); + break; + case CRISV10_IND_ADDX: + insn_len = dec10_alux_m(env, dc, CC_OP_ADD); + break; + case CRISV10_IND_SUBX: + insn_len = dec10_alux_m(env, dc, CC_OP_SUB); + break; + case CRISV10_IND_CMPX: + insn_len = dec10_alux_m(env, dc, CC_OP_CMP); + break; + case CRISV10_IND_MUL: + /* This is a reg insn coded in the mem indir space. */ + LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode); + cris_cc_mask(dc, CC_MASK_NZVC); + dec10_reg_mul(dc, size, dc->ir & (1 << 10)); + break; + case CRISV10_IND_BDAP_M: + insn_len = dec10_bdap_m(env, dc, size); + break; + default: + /* + * ADDC for v17: + * + * Instruction format: ADDC [Rs],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)| + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ + * + * Instruction format: ADDC [Rs+],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)| + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + */ + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && + env->pregs[PR_VR] == 17) { + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); + break; + } + + LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", + dc->pc, size, dc->opcode, dc->src, dc->dst); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); + break; + } + return insn_len; + } + + switch (dc->opcode) { + case CRISV10_IND_MOVE_M_SPR: + insn_len = dec10_ind_move_m_pr(env, dc); + break; + case CRISV10_IND_MOVE_SPR_M: + insn_len = dec10_ind_move_pr_m(dc); + break; + case CRISV10_IND_JUMP_M: + if (dc->src == 15) { + LOG_DIS("jump.%d %d r%d r%d direct\n", size, + dc->opcode, dc->src, dc->dst); + imm = cpu_ldl_code(env, dc->pc + 2); + if (dc->mode == CRISV10_MODE_AUTOINC) + insn_len += size; + + t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + dc->jmp_pc = imm; + cris_prepare_jmp(dc, JMP_DIRECT); + dc->delayed_branch--; /* v10 has no dslot here. */ + } else { + if (dc->dst == 14) { + LOG_DIS("break %d\n", dc->src); + cris_evaluate_flags(dc); + tcg_gen_movi_tl(env_pc, dc->pc + 2); + t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2)); + t_gen_raise_exception(EXCP_BREAK); + dc->is_jmp = DISAS_UPDATE; + return insn_len; + } + LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, + dc->opcode, dc->src, dc->dst); + t[0] = tcg_temp_new(); + t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + crisv10_prepare_memaddr(dc, t[0], size); + gen_load(dc, env_btarget, t[0], 4, 0); + insn_len += crisv10_post_memaddr(dc, size); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch--; /* v10 has no dslot here. */ + tcg_temp_free(t[0]); + } + break; + + case CRISV10_IND_MOVEM_R_M: + LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n", + dc->pc, dc->opcode, dc->dst, dc->src); + dec10_movem_r_m(dc); + break; + case CRISV10_IND_MOVEM_M_R: + LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode); + dec10_movem_m_r(dc); + break; + case CRISV10_IND_JUMP_R: + LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", + dc->pc, dc->opcode, dc->dst, dc->src); + tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); + t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + cris_prepare_jmp(dc, JMP_INDIRECT); + dc->delayed_branch--; /* v10 has no dslot here. */ + break; + case CRISV10_IND_MOVX: + insn_len = dec10_alux_m(env, dc, CC_OP_MOVE); + break; + case CRISV10_IND_ADDX: + insn_len = dec10_alux_m(env, dc, CC_OP_ADD); + break; + case CRISV10_IND_SUBX: + insn_len = dec10_alux_m(env, dc, CC_OP_SUB); + break; + case CRISV10_IND_CMPX: + insn_len = dec10_alux_m(env, dc, CC_OP_CMP); + break; + case CRISV10_IND_DIP: + insn_len = dec10_dip(env, dc); + break; + case CRISV10_IND_BCC_M: + + cris_cc_mask(dc, 0); + simm = cpu_ldsw_code(env, dc->pc + 2); + simm += 4; + + LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm); + cris_prepare_cc_branch(dc, simm, dc->cond); + insn_len = 4; + break; + default: + LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); + cpu_abort(CPU(dc->cpu), "Unhandled opcode"); + break; + } + + return insn_len; +} + +static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc) +{ + unsigned int insn_len = 2; + + /* Load a halfword onto the instruction register. */ + dc->ir = cpu_lduw_code(env, dc->pc); + + /* Now decode it. */ + dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9); + dc->mode = EXTRACT_FIELD(dc->ir, 10, 11); + dc->src = EXTRACT_FIELD(dc->ir, 0, 3); + dc->size = EXTRACT_FIELD(dc->ir, 4, 5); + dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15); + dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); + + dc->clear_prefix = 1; + + /* FIXME: What if this insn insn't 2 in length?? */ + if (dc->src == 15 || dc->dst == 15) + tcg_gen_movi_tl(cpu_R[15], dc->pc + 2); + + switch (dc->mode) { + case CRISV10_MODE_QIMMEDIATE: + insn_len = dec10_quick_imm(dc); + break; + case CRISV10_MODE_REG: + insn_len = dec10_reg(dc); + break; + case CRISV10_MODE_AUTOINC: + case CRISV10_MODE_INDIRECT: + insn_len = dec10_ind(env, dc); + break; + } + + if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) { + dc->tb_flags &= ~PFIX_FLAG; + tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG); + if (dc->tb_flags != dc->tb->flags) { + dc->cpustate_changed = 1; + } + } + + /* CRISv10 locks out interrupts on dslots. */ + if (dc->delayed_branch == 2) { + cris_lock_irq(dc); + } + return insn_len; +} + +void cris_initialize_crisv10_tcg(void) +{ + int i; + + cc_x = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_x), "cc_x"); + cc_src = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_src), "cc_src"); + cc_dest = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_dest), + "cc_dest"); + cc_result = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_result), + "cc_result"); + cc_op = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_op), "cc_op"); + cc_size = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_size), + "cc_size"); + cc_mask = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, cc_mask), + "cc_mask"); + + env_pc = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, pc), + "pc"); + env_btarget = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, btarget), + "btarget"); + env_btaken = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, btaken), + "btaken"); + for (i = 0; i < 16; i++) { + cpu_R[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, regs[i]), + regnames_v10[i]); + } + for (i = 0; i < 16; i++) { + cpu_PR[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUCRISState, pregs[i]), + pregnames_v10[i]); + } +} diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.inc.c deleted file mode 100644 index ae34a0d1a3..0000000000 --- a/target/cris/translate_v10.inc.c +++ /dev/null @@ -1,1312 +0,0 @@ -/* - * CRISv10 emulation for qemu: main translation routines. - * - * Copyright (c) 2010 AXIS Communications AB - * Written by Edgar E. Iglesias. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "crisv10-decode.h" - -static const char *regnames_v10[] = -{ - "$r0", "$r1", "$r2", "$r3", - "$r4", "$r5", "$r6", "$r7", - "$r8", "$r9", "$r10", "$r11", - "$r12", "$r13", "$sp", "$pc", -}; - -static const char *pregnames_v10[] = -{ - "$bz", "$vr", "$p2", "$p3", - "$wz", "$ccr", "$p6-prefix", "$mof", - "$dz", "$ibr", "$irp", "$srp", - "$bar", "$dccr", "$brp", "$usp", -}; - -/* We need this table to handle preg-moves with implicit width. */ -static int preg_sizes_v10[] = { - 1, /* bz. */ - 1, /* vr. */ - 1, /* pid. */ - 1, /* srs. */ - 2, /* wz. */ - 2, 2, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, -}; - -static inline int dec10_size(unsigned int size) -{ - size++; - if (size == 3) - size++; - return size; -} - -static inline void cris_illegal_insn(DisasContext *dc) -{ - qemu_log_mask(LOG_GUEST_ERROR, "illegal insn at pc=%x\n", dc->pc); - t_gen_raise_exception(EXCP_BREAK); -} - -static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val, - unsigned int size, int mem_index) -{ - TCGLabel *l1 = gen_new_label(); - TCGv taddr = tcg_temp_local_new(); - TCGv tval = tcg_temp_local_new(); - TCGv t1 = tcg_temp_local_new(); - dc->postinc = 0; - cris_evaluate_flags(dc); - - tcg_gen_mov_tl(taddr, addr); - tcg_gen_mov_tl(tval, val); - - /* Store only if F flag isn't set */ - tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - if (size == 1) { - tcg_gen_qemu_st8(tval, taddr, mem_index); - } else if (size == 2) { - tcg_gen_qemu_st16(tval, taddr, mem_index); - } else { - tcg_gen_qemu_st32(tval, taddr, mem_index); - } - gen_set_label(l1); - tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */ - tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/ - tcg_temp_free(t1); - tcg_temp_free(tval); - tcg_temp_free(taddr); -} - -static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, - unsigned int size) -{ - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - - /* If we get a fault on a delayslot we must keep the jmp state in - the cpu-state to be able to re-execute the jmp. */ - if (dc->delayed_branch == 1) { - cris_store_direct_jmp(dc); - } - - /* Conditional writes. We only support the kind were X is known - at translation time. */ - if (dc->flagx_known && dc->flags_x) { - gen_store_v10_conditional(dc, addr, val, size, mem_index); - return; - } - - if (size == 1) { - tcg_gen_qemu_st8(val, addr, mem_index); - } else if (size == 2) { - tcg_gen_qemu_st16(val, addr, mem_index); - } else { - tcg_gen_qemu_st32(val, addr, mem_index); - } -} - - -/* Prefix flag and register are used to handle the more complex - addressing modes. */ -static void cris_set_prefix(DisasContext *dc) -{ - dc->clear_prefix = 0; - dc->tb_flags |= PFIX_FLAG; - tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG); - - /* prefix insns don't clear the x flag. */ - dc->clear_x = 0; - cris_lock_irq(dc); -} - -static void crisv10_prepare_memaddr(DisasContext *dc, - TCGv addr, unsigned int size) -{ - if (dc->tb_flags & PFIX_FLAG) { - tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]); - } else { - tcg_gen_mov_tl(addr, cpu_R[dc->src]); - } -} - -static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size) -{ - unsigned int insn_len = 0; - - if (dc->tb_flags & PFIX_FLAG) { - if (dc->mode == CRISV10_MODE_AUTOINC) { - tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]); - } - } else { - if (dc->mode == CRISV10_MODE_AUTOINC) { - if (dc->src == 15) { - insn_len += size & ~1; - } else { - tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size); - } - } - } - return insn_len; -} - -static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc, - int s_ext, int memsize, TCGv dst) -{ - unsigned int rs; - uint32_t imm; - int is_imm; - int insn_len = 0; - - rs = dc->src; - is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG); - LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n", - rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG); - - /* Load [$rs] onto T1. */ - if (is_imm) { - if (memsize != 4) { - if (s_ext) { - if (memsize == 1) - imm = cpu_ldsb_code(env, dc->pc + 2); - else - imm = cpu_ldsw_code(env, dc->pc + 2); - } else { - if (memsize == 1) - imm = cpu_ldub_code(env, dc->pc + 2); - else - imm = cpu_lduw_code(env, dc->pc + 2); - } - } else - imm = cpu_ldl_code(env, dc->pc + 2); - - tcg_gen_movi_tl(dst, imm); - - if (dc->mode == CRISV10_MODE_AUTOINC) { - insn_len += memsize; - if (memsize == 1) - insn_len++; - tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); - } - } else { - TCGv addr; - - addr = tcg_temp_new(); - cris_flush_cc_state(dc); - crisv10_prepare_memaddr(dc, addr, memsize); - gen_load(dc, dst, addr, memsize, 0); - if (s_ext) - t_gen_sext(dst, dst, memsize); - else - t_gen_zext(dst, dst, memsize); - insn_len += crisv10_post_memaddr(dc, memsize); - tcg_temp_free(addr); - } - - if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) { - dc->dst = dc->src; - } - return insn_len; -} - -static unsigned int dec10_quick_imm(DisasContext *dc) -{ - int32_t imm, simm; - int op; - - /* sign extend. */ - imm = dc->ir & ((1 << 6) - 1); - simm = (int8_t) (imm << 2); - simm >>= 2; - switch (dc->opcode) { - case CRISV10_QIMM_BDAP_R0: - case CRISV10_QIMM_BDAP_R1: - case CRISV10_QIMM_BDAP_R2: - case CRISV10_QIMM_BDAP_R3: - simm = (int8_t)dc->ir; - LOG_DIS("bdap %d $r%d\n", simm, dc->dst); - LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", - dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); - cris_set_prefix(dc); - if (dc->dst == 15) { - tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm); - } else { - tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); - } - break; - - case CRISV10_QIMM_MOVEQ: - LOG_DIS("moveq %d, $r%d\n", simm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); - break; - case CRISV10_QIMM_CMPQ: - LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); - break; - case CRISV10_QIMM_ADDQ: - LOG_DIS("addq %d, $r%d\n", imm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); - break; - case CRISV10_QIMM_ANDQ: - LOG_DIS("andq %d, $r%d\n", simm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); - break; - case CRISV10_QIMM_ASHQ: - LOG_DIS("ashq %d, $r%d\n", simm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - op = imm & (1 << 5); - imm &= 0x1f; - if (op) { - cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); - } else { - /* BTST */ - cris_update_cc_op(dc, CC_OP_FLAGS, 4); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], - tcg_const_tl(imm), cpu_PR[PR_CCS]); - } - break; - case CRISV10_QIMM_LSHQ: - LOG_DIS("lshq %d, $r%d\n", simm, dc->dst); - - op = CC_OP_LSL; - if (imm & (1 << 5)) { - op = CC_OP_LSR; - } - imm &= 0x1f; - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, op, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); - break; - case CRISV10_QIMM_SUBQ: - LOG_DIS("subq %d, $r%d\n", imm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); - break; - case CRISV10_QIMM_ORQ: - LOG_DIS("andq %d, $r%d\n", simm, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); - break; - - case CRISV10_QIMM_BCC_R0: - case CRISV10_QIMM_BCC_R1: - case CRISV10_QIMM_BCC_R2: - case CRISV10_QIMM_BCC_R3: - imm = dc->ir & 0xff; - /* bit 0 is a sign bit. */ - if (imm & 1) { - imm |= 0xffffff00; /* sign extend. */ - imm &= ~1; /* get rid of the sign bit. */ - } - imm += 2; - LOG_DIS("b%s %d\n", cc_name(dc->cond), imm); - - cris_cc_mask(dc, 0); - cris_prepare_cc_branch(dc, imm, dc->cond); - break; - - default: - LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", - dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); - cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n"); - break; - } - return 2; -} - -static unsigned int dec10_setclrf(DisasContext *dc) -{ - uint32_t flags; - unsigned int set = ~dc->opcode & 1; - - flags = EXTRACT_FIELD(dc->ir, 0, 3) - | (EXTRACT_FIELD(dc->ir, 12, 15) << 4); - LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags); - - - if (flags & X_FLAG) { - dc->flagx_known = 1; - if (set) - dc->flags_x = X_FLAG; - else - dc->flags_x = 0; - } - - cris_evaluate_flags (dc); - cris_update_cc_op(dc, CC_OP_FLAGS, 4); - cris_update_cc_x(dc); - tcg_gen_movi_tl(cc_op, dc->cc_op); - - if (set) { - tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); - } else { - tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], - ~(flags|F_FLAG_V10|P_FLAG_V10)); - } - - dc->flags_uptodate = 1; - dc->clear_x = 0; - cris_lock_irq(dc); - return 2; -} - -static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext, - TCGv dd, TCGv ds, TCGv sd, TCGv ss) -{ - if (sext) { - t_gen_sext(dd, sd, size); - t_gen_sext(ds, ss, size); - } else { - t_gen_zext(dd, sd, size); - t_gen_zext(ds, ss, size); - } -} - -static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext) -{ - TCGv t[2]; - - t[0] = tcg_temp_new(); - t[1] = tcg_temp_new(); - dec10_reg_prep_sext(dc, size, sext, - t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); - - if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) { - tcg_gen_andi_tl(t[1], t[1], 63); - } - - assert(dc->dst != 15); - cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); -} - -static void dec10_reg_bound(DisasContext *dc, int size) -{ - TCGv t; - - t = tcg_temp_local_new(); - t_gen_zext(t, cpu_R[dc->src], size); - cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); -} - -static void dec10_reg_mul(DisasContext *dc, int size, int sext) -{ - int op = sext ? CC_OP_MULS : CC_OP_MULU; - TCGv t[2]; - - t[0] = tcg_temp_new(); - t[1] = tcg_temp_new(); - dec10_reg_prep_sext(dc, size, sext, - t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); - - cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); - - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); -} - - -static void dec10_reg_movs(DisasContext *dc) -{ - int size = (dc->size & 1) + 1; - TCGv t; - - LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - - t = tcg_temp_new(); - if (dc->ir & 32) - t_gen_sext(t, cpu_R[dc->src], size); - else - t_gen_zext(t, cpu_R[dc->src], size); - - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); -} - -static void dec10_reg_alux(DisasContext *dc, int op) -{ - int size = (dc->size & 1) + 1; - TCGv t; - - LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - - t = tcg_temp_new(); - if (dc->ir & 32) - t_gen_sext(t, cpu_R[dc->src], size); - else - t_gen_zext(t, cpu_R[dc->src], size); - - cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); -} - -static void dec10_reg_mov_pr(DisasContext *dc) -{ - LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]); - cris_lock_irq(dc); - if (dc->src == 15) { - tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - return; - } - if (dc->dst == PR_CCS) { - cris_evaluate_flags(dc); - } - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], - cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]); -} - -static void dec10_reg_abs(DisasContext *dc) -{ - TCGv t0; - - LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst); - - assert(dc->dst != 15); - t0 = tcg_temp_new(); - tcg_gen_sari_tl(t0, cpu_R[dc->src], 31); - tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); - tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); - - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4); - tcg_temp_free(t0); -} - -static void dec10_reg_swap(DisasContext *dc) -{ - TCGv t0; - - LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - t0 = tcg_temp_new(); - tcg_gen_mov_tl(t0, cpu_R[dc->src]); - if (dc->dst & 8) - tcg_gen_not_tl(t0, t0); - if (dc->dst & 4) - t_gen_swapw(t0, t0); - if (dc->dst & 2) - t_gen_swapb(t0, t0); - if (dc->dst & 1) - t_gen_swapr(t0, t0); - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4); - tcg_temp_free(t0); -} - -static void dec10_reg_scc(DisasContext *dc) -{ - int cond = dc->dst; - - LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src); - - gen_tst_cc(dc, cpu_R[dc->src], cond); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0); - - cris_cc_mask(dc, 0); -} - -static unsigned int dec10_reg(DisasContext *dc) -{ - TCGv t; - unsigned int insn_len = 2; - unsigned int size = dec10_size(dc->size); - unsigned int tmp; - - if (dc->size != 3) { - switch (dc->opcode) { - case CRISV10_REG_MOVE_R: - LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_MOVE, size, 0); - if (dc->dst == 15) { - tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - } - break; - case CRISV10_REG_MOVX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_movs(dc); - break; - case CRISV10_REG_ADDX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alux(dc, CC_OP_ADD); - break; - case CRISV10_REG_SUBX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alux(dc, CC_OP_SUB); - break; - case CRISV10_REG_ADD: - LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_ADD, size, 0); - break; - case CRISV10_REG_SUB: - LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_SUB, size, 0); - break; - case CRISV10_REG_CMP: - LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_CMP, size, 0); - break; - case CRISV10_REG_BOUND: - LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_bound(dc, size); - break; - case CRISV10_REG_AND: - LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_AND, size, 0); - break; - case CRISV10_REG_ADDI: - if (dc->src == 15) { - /* nop. */ - return 2; - } - t = tcg_temp_new(); - LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size); - tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3); - tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); - tcg_temp_free(t); - break; - case CRISV10_REG_LSL: - LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_LSL, size, 0); - break; - case CRISV10_REG_LSR: - LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_LSR, size, 0); - break; - case CRISV10_REG_ASR: - LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_ASR, size, 1); - break; - case CRISV10_REG_OR: - LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_OR, size, 0); - break; - case CRISV10_REG_NEG: - LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_NEG, size, 0); - break; - case CRISV10_REG_BIAP: - LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc, - dc->opcode, dc->src, dc->dst, size); - switch (size) { - case 4: tmp = 2; break; - case 2: tmp = 1; break; - case 1: tmp = 0; break; - default: - cpu_abort(CPU(dc->cpu), "Unhandled BIAP"); - break; - } - - t = tcg_temp_new(); - tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp); - if (dc->src == 15) { - tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1); - } else { - tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); - } - tcg_temp_free(t); - cris_set_prefix(dc); - break; - - default: - LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, - dc->opcode, dc->src, dc->dst); - cpu_abort(CPU(dc->cpu), "Unhandled opcode"); - break; - } - } else { - switch (dc->opcode) { - case CRISV10_REG_MOVX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_movs(dc); - break; - case CRISV10_REG_ADDX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alux(dc, CC_OP_ADD); - break; - case CRISV10_REG_SUBX: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alux(dc, CC_OP_SUB); - break; - case CRISV10_REG_MOVE_SPR_R: - cris_evaluate_flags(dc); - cris_cc_mask(dc, 0); - dec10_reg_mov_pr(dc); - break; - case CRISV10_REG_MOVE_R_SPR: - LOG_DIS("move r%d p%d\n", dc->src, dc->dst); - cris_evaluate_flags(dc); - if (dc->src != 11) /* fast for srp. */ - dc->cpustate_changed = 1; - t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]); - break; - case CRISV10_REG_SETF: - case CRISV10_REG_CLEARF: - dec10_setclrf(dc); - break; - case CRISV10_REG_SWAP: - dec10_reg_swap(dc); - break; - case CRISV10_REG_ABS: - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_abs(dc); - break; - case CRISV10_REG_LZ: - LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_LZ, 4, 0); - break; - case CRISV10_REG_XOR: - LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_alu(dc, CC_OP_XOR, 4, 0); - break; - case CRISV10_REG_BTST: - LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - cris_update_cc_op(dc, CC_OP_FLAGS, 4); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], - cpu_R[dc->src], cpu_PR[PR_CCS]); - break; - case CRISV10_REG_DSTEP: - LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst], - cpu_R[dc->dst], cpu_R[dc->src], 4); - break; - case CRISV10_REG_MSTEP: - LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); - cris_evaluate_flags(dc); - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst], - cpu_R[dc->dst], cpu_R[dc->src], 4); - break; - case CRISV10_REG_SCC: - dec10_reg_scc(dc); - break; - default: - LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, - dc->opcode, dc->src, dc->dst); - cpu_abort(CPU(dc->cpu), "Unhandled opcode"); - break; - } - } - return insn_len; -} - -static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc, - unsigned int size) -{ - unsigned int insn_len = 2; - TCGv t; - - LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__, - size, dc->src, dc->dst); - - cris_cc_mask(dc, CC_MASK_NZVC); - t = tcg_temp_new(); - insn_len += dec10_prep_move_m(env, dc, 0, size, t); - cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size); - if (dc->dst == 15) { - tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - return insn_len; - } - - tcg_temp_free(t); - return insn_len; -} - -static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) -{ - unsigned int insn_len = 2; - TCGv addr; - - LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst); - addr = tcg_temp_new(); - crisv10_prepare_memaddr(dc, addr, size); - gen_store_v10(dc, addr, cpu_R[dc->dst], size); - insn_len += crisv10_post_memaddr(dc, size); - - return insn_len; -} - -static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc) -{ - unsigned int insn_len = 2, rd = dc->dst; - TCGv t, addr; - - LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); - cris_lock_irq(dc); - - addr = tcg_temp_new(); - t = tcg_temp_new(); - insn_len += dec10_prep_move_m(env, dc, 0, 4, t); - if (rd == 15) { - tcg_gen_mov_tl(env_btarget, t); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - return insn_len; - } - - tcg_gen_mov_tl(cpu_PR[rd], t); - dc->cpustate_changed = 1; - tcg_temp_free(addr); - tcg_temp_free(t); - return insn_len; -} - -static unsigned int dec10_ind_move_pr_m(DisasContext *dc) -{ - unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst]; - TCGv addr, t0; - - LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); - - addr = tcg_temp_new(); - crisv10_prepare_memaddr(dc, addr, size); - if (dc->dst == PR_CCS) { - t0 = tcg_temp_new(); - cris_evaluate_flags(dc); - tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); - gen_store_v10(dc, addr, t0, size); - tcg_temp_free(t0); - } else { - gen_store_v10(dc, addr, cpu_PR[dc->dst], size); - } - t0 = tcg_temp_new(); - insn_len += crisv10_post_memaddr(dc, size); - cris_lock_irq(dc); - - return insn_len; -} - -static void dec10_movem_r_m(DisasContext *dc) -{ - int i, pfix = dc->tb_flags & PFIX_FLAG; - TCGv addr, t0; - - LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__, - dc->dst, dc->src, dc->postinc, dc->ir); - - addr = tcg_temp_new(); - t0 = tcg_temp_new(); - crisv10_prepare_memaddr(dc, addr, 4); - tcg_gen_mov_tl(t0, addr); - for (i = dc->dst; i >= 0; i--) { - if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) { - gen_store_v10(dc, addr, t0, 4); - } else { - gen_store_v10(dc, addr, cpu_R[i], 4); - } - tcg_gen_addi_tl(addr, addr, 4); - } - - if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { - tcg_gen_mov_tl(cpu_R[dc->src], t0); - } - - if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { - tcg_gen_mov_tl(cpu_R[dc->src], addr); - } - tcg_temp_free(addr); - tcg_temp_free(t0); -} - -static void dec10_movem_m_r(DisasContext *dc) -{ - int i, pfix = dc->tb_flags & PFIX_FLAG; - TCGv addr, t0; - - LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__, - dc->src, dc->dst, dc->postinc, dc->ir); - - addr = tcg_temp_new(); - t0 = tcg_temp_new(); - crisv10_prepare_memaddr(dc, addr, 4); - tcg_gen_mov_tl(t0, addr); - for (i = dc->dst; i >= 0; i--) { - gen_load(dc, cpu_R[i], addr, 4, 0); - tcg_gen_addi_tl(addr, addr, 4); - } - - if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { - tcg_gen_mov_tl(cpu_R[dc->src], t0); - } - - if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { - tcg_gen_mov_tl(cpu_R[dc->src], addr); - } - tcg_temp_free(addr); - tcg_temp_free(t0); -} - -static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc, - int op, unsigned int size) -{ - int insn_len = 0; - int rd = dc->dst; - TCGv t[2]; - - cris_alu_m_alloc_temps(t); - insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); - cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size); - if (dc->dst == 15) { - tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - return insn_len; - } - - cris_alu_m_free_temps(t); - - return insn_len; -} - -static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc, - unsigned int size) -{ - int insn_len = 0; - int rd = dc->dst; - TCGv t; - - t = tcg_temp_local_new(); - insn_len += dec10_prep_move_m(env, dc, 0, size, t); - cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4); - if (dc->dst == 15) { - tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - return insn_len; - } - - tcg_temp_free(t); - return insn_len; -} - -static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op) -{ - unsigned int size = (dc->size & 1) ? 2 : 1; - unsigned int sx = !!(dc->size & 2); - int insn_len = 2; - int rd = dc->dst; - TCGv t; - - LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst); - - t = tcg_temp_new(); - - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_prep_move_m(env, dc, sx, size, t); - cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4); - if (dc->dst == 15) { - tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch = 1; - return insn_len; - } - - tcg_temp_free(t); - return insn_len; -} - -static int dec10_dip(CPUCRISState *env, DisasContext *dc) -{ - int insn_len = 2; - uint32_t imm; - - LOG_DIS("dip pc=%x opcode=%d r%d r%d\n", - dc->pc, dc->opcode, dc->src, dc->dst); - if (dc->src == 15) { - imm = cpu_ldl_code(env, dc->pc + 2); - tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm); - if (dc->postinc) - insn_len += 4; - tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); - } else { - gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0); - if (dc->postinc) - tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4); - } - - cris_set_prefix(dc); - return insn_len; -} - -static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size) -{ - int insn_len = 2; - int rd = dc->dst; - - LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n", - dc->pc, dc->opcode, dc->src, dc->dst, size); - - assert(dc->dst != 15); -#if 0 - /* 8bit embedded offset? */ - if (!dc->postinc && (dc->ir & (1 << 11))) { - int simm = dc->ir & 0xff; - - /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */ - /* sign extended. */ - simm = (int8_t)simm; - - tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); - - cris_set_prefix(dc); - return insn_len; - } -#endif - /* Now the rest of the modes are truly indirect. */ - insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]); - tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]); - cris_set_prefix(dc); - return insn_len; -} - -static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) -{ - unsigned int insn_len = 2; - unsigned int size = dec10_size(dc->size); - uint32_t imm; - int32_t simm; - TCGv t[2]; - - if (dc->size != 3) { - switch (dc->opcode) { - case CRISV10_IND_MOVE_M_R: - return dec10_ind_move_m_r(env, dc, size); - break; - case CRISV10_IND_MOVE_R_M: - return dec10_ind_move_r_m(dc, size); - break; - case CRISV10_IND_CMP: - LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size); - break; - case CRISV10_IND_TEST: - LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst); - - cris_evaluate_flags(dc); - cris_cc_mask(dc, CC_MASK_NZVC); - cris_alu_m_alloc_temps(t); - insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); - tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); - cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], - t[0], tcg_const_tl(0), size); - cris_alu_m_free_temps(t); - break; - case CRISV10_IND_ADD: - LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size); - break; - case CRISV10_IND_SUB: - LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size); - break; - case CRISV10_IND_BOUND: - LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_bound(env, dc, size); - break; - case CRISV10_IND_AND: - LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size); - break; - case CRISV10_IND_OR: - LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size); - break; - case CRISV10_IND_MOVX: - insn_len = dec10_alux_m(env, dc, CC_OP_MOVE); - break; - case CRISV10_IND_ADDX: - insn_len = dec10_alux_m(env, dc, CC_OP_ADD); - break; - case CRISV10_IND_SUBX: - insn_len = dec10_alux_m(env, dc, CC_OP_SUB); - break; - case CRISV10_IND_CMPX: - insn_len = dec10_alux_m(env, dc, CC_OP_CMP); - break; - case CRISV10_IND_MUL: - /* This is a reg insn coded in the mem indir space. */ - LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode); - cris_cc_mask(dc, CC_MASK_NZVC); - dec10_reg_mul(dc, size, dc->ir & (1 << 10)); - break; - case CRISV10_IND_BDAP_M: - insn_len = dec10_bdap_m(env, dc, size); - break; - default: - /* - * ADDC for v17: - * - * Instruction format: ADDC [Rs],Rd - * - * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ - * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)| - * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ - * - * Instruction format: ADDC [Rs+],Rd - * - * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ - * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)| - * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ - */ - if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && - env->pregs[PR_VR] == 17) { - LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); - cris_cc_mask(dc, CC_MASK_NZVC); - insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); - break; - } - - LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", - dc->pc, size, dc->opcode, dc->src, dc->dst); - cpu_abort(CPU(dc->cpu), "Unhandled opcode"); - break; - } - return insn_len; - } - - switch (dc->opcode) { - case CRISV10_IND_MOVE_M_SPR: - insn_len = dec10_ind_move_m_pr(env, dc); - break; - case CRISV10_IND_MOVE_SPR_M: - insn_len = dec10_ind_move_pr_m(dc); - break; - case CRISV10_IND_JUMP_M: - if (dc->src == 15) { - LOG_DIS("jump.%d %d r%d r%d direct\n", size, - dc->opcode, dc->src, dc->dst); - imm = cpu_ldl_code(env, dc->pc + 2); - if (dc->mode == CRISV10_MODE_AUTOINC) - insn_len += size; - - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); - dc->jmp_pc = imm; - cris_prepare_jmp(dc, JMP_DIRECT); - dc->delayed_branch--; /* v10 has no dslot here. */ - } else { - if (dc->dst == 14) { - LOG_DIS("break %d\n", dc->src); - cris_evaluate_flags(dc); - tcg_gen_movi_tl(env_pc, dc->pc + 2); - t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2)); - t_gen_raise_exception(EXCP_BREAK); - dc->is_jmp = DISAS_UPDATE; - return insn_len; - } - LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, - dc->opcode, dc->src, dc->dst); - t[0] = tcg_temp_new(); - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); - crisv10_prepare_memaddr(dc, t[0], size); - gen_load(dc, env_btarget, t[0], 4, 0); - insn_len += crisv10_post_memaddr(dc, size); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch--; /* v10 has no dslot here. */ - tcg_temp_free(t[0]); - } - break; - - case CRISV10_IND_MOVEM_R_M: - LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n", - dc->pc, dc->opcode, dc->dst, dc->src); - dec10_movem_r_m(dc); - break; - case CRISV10_IND_MOVEM_M_R: - LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode); - dec10_movem_m_r(dc); - break; - case CRISV10_IND_JUMP_R: - LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", - dc->pc, dc->opcode, dc->dst, dc->src); - tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); - cris_prepare_jmp(dc, JMP_INDIRECT); - dc->delayed_branch--; /* v10 has no dslot here. */ - break; - case CRISV10_IND_MOVX: - insn_len = dec10_alux_m(env, dc, CC_OP_MOVE); - break; - case CRISV10_IND_ADDX: - insn_len = dec10_alux_m(env, dc, CC_OP_ADD); - break; - case CRISV10_IND_SUBX: - insn_len = dec10_alux_m(env, dc, CC_OP_SUB); - break; - case CRISV10_IND_CMPX: - insn_len = dec10_alux_m(env, dc, CC_OP_CMP); - break; - case CRISV10_IND_DIP: - insn_len = dec10_dip(env, dc); - break; - case CRISV10_IND_BCC_M: - - cris_cc_mask(dc, 0); - simm = cpu_ldsw_code(env, dc->pc + 2); - simm += 4; - - LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm); - cris_prepare_cc_branch(dc, simm, dc->cond); - insn_len = 4; - break; - default: - LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); - cpu_abort(CPU(dc->cpu), "Unhandled opcode"); - break; - } - - return insn_len; -} - -static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc) -{ - unsigned int insn_len = 2; - - /* Load a halfword onto the instruction register. */ - dc->ir = cpu_lduw_code(env, dc->pc); - - /* Now decode it. */ - dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9); - dc->mode = EXTRACT_FIELD(dc->ir, 10, 11); - dc->src = EXTRACT_FIELD(dc->ir, 0, 3); - dc->size = EXTRACT_FIELD(dc->ir, 4, 5); - dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15); - dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); - - dc->clear_prefix = 1; - - /* FIXME: What if this insn insn't 2 in length?? */ - if (dc->src == 15 || dc->dst == 15) - tcg_gen_movi_tl(cpu_R[15], dc->pc + 2); - - switch (dc->mode) { - case CRISV10_MODE_QIMMEDIATE: - insn_len = dec10_quick_imm(dc); - break; - case CRISV10_MODE_REG: - insn_len = dec10_reg(dc); - break; - case CRISV10_MODE_AUTOINC: - case CRISV10_MODE_INDIRECT: - insn_len = dec10_ind(env, dc); - break; - } - - if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) { - dc->tb_flags &= ~PFIX_FLAG; - tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG); - if (dc->tb_flags != dc->tb->flags) { - dc->cpustate_changed = 1; - } - } - - /* CRISv10 locks out interrupts on dslots. */ - if (dc->delayed_branch == 2) { - cris_lock_irq(dc); - } - return insn_len; -} - -void cris_initialize_crisv10_tcg(void) -{ - int i; - - cc_x = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_x), "cc_x"); - cc_src = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_src), "cc_src"); - cc_dest = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_dest), - "cc_dest"); - cc_result = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_result), - "cc_result"); - cc_op = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_op), "cc_op"); - cc_size = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_size), - "cc_size"); - cc_mask = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, cc_mask), - "cc_mask"); - - env_pc = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, pc), - "pc"); - env_btarget = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, btarget), - "btarget"); - env_btaken = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, btaken), - "btaken"); - for (i = 0; i < 16; i++) { - cpu_R[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, regs[i]), - regnames_v10[i]); - } - for (i = 0; i < 16; i++) { - cpu_PR[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUCRISState, pregs[i]), - pregnames_v10[i]); - } -} diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index 174f50a96c..190cbff197 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -4,8 +4,8 @@ obj-$(CONFIG_SOFTMMU) += machine.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/hppa/decode.inc.c: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE) +target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) -target/hppa/translate.o: target/hppa/decode.inc.c +target/hppa/translate.o: target/hppa/decode.c.inc diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4bd22d4820..316f58562e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -334,7 +334,7 @@ static int expand_shl11(DisasContext *ctx, int val) /* Include the auto-generated decoder. */ -#include "decode.inc.c" +#include "decode.c.inc" /* We are not using a goto_tb (for whatever reason), but have updated the iaq (for whatever reason), so don't do it again on exit. */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 9fad58ea2c..899b90ae0f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31322,7 +31322,7 @@ void mips_tcg_init(void) #endif } -#include "translate_init.inc.c" +#include "translate_init.c.inc" void cpu_mips_realize_env(CPUMIPSState *env) { diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc new file mode 100644 index 0000000000..637caccd89 --- /dev/null +++ b/target/mips/translate_init.c.inc @@ -0,0 +1,1047 @@ +/* + * MIPS emulation for qemu: CPU initialisation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2007 Herve Poussineau + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* CPU / CPU family specific config register values. */ + +/* Have config1, uncached coherency */ +#define MIPS_CONFIG0 \ + ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) + +/* Have config2, no coprocessor2 attached, no MDMX support attached, + no performance counters, watch registers present, + no code compression, EJTAG present, no FPU */ +#define MIPS_CONFIG1 \ +((1U << CP0C1_M) | \ + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ + (0 << CP0C1_FP)) + +/* Have config3, no tertiary/secondary caches implemented */ +#define MIPS_CONFIG2 \ +((1U << CP0C2_M)) + +/* No config4, no DSP ASE, no large physaddr (PABITS), + no external interrupt controller, no vectored interrupts, + no 1kb pages, no SmartMIPS ASE, no trace logic */ +#define MIPS_CONFIG3 \ +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ + (0 << CP0C3_SM) | (0 << CP0C3_TL)) + +#define MIPS_CONFIG4 \ +((0 << CP0C4_M)) + +#define MIPS_CONFIG5 \ +((0 << CP0C5_M)) + +/*****************************************************************************/ +/* MIPS CPU definitions */ +const mips_def_t mips_defs[] = +{ + { + .name = "4Kc", + .CP0_PRid = 0x00018000, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4Km", + .CP0_PRid = 0x00018300, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEcR1", + .CP0_PRid = 0x00018400, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEmR1", + .CP0_PRid = 0x00018500, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEc", + .CP0_PRid = 0x00019000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEm", + .CP0_PRid = 0x00019100, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "24Kc", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x1278FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "24KEc", + .CP0_PRid = 0x00019600, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* we have a DSP, but no FPU */ + .CP0_Status_rw_bitmask = 0x1378FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "24Kf", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x3678FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "34Kf", + .CP0_PRid = 0x00019500, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | + (1 << CP0C3_DSPP), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | + (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | + (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | + (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | + (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | + (0xff << CP0TCSt_TASID), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), + .CP0_SRSConf0_rw_bitmask = 0x3fffffff, + .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), + .CP0_SRSConf1_rw_bitmask = 0x3fffffff, + .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), + .CP0_SRSConf2_rw_bitmask = 0x3fffffff, + .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), + .CP0_SRSConf3_rw_bitmask = 0x3fffffff, + .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), + .CP0_SRSConf4_rw_bitmask = 0x3fffffff, + .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | + (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "74Kf", + .CP0_PRid = 0x00019700, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (1 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "M14K", + .CP0_PRid = 0x00019b00, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | + (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1, + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "M14Kc", + /* This is the TLB-based MMU core. */ + .CP0_PRid = 0x00019c00, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* FIXME: + * Config3: VZ, CTXTC, CDMM, TL + * Config4: MMUExtDef + * Config5: MRP + * FIR(FCR0): Has2008 + * */ + .name = "P5600", + .CP0_PRid = 0x0001A800, + .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_FP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | + (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | + (0x1c << CP0C4_KScrExist), + .CP0_Config4_rw_bitmask = 0, + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) | + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFR), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3C68FF1F, + .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | + (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | + (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 32, + .PABITS = 40, + .insn_flags = CPU_MIPS32R5 | ASE_MSA, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* A generic CPU supporting MIPS32 Release 6 ISA. + FIXME: Support IEEE 754-2008 FP. + Eventually this should be replaced by a real CPU model. */ + .name = "mips32r6-generic", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | + (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1U << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (3 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), + .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3058FF1F, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = 0, + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "I7200", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | + (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | + (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | + (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | + (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | + (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | + (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | + (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + (2 << CP0C4_IE) | (1U << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), + .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | + (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3158FF1F, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = 0, + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | + ASE_MT, + .mmu_type = MMU_TYPE_R4000, + }, +#if defined(TARGET_MIPS64) + { + .name = "R4000", + .CP0_PRid = 0x00000400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + /* Note: Config1 is only used internally, the R4000 has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0x0183FFFF, + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS3, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "VR5432", + .CP0_PRid = 0x00005400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 40, + .PABITS = 32, + .insn_flags = CPU_VR54XX, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kc", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x12F8FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kf", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | + (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "20Kc", + /* We emulate a later version of the 20Kc, earlier ones had a broken + WAIT instruction. */ + .CP0_PRid = 0x000182a0, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 1, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_D) | (1 << FCR0_S) | + (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS64 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* A generic CPU providing MIPS64 Release 2 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "MIPS64R2-generic", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5KEc", + .CP0_PRid = 0x00018900, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x12F8FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5KEf", + .CP0_PRid = 0x00018900, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | + (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "I6400", + .CP0_PRid = 0x1A900, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x30D8FFFF, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, + .SEGBITS = 48, + .PABITS = 48, + .insn_flags = CPU_MIPS64R6 | ASE_MSA, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "I6500", + .CP0_PRid = 0x1B000, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 64, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x30D8FFFF, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, + .SEGBITS = 48, + .PABITS = 48, + .insn_flags = CPU_MIPS64R6 | ASE_MSA, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-2E", + .CP0_PRid = 0x6302, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | + (0x1<<5) | (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, + Loongson-2E has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x35D0FFFF, + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2E, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-2F", + .CP0_PRid = 0x6303, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | + (0x1<<5) | (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, + Loongson-2F has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2F, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-3A1000", + .CP0_PRid = 0x6305, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) | + (3 << CP0C2_SA), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x74D8FFFF, + .CP0_PageGrain = (1 << CP0PG_ELPA), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | + (0x1 << FCR0_D) | (0x1 << FCR0_S), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 42, + .PABITS = 48, + .insn_flags = CPU_LOONGSON3A, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-3A4000", + .CP0_PRid = 0x14C000, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) | + (15 << CP0C2_SA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | + (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist), + .CP0_Config4_rw_bitmask = 0, + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists), + .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), + .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) | + (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) | + (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF), + .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) | + (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) | + (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) | + (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) | + (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) | + (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) | + (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) | + (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) | + (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) | + (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) | + (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) | + (1 << CP0C6_DATAPREF), + .CP0_Config7 = 0, + .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) | + (1 << CP0C7_VFPUCGEN), + .CP0_LLAddr_rw_bitmask = 1, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x7DDBFFFF, + .CP0_PageGrain = (1 << CP0PG_ELPA), + .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | + (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | + (0x1 << FCR0_D) | (0x1 << FCR0_S), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 48, + .PABITS = 48, + .insn_flags = CPU_LOONGSON3A, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* A generic CPU providing MIPS64 DSP R2 ASE features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "mips64dspr2", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x37FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, + .mmu_type = MMU_TYPE_R4000, + }, + +#endif +}; +const int mips_defs_number = ARRAY_SIZE(mips_defs); + +void mips_cpu_list(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + qemu_printf("MIPS '%s'\n", mips_defs[i].name); + } +} + +#ifndef CONFIG_USER_ONLY +static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &no_mmu_map_address; +} + +static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &fixed_mmu_map_address; +} + +static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address = &r4k_map_address; + env->tlb->helper_tlbwi = r4k_helper_tlbwi; + env->tlb->helper_tlbwr = r4k_helper_tlbwr; + env->tlb->helper_tlbp = r4k_helper_tlbp; + env->tlb->helper_tlbr = r4k_helper_tlbr; + env->tlb->helper_tlbinv = r4k_helper_tlbinv; + env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; +} + +static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); + } +} +#endif /* CONFIG_USER_ONLY */ + +static void fpu_init (CPUMIPSState *env, const mips_def_t *def) +{ + int i; + + for (i = 0; i < MIPS_FPU_MAX; i++) + env->fpus[i].fcr0 = def->CP1_fcr0; + + memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); +} + +static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); + + /* MVPConf1 implemented, TLB sharable, no gating storage support, + programmable cache partitioning implemented, number of allocatable + and sharable TLB entries, MVP has allocatable TCs, 2 VPEs + implemented, 5 TCs implemented. */ + env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | +// TODO: actually do 2 VPEs. +// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | +// (0x04 << CP0MVPC0_PTC); + (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | + (0x00 << CP0MVPC0_PTC); +#if !defined(CONFIG_USER_ONLY) + /* Usermode has no TLB support */ + env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); +#endif + + /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, + no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ + env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | + (0x1 << CP0MVPC1_PCP1); +} + +static void msa_reset(CPUMIPSState *env) +{ +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |= 1 << CP0C5_MSAEn; + env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* MSA CSR: + - non-signaling floating point exception mode off (NX bit is 0) + - Cause, Enables, and Flags are all 0 + - round to nearest / ties to even (RM bits are 0) */ + env->active_tc.msacsr = 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c deleted file mode 100644 index 637caccd89..0000000000 --- a/target/mips/translate_init.inc.c +++ /dev/null @@ -1,1047 +0,0 @@ -/* - * MIPS emulation for qemu: CPU initialisation routines. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * Copyright (c) 2007 Herve Poussineau - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -/* CPU / CPU family specific config register values. */ - -/* Have config1, uncached coherency */ -#define MIPS_CONFIG0 \ - ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) - -/* Have config2, no coprocessor2 attached, no MDMX support attached, - no performance counters, watch registers present, - no code compression, EJTAG present, no FPU */ -#define MIPS_CONFIG1 \ -((1U << CP0C1_M) | \ - (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ - (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ - (0 << CP0C1_FP)) - -/* Have config3, no tertiary/secondary caches implemented */ -#define MIPS_CONFIG2 \ -((1U << CP0C2_M)) - -/* No config4, no DSP ASE, no large physaddr (PABITS), - no external interrupt controller, no vectored interrupts, - no 1kb pages, no SmartMIPS ASE, no trace logic */ -#define MIPS_CONFIG3 \ -((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ - (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ - (0 << CP0C3_SM) | (0 << CP0C3_TL)) - -#define MIPS_CONFIG4 \ -((0 << CP0C4_M)) - -#define MIPS_CONFIG5 \ -((0 << CP0C5_M)) - -/*****************************************************************************/ -/* MIPS CPU definitions */ -const mips_def_t mips_defs[] = -{ - { - .name = "4Kc", - .CP0_PRid = 0x00018000, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "4Km", - .CP0_PRid = 0x00018300, - /* Config1 implemented, fixed mapping MMU, - no virtual icache, uncached coherency. */ - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, - }, - { - .name = "4KEcR1", - .CP0_PRid = 0x00018400, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "4KEmR1", - .CP0_PRid = 0x00018500, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, - }, - { - .name = "4KEc", - .CP0_PRid = 0x00019000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "4KEm", - .CP0_PRid = 0x00019100, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, - }, - { - .name = "24Kc", - .CP0_PRid = 0x00019300, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x1278FF1F, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "24KEc", - .CP0_PRid = 0x00019600, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - /* we have a DSP, but no FPU */ - .CP0_Status_rw_bitmask = 0x1378FF1F, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "24Kf", - .CP0_PRid = 0x00019300, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x3678FF1F, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "34Kf", - .CP0_PRid = 0x00019500, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | - (1 << CP0C3_DSPP), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | - (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | - (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | - (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | - (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | - (0xff << CP0TCSt_TASID), - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), - .CP0_SRSConf0_rw_bitmask = 0x3fffffff, - .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | - (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), - .CP0_SRSConf1_rw_bitmask = 0x3fffffff, - .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | - (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), - .CP0_SRSConf2_rw_bitmask = 0x3fffffff, - .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | - (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), - .CP0_SRSConf3_rw_bitmask = 0x3fffffff, - .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | - (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), - .CP0_SRSConf4_rw_bitmask = 0x3fffffff, - .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | - (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "74Kf", - .CP0_PRid = 0x00019700, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | - (1 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "M14K", - .CP0_PRid = 0x00019b00, - /* Config1 implemented, fixed mapping MMU, - no virtual icache, uncached coherency. */ - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | - (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1, - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, - .mmu_type = MMU_TYPE_FMT, - }, - { - .name = "M14Kc", - /* This is the TLB-based MMU core. */ - .CP0_PRid = 0x00019c00, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | - (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | - (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, - .mmu_type = MMU_TYPE_R4000, - }, - { - /* FIXME: - * Config3: VZ, CTXTC, CDMM, TL - * Config4: MMUExtDef - * Config5: MRP - * FIR(FCR0): Has2008 - * */ - .name = "P5600", - .CP0_PRid = 0x0001A800, - .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_FP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | - (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | - (1 << CP0C3_LPA) | (1 << CP0C3_VInt), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | - (0x1c << CP0C4_KScrExist), - .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), - .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | - (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | - (1 << CP0C5_FRE) | (1 << CP0C5_UFR), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3C68FF1F, - .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | - (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), - .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | - (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 32, - .PABITS = 40, - .insn_flags = CPU_MIPS32R5 | ASE_MSA, - .mmu_type = MMU_TYPE_R4000, - }, - { - /* A generic CPU supporting MIPS32 Release 6 ISA. - FIXME: Support IEEE 754-2008 FP. - Eventually this should be replaced by a real CPU model. */ - .name = "mips32r6-generic", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | - (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1U << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | - (3 << CP0C4_IE) | (1U << CP0C4_M), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3058FF1F, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = 0, - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0x0103FFFF, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "I7200", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | - (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | - (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | - (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | - (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | - (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | - (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | - (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | - (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | - (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | - (2 << CP0C4_IE) | (1U << CP0C4_M), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3158FF1F, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = 0, - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | - ASE_MT, - .mmu_type = MMU_TYPE_R4000, - }, -#if defined(TARGET_MIPS64) - { - .name = "R4000", - .CP0_PRid = 0x00000400, - /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ - .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), - /* Note: Config1 is only used internally, the R4000 has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3678FFFF, - /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0x0183FFFF, - .SEGBITS = 40, - .PABITS = 36, - .insn_flags = CPU_MIPS3, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "VR5432", - .CP0_PRid = 0x00005400, - /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ - .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3678FFFF, - /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 40, - .PABITS = 32, - .insn_flags = CPU_VR54XX, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "5Kc", - .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x12F8FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "5Kf", - .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x36F8FFFF, - /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | - (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "20Kc", - /* We emulate a later version of the 20Kc, earlier ones had a broken - WAIT instruction. */ - .CP0_PRid = 0x000182a0, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 1, - .CP0_Status_rw_bitmask = 0x36FBFFFF, - /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | - (1 << FCR0_D) | (1 << FCR0_S) | - (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 40, - .PABITS = 36, - .insn_flags = CPU_MIPS64 | ASE_MIPS3D, - .mmu_type = MMU_TYPE_R4000, - }, - { - /* A generic CPU providing MIPS64 Release 2 features. - FIXME: Eventually this should be replaced by a real CPU model. */ - .name = "MIPS64R2-generic", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x36FBFFFF, - .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "5KEc", - .CP0_PRid = 0x00018900, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x12F8FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64R2, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "5KEf", - .CP0_PRid = 0x00018900, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | - (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | - (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x36F8FFFF, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | - (1 << FCR0_D) | (1 << FCR0_S) | - (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64R2, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "I6400", - .CP0_PRid = 0x1A900, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), - .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | - (1 << CP0C5_FRE) | (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x30D8FFFF, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), - .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0x0103FFFF, - .MSAIR = 0x03 << MSAIR_ProcID, - .SEGBITS = 48, - .PABITS = 48, - .insn_flags = CPU_MIPS64R6 | ASE_MSA, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "I6500", - .CP0_PRid = 0x1B000, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | - (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), - .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | - (1 << CP0C5_FRE) | (1 << CP0C5_UFE), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 64, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x30D8FFFF, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), - .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), - .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0x0103FFFF, - .MSAIR = 0x03 << MSAIR_ProcID, - .SEGBITS = 48, - .PABITS = 48, - .insn_flags = CPU_MIPS64R6 | ASE_MSA, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "Loongson-2E", - .CP0_PRid = 0x6302, - /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | - (0x1<<5) | (0x1<<4) | (0x1<<1), - /* Note: Config1 is only used internally, - Loongson-2E has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x35D0FFFF, - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 40, - .PABITS = 40, - .insn_flags = CPU_LOONGSON2E, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "Loongson-2F", - .CP0_PRid = 0x6303, - /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | - (0x1<<5) | (0x1<<4) | (0x1<<1), - /* Note: Config1 is only used internally, - Loongson-2F has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 40, - .PABITS = 40, - .insn_flags = CPU_LOONGSON2F, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "Loongson-3A1000", - .CP0_PRid = 0x6305, - /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) | - (3 << CP0C2_SA), - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), - .CP0_LLAddr_rw_bitmask = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x74D8FFFF, - .CP0_PageGrain = (1 << CP0PG_ELPA), - .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | - (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | - (0x1 << FCR0_D) | (0x1 << FCR0_S), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, - .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, - .mmu_type = MMU_TYPE_R4000, - }, - { - .name = "Loongson-3A4000", - .CP0_PRid = 0x14C000, - /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) | - (15 << CP0C2_SA), - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | - (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | - (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | - (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist), - .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists), - .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | - (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | - (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), - .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) | - (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) | - (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF), - .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) | - (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) | - (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) | - (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) | - (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) | - (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) | - (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) | - (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) | - (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) | - (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) | - (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) | - (1 << CP0C6_DATAPREF), - .CP0_Config7 = 0, - .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) | - (1 << CP0C7_VFPUCGEN), - .CP0_LLAddr_rw_bitmask = 1, - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x7DDBFFFF, - .CP0_PageGrain = (1 << CP0PG_ELPA), - .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | - (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | - (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | - (0x1 << FCR0_D) | (0x1 << FCR0_S), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 48, - .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, - .mmu_type = MMU_TYPE_R4000, - }, - { - /* A generic CPU providing MIPS64 DSP R2 ASE features. - FIXME: Eventually this should be replaced by a real CPU model. */ - .name = "mips64dspr2", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | - (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | - (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | - (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | - (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | - (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x37FBFFFF, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | - (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | - (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .CP1_fcr31 = 0, - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, - .mmu_type = MMU_TYPE_R4000, - }, - -#endif -}; -const int mips_defs_number = ARRAY_SIZE(mips_defs); - -void mips_cpu_list(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { - qemu_printf("MIPS '%s'\n", mips_defs[i].name); - } -} - -#ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &no_mmu_map_address; -} - -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &fixed_mmu_map_address; -} - -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); - env->tlb->map_address = &r4k_map_address; - env->tlb->helper_tlbwi = r4k_helper_tlbwi; - env->tlb->helper_tlbwr = r4k_helper_tlbwr; - env->tlb->helper_tlbp = r4k_helper_tlbp; - env->tlb->helper_tlbr = r4k_helper_tlbr; - env->tlb->helper_tlbinv = r4k_helper_tlbinv; - env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; -} - -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); - - switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); - } -} -#endif /* CONFIG_USER_ONLY */ - -static void fpu_init (CPUMIPSState *env, const mips_def_t *def) -{ - int i; - - for (i = 0; i < MIPS_FPU_MAX; i++) - env->fpus[i].fcr0 = def->CP1_fcr0; - - memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); -} - -static void mvp_init (CPUMIPSState *env, const mips_def_t *def) -{ - env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); - - /* MVPConf1 implemented, TLB sharable, no gating storage support, - programmable cache partitioning implemented, number of allocatable - and sharable TLB entries, MVP has allocatable TCs, 2 VPEs - implemented, 5 TCs implemented. */ - env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | - (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | -// TODO: actually do 2 VPEs. -// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | -// (0x04 << CP0MVPC0_PTC); - (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | - (0x00 << CP0MVPC0_PTC); -#if !defined(CONFIG_USER_ONLY) - /* Usermode has no TLB support */ - env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); -#endif - - /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, - no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ - env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | - (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | - (0x1 << CP0MVPC1_PCP1); -} - -static void msa_reset(CPUMIPSState *env) -{ -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |= 1 << CP0C5_MSAEn; - env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* MSA CSR: - - non-signaling floating point exception mode off (NX bit is 0) - - Cause, Enables, and Flags are all 0 - - round to nearest / ties to even (RM bits are 0) */ - env->active_tc.msacsr = 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index b5432f4684..423d64512e 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -6,10 +6,10 @@ obj-y += gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/openrisc/decode.inc.c: \ +target/openrisc/decode.c.inc: \ $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) -target/openrisc/translate.o: target/openrisc/decode.inc.c -target/openrisc/disas.o: target/openrisc/decode.inc.c +target/openrisc/translate.o: target/openrisc/decode.c.inc +target/openrisc/disas.o: target/openrisc/decode.c.inc diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index ce112640b9..cc91775344 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -25,7 +25,7 @@ typedef disassemble_info DisasContext; /* Include the auto-generated decoder. */ -#include "decode.inc.c" +#include "decode.c.inc" #define output(mnemonic, format, ...) \ (info->fprintf_func(info->stream, "%-9s " format, \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 52323a16df..573428b8ea 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -65,7 +65,7 @@ static inline bool is_user(DisasContext *dc) } /* Include the auto-generated decoder. */ -#include "decode.inc.c" +#include "decode.c.inc" static TCGv cpu_sr; static TCGv cpu_regs[32]; diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index d8bd3c234a..43ebf1daad 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -398,7 +398,7 @@ target_ulong helper_divso(CPUPPCState *env, target_ulong arg1, target_ulong helper_602_mfrom(target_ulong arg) { if (likely(arg < 602)) { -#include "mfrom_table.inc.c" +#include "mfrom_table.c.inc" return mfrom_ROM_table[arg]; } else { return 0; diff --git a/target/ppc/mfrom_table.c.inc b/target/ppc/mfrom_table.c.inc new file mode 100644 index 0000000000..1653b974a4 --- /dev/null +++ b/target/ppc/mfrom_table.c.inc @@ -0,0 +1,78 @@ +static const uint8_t mfrom_ROM_table[602] = { + 77, 77, 76, 76, 75, 75, 74, 74, + 73, 73, 72, 72, 71, 71, 70, 70, + 69, 69, 68, 68, 68, 67, 67, 66, + 66, 65, 65, 64, 64, 64, 63, 63, + 62, 62, 61, 61, 61, 60, 60, 59, + 59, 58, 58, 58, 57, 57, 56, 56, + 56, 55, 55, 54, 54, 54, 53, 53, + 53, 52, 52, 51, 51, 51, 50, 50, + 50, 49, 49, 49, 48, 48, 47, 47, + 47, 46, 46, 46, 45, 45, 45, 44, + 44, 44, 43, 43, 43, 42, 42, 42, + 42, 41, 41, 41, 40, 40, 40, 39, + 39, 39, 39, 38, 38, 38, 37, 37, + 37, 37, 36, 36, 36, 35, 35, 35, + 35, 34, 34, 34, 34, 33, 33, 33, + 33, 32, 32, 32, 32, 31, 31, 31, + 31, 30, 30, 30, 30, 29, 29, 29, + 29, 28, 28, 28, 28, 28, 27, 27, + 27, 27, 26, 26, 26, 26, 26, 25, + 25, 25, 25, 25, 24, 24, 24, 24, + 24, 23, 23, 23, 23, 23, 23, 22, + 22, 22, 22, 22, 21, 21, 21, 21, + 21, 21, 20, 20, 20, 20, 20, 20, + 19, 19, 19, 19, 19, 19, 19, 18, + 18, 18, 18, 18, 18, 17, 17, 17, + 17, 17, 17, 17, 16, 16, 16, 16, + 16, 16, 16, 16, 15, 15, 15, 15, + 15, 15, 15, 15, 14, 14, 14, 14, + 14, 14, 14, 14, 13, 13, 13, 13, + 13, 13, 13, 13, 13, 12, 12, 12, + 12, 12, 12, 12, 12, 12, 12, 11, + 11, 11, 11, 11, 11, 11, 11, 11, + 11, 11, 10, 10, 10, 10, 10, 10, + 10, 10, 10, 10, 10, 9, 9, 9, + 9, 9, 9, 9, 9, 9, 9, 9, + 9, 9, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, + 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, + 7, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 0, +}; diff --git a/target/ppc/mfrom_table.inc.c b/target/ppc/mfrom_table.inc.c deleted file mode 100644 index 1653b974a4..0000000000 --- a/target/ppc/mfrom_table.inc.c +++ /dev/null @@ -1,78 +0,0 @@ -static const uint8_t mfrom_ROM_table[602] = { - 77, 77, 76, 76, 75, 75, 74, 74, - 73, 73, 72, 72, 71, 71, 70, 70, - 69, 69, 68, 68, 68, 67, 67, 66, - 66, 65, 65, 64, 64, 64, 63, 63, - 62, 62, 61, 61, 61, 60, 60, 59, - 59, 58, 58, 58, 57, 57, 56, 56, - 56, 55, 55, 54, 54, 54, 53, 53, - 53, 52, 52, 51, 51, 51, 50, 50, - 50, 49, 49, 49, 48, 48, 47, 47, - 47, 46, 46, 46, 45, 45, 45, 44, - 44, 44, 43, 43, 43, 42, 42, 42, - 42, 41, 41, 41, 40, 40, 40, 39, - 39, 39, 39, 38, 38, 38, 37, 37, - 37, 37, 36, 36, 36, 35, 35, 35, - 35, 34, 34, 34, 34, 33, 33, 33, - 33, 32, 32, 32, 32, 31, 31, 31, - 31, 30, 30, 30, 30, 29, 29, 29, - 29, 28, 28, 28, 28, 28, 27, 27, - 27, 27, 26, 26, 26, 26, 26, 25, - 25, 25, 25, 25, 24, 24, 24, 24, - 24, 23, 23, 23, 23, 23, 23, 22, - 22, 22, 22, 22, 21, 21, 21, 21, - 21, 21, 20, 20, 20, 20, 20, 20, - 19, 19, 19, 19, 19, 19, 19, 18, - 18, 18, 18, 18, 18, 17, 17, 17, - 17, 17, 17, 17, 16, 16, 16, 16, - 16, 16, 16, 16, 15, 15, 15, 15, - 15, 15, 15, 15, 14, 14, 14, 14, - 14, 14, 14, 14, 13, 13, 13, 13, - 13, 13, 13, 13, 13, 12, 12, 12, - 12, 12, 12, 12, 12, 12, 12, 11, - 11, 11, 11, 11, 11, 11, 11, 11, - 11, 11, 10, 10, 10, 10, 10, 10, - 10, 10, 10, 10, 10, 9, 9, 9, - 9, 9, 9, 9, 9, 9, 9, 9, - 9, 9, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, - 7, 7, 7, 7, 7, 7, 7, 7, - 7, 7, 7, 7, 7, 7, 7, 7, - 7, 6, 6, 6, 6, 6, 6, 6, - 6, 6, 6, 6, 6, 6, 6, 6, - 6, 6, 6, 6, 5, 5, 5, 5, - 5, 5, 5, 5, 5, 5, 5, 5, - 5, 5, 5, 5, 5, 5, 5, 5, - 5, 5, 5, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 0, -}; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4ce3d664b5..04db0d865c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6900,15 +6900,15 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } -#include "translate/fp-impl.inc.c" +#include "translate/fp-impl.c.inc" -#include "translate/vmx-impl.inc.c" +#include "translate/vmx-impl.c.inc" -#include "translate/vsx-impl.inc.c" +#include "translate/vsx-impl.c.inc" -#include "translate/dfp-impl.inc.c" +#include "translate/dfp-impl.c.inc" -#include "translate/spe-impl.inc.c" +#include "translate/spe-impl.c.inc" /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) @@ -7587,19 +7587,19 @@ GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ PPC_NONE, PPC2_TM), -#include "translate/fp-ops.inc.c" +#include "translate/fp-ops.c.inc" -#include "translate/vmx-ops.inc.c" +#include "translate/vmx-ops.c.inc" -#include "translate/vsx-ops.inc.c" +#include "translate/vsx-ops.c.inc" -#include "translate/dfp-ops.inc.c" +#include "translate/dfp-ops.c.inc" -#include "translate/spe-ops.inc.c" +#include "translate/spe-ops.c.inc" }; #include "helper_regs.h" -#include "translate_init.inc.c" +#include "translate_init.c.inc" /*****************************************************************************/ /* Misc PowerPC helpers */ diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc new file mode 100644 index 0000000000..6c556dc2e1 --- /dev/null +++ b/target/ppc/translate/dfp-impl.c.inc @@ -0,0 +1,232 @@ +/*** Decimal Floating Point ***/ + +static inline TCGv_ptr gen_fprp_ptr(int reg) +{ + TCGv_ptr r = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); + return r; +} + +#define GEN_DFP_T_A_B_Rc(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr rd, ra, rb; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + rd = gen_fprp_ptr(rD(ctx->opcode)); \ + ra = gen_fprp_ptr(rA(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_env, rd, ra, rb); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ +} + +#define GEN_DFP_BF_A_B(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + ra = gen_fprp_ptr(rA(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ + cpu_env, ra, rb); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ +} + +#define GEN_DFP_BF_I_B(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 uim; \ + TCGv_ptr rb; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + uim = tcg_const_i32(UIMM5(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ + cpu_env, uim, rb); \ + tcg_temp_free_i32(uim); \ + tcg_temp_free_ptr(rb); \ +} + +#define GEN_DFP_BF_A_DCM(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr ra; \ + TCGv_i32 dcm; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + ra = gen_fprp_ptr(rA(ctx->opcode)); \ + dcm = tcg_const_i32(DCM(ctx->opcode)); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ + cpu_env, ra, dcm); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_i32(dcm); \ +} + +#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr rt, rb; \ + TCGv_i32 u32_1, u32_2; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + rt = gen_fprp_ptr(rD(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ + u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ + gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_ptr(rt); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_i32(u32_1); \ + tcg_temp_free_i32(u32_2); \ +} + +#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr rt, ra, rb; \ + TCGv_i32 i32; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + rt = gen_fprp_ptr(rD(ctx->opcode)); \ + ra = gen_fprp_ptr(rA(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + i32 = tcg_const_i32(i32fld(ctx->opcode)); \ + gen_helper_##name(cpu_env, rt, ra, rb, i32); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_ptr(rt); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_i32(i32); \ + } + +#define GEN_DFP_T_B_Rc(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr rt, rb; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + rt = gen_fprp_ptr(rD(ctx->opcode)); \ + rb = gen_fprp_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_env, rt, rb); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_ptr(rt); \ + tcg_temp_free_ptr(rb); \ + } + +#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr rt, rs; \ + TCGv_i32 i32; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_update_nip(ctx, ctx->base.pc_next - 4); \ + rt = gen_fprp_ptr(rD(ctx->opcode)); \ + rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ + i32 = tcg_const_i32(i32fld(ctx->opcode)); \ + gen_helper_##name(cpu_env, rt, rs, i32); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_ptr(rt); \ + tcg_temp_free_ptr(rs); \ + tcg_temp_free_i32(i32); \ +} + +GEN_DFP_T_A_B_Rc(dadd) +GEN_DFP_T_A_B_Rc(daddq) +GEN_DFP_T_A_B_Rc(dsub) +GEN_DFP_T_A_B_Rc(dsubq) +GEN_DFP_T_A_B_Rc(dmul) +GEN_DFP_T_A_B_Rc(dmulq) +GEN_DFP_T_A_B_Rc(ddiv) +GEN_DFP_T_A_B_Rc(ddivq) +GEN_DFP_BF_A_B(dcmpu) +GEN_DFP_BF_A_B(dcmpuq) +GEN_DFP_BF_A_B(dcmpo) +GEN_DFP_BF_A_B(dcmpoq) +GEN_DFP_BF_A_DCM(dtstdc) +GEN_DFP_BF_A_DCM(dtstdcq) +GEN_DFP_BF_A_DCM(dtstdg) +GEN_DFP_BF_A_DCM(dtstdgq) +GEN_DFP_BF_A_B(dtstex) +GEN_DFP_BF_A_B(dtstexq) +GEN_DFP_BF_A_B(dtstsf) +GEN_DFP_BF_A_B(dtstsfq) +GEN_DFP_BF_I_B(dtstsfi) +GEN_DFP_BF_I_B(dtstsfiq) +GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) +GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) +GEN_DFP_T_A_B_I32_Rc(dqua, RMC) +GEN_DFP_T_A_B_I32_Rc(dquaq, RMC) +GEN_DFP_T_A_B_I32_Rc(drrnd, RMC) +GEN_DFP_T_A_B_I32_Rc(drrndq, RMC) +GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) +GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) +GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) +GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) +GEN_DFP_T_B_Rc(dctdp) +GEN_DFP_T_B_Rc(dctqpq) +GEN_DFP_T_B_Rc(drsp) +GEN_DFP_T_B_Rc(drdpq) +GEN_DFP_T_B_Rc(dcffix) +GEN_DFP_T_B_Rc(dcffixq) +GEN_DFP_T_B_Rc(dctfix) +GEN_DFP_T_B_Rc(dctfixq) +GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) +GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) +GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) +GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) +GEN_DFP_T_B_Rc(dxex) +GEN_DFP_T_B_Rc(dxexq) +GEN_DFP_T_A_B_Rc(diex) +GEN_DFP_T_A_B_Rc(diexq) +GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM) +GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM) +GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM) +GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) + +#undef GEN_DFP_T_A_B_Rc +#undef GEN_DFP_BF_A_B +#undef GEN_DFP_BF_A_DCM +#undef GEN_DFP_T_B_U32_U32_Rc +#undef GEN_DFP_T_A_B_I32_Rc +#undef GEN_DFP_T_B_Rc +#undef GEN_DFP_T_FPR_I32_Rc diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp-impl.inc.c deleted file mode 100644 index 6c556dc2e1..0000000000 --- a/target/ppc/translate/dfp-impl.inc.c +++ /dev/null @@ -1,232 +0,0 @@ -/*** Decimal Floating Point ***/ - -static inline TCGv_ptr gen_fprp_ptr(int reg) -{ - TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); - return r; -} - -#define GEN_DFP_T_A_B_Rc(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr rd, ra, rb; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - rd = gen_fprp_ptr(rD(ctx->opcode)); \ - ra = gen_fprp_ptr(rA(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, ra, rb); \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ -} - -#define GEN_DFP_BF_A_B(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - ra = gen_fprp_ptr(rA(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ - cpu_env, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ -} - -#define GEN_DFP_BF_I_B(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 uim; \ - TCGv_ptr rb; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - uim = tcg_const_i32(UIMM5(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ - cpu_env, uim, rb); \ - tcg_temp_free_i32(uim); \ - tcg_temp_free_ptr(rb); \ -} - -#define GEN_DFP_BF_A_DCM(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr ra; \ - TCGv_i32 dcm; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - ra = gen_fprp_ptr(rA(ctx->opcode)); \ - dcm = tcg_const_i32(DCM(ctx->opcode)); \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ - cpu_env, ra, dcm); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_i32(dcm); \ -} - -#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr rt, rb; \ - TCGv_i32 u32_1, u32_2; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - rt = gen_fprp_ptr(rD(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ - u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ - gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_i32(u32_1); \ - tcg_temp_free_i32(u32_2); \ -} - -#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr rt, ra, rb; \ - TCGv_i32 i32; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - rt = gen_fprp_ptr(rD(ctx->opcode)); \ - ra = gen_fprp_ptr(rA(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - i32 = tcg_const_i32(i32fld(ctx->opcode)); \ - gen_helper_##name(cpu_env, rt, ra, rb, i32); \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_i32(i32); \ - } - -#define GEN_DFP_T_B_Rc(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr rt, rb; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - rt = gen_fprp_ptr(rD(ctx->opcode)); \ - rb = gen_fprp_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_env, rt, rb); \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rb); \ - } - -#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr rt, rs; \ - TCGv_i32 i32; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ - rt = gen_fprp_ptr(rD(ctx->opcode)); \ - rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ - i32 = tcg_const_i32(i32fld(ctx->opcode)); \ - gen_helper_##name(cpu_env, rt, rs, i32); \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rs); \ - tcg_temp_free_i32(i32); \ -} - -GEN_DFP_T_A_B_Rc(dadd) -GEN_DFP_T_A_B_Rc(daddq) -GEN_DFP_T_A_B_Rc(dsub) -GEN_DFP_T_A_B_Rc(dsubq) -GEN_DFP_T_A_B_Rc(dmul) -GEN_DFP_T_A_B_Rc(dmulq) -GEN_DFP_T_A_B_Rc(ddiv) -GEN_DFP_T_A_B_Rc(ddivq) -GEN_DFP_BF_A_B(dcmpu) -GEN_DFP_BF_A_B(dcmpuq) -GEN_DFP_BF_A_B(dcmpo) -GEN_DFP_BF_A_B(dcmpoq) -GEN_DFP_BF_A_DCM(dtstdc) -GEN_DFP_BF_A_DCM(dtstdcq) -GEN_DFP_BF_A_DCM(dtstdg) -GEN_DFP_BF_A_DCM(dtstdgq) -GEN_DFP_BF_A_B(dtstex) -GEN_DFP_BF_A_B(dtstexq) -GEN_DFP_BF_A_B(dtstsf) -GEN_DFP_BF_A_B(dtstsfq) -GEN_DFP_BF_I_B(dtstsfi) -GEN_DFP_BF_I_B(dtstsfiq) -GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) -GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) -GEN_DFP_T_A_B_I32_Rc(dqua, RMC) -GEN_DFP_T_A_B_I32_Rc(dquaq, RMC) -GEN_DFP_T_A_B_I32_Rc(drrnd, RMC) -GEN_DFP_T_A_B_I32_Rc(drrndq, RMC) -GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) -GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) -GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) -GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) -GEN_DFP_T_B_Rc(dctdp) -GEN_DFP_T_B_Rc(dctqpq) -GEN_DFP_T_B_Rc(drsp) -GEN_DFP_T_B_Rc(drdpq) -GEN_DFP_T_B_Rc(dcffix) -GEN_DFP_T_B_Rc(dcffixq) -GEN_DFP_T_B_Rc(dctfix) -GEN_DFP_T_B_Rc(dctfixq) -GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) -GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) -GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) -GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) -GEN_DFP_T_B_Rc(dxex) -GEN_DFP_T_B_Rc(dxexq) -GEN_DFP_T_A_B_Rc(diex) -GEN_DFP_T_A_B_Rc(diexq) -GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM) -GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM) -GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM) -GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) - -#undef GEN_DFP_T_A_B_Rc -#undef GEN_DFP_BF_A_B -#undef GEN_DFP_BF_A_DCM -#undef GEN_DFP_T_B_U32_U32_Rc -#undef GEN_DFP_T_A_B_I32_Rc -#undef GEN_DFP_T_B_Rc -#undef GEN_DFP_T_FPR_I32_Rc diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc new file mode 100644 index 0000000000..6ef38e5712 --- /dev/null +++ b/target/ppc/translate/dfp-ops.c.inc @@ -0,0 +1,165 @@ +#define _GEN_DFP_LONG(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) + +#define _GEN_DFP_LONG_300(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300) + +#define _GEN_DFP_LONGx2(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) + +#define _GEN_DFP_LONGx4(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) + +#define _GEN_DFP_QUAD(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) + +#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300) + +#define _GEN_DFP_QUADx2(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) + +#define _GEN_DFP_QUADx4(name, op1, op2, mask) \ +GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ +GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) + +#define GEN_DFP_T_A_B_Rc(name, op1, op2) \ +_GEN_DFP_LONG(name, op1, op2, 0x00000000) + +#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x00210800) + +#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x00200800) + +#define GEN_DFP_T_B_Rc(name, op1, op2) \ +_GEN_DFP_LONG(name, op1, op2, 0x001F0000) + +#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x003F0800) + +#define GEN_DFP_Tp_B_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x003F0000) + +#define GEN_DFP_T_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x001F0800) + +#define GEN_DFP_BF_A_B(name, op1, op2) \ +_GEN_DFP_LONG(name, op1, op2, 0x00000001) + +#define GEN_DFP_BF_A_B_300(name, op1, op2) \ +_GEN_DFP_LONG_300(name, op1, op2, 0x00400001) + +#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x00610801) + +#define GEN_DFP_BF_A_Bp(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x00600801) + +#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \ +_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001) + +#define GEN_DFP_BF_A_DCM(name, op1, op2) \ +_GEN_DFP_LONGx2(name, op1, op2, 0x00600001) + +#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \ +_GEN_DFP_QUADx2(name, op1, op2, 0x00610001) + +#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \ +_GEN_DFP_LONGx4(name, op1, op2, 0x00000000) + +#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \ +_GEN_DFP_QUADx4(name, op1, op2, 0x02010800) + +#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \ +_GEN_DFP_QUADx4(name, op1, op2, 0x02000800) + +#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \ +_GEN_DFP_LONGx4(name, op1, op2, 0x00000000) + +#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \ +_GEN_DFP_QUADx4(name, op1, op2, 0x00200800) + +#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \ +_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000) + +#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \ +_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800) + +#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \ +_GEN_DFP_LONG(name, op1, op2, 0x00070000) + +#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x00270800) + +#define GEN_DFP_S_T_B_Rc(name, op1, op2) \ +_GEN_DFP_LONG(name, op1, op2, 0x000F0000) + +#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \ +_GEN_DFP_QUAD(name, op1, op2, 0x002F0800) + +#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \ +_GEN_DFP_LONGx2(name, op1, op2, 0x00000000) + +#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \ +_GEN_DFP_QUADx2(name, op1, op2, 0x00210000) + +GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00), +GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00), +GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10), +GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10), +GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01), +GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01), +GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11), +GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11), +GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14), +GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14), +GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04), +GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04), +GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06), +GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06), +GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07), +GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07), +GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), +GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), +GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), +GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), +GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15), +GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15), +GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), +GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), +GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00), +GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00), +GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01), +GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01), +GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), +GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), +GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), +GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), +GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), +GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), +GEN_DFP_T_B_Rc(drsp, 0x02, 0x18), +GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18), +GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19), +GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19), +GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09), +GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09), +GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), +GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), +GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), +GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), +GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), +GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), +GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b), +GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b), +GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02), +GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02), +GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03), +GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03), diff --git a/target/ppc/translate/dfp-ops.inc.c b/target/ppc/translate/dfp-ops.inc.c deleted file mode 100644 index 6ef38e5712..0000000000 --- a/target/ppc/translate/dfp-ops.inc.c +++ /dev/null @@ -1,165 +0,0 @@ -#define _GEN_DFP_LONG(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) - -#define _GEN_DFP_LONG_300(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300) - -#define _GEN_DFP_LONGx2(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) - -#define _GEN_DFP_LONGx4(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) - -#define _GEN_DFP_QUAD(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) - -#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300) - -#define _GEN_DFP_QUADx2(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) - -#define _GEN_DFP_QUADx4(name, op1, op2, mask) \ -GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ -GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) - -#define GEN_DFP_T_A_B_Rc(name, op1, op2) \ -_GEN_DFP_LONG(name, op1, op2, 0x00000000) - -#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x00210800) - -#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x00200800) - -#define GEN_DFP_T_B_Rc(name, op1, op2) \ -_GEN_DFP_LONG(name, op1, op2, 0x001F0000) - -#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x003F0800) - -#define GEN_DFP_Tp_B_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x003F0000) - -#define GEN_DFP_T_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x001F0800) - -#define GEN_DFP_BF_A_B(name, op1, op2) \ -_GEN_DFP_LONG(name, op1, op2, 0x00000001) - -#define GEN_DFP_BF_A_B_300(name, op1, op2) \ -_GEN_DFP_LONG_300(name, op1, op2, 0x00400001) - -#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x00610801) - -#define GEN_DFP_BF_A_Bp(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x00600801) - -#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \ -_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001) - -#define GEN_DFP_BF_A_DCM(name, op1, op2) \ -_GEN_DFP_LONGx2(name, op1, op2, 0x00600001) - -#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \ -_GEN_DFP_QUADx2(name, op1, op2, 0x00610001) - -#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \ -_GEN_DFP_LONGx4(name, op1, op2, 0x00000000) - -#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \ -_GEN_DFP_QUADx4(name, op1, op2, 0x02010800) - -#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \ -_GEN_DFP_QUADx4(name, op1, op2, 0x02000800) - -#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \ -_GEN_DFP_LONGx4(name, op1, op2, 0x00000000) - -#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \ -_GEN_DFP_QUADx4(name, op1, op2, 0x00200800) - -#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \ -_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000) - -#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \ -_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800) - -#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \ -_GEN_DFP_LONG(name, op1, op2, 0x00070000) - -#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x00270800) - -#define GEN_DFP_S_T_B_Rc(name, op1, op2) \ -_GEN_DFP_LONG(name, op1, op2, 0x000F0000) - -#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \ -_GEN_DFP_QUAD(name, op1, op2, 0x002F0800) - -#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \ -_GEN_DFP_LONGx2(name, op1, op2, 0x00000000) - -#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \ -_GEN_DFP_QUADx2(name, op1, op2, 0x00210000) - -GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00), -GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00), -GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10), -GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10), -GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01), -GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01), -GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11), -GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11), -GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14), -GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14), -GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04), -GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04), -GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06), -GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06), -GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07), -GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07), -GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), -GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), -GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), -GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), -GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15), -GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15), -GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), -GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), -GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00), -GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00), -GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01), -GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01), -GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), -GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), -GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), -GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), -GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), -GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), -GEN_DFP_T_B_Rc(drsp, 0x02, 0x18), -GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18), -GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19), -GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19), -GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09), -GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09), -GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), -GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), -GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), -GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), -GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), -GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), -GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b), -GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b), -GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02), -GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02), -GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03), -GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03), diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc new file mode 100644 index 0000000000..9f7868ee28 --- /dev/null +++ b/target/ppc/translate/fp-impl.c.inc @@ -0,0 +1,1495 @@ +/* + * translate-fp.c + * + * Standard FPU translation + */ + +static inline void gen_reset_fpstatus(void) +{ + gen_helper_reset_fpstatus(cpu_env); +} + +static inline void gen_compute_fprf_float64(TCGv_i64 arg) +{ + gen_helper_compute_fprf_float64(cpu_env, arg); + gen_helper_float_check_status(cpu_env); +} + +#if defined(TARGET_PPC64) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], tmp, 28); + tcg_temp_free_i32(tmp); +} +#else +static void gen_set_cr1_from_fpscr(DisasContext *ctx) +{ + tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); +} +#endif + +/*** Floating-Point arithmetic ***/ +#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ +static void gen_f##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + TCGv_i64 t3; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + t3 = tcg_temp_new_i64(); \ + gen_reset_fpstatus(); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rC(ctx->opcode)); \ + get_fpr(t2, rB(ctx->opcode)); \ + gen_helper_f##op(t3, cpu_env, t0, t1, t2); \ + if (isfloat) { \ + gen_helper_frsp(t3, cpu_env, t3); \ + } \ + set_fpr(rD(ctx->opcode), t3); \ + if (set_fprf) { \ + gen_compute_fprf_float64(t3); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ + tcg_temp_free_i64(t3); \ +} + +#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ +_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ +_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); + +#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +static void gen_f##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + gen_reset_fpstatus(); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rB(ctx->opcode)); \ + gen_helper_f##op(t2, cpu_env, t0, t1); \ + if (isfloat) { \ + gen_helper_frsp(t2, cpu_env, t2); \ + } \ + set_fpr(rD(ctx->opcode), t2); \ + if (set_fprf) { \ + gen_compute_fprf_float64(t2); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ +} +#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ +_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ +_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); + +#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +static void gen_f##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + gen_reset_fpstatus(); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rC(ctx->opcode)); \ + gen_helper_f##op(t2, cpu_env, t0, t1); \ + if (isfloat) { \ + gen_helper_frsp(t2, cpu_env, t2); \ + } \ + set_fpr(rD(ctx->opcode), t2); \ + if (set_fprf) { \ + gen_compute_fprf_float64(t2); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ +} +#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ +_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ +_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); + +#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ +static void gen_f##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + gen_reset_fpstatus(); \ + get_fpr(t0, rB(ctx->opcode)); \ + gen_helper_f##name(t1, cpu_env, t0); \ + set_fpr(rD(ctx->opcode), t1); \ + if (set_fprf) { \ + gen_compute_fprf_float64(t1); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ +} + +#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ +static void gen_f##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + gen_reset_fpstatus(); \ + get_fpr(t0, rB(ctx->opcode)); \ + gen_helper_f##name(t1, cpu_env, t0); \ + set_fpr(rD(ctx->opcode), t1); \ + if (set_fprf) { \ + gen_compute_fprf_float64(t1); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ +} + +/* fadd - fadds */ +GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); +/* fdiv - fdivs */ +GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); +/* fmul - fmuls */ +GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); + +/* fre */ +GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); + +/* fres */ +GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); + +/* frsqrte */ +GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); + +/* frsqrtes */ +static void gen_frsqrtes(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_frsqrte(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* fsel */ +_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); +/* fsub - fsubs */ +GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); +/* Optional: */ + +/* fsqrt */ +static void gen_fsqrt(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static void gen_fsqrts(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/*** Floating-Point multiply-and-add ***/ +/* fmadd - fmadds */ +GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); +/* fmsub - fmsubs */ +GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); +/* fnmadd - fnmadds */ +GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); +/* fnmsub - fnmsubs */ +GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); + +/*** Floating-Point round & convert ***/ +/* fctiw */ +GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); +/* fctiwu */ +GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); +/* fctiwz */ +GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); +/* fctiwuz */ +GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); +/* frsp */ +GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); +/* fcfid */ +GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64); +/* fcfids */ +GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); +/* fcfidu */ +GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); +/* fcfidus */ +GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); +/* fctid */ +GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64); +/* fctidu */ +GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); +/* fctidz */ +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64); +/* fctidu */ +GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); + +/* frin */ +GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); +/* friz */ +GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); +/* frip */ +GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); +/* frim */ +GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); + +static void gen_ftdiv(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static void gen_ftsqrt(DisasContext *ctx) +{ + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); + tcg_temp_free_i64(t0); +} + + + +/*** Floating-Point compare ***/ + +/* fcmpo */ +static void gen_fcmpo(DisasContext *ctx) +{ + TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + crf = tcg_const_i32(crfD(ctx->opcode)); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpo(cpu_env, t0, t1, crf); + tcg_temp_free_i32(crf); + gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* fcmpu */ +static void gen_fcmpu(DisasContext *ctx) +{ + TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + crf = tcg_const_i32(crfD(ctx->opcode)); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpu(cpu_env, t0, t1, crf); + tcg_temp_free_i32(crf); + gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/*** Floating-point move ***/ +/* fabs */ +/* XXX: beware that fabs never checks for NaNs nor update FPSCR */ +static void gen_fabs(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_andi_i64(t1, t0, ~(1ULL << 63)); + set_fpr(rD(ctx->opcode), t1); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* fmr - fmr. */ +/* XXX: beware that fmr never checks for NaNs nor update FPSCR */ +static void gen_fmr(DisasContext *ctx) +{ + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + set_fpr(rD(ctx->opcode), t0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); +} + +/* fnabs */ +/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ +static void gen_fnabs(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_ori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* fneg */ +/* XXX: beware that fneg never checks for NaNs nor update FPSCR */ +static void gen_fneg(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_xori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +/* fcpsgn: PowerPC 2.05 specification */ +/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ +static void gen_fcpsgn(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 0, 63); + set_fpr(rD(ctx->opcode), t2); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +static void gen_fmrgew(DisasContext *ctx) +{ + TCGv_i64 b0; + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + b0 = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_shri_i64(b0, t0, 32); + get_fpr(t0, rA(ctx->opcode)); + tcg_gen_deposit_i64(t1, t0, b0, 0, 32); + set_fpr(rD(ctx->opcode), t1); + tcg_temp_free_i64(b0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static void gen_fmrgow(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + get_fpr(t1, rA(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 32, 32); + set_fpr(rD(ctx->opcode), t2); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +/*** Floating-Point status & ctrl register ***/ + +/* mcrfs */ +static void gen_mcrfs(DisasContext *ctx) +{ + TCGv tmp = tcg_temp_new(); + TCGv_i32 tmask; + TCGv_i64 tnew_fpscr = tcg_temp_new_i64(); + int bfa; + int nibble; + int shift; + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + bfa = crfS(ctx->opcode); + nibble = 7 - bfa; + shift = 4 * nibble; + tcg_gen_shri_tl(tmp, cpu_fpscr, shift); + tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); + tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], + 0xf); + tcg_temp_free(tmp); + tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); + /* Only the exception bits (including FX) should be cleared if read */ + tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, + ~((0xF << shift) & FP_EX_CLEAR_BITS)); + /* FEX and VX need to be updated, so don't set fpscr directly */ + tmask = tcg_const_i32(1 << nibble); + gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); + tcg_temp_free_i32(tmask); + tcg_temp_free_i64(tnew_fpscr); +} + +/* mffs */ +static void gen_mffs(DisasContext *ctx) +{ + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + set_fpr(rD(ctx->opcode), t0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } + tcg_temp_free_i64(t0); +} + +/* mffsl */ +static void gen_mffsl(DisasContext *ctx) +{ + TCGv_i64 t0; + + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return gen_mffs(ctx); + } + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + t0 = tcg_temp_new_i64(); + gen_reset_fpstatus(); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + /* Mask everything except mode, status, and enables. */ + tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN); + set_fpr(rD(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} + +/* mffsce */ +static void gen_mffsce(DisasContext *ctx) +{ + TCGv_i64 t0; + TCGv_i32 mask; + + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return gen_mffs(ctx); + } + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + + t0 = tcg_temp_new_i64(); + + gen_reset_fpstatus(); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + set_fpr(rD(ctx->opcode), t0); + + /* Clear exception enable bits in the FPSCR. */ + tcg_gen_andi_i64(t0, t0, ~FP_ENABLES); + mask = tcg_const_i32(0x0003); + gen_helper_store_fpscr(cpu_env, t0, mask); + + tcg_temp_free_i32(mask); + tcg_temp_free_i64(t0); +} + +static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i32 mask = tcg_const_i32(0x0001); + + gen_reset_fpstatus(); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN); + set_fpr(rD(ctx->opcode), t0); + + /* Mask FPSCR value to clear RN. */ + tcg_gen_andi_i64(t0, t0, ~FP_RN); + + /* Merge RN into FPSCR value. */ + tcg_gen_or_i64(t0, t0, t1); + + gen_helper_store_fpscr(cpu_env, t0, mask); + + tcg_temp_free_i32(mask); + tcg_temp_free_i64(t0); +} + +/* mffscrn */ +static void gen_mffscrn(DisasContext *ctx) +{ + TCGv_i64 t1; + + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return gen_mffs(ctx); + } + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + + t1 = tcg_temp_new_i64(); + get_fpr(t1, rB(ctx->opcode)); + /* Mask FRB to get just RN. */ + tcg_gen_andi_i64(t1, t1, FP_RN); + + gen_helper_mffscrn(ctx, t1); + + tcg_temp_free_i64(t1); +} + +/* mffscrni */ +static void gen_mffscrni(DisasContext *ctx) +{ + TCGv_i64 t1; + + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return gen_mffs(ctx); + } + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + + t1 = tcg_const_i64((uint64_t)RM(ctx->opcode)); + + gen_helper_mffscrn(ctx, t1); + + tcg_temp_free_i64(t1); +} + +/* mtfsb0 */ +static void gen_mtfsb0(DisasContext *ctx) +{ + uint8_t crb; + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + crb = 31 - crbD(ctx->opcode); + gen_reset_fpstatus(); + if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { + TCGv_i32 t0; + t0 = tcg_const_i32(crb); + gen_helper_fpscr_clrbit(cpu_env, t0); + tcg_temp_free_i32(t0); + } + if (unlikely(Rc(ctx->opcode) != 0)) { + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + } +} + +/* mtfsb1 */ +static void gen_mtfsb1(DisasContext *ctx) +{ + uint8_t crb; + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + crb = 31 - crbD(ctx->opcode); + gen_reset_fpstatus(); + /* XXX: we pretend we can only do IEEE floating-point computations */ + if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { + TCGv_i32 t0; + t0 = tcg_const_i32(crb); + gen_helper_fpscr_setbit(cpu_env, t0); + tcg_temp_free_i32(t0); + } + if (unlikely(Rc(ctx->opcode) != 0)) { + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + } + /* We can raise a deferred exception */ + gen_helper_float_check_status(cpu_env); +} + +/* mtfsf */ +static void gen_mtfsf(DisasContext *ctx) +{ + TCGv_i32 t0; + TCGv_i64 t1; + int flm, l, w; + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + flm = FPFLM(ctx->opcode); + l = FPL(ctx->opcode); + w = FPW(ctx->opcode); + if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return; + } + gen_reset_fpstatus(); + if (l) { + t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); + } else { + t0 = tcg_const_i32(flm << (w * 8)); + } + t1 = tcg_temp_new_i64(); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_store_fpscr(cpu_env, t1, t0); + tcg_temp_free_i32(t0); + if (unlikely(Rc(ctx->opcode) != 0)) { + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + } + /* We can raise a deferred exception */ + gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t1); +} + +/* mtfsfi */ +static void gen_mtfsfi(DisasContext *ctx) +{ + int bf, sh, w; + TCGv_i64 t0; + TCGv_i32 t1; + + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + w = FPW(ctx->opcode); + bf = FPBF(ctx->opcode); + if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return; + } + sh = (8 * w) + 7 - bf; + gen_reset_fpstatus(); + t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); + t1 = tcg_const_i32(1 << sh); + gen_helper_store_fpscr(cpu_env, t0, t1); + tcg_temp_free_i64(t0); + tcg_temp_free_i32(t1); + if (unlikely(Rc(ctx->opcode) != 0)) { + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + } + /* We can raise a deferred exception */ + gen_helper_float_check_status(cpu_env); +} + +/*** Floating-point load ***/ +#define GEN_LDF(name, ldop, opc, type) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_imm_index(ctx, EA, 0); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_LDUF(name, ldop, opc, type) \ +static void glue(gen_, name##u)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + if (unlikely(rA(ctx->opcode) == 0)) { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_imm_index(ctx, EA, 0); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_LDUXF(name, ldop, opc, type) \ +static void glue(gen_, name##ux)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + if (unlikely(rA(ctx->opcode) == 0)) { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_LDXF(name, ldop, opc2, opc3, type) \ +static void glue(gen_, name##x)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_reg_index(ctx, EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_LDFS(name, ldop, op, type) \ +GEN_LDF(name, ldop, op | 0x20, type); \ +GEN_LDUF(name, ldop, op | 0x21, type); \ +GEN_LDUXF(name, ldop, op | 0x01, type); \ +GEN_LDXF(name, ldop, 0x17, op | 0x00, type) + +static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + gen_helper_todouble(dest, tmp); + tcg_temp_free_i32(tmp); +} + + /* lfd lfdu lfdux lfdx */ +GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT); + /* lfs lfsu lfsux lfsx */ +GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); + +/* lfdepx (external PID lfdx) */ +static void gen_lfdepx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + CHK_SV; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, EA); + tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q)); + set_fpr(rD(ctx->opcode), t0); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* lfdp */ +static void gen_lfdp(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + gen_addr_imm_index(ctx, EA, 0); + t0 = tcg_temp_new_i64(); + /* + * We only need to swap high and low halves. gen_qemu_ld64_i64 + * does necessary 64-bit byteswap already. + */ + if (unlikely(ctx->le_mode)) { + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); + } else { + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); + } + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* lfdpx */ +static void gen_lfdpx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + t0 = tcg_temp_new_i64(); + /* + * We only need to swap high and low halves. gen_qemu_ld64_i64 + * does necessary 64-bit byteswap already. + */ + if (unlikely(ctx->le_mode)) { + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); + } else { + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); + } + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* lfiwax */ +static void gen_lfiwax(DisasContext *ctx) +{ + TCGv EA; + TCGv t0; + TCGv_i64 t1; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32s(ctx, t0, EA); + tcg_gen_ext_tl_i64(t1, t0); + set_fpr(rD(ctx->opcode), t1); + tcg_temp_free(EA); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); +} + +/* lfiwzx */ +static void gen_lfiwzx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32u_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} +/*** Floating-point store ***/ +#define GEN_STF(name, stop, opc, type) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_imm_index(ctx, EA, 0); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_STUF(name, stop, opc, type) \ +static void glue(gen_, name##u)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + if (unlikely(rA(ctx->opcode) == 0)) { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_imm_index(ctx, EA, 0); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_STUXF(name, stop, opc, type) \ +static void glue(gen_, name##ux)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + if (unlikely(rA(ctx->opcode) == 0)) { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_reg_index(ctx, EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_STXF(name, stop, opc2, opc3, type) \ +static void glue(gen_, name##x)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + gen_addr_reg_index(ctx, EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +#define GEN_STFS(name, stop, op, type) \ +GEN_STF(name, stop, op | 0x20, type); \ +GEN_STUF(name, stop, op | 0x21, type); \ +GEN_STUXF(name, stop, op | 0x01, type); \ +GEN_STXF(name, stop, 0x17, op | 0x00, type) + +static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + gen_helper_tosingle(tmp, src); + tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + tcg_temp_free_i32(tmp); +} + +/* stfd stfdu stfdux stfdx */ +GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT); +/* stfs stfsu stfsux stfsx */ +GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); + +/* stfdepx (external PID lfdx) */ +static void gen_stfdepx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + CHK_SV; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, EA); + get_fpr(t0, rD(ctx->opcode)); + tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q)); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* stfdp */ +static void gen_stfdp(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); + gen_addr_imm_index(ctx, EA, 0); + /* + * We only need to swap high and low halves. gen_qemu_st64_i64 + * does necessary 64-bit byteswap already. + */ + if (unlikely(ctx->le_mode)) { + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_gen_addi_tl(EA, EA, 8); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + } else { + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_gen_addi_tl(EA, EA, 8); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); + } + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* stfdpx */ +static void gen_stfdpx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, EA); + /* + * We only need to swap high and low halves. gen_qemu_st64_i64 + * does necessary 64-bit byteswap already. + */ + if (unlikely(ctx->le_mode)) { + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_gen_addi_tl(EA, EA, 8); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + } else { + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_gen_addi_tl(EA, EA, 8); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); + } + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +/* Optional: */ +static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_trunc_i64_tl(t0, arg1), + gen_qemu_st32(ctx, t0, arg2); + tcg_temp_free(t0); +} +/* stfiwx */ +GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); + +/* POWER2 specific instructions */ +/* Quad manipulation (load/store two floats at a time) */ + +/* lfq */ +static void gen_lfq(DisasContext *ctx) +{ + int rd = rD(ctx->opcode); + TCGv t0; + TCGv_i64 t1; + gen_set_access_type(ctx, ACCESS_FLOAT); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); + gen_addr_imm_index(ctx, t0, 0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); + gen_addr_add(ctx, t0, t0, 8); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); +} + +/* lfqu */ +static void gen_lfqu(DisasContext *ctx) +{ + int ra = rA(ctx->opcode); + int rd = rD(ctx->opcode); + TCGv t0, t1; + TCGv_i64 t2; + gen_set_access_type(ctx, ACCESS_FLOAT); + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new_i64(); + gen_addr_imm_index(ctx, t0, 0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); + gen_addr_add(ctx, t1, t0, 8); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); + if (ra != 0) { + tcg_gen_mov_tl(cpu_gpr[ra], t0); + } + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free_i64(t2); +} + +/* lfqux */ +static void gen_lfqux(DisasContext *ctx) +{ + int ra = rA(ctx->opcode); + int rd = rD(ctx->opcode); + gen_set_access_type(ctx, ACCESS_FLOAT); + TCGv t0, t1; + TCGv_i64 t2; + t2 = tcg_temp_new_i64(); + t0 = tcg_temp_new(); + gen_addr_reg_index(ctx, t0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); + t1 = tcg_temp_new(); + gen_addr_add(ctx, t1, t0, 8); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); + tcg_temp_free(t1); + if (ra != 0) { + tcg_gen_mov_tl(cpu_gpr[ra], t0); + } + tcg_temp_free(t0); + tcg_temp_free_i64(t2); +} + +/* lfqx */ +static void gen_lfqx(DisasContext *ctx) +{ + int rd = rD(ctx->opcode); + TCGv t0; + TCGv_i64 t1; + gen_set_access_type(ctx, ACCESS_FLOAT); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); + gen_addr_reg_index(ctx, t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); + gen_addr_add(ctx, t0, t0, 8); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); +} + +/* stfq */ +static void gen_stfq(DisasContext *ctx) +{ + int rd = rD(ctx->opcode); + TCGv t0; + TCGv_i64 t1; + gen_set_access_type(ctx, ACCESS_FLOAT); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); + gen_addr_imm_index(ctx, t0, 0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); + gen_addr_add(ctx, t0, t0, 8); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); +} + +/* stfqu */ +static void gen_stfqu(DisasContext *ctx) +{ + int ra = rA(ctx->opcode); + int rd = rD(ctx->opcode); + TCGv t0, t1; + TCGv_i64 t2; + gen_set_access_type(ctx, ACCESS_FLOAT); + t2 = tcg_temp_new_i64(); + t0 = tcg_temp_new(); + gen_addr_imm_index(ctx, t0, 0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); + t1 = tcg_temp_new(); + gen_addr_add(ctx, t1, t0, 8); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); + tcg_temp_free(t1); + if (ra != 0) { + tcg_gen_mov_tl(cpu_gpr[ra], t0); + } + tcg_temp_free(t0); + tcg_temp_free_i64(t2); +} + +/* stfqux */ +static void gen_stfqux(DisasContext *ctx) +{ + int ra = rA(ctx->opcode); + int rd = rD(ctx->opcode); + TCGv t0, t1; + TCGv_i64 t2; + gen_set_access_type(ctx, ACCESS_FLOAT); + t2 = tcg_temp_new_i64(); + t0 = tcg_temp_new(); + gen_addr_reg_index(ctx, t0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); + t1 = tcg_temp_new(); + gen_addr_add(ctx, t1, t0, 8); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); + tcg_temp_free(t1); + if (ra != 0) { + tcg_gen_mov_tl(cpu_gpr[ra], t0); + } + tcg_temp_free(t0); + tcg_temp_free_i64(t2); +} + +/* stfqx */ +static void gen_stfqx(DisasContext *ctx) +{ + int rd = rD(ctx->opcode); + TCGv t0; + TCGv_i64 t1; + gen_set_access_type(ctx, ACCESS_FLOAT); + t1 = tcg_temp_new_i64(); + t0 = tcg_temp_new(); + gen_addr_reg_index(ctx, t0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); + gen_addr_add(ctx, t0, t0, 8); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); +} + +#undef _GEN_FLOAT_ACB +#undef GEN_FLOAT_ACB +#undef _GEN_FLOAT_AB +#undef GEN_FLOAT_AB +#undef _GEN_FLOAT_AC +#undef GEN_FLOAT_AC +#undef GEN_FLOAT_B +#undef GEN_FLOAT_BS + +#undef GEN_LDF +#undef GEN_LDUF +#undef GEN_LDUXF +#undef GEN_LDXF +#undef GEN_LDFS + +#undef GEN_STF +#undef GEN_STUF +#undef GEN_STUXF +#undef GEN_STXF +#undef GEN_STFS diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c deleted file mode 100644 index 9f7868ee28..0000000000 --- a/target/ppc/translate/fp-impl.inc.c +++ /dev/null @@ -1,1495 +0,0 @@ -/* - * translate-fp.c - * - * Standard FPU translation - */ - -static inline void gen_reset_fpstatus(void) -{ - gen_helper_reset_fpstatus(cpu_env); -} - -static inline void gen_compute_fprf_float64(TCGv_i64 arg) -{ - gen_helper_compute_fprf_float64(cpu_env, arg); - gen_helper_float_check_status(cpu_env); -} - -#if defined(TARGET_PPC64) -static void gen_set_cr1_from_fpscr(DisasContext *ctx) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], tmp, 28); - tcg_temp_free_i32(tmp); -} -#else -static void gen_set_cr1_from_fpscr(DisasContext *ctx) -{ - tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); -} -#endif - -/*** Floating-Point arithmetic ***/ -#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ -static void gen_f##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ - TCGv_i64 t3; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - t2 = tcg_temp_new_i64(); \ - t3 = tcg_temp_new_i64(); \ - gen_reset_fpstatus(); \ - get_fpr(t0, rA(ctx->opcode)); \ - get_fpr(t1, rC(ctx->opcode)); \ - get_fpr(t2, rB(ctx->opcode)); \ - gen_helper_f##op(t3, cpu_env, t0, t1, t2); \ - if (isfloat) { \ - gen_helper_frsp(t3, cpu_env, t3); \ - } \ - set_fpr(rD(ctx->opcode), t3); \ - if (set_fprf) { \ - gen_compute_fprf_float64(t3); \ - } \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ - tcg_temp_free_i64(t3); \ -} - -#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ -_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ -_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); - -#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ -static void gen_f##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - t2 = tcg_temp_new_i64(); \ - gen_reset_fpstatus(); \ - get_fpr(t0, rA(ctx->opcode)); \ - get_fpr(t1, rB(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ - set_fpr(rD(ctx->opcode), t2); \ - if (set_fprf) { \ - gen_compute_fprf_float64(t2); \ - } \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ -} -#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); - -#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ -static void gen_f##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - t2 = tcg_temp_new_i64(); \ - gen_reset_fpstatus(); \ - get_fpr(t0, rA(ctx->opcode)); \ - get_fpr(t1, rC(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ - set_fpr(rD(ctx->opcode), t2); \ - if (set_fprf) { \ - gen_compute_fprf_float64(t2); \ - } \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ -} -#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); - -#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ -static void gen_f##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - gen_reset_fpstatus(); \ - get_fpr(t0, rB(ctx->opcode)); \ - gen_helper_f##name(t1, cpu_env, t0); \ - set_fpr(rD(ctx->opcode), t1); \ - if (set_fprf) { \ - gen_compute_fprf_float64(t1); \ - } \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ -} - -#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ -static void gen_f##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - gen_reset_fpstatus(); \ - get_fpr(t0, rB(ctx->opcode)); \ - gen_helper_f##name(t1, cpu_env, t0); \ - set_fpr(rD(ctx->opcode), t1); \ - if (set_fprf) { \ - gen_compute_fprf_float64(t1); \ - } \ - if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr1_from_fpscr(ctx); \ - } \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ -} - -/* fadd - fadds */ -GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); -/* fdiv - fdivs */ -GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); -/* fmul - fmuls */ -GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); - -/* fre */ -GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); - -/* fres */ -GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); - -/* frsqrte */ -GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); - -/* frsqrtes */ -static void gen_frsqrtes(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - get_fpr(t0, rB(ctx->opcode)); - gen_helper_frsqrte(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); - set_fpr(rD(ctx->opcode), t1); - gen_compute_fprf_float64(t1); - if (unlikely(Rc(ctx->opcode) != 0)) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* fsel */ -_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); -/* fsub - fsubs */ -GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); -/* Optional: */ - -/* fsqrt */ -static void gen_fsqrt(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - get_fpr(t0, rB(ctx->opcode)); - gen_helper_fsqrt(t1, cpu_env, t0); - set_fpr(rD(ctx->opcode), t1); - gen_compute_fprf_float64(t1); - if (unlikely(Rc(ctx->opcode) != 0)) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static void gen_fsqrts(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - get_fpr(t0, rB(ctx->opcode)); - gen_helper_fsqrt(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); - set_fpr(rD(ctx->opcode), t1); - gen_compute_fprf_float64(t1); - if (unlikely(Rc(ctx->opcode) != 0)) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/*** Floating-Point multiply-and-add ***/ -/* fmadd - fmadds */ -GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); -/* fmsub - fmsubs */ -GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); -/* fnmadd - fnmadds */ -GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); -/* fnmsub - fnmsubs */ -GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); - -/*** Floating-Point round & convert ***/ -/* fctiw */ -GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); -/* fctiwu */ -GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); -/* fctiwz */ -GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); -/* fctiwuz */ -GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); -/* frsp */ -GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); -/* fcfid */ -GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64); -/* fcfids */ -GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); -/* fcfidu */ -GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); -/* fcfidus */ -GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); -/* fctid */ -GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64); -/* fctidu */ -GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); -/* fctidz */ -GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64); -/* fctidu */ -GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); - -/* frin */ -GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); -/* friz */ -GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); -/* frip */ -GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); -/* frim */ -GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); - -static void gen_ftdiv(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - get_fpr(t0, rA(ctx->opcode)); - get_fpr(t1, rB(ctx->opcode)); - gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static void gen_ftsqrt(DisasContext *ctx) -{ - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); - tcg_temp_free_i64(t0); -} - - - -/*** Floating-Point compare ***/ - -/* fcmpo */ -static void gen_fcmpo(DisasContext *ctx) -{ - TCGv_i32 crf; - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - crf = tcg_const_i32(crfD(ctx->opcode)); - get_fpr(t0, rA(ctx->opcode)); - get_fpr(t1, rB(ctx->opcode)); - gen_helper_fcmpo(cpu_env, t0, t1, crf); - tcg_temp_free_i32(crf); - gen_helper_float_check_status(cpu_env); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* fcmpu */ -static void gen_fcmpu(DisasContext *ctx) -{ - TCGv_i32 crf; - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - crf = tcg_const_i32(crfD(ctx->opcode)); - get_fpr(t0, rA(ctx->opcode)); - get_fpr(t1, rB(ctx->opcode)); - gen_helper_fcmpu(cpu_env, t0, t1, crf); - tcg_temp_free_i32(crf); - gen_helper_float_check_status(cpu_env); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/*** Floating-point move ***/ -/* fabs */ -/* XXX: beware that fabs never checks for NaNs nor update FPSCR */ -static void gen_fabs(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - tcg_gen_andi_i64(t1, t0, ~(1ULL << 63)); - set_fpr(rD(ctx->opcode), t1); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* fmr - fmr. */ -/* XXX: beware that fmr never checks for NaNs nor update FPSCR */ -static void gen_fmr(DisasContext *ctx) -{ - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - set_fpr(rD(ctx->opcode), t0); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); -} - -/* fnabs */ -/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ -static void gen_fnabs(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - tcg_gen_ori_i64(t1, t0, 1ULL << 63); - set_fpr(rD(ctx->opcode), t1); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* fneg */ -/* XXX: beware that fneg never checks for NaNs nor update FPSCR */ -static void gen_fneg(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - tcg_gen_xori_i64(t1, t0, 1ULL << 63); - set_fpr(rD(ctx->opcode), t1); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* fcpsgn: PowerPC 2.05 specification */ -/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ -static void gen_fcpsgn(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - TCGv_i64 t2; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - t2 = tcg_temp_new_i64(); - get_fpr(t0, rA(ctx->opcode)); - get_fpr(t1, rB(ctx->opcode)); - tcg_gen_deposit_i64(t2, t0, t1, 0, 63); - set_fpr(rD(ctx->opcode), t2); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); -} - -static void gen_fmrgew(DisasContext *ctx) -{ - TCGv_i64 b0; - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - b0 = tcg_temp_new_i64(); - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - tcg_gen_shri_i64(b0, t0, 32); - get_fpr(t0, rA(ctx->opcode)); - tcg_gen_deposit_i64(t1, t0, b0, 0, 32); - set_fpr(rD(ctx->opcode), t1); - tcg_temp_free_i64(b0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static void gen_fmrgow(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - TCGv_i64 t2; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - t2 = tcg_temp_new_i64(); - get_fpr(t0, rB(ctx->opcode)); - get_fpr(t1, rA(ctx->opcode)); - tcg_gen_deposit_i64(t2, t0, t1, 32, 32); - set_fpr(rD(ctx->opcode), t2); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); -} - -/*** Floating-Point status & ctrl register ***/ - -/* mcrfs */ -static void gen_mcrfs(DisasContext *ctx) -{ - TCGv tmp = tcg_temp_new(); - TCGv_i32 tmask; - TCGv_i64 tnew_fpscr = tcg_temp_new_i64(); - int bfa; - int nibble; - int shift; - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - bfa = crfS(ctx->opcode); - nibble = 7 - bfa; - shift = 4 * nibble; - tcg_gen_shri_tl(tmp, cpu_fpscr, shift); - tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); - tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], - 0xf); - tcg_temp_free(tmp); - tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); - /* Only the exception bits (including FX) should be cleared if read */ - tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, - ~((0xF << shift) & FP_EX_CLEAR_BITS)); - /* FEX and VX need to be updated, so don't set fpscr directly */ - tmask = tcg_const_i32(1 << nibble); - gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); - tcg_temp_free_i32(tmask); - tcg_temp_free_i64(tnew_fpscr); -} - -/* mffs */ -static void gen_mffs(DisasContext *ctx) -{ - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(t0, cpu_fpscr); - set_fpr(rD(ctx->opcode), t0); - if (unlikely(Rc(ctx->opcode))) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); -} - -/* mffsl */ -static void gen_mffsl(DisasContext *ctx) -{ - TCGv_i64 t0; - - if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { - return gen_mffs(ctx); - } - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(t0, cpu_fpscr); - /* Mask everything except mode, status, and enables. */ - tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN); - set_fpr(rD(ctx->opcode), t0); - tcg_temp_free_i64(t0); -} - -/* mffsce */ -static void gen_mffsce(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i32 mask; - - if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { - return gen_mffs(ctx); - } - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - - t0 = tcg_temp_new_i64(); - - gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(t0, cpu_fpscr); - set_fpr(rD(ctx->opcode), t0); - - /* Clear exception enable bits in the FPSCR. */ - tcg_gen_andi_i64(t0, t0, ~FP_ENABLES); - mask = tcg_const_i32(0x0003); - gen_helper_store_fpscr(cpu_env, t0, mask); - - tcg_temp_free_i32(mask); - tcg_temp_free_i64(t0); -} - -static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i32 mask = tcg_const_i32(0x0001); - - gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(t0, cpu_fpscr); - tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN); - set_fpr(rD(ctx->opcode), t0); - - /* Mask FPSCR value to clear RN. */ - tcg_gen_andi_i64(t0, t0, ~FP_RN); - - /* Merge RN into FPSCR value. */ - tcg_gen_or_i64(t0, t0, t1); - - gen_helper_store_fpscr(cpu_env, t0, mask); - - tcg_temp_free_i32(mask); - tcg_temp_free_i64(t0); -} - -/* mffscrn */ -static void gen_mffscrn(DisasContext *ctx) -{ - TCGv_i64 t1; - - if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { - return gen_mffs(ctx); - } - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - - t1 = tcg_temp_new_i64(); - get_fpr(t1, rB(ctx->opcode)); - /* Mask FRB to get just RN. */ - tcg_gen_andi_i64(t1, t1, FP_RN); - - gen_helper_mffscrn(ctx, t1); - - tcg_temp_free_i64(t1); -} - -/* mffscrni */ -static void gen_mffscrni(DisasContext *ctx) -{ - TCGv_i64 t1; - - if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { - return gen_mffs(ctx); - } - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - - t1 = tcg_const_i64((uint64_t)RM(ctx->opcode)); - - gen_helper_mffscrn(ctx, t1); - - tcg_temp_free_i64(t1); -} - -/* mtfsb0 */ -static void gen_mtfsb0(DisasContext *ctx) -{ - uint8_t crb; - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - crb = 31 - crbD(ctx->opcode); - gen_reset_fpstatus(); - if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { - TCGv_i32 t0; - t0 = tcg_const_i32(crb); - gen_helper_fpscr_clrbit(cpu_env, t0); - tcg_temp_free_i32(t0); - } - if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); - } -} - -/* mtfsb1 */ -static void gen_mtfsb1(DisasContext *ctx) -{ - uint8_t crb; - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - crb = 31 - crbD(ctx->opcode); - gen_reset_fpstatus(); - /* XXX: we pretend we can only do IEEE floating-point computations */ - if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { - TCGv_i32 t0; - t0 = tcg_const_i32(crb); - gen_helper_fpscr_setbit(cpu_env, t0); - tcg_temp_free_i32(t0); - } - if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); - } - /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); -} - -/* mtfsf */ -static void gen_mtfsf(DisasContext *ctx) -{ - TCGv_i32 t0; - TCGv_i64 t1; - int flm, l, w; - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - flm = FPFLM(ctx->opcode); - l = FPL(ctx->opcode); - w = FPW(ctx->opcode); - if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - gen_reset_fpstatus(); - if (l) { - t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); - } else { - t0 = tcg_const_i32(flm << (w * 8)); - } - t1 = tcg_temp_new_i64(); - get_fpr(t1, rB(ctx->opcode)); - gen_helper_store_fpscr(cpu_env, t1, t0); - tcg_temp_free_i32(t0); - if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); - } - /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); - tcg_temp_free_i64(t1); -} - -/* mtfsfi */ -static void gen_mtfsfi(DisasContext *ctx) -{ - int bf, sh, w; - TCGv_i64 t0; - TCGv_i32 t1; - - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - w = FPW(ctx->opcode); - bf = FPBF(ctx->opcode); - if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - sh = (8 * w) + 7 - bf; - gen_reset_fpstatus(); - t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); - t1 = tcg_const_i32(1 << sh); - gen_helper_store_fpscr(cpu_env, t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i32(t1); - if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); - } - /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); -} - -/*** Floating-point load ***/ -#define GEN_LDF(name, ldop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, t0, EA); \ - set_fpr(rD(ctx->opcode), t0); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_LDUF(name, ldop, opc, type) \ -static void glue(gen_, name##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, t0, EA); \ - set_fpr(rD(ctx->opcode), t0); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_LDUXF(name, ldop, opc, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, t0, EA); \ - set_fpr(rD(ctx->opcode), t0); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_LDXF(name, ldop, opc2, opc3, type) \ -static void glue(gen_, name##x)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, t0, EA); \ - set_fpr(rD(ctx->opcode), t0); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_LDFS(name, ldop, op, type) \ -GEN_LDF(name, ldop, op | 0x20, type); \ -GEN_LDUF(name, ldop, op | 0x21, type); \ -GEN_LDUXF(name, ldop, op | 0x01, type); \ -GEN_LDXF(name, ldop, 0x17, op | 0x00, type) - -static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); - gen_helper_todouble(dest, tmp); - tcg_temp_free_i32(tmp); -} - - /* lfd lfdu lfdux lfdx */ -GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT); - /* lfs lfsu lfsux lfsx */ -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); - -/* lfdepx (external PID lfdx) */ -static void gen_lfdepx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - CHK_SV; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q)); - set_fpr(rD(ctx->opcode), t0); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* lfdp */ -static void gen_lfdp(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - gen_addr_imm_index(ctx, EA, 0); - t0 = tcg_temp_new_i64(); - /* - * We only need to swap high and low halves. gen_qemu_ld64_i64 - * does necessary 64-bit byteswap already. - */ - if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode) + 1, t0); - tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode), t0); - } else { - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode), t0); - tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode) + 1, t0); - } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* lfdpx */ -static void gen_lfdpx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - t0 = tcg_temp_new_i64(); - /* - * We only need to swap high and low halves. gen_qemu_ld64_i64 - * does necessary 64-bit byteswap already. - */ - if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode) + 1, t0); - tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode), t0); - } else { - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode), t0); - tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode) + 1, t0); - } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* lfiwax */ -static void gen_lfiwax(DisasContext *ctx) -{ - TCGv EA; - TCGv t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new(); - t1 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, EA); - gen_qemu_ld32s(ctx, t0, EA); - tcg_gen_ext_tl_i64(t1, t0); - set_fpr(rD(ctx->opcode), t1); - tcg_temp_free(EA); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); -} - -/* lfiwzx */ -static void gen_lfiwzx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, EA); - gen_qemu_ld32u_i64(ctx, t0, EA); - set_fpr(rD(ctx->opcode), t0); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} -/*** Floating-point store ***/ -#define GEN_STF(name, stop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_imm_index(ctx, EA, 0); \ - get_fpr(t0, rS(ctx->opcode)); \ - gen_qemu_##stop(ctx, t0, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_STUF(name, stop, opc, type) \ -static void glue(gen_, name##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_imm_index(ctx, EA, 0); \ - get_fpr(t0, rS(ctx->opcode)); \ - gen_qemu_##stop(ctx, t0, EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_STUXF(name, stop, opc, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_reg_index(ctx, EA); \ - get_fpr(t0, rS(ctx->opcode)); \ - gen_qemu_##stop(ctx, t0, EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_STXF(name, stop, opc2, opc3, type) \ -static void glue(gen_, name##x)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_FLOAT); \ - EA = tcg_temp_new(); \ - t0 = tcg_temp_new_i64(); \ - gen_addr_reg_index(ctx, EA); \ - get_fpr(t0, rS(ctx->opcode)); \ - gen_qemu_##stop(ctx, t0, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -#define GEN_STFS(name, stop, op, type) \ -GEN_STF(name, stop, op | 0x20, type); \ -GEN_STUF(name, stop, op | 0x21, type); \ -GEN_STUXF(name, stop, op | 0x01, type); \ -GEN_STXF(name, stop, 0x17, op | 0x00, type) - -static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - gen_helper_tosingle(tmp, src); - tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); - tcg_temp_free_i32(tmp); -} - -/* stfd stfdu stfdux stfdx */ -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT); -/* stfs stfsu stfsux stfsx */ -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); - -/* stfdepx (external PID lfdx) */ -static void gen_stfdepx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - CHK_SV; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, EA); - get_fpr(t0, rD(ctx->opcode)); - tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q)); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* stfdp */ -static void gen_stfdp(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - gen_addr_imm_index(ctx, EA, 0); - /* - * We only need to swap high and low halves. gen_qemu_st64_i64 - * does necessary 64-bit byteswap already. - */ - if (unlikely(ctx->le_mode)) { - get_fpr(t0, rD(ctx->opcode) + 1); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_gen_addi_tl(EA, EA, 8); - get_fpr(t0, rD(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - } else { - get_fpr(t0, rD(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_gen_addi_tl(EA, EA, 8); - get_fpr(t0, rD(ctx->opcode) + 1); - gen_qemu_st64_i64(ctx, t0, EA); - } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* stfdpx */ -static void gen_stfdpx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - gen_set_access_type(ctx, ACCESS_FLOAT); - EA = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, EA); - /* - * We only need to swap high and low halves. gen_qemu_st64_i64 - * does necessary 64-bit byteswap already. - */ - if (unlikely(ctx->le_mode)) { - get_fpr(t0, rD(ctx->opcode) + 1); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_gen_addi_tl(EA, EA, 8); - get_fpr(t0, rD(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - } else { - get_fpr(t0, rD(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_gen_addi_tl(EA, EA, 8); - get_fpr(t0, rD(ctx->opcode) + 1); - gen_qemu_st64_i64(ctx, t0, EA); - } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -/* Optional: */ -static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_trunc_i64_tl(t0, arg1), - gen_qemu_st32(ctx, t0, arg2); - tcg_temp_free(t0); -} -/* stfiwx */ -GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); - -/* POWER2 specific instructions */ -/* Quad manipulation (load/store two floats at a time) */ - -/* lfq */ -static void gen_lfq(DisasContext *ctx) -{ - int rd = rD(ctx->opcode); - TCGv t0; - TCGv_i64 t1; - gen_set_access_type(ctx, ACCESS_FLOAT); - t0 = tcg_temp_new(); - t1 = tcg_temp_new_i64(); - gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, t1, t0); - set_fpr(rd, t1); - gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, t1, t0); - set_fpr((rd + 1) % 32, t1); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); -} - -/* lfqu */ -static void gen_lfqu(DisasContext *ctx) -{ - int ra = rA(ctx->opcode); - int rd = rD(ctx->opcode); - TCGv t0, t1; - TCGv_i64 t2; - gen_set_access_type(ctx, ACCESS_FLOAT); - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); - t2 = tcg_temp_new_i64(); - gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, t2, t0); - set_fpr(rd, t2); - gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, t2, t1); - set_fpr((rd + 1) % 32, t2); - if (ra != 0) { - tcg_gen_mov_tl(cpu_gpr[ra], t0); - } - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free_i64(t2); -} - -/* lfqux */ -static void gen_lfqux(DisasContext *ctx) -{ - int ra = rA(ctx->opcode); - int rd = rD(ctx->opcode); - gen_set_access_type(ctx, ACCESS_FLOAT); - TCGv t0, t1; - TCGv_i64 t2; - t2 = tcg_temp_new_i64(); - t0 = tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, t2, t0); - set_fpr(rd, t2); - t1 = tcg_temp_new(); - gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, t2, t1); - set_fpr((rd + 1) % 32, t2); - tcg_temp_free(t1); - if (ra != 0) { - tcg_gen_mov_tl(cpu_gpr[ra], t0); - } - tcg_temp_free(t0); - tcg_temp_free_i64(t2); -} - -/* lfqx */ -static void gen_lfqx(DisasContext *ctx) -{ - int rd = rD(ctx->opcode); - TCGv t0; - TCGv_i64 t1; - gen_set_access_type(ctx, ACCESS_FLOAT); - t0 = tcg_temp_new(); - t1 = tcg_temp_new_i64(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, t1, t0); - set_fpr(rd, t1); - gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, t1, t0); - set_fpr((rd + 1) % 32, t1); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); -} - -/* stfq */ -static void gen_stfq(DisasContext *ctx) -{ - int rd = rD(ctx->opcode); - TCGv t0; - TCGv_i64 t1; - gen_set_access_type(ctx, ACCESS_FLOAT); - t0 = tcg_temp_new(); - t1 = tcg_temp_new_i64(); - gen_addr_imm_index(ctx, t0, 0); - get_fpr(t1, rd); - gen_qemu_st64_i64(ctx, t1, t0); - gen_addr_add(ctx, t0, t0, 8); - get_fpr(t1, (rd + 1) % 32); - gen_qemu_st64_i64(ctx, t1, t0); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); -} - -/* stfqu */ -static void gen_stfqu(DisasContext *ctx) -{ - int ra = rA(ctx->opcode); - int rd = rD(ctx->opcode); - TCGv t0, t1; - TCGv_i64 t2; - gen_set_access_type(ctx, ACCESS_FLOAT); - t2 = tcg_temp_new_i64(); - t0 = tcg_temp_new(); - gen_addr_imm_index(ctx, t0, 0); - get_fpr(t2, rd); - gen_qemu_st64_i64(ctx, t2, t0); - t1 = tcg_temp_new(); - gen_addr_add(ctx, t1, t0, 8); - get_fpr(t2, (rd + 1) % 32); - gen_qemu_st64_i64(ctx, t2, t1); - tcg_temp_free(t1); - if (ra != 0) { - tcg_gen_mov_tl(cpu_gpr[ra], t0); - } - tcg_temp_free(t0); - tcg_temp_free_i64(t2); -} - -/* stfqux */ -static void gen_stfqux(DisasContext *ctx) -{ - int ra = rA(ctx->opcode); - int rd = rD(ctx->opcode); - TCGv t0, t1; - TCGv_i64 t2; - gen_set_access_type(ctx, ACCESS_FLOAT); - t2 = tcg_temp_new_i64(); - t0 = tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - get_fpr(t2, rd); - gen_qemu_st64_i64(ctx, t2, t0); - t1 = tcg_temp_new(); - gen_addr_add(ctx, t1, t0, 8); - get_fpr(t2, (rd + 1) % 32); - gen_qemu_st64_i64(ctx, t2, t1); - tcg_temp_free(t1); - if (ra != 0) { - tcg_gen_mov_tl(cpu_gpr[ra], t0); - } - tcg_temp_free(t0); - tcg_temp_free_i64(t2); -} - -/* stfqx */ -static void gen_stfqx(DisasContext *ctx) -{ - int rd = rD(ctx->opcode); - TCGv t0; - TCGv_i64 t1; - gen_set_access_type(ctx, ACCESS_FLOAT); - t1 = tcg_temp_new_i64(); - t0 = tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - get_fpr(t1, rd); - gen_qemu_st64_i64(ctx, t1, t0); - gen_addr_add(ctx, t0, t0, 8); - get_fpr(t1, (rd + 1) % 32); - gen_qemu_st64_i64(ctx, t1, t0); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); -} - -#undef _GEN_FLOAT_ACB -#undef GEN_FLOAT_ACB -#undef _GEN_FLOAT_AB -#undef GEN_FLOAT_AB -#undef _GEN_FLOAT_AC -#undef GEN_FLOAT_AC -#undef GEN_FLOAT_B -#undef GEN_FLOAT_BS - -#undef GEN_LDF -#undef GEN_LDUF -#undef GEN_LDUXF -#undef GEN_LDXF -#undef GEN_LDFS - -#undef GEN_STF -#undef GEN_STUF -#undef GEN_STUXF -#undef GEN_STXF -#undef GEN_STFS diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc new file mode 100644 index 0000000000..88fab65628 --- /dev/null +++ b/target/ppc/translate/fp-ops.c.inc @@ -0,0 +1,119 @@ +#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ +GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) +#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ +_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ +_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) +#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) +#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ +_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ +_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) +#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) +#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ +_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ +_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) +#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ +GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) +#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ +GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) + +GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), +GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), +GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), +GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), +GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), +GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), +_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), +GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), +GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), +GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), +GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), +GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), +GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), +GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), +GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), +GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), +GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), +GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), +GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), +GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), +GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), +GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), +GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), +GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), + +#define GEN_LDF(name, ldop, opc, type) \ +GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_LDUF(name, ldop, opc, type) \ +GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_LDUXF(name, ldop, opc, type) \ +GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), +#define GEN_LDXF(name, ldop, opc2, opc3, type) \ +GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), +#define GEN_LDFS(name, ldop, op, type) \ +GEN_LDF(name, ldop, op | 0x20, type) \ +GEN_LDUF(name, ldop, op | 0x21, type) \ +GEN_LDUXF(name, ldop, op | 0x01, type) \ +GEN_LDXF(name, ldop, 0x17, op | 0x00, type) + +GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) +GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) +GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206), +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), +GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206), +GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), + +#define GEN_STF(name, stop, opc, type) \ +GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_STUF(name, stop, opc, type) \ +GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_STUXF(name, stop, opc, type) \ +GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), +#define GEN_STXF(name, stop, opc2, opc3, type) \ +GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), +#define GEN_STFS(name, stop, op, type) \ +GEN_STF(name, stop, op | 0x20, type) \ +GEN_STUF(name, stop, op | 0x21, type) \ +GEN_STUXF(name, stop, op | 0x01, type) \ +GEN_STXF(name, stop, 0x17, op | 0x00, type) + +GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT) +GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) +GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) +GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206), +GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), + +GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), +GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), +GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), +GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), +GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), +GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), +GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), +GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), +GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), +GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), +GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), +GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), +GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE), +GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT, + PPC2_ISA300), +GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT, + PPC2_ISA300), +GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT, + PPC_NONE), +GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT, + PPC_NONE), +GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), +GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), +GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), +GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-ops.inc.c deleted file mode 100644 index 88fab65628..0000000000 --- a/target/ppc/translate/fp-ops.inc.c +++ /dev/null @@ -1,119 +0,0 @@ -#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ -GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) -#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ -_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ -_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) -#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ -GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) -#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ -_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) -#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ -GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) -#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ -_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) -#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ -GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) -#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ -GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) - -GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), -GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), -GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), -GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), -GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), -GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), -_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), -GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), -GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), -GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), -GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), -GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), -GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), -GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), -GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), -GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), -GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), -GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), -GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), -GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64), -GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), -GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), -GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), -GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), - -#define GEN_LDF(name, ldop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDUF(name, ldop, opc, type) \ -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDUXF(name, ldop, opc, type) \ -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), -#define GEN_LDXF(name, ldop, opc2, opc3, type) \ -GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), -#define GEN_LDFS(name, ldop, op, type) \ -GEN_LDF(name, ldop, op | 0x20, type) \ -GEN_LDUF(name, ldop, op | 0x21, type) \ -GEN_LDUXF(name, ldop, op | 0x01, type) \ -GEN_LDXF(name, ldop, 0x17, op | 0x00, type) - -GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) -GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) -GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206), -GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), -GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206), -GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), - -#define GEN_STF(name, stop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STUF(name, stop, opc, type) \ -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STUXF(name, stop, opc, type) \ -GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), -#define GEN_STXF(name, stop, opc2, opc3, type) \ -GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), -#define GEN_STFS(name, stop, op, type) \ -GEN_STF(name, stop, op | 0x20, type) \ -GEN_STUF(name, stop, op | 0x21, type) \ -GEN_STUXF(name, stop, op | 0x01, type) \ -GEN_STXF(name, stop, 0x17, op | 0x00, type) - -GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT) -GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) -GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) -GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206), -GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), - -GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), -GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), -GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), -GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), -GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), -GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), -GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), -GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), -GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), -GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), -GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), -GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), -GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE), -GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT, - PPC2_ISA300), -GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT, - PPC2_ISA300), -GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT, - PPC_NONE), -GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT, - PPC_NONE), -GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), -GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), -GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), -GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), diff --git a/target/ppc/translate/spe-impl.c.inc b/target/ppc/translate/spe-impl.c.inc new file mode 100644 index 0000000000..36b4d5654d --- /dev/null +++ b/target/ppc/translate/spe-impl.c.inc @@ -0,0 +1,1221 @@ +/* + * translate-spe.c + * + * Freescale SPE extension translation + */ + +/*** SPE extension ***/ +/* Register moves */ + +static inline void gen_evmra(DisasContext *ctx) +{ + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + + TCGv_i64 tmp = tcg_temp_new_i64(); + + /* tmp := rA_lo + rA_hi << 32 */ + tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], + cpu_gprh[rA(ctx->opcode)]); + + /* spe_acc := tmp */ + tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_temp_free_i64(tmp); + + /* rD := rA */ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); +} + +static inline void gen_load_gpr64(TCGv_i64 t, int reg) +{ + tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); +} + +static inline void gen_store_gpr64(int reg, TCGv_i64 t) +{ + tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); +} + +#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if (Rc(ctx->opcode)) \ + gen_##name1(ctx); \ + else \ + gen_##name0(ctx); \ +} + +/* Handler for undefined SPE opcodes */ +static inline void gen_speundef(DisasContext *ctx) +{ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); +} + +/* SPE logic */ +#define GEN_SPEOP_LOGIC2(name, tcg_op) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ + cpu_gpr[rB(ctx->opcode)]); \ + tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ + cpu_gprh[rB(ctx->opcode)]); \ +} + +GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); +GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); +GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); +GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); +GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); +GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); +GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); +GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); + +/* SPE logic immediate */ +#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ + tcg_opi(t0, t0, rB(ctx->opcode)); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ + tcg_opi(t0, t0, rB(ctx->opcode)); \ + tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ + \ + tcg_temp_free_i32(t0); \ +} +GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); +GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); +GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); +GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); + +/* SPE arithmetic */ +#define GEN_SPEOP_ARITH1(name, tcg_op) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ + tcg_op(t0, t0); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ + tcg_op(t0, t0); \ + tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ + \ + tcg_temp_free_i32(t0); \ +} + +GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); +GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); +GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); +GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); +static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) +{ + tcg_gen_addi_i32(ret, arg1, 0x8000); + tcg_gen_ext16u_i32(ret, ret); +} +GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); +GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); +GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); + +#define GEN_SPEOP_ARITH2(name, tcg_op) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0, t1; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + t1 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ + tcg_op(t0, t0, t1); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ + tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ + tcg_op(t0, t0, t1); \ + tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ + \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i32(t1); \ +} + +static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + TCGv_i32 t0 = tcg_temp_local_new_i32(); + + /* No error here: 6 bits are used */ + tcg_gen_andi_i32(t0, arg2, 0x3F); + tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); + tcg_gen_shr_i32(ret, arg1, t0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i32(ret, 0); + gen_set_label(l2); + tcg_temp_free_i32(t0); +} +GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); +static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + TCGv_i32 t0 = tcg_temp_local_new_i32(); + + /* No error here: 6 bits are used */ + tcg_gen_andi_i32(t0, arg2, 0x3F); + tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); + tcg_gen_sar_i32(ret, arg1, t0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i32(ret, 0); + gen_set_label(l2); + tcg_temp_free_i32(t0); +} +GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); +static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + TCGv_i32 t0 = tcg_temp_local_new_i32(); + + /* No error here: 6 bits are used */ + tcg_gen_andi_i32(t0, arg2, 0x3F); + tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); + tcg_gen_shl_i32(ret, arg1, t0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i32(ret, 0); + gen_set_label(l2); + tcg_temp_free_i32(t0); +} +GEN_SPEOP_ARITH2(evslw, gen_op_evslw); +static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_andi_i32(t0, arg2, 0x1F); + tcg_gen_rotl_i32(ret, arg1, t0); + tcg_temp_free_i32(t0); +} +GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); +static inline void gen_evmergehi(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); +} +GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); +static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_sub_i32(ret, arg2, arg1); +} +GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); + +/* SPE arithmetic immediate */ +#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ + tcg_op(t0, t0, rA(ctx->opcode)); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ + tcg_op(t0, t0, rA(ctx->opcode)); \ + tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ + \ + tcg_temp_free_i32(t0); \ +} +GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); +GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); + +/* SPE comparison */ +#define GEN_SPEOP_COMP(name, tcg_cond) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + TCGLabel *l1 = gen_new_label(); \ + TCGLabel *l2 = gen_new_label(); \ + TCGLabel *l3 = gen_new_label(); \ + TCGLabel *l4 = gen_new_label(); \ + \ + tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ + tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ + tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ + \ + tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ + cpu_gpr[rB(ctx->opcode)], l1); \ + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ + tcg_gen_br(l2); \ + gen_set_label(l1); \ + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ + CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ + gen_set_label(l2); \ + tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ + cpu_gprh[rB(ctx->opcode)], l3); \ + tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ + ~(CRF_CH | CRF_CH_AND_CL)); \ + tcg_gen_br(l4); \ + gen_set_label(l3); \ + tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ + CRF_CH | CRF_CH_OR_CL); \ + gen_set_label(l4); \ +} +GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); +GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); +GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); +GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); +GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); + +/* SPE misc */ +static inline void gen_brinc(DisasContext *ctx) +{ + /* Note: brinc is usable even if SPE is disabled */ + gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], + cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); +} +static inline void gen_evmergelo(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); +} +static inline void gen_evmergehilo(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); +} +static inline void gen_evmergelohi(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + if (rD(ctx->opcode) == rA(ctx->opcode)) { + TCGv tmp = tcg_temp_new(); + tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); + tcg_temp_free(tmp); + } else { + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + } +} +static inline void gen_evsplati(DisasContext *ctx) +{ + uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; + + tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); + tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); +} +static inline void gen_evsplatfi(DisasContext *ctx) +{ + uint64_t imm = rA(ctx->opcode) << 27; + + tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); + tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); +} + +static inline void gen_evsel(DisasContext *ctx) +{ + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + TCGLabel *l3 = gen_new_label(); + TCGLabel *l4 = gen_new_label(); + TCGv_i32 t0 = tcg_temp_local_new_i32(); + + tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + gen_set_label(l2); + tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_br(l4); + gen_set_label(l3); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); + gen_set_label(l4); + tcg_temp_free_i32(t0); +} + +static void gen_evsel0(DisasContext *ctx) +{ + gen_evsel(ctx); +} + +static void gen_evsel1(DisasContext *ctx) +{ + gen_evsel(ctx); +} + +static void gen_evsel2(DisasContext *ctx) +{ + gen_evsel(ctx); +} + +static void gen_evsel3(DisasContext *ctx) +{ + gen_evsel(ctx); +} + +/* Multiply */ + +static inline void gen_evmwumi(DisasContext *ctx) +{ + TCGv_i64 t0, t1; + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + /* t0 := rA; t1 := rB */ + tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32u_i64(t0, t0); + tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); + tcg_gen_ext32u_i64(t1, t1); + + tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ + + gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static inline void gen_evmwumia(DisasContext *ctx) +{ + TCGv_i64 tmp; + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + + gen_evmwumi(ctx); /* rD := rA * rB */ + + tmp = tcg_temp_new_i64(); + + /* acc := rD */ + gen_load_gpr64(tmp, rD(ctx->opcode)); + tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_temp_free_i64(tmp); +} + +static inline void gen_evmwumiaa(DisasContext *ctx) +{ + TCGv_i64 acc; + TCGv_i64 tmp; + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + + gen_evmwumi(ctx); /* rD := rA * rB */ + + acc = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); + + /* tmp := rD */ + gen_load_gpr64(tmp, rD(ctx->opcode)); + + /* Load acc */ + tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + + /* acc := tmp + acc */ + tcg_gen_add_i64(acc, acc, tmp); + + /* Store acc */ + tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + + /* rD := acc */ + gen_store_gpr64(rD(ctx->opcode), acc); + + tcg_temp_free_i64(acc); + tcg_temp_free_i64(tmp); +} + +static inline void gen_evmwsmi(DisasContext *ctx) +{ + TCGv_i64 t0, t1; + + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + /* t0 := rA; t1 := rB */ + tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_i64(t0, t0); + tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); + tcg_gen_ext32s_i64(t1, t1); + + tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ + + gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static inline void gen_evmwsmia(DisasContext *ctx) +{ + TCGv_i64 tmp; + + gen_evmwsmi(ctx); /* rD := rA * rB */ + + tmp = tcg_temp_new_i64(); + + /* acc := rD */ + gen_load_gpr64(tmp, rD(ctx->opcode)); + tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + + tcg_temp_free_i64(tmp); +} + +static inline void gen_evmwsmiaa(DisasContext *ctx) +{ + TCGv_i64 acc = tcg_temp_new_i64(); + TCGv_i64 tmp = tcg_temp_new_i64(); + + gen_evmwsmi(ctx); /* rD := rA * rB */ + + acc = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); + + /* tmp := rD */ + gen_load_gpr64(tmp, rD(ctx->opcode)); + + /* Load acc */ + tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + + /* acc := tmp + acc */ + tcg_gen_add_i64(acc, acc, tmp); + + /* Store acc */ + tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + + /* rD := acc */ + gen_store_gpr64(rD(ctx->opcode), acc); + + tcg_temp_free_i64(acc); + tcg_temp_free_i64(tmp); +} + +GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// +GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// +GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// +GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// +GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// +GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // +GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// +GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// +GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// +GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// +GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// +GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// +GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// +GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// +GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // +GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); +GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// +GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// +GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// +GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// +GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// + +/* SPE load and stores */ +static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) +{ + target_ulong uimm = rB(ctx->opcode); + + if (rA(ctx->opcode) == 0) { + tcg_gen_movi_tl(EA, uimm << sh); + } else { + tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(EA, EA); + } + } +} + +static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + gen_qemu_ld64_i64(ctx, t0, addr); + gen_store_gpr64(rD(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} + +static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) +{ + gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 4); + gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); +} + +static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(t0, t0, 16); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16s(ctx, t0, addr); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); + tcg_temp_free(t0); +} + +static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) +{ + gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); +} + +static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) +{ + gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); +} + +static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld32u(ctx, t0, addr); + tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); + tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_ld16u(ctx, t0, addr); + tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); + tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); + tcg_temp_free(t0); +} + +static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + gen_load_gpr64(t0, rS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, addr); + tcg_temp_free_i64(t0); +} + +static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) +{ + gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 4); + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); +} + +static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); + gen_qemu_st16(ctx, t0, addr); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 2); + tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); + gen_qemu_st16(ctx, t0, addr); + tcg_temp_free(t0); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); +} + +static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); + gen_qemu_st16(ctx, t0, addr); + gen_addr_add(ctx, addr, addr, 2); + tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); + gen_qemu_st16(ctx, t0, addr); + tcg_temp_free(t0); +} + +static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) +{ + gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); + gen_addr_add(ctx, addr, addr, 2); + gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); +} + +static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) +{ + gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); +} + +static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) +{ + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); +} + +#define GEN_SPEOP_LDST(name, opc2, sh) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv t0; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + t0 = tcg_temp_new(); \ + if (Rc(ctx->opcode)) { \ + gen_addr_spe_imm_index(ctx, t0, sh); \ + } else { \ + gen_addr_reg_index(ctx, t0); \ + } \ + gen_op_##name(ctx, t0); \ + tcg_temp_free(t0); \ +} + +GEN_SPEOP_LDST(evldd, 0x00, 3); +GEN_SPEOP_LDST(evldw, 0x01, 3); +GEN_SPEOP_LDST(evldh, 0x02, 3); +GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); +GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); +GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); +GEN_SPEOP_LDST(evlwhe, 0x08, 2); +GEN_SPEOP_LDST(evlwhou, 0x0A, 2); +GEN_SPEOP_LDST(evlwhos, 0x0B, 2); +GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); +GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); + +GEN_SPEOP_LDST(evstdd, 0x10, 3); +GEN_SPEOP_LDST(evstdw, 0x11, 3); +GEN_SPEOP_LDST(evstdh, 0x12, 3); +GEN_SPEOP_LDST(evstwhe, 0x18, 2); +GEN_SPEOP_LDST(evstwho, 0x1A, 2); +GEN_SPEOP_LDST(evstwwe, 0x1C, 2); +GEN_SPEOP_LDST(evstwwo, 0x1E, 2); + +/* Multiply and add - TODO */ +#if 0 +GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// +GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); + +GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); +GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); + +GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); +GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); +GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); +GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); +GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); + +GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); + +GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); + +GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); + +GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); +GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); +GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); +#endif + +/*** SPE floating-point extension ***/ +#define GEN_SPEFPUOP_CONV_32_32(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0 = tcg_temp_new_i32(); \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ + gen_helper_##name(t0, cpu_env, t0); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + tcg_temp_free_i32(t0); \ +} +#define GEN_SPEFPUOP_CONV_32_64(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0 = tcg_temp_new_i64(); \ + TCGv_i32 t1 = tcg_temp_new_i32(); \ + gen_load_gpr64(t0, rB(ctx->opcode)); \ + gen_helper_##name(t1, cpu_env, t0); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i32(t1); \ +} +#define GEN_SPEFPUOP_CONV_64_32(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0 = tcg_temp_new_i64(); \ + TCGv_i32 t1 = tcg_temp_new_i32(); \ + tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ + gen_helper_##name(t0, cpu_env, t1); \ + gen_store_gpr64(rD(ctx->opcode), t0); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i32(t1); \ +} +#define GEN_SPEFPUOP_CONV_64_64(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0 = tcg_temp_new_i64(); \ + gen_load_gpr64(t0, rB(ctx->opcode)); \ + gen_helper_##name(t0, cpu_env, t0); \ + gen_store_gpr64(rD(ctx->opcode), t0); \ + tcg_temp_free_i64(t0); \ +} +#define GEN_SPEFPUOP_ARITH2_32_32(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0, t1; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + t1 = tcg_temp_new_i32(); \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ + gen_helper_##name(t0, cpu_env, t0, t1); \ + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ + \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i32(t1); \ +} +#define GEN_SPEFPUOP_ARITH2_64_64(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0, t1; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + gen_load_gpr64(t0, rA(ctx->opcode)); \ + gen_load_gpr64(t1, rB(ctx->opcode)); \ + gen_helper_##name(t0, cpu_env, t0, t1); \ + gen_store_gpr64(rD(ctx->opcode), t0); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ +} +#define GEN_SPEFPUOP_COMP_32(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0, t1; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i32(); \ + t1 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ + \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i32(t1); \ +} +#define GEN_SPEFPUOP_COMP_64(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0, t1; \ + if (unlikely(!ctx->spe_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_SPEU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + gen_load_gpr64(t0, rA(ctx->opcode)); \ + gen_load_gpr64(t1, rB(ctx->opcode)); \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ +} + +/* Single precision floating-point vectors operations */ +/* Arithmetic */ +GEN_SPEFPUOP_ARITH2_64_64(evfsadd); +GEN_SPEFPUOP_ARITH2_64_64(evfssub); +GEN_SPEFPUOP_ARITH2_64_64(evfsmul); +GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); +static inline void gen_evfsabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + ~0x80000000); + tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + ~0x80000000); +} +static inline void gen_evfsnabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + 0x80000000); + tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + 0x80000000); +} +static inline void gen_evfsneg(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + 0x80000000); + tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + 0x80000000); +} + +/* Conversion */ +GEN_SPEFPUOP_CONV_64_64(evfscfui); +GEN_SPEFPUOP_CONV_64_64(evfscfsi); +GEN_SPEFPUOP_CONV_64_64(evfscfuf); +GEN_SPEFPUOP_CONV_64_64(evfscfsf); +GEN_SPEFPUOP_CONV_64_64(evfsctui); +GEN_SPEFPUOP_CONV_64_64(evfsctsi); +GEN_SPEFPUOP_CONV_64_64(evfsctuf); +GEN_SPEFPUOP_CONV_64_64(evfsctsf); +GEN_SPEFPUOP_CONV_64_64(evfsctuiz); +GEN_SPEFPUOP_CONV_64_64(evfsctsiz); + +/* Comparison */ +GEN_SPEFPUOP_COMP_64(evfscmpgt); +GEN_SPEFPUOP_COMP_64(evfscmplt); +GEN_SPEFPUOP_COMP_64(evfscmpeq); +GEN_SPEFPUOP_COMP_64(evfststgt); +GEN_SPEFPUOP_COMP_64(evfststlt); +GEN_SPEFPUOP_COMP_64(evfststeq); + +/* Opcodes definitions */ +GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // +GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // +GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // +GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // +GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // +GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // + +/* Single precision floating-point operations */ +/* Arithmetic */ +GEN_SPEFPUOP_ARITH2_32_32(efsadd); +GEN_SPEFPUOP_ARITH2_32_32(efssub); +GEN_SPEFPUOP_ARITH2_32_32(efsmul); +GEN_SPEFPUOP_ARITH2_32_32(efsdiv); +static inline void gen_efsabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + (target_long)~0x80000000LL); +} +static inline void gen_efsnabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + 0x80000000); +} +static inline void gen_efsneg(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], + 0x80000000); +} + +/* Conversion */ +GEN_SPEFPUOP_CONV_32_32(efscfui); +GEN_SPEFPUOP_CONV_32_32(efscfsi); +GEN_SPEFPUOP_CONV_32_32(efscfuf); +GEN_SPEFPUOP_CONV_32_32(efscfsf); +GEN_SPEFPUOP_CONV_32_32(efsctui); +GEN_SPEFPUOP_CONV_32_32(efsctsi); +GEN_SPEFPUOP_CONV_32_32(efsctuf); +GEN_SPEFPUOP_CONV_32_32(efsctsf); +GEN_SPEFPUOP_CONV_32_32(efsctuiz); +GEN_SPEFPUOP_CONV_32_32(efsctsiz); +GEN_SPEFPUOP_CONV_32_64(efscfd); + +/* Comparison */ +GEN_SPEFPUOP_COMP_32(efscmpgt); +GEN_SPEFPUOP_COMP_32(efscmplt); +GEN_SPEFPUOP_COMP_32(efscmpeq); +GEN_SPEFPUOP_COMP_32(efststgt); +GEN_SPEFPUOP_COMP_32(efststlt); +GEN_SPEFPUOP_COMP_32(efststeq); + +/* Opcodes definitions */ +GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // +GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // +GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // +GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // +GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // +GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // +GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // +GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // + +/* Double precision floating-point operations */ +/* Arithmetic */ +GEN_SPEFPUOP_ARITH2_64_64(efdadd); +GEN_SPEFPUOP_ARITH2_64_64(efdsub); +GEN_SPEFPUOP_ARITH2_64_64(efdmul); +GEN_SPEFPUOP_ARITH2_64_64(efddiv); +static inline void gen_efdabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + ~0x80000000); +} +static inline void gen_efdnabs(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + 0x80000000); +} +static inline void gen_efdneg(DisasContext *ctx) +{ + if (unlikely(!ctx->spe_enabled)) { + gen_exception(ctx, POWERPC_EXCP_SPEU); + return; + } + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], + 0x80000000); +} + +/* Conversion */ +GEN_SPEFPUOP_CONV_64_32(efdcfui); +GEN_SPEFPUOP_CONV_64_32(efdcfsi); +GEN_SPEFPUOP_CONV_64_32(efdcfuf); +GEN_SPEFPUOP_CONV_64_32(efdcfsf); +GEN_SPEFPUOP_CONV_32_64(efdctui); +GEN_SPEFPUOP_CONV_32_64(efdctsi); +GEN_SPEFPUOP_CONV_32_64(efdctuf); +GEN_SPEFPUOP_CONV_32_64(efdctsf); +GEN_SPEFPUOP_CONV_32_64(efdctuiz); +GEN_SPEFPUOP_CONV_32_64(efdctsiz); +GEN_SPEFPUOP_CONV_64_32(efdcfs); +GEN_SPEFPUOP_CONV_64_64(efdcfuid); +GEN_SPEFPUOP_CONV_64_64(efdcfsid); +GEN_SPEFPUOP_CONV_64_64(efdctuidz); +GEN_SPEFPUOP_CONV_64_64(efdctsidz); + +/* Comparison */ +GEN_SPEFPUOP_COMP_64(efdcmpgt); +GEN_SPEFPUOP_COMP_64(efdcmplt); +GEN_SPEFPUOP_COMP_64(efdcmpeq); +GEN_SPEFPUOP_COMP_64(efdtstgt); +GEN_SPEFPUOP_COMP_64(efdtstlt); +GEN_SPEFPUOP_COMP_64(efdtsteq); + +/* Opcodes definitions */ +GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // +GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // +GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // +GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // +GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // +GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // +GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // +GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // +GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // +GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // + +#undef GEN_SPE +#undef GEN_SPEOP_LDST diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe-impl.inc.c deleted file mode 100644 index 36b4d5654d..0000000000 --- a/target/ppc/translate/spe-impl.inc.c +++ /dev/null @@ -1,1221 +0,0 @@ -/* - * translate-spe.c - * - * Freescale SPE extension translation - */ - -/*** SPE extension ***/ -/* Register moves */ - -static inline void gen_evmra(DisasContext *ctx) -{ - - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - - TCGv_i64 tmp = tcg_temp_new_i64(); - - /* tmp := rA_lo + rA_hi << 32 */ - tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], - cpu_gprh[rA(ctx->opcode)]); - - /* spe_acc := tmp */ - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - tcg_temp_free_i64(tmp); - - /* rD := rA */ - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); -} - -static inline void gen_load_gpr64(TCGv_i64 t, int reg) -{ - tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); -} - -static inline void gen_store_gpr64(int reg, TCGv_i64 t) -{ - tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); -} - -#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ -{ \ - if (Rc(ctx->opcode)) \ - gen_##name1(ctx); \ - else \ - gen_##name0(ctx); \ -} - -/* Handler for undefined SPE opcodes */ -static inline void gen_speundef(DisasContext *ctx) -{ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); -} - -/* SPE logic */ -#define GEN_SPEOP_LOGIC2(name, tcg_op) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ - cpu_gpr[rB(ctx->opcode)]); \ - tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ - cpu_gprh[rB(ctx->opcode)]); \ -} - -GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); -GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); -GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); -GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); -GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); -GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); -GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); -GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); - -/* SPE logic immediate */ -#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ - tcg_opi(t0, t0, rB(ctx->opcode)); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ - tcg_opi(t0, t0, rB(ctx->opcode)); \ - tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ - \ - tcg_temp_free_i32(t0); \ -} -GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); -GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); -GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); -GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); - -/* SPE arithmetic */ -#define GEN_SPEOP_ARITH1(name, tcg_op) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ - tcg_op(t0, t0); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ - tcg_op(t0, t0); \ - tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ - \ - tcg_temp_free_i32(t0); \ -} - -GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); -GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); -GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); -GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); -static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) -{ - tcg_gen_addi_i32(ret, arg1, 0x8000); - tcg_gen_ext16u_i32(ret, ret); -} -GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); -GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); -GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); - -#define GEN_SPEOP_ARITH2(name, tcg_op) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0, t1; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - t1 = tcg_temp_new_i32(); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ - tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ - tcg_op(t0, t0, t1); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ - tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ - tcg_op(t0, t0, t1); \ - tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ - \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_i32(t1); \ -} - -static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv_i32 t0 = tcg_temp_local_new_i32(); - - /* No error here: 6 bits are used */ - tcg_gen_andi_i32(t0, arg2, 0x3F); - tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); - tcg_gen_shr_i32(ret, arg1, t0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_i32(ret, 0); - gen_set_label(l2); - tcg_temp_free_i32(t0); -} -GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); -static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv_i32 t0 = tcg_temp_local_new_i32(); - - /* No error here: 6 bits are used */ - tcg_gen_andi_i32(t0, arg2, 0x3F); - tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); - tcg_gen_sar_i32(ret, arg1, t0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_i32(ret, 0); - gen_set_label(l2); - tcg_temp_free_i32(t0); -} -GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); -static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv_i32 t0 = tcg_temp_local_new_i32(); - - /* No error here: 6 bits are used */ - tcg_gen_andi_i32(t0, arg2, 0x3F); - tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); - tcg_gen_shl_i32(ret, arg1, t0); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_movi_i32(ret, 0); - gen_set_label(l2); - tcg_temp_free_i32(t0); -} -GEN_SPEOP_ARITH2(evslw, gen_op_evslw); -static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_andi_i32(t0, arg2, 0x1F); - tcg_gen_rotl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); -} -GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); -static inline void gen_evmergehi(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); -} -GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); -static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_sub_i32(ret, arg2, arg1); -} -GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); - -/* SPE arithmetic immediate */ -#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ - tcg_op(t0, t0, rA(ctx->opcode)); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ - tcg_op(t0, t0, rA(ctx->opcode)); \ - tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ - \ - tcg_temp_free_i32(t0); \ -} -GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); -GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); - -/* SPE comparison */ -#define GEN_SPEOP_COMP(name, tcg_cond) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - TCGLabel *l1 = gen_new_label(); \ - TCGLabel *l2 = gen_new_label(); \ - TCGLabel *l3 = gen_new_label(); \ - TCGLabel *l4 = gen_new_label(); \ - \ - tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ - tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ - tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ - tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ - \ - tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ - cpu_gpr[rB(ctx->opcode)], l1); \ - tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ - tcg_gen_br(l2); \ - gen_set_label(l1); \ - tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ - CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ - gen_set_label(l2); \ - tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ - cpu_gprh[rB(ctx->opcode)], l3); \ - tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ - ~(CRF_CH | CRF_CH_AND_CL)); \ - tcg_gen_br(l4); \ - gen_set_label(l3); \ - tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ - CRF_CH | CRF_CH_OR_CL); \ - gen_set_label(l4); \ -} -GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); -GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); -GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); -GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); -GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); - -/* SPE misc */ -static inline void gen_brinc(DisasContext *ctx) -{ - /* Note: brinc is usable even if SPE is disabled */ - gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); -} -static inline void gen_evmergelo(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); -} -static inline void gen_evmergehilo(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); -} -static inline void gen_evmergelohi(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - if (rD(ctx->opcode) == rA(ctx->opcode)) { - TCGv tmp = tcg_temp_new(); - tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); - tcg_temp_free(tmp); - } else { - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - } -} -static inline void gen_evsplati(DisasContext *ctx) -{ - uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; - - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); - tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); -} -static inline void gen_evsplatfi(DisasContext *ctx) -{ - uint64_t imm = rA(ctx->opcode) << 27; - - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); - tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); -} - -static inline void gen_evsel(DisasContext *ctx) -{ - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - TCGLabel *l4 = gen_new_label(); - TCGv_i32 t0 = tcg_temp_local_new_i32(); - - tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - gen_set_label(l2); - tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l4); - gen_set_label(l3); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - gen_set_label(l4); - tcg_temp_free_i32(t0); -} - -static void gen_evsel0(DisasContext *ctx) -{ - gen_evsel(ctx); -} - -static void gen_evsel1(DisasContext *ctx) -{ - gen_evsel(ctx); -} - -static void gen_evsel2(DisasContext *ctx) -{ - gen_evsel(ctx); -} - -static void gen_evsel3(DisasContext *ctx) -{ - gen_evsel(ctx); -} - -/* Multiply */ - -static inline void gen_evmwumi(DisasContext *ctx) -{ - TCGv_i64 t0, t1; - - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - - /* t0 := rA; t1 := rB */ - tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_ext32u_i64(t0, t0); - tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); - tcg_gen_ext32u_i64(t1, t1); - - tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ - - gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static inline void gen_evmwumia(DisasContext *ctx) -{ - TCGv_i64 tmp; - - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - - gen_evmwumi(ctx); /* rD := rA * rB */ - - tmp = tcg_temp_new_i64(); - - /* acc := rD */ - gen_load_gpr64(tmp, rD(ctx->opcode)); - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - tcg_temp_free_i64(tmp); -} - -static inline void gen_evmwumiaa(DisasContext *ctx) -{ - TCGv_i64 acc; - TCGv_i64 tmp; - - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - - gen_evmwumi(ctx); /* rD := rA * rB */ - - acc = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - - /* tmp := rD */ - gen_load_gpr64(tmp, rD(ctx->opcode)); - - /* Load acc */ - tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); - - /* acc := tmp + acc */ - tcg_gen_add_i64(acc, acc, tmp); - - /* Store acc */ - tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); - - /* rD := acc */ - gen_store_gpr64(rD(ctx->opcode), acc); - - tcg_temp_free_i64(acc); - tcg_temp_free_i64(tmp); -} - -static inline void gen_evmwsmi(DisasContext *ctx) -{ - TCGv_i64 t0, t1; - - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - - /* t0 := rA; t1 := rB */ - tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_ext32s_i64(t0, t0); - tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); - tcg_gen_ext32s_i64(t1, t1); - - tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ - - gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static inline void gen_evmwsmia(DisasContext *ctx) -{ - TCGv_i64 tmp; - - gen_evmwsmi(ctx); /* rD := rA * rB */ - - tmp = tcg_temp_new_i64(); - - /* acc := rD */ - gen_load_gpr64(tmp, rD(ctx->opcode)); - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - - tcg_temp_free_i64(tmp); -} - -static inline void gen_evmwsmiaa(DisasContext *ctx) -{ - TCGv_i64 acc = tcg_temp_new_i64(); - TCGv_i64 tmp = tcg_temp_new_i64(); - - gen_evmwsmi(ctx); /* rD := rA * rB */ - - acc = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - - /* tmp := rD */ - gen_load_gpr64(tmp, rD(ctx->opcode)); - - /* Load acc */ - tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); - - /* acc := tmp + acc */ - tcg_gen_add_i64(acc, acc, tmp); - - /* Store acc */ - tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); - - /* rD := acc */ - gen_store_gpr64(rD(ctx->opcode), acc); - - tcg_temp_free_i64(acc); - tcg_temp_free_i64(tmp); -} - -GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// -GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// -GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// -GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// -GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// -GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // -GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// -GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// -GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// -GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// -GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// -GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// -GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// -GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// -GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // -GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); -GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// -GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// -GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// -GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// -GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// - -/* SPE load and stores */ -static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) -{ - target_ulong uimm = rB(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - tcg_gen_movi_tl(EA, uimm << sh); - } else { - tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(EA, EA); - } - } -} - -static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - gen_qemu_ld64_i64(ctx, t0, addr); - gen_store_gpr64(rD(ctx->opcode), t0); - tcg_temp_free_i64(t0); -} - -static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) -{ - gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 4); - gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); -} - -static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(t0, t0, 16); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16s(ctx, t0, addr); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); - tcg_temp_free(t0); -} - -static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) -{ - gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); -} - -static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) -{ - gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); -} - -static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld32u(ctx, t0, addr); - tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); - tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_ld16u(ctx, t0, addr); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); - tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); - tcg_temp_free(t0); -} - -static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - gen_load_gpr64(t0, rS(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, addr); - tcg_temp_free_i64(t0); -} - -static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) -{ - gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 4); - gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); -} - -static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); - gen_qemu_st16(ctx, t0, addr); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 2); - tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); - gen_qemu_st16(ctx, t0, addr); - tcg_temp_free(t0); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); -} - -static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); - gen_qemu_st16(ctx, t0, addr); - gen_addr_add(ctx, addr, addr, 2); - tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); - gen_qemu_st16(ctx, t0, addr); - tcg_temp_free(t0); -} - -static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) -{ - gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); - gen_addr_add(ctx, addr, addr, 2); - gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); -} - -static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) -{ - gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); -} - -static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) -{ - gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); -} - -#define GEN_SPEOP_LDST(name, opc2, sh) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv t0; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - t0 = tcg_temp_new(); \ - if (Rc(ctx->opcode)) { \ - gen_addr_spe_imm_index(ctx, t0, sh); \ - } else { \ - gen_addr_reg_index(ctx, t0); \ - } \ - gen_op_##name(ctx, t0); \ - tcg_temp_free(t0); \ -} - -GEN_SPEOP_LDST(evldd, 0x00, 3); -GEN_SPEOP_LDST(evldw, 0x01, 3); -GEN_SPEOP_LDST(evldh, 0x02, 3); -GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); -GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); -GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); -GEN_SPEOP_LDST(evlwhe, 0x08, 2); -GEN_SPEOP_LDST(evlwhou, 0x0A, 2); -GEN_SPEOP_LDST(evlwhos, 0x0B, 2); -GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); -GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); - -GEN_SPEOP_LDST(evstdd, 0x10, 3); -GEN_SPEOP_LDST(evstdw, 0x11, 3); -GEN_SPEOP_LDST(evstdh, 0x12, 3); -GEN_SPEOP_LDST(evstwhe, 0x18, 2); -GEN_SPEOP_LDST(evstwho, 0x1A, 2); -GEN_SPEOP_LDST(evstwwe, 0x1C, 2); -GEN_SPEOP_LDST(evstwwo, 0x1E, 2); - -/* Multiply and add - TODO */ -#if 0 -GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// -GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); - -GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); -GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); - -GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); -GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); -GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); -GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); -GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); - -GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); - -GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); - -GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); - -GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); -GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); -GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); -#endif - -/*** SPE floating-point extension ***/ -#define GEN_SPEFPUOP_CONV_32_32(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0 = tcg_temp_new_i32(); \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ - gen_helper_##name(t0, cpu_env, t0); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - tcg_temp_free_i32(t0); \ -} -#define GEN_SPEFPUOP_CONV_32_64(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0 = tcg_temp_new_i64(); \ - TCGv_i32 t1 = tcg_temp_new_i32(); \ - gen_load_gpr64(t0, rB(ctx->opcode)); \ - gen_helper_##name(t1, cpu_env, t0); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i32(t1); \ -} -#define GEN_SPEFPUOP_CONV_64_32(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0 = tcg_temp_new_i64(); \ - TCGv_i32 t1 = tcg_temp_new_i32(); \ - tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ - gen_helper_##name(t0, cpu_env, t1); \ - gen_store_gpr64(rD(ctx->opcode), t0); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i32(t1); \ -} -#define GEN_SPEFPUOP_CONV_64_64(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0 = tcg_temp_new_i64(); \ - gen_load_gpr64(t0, rB(ctx->opcode)); \ - gen_helper_##name(t0, cpu_env, t0); \ - gen_store_gpr64(rD(ctx->opcode), t0); \ - tcg_temp_free_i64(t0); \ -} -#define GEN_SPEFPUOP_ARITH2_32_32(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0, t1; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - t1 = tcg_temp_new_i32(); \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ - tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ - gen_helper_##name(t0, cpu_env, t0, t1); \ - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ - \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_i32(t1); \ -} -#define GEN_SPEFPUOP_ARITH2_64_64(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0, t1; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - gen_load_gpr64(t0, rA(ctx->opcode)); \ - gen_load_gpr64(t1, rB(ctx->opcode)); \ - gen_helper_##name(t0, cpu_env, t0, t1); \ - gen_store_gpr64(rD(ctx->opcode), t0); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ -} -#define GEN_SPEFPUOP_COMP_32(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 t0, t1; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i32(); \ - t1 = tcg_temp_new_i32(); \ - \ - tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ - tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ - \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_i32(t1); \ -} -#define GEN_SPEFPUOP_COMP_64(name) \ -static inline void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0, t1; \ - if (unlikely(!ctx->spe_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_SPEU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - gen_load_gpr64(t0, rA(ctx->opcode)); \ - gen_load_gpr64(t1, rB(ctx->opcode)); \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ -} - -/* Single precision floating-point vectors operations */ -/* Arithmetic */ -GEN_SPEFPUOP_ARITH2_64_64(evfsadd); -GEN_SPEFPUOP_ARITH2_64_64(evfssub); -GEN_SPEFPUOP_ARITH2_64_64(evfsmul); -GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); -static inline void gen_evfsabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - ~0x80000000); - tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - ~0x80000000); -} -static inline void gen_evfsnabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - 0x80000000); - tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - 0x80000000); -} -static inline void gen_evfsneg(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - 0x80000000); - tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - 0x80000000); -} - -/* Conversion */ -GEN_SPEFPUOP_CONV_64_64(evfscfui); -GEN_SPEFPUOP_CONV_64_64(evfscfsi); -GEN_SPEFPUOP_CONV_64_64(evfscfuf); -GEN_SPEFPUOP_CONV_64_64(evfscfsf); -GEN_SPEFPUOP_CONV_64_64(evfsctui); -GEN_SPEFPUOP_CONV_64_64(evfsctsi); -GEN_SPEFPUOP_CONV_64_64(evfsctuf); -GEN_SPEFPUOP_CONV_64_64(evfsctsf); -GEN_SPEFPUOP_CONV_64_64(evfsctuiz); -GEN_SPEFPUOP_CONV_64_64(evfsctsiz); - -/* Comparison */ -GEN_SPEFPUOP_COMP_64(evfscmpgt); -GEN_SPEFPUOP_COMP_64(evfscmplt); -GEN_SPEFPUOP_COMP_64(evfscmpeq); -GEN_SPEFPUOP_COMP_64(evfststgt); -GEN_SPEFPUOP_COMP_64(evfststlt); -GEN_SPEFPUOP_COMP_64(evfststeq); - -/* Opcodes definitions */ -GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // -GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // -GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // -GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // -GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // -GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // - -/* Single precision floating-point operations */ -/* Arithmetic */ -GEN_SPEFPUOP_ARITH2_32_32(efsadd); -GEN_SPEFPUOP_ARITH2_32_32(efssub); -GEN_SPEFPUOP_ARITH2_32_32(efsmul); -GEN_SPEFPUOP_ARITH2_32_32(efsdiv); -static inline void gen_efsabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - (target_long)~0x80000000LL); -} -static inline void gen_efsnabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - 0x80000000); -} -static inline void gen_efsneg(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], - 0x80000000); -} - -/* Conversion */ -GEN_SPEFPUOP_CONV_32_32(efscfui); -GEN_SPEFPUOP_CONV_32_32(efscfsi); -GEN_SPEFPUOP_CONV_32_32(efscfuf); -GEN_SPEFPUOP_CONV_32_32(efscfsf); -GEN_SPEFPUOP_CONV_32_32(efsctui); -GEN_SPEFPUOP_CONV_32_32(efsctsi); -GEN_SPEFPUOP_CONV_32_32(efsctuf); -GEN_SPEFPUOP_CONV_32_32(efsctsf); -GEN_SPEFPUOP_CONV_32_32(efsctuiz); -GEN_SPEFPUOP_CONV_32_32(efsctsiz); -GEN_SPEFPUOP_CONV_32_64(efscfd); - -/* Comparison */ -GEN_SPEFPUOP_COMP_32(efscmpgt); -GEN_SPEFPUOP_COMP_32(efscmplt); -GEN_SPEFPUOP_COMP_32(efscmpeq); -GEN_SPEFPUOP_COMP_32(efststgt); -GEN_SPEFPUOP_COMP_32(efststlt); -GEN_SPEFPUOP_COMP_32(efststeq); - -/* Opcodes definitions */ -GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // -GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // -GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // -GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // -GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // -GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // -GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // -GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // - -/* Double precision floating-point operations */ -/* Arithmetic */ -GEN_SPEFPUOP_ARITH2_64_64(efdadd); -GEN_SPEFPUOP_ARITH2_64_64(efdsub); -GEN_SPEFPUOP_ARITH2_64_64(efdmul); -GEN_SPEFPUOP_ARITH2_64_64(efddiv); -static inline void gen_efdabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - ~0x80000000); -} -static inline void gen_efdnabs(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - 0x80000000); -} -static inline void gen_efdneg(DisasContext *ctx) -{ - if (unlikely(!ctx->spe_enabled)) { - gen_exception(ctx, POWERPC_EXCP_SPEU); - return; - } - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], - 0x80000000); -} - -/* Conversion */ -GEN_SPEFPUOP_CONV_64_32(efdcfui); -GEN_SPEFPUOP_CONV_64_32(efdcfsi); -GEN_SPEFPUOP_CONV_64_32(efdcfuf); -GEN_SPEFPUOP_CONV_64_32(efdcfsf); -GEN_SPEFPUOP_CONV_32_64(efdctui); -GEN_SPEFPUOP_CONV_32_64(efdctsi); -GEN_SPEFPUOP_CONV_32_64(efdctuf); -GEN_SPEFPUOP_CONV_32_64(efdctsf); -GEN_SPEFPUOP_CONV_32_64(efdctuiz); -GEN_SPEFPUOP_CONV_32_64(efdctsiz); -GEN_SPEFPUOP_CONV_64_32(efdcfs); -GEN_SPEFPUOP_CONV_64_64(efdcfuid); -GEN_SPEFPUOP_CONV_64_64(efdcfsid); -GEN_SPEFPUOP_CONV_64_64(efdctuidz); -GEN_SPEFPUOP_CONV_64_64(efdctsidz); - -/* Comparison */ -GEN_SPEFPUOP_COMP_64(efdcmpgt); -GEN_SPEFPUOP_COMP_64(efdcmplt); -GEN_SPEFPUOP_COMP_64(efdcmpeq); -GEN_SPEFPUOP_COMP_64(efdtstgt); -GEN_SPEFPUOP_COMP_64(efdtstlt); -GEN_SPEFPUOP_COMP_64(efdtsteq); - -/* Opcodes definitions */ -GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // -GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // -GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // -GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // -GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // -GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // -GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // -GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // -GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // -GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // - -#undef GEN_SPE -#undef GEN_SPEOP_LDST diff --git a/target/ppc/translate/spe-ops.c.inc b/target/ppc/translate/spe-ops.c.inc new file mode 100644 index 0000000000..7efe8b8746 --- /dev/null +++ b/target/ppc/translate/spe-ops.c.inc @@ -0,0 +1,105 @@ +GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), +GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), +GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), +GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), + +#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ + GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) +GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), +GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), +GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), +GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), +GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), +GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), +GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), +GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), +GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), +GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), +GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), +GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), +GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), + +GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), +GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), +GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), +GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), +GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), +GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), + +GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), +GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), +GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), +GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), +GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), +GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), +GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), +GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), + +GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), +GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), +GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), +GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), +GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), +GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), +GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), +GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), +GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), +GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), + +#define GEN_SPEOP_LDST(name, opc2, sh) \ +GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) +GEN_SPEOP_LDST(evldd, 0x00, 3), +GEN_SPEOP_LDST(evldw, 0x01, 3), +GEN_SPEOP_LDST(evldh, 0x02, 3), +GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), +GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), +GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), +GEN_SPEOP_LDST(evlwhe, 0x08, 2), +GEN_SPEOP_LDST(evlwhou, 0x0A, 2), +GEN_SPEOP_LDST(evlwhos, 0x0B, 2), +GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), +GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), + +GEN_SPEOP_LDST(evstdd, 0x10, 3), +GEN_SPEOP_LDST(evstdw, 0x11, 3), +GEN_SPEOP_LDST(evstdh, 0x12, 3), +GEN_SPEOP_LDST(evstwhe, 0x18, 2), +GEN_SPEOP_LDST(evstwho, 0x1A, 2), +GEN_SPEOP_LDST(evstwwe, 0x1C, 2), +GEN_SPEOP_LDST(evstwwo, 0x1E, 2), diff --git a/target/ppc/translate/spe-ops.inc.c b/target/ppc/translate/spe-ops.inc.c deleted file mode 100644 index 7efe8b8746..0000000000 --- a/target/ppc/translate/spe-ops.inc.c +++ /dev/null @@ -1,105 +0,0 @@ -GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), -GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), -GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), -GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), - -#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ - GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) -GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), -GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), -GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), -GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), -GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), -GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), -GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), -GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), -GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), -GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), -GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), -GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), -GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), - -GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), -GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), -GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), -GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), -GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), -GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), - -GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), -GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), -GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), -GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), -GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), -GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), -GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), -GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), - -GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), -GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), -GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), -GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), -GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), -GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), -GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), -GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), -GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), -GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), - -#define GEN_SPEOP_LDST(name, opc2, sh) \ -GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) -GEN_SPEOP_LDST(evldd, 0x00, 3), -GEN_SPEOP_LDST(evldw, 0x01, 3), -GEN_SPEOP_LDST(evldh, 0x02, 3), -GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), -GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), -GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), -GEN_SPEOP_LDST(evlwhe, 0x08, 2), -GEN_SPEOP_LDST(evlwhou, 0x0A, 2), -GEN_SPEOP_LDST(evlwhos, 0x0B, 2), -GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), -GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), - -GEN_SPEOP_LDST(evstdd, 0x10, 3), -GEN_SPEOP_LDST(evstdw, 0x11, 3), -GEN_SPEOP_LDST(evstdh, 0x12, 3), -GEN_SPEOP_LDST(evstwhe, 0x18, 2), -GEN_SPEOP_LDST(evstwho, 0x1A, 2), -GEN_SPEOP_LDST(evstwwe, 0x1C, 2), -GEN_SPEOP_LDST(evstwwo, 0x1E, 2), diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc new file mode 100644 index 0000000000..de2fd136ff --- /dev/null +++ b/target/ppc/translate/vmx-impl.c.inc @@ -0,0 +1,1571 @@ +/* + * translate/vmx-impl.c + * + * Altivec/VMX translation + */ + +/*** Altivec vector extension ***/ +/* Altivec registers moves */ + +static inline TCGv_ptr gen_avr_ptr(int reg) +{ + TCGv_ptr r = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); + return r; +} + +#define GEN_VR_LDX(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 avr; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + avr = tcg_temp_new_i64(); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + tcg_gen_andi_tl(EA, EA, ~0xf); \ + /* \ + * We only need to swap high and low halves. gen_qemu_ld64_i64 \ + * does necessary 64-bit byteswap already. \ + */ \ + if (ctx->le_mode) { \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, false); \ + tcg_gen_addi_tl(EA, EA, 8); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, true); \ + } else { \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, true); \ + tcg_gen_addi_tl(EA, EA, 8); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, false); \ + } \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(avr); \ +} + +#define GEN_VR_STX(name, opc2, opc3) \ +static void gen_st##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 avr; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + avr = tcg_temp_new_i64(); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + tcg_gen_andi_tl(EA, EA, ~0xf); \ + /* \ + * We only need to swap high and low halves. gen_qemu_st64_i64 \ + * does necessary 64-bit byteswap already. \ + */ \ + if (ctx->le_mode) { \ + get_avr64(avr, rD(ctx->opcode), false); \ + gen_qemu_st64_i64(ctx, avr, EA); \ + tcg_gen_addi_tl(EA, EA, 8); \ + get_avr64(avr, rD(ctx->opcode), true); \ + gen_qemu_st64_i64(ctx, avr, EA); \ + } else { \ + get_avr64(avr, rD(ctx->opcode), true); \ + gen_qemu_st64_i64(ctx, avr, EA); \ + tcg_gen_addi_tl(EA, EA, 8); \ + get_avr64(avr, rD(ctx->opcode), false); \ + gen_qemu_st64_i64(ctx, avr, EA); \ + } \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(avr); \ +} + +#define GEN_VR_LVE(name, opc2, opc3, size) \ +static void gen_lve##name(DisasContext *ctx) \ + { \ + TCGv EA; \ + TCGv_ptr rs; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + if (size > 1) { \ + tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ + } \ + rs = gen_avr_ptr(rS(ctx->opcode)); \ + gen_helper_lve##name(cpu_env, rs, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(rs); \ + } + +#define GEN_VR_STVE(name, opc2, opc3, size) \ +static void gen_stve##name(DisasContext *ctx) \ + { \ + TCGv EA; \ + TCGv_ptr rs; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + if (size > 1) { \ + tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ + } \ + rs = gen_avr_ptr(rS(ctx->opcode)); \ + gen_helper_stve##name(cpu_env, rs, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(rs); \ + } + +GEN_VR_LDX(lvx, 0x07, 0x03); +/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ +GEN_VR_LDX(lvxl, 0x07, 0x0B); + +GEN_VR_LVE(bx, 0x07, 0x00, 1); +GEN_VR_LVE(hx, 0x07, 0x01, 2); +GEN_VR_LVE(wx, 0x07, 0x02, 4); + +GEN_VR_STX(svx, 0x07, 0x07); +/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ +GEN_VR_STX(svxl, 0x07, 0x0F); + +GEN_VR_STVE(bx, 0x07, 0x04, 1); +GEN_VR_STVE(hx, 0x07, 0x05, 2); +GEN_VR_STVE(wx, 0x07, 0x06, 4); + +static void gen_mfvscr(DisasContext *ctx) +{ + TCGv_i32 t; + TCGv_i64 avr; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + avr = tcg_temp_new_i64(); + tcg_gen_movi_i64(avr, 0); + set_avr64(rD(ctx->opcode), avr, true); + t = tcg_temp_new_i32(); + gen_helper_mfvscr(t, cpu_env); + tcg_gen_extu_i32_i64(avr, t); + set_avr64(rD(ctx->opcode), avr, false); + tcg_temp_free_i32(t); + tcg_temp_free_i64(avr); +} + +static void gen_mtvscr(DisasContext *ctx) +{ + TCGv_i32 val; + int bofs; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + + val = tcg_temp_new_i32(); + bofs = avr_full_offset(rB(ctx->opcode)); +#ifdef HOST_WORDS_BIGENDIAN + bofs += 3 * 4; +#endif + + tcg_gen_ld_i32(val, cpu_env, bofs); + gen_helper_mtvscr(cpu_env, val); + tcg_temp_free_i32(val); +} + +#define GEN_VX_VMUL10(name, add_cin, ret_carry) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + TCGv_i64 avr; \ + TCGv_i64 ten, z; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + avr = tcg_temp_new_i64(); \ + ten = tcg_const_i64(10); \ + z = tcg_const_i64(0); \ + \ + if (add_cin) { \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + get_avr64(avr, rB(ctx->opcode), false); \ + tcg_gen_andi_i64(t2, avr, 0xF); \ + tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ + } else { \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(avr, t2, avr, ten); \ + set_avr64(rD(ctx->opcode), avr, false); \ + } \ + \ + if (ret_carry) { \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ + set_avr64(rD(ctx->opcode), z, true); \ + } else { \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mul_i64(t0, avr, ten); \ + tcg_gen_add_i64(avr, t0, t2); \ + set_avr64(rD(ctx->opcode), avr, true); \ + } \ + \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ + tcg_temp_free_i64(avr); \ + tcg_temp_free_i64(ten); \ + tcg_temp_free_i64(z); \ +} \ + +GEN_VX_VMUL10(vmul10uq, 0, 0); +GEN_VX_VMUL10(vmul10euq, 1, 0); +GEN_VX_VMUL10(vmul10cuq, 0, 1); +GEN_VX_VMUL10(vmul10ecuq, 1, 1); + +#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + tcg_op(vece, \ + avr_full_offset(rD(ctx->opcode)), \ + avr_full_offset(rA(ctx->opcode)), \ + avr_full_offset(rB(ctx->opcode)), \ + 16, 16); \ +} + +/* Logical operations */ +GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); +GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); +GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); +GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); +GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20); +GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26); +GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22); +GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); + +#define GEN_VXFORM(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(rd, ra, rb); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ +} + +#define GEN_VXFORM_TRANS(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + trans_##name(ctx); \ +} + +#define GEN_VXFORM_ENV(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(cpu_env, rd, ra, rb); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ +} + +#define GEN_VXFORM3(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb, rc, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rc = gen_avr_ptr(rC(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(rd, ra, rb, rc); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rc); \ + tcg_temp_free_ptr(rd); \ +} + +/* + * Support for Altivec instruction pairs that use bit 31 (Rc) as + * an opcode bit. In general, these pairs come from different + * versions of the ISA, so we must also support a pair of flags for + * each instruction. + */ +#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) == 0) && \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ + gen_##name0(ctx); \ + } else if ((Rc(ctx->opcode) == 1) && \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ + gen_##name1(ctx); \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + +/* + * We use this macro if one instruction is realized with direct + * translation, and second one with helper. + */ +#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) == 0) && \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + trans_##name0(ctx); \ + } else if ((Rc(ctx->opcode) == 1) && \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ + gen_##name1(ctx); \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + +/* Adds support to provide invalid mask */ +#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \ + name1, flg1, flg2_1, inval1) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) == 0) && \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \ + !(ctx->opcode & inval0)) { \ + gen_##name0(ctx); \ + } else if ((Rc(ctx->opcode) == 1) && \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \ + !(ctx->opcode & inval1)) { \ + gen_##name1(ctx); \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + +#define GEN_VXFORM_HETRO(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_ptr rb; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \ + tcg_temp_free_ptr(rb); \ +} + +GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); +GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ + vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) +GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); +GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ + vmul10ecuq, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); +GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); +GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); +GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); +GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); +GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); +GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0); +GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1); +GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2); +GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3); +GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4); +GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5); +GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6); +GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7); +GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8); +GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9); +GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10); +GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11); +GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12); +GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13); +GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14); +GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15); +GEN_VXFORM(vavgub, 1, 16); +GEN_VXFORM(vabsdub, 1, 16); +GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \ + vabsdub, PPC_NONE, PPC2_ISA300) +GEN_VXFORM(vavguh, 1, 17); +GEN_VXFORM(vabsduh, 1, 17); +GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \ + vabsduh, PPC_NONE, PPC2_ISA300) +GEN_VXFORM(vavguw, 1, 18); +GEN_VXFORM(vabsduw, 1, 18); +GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \ + vabsduw, PPC_NONE, PPC2_ISA300) +GEN_VXFORM(vavgsb, 1, 20); +GEN_VXFORM(vavgsh, 1, 21); +GEN_VXFORM(vavgsw, 1, 22); +GEN_VXFORM(vmrghb, 6, 0); +GEN_VXFORM(vmrghh, 6, 1); +GEN_VXFORM(vmrghw, 6, 2); +GEN_VXFORM(vmrglb, 6, 4); +GEN_VXFORM(vmrglh, 6, 5); +GEN_VXFORM(vmrglw, 6, 6); + +static void trans_vmrgew(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VA = rA(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 avr = tcg_temp_new_i64(); + + get_avr64(avr, VB, true); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, true); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, true); + + get_avr64(avr, VB, false); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, false); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(avr); +} + +static void trans_vmrgow(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VA = rA(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 avr = tcg_temp_new_i64(); + + get_avr64(t0, VB, true); + get_avr64(t1, VA, true); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, true); + + get_avr64(t0, VB, false); + get_avr64(t1, VA, false); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(avr); +} + +/* + * lvsl VRT,RA,RB - Load Vector for Shift Left + * + * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. + * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. + * Bytes sh:sh+15 of X are placed into vD. + */ +static void trans_lvsl(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + TCGv_i64 result = tcg_temp_new_i64(); + TCGv_i64 sh = tcg_temp_new_i64(); + TCGv EA = tcg_temp_new(); + + /* Get sh(from description) by anding EA with 0xf. */ + gen_addr_reg_index(ctx, EA); + tcg_gen_extu_tl_i64(sh, EA); + tcg_gen_andi_i64(sh, sh, 0xfULL); + + /* + * Create bytes sh:sh+7 of X(from description) and place them in + * higher doubleword of vD. + */ + tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); + tcg_gen_addi_i64(result, sh, 0x0001020304050607ull); + set_avr64(VT, result, true); + /* + * Create bytes sh+8:sh+15 of X(from description) and place them in + * lower doubleword of vD. + */ + tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL); + set_avr64(VT, result, false); + + tcg_temp_free_i64(result); + tcg_temp_free_i64(sh); + tcg_temp_free(EA); +} + +/* + * lvsr VRT,RA,RB - Load Vector for Shift Right + * + * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. + * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. + * Bytes (16-sh):(31-sh) of X are placed into vD. + */ +static void trans_lvsr(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + TCGv_i64 result = tcg_temp_new_i64(); + TCGv_i64 sh = tcg_temp_new_i64(); + TCGv EA = tcg_temp_new(); + + + /* Get sh(from description) by anding EA with 0xf. */ + gen_addr_reg_index(ctx, EA); + tcg_gen_extu_tl_i64(sh, EA); + tcg_gen_andi_i64(sh, sh, 0xfULL); + + /* + * Create bytes (16-sh):(23-sh) of X(from description) and place them in + * higher doubleword of vD. + */ + tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); + tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh); + set_avr64(VT, result, true); + /* + * Create bytes (24-sh):(32-sh) of X(from description) and place them in + * lower doubleword of vD. + */ + tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh); + set_avr64(VT, result, false); + + tcg_temp_free_i64(result); + tcg_temp_free_i64(sh); + tcg_temp_free(EA); +} + +/* + * vsl VRT,VRA,VRB - Vector Shift Left + * + * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB. + * Lowest 3 bits in each byte element of register vB must be identical or + * result is undefined. + */ +static void trans_vsl(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VA = rA(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 avr = tcg_temp_new_i64(); + TCGv_i64 sh = tcg_temp_new_i64(); + TCGv_i64 carry = tcg_temp_new_i64(); + TCGv_i64 tmp = tcg_temp_new_i64(); + + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); + + /* + * Save highest 'sh' bits of lower doubleword element of vA in variable + * 'carry' and perform shift on lower doubleword. + */ + get_avr64(avr, VA, false); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shri_i64(carry, avr, 32); + tcg_gen_shr_i64(carry, carry, tmp); + tcg_gen_shl_i64(avr, avr, sh); + set_avr64(VT, avr, false); + + /* + * Perform shift on higher doubleword element of vA and replace lowest + * 'sh' bits with 'carry'. + */ + get_avr64(avr, VA, true); + tcg_gen_shl_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, true); + + tcg_temp_free_i64(avr); + tcg_temp_free_i64(sh); + tcg_temp_free_i64(carry); + tcg_temp_free_i64(tmp); +} + +/* + * vsr VRT,VRA,VRB - Vector Shift Right + * + * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB. + * Lowest 3 bits in each byte element of register vB must be identical or + * result is undefined. + */ +static void trans_vsr(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VA = rA(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 avr = tcg_temp_new_i64(); + TCGv_i64 sh = tcg_temp_new_i64(); + TCGv_i64 carry = tcg_temp_new_i64(); + TCGv_i64 tmp = tcg_temp_new_i64(); + + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); + + /* + * Save lowest 'sh' bits of higher doubleword element of vA in variable + * 'carry' and perform shift on higher doubleword. + */ + get_avr64(avr, VA, true); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shli_i64(carry, avr, 32); + tcg_gen_shl_i64(carry, carry, tmp); + tcg_gen_shr_i64(avr, avr, sh); + set_avr64(VT, avr, true); + /* + * Perform shift on lower doubleword element of vA and replace highest + * 'sh' bits with 'carry'. + */ + get_avr64(avr, VA, false); + tcg_gen_shr_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(avr); + tcg_temp_free_i64(sh); + tcg_temp_free_i64(carry); + tcg_temp_free_i64(tmp); +} + +/* + * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword + * + * All ith bits (i in range 1 to 8) of each byte of doubleword element in source + * register are concatenated and placed into ith byte of appropriate doubleword + * element in destination register. + * + * Following solution is done for both doubleword elements of source register + * in parallel, in order to reduce the number of instructions needed(that's why + * arrays are used): + * First, both doubleword elements of source register vB are placed in + * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for + * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of + * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with + * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables + * have to be shifted right for 7 and 8 places, respectively, in order to get + * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so + * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask... + * After first 8 iteration(first loop), all the first bits are in their final + * places, all second bits but second bit from eight byte are in their places... + * only 1 eight bit from eight byte is in it's place). In second loop we do all + * operations symmetrically, in order to get other half of bits in their final + * spots. Results for first and second doubleword elements are saved in + * result[0] and result[1] respectively. In the end those results are saved in + * appropriate doubleword element of destination register vD. + */ +static void trans_vgbbd(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 tmp = tcg_temp_new_i64(); + uint64_t mask = 0x8040201008040201ULL; + int i, j; + + TCGv_i64 result[2]; + result[0] = tcg_temp_new_i64(); + result[1] = tcg_temp_new_i64(); + TCGv_i64 avr[2]; + avr[0] = tcg_temp_new_i64(); + avr[1] = tcg_temp_new_i64(); + TCGv_i64 tcg_mask = tcg_temp_new_i64(); + + tcg_gen_movi_i64(tcg_mask, mask); + for (j = 0; j < 2; j++) { + get_avr64(avr[j], VB, j); + tcg_gen_and_i64(result[j], avr[j], tcg_mask); + } + for (i = 1; i < 8; i++) { + tcg_gen_movi_i64(tcg_mask, mask >> (i * 8)); + for (j = 0; j < 2; j++) { + tcg_gen_shri_i64(tmp, avr[j], i * 7); + tcg_gen_and_i64(tmp, tmp, tcg_mask); + tcg_gen_or_i64(result[j], result[j], tmp); + } + } + for (i = 1; i < 8; i++) { + tcg_gen_movi_i64(tcg_mask, mask << (i * 8)); + for (j = 0; j < 2; j++) { + tcg_gen_shli_i64(tmp, avr[j], i * 7); + tcg_gen_and_i64(tmp, tmp, tcg_mask); + tcg_gen_or_i64(result[j], result[j], tmp); + } + } + for (j = 0; j < 2; j++) { + set_avr64(VT, result[j], j); + } + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(tcg_mask); + tcg_temp_free_i64(result[0]); + tcg_temp_free_i64(result[1]); + tcg_temp_free_i64(avr[0]); + tcg_temp_free_i64(avr[1]); +} + +/* + * vclzw VRT,VRB - Vector Count Leading Zeros Word + * + * Counting the number of leading zero bits of each word element in source + * register and placing result in appropriate word element of destination + * register. + */ +static void trans_vclzw(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i32 tmp = tcg_temp_new_i32(); + int i; + + /* Perform count for every word element using tcg_gen_clzi_i32. */ + for (i = 0; i < 4; i++) { + tcg_gen_ld_i32(tmp, cpu_env, + offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4); + tcg_gen_clzi_i32(tmp, tmp, 32); + tcg_gen_st_i32(tmp, cpu_env, + offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); + } + + tcg_temp_free_i32(tmp); +} + +/* + * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword + * + * Counting the number of leading zero bits of each doubleword element in source + * register and placing result in appropriate doubleword element of destination + * register. + */ +static void trans_vclzd(DisasContext *ctx) +{ + int VT = rD(ctx->opcode); + int VB = rB(ctx->opcode); + TCGv_i64 avr = tcg_temp_new_i64(); + + /* high doubleword */ + get_avr64(avr, VB, true); + tcg_gen_clzi_i64(avr, avr, 64); + set_avr64(VT, avr, true); + + /* low doubleword */ + get_avr64(avr, VB, false); + tcg_gen_clzi_i64(avr, avr, 64); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(avr); +} + +GEN_VXFORM(vmuloub, 4, 0); +GEN_VXFORM(vmulouh, 4, 1); +GEN_VXFORM(vmulouw, 4, 2); +GEN_VXFORM(vmuluwm, 4, 2); +GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, + vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM(vmulosb, 4, 4); +GEN_VXFORM(vmulosh, 4, 5); +GEN_VXFORM(vmulosw, 4, 6); +GEN_VXFORM(vmuleub, 4, 8); +GEN_VXFORM(vmuleuh, 4, 9); +GEN_VXFORM(vmuleuw, 4, 10); +GEN_VXFORM(vmulesb, 4, 12); +GEN_VXFORM(vmulesh, 4, 13); +GEN_VXFORM(vmulesw, 4, 14); +GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4); +GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5); +GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6); +GEN_VXFORM(vrlwnm, 2, 6); +GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \ + vrlwnm, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23); +GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8); +GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9); +GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10); +GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27); +GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12); +GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13); +GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14); +GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15); +GEN_VXFORM(vsrv, 2, 28); +GEN_VXFORM(vslv, 2, 29); +GEN_VXFORM(vslo, 6, 16); +GEN_VXFORM(vsro, 6, 17); +GEN_VXFORM(vaddcuw, 0, 6); +GEN_VXFORM(vsubcuw, 0, 22); + +#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ +static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ + TCGv_vec sat, TCGv_vec a, \ + TCGv_vec b) \ +{ \ + TCGv_vec x = tcg_temp_new_vec_matching(t); \ + glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \ + glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \ + tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \ + tcg_gen_or_vec(VECE, sat, sat, x); \ + tcg_temp_free_vec(x); \ +} \ +static void glue(gen_, NAME)(DisasContext *ctx) \ +{ \ + static const TCGOpcode vecop_list[] = { \ + glue(glue(INDEX_op_, NORM), _vec), \ + glue(glue(INDEX_op_, SAT), _vec), \ + INDEX_op_cmp_vec, 0 \ + }; \ + static const GVecGen4 g = { \ + .fniv = glue(glue(gen_, NAME), _vec), \ + .fno = glue(gen_helper_, NAME), \ + .opt_opc = vecop_list, \ + .write_aofs = true, \ + .vece = VECE, \ + }; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \ + offsetof(CPUPPCState, vscr_sat), \ + avr_full_offset(rA(ctx->opcode)), \ + avr_full_offset(rB(ctx->opcode)), \ + 16, 16, &g); \ +} + +GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8); +GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \ + vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800) +GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9); +GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \ + vmul10euq, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10); +GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12); +GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13); +GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14); +GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24); +GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25); +GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26); +GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); +GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); +GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); +GEN_VXFORM(vadduqm, 0, 4); +GEN_VXFORM(vaddcuq, 0, 5); +GEN_VXFORM3(vaddeuqm, 30, 0); +GEN_VXFORM3(vaddecuq, 30, 0); +GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ + vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM(vsubuqm, 0, 20); +GEN_VXFORM(vsubcuq, 0, 21); +GEN_VXFORM3(vsubeuqm, 31, 0); +GEN_VXFORM3(vsubecuq, 31, 0); +GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ + vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); +GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); +GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); +GEN_VXFORM(vrlwmi, 2, 2); +GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ + vrlwmi, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); +GEN_VXFORM(vrldmi, 2, 3); +GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ + vrldmi, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_TRANS(vsl, 2, 7); +GEN_VXFORM(vrldnm, 2, 7); +GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \ + vrldnm, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_TRANS(vsr, 2, 11); +GEN_VXFORM_ENV(vpkuhum, 7, 0); +GEN_VXFORM_ENV(vpkuwum, 7, 1); +GEN_VXFORM_ENV(vpkudum, 7, 17); +GEN_VXFORM_ENV(vpkuhus, 7, 2); +GEN_VXFORM_ENV(vpkuwus, 7, 3); +GEN_VXFORM_ENV(vpkudus, 7, 19); +GEN_VXFORM_ENV(vpkshus, 7, 4); +GEN_VXFORM_ENV(vpkswus, 7, 5); +GEN_VXFORM_ENV(vpksdus, 7, 21); +GEN_VXFORM_ENV(vpkshss, 7, 6); +GEN_VXFORM_ENV(vpkswss, 7, 7); +GEN_VXFORM_ENV(vpksdss, 7, 23); +GEN_VXFORM(vpkpx, 7, 12); +GEN_VXFORM_ENV(vsum4ubs, 4, 24); +GEN_VXFORM_ENV(vsum4sbs, 4, 28); +GEN_VXFORM_ENV(vsum4shs, 4, 25); +GEN_VXFORM_ENV(vsum2sws, 4, 26); +GEN_VXFORM_ENV(vsumsws, 4, 30); +GEN_VXFORM_ENV(vaddfp, 5, 0); +GEN_VXFORM_ENV(vsubfp, 5, 1); +GEN_VXFORM_ENV(vmaxfp, 5, 16); +GEN_VXFORM_ENV(vminfp, 5, 17); +GEN_VXFORM_HETRO(vextublx, 6, 24) +GEN_VXFORM_HETRO(vextuhlx, 6, 25) +GEN_VXFORM_HETRO(vextuwlx, 6, 26) +GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, + vextuwlx, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_HETRO(vextubrx, 6, 28) +GEN_VXFORM_HETRO(vextuhrx, 6, 29) +GEN_VXFORM_HETRO(vextuwrx, 6, 30) +GEN_VXFORM_TRANS(lvsl, 6, 31) +GEN_VXFORM_TRANS(lvsr, 6, 32) +GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, + vextuwrx, PPC_NONE, PPC2_ISA300) + +#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr ra, rb, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##opname(cpu_env, rd, ra, rb); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +#define GEN_VXRFORM(name, opc2, opc3) \ + GEN_VXRFORM1(name, name, #name, opc2, opc3) \ + GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) + +/* + * Support for Altivec instructions that use bit 31 (Rc) as an opcode + * bit but also use bit 21 as an actual Rc bit. In general, thse pairs + * come from different versions of the ISA, so we must also support a + * pair of flags for each instruction. + */ +#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) == 0) && \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ + if (Rc21(ctx->opcode) == 0) { \ + gen_##name0(ctx); \ + } else { \ + gen_##name0##_(ctx); \ + } \ + } else if ((Rc(ctx->opcode) == 1) && \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ + if (Rc21(ctx->opcode) == 0) { \ + gen_##name1(ctx); \ + } else { \ + gen_##name1##_(ctx); \ + } \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + +GEN_VXRFORM(vcmpequb, 3, 0) +GEN_VXRFORM(vcmpequh, 3, 1) +GEN_VXRFORM(vcmpequw, 3, 2) +GEN_VXRFORM(vcmpequd, 3, 3) +GEN_VXRFORM(vcmpnezb, 3, 4) +GEN_VXRFORM(vcmpnezh, 3, 5) +GEN_VXRFORM(vcmpnezw, 3, 6) +GEN_VXRFORM(vcmpgtsb, 3, 12) +GEN_VXRFORM(vcmpgtsh, 3, 13) +GEN_VXRFORM(vcmpgtsw, 3, 14) +GEN_VXRFORM(vcmpgtsd, 3, 15) +GEN_VXRFORM(vcmpgtub, 3, 8) +GEN_VXRFORM(vcmpgtuh, 3, 9) +GEN_VXRFORM(vcmpgtuw, 3, 10) +GEN_VXRFORM(vcmpgtud, 3, 11) +GEN_VXRFORM(vcmpeqfp, 3, 3) +GEN_VXRFORM(vcmpgefp, 3, 7) +GEN_VXRFORM(vcmpgtfp, 3, 11) +GEN_VXRFORM(vcmpbfp, 3, 15) +GEN_VXRFORM(vcmpneb, 3, 0) +GEN_VXRFORM(vcmpneh, 3, 1) +GEN_VXRFORM(vcmpnew, 3, 2) + +GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \ + vcmpneb, PPC_NONE, PPC2_ISA300) +GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \ + vcmpneh, PPC_NONE, PPC2_ISA300) +GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \ + vcmpnew, PPC_NONE, PPC2_ISA300) +GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ + vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ + vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ + vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) + +static void gen_vsplti(DisasContext *ctx, int vece) +{ + int simm; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + + simm = SIMM5(ctx->opcode); + tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm); +} + +#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); } + +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12); +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13); +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14); + +#define GEN_VXFORM_NOA(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(rd, rb); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb, rd; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(cpu_env, rd, rb); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(rd, rb); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ + tcg_temp_free_ptr(rb); \ + } +GEN_VXFORM_NOA(vupkhsb, 7, 8); +GEN_VXFORM_NOA(vupkhsh, 7, 9); +GEN_VXFORM_NOA(vupkhsw, 7, 25); +GEN_VXFORM_NOA(vupklsb, 7, 10); +GEN_VXFORM_NOA(vupklsh, 7, 11); +GEN_VXFORM_NOA(vupklsw, 7, 27); +GEN_VXFORM_NOA(vupkhpx, 7, 13); +GEN_VXFORM_NOA(vupklpx, 7, 15); +GEN_VXFORM_NOA_ENV(vrefp, 5, 4); +GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); +GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); +GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); +GEN_VXFORM_NOA_ENV(vrfim, 5, 11); +GEN_VXFORM_NOA_ENV(vrfin, 5, 8); +GEN_VXFORM_NOA_ENV(vrfip, 5, 10); +GEN_VXFORM_NOA_ENV(vrfiz, 5, 9); +GEN_VXFORM_NOA(vprtybw, 1, 24); +GEN_VXFORM_NOA(vprtybd, 1, 24); +GEN_VXFORM_NOA(vprtybq, 1, 24); + +static void gen_vsplt(DisasContext *ctx, int vece) +{ + int uimm, dofs, bofs; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + + uimm = UIMM5(ctx->opcode); + bofs = avr_full_offset(rB(ctx->opcode)); + dofs = avr_full_offset(rD(ctx->opcode)); + + /* Experimental testing shows that hardware masks the immediate. */ + bofs += (uimm << vece) & 15; +#ifndef HOST_WORDS_BIGENDIAN + bofs ^= 15; + bofs &= ~((1 << vece) - 1); +#endif + + tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16); +} + +#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); } + +#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb, rd; \ + TCGv_i32 uimm; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(cpu_env, rd, rb, uimm); \ + tcg_temp_free_i32(uimm); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_ptr rb, rd; \ + uint8_t uimm = UIMM4(ctx->opcode); \ + TCGv_i32 t0; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + if (uimm > splat_max) { \ + uimm = 0; \ + } \ + t0 = tcg_temp_new_i32(); \ + tcg_gen_movi_i32(t0, uimm); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(rd, rb, t0); \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + } + +GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8); +GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9); +GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10); +GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15); +GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14); +GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12); +GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8); +GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15); +GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14); +GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12); +GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8); +GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); +GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); +GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); +GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); +GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE, + vextractub, PPC_NONE, PPC2_ISA300); +GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE, + vextractuh, PPC_NONE, PPC2_ISA300); +GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE, + vextractuw, PPC_NONE, PPC2_ISA300); +GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE, + vinsertb, PPC_NONE, PPC2_ISA300); +GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE, + vinserth, PPC_NONE, PPC2_ISA300); +GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE, + vinsertw, PPC_NONE, PPC2_ISA300); + +static void gen_vsldoi(DisasContext *ctx) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 sh; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + ra = gen_avr_ptr(rA(ctx->opcode)); + rb = gen_avr_ptr(rB(ctx->opcode)); + rd = gen_avr_ptr(rD(ctx->opcode)); + sh = tcg_const_i32(VSH(ctx->opcode)); + gen_helper_vsldoi(rd, ra, rb, sh); + tcg_temp_free_ptr(ra); + tcg_temp_free_ptr(rb); + tcg_temp_free_ptr(rd); + tcg_temp_free_i32(sh); +} + +#define GEN_VAFORM_PAIRED(name0, name1, opc2) \ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ + { \ + TCGv_ptr ra, rb, rc, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rc = gen_avr_ptr(rC(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + if (Rc(ctx->opcode)) { \ + gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ + } else { \ + gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ + } \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rc); \ + tcg_temp_free_ptr(rd); \ + } + +GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) + +static void gen_vmladduhm(DisasContext *ctx) +{ + TCGv_ptr ra, rb, rc, rd; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + ra = gen_avr_ptr(rA(ctx->opcode)); + rb = gen_avr_ptr(rB(ctx->opcode)); + rc = gen_avr_ptr(rC(ctx->opcode)); + rd = gen_avr_ptr(rD(ctx->opcode)); + gen_helper_vmladduhm(rd, ra, rb, rc); + tcg_temp_free_ptr(ra); + tcg_temp_free_ptr(rb); + tcg_temp_free_ptr(rc); + tcg_temp_free_ptr(rd); +} + +static void gen_vpermr(DisasContext *ctx) +{ + TCGv_ptr ra, rb, rc, rd; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + ra = gen_avr_ptr(rA(ctx->opcode)); + rb = gen_avr_ptr(rB(ctx->opcode)); + rc = gen_avr_ptr(rC(ctx->opcode)); + rd = gen_avr_ptr(rD(ctx->opcode)); + gen_helper_vpermr(cpu_env, rd, ra, rb, rc); + tcg_temp_free_ptr(ra); + tcg_temp_free_ptr(rb); + tcg_temp_free_ptr(rc); + tcg_temp_free_ptr(rd); +} + +GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) +GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) +GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) +GEN_VAFORM_PAIRED(vsel, vperm, 21) +GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) + +GEN_VXFORM_NOA(vclzb, 1, 28) +GEN_VXFORM_NOA(vclzh, 1, 29) +GEN_VXFORM_TRANS(vclzw, 1, 30) +GEN_VXFORM_TRANS(vclzd, 1, 31) +GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) +GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) +GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) +GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) +GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) +GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) +GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) +GEN_VXFORM_NOA_2(vctzb, 1, 24, 28) +GEN_VXFORM_NOA_2(vctzh, 1, 24, 29) +GEN_VXFORM_NOA_2(vctzw, 1, 24, 30) +GEN_VXFORM_NOA_2(vctzd, 1, 24, 31) +GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0) +GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1) +GEN_VXFORM_NOA(vpopcntb, 1, 28) +GEN_VXFORM_NOA(vpopcnth, 1, 29) +GEN_VXFORM_NOA(vpopcntw, 1, 30) +GEN_VXFORM_NOA(vpopcntd, 1, 31) +GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ + vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ + vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ + vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ + vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM(vbpermd, 6, 23); +GEN_VXFORM(vbpermq, 6, 21); +GEN_VXFORM_TRANS(vgbbd, 6, 20); +GEN_VXFORM(vpmsumb, 4, 16) +GEN_VXFORM(vpmsumh, 4, 17) +GEN_VXFORM(vpmsumw, 4, 18) +GEN_VXFORM(vpmsumd, 4, 19) + +#define GEN_BCD(op) \ +static void gen_##op(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb, rd; \ + TCGv_i32 ps; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + \ + ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ + \ + gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ + \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_i32(ps); \ +} + +#define GEN_BCD2(op) \ +static void gen_##op(DisasContext *ctx) \ +{ \ + TCGv_ptr rd, rb; \ + TCGv_i32 ps; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + \ + ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ + \ + gen_helper_##op(cpu_crf[6], rd, rb, ps); \ + \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_i32(ps); \ +} + +GEN_BCD(bcdadd) +GEN_BCD(bcdsub) +GEN_BCD2(bcdcfn) +GEN_BCD2(bcdctn) +GEN_BCD2(bcdcfz) +GEN_BCD2(bcdctz) +GEN_BCD2(bcdcfsq) +GEN_BCD2(bcdctsq) +GEN_BCD2(bcdsetsgn) +GEN_BCD(bcdcpsgn); +GEN_BCD(bcds); +GEN_BCD(bcdus); +GEN_BCD(bcdsr); +GEN_BCD(bcdtrunc); +GEN_BCD(bcdutrunc); + +static void gen_xpnd04_1(DisasContext *ctx) +{ + switch (opc4(ctx->opcode)) { + case 0: + gen_bcdctsq(ctx); + break; + case 2: + gen_bcdcfsq(ctx); + break; + case 4: + gen_bcdctz(ctx); + break; + case 5: + gen_bcdctn(ctx); + break; + case 6: + gen_bcdcfz(ctx); + break; + case 7: + gen_bcdcfn(ctx); + break; + case 31: + gen_bcdsetsgn(ctx); + break; + default: + gen_invalid(ctx); + break; + } +} + +static void gen_xpnd04_2(DisasContext *ctx) +{ + switch (opc4(ctx->opcode)) { + case 0: + gen_bcdctsq(ctx); + break; + case 2: + gen_bcdcfsq(ctx); + break; + case 4: + gen_bcdctz(ctx); + break; + case 6: + gen_bcdcfz(ctx); + break; + case 7: + gen_bcdcfn(ctx); + break; + case 31: + gen_bcdsetsgn(ctx); + break; + default: + gen_invalid(ctx); + break; + } +} + + +GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ + xpnd04_1, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ + xpnd04_2, PPC_NONE, PPC2_ISA300) + +GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ + bcdadd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ + bcdadd, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ + bcdsub, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ + bcdsub, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ + bcdcpsgn, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ + bcds, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ + bcdus, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \ + bcdtrunc, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \ + bcdtrunc, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \ + bcdutrunc, PPC_NONE, PPC2_ISA300) + + +static void gen_vsbox(DisasContext *ctx) +{ + TCGv_ptr ra, rd; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + ra = gen_avr_ptr(rA(ctx->opcode)); + rd = gen_avr_ptr(rD(ctx->opcode)); + gen_helper_vsbox(rd, ra); + tcg_temp_free_ptr(ra); + tcg_temp_free_ptr(rd); +} + +GEN_VXFORM(vcipher, 4, 20) +GEN_VXFORM(vcipherlast, 4, 20) +GEN_VXFORM(vncipher, 4, 21) +GEN_VXFORM(vncipherlast, 4, 21) + +GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, + vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) +GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, + vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) + +#define VSHASIGMA(op) \ +static void gen_##op(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rd; \ + TCGv_i32 st_six; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + st_six = tcg_const_i32(rB(ctx->opcode)); \ + gen_helper_##op(rd, ra, st_six); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rd); \ + tcg_temp_free_i32(st_six); \ +} + +VSHASIGMA(vshasigmaw) +VSHASIGMA(vshasigmad) + +GEN_VXFORM3(vpermxor, 22, 0xFF) +GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, + vpermxor, PPC_NONE, PPC2_ALTIVEC_207) + +#undef GEN_VR_LDX +#undef GEN_VR_STX +#undef GEN_VR_LVE +#undef GEN_VR_STVE + +#undef GEN_VX_LOGICAL +#undef GEN_VX_LOGICAL_207 +#undef GEN_VXFORM +#undef GEN_VXFORM_207 +#undef GEN_VXFORM_DUAL +#undef GEN_VXRFORM_DUAL +#undef GEN_VXRFORM1 +#undef GEN_VXRFORM +#undef GEN_VXFORM_VSPLTI +#undef GEN_VXFORM_NOA +#undef GEN_VXFORM_UIMM +#undef GEN_VAFORM_PAIRED + +#undef GEN_BCD2 diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c deleted file mode 100644 index de2fd136ff..0000000000 --- a/target/ppc/translate/vmx-impl.inc.c +++ /dev/null @@ -1,1571 +0,0 @@ -/* - * translate/vmx-impl.c - * - * Altivec/VMX translation - */ - -/*** Altivec vector extension ***/ -/* Altivec registers moves */ - -static inline TCGv_ptr gen_avr_ptr(int reg) -{ - TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); - return r; -} - -#define GEN_VR_LDX(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 avr; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - avr = tcg_temp_new_i64(); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - tcg_gen_andi_tl(EA, EA, ~0xf); \ - /* \ - * We only need to swap high and low halves. gen_qemu_ld64_i64 \ - * does necessary 64-bit byteswap already. \ - */ \ - if (ctx->le_mode) { \ - gen_qemu_ld64_i64(ctx, avr, EA); \ - set_avr64(rD(ctx->opcode), avr, false); \ - tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_ld64_i64(ctx, avr, EA); \ - set_avr64(rD(ctx->opcode), avr, true); \ - } else { \ - gen_qemu_ld64_i64(ctx, avr, EA); \ - set_avr64(rD(ctx->opcode), avr, true); \ - tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_ld64_i64(ctx, avr, EA); \ - set_avr64(rD(ctx->opcode), avr, false); \ - } \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(avr); \ -} - -#define GEN_VR_STX(name, opc2, opc3) \ -static void gen_st##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 avr; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - avr = tcg_temp_new_i64(); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - tcg_gen_andi_tl(EA, EA, ~0xf); \ - /* \ - * We only need to swap high and low halves. gen_qemu_st64_i64 \ - * does necessary 64-bit byteswap already. \ - */ \ - if (ctx->le_mode) { \ - get_avr64(avr, rD(ctx->opcode), false); \ - gen_qemu_st64_i64(ctx, avr, EA); \ - tcg_gen_addi_tl(EA, EA, 8); \ - get_avr64(avr, rD(ctx->opcode), true); \ - gen_qemu_st64_i64(ctx, avr, EA); \ - } else { \ - get_avr64(avr, rD(ctx->opcode), true); \ - gen_qemu_st64_i64(ctx, avr, EA); \ - tcg_gen_addi_tl(EA, EA, 8); \ - get_avr64(avr, rD(ctx->opcode), false); \ - gen_qemu_st64_i64(ctx, avr, EA); \ - } \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(avr); \ -} - -#define GEN_VR_LVE(name, opc2, opc3, size) \ -static void gen_lve##name(DisasContext *ctx) \ - { \ - TCGv EA; \ - TCGv_ptr rs; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - if (size > 1) { \ - tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ - } \ - rs = gen_avr_ptr(rS(ctx->opcode)); \ - gen_helper_lve##name(cpu_env, rs, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(rs); \ - } - -#define GEN_VR_STVE(name, opc2, opc3, size) \ -static void gen_stve##name(DisasContext *ctx) \ - { \ - TCGv EA; \ - TCGv_ptr rs; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - if (size > 1) { \ - tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ - } \ - rs = gen_avr_ptr(rS(ctx->opcode)); \ - gen_helper_stve##name(cpu_env, rs, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(rs); \ - } - -GEN_VR_LDX(lvx, 0x07, 0x03); -/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ -GEN_VR_LDX(lvxl, 0x07, 0x0B); - -GEN_VR_LVE(bx, 0x07, 0x00, 1); -GEN_VR_LVE(hx, 0x07, 0x01, 2); -GEN_VR_LVE(wx, 0x07, 0x02, 4); - -GEN_VR_STX(svx, 0x07, 0x07); -/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ -GEN_VR_STX(svxl, 0x07, 0x0F); - -GEN_VR_STVE(bx, 0x07, 0x04, 1); -GEN_VR_STVE(hx, 0x07, 0x05, 2); -GEN_VR_STVE(wx, 0x07, 0x06, 4); - -static void gen_mfvscr(DisasContext *ctx) -{ - TCGv_i32 t; - TCGv_i64 avr; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - avr = tcg_temp_new_i64(); - tcg_gen_movi_i64(avr, 0); - set_avr64(rD(ctx->opcode), avr, true); - t = tcg_temp_new_i32(); - gen_helper_mfvscr(t, cpu_env); - tcg_gen_extu_i32_i64(avr, t); - set_avr64(rD(ctx->opcode), avr, false); - tcg_temp_free_i32(t); - tcg_temp_free_i64(avr); -} - -static void gen_mtvscr(DisasContext *ctx) -{ - TCGv_i32 val; - int bofs; - - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - - val = tcg_temp_new_i32(); - bofs = avr_full_offset(rB(ctx->opcode)); -#ifdef HOST_WORDS_BIGENDIAN - bofs += 3 * 4; -#endif - - tcg_gen_ld_i32(val, cpu_env, bofs); - gen_helper_mtvscr(cpu_env, val); - tcg_temp_free_i32(val); -} - -#define GEN_VX_VMUL10(name, add_cin, ret_carry) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ - TCGv_i64 avr; \ - TCGv_i64 ten, z; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - t2 = tcg_temp_new_i64(); \ - avr = tcg_temp_new_i64(); \ - ten = tcg_const_i64(10); \ - z = tcg_const_i64(0); \ - \ - if (add_cin) { \ - get_avr64(avr, rA(ctx->opcode), false); \ - tcg_gen_mulu2_i64(t0, t1, avr, ten); \ - get_avr64(avr, rB(ctx->opcode), false); \ - tcg_gen_andi_i64(t2, avr, 0xF); \ - tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ - set_avr64(rD(ctx->opcode), avr, false); \ - } else { \ - get_avr64(avr, rA(ctx->opcode), false); \ - tcg_gen_mulu2_i64(avr, t2, avr, ten); \ - set_avr64(rD(ctx->opcode), avr, false); \ - } \ - \ - if (ret_carry) { \ - get_avr64(avr, rA(ctx->opcode), true); \ - tcg_gen_mulu2_i64(t0, t1, avr, ten); \ - tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ - set_avr64(rD(ctx->opcode), avr, false); \ - set_avr64(rD(ctx->opcode), z, true); \ - } else { \ - get_avr64(avr, rA(ctx->opcode), true); \ - tcg_gen_mul_i64(t0, avr, ten); \ - tcg_gen_add_i64(avr, t0, t2); \ - set_avr64(rD(ctx->opcode), avr, true); \ - } \ - \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ - tcg_temp_free_i64(avr); \ - tcg_temp_free_i64(ten); \ - tcg_temp_free_i64(z); \ -} \ - -GEN_VX_VMUL10(vmul10uq, 0, 0); -GEN_VX_VMUL10(vmul10euq, 1, 0); -GEN_VX_VMUL10(vmul10cuq, 0, 1); -GEN_VX_VMUL10(vmul10ecuq, 1, 1); - -#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - tcg_op(vece, \ - avr_full_offset(rD(ctx->opcode)), \ - avr_full_offset(rA(ctx->opcode)), \ - avr_full_offset(rB(ctx->opcode)), \ - 16, 16); \ -} - -/* Logical operations */ -GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); -GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); -GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); -GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); -GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20); -GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26); -GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22); -GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); - -#define GEN_VXFORM(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ -} - -#define GEN_VXFORM_TRANS(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - trans_##name(ctx); \ -} - -#define GEN_VXFORM_ENV(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ -} - -#define GEN_VXFORM3(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rc, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rc = gen_avr_ptr(rC(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(rd, ra, rb, rc); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rc); \ - tcg_temp_free_ptr(rd); \ -} - -/* - * Support for Altivec instruction pairs that use bit 31 (Rc) as - * an opcode bit. In general, these pairs come from different - * versions of the ISA, so we must also support a pair of flags for - * each instruction. - */ -#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ -{ \ - if ((Rc(ctx->opcode) == 0) && \ - ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ - gen_##name0(ctx); \ - } else if ((Rc(ctx->opcode) == 1) && \ - ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ - gen_##name1(ctx); \ - } else { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - } \ -} - -/* - * We use this macro if one instruction is realized with direct - * translation, and second one with helper. - */ -#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ -{ \ - if ((Rc(ctx->opcode) == 0) && \ - ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - trans_##name0(ctx); \ - } else if ((Rc(ctx->opcode) == 1) && \ - ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ - gen_##name1(ctx); \ - } else { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - } \ -} - -/* Adds support to provide invalid mask */ -#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \ - name1, flg1, flg2_1, inval1) \ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ -{ \ - if ((Rc(ctx->opcode) == 0) && \ - ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \ - !(ctx->opcode & inval0)) { \ - gen_##name0(ctx); \ - } else if ((Rc(ctx->opcode) == 1) && \ - ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \ - !(ctx->opcode & inval1)) { \ - gen_##name1(ctx); \ - } else { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - } \ -} - -#define GEN_VXFORM_HETRO(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_ptr rb; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \ - tcg_temp_free_ptr(rb); \ -} - -GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); -GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ - vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); -GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ - vmul10ecuq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); -GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); -GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); -GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); -GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); -GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); -GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0); -GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1); -GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2); -GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3); -GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4); -GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5); -GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6); -GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7); -GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8); -GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9); -GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10); -GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11); -GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12); -GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13); -GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14); -GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15); -GEN_VXFORM(vavgub, 1, 16); -GEN_VXFORM(vabsdub, 1, 16); -GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \ - vabsdub, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vavguh, 1, 17); -GEN_VXFORM(vabsduh, 1, 17); -GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \ - vabsduh, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vavguw, 1, 18); -GEN_VXFORM(vabsduw, 1, 18); -GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \ - vabsduw, PPC_NONE, PPC2_ISA300) -GEN_VXFORM(vavgsb, 1, 20); -GEN_VXFORM(vavgsh, 1, 21); -GEN_VXFORM(vavgsw, 1, 22); -GEN_VXFORM(vmrghb, 6, 0); -GEN_VXFORM(vmrghh, 6, 1); -GEN_VXFORM(vmrghw, 6, 2); -GEN_VXFORM(vmrglb, 6, 4); -GEN_VXFORM(vmrglh, 6, 5); -GEN_VXFORM(vmrglw, 6, 6); - -static void trans_vmrgew(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VA = rA(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv_i64 avr = tcg_temp_new_i64(); - - get_avr64(avr, VB, true); - tcg_gen_shri_i64(tmp, avr, 32); - get_avr64(avr, VA, true); - tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); - set_avr64(VT, avr, true); - - get_avr64(avr, VB, false); - tcg_gen_shri_i64(tmp, avr, 32); - get_avr64(avr, VA, false); - tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); - set_avr64(VT, avr, false); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(avr); -} - -static void trans_vmrgow(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VA = rA(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 avr = tcg_temp_new_i64(); - - get_avr64(t0, VB, true); - get_avr64(t1, VA, true); - tcg_gen_deposit_i64(avr, t0, t1, 32, 32); - set_avr64(VT, avr, true); - - get_avr64(t0, VB, false); - get_avr64(t1, VA, false); - tcg_gen_deposit_i64(avr, t0, t1, 32, 32); - set_avr64(VT, avr, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(avr); -} - -/* - * lvsl VRT,RA,RB - Load Vector for Shift Left - * - * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. - * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. - * Bytes sh:sh+15 of X are placed into vD. - */ -static void trans_lvsl(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - TCGv_i64 result = tcg_temp_new_i64(); - TCGv_i64 sh = tcg_temp_new_i64(); - TCGv EA = tcg_temp_new(); - - /* Get sh(from description) by anding EA with 0xf. */ - gen_addr_reg_index(ctx, EA); - tcg_gen_extu_tl_i64(sh, EA); - tcg_gen_andi_i64(sh, sh, 0xfULL); - - /* - * Create bytes sh:sh+7 of X(from description) and place them in - * higher doubleword of vD. - */ - tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); - tcg_gen_addi_i64(result, sh, 0x0001020304050607ull); - set_avr64(VT, result, true); - /* - * Create bytes sh+8:sh+15 of X(from description) and place them in - * lower doubleword of vD. - */ - tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL); - set_avr64(VT, result, false); - - tcg_temp_free_i64(result); - tcg_temp_free_i64(sh); - tcg_temp_free(EA); -} - -/* - * lvsr VRT,RA,RB - Load Vector for Shift Right - * - * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. - * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. - * Bytes (16-sh):(31-sh) of X are placed into vD. - */ -static void trans_lvsr(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - TCGv_i64 result = tcg_temp_new_i64(); - TCGv_i64 sh = tcg_temp_new_i64(); - TCGv EA = tcg_temp_new(); - - - /* Get sh(from description) by anding EA with 0xf. */ - gen_addr_reg_index(ctx, EA); - tcg_gen_extu_tl_i64(sh, EA); - tcg_gen_andi_i64(sh, sh, 0xfULL); - - /* - * Create bytes (16-sh):(23-sh) of X(from description) and place them in - * higher doubleword of vD. - */ - tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); - tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh); - set_avr64(VT, result, true); - /* - * Create bytes (24-sh):(32-sh) of X(from description) and place them in - * lower doubleword of vD. - */ - tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh); - set_avr64(VT, result, false); - - tcg_temp_free_i64(result); - tcg_temp_free_i64(sh); - tcg_temp_free(EA); -} - -/* - * vsl VRT,VRA,VRB - Vector Shift Left - * - * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB. - * Lowest 3 bits in each byte element of register vB must be identical or - * result is undefined. - */ -static void trans_vsl(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VA = rA(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 avr = tcg_temp_new_i64(); - TCGv_i64 sh = tcg_temp_new_i64(); - TCGv_i64 carry = tcg_temp_new_i64(); - TCGv_i64 tmp = tcg_temp_new_i64(); - - /* Place bits 125-127 of vB in 'sh'. */ - get_avr64(avr, VB, false); - tcg_gen_andi_i64(sh, avr, 0x07ULL); - - /* - * Save highest 'sh' bits of lower doubleword element of vA in variable - * 'carry' and perform shift on lower doubleword. - */ - get_avr64(avr, VA, false); - tcg_gen_subfi_i64(tmp, 32, sh); - tcg_gen_shri_i64(carry, avr, 32); - tcg_gen_shr_i64(carry, carry, tmp); - tcg_gen_shl_i64(avr, avr, sh); - set_avr64(VT, avr, false); - - /* - * Perform shift on higher doubleword element of vA and replace lowest - * 'sh' bits with 'carry'. - */ - get_avr64(avr, VA, true); - tcg_gen_shl_i64(avr, avr, sh); - tcg_gen_or_i64(avr, avr, carry); - set_avr64(VT, avr, true); - - tcg_temp_free_i64(avr); - tcg_temp_free_i64(sh); - tcg_temp_free_i64(carry); - tcg_temp_free_i64(tmp); -} - -/* - * vsr VRT,VRA,VRB - Vector Shift Right - * - * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB. - * Lowest 3 bits in each byte element of register vB must be identical or - * result is undefined. - */ -static void trans_vsr(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VA = rA(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 avr = tcg_temp_new_i64(); - TCGv_i64 sh = tcg_temp_new_i64(); - TCGv_i64 carry = tcg_temp_new_i64(); - TCGv_i64 tmp = tcg_temp_new_i64(); - - /* Place bits 125-127 of vB in 'sh'. */ - get_avr64(avr, VB, false); - tcg_gen_andi_i64(sh, avr, 0x07ULL); - - /* - * Save lowest 'sh' bits of higher doubleword element of vA in variable - * 'carry' and perform shift on higher doubleword. - */ - get_avr64(avr, VA, true); - tcg_gen_subfi_i64(tmp, 32, sh); - tcg_gen_shli_i64(carry, avr, 32); - tcg_gen_shl_i64(carry, carry, tmp); - tcg_gen_shr_i64(avr, avr, sh); - set_avr64(VT, avr, true); - /* - * Perform shift on lower doubleword element of vA and replace highest - * 'sh' bits with 'carry'. - */ - get_avr64(avr, VA, false); - tcg_gen_shr_i64(avr, avr, sh); - tcg_gen_or_i64(avr, avr, carry); - set_avr64(VT, avr, false); - - tcg_temp_free_i64(avr); - tcg_temp_free_i64(sh); - tcg_temp_free_i64(carry); - tcg_temp_free_i64(tmp); -} - -/* - * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword - * - * All ith bits (i in range 1 to 8) of each byte of doubleword element in source - * register are concatenated and placed into ith byte of appropriate doubleword - * element in destination register. - * - * Following solution is done for both doubleword elements of source register - * in parallel, in order to reduce the number of instructions needed(that's why - * arrays are used): - * First, both doubleword elements of source register vB are placed in - * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for - * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of - * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with - * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables - * have to be shifted right for 7 and 8 places, respectively, in order to get - * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so - * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask... - * After first 8 iteration(first loop), all the first bits are in their final - * places, all second bits but second bit from eight byte are in their places... - * only 1 eight bit from eight byte is in it's place). In second loop we do all - * operations symmetrically, in order to get other half of bits in their final - * spots. Results for first and second doubleword elements are saved in - * result[0] and result[1] respectively. In the end those results are saved in - * appropriate doubleword element of destination register vD. - */ -static void trans_vgbbd(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 tmp = tcg_temp_new_i64(); - uint64_t mask = 0x8040201008040201ULL; - int i, j; - - TCGv_i64 result[2]; - result[0] = tcg_temp_new_i64(); - result[1] = tcg_temp_new_i64(); - TCGv_i64 avr[2]; - avr[0] = tcg_temp_new_i64(); - avr[1] = tcg_temp_new_i64(); - TCGv_i64 tcg_mask = tcg_temp_new_i64(); - - tcg_gen_movi_i64(tcg_mask, mask); - for (j = 0; j < 2; j++) { - get_avr64(avr[j], VB, j); - tcg_gen_and_i64(result[j], avr[j], tcg_mask); - } - for (i = 1; i < 8; i++) { - tcg_gen_movi_i64(tcg_mask, mask >> (i * 8)); - for (j = 0; j < 2; j++) { - tcg_gen_shri_i64(tmp, avr[j], i * 7); - tcg_gen_and_i64(tmp, tmp, tcg_mask); - tcg_gen_or_i64(result[j], result[j], tmp); - } - } - for (i = 1; i < 8; i++) { - tcg_gen_movi_i64(tcg_mask, mask << (i * 8)); - for (j = 0; j < 2; j++) { - tcg_gen_shli_i64(tmp, avr[j], i * 7); - tcg_gen_and_i64(tmp, tmp, tcg_mask); - tcg_gen_or_i64(result[j], result[j], tmp); - } - } - for (j = 0; j < 2; j++) { - set_avr64(VT, result[j], j); - } - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tcg_mask); - tcg_temp_free_i64(result[0]); - tcg_temp_free_i64(result[1]); - tcg_temp_free_i64(avr[0]); - tcg_temp_free_i64(avr[1]); -} - -/* - * vclzw VRT,VRB - Vector Count Leading Zeros Word - * - * Counting the number of leading zero bits of each word element in source - * register and placing result in appropriate word element of destination - * register. - */ -static void trans_vclzw(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i32 tmp = tcg_temp_new_i32(); - int i; - - /* Perform count for every word element using tcg_gen_clzi_i32. */ - for (i = 0; i < 4; i++) { - tcg_gen_ld_i32(tmp, cpu_env, - offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4); - tcg_gen_clzi_i32(tmp, tmp, 32); - tcg_gen_st_i32(tmp, cpu_env, - offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); - } - - tcg_temp_free_i32(tmp); -} - -/* - * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword - * - * Counting the number of leading zero bits of each doubleword element in source - * register and placing result in appropriate doubleword element of destination - * register. - */ -static void trans_vclzd(DisasContext *ctx) -{ - int VT = rD(ctx->opcode); - int VB = rB(ctx->opcode); - TCGv_i64 avr = tcg_temp_new_i64(); - - /* high doubleword */ - get_avr64(avr, VB, true); - tcg_gen_clzi_i64(avr, avr, 64); - set_avr64(VT, avr, true); - - /* low doubleword */ - get_avr64(avr, VB, false); - tcg_gen_clzi_i64(avr, avr, 64); - set_avr64(VT, avr, false); - - tcg_temp_free_i64(avr); -} - -GEN_VXFORM(vmuloub, 4, 0); -GEN_VXFORM(vmulouh, 4, 1); -GEN_VXFORM(vmulouw, 4, 2); -GEN_VXFORM(vmuluwm, 4, 2); -GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, - vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM(vmulosb, 4, 4); -GEN_VXFORM(vmulosh, 4, 5); -GEN_VXFORM(vmulosw, 4, 6); -GEN_VXFORM(vmuleub, 4, 8); -GEN_VXFORM(vmuleuh, 4, 9); -GEN_VXFORM(vmuleuw, 4, 10); -GEN_VXFORM(vmulesb, 4, 12); -GEN_VXFORM(vmulesh, 4, 13); -GEN_VXFORM(vmulesw, 4, 14); -GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4); -GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5); -GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6); -GEN_VXFORM(vrlwnm, 2, 6); -GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \ - vrlwnm, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23); -GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8); -GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9); -GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10); -GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27); -GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12); -GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13); -GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14); -GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15); -GEN_VXFORM(vsrv, 2, 28); -GEN_VXFORM(vslv, 2, 29); -GEN_VXFORM(vslo, 6, 16); -GEN_VXFORM(vsro, 6, 17); -GEN_VXFORM(vaddcuw, 0, 6); -GEN_VXFORM(vsubcuw, 0, 22); - -#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ -static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ - TCGv_vec sat, TCGv_vec a, \ - TCGv_vec b) \ -{ \ - TCGv_vec x = tcg_temp_new_vec_matching(t); \ - glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \ - glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \ - tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \ - tcg_gen_or_vec(VECE, sat, sat, x); \ - tcg_temp_free_vec(x); \ -} \ -static void glue(gen_, NAME)(DisasContext *ctx) \ -{ \ - static const TCGOpcode vecop_list[] = { \ - glue(glue(INDEX_op_, NORM), _vec), \ - glue(glue(INDEX_op_, SAT), _vec), \ - INDEX_op_cmp_vec, 0 \ - }; \ - static const GVecGen4 g = { \ - .fniv = glue(glue(gen_, NAME), _vec), \ - .fno = glue(gen_helper_, NAME), \ - .opt_opc = vecop_list, \ - .write_aofs = true, \ - .vece = VECE, \ - }; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \ - offsetof(CPUPPCState, vscr_sat), \ - avr_full_offset(rA(ctx->opcode)), \ - avr_full_offset(rB(ctx->opcode)), \ - 16, 16, &g); \ -} - -GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8); -GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \ - vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9); -GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \ - vmul10euq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10); -GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12); -GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13); -GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14); -GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24); -GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25); -GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26); -GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); -GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); -GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); -GEN_VXFORM(vadduqm, 0, 4); -GEN_VXFORM(vaddcuq, 0, 5); -GEN_VXFORM3(vaddeuqm, 30, 0); -GEN_VXFORM3(vaddecuq, 30, 0); -GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ - vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM(vsubuqm, 0, 20); -GEN_VXFORM(vsubcuq, 0, 21); -GEN_VXFORM3(vsubeuqm, 31, 0); -GEN_VXFORM3(vsubecuq, 31, 0); -GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ - vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); -GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); -GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); -GEN_VXFORM(vrlwmi, 2, 2); -GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ - vrlwmi, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); -GEN_VXFORM(vrldmi, 2, 3); -GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ - vrldmi, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_TRANS(vsl, 2, 7); -GEN_VXFORM(vrldnm, 2, 7); -GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \ - vrldnm, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_TRANS(vsr, 2, 11); -GEN_VXFORM_ENV(vpkuhum, 7, 0); -GEN_VXFORM_ENV(vpkuwum, 7, 1); -GEN_VXFORM_ENV(vpkudum, 7, 17); -GEN_VXFORM_ENV(vpkuhus, 7, 2); -GEN_VXFORM_ENV(vpkuwus, 7, 3); -GEN_VXFORM_ENV(vpkudus, 7, 19); -GEN_VXFORM_ENV(vpkshus, 7, 4); -GEN_VXFORM_ENV(vpkswus, 7, 5); -GEN_VXFORM_ENV(vpksdus, 7, 21); -GEN_VXFORM_ENV(vpkshss, 7, 6); -GEN_VXFORM_ENV(vpkswss, 7, 7); -GEN_VXFORM_ENV(vpksdss, 7, 23); -GEN_VXFORM(vpkpx, 7, 12); -GEN_VXFORM_ENV(vsum4ubs, 4, 24); -GEN_VXFORM_ENV(vsum4sbs, 4, 28); -GEN_VXFORM_ENV(vsum4shs, 4, 25); -GEN_VXFORM_ENV(vsum2sws, 4, 26); -GEN_VXFORM_ENV(vsumsws, 4, 30); -GEN_VXFORM_ENV(vaddfp, 5, 0); -GEN_VXFORM_ENV(vsubfp, 5, 1); -GEN_VXFORM_ENV(vmaxfp, 5, 16); -GEN_VXFORM_ENV(vminfp, 5, 17); -GEN_VXFORM_HETRO(vextublx, 6, 24) -GEN_VXFORM_HETRO(vextuhlx, 6, 25) -GEN_VXFORM_HETRO(vextuwlx, 6, 26) -GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, - vextuwlx, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_HETRO(vextubrx, 6, 28) -GEN_VXFORM_HETRO(vextuhrx, 6, 29) -GEN_VXFORM_HETRO(vextuwrx, 6, 30) -GEN_VXFORM_TRANS(lvsl, 6, 31) -GEN_VXFORM_TRANS(lvsr, 6, 32) -GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, - vextuwrx, PPC_NONE, PPC2_ISA300) - -#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr ra, rb, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##opname(cpu_env, rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -#define GEN_VXRFORM(name, opc2, opc3) \ - GEN_VXRFORM1(name, name, #name, opc2, opc3) \ - GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) - -/* - * Support for Altivec instructions that use bit 31 (Rc) as an opcode - * bit but also use bit 21 as an actual Rc bit. In general, thse pairs - * come from different versions of the ISA, so we must also support a - * pair of flags for each instruction. - */ -#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ -{ \ - if ((Rc(ctx->opcode) == 0) && \ - ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ - if (Rc21(ctx->opcode) == 0) { \ - gen_##name0(ctx); \ - } else { \ - gen_##name0##_(ctx); \ - } \ - } else if ((Rc(ctx->opcode) == 1) && \ - ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ - if (Rc21(ctx->opcode) == 0) { \ - gen_##name1(ctx); \ - } else { \ - gen_##name1##_(ctx); \ - } \ - } else { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - } \ -} - -GEN_VXRFORM(vcmpequb, 3, 0) -GEN_VXRFORM(vcmpequh, 3, 1) -GEN_VXRFORM(vcmpequw, 3, 2) -GEN_VXRFORM(vcmpequd, 3, 3) -GEN_VXRFORM(vcmpnezb, 3, 4) -GEN_VXRFORM(vcmpnezh, 3, 5) -GEN_VXRFORM(vcmpnezw, 3, 6) -GEN_VXRFORM(vcmpgtsb, 3, 12) -GEN_VXRFORM(vcmpgtsh, 3, 13) -GEN_VXRFORM(vcmpgtsw, 3, 14) -GEN_VXRFORM(vcmpgtsd, 3, 15) -GEN_VXRFORM(vcmpgtub, 3, 8) -GEN_VXRFORM(vcmpgtuh, 3, 9) -GEN_VXRFORM(vcmpgtuw, 3, 10) -GEN_VXRFORM(vcmpgtud, 3, 11) -GEN_VXRFORM(vcmpeqfp, 3, 3) -GEN_VXRFORM(vcmpgefp, 3, 7) -GEN_VXRFORM(vcmpgtfp, 3, 11) -GEN_VXRFORM(vcmpbfp, 3, 15) -GEN_VXRFORM(vcmpneb, 3, 0) -GEN_VXRFORM(vcmpneh, 3, 1) -GEN_VXRFORM(vcmpnew, 3, 2) - -GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \ - vcmpneb, PPC_NONE, PPC2_ISA300) -GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \ - vcmpneh, PPC_NONE, PPC2_ISA300) -GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \ - vcmpnew, PPC_NONE, PPC2_ISA300) -GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ - vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ - vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ - vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) - -static void gen_vsplti(DisasContext *ctx, int vece) -{ - int simm; - - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - - simm = SIMM5(ctx->opcode); - tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm); -} - -#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); } - -GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12); -GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13); -GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14); - -#define GEN_VXFORM_NOA(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb, rd; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -#define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ - tcg_temp_free_ptr(rb); \ - } -GEN_VXFORM_NOA(vupkhsb, 7, 8); -GEN_VXFORM_NOA(vupkhsh, 7, 9); -GEN_VXFORM_NOA(vupkhsw, 7, 25); -GEN_VXFORM_NOA(vupklsb, 7, 10); -GEN_VXFORM_NOA(vupklsh, 7, 11); -GEN_VXFORM_NOA(vupklsw, 7, 27); -GEN_VXFORM_NOA(vupkhpx, 7, 13); -GEN_VXFORM_NOA(vupklpx, 7, 15); -GEN_VXFORM_NOA_ENV(vrefp, 5, 4); -GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); -GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); -GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); -GEN_VXFORM_NOA_ENV(vrfim, 5, 11); -GEN_VXFORM_NOA_ENV(vrfin, 5, 8); -GEN_VXFORM_NOA_ENV(vrfip, 5, 10); -GEN_VXFORM_NOA_ENV(vrfiz, 5, 9); -GEN_VXFORM_NOA(vprtybw, 1, 24); -GEN_VXFORM_NOA(vprtybd, 1, 24); -GEN_VXFORM_NOA(vprtybq, 1, 24); - -static void gen_vsplt(DisasContext *ctx, int vece) -{ - int uimm, dofs, bofs; - - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - - uimm = UIMM5(ctx->opcode); - bofs = avr_full_offset(rB(ctx->opcode)); - dofs = avr_full_offset(rD(ctx->opcode)); - - /* Experimental testing shows that hardware masks the immediate. */ - bofs += (uimm << vece) & 15; -#ifndef HOST_WORDS_BIGENDIAN - bofs ^= 15; - bofs &= ~((1 << vece) - 1); -#endif - - tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16); -} - -#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); } - -#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb, rd; \ - TCGv_i32 uimm; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, rb, uimm); \ - tcg_temp_free_i32(uimm); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_ptr rb, rd; \ - uint8_t uimm = UIMM4(ctx->opcode); \ - TCGv_i32 t0; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - if (uimm > splat_max) { \ - uimm = 0; \ - } \ - t0 = tcg_temp_new_i32(); \ - tcg_gen_movi_i32(t0, uimm); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(rd, rb, t0); \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - } - -GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8); -GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9); -GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10); -GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15); -GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14); -GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12); -GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8); -GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15); -GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14); -GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12); -GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8); -GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); -GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); -GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); -GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); -GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE, - vextractub, PPC_NONE, PPC2_ISA300); -GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE, - vextractuh, PPC_NONE, PPC2_ISA300); -GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE, - vextractuw, PPC_NONE, PPC2_ISA300); -GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE, - vinsertb, PPC_NONE, PPC2_ISA300); -GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE, - vinserth, PPC_NONE, PPC2_ISA300); -GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE, - vinsertw, PPC_NONE, PPC2_ISA300); - -static void gen_vsldoi(DisasContext *ctx) -{ - TCGv_ptr ra, rb, rd; - TCGv_i32 sh; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rb = gen_avr_ptr(rB(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - sh = tcg_const_i32(VSH(ctx->opcode)); - gen_helper_vsldoi(rd, ra, rb, sh); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rd); - tcg_temp_free_i32(sh); -} - -#define GEN_VAFORM_PAIRED(name0, name1, opc2) \ -static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ - { \ - TCGv_ptr ra, rb, rc, rd; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rc = gen_avr_ptr(rC(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - if (Rc(ctx->opcode)) { \ - gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ - } else { \ - gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ - } \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rc); \ - tcg_temp_free_ptr(rd); \ - } - -GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) - -static void gen_vmladduhm(DisasContext *ctx) -{ - TCGv_ptr ra, rb, rc, rd; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rb = gen_avr_ptr(rB(ctx->opcode)); - rc = gen_avr_ptr(rC(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - gen_helper_vmladduhm(rd, ra, rb, rc); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rc); - tcg_temp_free_ptr(rd); -} - -static void gen_vpermr(DisasContext *ctx) -{ - TCGv_ptr ra, rb, rc, rd; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rb = gen_avr_ptr(rB(ctx->opcode)); - rc = gen_avr_ptr(rC(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - gen_helper_vpermr(cpu_env, rd, ra, rb, rc); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rc); - tcg_temp_free_ptr(rd); -} - -GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) -GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) -GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) -GEN_VAFORM_PAIRED(vsel, vperm, 21) -GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) - -GEN_VXFORM_NOA(vclzb, 1, 28) -GEN_VXFORM_NOA(vclzh, 1, 29) -GEN_VXFORM_TRANS(vclzw, 1, 30) -GEN_VXFORM_TRANS(vclzd, 1, 31) -GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) -GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) -GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) -GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) -GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) -GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) -GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) -GEN_VXFORM_NOA_2(vctzb, 1, 24, 28) -GEN_VXFORM_NOA_2(vctzh, 1, 24, 29) -GEN_VXFORM_NOA_2(vctzw, 1, 24, 30) -GEN_VXFORM_NOA_2(vctzd, 1, 24, 31) -GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0) -GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1) -GEN_VXFORM_NOA(vpopcntb, 1, 28) -GEN_VXFORM_NOA(vpopcnth, 1, 29) -GEN_VXFORM_NOA(vpopcntw, 1, 30) -GEN_VXFORM_NOA(vpopcntd, 1, 31) -GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ - vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM(vbpermd, 6, 23); -GEN_VXFORM(vbpermq, 6, 21); -GEN_VXFORM_TRANS(vgbbd, 6, 20); -GEN_VXFORM(vpmsumb, 4, 16) -GEN_VXFORM(vpmsumh, 4, 17) -GEN_VXFORM(vpmsumw, 4, 18) -GEN_VXFORM(vpmsumd, 4, 19) - -#define GEN_BCD(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ - \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(ps); \ -} - -#define GEN_BCD2(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr rd, rb; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - rb = gen_avr_ptr(rB(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, rb, ps); \ - \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(ps); \ -} - -GEN_BCD(bcdadd) -GEN_BCD(bcdsub) -GEN_BCD2(bcdcfn) -GEN_BCD2(bcdctn) -GEN_BCD2(bcdcfz) -GEN_BCD2(bcdctz) -GEN_BCD2(bcdcfsq) -GEN_BCD2(bcdctsq) -GEN_BCD2(bcdsetsgn) -GEN_BCD(bcdcpsgn); -GEN_BCD(bcds); -GEN_BCD(bcdus); -GEN_BCD(bcdsr); -GEN_BCD(bcdtrunc); -GEN_BCD(bcdutrunc); - -static void gen_xpnd04_1(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 5: - gen_bcdctn(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } -} - -static void gen_xpnd04_2(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } -} - - -GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ - xpnd04_1, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ - xpnd04_2, PPC_NONE, PPC2_ISA300) - -GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ - bcdadd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ - bcdadd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ - bcdsub, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ - bcdsub, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ - bcdcpsgn, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ - bcds, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ - bcdus, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \ - bcdtrunc, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \ - bcdtrunc, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \ - bcdutrunc, PPC_NONE, PPC2_ISA300) - - -static void gen_vsbox(DisasContext *ctx) -{ - TCGv_ptr ra, rd; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - gen_helper_vsbox(rd, ra); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rd); -} - -GEN_VXFORM(vcipher, 4, 20) -GEN_VXFORM(vcipherlast, 4, 20) -GEN_VXFORM(vncipher, 4, 21) -GEN_VXFORM(vncipherlast, 4, 21) - -GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, - vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, - vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) - -#define VSHASIGMA(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rd; \ - TCGv_i32 st_six; \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - ra = gen_avr_ptr(rA(ctx->opcode)); \ - rd = gen_avr_ptr(rD(ctx->opcode)); \ - st_six = tcg_const_i32(rB(ctx->opcode)); \ - gen_helper_##op(rd, ra, st_six); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(st_six); \ -} - -VSHASIGMA(vshasigmaw) -VSHASIGMA(vshasigmad) - -GEN_VXFORM3(vpermxor, 22, 0xFF) -GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, - vpermxor, PPC_NONE, PPC2_ALTIVEC_207) - -#undef GEN_VR_LDX -#undef GEN_VR_STX -#undef GEN_VR_LVE -#undef GEN_VR_STVE - -#undef GEN_VX_LOGICAL -#undef GEN_VX_LOGICAL_207 -#undef GEN_VXFORM -#undef GEN_VXFORM_207 -#undef GEN_VXFORM_DUAL -#undef GEN_VXRFORM_DUAL -#undef GEN_VXRFORM1 -#undef GEN_VXRFORM -#undef GEN_VXFORM_VSPLTI -#undef GEN_VXFORM_NOA -#undef GEN_VXFORM_UIMM -#undef GEN_VAFORM_PAIRED - -#undef GEN_BCD2 diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc new file mode 100644 index 0000000000..84e05fb827 --- /dev/null +++ b/target/ppc/translate/vmx-ops.c.inc @@ -0,0 +1,301 @@ +#define GEN_VR_LDX(name, opc2, opc3) \ +GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) +#define GEN_VR_STX(name, opc2, opc3) \ +GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) +#define GEN_VR_LVE(name, opc2, opc3) \ + GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) +#define GEN_VR_STVE(name, opc2, opc3) \ + GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) +GEN_VR_LDX(lvx, 0x07, 0x03), +GEN_VR_LDX(lvxl, 0x07, 0x0B), +GEN_VR_LVE(bx, 0x07, 0x00), +GEN_VR_LVE(hx, 0x07, 0x01), +GEN_VR_LVE(wx, 0x07, 0x02), +GEN_VR_STX(svx, 0x07, 0x07), +GEN_VR_STX(svxl, 0x07, 0x0F), +GEN_VR_STVE(bx, 0x07, 0x04), +GEN_VR_STVE(hx, 0x07, 0x05), +GEN_VR_STVE(wx, 0x07, 0x06), + +#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) + +#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) + +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), +GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26), +GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22), +GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21), + +#define GEN_VXFORM(name, opc2, opc3) \ +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) + +#define GEN_VXFORM_207(name, opc2, opc3) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) + +#define GEN_VXFORM_300(name, opc2, opc3) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300) + +#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) + +#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \ +GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \ + PPC2_ISA300) + +#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ +GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) + +#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ +GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ +GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), + +GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vadduwm, 0, 2), +GEN_VXFORM_207(vaddudm, 0, 3), +GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), +GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_300(bcds, 0, 27), +GEN_VXFORM(vmaxub, 1, 0), +GEN_VXFORM(vmaxuh, 1, 1), +GEN_VXFORM(vmaxuw, 1, 2), +GEN_VXFORM_207(vmaxud, 1, 3), +GEN_VXFORM(vmaxsb, 1, 4), +GEN_VXFORM(vmaxsh, 1, 5), +GEN_VXFORM(vmaxsw, 1, 6), +GEN_VXFORM_207(vmaxsd, 1, 7), +GEN_VXFORM(vminub, 1, 8), +GEN_VXFORM(vminuh, 1, 9), +GEN_VXFORM(vminuw, 1, 10), +GEN_VXFORM_207(vminud, 1, 11), +GEN_VXFORM(vminsb, 1, 12), +GEN_VXFORM(vminsh, 1, 13), +GEN_VXFORM(vminsw, 1, 14), +GEN_VXFORM_207(vminsd, 1, 15), +GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vavgsb, 1, 20), +GEN_VXFORM(vavgsh, 1, 21), +GEN_VXFORM(vavgsw, 1, 22), +GEN_VXFORM(vmrghb, 6, 0), +GEN_VXFORM(vmrghh, 6, 1), +GEN_VXFORM(vmrghw, 6, 2), +GEN_VXFORM(vmrglb, 6, 4), +GEN_VXFORM(vmrglh, 6, 5), +GEN_VXFORM(vmrglw, 6, 6), +GEN_VXFORM_300(vextublx, 6, 24), +GEN_VXFORM_300(vextuhlx, 6, 25), +GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_300(vextubrx, 6, 28), +GEN_VXFORM_300(vextuhrx, 6, 29), +GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM(vmuloub, 4, 0), +GEN_VXFORM(vmulouh, 4, 1), +GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vmulosb, 4, 4), +GEN_VXFORM(vmulosh, 4, 5), +GEN_VXFORM_207(vmulosw, 4, 6), +GEN_VXFORM(vmuleub, 4, 8), +GEN_VXFORM(vmuleuh, 4, 9), +GEN_VXFORM_207(vmuleuw, 4, 10), +GEN_VXFORM(vmulesb, 4, 12), +GEN_VXFORM(vmulesh, 4, 13), +GEN_VXFORM_207(vmulesw, 4, 14), +GEN_VXFORM(vslb, 2, 4), +GEN_VXFORM(vslh, 2, 5), +GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_207(vsld, 2, 23), +GEN_VXFORM(vsrb, 2, 8), +GEN_VXFORM(vsrh, 2, 9), +GEN_VXFORM(vsrw, 2, 10), +GEN_VXFORM_207(vsrd, 2, 27), +GEN_VXFORM(vsrab, 2, 12), +GEN_VXFORM(vsrah, 2, 13), +GEN_VXFORM(vsraw, 2, 14), +GEN_VXFORM_207(vsrad, 2, 15), +GEN_VXFORM_300(vsrv, 2, 28), +GEN_VXFORM_300(vslv, 2, 29), +GEN_VXFORM(vslo, 6, 16), +GEN_VXFORM(vsro, 6, 17), +GEN_VXFORM(vaddcuw, 0, 6), +GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300), + +GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_300(bcdsr, 0, 23), +GEN_VXFORM_300(bcdsr, 0, 31), +GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vadduws, 0, 10), +GEN_VXFORM(vaddsbs, 0, 12), +GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vaddsws, 0, 14), +GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vsubuws, 0, 26), +GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300), +GEN_VXFORM(vsubshs, 0, 29), +GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_207(vadduqm, 0, 4), +GEN_VXFORM_207(vaddcuq, 0, 5), +GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM(vrlb, 2, 0), +GEN_VXFORM(vrlh, 2, 1), +GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM(vsr, 2, 11), +GEN_VXFORM(vpkuhum, 7, 0), +GEN_VXFORM(vpkuwum, 7, 1), +GEN_VXFORM_207(vpkudum, 7, 17), +GEN_VXFORM(vpkuhus, 7, 2), +GEN_VXFORM(vpkuwus, 7, 3), +GEN_VXFORM_207(vpkudus, 7, 19), +GEN_VXFORM(vpkshus, 7, 4), +GEN_VXFORM(vpkswus, 7, 5), +GEN_VXFORM_207(vpksdus, 7, 21), +GEN_VXFORM(vpkshss, 7, 6), +GEN_VXFORM(vpkswss, 7, 7), +GEN_VXFORM_207(vpksdss, 7, 23), +GEN_VXFORM(vpkpx, 7, 12), +GEN_VXFORM(vsum4ubs, 4, 24), +GEN_VXFORM(vsum4sbs, 4, 28), +GEN_VXFORM(vsum4shs, 4, 25), +GEN_VXFORM(vsum2sws, 4, 26), +GEN_VXFORM(vsumsws, 4, 30), +GEN_VXFORM(vaddfp, 5, 0), +GEN_VXFORM(vsubfp, 5, 1), +GEN_VXFORM(vmaxfp, 5, 16), +GEN_VXFORM(vminfp, 5, 17), + +#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ + GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), +#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \ +GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300), +#define GEN_VXRFORM(name, opc2, opc3) \ + GEN_VXRFORM1(name, name, #name, opc2, opc3) \ + GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) +#define GEN_VXRFORM_300(name, opc2, opc3) \ + GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \ + GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) + +GEN_VXRFORM_300(vcmpnezb, 3, 4) +GEN_VXRFORM_300(vcmpnezh, 3, 5) +GEN_VXRFORM_300(vcmpnezw, 3, 6) +GEN_VXRFORM(vcmpgtsb, 3, 12) +GEN_VXRFORM(vcmpgtsh, 3, 13) +GEN_VXRFORM(vcmpgtsw, 3, 14) +GEN_VXRFORM(vcmpgtub, 3, 8) +GEN_VXRFORM(vcmpgtuh, 3, 9) +GEN_VXRFORM(vcmpgtuw, 3, 10) +GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM(vcmpgefp, 3, 7) +GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE) +GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE) + +#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \ +GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \ + PPC_NONE) +GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000), +GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000, + PPC_ALTIVEC), +GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000), +GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06), +GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07), +GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10), +GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11), +GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18), +GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19), +GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A), +GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C), +GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D), +GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E), +GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F), +GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0), +GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1), +GEN_VXFORM_300(vpermr, 0x1D, 0xFF), + +#define GEN_VXFORM_NOA(name, opc2, opc3) \ + GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) +GEN_VXFORM_NOA(vupkhsb, 7, 8), +GEN_VXFORM_NOA(vupkhsh, 7, 9), +GEN_VXFORM_207(vupkhsw, 7, 25), +GEN_VXFORM_NOA(vupklsb, 7, 10), +GEN_VXFORM_NOA(vupklsh, 7, 11), +GEN_VXFORM_207(vupklsw, 7, 27), +GEN_VXFORM_NOA(vupkhpx, 7, 13), +GEN_VXFORM_NOA(vupklpx, 7, 15), +GEN_VXFORM_NOA(vrefp, 5, 4), +GEN_VXFORM_NOA(vrsqrtefp, 5, 5), +GEN_VXFORM_NOA(vexptefp, 5, 6), +GEN_VXFORM_NOA(vlogefp, 5, 7), +GEN_VXFORM_NOA(vrfim, 5, 11), +GEN_VXFORM_NOA(vrfin, 5, 8), +GEN_VXFORM_NOA(vrfip, 5, 10), +GEN_VXFORM_NOA(vrfiz, 5, 9), + +#define GEN_VXFORM_UIMM(name, opc2, opc3) \ + GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) +GEN_VXFORM_UIMM(vcfux, 5, 12), +GEN_VXFORM_UIMM(vcfsx, 5, 13), +GEN_VXFORM_UIMM(vctuxs, 5, 14), +GEN_VXFORM_UIMM(vctsxs, 5, 15), + + +#define GEN_VAFORM_PAIRED(name0, name1, opc2) \ + GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) +GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), +GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), +GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), +GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), +GEN_VAFORM_PAIRED(vsel, vperm, 21), +GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), + +GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), + +GEN_VXFORM_300(vbpermd, 6, 23), +GEN_VXFORM_207(vbpermq, 6, 21), +GEN_VXFORM_207(vgbbd, 6, 20), +GEN_VXFORM_207(vpmsumb, 4, 16), +GEN_VXFORM_207(vpmsumh, 4, 17), +GEN_VXFORM_207(vpmsumw, 4, 18), +GEN_VXFORM_207(vpmsumd, 4, 19), + +GEN_VXFORM_207(vsbox, 4, 23), + +GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), + +GEN_VXFORM_207(vshasigmaw, 1, 26), +GEN_VXFORM_207(vshasigmad, 1, 27), + +GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c deleted file mode 100644 index 84e05fb827..0000000000 --- a/target/ppc/translate/vmx-ops.inc.c +++ /dev/null @@ -1,301 +0,0 @@ -#define GEN_VR_LDX(name, opc2, opc3) \ -GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) -#define GEN_VR_STX(name, opc2, opc3) \ -GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) -#define GEN_VR_LVE(name, opc2, opc3) \ - GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) -#define GEN_VR_STVE(name, opc2, opc3) \ - GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) -GEN_VR_LDX(lvx, 0x07, 0x03), -GEN_VR_LDX(lvxl, 0x07, 0x0B), -GEN_VR_LVE(bx, 0x07, 0x00), -GEN_VR_LVE(hx, 0x07, 0x01), -GEN_VR_LVE(wx, 0x07, 0x02), -GEN_VR_STX(svx, 0x07, 0x07), -GEN_VR_STX(svxl, 0x07, 0x0F), -GEN_VR_STVE(bx, 0x07, 0x04), -GEN_VR_STVE(hx, 0x07, 0x05), -GEN_VR_STVE(wx, 0x07, 0x06), - -#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ -GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) - -#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) - -GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), -GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), -GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), -GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), -GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), -GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26), -GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22), -GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21), - -#define GEN_VXFORM(name, opc2, opc3) \ -GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) - -#define GEN_VXFORM_207(name, opc2, opc3) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) - -#define GEN_VXFORM_300(name, opc2, opc3) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300) - -#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \ -GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) - -#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \ -GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \ - PPC2_ISA300) - -#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ -GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) - -#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ -GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ -GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), - -GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vadduwm, 0, 2), -GEN_VXFORM_207(vaddudm, 0, 3), -GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_300(bcds, 0, 27), -GEN_VXFORM(vmaxub, 1, 0), -GEN_VXFORM(vmaxuh, 1, 1), -GEN_VXFORM(vmaxuw, 1, 2), -GEN_VXFORM_207(vmaxud, 1, 3), -GEN_VXFORM(vmaxsb, 1, 4), -GEN_VXFORM(vmaxsh, 1, 5), -GEN_VXFORM(vmaxsw, 1, 6), -GEN_VXFORM_207(vmaxsd, 1, 7), -GEN_VXFORM(vminub, 1, 8), -GEN_VXFORM(vminuh, 1, 9), -GEN_VXFORM(vminuw, 1, 10), -GEN_VXFORM_207(vminud, 1, 11), -GEN_VXFORM(vminsb, 1, 12), -GEN_VXFORM(vminsh, 1, 13), -GEN_VXFORM(vminsw, 1, 14), -GEN_VXFORM_207(vminsd, 1, 15), -GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vavgsb, 1, 20), -GEN_VXFORM(vavgsh, 1, 21), -GEN_VXFORM(vavgsw, 1, 22), -GEN_VXFORM(vmrghb, 6, 0), -GEN_VXFORM(vmrghh, 6, 1), -GEN_VXFORM(vmrghw, 6, 2), -GEN_VXFORM(vmrglb, 6, 4), -GEN_VXFORM(vmrglh, 6, 5), -GEN_VXFORM(vmrglw, 6, 6), -GEN_VXFORM_300(vextublx, 6, 24), -GEN_VXFORM_300(vextuhlx, 6, 25), -GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_300(vextubrx, 6, 28), -GEN_VXFORM_300(vextuhrx, 6, 29), -GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM(vmuloub, 4, 0), -GEN_VXFORM(vmulouh, 4, 1), -GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vmulosb, 4, 4), -GEN_VXFORM(vmulosh, 4, 5), -GEN_VXFORM_207(vmulosw, 4, 6), -GEN_VXFORM(vmuleub, 4, 8), -GEN_VXFORM(vmuleuh, 4, 9), -GEN_VXFORM_207(vmuleuw, 4, 10), -GEN_VXFORM(vmulesb, 4, 12), -GEN_VXFORM(vmulesh, 4, 13), -GEN_VXFORM_207(vmulesw, 4, 14), -GEN_VXFORM(vslb, 2, 4), -GEN_VXFORM(vslh, 2, 5), -GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_207(vsld, 2, 23), -GEN_VXFORM(vsrb, 2, 8), -GEN_VXFORM(vsrh, 2, 9), -GEN_VXFORM(vsrw, 2, 10), -GEN_VXFORM_207(vsrd, 2, 27), -GEN_VXFORM(vsrab, 2, 12), -GEN_VXFORM(vsrah, 2, 13), -GEN_VXFORM(vsraw, 2, 14), -GEN_VXFORM_207(vsrad, 2, 15), -GEN_VXFORM_300(vsrv, 2, 28), -GEN_VXFORM_300(vslv, 2, 29), -GEN_VXFORM(vslo, 6, 16), -GEN_VXFORM(vsro, 6, 17), -GEN_VXFORM(vaddcuw, 0, 6), -GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300), - -GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_300(bcdsr, 0, 23), -GEN_VXFORM_300(bcdsr, 0, 31), -GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vadduws, 0, 10), -GEN_VXFORM(vaddsbs, 0, 12), -GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vaddsws, 0, 14), -GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vsubuws, 0, 26), -GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300), -GEN_VXFORM(vsubshs, 0, 29), -GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_207(vadduqm, 0, 4), -GEN_VXFORM_207(vaddcuq, 0, 5), -GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM(vrlb, 2, 0), -GEN_VXFORM(vrlh, 2, 1), -GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vsr, 2, 11), -GEN_VXFORM(vpkuhum, 7, 0), -GEN_VXFORM(vpkuwum, 7, 1), -GEN_VXFORM_207(vpkudum, 7, 17), -GEN_VXFORM(vpkuhus, 7, 2), -GEN_VXFORM(vpkuwus, 7, 3), -GEN_VXFORM_207(vpkudus, 7, 19), -GEN_VXFORM(vpkshus, 7, 4), -GEN_VXFORM(vpkswus, 7, 5), -GEN_VXFORM_207(vpksdus, 7, 21), -GEN_VXFORM(vpkshss, 7, 6), -GEN_VXFORM(vpkswss, 7, 7), -GEN_VXFORM_207(vpksdss, 7, 23), -GEN_VXFORM(vpkpx, 7, 12), -GEN_VXFORM(vsum4ubs, 4, 24), -GEN_VXFORM(vsum4sbs, 4, 28), -GEN_VXFORM(vsum4shs, 4, 25), -GEN_VXFORM(vsum2sws, 4, 26), -GEN_VXFORM(vsumsws, 4, 30), -GEN_VXFORM(vaddfp, 5, 0), -GEN_VXFORM(vsubfp, 5, 1), -GEN_VXFORM(vmaxfp, 5, 16), -GEN_VXFORM(vminfp, 5, 17), - -#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ - GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), -#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \ -GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300), -#define GEN_VXRFORM(name, opc2, opc3) \ - GEN_VXRFORM1(name, name, #name, opc2, opc3) \ - GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) -#define GEN_VXRFORM_300(name, opc2, opc3) \ - GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \ - GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) - -GEN_VXRFORM_300(vcmpnezb, 3, 4) -GEN_VXRFORM_300(vcmpnezh, 3, 5) -GEN_VXRFORM_300(vcmpnezw, 3, 6) -GEN_VXRFORM(vcmpgtsb, 3, 12) -GEN_VXRFORM(vcmpgtsh, 3, 13) -GEN_VXRFORM(vcmpgtsw, 3, 14) -GEN_VXRFORM(vcmpgtub, 3, 8) -GEN_VXRFORM(vcmpgtuh, 3, 9) -GEN_VXRFORM(vcmpgtuw, 3, 10) -GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM(vcmpgefp, 3, 7) -GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE) -GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE) - -#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \ -GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \ - PPC_NONE) -GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000), -GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000, - PPC_ALTIVEC), -GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000), -GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06), -GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07), -GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10), -GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11), -GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18), -GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19), -GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A), -GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C), -GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D), -GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E), -GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F), -GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0), -GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1), -GEN_VXFORM_300(vpermr, 0x1D, 0xFF), - -#define GEN_VXFORM_NOA(name, opc2, opc3) \ - GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) -GEN_VXFORM_NOA(vupkhsb, 7, 8), -GEN_VXFORM_NOA(vupkhsh, 7, 9), -GEN_VXFORM_207(vupkhsw, 7, 25), -GEN_VXFORM_NOA(vupklsb, 7, 10), -GEN_VXFORM_NOA(vupklsh, 7, 11), -GEN_VXFORM_207(vupklsw, 7, 27), -GEN_VXFORM_NOA(vupkhpx, 7, 13), -GEN_VXFORM_NOA(vupklpx, 7, 15), -GEN_VXFORM_NOA(vrefp, 5, 4), -GEN_VXFORM_NOA(vrsqrtefp, 5, 5), -GEN_VXFORM_NOA(vexptefp, 5, 6), -GEN_VXFORM_NOA(vlogefp, 5, 7), -GEN_VXFORM_NOA(vrfim, 5, 11), -GEN_VXFORM_NOA(vrfin, 5, 8), -GEN_VXFORM_NOA(vrfip, 5, 10), -GEN_VXFORM_NOA(vrfiz, 5, 9), - -#define GEN_VXFORM_UIMM(name, opc2, opc3) \ - GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) -GEN_VXFORM_UIMM(vcfux, 5, 12), -GEN_VXFORM_UIMM(vcfsx, 5, 13), -GEN_VXFORM_UIMM(vctuxs, 5, 14), -GEN_VXFORM_UIMM(vctsxs, 5, 15), - - -#define GEN_VAFORM_PAIRED(name0, name1, opc2) \ - GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) -GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), -GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), -GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), -GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), -GEN_VAFORM_PAIRED(vsel, vperm, 21), -GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), - -GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), - -GEN_VXFORM_300(vbpermd, 6, 23), -GEN_VXFORM_207(vbpermq, 6, 21), -GEN_VXFORM_207(vgbbd, 6, 20), -GEN_VXFORM_207(vpmsumb, 4, 16), -GEN_VXFORM_207(vpmsumh, 4, 17), -GEN_VXFORM_207(vpmsumw, 4, 18), -GEN_VXFORM_207(vpmsumd, 4, 19), - -GEN_VXFORM_207(vsbox, 4, 23), - -GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), - -GEN_VXFORM_207(vshasigmaw, 1, 26), -GEN_VXFORM_207(vshasigmad, 1, 27), - -GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc new file mode 100644 index 0000000000..b518de46db --- /dev/null +++ b/target/ppc/translate/vsx-impl.c.inc @@ -0,0 +1,2055 @@ +/*** VSX extension ***/ + +static inline void get_cpu_vsrh(TCGv_i64 dst, int n) +{ + tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true)); +} + +static inline void get_cpu_vsrl(TCGv_i64 dst, int n) +{ + tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false)); +} + +static inline void set_cpu_vsrh(int n, TCGv_i64 src) +{ + tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true)); +} + +static inline void set_cpu_vsrl(int n, TCGv_i64 src) +{ + tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false)); +} + +static inline TCGv_ptr gen_vsr_ptr(int reg) +{ + TCGv_ptr r = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg)); + return r; +} + +#define VSX_LOAD_SCALAR(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + gen_qemu_##operation(ctx, t0, EA); \ + set_cpu_vsrh(xT(ctx->opcode), t0); \ + /* NOTE: cpu_vsrl is undefined */ \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +VSX_LOAD_SCALAR(lxsdx, ld64_i64) +VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) +VSX_LOAD_SCALAR(lxsibzx, ld8u_i64) +VSX_LOAD_SCALAR(lxsihzx, ld16u_i64) +VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) +VSX_LOAD_SCALAR(lxsspx, ld32fs) + +static void gen_lxvd2x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_gen_addi_tl(EA, EA, 8); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrl(xT(ctx->opcode), t0); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +static void gen_lxvdsx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + TCGv_i64 t1; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_gen_mov_i64(t1, t0); + set_cpu_vsrl(xT(ctx->opcode), t1); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static void gen_lxvw4x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xth; + TCGv_i64 xtl; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + + gen_addr_reg_index(ctx, EA); + if (ctx->le_mode) { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_shri_i64(t1, t0, 32); + tcg_gen_deposit_i64(xth, t1, t0, 32, 32); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_shri_i64(t1, t0, 32); + tcg_gen_deposit_i64(xtl, t1, t0, 32, 32); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + } else { + tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); +} + +static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, + TCGv_i64 inh, TCGv_i64 inl) +{ + TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + /* outh = ((inh & mask) << 8) | ((inh >> 8) & mask) */ + tcg_gen_and_i64(t0, inh, mask); + tcg_gen_shli_i64(t0, t0, 8); + tcg_gen_shri_i64(t1, inh, 8); + tcg_gen_and_i64(t1, t1, mask); + tcg_gen_or_i64(outh, t0, t1); + + /* outl = ((inl & mask) << 8) | ((inl >> 8) & mask) */ + tcg_gen_and_i64(t0, inl, mask); + tcg_gen_shli_i64(t0, t0, 8); + tcg_gen_shri_i64(t1, inl, 8); + tcg_gen_and_i64(t1, t1, mask); + tcg_gen_or_i64(outl, t0, t1); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(mask); +} + +static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, + TCGv_i64 inh, TCGv_i64 inl) +{ + TCGv_i64 hi = tcg_temp_new_i64(); + TCGv_i64 lo = tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(hi, inh); + tcg_gen_bswap64_i64(lo, inl); + tcg_gen_shri_i64(outh, hi, 32); + tcg_gen_deposit_i64(outh, outh, hi, 32, 32); + tcg_gen_shri_i64(outl, lo, 32); + tcg_gen_deposit_i64(outl, outl, lo, 32, 32); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); +} +static void gen_lxvh8x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xth; + TCGv_i64 xtl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + gen_set_access_type(ctx, ACCESS_INT); + + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + if (ctx->le_mode) { + gen_bswap16x8(xth, xtl, xth, xtl); + } + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); +} + +static void gen_lxvb16x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xth; + TCGv_i64 xtl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); +} + +#define VSX_VECTOR_LOAD(name, op, indexed) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + int xt; \ + TCGv EA; \ + TCGv_i64 xth; \ + TCGv_i64 xtl; \ + \ + if (indexed) { \ + xt = xT(ctx->opcode); \ + } else { \ + xt = DQxT(ctx->opcode); \ + } \ + \ + if (xt < 32) { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + } else { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + } \ + xth = tcg_temp_new_i64(); \ + xtl = tcg_temp_new_i64(); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + if (indexed) { \ + gen_addr_reg_index(ctx, EA); \ + } else { \ + gen_addr_imm_index(ctx, EA, 0x0F); \ + } \ + if (ctx->le_mode) { \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrl(xt, xtl); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrh(xt, xth); \ + } else { \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrh(xt, xth); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrl(xt, xtl); \ + } \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ + tcg_temp_free_i64(xtl); \ +} + +VSX_VECTOR_LOAD(lxv, ld_i64, 0) +VSX_VECTOR_LOAD(lxvx, ld_i64, 1) + +#define VSX_VECTOR_STORE(name, op, indexed) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + int xt; \ + TCGv EA; \ + TCGv_i64 xth; \ + TCGv_i64 xtl; \ + \ + if (indexed) { \ + xt = xT(ctx->opcode); \ + } else { \ + xt = DQxT(ctx->opcode); \ + } \ + \ + if (xt < 32) { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + } else { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + } \ + xth = tcg_temp_new_i64(); \ + xtl = tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, xt); \ + get_cpu_vsrl(xtl, xt); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + if (indexed) { \ + gen_addr_reg_index(ctx, EA); \ + } else { \ + gen_addr_imm_index(ctx, EA, 0x0F); \ + } \ + if (ctx->le_mode) { \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ + } else { \ + tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ + tcg_gen_addi_tl(EA, EA, 8); \ + tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ + } \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ + tcg_temp_free_i64(xtl); \ +} + +VSX_VECTOR_STORE(stxv, st_i64, 0) +VSX_VECTOR_STORE(stxvx, st_i64, 1) + +#ifdef TARGET_PPC64 +#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_ptr xt; \ + \ + if (xT(ctx->opcode) < 32) { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + } else { \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + } \ + EA = tcg_temp_new(); \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + gen_set_access_type(ctx, ACCESS_INT); \ + gen_addr_register(ctx, EA); \ + gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(xt); \ +} + +VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) +VSX_VECTOR_LOAD_STORE_LENGTH(lxvll) +VSX_VECTOR_LOAD_STORE_LENGTH(stxvl) +VSX_VECTOR_LOAD_STORE_LENGTH(stxvll) +#endif + +#define VSX_LOAD_SCALAR_DS(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 xth; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + xth = tcg_temp_new_i64(); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_imm_index(ctx, EA, 0x03); \ + gen_qemu_##operation(ctx, xth, EA); \ + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \ + /* NOTE: cpu_vsrl is undefined */ \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ +} + +VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) +VSX_LOAD_SCALAR_DS(lxssp, ld32fs) + +#define VSX_STORE_SCALAR(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + get_cpu_vsrh(t0, xS(ctx->opcode)); \ + gen_qemu_##operation(ctx, t0, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + +VSX_STORE_SCALAR(stxsdx, st64_i64) + +VSX_STORE_SCALAR(stxsibx, st8_i64) +VSX_STORE_SCALAR(stxsihx, st16_i64) +VSX_STORE_SCALAR(stxsiwx, st32_i64) +VSX_STORE_SCALAR(stxsspx, st32fs) + +static void gen_stxvd2x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 t0; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + get_cpu_vsrh(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_gen_addi_tl(EA, EA, 8); + get_cpu_vsrl(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); + tcg_temp_free(EA); + tcg_temp_free_i64(t0); +} + +static void gen_stxvw4x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + if (ctx->le_mode) { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_shri_i64(t0, xsh, 32); + tcg_gen_deposit_i64(t1, t0, xsh, 32, 32); + tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_shri_i64(t0, xsl, 32); + tcg_gen_deposit_i64(t1, t0, xsl, 32, 32); + tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + } else { + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); + } + tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); +} + +static void gen_stxvh8x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + if (ctx->le_mode) { + TCGv_i64 outh = tcg_temp_new_i64(); + TCGv_i64 outl = tcg_temp_new_i64(); + + gen_bswap16x8(outh, outl, xsh, xsl); + tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEQ); + tcg_temp_free_i64(outh); + tcg_temp_free_i64(outl); + } else { + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); + } + tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); +} + +static void gen_stxvb16x(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); + tcg_gen_addi_tl(EA, EA, 8); + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); + tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); +} + +#define VSX_STORE_SCALAR_DS(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 xth; \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + xth = tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_imm_index(ctx, EA, 0x03); \ + gen_qemu_##operation(ctx, xth, EA); \ + /* NOTE: cpu_vsrl is undefined */ \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ +} + +VSX_STORE_SCALAR_DS(stxsd, st64_i64) +VSX_STORE_SCALAR_DS(stxssp, st32fs) + +static void gen_mfvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + tcg_gen_ext32u_i64(tmp, xsh); + tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} + +static void gen_mtvsrwa(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} + +static void gen_mtvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32u_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} + +#if defined(TARGET_PPC64) +static void gen_mfvsrd(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + t0 = tcg_temp_new_i64(); + get_cpu_vsrh(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); +} + +static void gen_mtvsrd(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + t0 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} + +static void gen_mfvsrld(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + t0 = tcg_temp_new_i64(); + get_cpu_vsrl(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); +} + +static void gen_mtvsrdd(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xT(ctx->opcode) < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + + t0 = tcg_temp_new_i64(); + if (!rA(ctx->opcode)) { + tcg_gen_movi_i64(t0, 0); + } else { + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); + } + set_cpu_vsrh(xT(ctx->opcode), t0); + + tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); + set_cpu_vsrl(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} + +static void gen_mtvsrws(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xT(ctx->opcode) < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + + t0 = tcg_temp_new_i64(); + tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rA(ctx->opcode)], 32, 32); + set_cpu_vsrl(xT(ctx->opcode), t0); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} + +#endif + +static void gen_xxpermdi(DisasContext *ctx) +{ + TCGv_i64 xh, xl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + + xh = tcg_temp_new_i64(); + xl = tcg_temp_new_i64(); + + if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || + (xT(ctx->opcode) == xB(ctx->opcode)))) { + if ((DM(ctx->opcode) & 2) == 0) { + get_cpu_vsrh(xh, xA(ctx->opcode)); + } else { + get_cpu_vsrl(xh, xA(ctx->opcode)); + } + if ((DM(ctx->opcode) & 1) == 0) { + get_cpu_vsrh(xl, xB(ctx->opcode)); + } else { + get_cpu_vsrl(xl, xB(ctx->opcode)); + } + + set_cpu_vsrh(xT(ctx->opcode), xh); + set_cpu_vsrl(xT(ctx->opcode), xl); + } else { + if ((DM(ctx->opcode) & 2) == 0) { + get_cpu_vsrh(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); + } else { + get_cpu_vsrl(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); + } + if ((DM(ctx->opcode) & 1) == 0) { + get_cpu_vsrh(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); + } else { + get_cpu_vsrl(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); + } + } + tcg_temp_free_i64(xh); + tcg_temp_free_i64(xl); +} + +#define OP_ABS 1 +#define OP_NABS 2 +#define OP_NEG 3 +#define OP_CPSGN 4 +#define SGN_MASK_DP 0x8000000000000000ull +#define SGN_MASK_SP 0x8000000080000000ull + +#define VSX_SCALAR_MOVE(name, op, sgn_mask) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_i64 xb, sgm; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xb = tcg_temp_new_i64(); \ + sgm = tcg_temp_new_i64(); \ + get_cpu_vsrh(xb, xB(ctx->opcode)); \ + tcg_gen_movi_i64(sgm, sgn_mask); \ + switch (op) { \ + case OP_ABS: { \ + tcg_gen_andc_i64(xb, xb, sgm); \ + break; \ + } \ + case OP_NABS: { \ + tcg_gen_or_i64(xb, xb, sgm); \ + break; \ + } \ + case OP_NEG: { \ + tcg_gen_xor_i64(xb, xb, sgm); \ + break; \ + } \ + case OP_CPSGN: { \ + TCGv_i64 xa = tcg_temp_new_i64(); \ + get_cpu_vsrh(xa, xA(ctx->opcode)); \ + tcg_gen_and_i64(xa, xa, sgm); \ + tcg_gen_andc_i64(xb, xb, sgm); \ + tcg_gen_or_i64(xb, xb, xa); \ + tcg_temp_free_i64(xa); \ + break; \ + } \ + } \ + set_cpu_vsrh(xT(ctx->opcode), xb); \ + tcg_temp_free_i64(xb); \ + tcg_temp_free_i64(sgm); \ + } + +VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) +VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) +VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) +VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) + +#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + int xa; \ + int xt = rD(ctx->opcode) + 32; \ + int xb = rB(ctx->opcode) + 32; \ + TCGv_i64 xah, xbh, xbl, sgm, tmp; \ + \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xbh = tcg_temp_new_i64(); \ + xbl = tcg_temp_new_i64(); \ + sgm = tcg_temp_new_i64(); \ + tmp = tcg_temp_new_i64(); \ + get_cpu_vsrh(xbh, xb); \ + get_cpu_vsrl(xbl, xb); \ + tcg_gen_movi_i64(sgm, sgn_mask); \ + switch (op) { \ + case OP_ABS: \ + tcg_gen_andc_i64(xbh, xbh, sgm); \ + break; \ + case OP_NABS: \ + tcg_gen_or_i64(xbh, xbh, sgm); \ + break; \ + case OP_NEG: \ + tcg_gen_xor_i64(xbh, xbh, sgm); \ + break; \ + case OP_CPSGN: \ + xah = tcg_temp_new_i64(); \ + xa = rA(ctx->opcode) + 32; \ + get_cpu_vsrh(tmp, xa); \ + tcg_gen_and_i64(xah, tmp, sgm); \ + tcg_gen_andc_i64(xbh, xbh, sgm); \ + tcg_gen_or_i64(xbh, xbh, xah); \ + tcg_temp_free_i64(xah); \ + break; \ + } \ + set_cpu_vsrh(xt, xbh); \ + set_cpu_vsrl(xt, xbl); \ + tcg_temp_free_i64(xbl); \ + tcg_temp_free_i64(xbh); \ + tcg_temp_free_i64(sgm); \ + tcg_temp_free_i64(tmp); \ +} + +VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP) +VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP) +VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP) +VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP) + +#define VSX_VECTOR_MOVE(name, op, sgn_mask) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_i64 xbh, xbl, sgm; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xbh = tcg_temp_new_i64(); \ + xbl = tcg_temp_new_i64(); \ + sgm = tcg_temp_new_i64(); \ + get_cpu_vsrh(xbh, xB(ctx->opcode)); \ + get_cpu_vsrl(xbl, xB(ctx->opcode)); \ + tcg_gen_movi_i64(sgm, sgn_mask); \ + switch (op) { \ + case OP_ABS: { \ + tcg_gen_andc_i64(xbh, xbh, sgm); \ + tcg_gen_andc_i64(xbl, xbl, sgm); \ + break; \ + } \ + case OP_NABS: { \ + tcg_gen_or_i64(xbh, xbh, sgm); \ + tcg_gen_or_i64(xbl, xbl, sgm); \ + break; \ + } \ + case OP_NEG: { \ + tcg_gen_xor_i64(xbh, xbh, sgm); \ + tcg_gen_xor_i64(xbl, xbl, sgm); \ + break; \ + } \ + case OP_CPSGN: { \ + TCGv_i64 xah = tcg_temp_new_i64(); \ + TCGv_i64 xal = tcg_temp_new_i64(); \ + get_cpu_vsrh(xah, xA(ctx->opcode)); \ + get_cpu_vsrl(xal, xA(ctx->opcode)); \ + tcg_gen_and_i64(xah, xah, sgm); \ + tcg_gen_and_i64(xal, xal, sgm); \ + tcg_gen_andc_i64(xbh, xbh, sgm); \ + tcg_gen_andc_i64(xbl, xbl, sgm); \ + tcg_gen_or_i64(xbh, xbh, xah); \ + tcg_gen_or_i64(xbl, xbl, xal); \ + tcg_temp_free_i64(xah); \ + tcg_temp_free_i64(xal); \ + break; \ + } \ + } \ + set_cpu_vsrh(xT(ctx->opcode), xbh); \ + set_cpu_vsrl(xT(ctx->opcode), xbl); \ + tcg_temp_free_i64(xbh); \ + tcg_temp_free_i64(xbl); \ + tcg_temp_free_i64(sgm); \ + } + +VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) +VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) +VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) +VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) +VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) +VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) +VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) +VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) + +#define VSX_CMP(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 ignored; \ + TCGv_ptr xt, xa, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + xa = gen_vsr_ptr(xA(ctx->opcode)); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + if ((ctx->opcode >> (31 - 21)) & 1) { \ + gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \ + } else { \ + ignored = tcg_temp_new_i32(); \ + gen_helper_##name(ignored, cpu_env, xt, xa, xb); \ + tcg_temp_free_i32(ignored); \ + } \ + gen_helper_float_check_status(cpu_env); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(xb); \ +} + +VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) +VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) +VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) +VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300) +VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) +VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) +VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) +VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) + +static void gen_xscvqpdp(DisasContext *ctx) +{ + TCGv_i32 opc; + TCGv_ptr xt, xb; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + opc = tcg_const_i32(ctx->opcode); + xt = gen_vsr_ptr(xT(ctx->opcode)); + xb = gen_vsr_ptr(xB(ctx->opcode)); + gen_helper_xscvqpdp(cpu_env, opc, xt, xb); + tcg_temp_free_i32(opc); + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xb); +} + +#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + gen_helper_##name(cpu_env, opc); \ + tcg_temp_free_i32(opc); \ +} + +#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr xt, xa, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + xa = gen_vsr_ptr(xA(ctx->opcode)); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + gen_helper_##name(cpu_env, xt, xa, xb); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr xt, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + gen_helper_##name(cpu_env, xt, xb); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xa, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xa = gen_vsr_ptr(xA(ctx->opcode)); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + gen_helper_##name(cpu_env, opc, xa, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + gen_helper_##name(cpu_env, opc, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xt, xa, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ + xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ + xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ + gen_helper_##name(cpu_env, opc, xt, xa, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xt, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ + xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ + gen_helper_##name(cpu_env, opc, xt, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 opc; \ + TCGv_ptr xa, xb; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + opc = tcg_const_i32(ctx->opcode); \ + xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ + xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ + gen_helper_##name(cpu_env, opc, xa, xb); \ + tcg_temp_free_i32(opc); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(xb); \ +} + +#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + get_cpu_vsrh(t0, xB(ctx->opcode)); \ + gen_helper_##name(t1, cpu_env, t0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ +} + +GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) +GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) +GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) +GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) +GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) +GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) +GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) +GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) +GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) +GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) +GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) +GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) +GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) + +GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) + +GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) +GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) +GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) +GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) +GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) + +#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr xt, xa, b, c; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + xa = gen_vsr_ptr(xA(ctx->opcode)); \ + if (ctx->opcode & PPC_BIT32(25)) { \ + /* \ + * AxT + B \ + */ \ + b = gen_vsr_ptr(xT(ctx->opcode)); \ + c = gen_vsr_ptr(xB(ctx->opcode)); \ + } else { \ + /* \ + * AxB + T \ + */ \ + b = gen_vsr_ptr(xB(ctx->opcode)); \ + c = gen_vsr_ptr(xT(ctx->opcode)); \ + } \ + gen_helper_##name(cpu_env, xt, xa, b, c); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_ptr(xa); \ + tcg_temp_free_ptr(b); \ + tcg_temp_free_ptr(c); \ +} + +GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207) +GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX) +GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX) + +static void gen_xxbrd(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + tcg_gen_bswap64_i64(xth, xbh); + tcg_gen_bswap64_i64(xtl, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xxbrh(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + gen_bswap16x8(xth, xtl, xbh, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xxbrq(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + TCGv_i64 t0; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + t0 = tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(t0, xbl); + tcg_gen_bswap64_i64(xtl, xbh); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_gen_mov_i64(xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xxbrw(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + gen_bswap32x4(xth, xtl, xbh, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +#define VSX_LOGICAL(name, vece, tcg_op) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \ + vsr_full_offset(xA(ctx->opcode)), \ + vsr_full_offset(xB(ctx->opcode)), 16, 16); \ + } + +VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and) +VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc) +VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or) +VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor) +VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor) +VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv) +VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand) +VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc) + +#define VSX_XXMRG(name, high) \ +static void glue(gen_, name)(DisasContext *ctx) \ + { \ + TCGv_i64 a0, a1, b0, b1, tmp; \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + a0 = tcg_temp_new_i64(); \ + a1 = tcg_temp_new_i64(); \ + b0 = tcg_temp_new_i64(); \ + b1 = tcg_temp_new_i64(); \ + tmp = tcg_temp_new_i64(); \ + if (high) { \ + get_cpu_vsrh(a0, xA(ctx->opcode)); \ + get_cpu_vsrh(a1, xA(ctx->opcode)); \ + get_cpu_vsrh(b0, xB(ctx->opcode)); \ + get_cpu_vsrh(b1, xB(ctx->opcode)); \ + } else { \ + get_cpu_vsrl(a0, xA(ctx->opcode)); \ + get_cpu_vsrl(a1, xA(ctx->opcode)); \ + get_cpu_vsrl(b0, xB(ctx->opcode)); \ + get_cpu_vsrl(b1, xB(ctx->opcode)); \ + } \ + tcg_gen_shri_i64(a0, a0, 32); \ + tcg_gen_shri_i64(b0, b0, 32); \ + tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \ + set_cpu_vsrh(xT(ctx->opcode), tmp); \ + tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \ + set_cpu_vsrl(xT(ctx->opcode), tmp); \ + tcg_temp_free_i64(a0); \ + tcg_temp_free_i64(a1); \ + tcg_temp_free_i64(b0); \ + tcg_temp_free_i64(b1); \ + tcg_temp_free_i64(tmp); \ + } + +VSX_XXMRG(xxmrghw, 1) +VSX_XXMRG(xxmrglw, 0) + +static void gen_xxsel(DisasContext *ctx) +{ + int rt = xT(ctx->opcode); + int ra = xA(ctx->opcode); + int rb = xB(ctx->opcode); + int rc = xC(ctx->opcode); + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc), + vsr_full_offset(rb), vsr_full_offset(ra), 16, 16); +} + +static void gen_xxspltw(DisasContext *ctx) +{ + int rt = xT(ctx->opcode); + int rb = xB(ctx->opcode); + int uim = UIM(ctx->opcode); + int tofs, bofs; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + + tofs = vsr_full_offset(rt); + bofs = vsr_full_offset(rb); + bofs += uim << MO_32; +#ifndef HOST_WORDS_BIG_ENDIAN + bofs ^= 8 | 4; +#endif + + tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16); +} + +#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff)) + +static void gen_xxspltib(DisasContext *ctx) +{ + uint8_t uim8 = IMM8(ctx->opcode); + int rt = xT(ctx->opcode); + + if (rt < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8); +} + +static void gen_xxsldwi(DisasContext *ctx) +{ + TCGv_i64 xth, xtl; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + + switch (SHW(ctx->opcode)) { + case 0: { + get_cpu_vsrh(xth, xA(ctx->opcode)); + get_cpu_vsrl(xtl, xA(ctx->opcode)); + break; + } + case 1: { + TCGv_i64 t0 = tcg_temp_new_i64(); + get_cpu_vsrh(xth, xA(ctx->opcode)); + tcg_gen_shli_i64(xth, xth, 32); + get_cpu_vsrl(t0, xA(ctx->opcode)); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_or_i64(xth, xth, t0); + get_cpu_vsrl(xtl, xA(ctx->opcode)); + tcg_gen_shli_i64(xtl, xtl, 32); + get_cpu_vsrh(t0, xB(ctx->opcode)); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_or_i64(xtl, xtl, t0); + tcg_temp_free_i64(t0); + break; + } + case 2: { + get_cpu_vsrl(xth, xA(ctx->opcode)); + get_cpu_vsrh(xtl, xB(ctx->opcode)); + break; + } + case 3: { + TCGv_i64 t0 = tcg_temp_new_i64(); + get_cpu_vsrl(xth, xA(ctx->opcode)); + tcg_gen_shli_i64(xth, xth, 32); + get_cpu_vsrh(t0, xB(ctx->opcode)); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_or_i64(xth, xth, t0); + get_cpu_vsrh(xtl, xB(ctx->opcode)); + tcg_gen_shli_i64(xtl, xtl, 32); + get_cpu_vsrl(t0, xB(ctx->opcode)); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_or_i64(xtl, xtl, t0); + tcg_temp_free_i64(t0); + break; + } + } + + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); +} + +#define VSX_EXTRACT_INSERT(name) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_ptr xt, xb; \ + TCGv_i32 t0; \ + TCGv_i64 t1; \ + uint8_t uimm = UIMM4(ctx->opcode); \ + \ + if (unlikely(!ctx->vsx_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VSXU); \ + return; \ + } \ + xt = gen_vsr_ptr(xT(ctx->opcode)); \ + xb = gen_vsr_ptr(xB(ctx->opcode)); \ + t0 = tcg_temp_new_i32(); \ + t1 = tcg_temp_new_i64(); \ + /* \ + * uimm > 15 out of bound and for \ + * uimm > 12 handle as per hardware in helper \ + */ \ + if (uimm > 15) { \ + tcg_gen_movi_i64(t1, 0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + set_cpu_vsrl(xT(ctx->opcode), t1); \ + return; \ + } \ + tcg_gen_movi_i32(t0, uimm); \ + gen_helper_##name(cpu_env, xt, xb, t0); \ + tcg_temp_free_ptr(xb); \ + tcg_temp_free_ptr(xt); \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i64(t1); \ +} + +VSX_EXTRACT_INSERT(xxextractuw) +VSX_EXTRACT_INSERT(xxinsertw) + +#ifdef TARGET_PPC64 +static void gen_xsxexpdp(DisasContext *ctx) +{ + TCGv rt = cpu_gpr[rD(ctx->opcode)]; + TCGv_i64 t0; + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + get_cpu_vsrh(t0, xB(ctx->opcode)); + tcg_gen_extract_i64(rt, t0, 52, 11); + tcg_temp_free_i64(t0); +} + +static void gen_xsxexpqp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + + tcg_gen_extract_i64(xth, xbh, 48, 15); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); + tcg_gen_movi_i64(xtl, 0); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); +} + +static void gen_xsiexpdp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv ra = cpu_gpr[rA(ctx->opcode)]; + TCGv rb = cpu_gpr[rB(ctx->opcode)]; + TCGv_i64 t0; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + t0 = tcg_temp_new_i64(); + xth = tcg_temp_new_i64(); + tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF); + tcg_gen_andi_i64(t0, rb, 0x7FF); + tcg_gen_shli_i64(t0, t0, 52); + tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); + /* dword[1] is undefined */ + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); +} + +static void gen_xsiexpqp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; + TCGv_i64 t0; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + get_cpu_vsrh(xah, rA(ctx->opcode) + 32); + get_cpu_vsrl(xal, rA(ctx->opcode) + 32); + xbh = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + t0 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF); + tcg_gen_andi_i64(t0, xbh, 0x7FFF); + tcg_gen_shli_i64(t0, t0, 48); + tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); + tcg_gen_mov_i64(xtl, xal); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); +} + +static void gen_xsxsigdp(DisasContext *ctx) +{ + TCGv rt = cpu_gpr[rD(ctx->opcode)]; + TCGv_i64 t0, t1, zr, nan, exp; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + exp = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + zr = tcg_const_i64(0); + nan = tcg_const_i64(2047); + + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_extract_i64(exp, t1, 52, 11); + tcg_gen_movi_i64(t0, 0x0010000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_deposit_i64(rt, t0, t1, 0, 52); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(exp); + tcg_temp_free_i64(zr); + tcg_temp_free_i64(nan); +} + +static void gen_xsxsigqp(DisasContext *ctx) +{ + TCGv_i64 t0, zr, nan, exp; + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + get_cpu_vsrl(xbl, rB(ctx->opcode) + 32); + exp = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + zr = tcg_const_i64(0); + nan = tcg_const_i64(32767); + + tcg_gen_extract_i64(exp, xbh, 48, 15); + tcg_gen_movi_i64(t0, 0x0001000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + tcg_gen_deposit_i64(xth, t0, xbh, 0, 48); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); + tcg_gen_mov_i64(xtl, xbl); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(exp); + tcg_temp_free_i64(zr); + tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} +#endif + +static void gen_xviexpsp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; + TCGv_i64 xbl; + TCGv_i64 t0; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + t0 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF); + tcg_gen_andi_i64(t0, xbh, 0xFF000000FF); + tcg_gen_shli_i64(t0, t0, 23); + tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); + tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF); + tcg_gen_andi_i64(t0, xbl, 0xFF000000FF); + tcg_gen_shli_i64(t0, t0, 23); + tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xviexpdp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + tcg_gen_deposit_i64(xth, xah, xbh, 52, 11); + set_cpu_vsrh(xT(ctx->opcode), xth); + + tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xvxexpsp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + tcg_gen_shri_i64(xth, xbh, 23); + tcg_gen_andi_i64(xth, xth, 0xFF000000FF); + set_cpu_vsrh(xT(ctx->opcode), xth); + tcg_gen_shri_i64(xtl, xbl, 23); + tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +static void gen_xvxexpdp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + + tcg_gen_extract_i64(xth, xbh, 52, 11); + set_cpu_vsrh(xT(ctx->opcode), xth); + tcg_gen_extract_i64(xtl, xbl, 52, 11); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) + +static void gen_xvxsigdp(DisasContext *ctx) +{ + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + TCGv_i64 t0, zr, nan, exp; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + exp = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + zr = tcg_const_i64(0); + nan = tcg_const_i64(2047); + + tcg_gen_extract_i64(exp, xbh, 52, 11); + tcg_gen_movi_i64(t0, 0x0010000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + tcg_gen_deposit_i64(xth, t0, xbh, 0, 52); + set_cpu_vsrh(xT(ctx->opcode), xth); + + tcg_gen_extract_i64(exp, xbl, 52, 11); + tcg_gen_movi_i64(t0, 0x0010000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(exp); + tcg_temp_free_i64(zr); + tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); +} + +#undef GEN_XX2FORM +#undef GEN_XX3FORM +#undef GEN_XX2IFORM +#undef GEN_XX3_RC_FORM +#undef GEN_XX3FORM_DM +#undef VSX_LOGICAL diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c deleted file mode 100644 index b518de46db..0000000000 --- a/target/ppc/translate/vsx-impl.inc.c +++ /dev/null @@ -1,2055 +0,0 @@ -/*** VSX extension ***/ - -static inline void get_cpu_vsrh(TCGv_i64 dst, int n) -{ - tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true)); -} - -static inline void get_cpu_vsrl(TCGv_i64 dst, int n) -{ - tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false)); -} - -static inline void set_cpu_vsrh(int n, TCGv_i64 src) -{ - tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true)); -} - -static inline void set_cpu_vsrl(int n, TCGv_i64 src) -{ - tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false)); -} - -static inline TCGv_ptr gen_vsr_ptr(int reg) -{ - TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg)); - return r; -} - -#define VSX_LOAD_SCALAR(name, operation) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##operation(ctx, t0, EA); \ - set_cpu_vsrh(xT(ctx->opcode), t0); \ - /* NOTE: cpu_vsrl is undefined */ \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -VSX_LOAD_SCALAR(lxsdx, ld64_i64) -VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) -VSX_LOAD_SCALAR(lxsibzx, ld8u_i64) -VSX_LOAD_SCALAR(lxsihzx, ld16u_i64) -VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) -VSX_LOAD_SCALAR(lxsspx, ld32fs) - -static void gen_lxvd2x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, t0, EA); - set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, t0, EA); - set_cpu_vsrl(xT(ctx->opcode), t0); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -static void gen_lxvdsx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, t0, EA); - set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_gen_mov_i64(t1, t0); - set_cpu_vsrl(xT(ctx->opcode), t1); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static void gen_lxvw4x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xth; - TCGv_i64 xtl; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - - gen_addr_reg_index(ctx, EA); - if (ctx->le_mode) { - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); - tcg_gen_shri_i64(t1, t0, 32); - tcg_gen_deposit_i64(xth, t1, t0, 32, 32); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ); - tcg_gen_shri_i64(t1, t0, 32); - tcg_gen_deposit_i64(xtl, t1, t0, 32, 32); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } else { - tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); - } - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); -} - -static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, - TCGv_i64 inh, TCGv_i64 inl) -{ - TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF); - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - /* outh = ((inh & mask) << 8) | ((inh >> 8) & mask) */ - tcg_gen_and_i64(t0, inh, mask); - tcg_gen_shli_i64(t0, t0, 8); - tcg_gen_shri_i64(t1, inh, 8); - tcg_gen_and_i64(t1, t1, mask); - tcg_gen_or_i64(outh, t0, t1); - - /* outl = ((inl & mask) << 8) | ((inl >> 8) & mask) */ - tcg_gen_and_i64(t0, inl, mask); - tcg_gen_shli_i64(t0, t0, 8); - tcg_gen_shri_i64(t1, inl, 8); - tcg_gen_and_i64(t1, t1, mask); - tcg_gen_or_i64(outl, t0, t1); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(mask); -} - -static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, - TCGv_i64 inh, TCGv_i64 inl) -{ - TCGv_i64 hi = tcg_temp_new_i64(); - TCGv_i64 lo = tcg_temp_new_i64(); - - tcg_gen_bswap64_i64(hi, inh); - tcg_gen_bswap64_i64(lo, inl); - tcg_gen_shri_i64(outh, hi, 32); - tcg_gen_deposit_i64(outh, outh, hi, 32, 32); - tcg_gen_shri_i64(outl, lo, 32); - tcg_gen_deposit_i64(outl, outl, lo, 32, 32); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); -} -static void gen_lxvh8x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xth; - TCGv_i64 xtl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); - if (ctx->le_mode) { - gen_bswap16x8(xth, xtl, xth, xtl); - } - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); -} - -static void gen_lxvb16x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xth; - TCGv_i64 xtl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); -} - -#define VSX_VECTOR_LOAD(name, op, indexed) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int xt; \ - TCGv EA; \ - TCGv_i64 xth; \ - TCGv_i64 xtl; \ - \ - if (indexed) { \ - xt = xT(ctx->opcode); \ - } else { \ - xt = DQxT(ctx->opcode); \ - } \ - \ - if (xt < 32) { \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - xth = tcg_temp_new_i64(); \ - xtl = tcg_temp_new_i64(); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (indexed) { \ - gen_addr_reg_index(ctx, EA); \ - } else { \ - gen_addr_imm_index(ctx, EA, 0x0F); \ - } \ - if (ctx->le_mode) { \ - tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ - set_cpu_vsrl(xt, xtl); \ - tcg_gen_addi_tl(EA, EA, 8); \ - tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ - set_cpu_vsrh(xt, xth); \ - } else { \ - tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ - set_cpu_vsrh(xt, xth); \ - tcg_gen_addi_tl(EA, EA, 8); \ - tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ - set_cpu_vsrl(xt, xtl); \ - } \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(xth); \ - tcg_temp_free_i64(xtl); \ -} - -VSX_VECTOR_LOAD(lxv, ld_i64, 0) -VSX_VECTOR_LOAD(lxvx, ld_i64, 1) - -#define VSX_VECTOR_STORE(name, op, indexed) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int xt; \ - TCGv EA; \ - TCGv_i64 xth; \ - TCGv_i64 xtl; \ - \ - if (indexed) { \ - xt = xT(ctx->opcode); \ - } else { \ - xt = DQxT(ctx->opcode); \ - } \ - \ - if (xt < 32) { \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - xth = tcg_temp_new_i64(); \ - xtl = tcg_temp_new_i64(); \ - get_cpu_vsrh(xth, xt); \ - get_cpu_vsrl(xtl, xt); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (indexed) { \ - gen_addr_reg_index(ctx, EA); \ - } else { \ - gen_addr_imm_index(ctx, EA, 0x0F); \ - } \ - if (ctx->le_mode) { \ - tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ - tcg_gen_addi_tl(EA, EA, 8); \ - tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ - } else { \ - tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ - tcg_gen_addi_tl(EA, EA, 8); \ - tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ - } \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(xth); \ - tcg_temp_free_i64(xtl); \ -} - -VSX_VECTOR_STORE(stxv, st_i64, 0) -VSX_VECTOR_STORE(stxvx, st_i64, 1) - -#ifdef TARGET_PPC64 -#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_ptr xt; \ - \ - if (xT(ctx->opcode) < 32) { \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - EA = tcg_temp_new(); \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - gen_set_access_type(ctx, ACCESS_INT); \ - gen_addr_register(ctx, EA); \ - gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(xt); \ -} - -VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) -VSX_VECTOR_LOAD_STORE_LENGTH(lxvll) -VSX_VECTOR_LOAD_STORE_LENGTH(stxvl) -VSX_VECTOR_LOAD_STORE_LENGTH(stxvll) -#endif - -#define VSX_LOAD_SCALAR_DS(name, operation) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 xth; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - xth = tcg_temp_new_i64(); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0x03); \ - gen_qemu_##operation(ctx, xth, EA); \ - set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \ - /* NOTE: cpu_vsrl is undefined */ \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(xth); \ -} - -VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) -VSX_LOAD_SCALAR_DS(lxssp, ld32fs) - -#define VSX_STORE_SCALAR(name, operation) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 t0; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - get_cpu_vsrh(t0, xS(ctx->opcode)); \ - gen_qemu_##operation(ctx, t0, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ -} - -VSX_STORE_SCALAR(stxsdx, st64_i64) - -VSX_STORE_SCALAR(stxsibx, st8_i64) -VSX_STORE_SCALAR(stxsihx, st16_i64) -VSX_STORE_SCALAR(stxsiwx, st32_i64) -VSX_STORE_SCALAR(stxsspx, st32fs) - -static void gen_stxvd2x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - get_cpu_vsrh(t0, xS(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_gen_addi_tl(EA, EA, 8); - get_cpu_vsrl(t0, xS(ctx->opcode)); - gen_qemu_st64_i64(ctx, t0, EA); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); -} - -static void gen_stxvw4x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xsh; - TCGv_i64 xsl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xsh = tcg_temp_new_i64(); - xsl = tcg_temp_new_i64(); - get_cpu_vsrh(xsh, xS(ctx->opcode)); - get_cpu_vsrl(xsl, xS(ctx->opcode)); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - if (ctx->le_mode) { - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - tcg_gen_shri_i64(t0, xsh, 32); - tcg_gen_deposit_i64(t1, t0, xsh, 32, 32); - tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_shri_i64(t0, xsl, 32); - tcg_gen_deposit_i64(t1, t0, xsl, 32, 32); - tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEQ); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } else { - tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); - } - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); -} - -static void gen_stxvh8x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xsh; - TCGv_i64 xsl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xsh = tcg_temp_new_i64(); - xsl = tcg_temp_new_i64(); - get_cpu_vsrh(xsh, xS(ctx->opcode)); - get_cpu_vsrl(xsl, xS(ctx->opcode)); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - if (ctx->le_mode) { - TCGv_i64 outh = tcg_temp_new_i64(); - TCGv_i64 outl = tcg_temp_new_i64(); - - gen_bswap16x8(outh, outl, xsh, xsl); - tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEQ); - tcg_temp_free_i64(outh); - tcg_temp_free_i64(outl); - } else { - tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); - } - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); -} - -static void gen_stxvb16x(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 xsh; - TCGv_i64 xsl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xsh = tcg_temp_new_i64(); - xsl = tcg_temp_new_i64(); - get_cpu_vsrh(xsh, xS(ctx->opcode)); - get_cpu_vsrl(xsl, xS(ctx->opcode)); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); - tcg_gen_addi_tl(EA, EA, 8); - tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); -} - -#define VSX_STORE_SCALAR_DS(name, operation) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv EA; \ - TCGv_i64 xth; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - xth = tcg_temp_new_i64(); \ - get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0x03); \ - gen_qemu_##operation(ctx, xth, EA); \ - /* NOTE: cpu_vsrl is undefined */ \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(xth); \ -} - -VSX_STORE_SCALAR_DS(stxsd, st64_i64) -VSX_STORE_SCALAR_DS(stxssp, st32fs) - -static void gen_mfvsrwz(DisasContext *ctx) -{ - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv_i64 xsh = tcg_temp_new_i64(); - get_cpu_vsrh(xsh, xS(ctx->opcode)); - tcg_gen_ext32u_i64(tmp, xsh); - tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); -} - -static void gen_mtvsrwa(DisasContext *ctx) -{ - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv_i64 xsh = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_ext32s_i64(xsh, tmp); - set_cpu_vsrh(xT(ctx->opcode), xsh); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); -} - -static void gen_mtvsrwz(DisasContext *ctx) -{ - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv_i64 xsh = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); - tcg_gen_ext32u_i64(xsh, tmp); - set_cpu_vsrh(xT(ctx->opcode), xsh); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); -} - -#if defined(TARGET_PPC64) -static void gen_mfvsrd(DisasContext *ctx) -{ - TCGv_i64 t0; - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - t0 = tcg_temp_new_i64(); - get_cpu_vsrh(t0, xS(ctx->opcode)); - tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); - tcg_temp_free_i64(t0); -} - -static void gen_mtvsrd(DisasContext *ctx) -{ - TCGv_i64 t0; - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - t0 = tcg_temp_new_i64(); - tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); - set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_temp_free_i64(t0); -} - -static void gen_mfvsrld(DisasContext *ctx) -{ - TCGv_i64 t0; - if (xS(ctx->opcode) < 32) { - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - t0 = tcg_temp_new_i64(); - get_cpu_vsrl(t0, xS(ctx->opcode)); - tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); - tcg_temp_free_i64(t0); -} - -static void gen_mtvsrdd(DisasContext *ctx) -{ - TCGv_i64 t0; - if (xT(ctx->opcode) < 32) { - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - - t0 = tcg_temp_new_i64(); - if (!rA(ctx->opcode)) { - tcg_gen_movi_i64(t0, 0); - } else { - tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); - } - set_cpu_vsrh(xT(ctx->opcode), t0); - - tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); - set_cpu_vsrl(xT(ctx->opcode), t0); - tcg_temp_free_i64(t0); -} - -static void gen_mtvsrws(DisasContext *ctx) -{ - TCGv_i64 t0; - if (xT(ctx->opcode) < 32) { - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - - t0 = tcg_temp_new_i64(); - tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], 32, 32); - set_cpu_vsrl(xT(ctx->opcode), t0); - set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_temp_free_i64(t0); -} - -#endif - -static void gen_xxpermdi(DisasContext *ctx) -{ - TCGv_i64 xh, xl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - - xh = tcg_temp_new_i64(); - xl = tcg_temp_new_i64(); - - if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || - (xT(ctx->opcode) == xB(ctx->opcode)))) { - if ((DM(ctx->opcode) & 2) == 0) { - get_cpu_vsrh(xh, xA(ctx->opcode)); - } else { - get_cpu_vsrl(xh, xA(ctx->opcode)); - } - if ((DM(ctx->opcode) & 1) == 0) { - get_cpu_vsrh(xl, xB(ctx->opcode)); - } else { - get_cpu_vsrl(xl, xB(ctx->opcode)); - } - - set_cpu_vsrh(xT(ctx->opcode), xh); - set_cpu_vsrl(xT(ctx->opcode), xl); - } else { - if ((DM(ctx->opcode) & 2) == 0) { - get_cpu_vsrh(xh, xA(ctx->opcode)); - set_cpu_vsrh(xT(ctx->opcode), xh); - } else { - get_cpu_vsrl(xh, xA(ctx->opcode)); - set_cpu_vsrh(xT(ctx->opcode), xh); - } - if ((DM(ctx->opcode) & 1) == 0) { - get_cpu_vsrh(xl, xB(ctx->opcode)); - set_cpu_vsrl(xT(ctx->opcode), xl); - } else { - get_cpu_vsrl(xl, xB(ctx->opcode)); - set_cpu_vsrl(xT(ctx->opcode), xl); - } - } - tcg_temp_free_i64(xh); - tcg_temp_free_i64(xl); -} - -#define OP_ABS 1 -#define OP_NABS 2 -#define OP_NEG 3 -#define OP_CPSGN 4 -#define SGN_MASK_DP 0x8000000000000000ull -#define SGN_MASK_SP 0x8000000080000000ull - -#define VSX_SCALAR_MOVE(name, op, sgn_mask) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_i64 xb, sgm; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xb = tcg_temp_new_i64(); \ - sgm = tcg_temp_new_i64(); \ - get_cpu_vsrh(xb, xB(ctx->opcode)); \ - tcg_gen_movi_i64(sgm, sgn_mask); \ - switch (op) { \ - case OP_ABS: { \ - tcg_gen_andc_i64(xb, xb, sgm); \ - break; \ - } \ - case OP_NABS: { \ - tcg_gen_or_i64(xb, xb, sgm); \ - break; \ - } \ - case OP_NEG: { \ - tcg_gen_xor_i64(xb, xb, sgm); \ - break; \ - } \ - case OP_CPSGN: { \ - TCGv_i64 xa = tcg_temp_new_i64(); \ - get_cpu_vsrh(xa, xA(ctx->opcode)); \ - tcg_gen_and_i64(xa, xa, sgm); \ - tcg_gen_andc_i64(xb, xb, sgm); \ - tcg_gen_or_i64(xb, xb, xa); \ - tcg_temp_free_i64(xa); \ - break; \ - } \ - } \ - set_cpu_vsrh(xT(ctx->opcode), xb); \ - tcg_temp_free_i64(xb); \ - tcg_temp_free_i64(sgm); \ - } - -VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) -VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) -VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) -VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) - -#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - int xa; \ - int xt = rD(ctx->opcode) + 32; \ - int xb = rB(ctx->opcode) + 32; \ - TCGv_i64 xah, xbh, xbl, sgm, tmp; \ - \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xbh = tcg_temp_new_i64(); \ - xbl = tcg_temp_new_i64(); \ - sgm = tcg_temp_new_i64(); \ - tmp = tcg_temp_new_i64(); \ - get_cpu_vsrh(xbh, xb); \ - get_cpu_vsrl(xbl, xb); \ - tcg_gen_movi_i64(sgm, sgn_mask); \ - switch (op) { \ - case OP_ABS: \ - tcg_gen_andc_i64(xbh, xbh, sgm); \ - break; \ - case OP_NABS: \ - tcg_gen_or_i64(xbh, xbh, sgm); \ - break; \ - case OP_NEG: \ - tcg_gen_xor_i64(xbh, xbh, sgm); \ - break; \ - case OP_CPSGN: \ - xah = tcg_temp_new_i64(); \ - xa = rA(ctx->opcode) + 32; \ - get_cpu_vsrh(tmp, xa); \ - tcg_gen_and_i64(xah, tmp, sgm); \ - tcg_gen_andc_i64(xbh, xbh, sgm); \ - tcg_gen_or_i64(xbh, xbh, xah); \ - tcg_temp_free_i64(xah); \ - break; \ - } \ - set_cpu_vsrh(xt, xbh); \ - set_cpu_vsrl(xt, xbl); \ - tcg_temp_free_i64(xbl); \ - tcg_temp_free_i64(xbh); \ - tcg_temp_free_i64(sgm); \ - tcg_temp_free_i64(tmp); \ -} - -VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP) -VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP) -VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP) -VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP) - -#define VSX_VECTOR_MOVE(name, op, sgn_mask) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_i64 xbh, xbl, sgm; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xbh = tcg_temp_new_i64(); \ - xbl = tcg_temp_new_i64(); \ - sgm = tcg_temp_new_i64(); \ - get_cpu_vsrh(xbh, xB(ctx->opcode)); \ - get_cpu_vsrl(xbl, xB(ctx->opcode)); \ - tcg_gen_movi_i64(sgm, sgn_mask); \ - switch (op) { \ - case OP_ABS: { \ - tcg_gen_andc_i64(xbh, xbh, sgm); \ - tcg_gen_andc_i64(xbl, xbl, sgm); \ - break; \ - } \ - case OP_NABS: { \ - tcg_gen_or_i64(xbh, xbh, sgm); \ - tcg_gen_or_i64(xbl, xbl, sgm); \ - break; \ - } \ - case OP_NEG: { \ - tcg_gen_xor_i64(xbh, xbh, sgm); \ - tcg_gen_xor_i64(xbl, xbl, sgm); \ - break; \ - } \ - case OP_CPSGN: { \ - TCGv_i64 xah = tcg_temp_new_i64(); \ - TCGv_i64 xal = tcg_temp_new_i64(); \ - get_cpu_vsrh(xah, xA(ctx->opcode)); \ - get_cpu_vsrl(xal, xA(ctx->opcode)); \ - tcg_gen_and_i64(xah, xah, sgm); \ - tcg_gen_and_i64(xal, xal, sgm); \ - tcg_gen_andc_i64(xbh, xbh, sgm); \ - tcg_gen_andc_i64(xbl, xbl, sgm); \ - tcg_gen_or_i64(xbh, xbh, xah); \ - tcg_gen_or_i64(xbl, xbl, xal); \ - tcg_temp_free_i64(xah); \ - tcg_temp_free_i64(xal); \ - break; \ - } \ - } \ - set_cpu_vsrh(xT(ctx->opcode), xbh); \ - set_cpu_vsrl(xT(ctx->opcode), xbl); \ - tcg_temp_free_i64(xbh); \ - tcg_temp_free_i64(xbl); \ - tcg_temp_free_i64(sgm); \ - } - -VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) -VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) -VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) -VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) -VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) -VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) -VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) -VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) - -#define VSX_CMP(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 ignored; \ - TCGv_ptr xt, xa, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xa = gen_vsr_ptr(xA(ctx->opcode)); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - if ((ctx->opcode >> (31 - 21)) & 1) { \ - gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \ - } else { \ - ignored = tcg_temp_new_i32(); \ - gen_helper_##name(ignored, cpu_env, xt, xa, xb); \ - tcg_temp_free_i32(ignored); \ - } \ - gen_helper_float_check_status(cpu_env); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(xb); \ -} - -VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) -VSX_CMP(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) -VSX_CMP(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) -VSX_CMP(xvcmpnedp, 0x0C, 0x0F, 0, PPC2_ISA300) -VSX_CMP(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) -VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) -VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) -VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) - -static void gen_xscvqpdp(DisasContext *ctx) -{ - TCGv_i32 opc; - TCGv_ptr xt, xb; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - opc = tcg_const_i32(ctx->opcode); - xt = gen_vsr_ptr(xT(ctx->opcode)); - xb = gen_vsr_ptr(xB(ctx->opcode)); - gen_helper_xscvqpdp(cpu_env, opc, xt, xb); - tcg_temp_free_i32(opc); - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xb); -} - -#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - gen_helper_##name(cpu_env, opc); \ - tcg_temp_free_i32(opc); \ -} - -#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr xt, xa, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xa = gen_vsr_ptr(xA(ctx->opcode)); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - gen_helper_##name(cpu_env, xt, xa, xb); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr xt, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - gen_helper_##name(cpu_env, xt, xb); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - TCGv_ptr xa, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - xa = gen_vsr_ptr(xA(ctx->opcode)); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - gen_helper_##name(cpu_env, opc, xa, xb); \ - tcg_temp_free_i32(opc); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - TCGv_ptr xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - gen_helper_##name(cpu_env, opc, xb); \ - tcg_temp_free_i32(opc); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - TCGv_ptr xt, xa, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ - xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ - xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ - gen_helper_##name(cpu_env, opc, xt, xa, xb); \ - tcg_temp_free_i32(opc); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - TCGv_ptr xt, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ - xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ - gen_helper_##name(cpu_env, opc, xt, xb); \ - tcg_temp_free_i32(opc); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i32 opc; \ - TCGv_ptr xa, xb; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - opc = tcg_const_i32(ctx->opcode); \ - xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ - xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ - gen_helper_##name(cpu_env, opc, xa, xb); \ - tcg_temp_free_i32(opc); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(xb); \ -} - -#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - get_cpu_vsrh(t0, xB(ctx->opcode)); \ - gen_helper_##name(t1, cpu_env, t0); \ - set_cpu_vsrh(xT(ctx->opcode), t1); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ -} - -GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xssubdp, 0x00, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsmulqp, 0x04, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsdivqp, 0x04, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2(xsredp, 0x14, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300) -GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_X2_AB(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) -GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) -GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) -GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) -GEN_VSX_HELPER_R2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300) -GEN_VSX_HELPER_R2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300) -GEN_VSX_HELPER_R2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300) -GEN_VSX_HELPER_R2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300) -GEN_VSX_HELPER_X2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300) -GEN_VSX_HELPER_R2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300) -GEN_VSX_HELPER_X2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) -GEN_VSX_HELPER_R2(xscvudqp, 0x04, 0x1A, 0x02, PPC2_ISA300) -GEN_VSX_HELPER_X2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) -GEN_VSX_HELPER_R2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300) -GEN_VSX_HELPER_R2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300) -GEN_VSX_HELPER_R2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300) -GEN_VSX_HELPER_R3(xssubqp, 0x04, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) -GEN_VSX_HELPER_X3(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_X2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) -GEN_VSX_HELPER_X1(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300) -GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300) - -GEN_VSX_HELPER_X3(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2_AB(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_X1(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) - -GEN_VSX_HELPER_X3(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvresp, 0x14, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X2_AB(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_X1(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xvminsp, 0x00, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300) -GEN_VSX_HELPER_X2(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300) -GEN_VSX_HELPER_X2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) -GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) -GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) - -#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr xt, xa, b, c; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xa = gen_vsr_ptr(xA(ctx->opcode)); \ - if (ctx->opcode & PPC_BIT32(25)) { \ - /* \ - * AxT + B \ - */ \ - b = gen_vsr_ptr(xT(ctx->opcode)); \ - c = gen_vsr_ptr(xB(ctx->opcode)); \ - } else { \ - /* \ - * AxB + T \ - */ \ - b = gen_vsr_ptr(xB(ctx->opcode)); \ - c = gen_vsr_ptr(xT(ctx->opcode)); \ - } \ - gen_helper_##name(cpu_env, xt, xa, b, c); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(b); \ - tcg_temp_free_ptr(c); \ -} - -GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207) -GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207) -GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207) -GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207) -GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvnmsubdp, 0x04, 0x1E, 0x1F, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvmaddsp, 0x04, 0x08, 0x09, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvmsubsp, 0x04, 0x0A, 0x0B, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvnmaddsp, 0x04, 0x18, 0x19, 0, PPC2_VSX) -GEN_VSX_HELPER_VSX_MADD(xvnmsubsp, 0x04, 0x1A, 0x1B, 0, PPC2_VSX) - -static void gen_xxbrd(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - tcg_gen_bswap64_i64(xth, xbh); - tcg_gen_bswap64_i64(xtl, xbl); - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xxbrh(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - gen_bswap16x8(xth, xtl, xbh, xbl); - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xxbrq(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - TCGv_i64 t0; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - t0 = tcg_temp_new_i64(); - - tcg_gen_bswap64_i64(t0, xbl); - tcg_gen_bswap64_i64(xtl, xbh); - set_cpu_vsrl(xT(ctx->opcode), xtl); - tcg_gen_mov_i64(xth, t0); - set_cpu_vsrh(xT(ctx->opcode), xth); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xxbrw(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - gen_bswap32x4(xth, xtl, xbh, xbl); - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -#define VSX_LOGICAL(name, vece, tcg_op) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \ - vsr_full_offset(xA(ctx->opcode)), \ - vsr_full_offset(xB(ctx->opcode)), 16, 16); \ - } - -VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and) -VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc) -VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or) -VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor) -VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor) -VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv) -VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand) -VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc) - -#define VSX_XXMRG(name, high) \ -static void glue(gen_, name)(DisasContext *ctx) \ - { \ - TCGv_i64 a0, a1, b0, b1, tmp; \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - a0 = tcg_temp_new_i64(); \ - a1 = tcg_temp_new_i64(); \ - b0 = tcg_temp_new_i64(); \ - b1 = tcg_temp_new_i64(); \ - tmp = tcg_temp_new_i64(); \ - if (high) { \ - get_cpu_vsrh(a0, xA(ctx->opcode)); \ - get_cpu_vsrh(a1, xA(ctx->opcode)); \ - get_cpu_vsrh(b0, xB(ctx->opcode)); \ - get_cpu_vsrh(b1, xB(ctx->opcode)); \ - } else { \ - get_cpu_vsrl(a0, xA(ctx->opcode)); \ - get_cpu_vsrl(a1, xA(ctx->opcode)); \ - get_cpu_vsrl(b0, xB(ctx->opcode)); \ - get_cpu_vsrl(b1, xB(ctx->opcode)); \ - } \ - tcg_gen_shri_i64(a0, a0, 32); \ - tcg_gen_shri_i64(b0, b0, 32); \ - tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \ - set_cpu_vsrh(xT(ctx->opcode), tmp); \ - tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \ - set_cpu_vsrl(xT(ctx->opcode), tmp); \ - tcg_temp_free_i64(a0); \ - tcg_temp_free_i64(a1); \ - tcg_temp_free_i64(b0); \ - tcg_temp_free_i64(b1); \ - tcg_temp_free_i64(tmp); \ - } - -VSX_XXMRG(xxmrghw, 1) -VSX_XXMRG(xxmrglw, 0) - -static void gen_xxsel(DisasContext *ctx) -{ - int rt = xT(ctx->opcode); - int ra = xA(ctx->opcode); - int rb = xB(ctx->opcode); - int rc = xC(ctx->opcode); - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc), - vsr_full_offset(rb), vsr_full_offset(ra), 16, 16); -} - -static void gen_xxspltw(DisasContext *ctx) -{ - int rt = xT(ctx->opcode); - int rb = xB(ctx->opcode); - int uim = UIM(ctx->opcode); - int tofs, bofs; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - - tofs = vsr_full_offset(rt); - bofs = vsr_full_offset(rb); - bofs += uim << MO_32; -#ifndef HOST_WORDS_BIG_ENDIAN - bofs ^= 8 | 4; -#endif - - tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16); -} - -#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff)) - -static void gen_xxspltib(DisasContext *ctx) -{ - uint8_t uim8 = IMM8(ctx->opcode); - int rt = xT(ctx->opcode); - - if (rt < 32) { - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - } - tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8); -} - -static void gen_xxsldwi(DisasContext *ctx) -{ - TCGv_i64 xth, xtl; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - - switch (SHW(ctx->opcode)) { - case 0: { - get_cpu_vsrh(xth, xA(ctx->opcode)); - get_cpu_vsrl(xtl, xA(ctx->opcode)); - break; - } - case 1: { - TCGv_i64 t0 = tcg_temp_new_i64(); - get_cpu_vsrh(xth, xA(ctx->opcode)); - tcg_gen_shli_i64(xth, xth, 32); - get_cpu_vsrl(t0, xA(ctx->opcode)); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_or_i64(xth, xth, t0); - get_cpu_vsrl(xtl, xA(ctx->opcode)); - tcg_gen_shli_i64(xtl, xtl, 32); - get_cpu_vsrh(t0, xB(ctx->opcode)); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_or_i64(xtl, xtl, t0); - tcg_temp_free_i64(t0); - break; - } - case 2: { - get_cpu_vsrl(xth, xA(ctx->opcode)); - get_cpu_vsrh(xtl, xB(ctx->opcode)); - break; - } - case 3: { - TCGv_i64 t0 = tcg_temp_new_i64(); - get_cpu_vsrl(xth, xA(ctx->opcode)); - tcg_gen_shli_i64(xth, xth, 32); - get_cpu_vsrh(t0, xB(ctx->opcode)); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_or_i64(xth, xth, t0); - get_cpu_vsrh(xtl, xB(ctx->opcode)); - tcg_gen_shli_i64(xtl, xtl, 32); - get_cpu_vsrl(t0, xB(ctx->opcode)); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_or_i64(xtl, xtl, t0); - tcg_temp_free_i64(t0); - break; - } - } - - set_cpu_vsrh(xT(ctx->opcode), xth); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); -} - -#define VSX_EXTRACT_INSERT(name) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv_ptr xt, xb; \ - TCGv_i32 t0; \ - TCGv_i64 t1; \ - uint8_t uimm = UIMM4(ctx->opcode); \ - \ - if (unlikely(!ctx->vsx_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VSXU); \ - return; \ - } \ - xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xb = gen_vsr_ptr(xB(ctx->opcode)); \ - t0 = tcg_temp_new_i32(); \ - t1 = tcg_temp_new_i64(); \ - /* \ - * uimm > 15 out of bound and for \ - * uimm > 12 handle as per hardware in helper \ - */ \ - if (uimm > 15) { \ - tcg_gen_movi_i64(t1, 0); \ - set_cpu_vsrh(xT(ctx->opcode), t1); \ - set_cpu_vsrl(xT(ctx->opcode), t1); \ - return; \ - } \ - tcg_gen_movi_i32(t0, uimm); \ - gen_helper_##name(cpu_env, xt, xb, t0); \ - tcg_temp_free_ptr(xb); \ - tcg_temp_free_ptr(xt); \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_i64(t1); \ -} - -VSX_EXTRACT_INSERT(xxextractuw) -VSX_EXTRACT_INSERT(xxinsertw) - -#ifdef TARGET_PPC64 -static void gen_xsxexpdp(DisasContext *ctx) -{ - TCGv rt = cpu_gpr[rD(ctx->opcode)]; - TCGv_i64 t0; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - get_cpu_vsrh(t0, xB(ctx->opcode)); - tcg_gen_extract_i64(rt, t0, 52, 11); - tcg_temp_free_i64(t0); -} - -static void gen_xsxexpqp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); - - tcg_gen_extract_i64(xth, xbh, 48, 15); - set_cpu_vsrh(rD(ctx->opcode) + 32, xth); - tcg_gen_movi_i64(xtl, 0); - set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); - - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); -} - -static void gen_xsiexpdp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv ra = cpu_gpr[rA(ctx->opcode)]; - TCGv rb = cpu_gpr[rB(ctx->opcode)]; - TCGv_i64 t0; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - xth = tcg_temp_new_i64(); - tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF); - tcg_gen_andi_i64(t0, rb, 0x7FF); - tcg_gen_shli_i64(t0, t0, 52); - tcg_gen_or_i64(xth, xth, t0); - set_cpu_vsrh(xT(ctx->opcode), xth); - /* dword[1] is undefined */ - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); -} - -static void gen_xsiexpqp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xah; - TCGv_i64 xal; - TCGv_i64 xbh; - TCGv_i64 t0; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xah = tcg_temp_new_i64(); - xal = tcg_temp_new_i64(); - get_cpu_vsrh(xah, rA(ctx->opcode) + 32); - get_cpu_vsrl(xal, rA(ctx->opcode) + 32); - xbh = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); - t0 = tcg_temp_new_i64(); - - tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF); - tcg_gen_andi_i64(t0, xbh, 0x7FFF); - tcg_gen_shli_i64(t0, t0, 48); - tcg_gen_or_i64(xth, xth, t0); - set_cpu_vsrh(rD(ctx->opcode) + 32, xth); - tcg_gen_mov_i64(xtl, xal); - set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); -} - -static void gen_xsxsigdp(DisasContext *ctx) -{ - TCGv rt = cpu_gpr[rD(ctx->opcode)]; - TCGv_i64 t0, t1, zr, nan, exp; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - exp = tcg_temp_new_i64(); - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(2047); - - get_cpu_vsrh(t1, xB(ctx->opcode)); - tcg_gen_extract_i64(exp, t1, 52, 11); - tcg_gen_movi_i64(t0, 0x0010000000000000); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - get_cpu_vsrh(t1, xB(ctx->opcode)); - tcg_gen_deposit_i64(rt, t0, t1, 0, 52); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); -} - -static void gen_xsxsigqp(DisasContext *ctx) -{ - TCGv_i64 t0, zr, nan, exp; - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); - get_cpu_vsrl(xbl, rB(ctx->opcode) + 32); - exp = tcg_temp_new_i64(); - t0 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(32767); - - tcg_gen_extract_i64(exp, xbh, 48, 15); - tcg_gen_movi_i64(t0, 0x0001000000000000); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_deposit_i64(xth, t0, xbh, 0, 48); - set_cpu_vsrh(rD(ctx->opcode) + 32, xth); - tcg_gen_mov_i64(xtl, xbl); - set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} -#endif - -static void gen_xviexpsp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xah; - TCGv_i64 xal; - TCGv_i64 xbh; - TCGv_i64 xbl; - TCGv_i64 t0; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xah = tcg_temp_new_i64(); - xal = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xah, xA(ctx->opcode)); - get_cpu_vsrl(xal, xA(ctx->opcode)); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - t0 = tcg_temp_new_i64(); - - tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF); - tcg_gen_andi_i64(t0, xbh, 0xFF000000FF); - tcg_gen_shli_i64(t0, t0, 23); - tcg_gen_or_i64(xth, xth, t0); - set_cpu_vsrh(xT(ctx->opcode), xth); - tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF); - tcg_gen_andi_i64(t0, xbl, 0xFF000000FF); - tcg_gen_shli_i64(t0, t0, 23); - tcg_gen_or_i64(xtl, xtl, t0); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xviexpdp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xah; - TCGv_i64 xal; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xah = tcg_temp_new_i64(); - xal = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xah, xA(ctx->opcode)); - get_cpu_vsrl(xal, xA(ctx->opcode)); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - tcg_gen_deposit_i64(xth, xah, xbh, 52, 11); - set_cpu_vsrh(xT(ctx->opcode), xth); - - tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xvxexpsp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - tcg_gen_shri_i64(xth, xbh, 23); - tcg_gen_andi_i64(xth, xth, 0xFF000000FF); - set_cpu_vsrh(xT(ctx->opcode), xth); - tcg_gen_shri_i64(xtl, xbl, 23); - tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -static void gen_xvxexpdp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - - tcg_gen_extract_i64(xth, xbh, 52, 11); - set_cpu_vsrh(xT(ctx->opcode), xth); - tcg_gen_extract_i64(xtl, xbl, 52, 11); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) - -static void gen_xvxsigdp(DisasContext *ctx) -{ - TCGv_i64 xth; - TCGv_i64 xtl; - TCGv_i64 xbh; - TCGv_i64 xbl; - TCGv_i64 t0, zr, nan, exp; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - xth = tcg_temp_new_i64(); - xtl = tcg_temp_new_i64(); - xbh = tcg_temp_new_i64(); - xbl = tcg_temp_new_i64(); - get_cpu_vsrh(xbh, xB(ctx->opcode)); - get_cpu_vsrl(xbl, xB(ctx->opcode)); - exp = tcg_temp_new_i64(); - t0 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(2047); - - tcg_gen_extract_i64(exp, xbh, 52, 11); - tcg_gen_movi_i64(t0, 0x0010000000000000); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_deposit_i64(xth, t0, xbh, 0, 52); - set_cpu_vsrh(xT(ctx->opcode), xth); - - tcg_gen_extract_i64(exp, xbl, 52, 11); - tcg_gen_movi_i64(t0, 0x0010000000000000); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); - tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52); - set_cpu_vsrl(xT(ctx->opcode), xtl); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); -} - -#undef GEN_XX2FORM -#undef GEN_XX3FORM -#undef GEN_XX2IFORM -#undef GEN_XX3_RC_FORM -#undef GEN_XX3FORM_DM -#undef VSX_LOGICAL diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc new file mode 100644 index 0000000000..7fd3942b84 --- /dev/null +++ b/target/ppc/translate/vsx-ops.c.inc @@ -0,0 +1,401 @@ +GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300), +#if defined(TARGET_PPC64) +GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300), +#endif + +GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300), +#if defined(TARGET_PPC64) +GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300), +#endif + +GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), +#if defined(TARGET_PPC64) +GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300), +#endif + +#define GEN_XX1FORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) + +#define GEN_XX2FORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) + +#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2) + +#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \ +GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2) + +#define GEN_XX3FORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) + +#define GEN_XX3FORM_NAME(name, opcname, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) + +#define GEN_XX2IFORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2) + +#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) + +#define GEN_XX3FORM_DM(name, opc2, opc3) \ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ +GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) + +#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \ +GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) + +#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \ +GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300) + +#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \ +GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval) + +GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0), +GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0), +GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x0), +GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0), + +GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), +GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), +GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), +GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), + +GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001), +GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001), +GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001), +GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), +GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001), +GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0), +GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001), +GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001), +GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001), +GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001), + +#ifdef TARGET_PPC64 +GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300), +GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001), +GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300), +GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001), +GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300), +GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001), +#endif + +GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300), +GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300), +GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001), + +GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300), +GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), +GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), +GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300), +GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), +GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300), + +/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */ +#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \ +GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \ +GEN_XX3FORM(name, opc2, opc3 | 1, fl2) + +GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300), +GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300), + +GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), +GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), +GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), +GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), +GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), +GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), +GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), +GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), + +GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), +GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0), +GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), +GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), +GEN_VSX_XFORM_300(xsmulqp, 0x04, 0x01, 0x0), +GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), +GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), +GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), +GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), +GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), +GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), +GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX), +GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX), +GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX), +GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX), +GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX), +GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300), +GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300), +GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300), +GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300), +GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300), +GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001), +GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), +GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), +GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), +GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), +GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), +GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), +GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300), +GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300), +GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300), +GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300), +GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), +GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), +GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), +GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300), +GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001), +GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), +GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), +GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), +GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), +GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), +GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), +GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), +GEN_VSX_XFORM_300_EO(xscvudqp, 0x04, 0x1A, 0x02, 0x00000001), +GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), +GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), +GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), +GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), +GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), +GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), + +GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), +GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), +GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), +GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), +GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0), +GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), +GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), +GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), +GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207), +GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207), +GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207), +GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), +GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), + +GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), +GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), +GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), +GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), +GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), +GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), +GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), +GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), +GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), +GEN_XX3FORM_NAME(xvmadddp, "xvmaddadp", 0x04, 0x0C, PPC2_VSX), +GEN_XX3FORM_NAME(xvmadddp, "xvmaddmdp", 0x04, 0x0D, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubdp, "xvmsubadp", 0x04, 0x0E, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubdp, "xvmsubmdp", 0x04, 0x0F, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddadp", 0x04, 0x1C, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddmdp", 0x04, 0x1D, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubadp", 0x04, 0x1E, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubmdp", 0x04, 0x1F, PPC2_VSX), +GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), +GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpnedp, 0x0C, 0x0F, PPC2_ISA300), +GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), +GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), +GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), +GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), +GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), +GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), +GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), +GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), +GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), +GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), +GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), +GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), +GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), +GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), + +GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), +GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), +GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), +GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), +GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), +GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), +GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), +GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), +GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), +GEN_XX3FORM_NAME(xvmaddsp, "xvmaddasp", 0x04, 0x08, PPC2_VSX), +GEN_XX3FORM_NAME(xvmaddsp, "xvmaddmsp", 0x04, 0x09, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubsp, "xvmsubasp", 0x04, 0x0A, PPC2_VSX), +GEN_XX3FORM_NAME(xvmsubsp, "xvmsubmsp", 0x04, 0x0B, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddasp", 0x04, 0x18, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddmsp", 0x04, 0x19, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubasp", 0x04, 0x1A, PPC2_VSX), +GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubmsp", 0x04, 0x1B, PPC2_VSX), +GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), +GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), +GEN_XX3_RC_FORM(xvcmpnesp, 0x0C, 0x0B, PPC2_ISA300), +GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), +GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), +GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), +GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), +GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), +GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), +GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), +GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), +GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), +GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), +GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), +GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), +GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), +GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), +GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300), +GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300), +GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300), +GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300), +GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300), +GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300), + +#define VSX_LOGICAL(name, opc2, opc3, fl2) \ +GEN_XX3FORM(name, opc2, opc3, fl2) + +VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), +VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), +VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), +VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), +VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), +VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), +VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), +VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), +GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), +GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), +GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300), +GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300), +GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), +GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300), +GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), +GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), +GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), + +#define GEN_XXSEL_ROW(opc3) \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ +GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ + +GEN_XXSEL_ROW(0x00) +GEN_XXSEL_ROW(0x01) +GEN_XXSEL_ROW(0x02) +GEN_XXSEL_ROW(0x03) +GEN_XXSEL_ROW(0x04) +GEN_XXSEL_ROW(0x05) +GEN_XXSEL_ROW(0x06) +GEN_XXSEL_ROW(0x07) +GEN_XXSEL_ROW(0x08) +GEN_XXSEL_ROW(0x09) +GEN_XXSEL_ROW(0x0A) +GEN_XXSEL_ROW(0x0B) +GEN_XXSEL_ROW(0x0C) +GEN_XXSEL_ROW(0x0D) +GEN_XXSEL_ROW(0x0E) +GEN_XXSEL_ROW(0x0F) +GEN_XXSEL_ROW(0x10) +GEN_XXSEL_ROW(0x11) +GEN_XXSEL_ROW(0x12) +GEN_XXSEL_ROW(0x13) +GEN_XXSEL_ROW(0x14) +GEN_XXSEL_ROW(0x15) +GEN_XXSEL_ROW(0x16) +GEN_XXSEL_ROW(0x17) +GEN_XXSEL_ROW(0x18) +GEN_XXSEL_ROW(0x19) +GEN_XXSEL_ROW(0x1A) +GEN_XXSEL_ROW(0x1B) +GEN_XXSEL_ROW(0x1C) +GEN_XXSEL_ROW(0x1D) +GEN_XXSEL_ROW(0x1E) +GEN_XXSEL_ROW(0x1F) + +GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c deleted file mode 100644 index 7fd3942b84..0000000000 --- a/target/ppc/translate/vsx-ops.inc.c +++ /dev/null @@ -1,401 +0,0 @@ -GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300), -#endif - -GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), -GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300), -#endif - -GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), -GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300), -#endif - -#define GEN_XX1FORM(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) - -#define GEN_XX2FORM(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) - -#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2) - -#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \ -GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2) - -#define GEN_XX3FORM(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) - -#define GEN_XX3FORM_NAME(name, opcname, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, opcname, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) - -#define GEN_XX2IFORM(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2) - -#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) - -#define GEN_XX3FORM_DM(name, opc2, opc3) \ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ -GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) - -#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \ -GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) - -#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \ -GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300) - -#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \ -GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval) - -GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0), -GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0), -GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x0), -GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0), - -GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), -GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), -GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), -GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), - -GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001), -GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001), -GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001), -GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0), -GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001), - -#ifdef TARGET_PPC64 -GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300), -GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001), -GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300), -GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001), -GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300), -GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001), -#endif - -GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300), -GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300), -GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001), - -GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300), -GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), -GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), -GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300), -GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), -GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300), - -/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */ -#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \ -GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \ -GEN_XX3FORM(name, opc2, opc3 | 1, fl2) - -GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300), -GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300), - -GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), -GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), -GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), -GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), -GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), -GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), -GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), -GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), - -GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), -GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0), -GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), -GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), -GEN_VSX_XFORM_300(xsmulqp, 0x04, 0x01, 0x0), -GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), -GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), -GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), -GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), -GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), -GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), -GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX), -GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX), -GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX), -GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX), -GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX), -GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX), -GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX), -GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX), -GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300), -GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300), -GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300), -GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300), -GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300), -GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001), -GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), -GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), -GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), -GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), -GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), -GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), -GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300), -GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300), -GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300), -GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300), -GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), -GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), -GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), -GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300), -GEN_VSX_XFORM_300_EO(xscvsdqp, 0x04, 0x1A, 0x0A, 0x00000001), -GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), -GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), -GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), -GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), -GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), -GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), -GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), -GEN_VSX_XFORM_300_EO(xscvudqp, 0x04, 0x1A, 0x02, 0x00000001), -GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), -GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), -GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), -GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), -GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), -GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), - -GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), -GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), -GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), -GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), -GEN_VSX_XFORM_300(xsdivqp, 0x04, 0x11, 0x0), -GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), -GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), -GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), -GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), -GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207), -GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207), -GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207), -GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207), -GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207), -GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207), -GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207), -GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207), -GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), -GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), - -GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), -GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), -GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), -GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), -GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), -GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), -GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), -GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), -GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), -GEN_XX3FORM_NAME(xvmadddp, "xvmaddadp", 0x04, 0x0C, PPC2_VSX), -GEN_XX3FORM_NAME(xvmadddp, "xvmaddmdp", 0x04, 0x0D, PPC2_VSX), -GEN_XX3FORM_NAME(xvmsubdp, "xvmsubadp", 0x04, 0x0E, PPC2_VSX), -GEN_XX3FORM_NAME(xvmsubdp, "xvmsubmdp", 0x04, 0x0F, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddadp", 0x04, 0x1C, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmadddp, "xvnmaddmdp", 0x04, 0x1D, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubadp", 0x04, 0x1E, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmsubdp, "xvnmsubmdp", 0x04, 0x1F, PPC2_VSX), -GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), -GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpnedp, 0x0C, 0x0F, PPC2_ISA300), -GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), -GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), -GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), -GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), -GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), -GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), -GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), -GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), -GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), -GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), -GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), -GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), -GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), -GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), - -GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), -GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), -GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), -GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), -GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), -GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), -GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), -GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), -GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), -GEN_XX3FORM_NAME(xvmaddsp, "xvmaddasp", 0x04, 0x08, PPC2_VSX), -GEN_XX3FORM_NAME(xvmaddsp, "xvmaddmsp", 0x04, 0x09, PPC2_VSX), -GEN_XX3FORM_NAME(xvmsubsp, "xvmsubasp", 0x04, 0x0A, PPC2_VSX), -GEN_XX3FORM_NAME(xvmsubsp, "xvmsubmsp", 0x04, 0x0B, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddasp", 0x04, 0x18, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmaddsp, "xvnmaddmsp", 0x04, 0x19, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubasp", 0x04, 0x1A, PPC2_VSX), -GEN_XX3FORM_NAME(xvnmsubsp, "xvnmsubmsp", 0x04, 0x1B, PPC2_VSX), -GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), -GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), -GEN_XX3_RC_FORM(xvcmpnesp, 0x0C, 0x0B, PPC2_ISA300), -GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), -GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), -GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), -GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), -GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), -GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), -GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), -GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), -GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), -GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), -GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), -GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), -GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), -GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), -GEN_XX2FORM_EO(xxbrh, 0x16, 0x1D, 0x07, PPC2_ISA300), -GEN_XX2FORM_EO(xxbrw, 0x16, 0x1D, 0x0F, PPC2_ISA300), -GEN_XX2FORM_EO(xxbrd, 0x16, 0x1D, 0x17, PPC2_ISA300), -GEN_XX2FORM_EO(xvcvhpsp, 0x16, 0x1D, 0x18, PPC2_ISA300), -GEN_XX2FORM_EO(xvcvsphp, 0x16, 0x1D, 0x19, PPC2_ISA300), -GEN_XX2FORM_EO(xxbrq, 0x16, 0x1D, 0x1F, PPC2_ISA300), - -#define VSX_LOGICAL(name, opc2, opc3, fl2) \ -GEN_XX3FORM(name, opc2, opc3, fl2) - -VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), -VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), -VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), -VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), -VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), -VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), -VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), -VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), -GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), -GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), -GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300), -GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300), -GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), -GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300), -GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), -GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), -GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), - -#define GEN_XXSEL_ROW(opc3) \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ - -GEN_XXSEL_ROW(0x00) -GEN_XXSEL_ROW(0x01) -GEN_XXSEL_ROW(0x02) -GEN_XXSEL_ROW(0x03) -GEN_XXSEL_ROW(0x04) -GEN_XXSEL_ROW(0x05) -GEN_XXSEL_ROW(0x06) -GEN_XXSEL_ROW(0x07) -GEN_XXSEL_ROW(0x08) -GEN_XXSEL_ROW(0x09) -GEN_XXSEL_ROW(0x0A) -GEN_XXSEL_ROW(0x0B) -GEN_XXSEL_ROW(0x0C) -GEN_XXSEL_ROW(0x0D) -GEN_XXSEL_ROW(0x0E) -GEN_XXSEL_ROW(0x0F) -GEN_XXSEL_ROW(0x10) -GEN_XXSEL_ROW(0x11) -GEN_XXSEL_ROW(0x12) -GEN_XXSEL_ROW(0x13) -GEN_XXSEL_ROW(0x14) -GEN_XXSEL_ROW(0x15) -GEN_XXSEL_ROW(0x16) -GEN_XXSEL_ROW(0x17) -GEN_XXSEL_ROW(0x18) -GEN_XXSEL_ROW(0x19) -GEN_XXSEL_ROW(0x1A) -GEN_XXSEL_ROW(0x1B) -GEN_XXSEL_ROW(0x1C) -GEN_XXSEL_ROW(0x1D) -GEN_XXSEL_ROW(0x1E) -GEN_XXSEL_ROW(0x1F) - -GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc new file mode 100644 index 0000000000..7e66822b5d --- /dev/null +++ b/target/ppc/translate_init.c.inc @@ -0,0 +1,10956 @@ +/* + * PowerPC CPU initialization for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "disas/dis-asm.h" +#include "exec/gdbstub.h" +#include "kvm_ppc.h" +#include "sysemu/arch_init.h" +#include "sysemu/cpus.h" +#include "sysemu/hw_accel.h" +#include "sysemu/tcg.h" +#include "cpu-models.h" +#include "mmu-hash32.h" +#include "mmu-hash64.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "qemu/qemu-print.h" +#include "qapi/error.h" +#include "qapi/qmp/qnull.h" +#include "qapi/visitor.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/ppc.h" +#include "mmu-book3s-v3.h" +#include "sysemu/qtest.h" +#include "qemu/cutils.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" +#include "qapi/qapi-commands-machine-target.h" + +/* #define PPC_DUMP_CPU */ +/* #define PPC_DEBUG_SPR */ +/* #define PPC_DUMP_SPR_ACCESSES */ +/* #define USE_APPLE_GDB */ + +/* + * Generic callbacks: + * do nothing but store/retrieve spr value + */ +static void spr_load_dump_spr(int sprn) +{ +#ifdef PPC_DUMP_SPR_ACCESSES + TCGv_i32 t0 = tcg_const_i32(sprn); + gen_helper_load_dump_spr(cpu_env, t0); + tcg_temp_free_i32(t0); +#endif +} + +static void spr_read_generic(DisasContext *ctx, int gprn, int sprn) +{ + gen_load_spr(cpu_gpr[gprn], sprn); + spr_load_dump_spr(sprn); +} + +static void spr_store_dump_spr(int sprn) +{ +#ifdef PPC_DUMP_SPR_ACCESSES + TCGv_i32 t0 = tcg_const_i32(sprn); + gen_helper_store_dump_spr(cpu_env, t0); + tcg_temp_free_i32(t0); +#endif +} + +static void spr_write_generic(DisasContext *ctx, int sprn, int gprn) +{ + gen_store_spr(sprn, cpu_gpr[gprn]); + spr_store_dump_spr(sprn); +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) +{ +#ifdef TARGET_PPC64 + TCGv t0 = tcg_temp_new(); + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); + spr_store_dump_spr(sprn); +#else + spr_write_generic(ctx, sprn, gprn); +#endif +} + +static void spr_write_clear(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + gen_load_spr(t0, sprn); + tcg_gen_neg_tl(t1, cpu_gpr[gprn]); + tcg_gen_and_tl(t0, t0, t1); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) +{ +} + +#endif + +/* SPR common to all PowerPC */ +/* XER */ +static void spr_read_xer(DisasContext *ctx, int gprn, int sprn) +{ + gen_read_xer(ctx, cpu_gpr[gprn]); +} + +static void spr_write_xer(DisasContext *ctx, int sprn, int gprn) +{ + gen_write_xer(cpu_gpr[gprn]); +} + +/* LR */ +static void spr_read_lr(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); +} + +static void spr_write_lr(DisasContext *ctx, int sprn, int gprn) +{ + tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); +} + +/* CFAR */ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); +} + +static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) +{ + tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); +} +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ + +/* CTR */ +static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); +} + +static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) +{ + tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); +} + +/* User read access to SPR */ +/* USPRx */ +/* UMMCRx */ +/* UPMCx */ +/* USIA */ +/* UDECR */ +static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) +{ + gen_load_spr(cpu_gpr[gprn], sprn + 0x10); +} + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) +{ + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); +} +#endif + +/* SPR common to all non-embedded PowerPC */ +/* DECR */ +#if !defined(CONFIG_USER_ONLY) +static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_load_decr(cpu_gpr[gprn], cpu_env); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_stop_exception(ctx); + } +} + +static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_stop_exception(ctx); + } +} +#endif + +/* SPR common to all non-embedded PowerPC, except 601 */ +/* Time base */ +static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +ATTRIBUTE_UNUSED +static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); +} + +ATTRIBUTE_UNUSED +static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +ATTRIBUTE_UNUSED +static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); +} + +ATTRIBUTE_UNUSED +static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); +} + +#if defined(TARGET_PPC64) +ATTRIBUTE_UNUSED +static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_purr(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); +} + +/* HDECR */ +static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + gen_stop_exception(ctx); + } +} + +static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); +} + +#endif +#endif + +#if !defined(CONFIG_USER_ONLY) +/* IBAT0U...IBAT0U */ +/* IBAT0L...IBAT7L */ +static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); +} + +static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, + IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); +} + +static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +/* DBAT0U...DBAT7U */ +/* DBAT0L...DBAT7L */ +static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, + DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); +} + +static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, + DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); +} + +static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +/* SDR1 */ +static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); +} + +#if defined(TARGET_PPC64) +/* 64 bits PowerPC specific SPRs */ +/* PIDR */ +static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); +} + +static void spr_read_hior(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); +} + +static void spr_write_hior(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); + tcg_temp_free(t0); +} +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); +} + +/* DPDES */ +static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); +} +#endif +#endif + +/* PowerPC 601 specific registers */ +/* RTC */ +static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); +} + +static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); + /* Must stop the translation as endianness may have changed */ + gen_stop_exception(ctx); +} +#endif + +/* Unified bats */ +#if !defined(CONFIG_USER_ONLY) +static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); +} + +static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); + gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); + gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} +#endif + +/* PowerPC 40x specific registers */ +#if !defined(CONFIG_USER_ONLY) +static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) +{ + gen_store_spr(sprn, cpu_gpr[gprn]); + gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); + /* We must stop translation as we may have rebooted */ + gen_stop_exception(ctx); +} + +static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); +} +#endif + +/* PowerPC 403 specific registers */ +/* PBL1 / PBU1 / PBL2 / PBU2 */ +#if !defined(CONFIG_USER_ONLY) +static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) +{ + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); +} + +static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); + gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} + +static void spr_write_pir(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); + gen_store_spr(SPR_PIR, t0); + tcg_temp_free(t0); +} +#endif + +/* SPE specific registers */ +static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); + tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); + tcg_temp_free_i32(t0); +} + +static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); + tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); + tcg_temp_free_i32(t0); +} + +#if !defined(CONFIG_USER_ONLY) +/* Callback used to write the exception vector base */ +static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); +} + +static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) +{ + int sprn_offs; + + if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { + sprn_offs = sprn - SPR_BOOKE_IVOR0; + } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { + sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; + } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { + sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; + } else { + printf("Trying to write an unknown exception vector %d %03x\n", + sprn, sprn); + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); + return; + } + + TCGv t0 = tcg_temp_new(); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); +} +#endif + +static inline void vscr_init(CPUPPCState *env, uint32_t val) +{ + /* Altivec always uses round-to-nearest */ + set_float_rounding_mode(float_round_nearest_even, &env->vec_status); + helper_mtvscr(env, val); +} + +#ifdef CONFIG_USER_ONLY +#define spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, initial_value) +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, initial_value) +#else +#if !defined(CONFIG_KVM) +#define spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, oea_read, oea_write, initial_value) +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, initial_value) +#else +#define spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, oea_read, oea_write, \ + one_reg_id, initial_value) +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + one_reg_id, initial_value) \ + _spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + one_reg_id, initial_value) +#endif +#endif + +#define spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, initial_value) \ + spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, 0, initial_value) + +#define spr_register_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + initial_value) \ + spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + 0, initial_value) + +static inline void _spr_register(CPUPPCState *env, int num, + const char *name, + void (*uea_read)(DisasContext *ctx, + int gprn, int sprn), + void (*uea_write)(DisasContext *ctx, + int sprn, int gprn), +#if !defined(CONFIG_USER_ONLY) + + void (*oea_read)(DisasContext *ctx, + int gprn, int sprn), + void (*oea_write)(DisasContext *ctx, + int sprn, int gprn), + void (*hea_read)(DisasContext *opaque, + int gprn, int sprn), + void (*hea_write)(DisasContext *opaque, + int sprn, int gprn), +#endif +#if defined(CONFIG_KVM) + uint64_t one_reg_id, +#endif + target_ulong initial_value) +{ + ppc_spr_t *spr; + + spr = &env->spr_cb[num]; + if (spr->name != NULL || env->spr[num] != 0x00000000 || +#if !defined(CONFIG_USER_ONLY) + spr->oea_read != NULL || spr->oea_write != NULL || +#endif + spr->uea_read != NULL || spr->uea_write != NULL) { + printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); + exit(1); + } +#if defined(PPC_DEBUG_SPR) + printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, + name, initial_value); +#endif + spr->name = name; + spr->uea_read = uea_read; + spr->uea_write = uea_write; +#if !defined(CONFIG_USER_ONLY) + spr->oea_read = oea_read; + spr->oea_write = oea_write; + spr->hea_read = hea_read; + spr->hea_write = hea_write; +#endif +#if defined(CONFIG_KVM) + spr->one_reg_id = one_reg_id, +#endif + env->spr[num] = spr->default_value = initial_value; +} + +/* Generic PowerPC SPRs */ +static void gen_spr_generic(CPUPPCState *env) +{ + /* Integer processing */ + spr_register(env, SPR_XER, "XER", + &spr_read_xer, &spr_write_xer, + &spr_read_xer, &spr_write_xer, + 0x00000000); + /* Branch contol */ + spr_register(env, SPR_LR, "LR", + &spr_read_lr, &spr_write_lr, + &spr_read_lr, &spr_write_lr, + 0x00000000); + spr_register(env, SPR_CTR, "CTR", + &spr_read_ctr, &spr_write_ctr, + &spr_read_ctr, &spr_write_ctr, + 0x00000000); + /* Interrupt processing */ + spr_register(env, SPR_SRR0, "SRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SRR1, "SRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Processor control */ + spr_register(env, SPR_SPRG0, "SPRG0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG1, "SPRG1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG2, "SPRG2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG3, "SPRG3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR common to all non-embedded PowerPC, including 601 */ +static void gen_spr_ne_601(CPUPPCState *env) +{ + /* Exception processing */ + spr_register_kvm(env, SPR_DSISR, "DSISR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DSISR, 0x00000000); + spr_register_kvm(env, SPR_DAR, "DAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DAR, 0x00000000); + /* Timer */ + spr_register(env, SPR_DECR, "DECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_decr, &spr_write_decr, + 0x00000000); +} + +/* Storage Description Register 1 */ +static void gen_spr_sdr1(CPUPPCState *env) +{ +#ifndef CONFIG_USER_ONLY + if (env->has_hv_mode) { + /* + * SDR1 is a hypervisor resource on CPUs which have a + * hypervisor mode + */ + spr_register_hv(env, SPR_SDR1, "SDR1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_sdr1, + 0x00000000); + } else { + spr_register(env, SPR_SDR1, "SDR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_sdr1, + 0x00000000); + } +#endif +} + +/* BATs 0-3 */ +static void gen_low_BATs(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register(env, SPR_IBAT0U, "IBAT0U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatu, + 0x00000000); + spr_register(env, SPR_IBAT0L, "IBAT0L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatl, + 0x00000000); + spr_register(env, SPR_IBAT1U, "IBAT1U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatu, + 0x00000000); + spr_register(env, SPR_IBAT1L, "IBAT1L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatl, + 0x00000000); + spr_register(env, SPR_IBAT2U, "IBAT2U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatu, + 0x00000000); + spr_register(env, SPR_IBAT2L, "IBAT2L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatl, + 0x00000000); + spr_register(env, SPR_IBAT3U, "IBAT3U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatu, + 0x00000000); + spr_register(env, SPR_IBAT3L, "IBAT3L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat, &spr_write_ibatl, + 0x00000000); + spr_register(env, SPR_DBAT0U, "DBAT0U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatu, + 0x00000000); + spr_register(env, SPR_DBAT0L, "DBAT0L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatl, + 0x00000000); + spr_register(env, SPR_DBAT1U, "DBAT1U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatu, + 0x00000000); + spr_register(env, SPR_DBAT1L, "DBAT1L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatl, + 0x00000000); + spr_register(env, SPR_DBAT2U, "DBAT2U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatu, + 0x00000000); + spr_register(env, SPR_DBAT2L, "DBAT2L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatl, + 0x00000000); + spr_register(env, SPR_DBAT3U, "DBAT3U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatu, + 0x00000000); + spr_register(env, SPR_DBAT3L, "DBAT3L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat, &spr_write_dbatl, + 0x00000000); + env->nb_BATs += 4; +#endif +} + +/* BATs 4-7 */ +static void gen_high_BATs(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register(env, SPR_IBAT4U, "IBAT4U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatu_h, + 0x00000000); + spr_register(env, SPR_IBAT4L, "IBAT4L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatl_h, + 0x00000000); + spr_register(env, SPR_IBAT5U, "IBAT5U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatu_h, + 0x00000000); + spr_register(env, SPR_IBAT5L, "IBAT5L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatl_h, + 0x00000000); + spr_register(env, SPR_IBAT6U, "IBAT6U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatu_h, + 0x00000000); + spr_register(env, SPR_IBAT6L, "IBAT6L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatl_h, + 0x00000000); + spr_register(env, SPR_IBAT7U, "IBAT7U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatu_h, + 0x00000000); + spr_register(env, SPR_IBAT7L, "IBAT7L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_ibat_h, &spr_write_ibatl_h, + 0x00000000); + spr_register(env, SPR_DBAT4U, "DBAT4U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatu_h, + 0x00000000); + spr_register(env, SPR_DBAT4L, "DBAT4L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatl_h, + 0x00000000); + spr_register(env, SPR_DBAT5U, "DBAT5U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatu_h, + 0x00000000); + spr_register(env, SPR_DBAT5L, "DBAT5L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatl_h, + 0x00000000); + spr_register(env, SPR_DBAT6U, "DBAT6U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatu_h, + 0x00000000); + spr_register(env, SPR_DBAT6L, "DBAT6L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatl_h, + 0x00000000); + spr_register(env, SPR_DBAT7U, "DBAT7U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatu_h, + 0x00000000); + spr_register(env, SPR_DBAT7L, "DBAT7L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dbat_h, &spr_write_dbatl_h, + 0x00000000); + env->nb_BATs += 4; +#endif +} + +/* Generic PowerPC time base */ +static void gen_tbl(CPUPPCState *env) +{ + spr_register(env, SPR_VTBL, "TBL", + &spr_read_tbl, SPR_NOACCESS, + &spr_read_tbl, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_TBL, "TBL", + &spr_read_tbl, SPR_NOACCESS, + &spr_read_tbl, &spr_write_tbl, + 0x00000000); + spr_register(env, SPR_VTBU, "TBU", + &spr_read_tbu, SPR_NOACCESS, + &spr_read_tbu, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_TBU, "TBU", + &spr_read_tbu, SPR_NOACCESS, + &spr_read_tbu, &spr_write_tbu, + 0x00000000); +} + +/* Softare table search registers */ +static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) +{ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = nb_tlbs; + env->nb_ways = nb_ways; + env->id_tlbs = 1; + env->tlb_type = TLB_6XX; + spr_register(env, SPR_DMISS, "DMISS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_DCMP, "DCMP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_HASH1, "HASH1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_HASH2, "HASH2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_IMISS, "IMISS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_ICMP, "ICMP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_RPA, "RPA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#endif +} + +/* SPR common to MPC755 and G2 */ +static void gen_spr_G2_755(CPUPPCState *env) +{ + /* SGPRs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR common to all 7xx PowerPC implementations */ +static void gen_spr_7xx(CPUPPCState *env) +{ + /* Breakpoints */ + /* XXX : not implemented */ + spr_register_kvm(env, SPR_DABR, "DABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DABR, 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Cache management */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTC, "ICTC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Performance monitors */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_MMCR0, "MMCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_MMCR1, "MMCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC1, "PMC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC2, "PMC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC3, "PMC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC4, "PMC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_SIAR, "SIAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC1, "UPMC1", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC2, "UPMC2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC3, "UPMC3", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC4, "UPMC4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_USIAR, "USIAR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +#ifdef TARGET_PPC64 +#ifndef CONFIG_USER_ONLY +static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + /* + * Note, the HV=1 PR=0 case is handled earlier by simply using + * spr_write_generic for HV mode in the SPR table + */ + + /* Build insertion mask into t1 based on context */ + if (ctx->pr) { + gen_load_spr(t1, SPR_UAMOR); + } else { + gen_load_spr(t1, SPR_AMOR); + } + + /* Mask new bits into t2 */ + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); + + /* Load AMR and clear new bits in t0 */ + gen_load_spr(t0, SPR_AMR); + tcg_gen_andc_tl(t0, t0, t1); + + /* Or'in new bits and write it out */ + tcg_gen_or_tl(t0, t0, t2); + gen_store_spr(SPR_AMR, t0); + spr_store_dump_spr(SPR_AMR); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} + +static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + /* + * Note, the HV=1 case is handled earlier by simply using + * spr_write_generic for HV mode in the SPR table + */ + + /* Build insertion mask into t1 based on context */ + gen_load_spr(t1, SPR_AMOR); + + /* Mask new bits into t2 */ + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); + + /* Load AMR and clear new bits in t0 */ + gen_load_spr(t0, SPR_UAMOR); + tcg_gen_andc_tl(t0, t0, t1); + + /* Or'in new bits and write it out */ + tcg_gen_or_tl(t0, t0, t2); + gen_store_spr(SPR_UAMOR, t0); + spr_store_dump_spr(SPR_UAMOR); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} + +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + + /* + * Note, the HV=1 case is handled earlier by simply using + * spr_write_generic for HV mode in the SPR table + */ + + /* Build insertion mask into t1 based on context */ + gen_load_spr(t1, SPR_AMOR); + + /* Mask new bits into t2 */ + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); + + /* Load AMR and clear new bits in t0 */ + gen_load_spr(t0, SPR_IAMR); + tcg_gen_andc_tl(t0, t0, t1); + + /* Or'in new bits and write it out */ + tcg_gen_or_tl(t0, t0, t2); + gen_store_spr(SPR_IAMR, t0); + spr_store_dump_spr(SPR_IAMR); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} +#endif /* CONFIG_USER_ONLY */ + +static void gen_spr_amr(CPUPPCState *env) +{ +#ifndef CONFIG_USER_ONLY + /* + * Virtual Page Class Key protection + * + * The AMR is accessible either via SPR 13 or SPR 29. 13 is + * userspace accessible, 29 is privileged. So we only need to set + * the kvm ONE_REG id on one of them, we use 29 + */ + spr_register(env, SPR_UAMR, "UAMR", + &spr_read_generic, &spr_write_amr, + &spr_read_generic, &spr_write_amr, + 0); + spr_register_kvm_hv(env, SPR_AMR, "AMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_amr, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_AMR, 0); + spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_uamor, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_UAMOR, 0); + spr_register_hv(env, SPR_AMOR, "AMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); +#endif /* !CONFIG_USER_ONLY */ +} + +static void gen_spr_iamr(CPUPPCState *env) +{ +#ifndef CONFIG_USER_ONLY + spr_register_kvm_hv(env, SPR_IAMR, "IAMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_iamr, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_IAMR, 0); +#endif /* !CONFIG_USER_ONLY */ +} +#endif /* TARGET_PPC64 */ + +#ifndef CONFIG_USER_ONLY +static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_fixup_thrm(cpu_env); + gen_load_spr(cpu_gpr[gprn], sprn); + spr_load_dump_spr(sprn); +} +#endif /* !CONFIG_USER_ONLY */ + +static void gen_spr_thrm(CPUPPCState *env) +{ + /* Thermal management */ + /* XXX : not implemented */ + spr_register(env, SPR_THRM1, "THRM1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_thrm, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_THRM2, "THRM2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_thrm, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_THRM3, "THRM3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_thrm, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 604 implementation */ +static void gen_spr_604(CPUPPCState *env) +{ + /* Processor identification */ + spr_register(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* Breakpoints */ + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register_kvm(env, SPR_DABR, "DABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DABR, 0x00000000); + /* Performance counters */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_MMCR0, "MMCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC1, "PMC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC2, "PMC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_SIAR, "SIAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_SDA, "SDA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 603 implementation */ +static void gen_spr_603(CPUPPCState *env) +{ + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Breakpoints */ + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + +} + +/* SPR specific to PowerPC G2 implementation */ +static void gen_spr_G2(CPUPPCState *env) +{ + /* Memory base address */ + /* MBAR */ + /* XXX : not implemented */ + spr_register(env, SPR_MBAR, "MBAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Exception processing */ + spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Breakpoints */ + /* XXX : not implemented */ + spr_register(env, SPR_DABR, "DABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_DABR2, "DABR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR2, "IABR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IBCR, "IBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_DBCR, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 602 implementation */ +static void gen_spr_602(CPUPPCState *env) +{ + /* ESA registers */ + /* XXX : not implemented */ + spr_register(env, SPR_SER, "SER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_SEBR, "SEBR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_ESASRR, "ESASRR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Floating point status */ + /* XXX : not implemented */ + spr_register(env, SPR_SP, "SP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_LT, "LT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Watchdog timer */ + /* XXX : not implemented */ + spr_register(env, SPR_TCR, "TCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Interrupt base */ + spr_register(env, SPR_IBR, "IBR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 601 implementation */ +static void gen_spr_601(CPUPPCState *env) +{ + /* Multiplication/division register */ + /* MQ */ + spr_register(env, SPR_MQ, "MQ", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* RTC registers */ + spr_register(env, SPR_601_RTCU, "RTCU", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_601_rtcu, + 0x00000000); + spr_register(env, SPR_601_VRTCU, "RTCU", + &spr_read_601_rtcu, SPR_NOACCESS, + &spr_read_601_rtcu, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_601_RTCL, "RTCL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_601_rtcl, + 0x00000000); + spr_register(env, SPR_601_VRTCL, "RTCL", + &spr_read_601_rtcl, SPR_NOACCESS, + &spr_read_601_rtcl, SPR_NOACCESS, + 0x00000000); + /* Timer */ +#if 0 /* ? */ + spr_register(env, SPR_601_UDECR, "UDECR", + &spr_read_decr, SPR_NOACCESS, + &spr_read_decr, SPR_NOACCESS, + 0x00000000); +#endif + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + spr_register(env, SPR_IBAT0U, "IBAT0U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatu, + 0x00000000); + spr_register(env, SPR_IBAT0L, "IBAT0L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatl, + 0x00000000); + spr_register(env, SPR_IBAT1U, "IBAT1U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatu, + 0x00000000); + spr_register(env, SPR_IBAT1L, "IBAT1L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatl, + 0x00000000); + spr_register(env, SPR_IBAT2U, "IBAT2U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatu, + 0x00000000); + spr_register(env, SPR_IBAT2L, "IBAT2L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatl, + 0x00000000); + spr_register(env, SPR_IBAT3U, "IBAT3U", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatu, + 0x00000000); + spr_register(env, SPR_IBAT3L, "IBAT3L", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_601_ubat, &spr_write_601_ubatl, + 0x00000000); + env->nb_BATs = 4; +#endif +} + +static void gen_spr_74xx(CPUPPCState *env) +{ + /* Processor identification */ + spr_register(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_74XX_MMCR2, "MMCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX: not implemented */ + spr_register(env, SPR_BAMR, "BAMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MSSCR0, "MSSCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Altivec */ + spr_register(env, SPR_VRSAVE, "VRSAVE", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Not strictly an SPR */ + vscr_init(env, 0x00010000); +} + +static void gen_l3_ctrl(CPUPPCState *env) +{ + /* L3CR */ + /* XXX : not implemented */ + spr_register(env, SPR_L3CR, "L3CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR0, "L3ITCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3PM */ + /* XXX : not implemented */ + spr_register(env, SPR_L3PM, "L3PM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) +{ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = nb_tlbs; + env->nb_ways = nb_ways; + env->id_tlbs = 1; + env->tlb_type = TLB_6XX; + /* XXX : not implemented */ + spr_register(env, SPR_PTEHI, "PTEHI", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_PTELO, "PTELO", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_TLBMISS, "TLBMISS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#endif +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); +} + +static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); +} + +static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); +} + +static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t0 = tcg_const_i32(sprn); + gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); + tcg_temp_free_i32(t0); +} +static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); +} +static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); +} + +#endif + +static void gen_spr_usprg3(CPUPPCState *env) +{ + spr_register(env, SPR_USPRG3, "USPRG3", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); +} + +static void gen_spr_usprgh(CPUPPCState *env) +{ + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); +} + +/* PowerPC BookE SPR */ +static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask) +{ + const char *ivor_names[64] = { + "IVOR0", "IVOR1", "IVOR2", "IVOR3", + "IVOR4", "IVOR5", "IVOR6", "IVOR7", + "IVOR8", "IVOR9", "IVOR10", "IVOR11", + "IVOR12", "IVOR13", "IVOR14", "IVOR15", + "IVOR16", "IVOR17", "IVOR18", "IVOR19", + "IVOR20", "IVOR21", "IVOR22", "IVOR23", + "IVOR24", "IVOR25", "IVOR26", "IVOR27", + "IVOR28", "IVOR29", "IVOR30", "IVOR31", + "IVOR32", "IVOR33", "IVOR34", "IVOR35", + "IVOR36", "IVOR37", "IVOR38", "IVOR39", + "IVOR40", "IVOR41", "IVOR42", "IVOR43", + "IVOR44", "IVOR45", "IVOR46", "IVOR47", + "IVOR48", "IVOR49", "IVOR50", "IVOR51", + "IVOR52", "IVOR53", "IVOR54", "IVOR55", + "IVOR56", "IVOR57", "IVOR58", "IVOR59", + "IVOR60", "IVOR61", "IVOR62", "IVOR63", + }; +#define SPR_BOOKE_IVORxx (-1) + int ivor_sprn[64] = { + SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, + SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, + SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, + SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, + SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, + SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, + }; + int i; + + /* Interrupt processing */ + spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Debug */ + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC1, "IAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC2, "IAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DAC1, "DAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DAC2, "DAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + 0x00000000); + spr_register(env, SPR_BOOKE_DEAR, "DEAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_ESR, "ESR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_IVPR, "IVPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_excp_prefix, + 0x00000000); + /* Exception vectors */ + for (i = 0; i < 64; i++) { + if (ivor_mask & (1ULL << i)) { + if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { + fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); + exit(1); + } + spr_register(env, ivor_sprn[i], ivor_names[i], + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_excp_vector, + 0x00000000); + } + } + spr_register(env, SPR_BOOKE_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_pid, + 0x00000000); + spr_register(env, SPR_BOOKE_TCR, "TCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tcr, + 0x00000000); + spr_register(env, SPR_BOOKE_TSR, "TSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tsr, + 0x00000000); + /* Timer */ + spr_register(env, SPR_DECR, "DECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_decr, &spr_write_decr, + 0x00000000); + spr_register(env, SPR_BOOKE_DECAR, "DECAR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_generic, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_USPRG0, "USPRG0", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, + uint32_t maxsize, uint32_t flags, + uint32_t nentries) +{ + return (assoc << TLBnCFG_ASSOC_SHIFT) | + (minsize << TLBnCFG_MINSIZE_SHIFT) | + (maxsize << TLBnCFG_MAXSIZE_SHIFT) | + flags | nentries; +} + +/* BookE 2.06 storage control registers */ +static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, + uint32_t *tlbncfg, uint32_t mmucfg) +{ +#if !defined(CONFIG_USER_ONLY) + const char *mas_names[8] = { + "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", + }; + int mas_sprn[8] = { + SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, + SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, + }; + int i; + + /* TLB assist registers */ + /* XXX : not implemented */ + for (i = 0; i < 8; i++) { + void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = + &spr_write_generic32; + if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { + uea_write = &spr_write_generic; + } + if (mas_mask & (1 << i)) { + spr_register(env, mas_sprn[i], mas_names[i], + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, uea_write, + 0x00000000); + } + } + if (env->nb_pids > 1) { + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_PID1, "PID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_pid, + 0x00000000); + } + if (env->nb_pids > 2) { + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_PID2, "PID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_pid, + 0x00000000); + } + + spr_register(env, SPR_BOOKE_EPLC, "EPLC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_eplc, + 0x00000000); + spr_register(env, SPR_BOOKE_EPSC, "EPSC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_epsc, + 0x00000000); + + /* XXX : not implemented */ + spr_register(env, SPR_MMUCFG, "MMUCFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + mmucfg); + switch (env->nb_ways) { + case 4: + spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + tlbncfg[3]); + /* Fallthru */ + case 3: + spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + tlbncfg[2]); + /* Fallthru */ + case 2: + spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + tlbncfg[1]); + /* Fallthru */ + case 1: + spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + tlbncfg[0]); + /* Fallthru */ + case 0: + default: + break; + } +#endif + + gen_spr_usprgh(env); +} + +/* SPR specific to PowerPC 440 implementation */ +static void gen_spr_440(CPUPPCState *env) +{ + /* Cache control */ + /* XXX : not implemented */ + spr_register(env, SPR_440_DNV0, "DNV0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DNV1, "DNV1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DNV2, "DNV2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DNV3, "DNV3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DTV0, "DTV0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DTV1, "DTV1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DTV2, "DTV2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DTV3, "DTV3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DVLIM, "DVLIM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_INV0, "INV0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_INV1, "INV1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_INV2, "INV2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_INV3, "INV3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_ITV0, "ITV0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_ITV1, "ITV1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_ITV2, "ITV2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_ITV3, "ITV3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_IVLIM, "IVLIM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Cache debug */ + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_DBDR, "DBDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Processor control */ + spr_register(env, SPR_4xx_CCR0, "CCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_440_RSTCFG, "RSTCFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* Storage control */ + spr_register(env, SPR_440_MMUCR, "MMUCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR shared between PowerPC 40x implementations */ +static void gen_spr_40x(CPUPPCState *env) +{ + /* Cache */ + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCCR, "DCCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_ICCR, "ICCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* Exception */ + spr_register(env, SPR_40x_DEAR, "DEAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_ESR, "ESR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_EVPR, "EVPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_excp_prefix, + 0x00000000); + spr_register(env, SPR_40x_SRR2, "SRR2", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_SRR3, "SRR3", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Timers */ + spr_register(env, SPR_40x_PIT, "PIT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_40x_pit, &spr_write_40x_pit, + 0x00000000); + spr_register(env, SPR_40x_TCR, "TCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tcr, + 0x00000000); + spr_register(env, SPR_40x_TSR, "TSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke_tsr, + 0x00000000); +} + +/* SPR specific to PowerPC 405 implementation */ +static void gen_spr_405(CPUPPCState *env) +{ + /* MMU */ + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_4xx_CCR0, "CCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00700000); + /* Debug interface */ + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBCR0, "DBCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_DBCR1, "DBCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + /* Last reset was system reset */ + 0x00000300); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC1, "DAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_DAC2, "DAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_DVC1, "DVC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_DVC2, "DVC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC1, "IAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_IAC2, "IAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Storage control */ + /* XXX: TODO: not implemented */ + spr_register(env, SPR_405_SLER, "SLER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_sler, + 0x00000000); + spr_register(env, SPR_40x_ZPR, "ZPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_405_SU0R, "SU0R", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* SPRG */ + spr_register(env, SPR_USPRG0, "USPRG0", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + spr_read_generic, &spr_write_generic, + 0x00000000); + gen_spr_usprgh(env); +} + +/* SPR shared between PowerPC 401 & 403 implementations */ +static void gen_spr_401_403(CPUPPCState *env) +{ + /* Time base */ + spr_register(env, SPR_403_VTBL, "TBL", + &spr_read_tbl, SPR_NOACCESS, + &spr_read_tbl, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_403_TBL, "TBL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbl, + 0x00000000); + spr_register(env, SPR_403_VTBU, "TBU", + &spr_read_tbu, SPR_NOACCESS, + &spr_read_tbu, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_403_TBU, "TBU", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbu, + 0x00000000); + /* Debug */ + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_403_CDBCR, "CDBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 401 implementation */ +static void gen_spr_401(CPUPPCState *env) +{ + /* Debug interface */ + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBCR0, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + /* Last reset was system reset */ + 0x00000300); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC1, "DAC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC1, "IAC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Storage control */ + /* XXX: TODO: not implemented */ + spr_register(env, SPR_405_SLER, "SLER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_sler, + 0x00000000); + /* not emulated, as QEMU never does speculative access */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_401x2(CPUPPCState *env) +{ + gen_spr_401(env); + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_ZPR, "ZPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC 403 implementation */ +static void gen_spr_403(CPUPPCState *env) +{ + /* Debug interface */ + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBCR0, "DBCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + /* Last reset was system reset */ + 0x00000300); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC1, "DAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC2, "DAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC1, "IAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC2, "IAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_403_real(CPUPPCState *env) +{ + spr_register(env, SPR_403_PBL1, "PBL1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_403_pbr, &spr_write_403_pbr, + 0x00000000); + spr_register(env, SPR_403_PBU1, "PBU1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_403_pbr, &spr_write_403_pbr, + 0x00000000); + spr_register(env, SPR_403_PBL2, "PBL2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_403_pbr, &spr_write_403_pbr, + 0x00000000); + spr_register(env, SPR_403_PBU2, "PBU2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_403_pbr, &spr_write_403_pbr, + 0x00000000); +} + +static void gen_spr_403_mmu(CPUPPCState *env) +{ + /* MMU */ + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_ZPR, "ZPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* SPR specific to PowerPC compression coprocessor extension */ +static void gen_spr_compress(CPUPPCState *env) +{ + /* XXX : not implemented */ + spr_register(env, SPR_401_SKR, "SKR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_5xx_8xx(CPUPPCState *env) +{ + /* Exception processing */ + spr_register_kvm(env, SPR_DSISR, "DSISR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DSISR, 0x00000000); + spr_register_kvm(env, SPR_DAR, "DAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DAR, 0x00000000); + /* Timer */ + spr_register(env, SPR_DECR, "DECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_decr, &spr_write_decr, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_EIE, "EIE", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_EID, "EID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_NRI, "NRI", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPA, "CMPA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPB, "CMPB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPC, "CMPC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPD, "CMPD", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_ECR, "ECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_DER, "DER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_COUNTA, "COUNTA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_COUNTB, "COUNTB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPE, "CMPE", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPF, "CMPF", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPG, "CMPG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_CMPH, "CMPH", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_BAR, "BAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_DPDR, "DPDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_IMMR, "IMMR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_5xx(CPUPPCState *env) +{ + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_RCPU_FPECR, "FPECR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_8xx(CPUPPCState *env) +{ + /* XXX : not implemented */ + spr_register(env, SPR_MPC_IC_CST, "IC_CST", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_DC_CST, "DC_CST", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_AP, "MI_AP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_AP, "MD_AP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_TW, "MD_TW", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +/* + * AMR => SPR 29 (Power 2.04) + * CTRL => SPR 136 (Power 2.04) + * CTRL => SPR 152 (Power 2.04) + * SCOMC => SPR 276 (64 bits ?) + * SCOMD => SPR 277 (64 bits ?) + * TBU40 => SPR 286 (Power 2.04 hypv) + * HSPRG0 => SPR 304 (Power 2.04 hypv) + * HSPRG1 => SPR 305 (Power 2.04 hypv) + * HDSISR => SPR 306 (Power 2.04 hypv) + * HDAR => SPR 307 (Power 2.04 hypv) + * PURR => SPR 309 (Power 2.04 hypv) + * HDEC => SPR 310 (Power 2.04 hypv) + * HIOR => SPR 311 (hypv) + * RMOR => SPR 312 (970) + * HRMOR => SPR 313 (Power 2.04 hypv) + * HSRR0 => SPR 314 (Power 2.04 hypv) + * HSRR1 => SPR 315 (Power 2.04 hypv) + * LPIDR => SPR 317 (970) + * EPR => SPR 702 (Power 2.04 emb) + * perf => 768-783 (Power 2.04) + * perf => 784-799 (Power 2.04) + * PPR => SPR 896 (Power 2.04) + * DABRX => 1015 (Power 2.04 hypv) + * FPECR => SPR 1022 (?) + * ... and more (thermal management, performance counters, ...) + */ + +/*****************************************************************************/ +/* Exception vectors models */ +static void init_excp_4xx_real(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; + env->ivor_mask = 0x0000FFF0UL; + env->ivpr_mask = 0xFFFF0000UL; + /* Hardware reset vector */ + env->hreset_vector = 0xFFFFFFFCUL; +#endif +} + +static void init_excp_4xx_softmmu(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; + env->ivor_mask = 0x0000FFF0UL; + env->ivpr_mask = 0xFFFF0000UL; + /* Hardware reset vector */ + env->hreset_vector = 0xFFFFFFFCUL; +#endif +} + +static void init_excp_MPC5xx(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; + env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; + env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; + env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; + env->ivor_mask = 0x0000FFF0UL; + env->ivpr_mask = 0xFFFF0000UL; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_MPC8xx(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; + env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; + env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; + env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; + env->ivor_mask = 0x0000FFF0UL; + env->ivpr_mask = 0xFFFF0000UL; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_G2(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; + env->ivor_mask = 0x0000FFF7UL; + env->ivpr_mask = ivpr_mask; + /* Hardware reset vector */ + env->hreset_vector = 0xFFFFFFFCUL; +#endif +} + +static void init_excp_BookE(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; + env->ivor_mask = 0x0000FFF0UL; + env->ivpr_mask = 0xFFFF0000UL; + /* Hardware reset vector */ + env->hreset_vector = 0xFFFFFFFCUL; +#endif +} + +static void init_excp_601(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_602(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* XXX: exception prefix has a special behavior on 602 */ + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; + env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_603(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_604(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_7x0(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_750cl(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_750cx(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +/* XXX: Check if this is correct */ +static void init_excp_7x5(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_7400(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +static void init_excp_7450(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; + env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; + env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; + env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; + /* Hardware reset vector */ + env->hreset_vector = 0x00000100UL; +#endif +} + +#if defined(TARGET_PPC64) +static void init_excp_970(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; + env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; + env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; + env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; + env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; + /* Hardware reset vector */ + env->hreset_vector = 0x0000000000000100ULL; +#endif +} + +static void init_excp_POWER7(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; + env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; + env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; + env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; + env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; + env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; + env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; + env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; + env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; + env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; + env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; + env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; + env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; + env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; + env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; + env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; + env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; + env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; + env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; + /* Hardware reset vector */ + env->hreset_vector = 0x0000000000000100ULL; +#endif +} + +static void init_excp_POWER8(CPUPPCState *env) +{ + init_excp_POWER7(env); + +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; + env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; + env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; + env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; +#endif +} + +static void init_excp_POWER9(CPUPPCState *env) +{ + init_excp_POWER8(env); + +#if !defined(CONFIG_USER_ONLY) + env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; + env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000; +#endif +} + +static void init_excp_POWER10(CPUPPCState *env) +{ + init_excp_POWER9(env); +} + +#endif + +/*****************************************************************************/ +/* Power management enable checks */ +static int check_pow_none(CPUPPCState *env) +{ + return 0; +} + +static int check_pow_nocheck(CPUPPCState *env) +{ + return 1; +} + +static int check_pow_hid0(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & 0x00E00000) { + return 1; + } + + return 0; +} + +static int check_pow_hid0_74xx(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & 0x00600000) { + return 1; + } + + return 0; +} + +static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) +{ + return true; +} + +#ifdef TARGET_PPC64 +static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) +{ + return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); +} +#endif + +/*****************************************************************************/ +/* PowerPC implementations definitions */ + +#define POWERPC_FAMILY(_name) \ + static void \ + glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ + \ + static const TypeInfo \ + glue(glue(ppc_, _name), _cpu_family_type_info) = { \ + .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ + .parent = TYPE_POWERPC_CPU, \ + .abstract = true, \ + .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ + }; \ + \ + static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ + { \ + type_register_static( \ + &glue(glue(ppc_, _name), _cpu_family_type_info)); \ + } \ + \ + type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ + \ + static void glue(glue(ppc_, _name), _cpu_family_class_init) + +static void init_proc_401(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401(env); + init_excp_4xx_real(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(401)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 401"; + pcc->init_proc = init_proc_401; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_WRTEE | PPC_DCR | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << MSR_KEY) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_DE) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_REAL; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_401x2(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401x2(env); + gen_spr_compress(env); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_4xx_softmmu(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 401x2"; + pcc->init_proc = init_proc_401x2; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << 20) | + (1ull << MSR_KEY) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_DE) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_401x3(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401(env); + gen_spr_401x2(env); + gen_spr_compress(env); + init_excp_4xx_softmmu(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 401x3"; + pcc->init_proc = init_proc_401x3; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << 20) | + (1ull << MSR_KEY) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_IOP480(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_401x2(env); + gen_spr_compress(env); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_4xx_softmmu(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "IOP480"; + pcc->init_proc = init_proc_IOP480; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << 20) | + (1ull << MSR_KEY) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_DE) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_403(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_403(env); + gen_spr_403_real(env); + init_excp_4xx_real(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(403)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 403"; + pcc->init_proc = init_proc_403; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_PE) | + (1ull << MSR_PX) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_REAL; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_403GCX(CPUPPCState *env) +{ + gen_spr_40x(env); + gen_spr_401_403(env); + gen_spr_403(env); + gen_spr_403_real(env); + gen_spr_403_mmu(env); + /* Bus access control */ + /* not emulated, as QEMU never does speculative access */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_4xx_softmmu(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 403 GCX"; + pcc->init_proc = init_proc_403GCX; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | + PPC_4xx_COMMON | PPC_40x_EXCP; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_ME) | + (1ull << MSR_PE) | + (1ull << MSR_PX) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_401; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_405(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_40x(env); + gen_spr_405(env); + /* Bus access control */ + /* not emulated, as QEMU never does speculative access */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_4xx_softmmu(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(8, 12, 16, 20); + SET_WDT_PERIOD(16, 20, 24, 28); +} + +POWERPC_FAMILY(405)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 405"; + pcc->init_proc = init_proc_405; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | + PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_SOFT_4xx; + pcc->excp_model = POWERPC_EXCP_40x; + pcc->bus_model = PPC_FLAGS_INPUT_405; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_440EP(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env, 0x000000000000FFFFULL); + gen_spr_440(env); + gen_spr_usprgh(env); + /* Processor identification */ + spr_register(env, SPR_BOOKE_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC1, "DVC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC2, "DVC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_CCR1, "CCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_BookE(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(20, 24, 28, 32); +} + +POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440 EP"; + pcc->init_proc = init_proc_440EP; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_DCR | PPC_WRTEE | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 460 EX"; + pcc->init_proc = init_proc_440EP; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_440GP(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env, 0x000000000000FFFFULL); + gen_spr_440(env); + gen_spr_usprgh(env); + /* Processor identification */ + spr_register(env, SPR_BOOKE_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC1, "DVC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC2, "DVC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_BookE(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* XXX: TODO: allocate internal IRQ controller */ + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(20, 24, 28, 32); +} + +POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440 GP"; + pcc->init_proc = init_proc_440GP; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_440x4(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env, 0x000000000000FFFFULL); + gen_spr_440(env); + gen_spr_usprgh(env); + /* Processor identification */ + spr_register(env, SPR_BOOKE_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC1, "DVC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC2, "DVC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_BookE(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* XXX: TODO: allocate internal IRQ controller */ + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(20, 24, 28, 32); +} + +POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440x4"; + pcc->init_proc = init_proc_440x4; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_WRTEE | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_440x5(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env, 0x000000000000FFFFULL); + gen_spr_440(env); + gen_spr_usprgh(env); + /* Processor identification */ + spr_register(env, SPR_BOOKE_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC1, "DVC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_DVC2, "DVC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_440_CCR1, "CCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_BookE(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + ppc40x_irq_init(env_archcpu(env)); + + SET_FIT_PERIOD(12, 16, 20, 24); + SET_WDT_PERIOD(20, 24, 28, 32); +} + +POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440x5"; + pcc->init_proc = init_proc_440x5; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_DCR | PPC_WRTEE | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440x5 with double precision FPU"; + pcc->init_proc = init_proc_440x5; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_FLOAT | PPC_FLOAT_FSQRT | + PPC_FLOAT_STFIWX | + PPC_DCR | PPC_WRTEE | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_MPC5xx(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_5xx_8xx(env); + gen_spr_5xx(env); + init_excp_MPC5xx(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* XXX: TODO: allocate internal IRQ controller */ +} + +POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "Freescale 5xx cores (aka RCPU)"; + pcc->init_proc = init_proc_MPC5xx; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_MEM_EIEIO | PPC_MEM_SYNC | + PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | + PPC_MFTB; + pcc->msr_mask = (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_REAL; + pcc->excp_model = POWERPC_EXCP_603; + pcc->bus_model = PPC_FLAGS_INPUT_RCPU; + pcc->bfd_mach = bfd_mach_ppc_505; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_MPC8xx(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_5xx_8xx(env); + gen_spr_8xx(env); + init_excp_MPC8xx(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* XXX: TODO: allocate internal IRQ controller */ +} + +POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; + pcc->init_proc = init_proc_MPC8xx; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_MEM_EIEIO | PPC_MEM_SYNC | + PPC_CACHE_ICBI | PPC_MFTB; + pcc->msr_mask = (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_MPC8xx; + pcc->excp_model = POWERPC_EXCP_603; + pcc->bus_model = PPC_FLAGS_INPUT_RCPU; + pcc->bfd_mach = bfd_mach_ppc_860; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_BUS_CLK; +} + +/* Freescale 82xx cores (aka PowerQUICC-II) */ + +static void init_proc_G2(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_G2_755(env); + gen_spr_G2(env); + /* Time base */ + gen_tbl(env); + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation register */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_G2(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC G2"; + pcc->init_proc = init_proc_G2; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_AL) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_G2; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_ec603e; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_G2LE(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_G2_755(env); + gen_spr_G2(env); + /* Time base */ + gen_tbl(env); + /* External access control */ + /* XXX : not implemented */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation register */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_G2(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC G2LE"; + pcc->init_proc = init_proc_G2LE; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_AL) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_G2; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_ec603e; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e200(CPUPPCState *env) +{ + /* Time base */ + gen_tbl(env); + gen_spr_BookE(env, 0x000000070000FFFFULL); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", + &spr_read_spefscr, &spr_write_spefscr, + &spr_read_spefscr, &spr_write_spefscr, + 0x00000000); + /* Memory management */ + gen_spr_BookE206(env, 0x0000005D, NULL, 0); + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_BUCSR, "BUCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_CTXCR, "CTXCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_DBCNT, "DBCNT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_DBCR3, "DBCR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC3, "IAC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_IAC4, "IAC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MMUCSR0, "MMUCSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); /* TOFIX */ + spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 64; + env->nb_ways = 1; + env->id_tlbs = 0; + env->tlb_type = TLB_EMB; +#endif + init_excp_e200(env, 0xFFFF0000UL); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* XXX: TODO: allocate internal IRQ controller */ +} + +POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e200 core"; + pcc->init_proc = init_proc_e200; + pcc->check_pow = check_pow_hid0; + /* + * XXX: unimplemented instructions: + * dcblc + * dcbtlst + * dcbtstls + * icblc + * icbtls + * tlbivax + * all SPE multiply-accumulate instructions + */ + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | + PPC_SPE | PPC_SPE_SINGLE | + PPC_WRTEE | PPC_RFDI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | + PPC_BOOKE; + pcc->msr_mask = (1ull << MSR_UCLE) | + (1ull << MSR_SPE) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_860; + pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | + POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e300(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_603(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Breakpoints */ + /* XXX : not implemented */ + spr_register(env, SPR_DABR, "DABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_DABR2, "DABR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IABR2, "IABR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_IBCR, "IBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_DBCR, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_603(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e300 core"; + pcc->init_proc = init_proc_e300; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_AL) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_603; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_603; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) +{ + TCGv val = tcg_temp_new(); + tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); + gen_store_spr(SPR_BOOKE_MAS3, val); + tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); + gen_store_spr(SPR_BOOKE_MAS7, val); + tcg_temp_free(val); +} + +static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) +{ + TCGv mas7 = tcg_temp_new(); + TCGv mas3 = tcg_temp_new(); + gen_load_spr(mas7, SPR_BOOKE_MAS7); + tcg_gen_shli_tl(mas7, mas7, 32); + gen_load_spr(mas3, SPR_BOOKE_MAS3); + tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); + tcg_temp_free(mas3); + tcg_temp_free(mas7); +} + +#endif + +enum fsl_e500_version { + fsl_e500v1, + fsl_e500v2, + fsl_e500mc, + fsl_e5500, + fsl_e6500, +}; + +static void init_proc_e500(CPUPPCState *env, int version) +{ + uint32_t tlbncfg[2]; + uint64_t ivor_mask; + uint64_t ivpr_mask = 0xFFFF0000ULL; + uint32_t l1cfg0 = 0x3800 /* 8 ways */ + | 0x0020; /* 32 kb */ + uint32_t l1cfg1 = 0x3800 /* 8 ways */ + | 0x0020; /* 32 kb */ + uint32_t mmucfg = 0; +#if !defined(CONFIG_USER_ONLY) + int i; +#endif + + /* Time base */ + gen_tbl(env); + /* + * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't + * complain when accessing them. + * gen_spr_BookE(env, 0x0000000F0000FD7FULL); + */ + switch (version) { + case fsl_e500v1: + case fsl_e500v2: + default: + ivor_mask = 0x0000000F0000FFFFULL; + break; + case fsl_e500mc: + case fsl_e5500: + ivor_mask = 0x000003FE0000FFFFULL; + break; + case fsl_e6500: + ivor_mask = 0x000003FF0000FFFFULL; + break; + } + gen_spr_BookE(env, ivor_mask); + gen_spr_usprg3(env); + /* Processor identification */ + spr_register(env, SPR_BOOKE_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", + &spr_read_spefscr, &spr_write_spefscr, + &spr_read_spefscr, &spr_write_spefscr, + 0x00000000); +#if !defined(CONFIG_USER_ONLY) + /* Memory management */ + env->nb_pids = 3; + env->nb_ways = 2; + env->id_tlbs = 0; + switch (version) { + case fsl_e500v1: + tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); + tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); + break; + case fsl_e500v2: + tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); + tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); + break; + case fsl_e500mc: + case fsl_e5500: + tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); + tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); + break; + case fsl_e6500: + mmucfg = 0x6510B45; + env->nb_pids = 1; + tlbncfg[0] = 0x08052400; + tlbncfg[1] = 0x40028040; + break; + default: + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", + env->spr[SPR_PVR]); + } +#endif + /* Cache sizes */ + switch (version) { + case fsl_e500v1: + case fsl_e500v2: + env->dcache_line_size = 32; + env->icache_line_size = 32; + break; + case fsl_e500mc: + case fsl_e5500: + env->dcache_line_size = 64; + env->icache_line_size = 64; + l1cfg0 |= 0x1000000; /* 64 byte cache block size */ + l1cfg1 |= 0x1000000; /* 64 byte cache block size */ + break; + case fsl_e6500: + env->dcache_line_size = 32; + env->icache_line_size = 32; + l1cfg0 |= 0x0F83820; + l1cfg1 |= 0x0B83820; + break; + default: + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", + env->spr[SPR_PVR]); + } + gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_BBEAR, "BBEAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_BBTAR, "BBTAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_MCAR, "MCAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_BOOKE_MCSR, "MCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_NPIDR, "NPIDR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_BUCSR, "BUCSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + l1cfg0); + spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + l1cfg1); + spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_e500_l1csr0, + 0x00000000); + spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_e500_l1csr1, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_MMUCSR0, "MMUCSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_booke206_mmucsr0, + 0x00000000); + spr_register(env, SPR_BOOKE_EPR, "EPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + /* XXX better abstract into Emb.xxx features */ + if ((version == fsl_e5500) || (version == fsl_e6500)) { + spr_register(env, SPR_BOOKE_EPCR, "EPCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_mas73, &spr_write_mas73, + 0x00000000); + ivpr_mask = (target_ulong)~0xFFFFULL; + } + + if (version == fsl_e6500) { + /* Thread identification */ + spr_register(env, SPR_TIR, "TIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000004); + spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x7FFFFFFC); + } + +#if !defined(CONFIG_USER_ONLY) + env->nb_tlb = 0; + env->tlb_type = TLB_MAS; + for (i = 0; i < BOOKE206_MAX_TLBN; i++) { + env->nb_tlb += booke206_tlb_size(env, i); + } +#endif + + init_excp_e200(env, ivpr_mask); + /* Allocate hardware IRQ controller */ + ppce500_irq_init(env_archcpu(env)); +} + +static void init_proc_e500v1(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e500v1); +} + +POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e500v1 core"; + pcc->init_proc = init_proc_e500v1; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | + PPC_SPE | PPC_SPE_SINGLE | + PPC_WRTEE | PPC_RFDI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + pcc->insns_flags2 = PPC2_BOOKE206; + pcc->msr_mask = (1ull << MSR_UCLE) | + (1ull << MSR_SPE) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_860; + pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | + POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e500v2(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e500v2); +} + +POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e500v2 core"; + pcc->init_proc = init_proc_e500v2; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | + PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | + PPC_WRTEE | PPC_RFDI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + pcc->insns_flags2 = PPC2_BOOKE206; + pcc->msr_mask = (1ull << MSR_UCLE) | + (1ull << MSR_SPE) | + (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_860; + pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | + POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e500mc(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e500mc); +} + +POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e500mc core"; + pcc->init_proc = init_proc_e500mc; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | + PPC_WRTEE | PPC_RFDI | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_FLOAT | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | + PPC_FLOAT_STFIWX | PPC_WAIT | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; + pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; + pcc->msr_mask = (1ull << MSR_GS) | + (1ull << MSR_UCLE) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PX) | + (1ull << MSR_RI); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + /* FIXME: figure out the correct flag for e500mc */ + pcc->bfd_mach = bfd_mach_ppc_e500; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +#ifdef TARGET_PPC64 +static void init_proc_e5500(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e5500); +} + +POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e5500 core"; + pcc->init_proc = init_proc_e5500; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | + PPC_WRTEE | PPC_RFDI | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_FLOAT | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | + PPC_FLOAT_STFIWX | PPC_WAIT | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | + PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; + pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | + PPC2_FP_CVT_S64; + pcc->msr_mask = (1ull << MSR_CM) | + (1ull << MSR_GS) | + (1ull << MSR_UCLE) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PX) | + (1ull << MSR_RI); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + /* FIXME: figure out the correct flag for e5500 */ + pcc->bfd_mach = bfd_mach_ppc_e500; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e6500(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e6500); +} + +POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "e6500 core"; + pcc->init_proc = init_proc_e6500; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | + PPC_WRTEE | PPC_RFDI | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_FLOAT | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | + PPC_FLOAT_STFIWX | PPC_WAIT | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | + PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; + pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | + PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; + pcc->msr_mask = (1ull << MSR_CM) | + (1ull << MSR_GS) | + (1ull << MSR_UCLE) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IS) | + (1ull << MSR_DS) | + (1ull << MSR_PX) | + (1ull << MSR_RI) | + (1ull << MSR_VR); + pcc->mmu_model = POWERPC_MMU_BOOKE206; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_e500; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; +} + +#endif + +/* Non-embedded PowerPC */ + +#define POWERPC_MSRR_601 (0x0000000000001040ULL) + +static void init_proc_601(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_601(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_hid0_601, + 0x80010080); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID5, "HID5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + init_excp_601(env); + /* + * XXX: beware that dcache line size is 64 + * but dcbz uses 32 bytes "sectors" + * XXX: this breaks clcs instruction ! + */ + env->dcache_line_size = 32; + env->icache_line_size = 64; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(601)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 601"; + pcc->init_proc = init_proc_601; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | + PPC_FLOAT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_601; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_601; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_601; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; +} + +#define POWERPC_MSRR_601v (0x0000000000001040ULL) + +static void init_proc_601v(CPUPPCState *env) +{ + init_proc_601(env); + /* XXX : not implemented */ + spr_register(env, SPR_601_HID15, "HID15", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 601v"; + pcc->init_proc = init_proc_601v; + pcc->check_pow = check_pow_none; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | + PPC_FLOAT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_601; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_601; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; +} + +static void init_proc_602(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_602(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_602(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(602)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 602"; + pcc->init_proc = init_proc_602; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_602_SPEC; + pcc->msr_mask = (1ull << MSR_VSX) | + (1ull << MSR_SA) | + (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + /* XXX: 602 MMU is quite specific. Should add a special case */ + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_602; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_602; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_603(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_603(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_603(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(603)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 603"; + pcc->init_proc = init_proc_603; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_603; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_603; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_603E(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_603(env); + /* Time base */ + gen_tbl(env); + /* hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_603(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 603e"; + pcc->init_proc = init_proc_603E; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_TGPR) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_603E; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_ec603e; + pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_604(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_604(env); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + init_excp_604(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(604)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 604"; + pcc->init_proc = init_proc_604; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_604; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_604; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_604E(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_604(env); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_MMCR1, "MMCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC3, "PMC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC4, "PMC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + init_excp_604(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 604E"; + pcc->init_proc = init_proc_604E; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_604; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_604; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_740(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + init_excp_7x0(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(740)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 740"; + pcc->init_proc = init_proc_740; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_750(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* + * XXX: high BATs are also present but are known to be bugged on + * die version 1.x + */ + init_excp_7x0(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(750)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 750"; + pcc->init_proc = init_proc_750; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_750cl(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + /* Those registers are fake on 750CL */ + spr_register(env, SPR_THRM1, "THRM1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_THRM2, "THRM2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_THRM3, "THRM3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX: not implemented */ + spr_register(env, SPR_750_TDCL, "TDCL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_750_TDCH, "TDCH", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* DMA */ + /* XXX : not implemented */ + spr_register(env, SPR_750_WPAR, "WPAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_750_DMAL, "DMAL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_750_DMAU, "DMAU", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750CL_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750CL_HID4, "HID4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Quantization registers */ + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR0, "GQR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR1, "GQR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR2, "GQR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR3, "GQR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR4, "GQR4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR5, "GQR5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR6, "GQR6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750_GQR7, "GQR7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* PowerPC 750cl has 8 DBATs and 8 IBATs */ + gen_high_BATs(env); + init_excp_750cl(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 750 CL"; + pcc->init_proc = init_proc_750cl; + pcc->check_pow = check_pow_hid0; + /* + * XXX: not implemented: + * cache lock instructions: + * dcbz_l + * floating point paired instructions + * psq_lux + * psq_lx + * psq_stux + * psq_stx + * ps_abs + * ps_add + * ps_cmpo0 + * ps_cmpo1 + * ps_cmpu0 + * ps_cmpu1 + * ps_div + * ps_madd + * ps_madds0 + * ps_madds1 + * ps_merge00 + * ps_merge01 + * ps_merge10 + * ps_merge11 + * ps_mr + * ps_msub + * ps_mul + * ps_muls0 + * ps_muls1 + * ps_nabs + * ps_neg + * ps_nmadd + * ps_nmsub + * ps_res + * ps_rsqrte + * ps_sel + * ps_sub + * ps_sum0 + * ps_sum1 + */ + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_750cx(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* This register is not implemented but is present for compatibility */ + spr_register(env, SPR_SDA, "SDA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* PowerPC 750cx has 8 DBATs and 8 IBATs */ + gen_high_BATs(env); + init_excp_750cx(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 750CX"; + pcc->init_proc = init_proc_750cx; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_750fx(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* XXX : not implemented */ + spr_register(env, SPR_750_THRM4, "THRM4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_750FX_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ + gen_high_BATs(env); + init_excp_7x0(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 750FX"; + pcc->init_proc = init_proc_750fx; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_750gx(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* XXX : not implemented (XXX: different from 750fx) */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* XXX : not implemented */ + spr_register(env, SPR_750_THRM4, "THRM4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Hardware implementation registers */ + /* XXX : not implemented (XXX: different from 750fx) */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented (XXX: different from 750fx) */ + spr_register(env, SPR_750FX_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ + gen_high_BATs(env); + init_excp_7x0(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 750GX"; + pcc->init_proc = init_proc_750gx; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_7x0; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_745(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + gen_spr_G2_755(env); + /* Time base */ + gen_tbl(env); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_7x5(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(745)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 745"; + pcc->init_proc = init_proc_745; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_7x5; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_755(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + gen_spr_G2_755(env); + /* Time base */ + gen_tbl(env); + /* L2 cache control */ + /* XXX : not implemented */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_L2PMCR, "L2PMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Thermal management */ + gen_spr_thrm(env); + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_6xx_7xx_soft_tlb(env, 64, 2); + init_excp_7x5(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(755)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 755"; + pcc->init_proc = init_proc_755; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | + PPC_SEGMENT | PPC_EXTERN; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_6xx; + pcc->excp_model = POWERPC_EXCP_7x5; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_750; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7400(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX: this seems not implemented on all revisions. */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSCR1, "MSSCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Thermal management */ + gen_spr_thrm(env); + /* Memory management */ + gen_low_BATs(env); + init_excp_7400(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7400 (aka G4)"; + pcc->init_proc = init_proc_7400; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7410(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Thermal management */ + gen_spr_thrm(env); + /* L2PMCR */ + /* XXX : not implemented */ + spr_register(env, SPR_L2PMCR, "L2PMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* LDSTDB */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTDB, "LDSTDB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + init_excp_7400(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7410 (aka G4)"; + pcc->init_proc = init_proc_7410; + pcc->check_pow = check_pow_hid0; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7440(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7440 (aka G4)"; + pcc->init_proc = init_proc_7440; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7450(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Level 3 cache control */ + gen_l3_ctrl(env); + /* L3ITCR1 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR1, "L3ITCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR2 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR2, "L3ITCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR3 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR3, "L3ITCR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3OHCR */ + /* XXX : not implemented */ + spr_register(env, SPR_L3OHCR, "L3OHCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7450 (aka G4)"; + pcc->init_proc = init_proc_7450; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7445(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7445 (aka G4)"; + pcc->init_proc = init_proc_7445; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7455(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Level 3 cache control */ + gen_l3_ctrl(env); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7455 (aka G4)"; + pcc->init_proc = init_proc_7455; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_7457(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* Level 3 cache control */ + gen_l3_ctrl(env); + /* L3ITCR1 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR1, "L3ITCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR2 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR2, "L3ITCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3ITCR3 */ + /* XXX : not implemented */ + spr_register(env, SPR_L3ITCR3, "L3ITCR3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* L3OHCR */ + /* XXX : not implemented */ + spr_register(env, SPR_L3OHCR, "L3OHCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* LDSTCR */ + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* ICTRL */ + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* MSSSR0 */ + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* PMC */ + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 7457 (aka G4)"; + pcc->init_proc = init_proc_7457; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +static void init_proc_e600(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_sdr1(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + /* 74xx specific SPR */ + gen_spr_74xx(env); + /* XXX : not implemented */ + spr_register(env, SPR_UBAMR, "UBAMR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_LDSTCR, "LDSTCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_ICTRL, "ICTRL", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_MSSSR0, "MSSSR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_7XX_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* SPRGs */ + spr_register(env, SPR_SPRG4, "SPRG4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG4, "USPRG4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG5, "SPRG5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG5, "USPRG5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG6, "SPRG6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG6, "USPRG6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_SPRG7, "SPRG7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_USPRG7, "USPRG7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); + /* Memory management */ + gen_low_BATs(env); + gen_high_BATs(env); + gen_74xx_soft_tlb(env, 128, 2); + init_excp_7450(env); + env->dcache_line_size = 32; + env->icache_line_size = 32; + /* Allocate hardware IRQ controller */ + ppc6xx_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC e600"; + pcc->init_proc = init_proc_e600; + pcc->check_pow = check_pow_hid0_74xx; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBA | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_SEGMENT | PPC_EXTERN | + PPC_ALTIVEC; + pcc->insns_flags2 = PPC_NONE; + pcc->msr_mask = (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_ILE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_EP) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_32B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; +#endif + pcc->excp_model = POWERPC_EXCP_74xx; + pcc->bus_model = PPC_FLAGS_INPUT_6xx; + pcc->bfd_mach = bfd_mach_ppc_7400; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; +} + +#if defined(TARGET_PPC64) +#if defined(CONFIG_USER_ONLY) +#define POWERPC970_HID5_INIT 0x00000080 +#else +#define POWERPC970_HID5_INIT 0x00000000 +#endif + +static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) +{ + TCGv_i32 t1 = tcg_const_i32(bit); + TCGv_i32 t2 = tcg_const_i32(sprn); + TCGv_i32 t3 = tcg_const_i32(cause); + + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); + + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + +static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) +{ + TCGv_i32 t1 = tcg_const_i32(bit); + TCGv_i32 t2 = tcg_const_i32(sprn); + TCGv_i32 t3 = tcg_const_i32(cause); + + gen_helper_msr_facility_check(cpu_env, t1, t2, t3); + + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + +static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) +{ + TCGv spr_up = tcg_temp_new(); + TCGv spr = tcg_temp_new(); + + gen_load_spr(spr, sprn - 1); + tcg_gen_shri_tl(spr_up, spr, 32); + tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); + + tcg_temp_free(spr); + tcg_temp_free(spr_up); +} + +static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) +{ + TCGv spr = tcg_temp_new(); + + gen_load_spr(spr, sprn - 1); + tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); + gen_store_spr(sprn - 1, spr); + + tcg_temp_free(spr); +} + +static int check_pow_970(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { + return 1; + } + + return 0; +} + +static void gen_spr_970_hid(CPUPPCState *env) +{ + /* Hardware implementation registers */ + /* XXX : not implemented */ + spr_register(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + 0x60000000); + spr_register(env, SPR_HID1, "HID1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_970_HID5, "HID5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + POWERPC970_HID5_INIT); +} + +static void gen_spr_970_hior(CPUPPCState *env) +{ + spr_register(env, SPR_HIOR, "SPR_HIOR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_hior, &spr_write_hior, + 0x00000000); +} + +static void gen_spr_book3s_ctrl(CPUPPCState *env) +{ + spr_register(env, SPR_CTRL, "SPR_CTRL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_UCTRL, "SPR_UCTRL", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); +} + +static void gen_spr_book3s_altivec(CPUPPCState *env) +{ + if (!(env->insns_flags & PPC_ALTIVEC)) { + return; + } + + spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_VRSAVE, 0x00000000); + + /* + * Can't find information on what this should be on reset. This + * value is the one used by 74xx processors. + */ + vscr_init(env, 0x00010000); +} + +static void gen_spr_book3s_dbg(CPUPPCState *env) +{ + /* + * TODO: different specs define different scopes for these, + * will have to address this: + * 970: super/write and super/read + * powerisa 2.03..2.04: hypv/write and super/read. + * powerisa 2.05 and newer: hypv/write and hypv/read. + */ + spr_register_kvm(env, SPR_DABR, "DABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DABR, 0x00000000); + spr_register_kvm(env, SPR_DABRX, "DABRX", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DABRX, 0x00000000); +} + +static void gen_spr_book3s_207_dbg(CPUPPCState *env) +{ + spr_register_kvm_hv(env, SPR_DAWR, "DAWR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DAWR, 0x00000000); + spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DAWRX, 0x00000000); + spr_register_kvm_hv(env, SPR_CIABR, "CIABR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_CIABR, 0x00000000); +} + +static void gen_spr_970_dbg(CPUPPCState *env) +{ + /* Breakpoints */ + spr_register(env, SPR_IABR, "IABR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_book3s_pmu_sup(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR0, 0x00000000); + spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR1, 0x00000000); + spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRA, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC1, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC2, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC3, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC4, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC5, 0x00000000); + spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC6, 0x00000000); + spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SIAR, 0x00000000); + spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SDAR, 0x00000000); +} + +static void gen_spr_book3s_pmu_user(CPUPPCState *env) +{ + spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC1, "UPMC1", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC2, "UPMC2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC3, "UPMC3", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC4, "UPMC4", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC5, "UPMC5", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC6, "UPMC6", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_USIAR, "USIAR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_USDAR, "USDAR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); +} + +static void gen_spr_970_pmu_sup(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_970_PMC7, "PMC7", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC7, 0x00000000); + spr_register_kvm(env, SPR_970_PMC8, "PMC8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PMC8, 0x00000000); +} + +static void gen_spr_970_pmu_user(CPUPPCState *env) +{ + spr_register(env, SPR_970_UPMC7, "UPMC7", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_970_UPMC8, "UPMC8", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); +} + +static void gen_spr_power8_pmu_sup(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR2, 0x00000000); + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRS, 0x00000000); + spr_register_kvm(env, SPR_POWER_SIER, "SIER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SIER, 0x00000000); + spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SPMC1, 0x00000000); + spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SPMC2, 0x00000000); + spr_register_kvm(env, SPR_TACR, "TACR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TACR, 0x00000000); + spr_register_kvm(env, SPR_TCSCR, "TCSCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TCSCR, 0x00000000); + spr_register_kvm(env, SPR_CSIGR, "CSIGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_CSIGR, 0x00000000); +} + +static void gen_spr_power8_pmu_user(CPUPPCState *env) +{ + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_USIER, "USIER", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_power5p_ear(CPUPPCState *env) +{ + /* External access control */ + spr_register(env, SPR_EAR, "EAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_power5p_tb(CPUPPCState *env) +{ + /* TBU40 (High 40 bits of the Timebase register */ + spr_register_hv(env, SPR_TBU40, "TBU40", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbu40, + 0x00000000); +} + +#if !defined(CONFIG_USER_ONLY) +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) +{ + TCGv hmer = tcg_temp_new(); + + gen_load_spr(hmer, sprn); + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); + gen_store_spr(sprn, hmer); + spr_store_dump_spr(sprn); + tcg_temp_free(hmer); +} + +static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); +} +#endif /* !defined(CONFIG_USER_ONLY) */ + +static void gen_spr_970_lpar(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* + * PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it + */ + spr_register(env, SPR_970_HID4, "HID4", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#endif +} + +static void gen_spr_power5p_lpar(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* Logical partitionning */ + spr_register_kvm_hv(env, SPR_LPCR, "LPCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_lpcr, + KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); + spr_register_hv(env, SPR_HDEC, "HDEC", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_hdecr, &spr_write_hdecr, 0); +#endif +} + +static void gen_spr_book3s_ids(CPUPPCState *env) +{ + /* FIXME: Will need to deal with thread vs core only SPRs */ + + /* Processor identification */ + spr_register_hv(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, NULL, + 0x00000000); + spr_register_hv(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TSCR, "TSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HMER, "HMER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_hmer, + 0x00000000); + spr_register_hv(env, SPR_HMEER, "HMEER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TFMR, "TFMR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_LPIDR, "LPIDR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_lpidr, + 0x00000000); + spr_register_hv(env, SPR_HFSCR, "HFSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_MMCRC, "MMCRC", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_MMCRH, "MMCRH", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSPRG0, "HSPRG0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSPRG1, "HSPRG1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSRR0, "HSRR0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HSRR1, "HSRR1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HDAR, "HDAR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HDSISR, "HDSISR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_HRMOR, "HRMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_rmor(CPUPPCState *env) +{ + spr_register_hv(env, SPR_RMOR, "RMOR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void gen_spr_power8_ids(CPUPPCState *env) +{ + /* Thread identification */ + spr_register(env, SPR_TIR, "TIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); +} + +static void gen_spr_book3s_purr(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ + spr_register_kvm_hv(env, SPR_PURR, "PURR", + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, &spr_write_purr, + KVM_REG_PPC_PURR, 0x00000000); + spr_register_kvm_hv(env, SPR_SPURR, "SPURR", + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, &spr_write_purr, + KVM_REG_PPC_SPURR, 0x00000000); +#endif +} + +static void gen_spr_power6_dbg(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register(env, SPR_CFAR, "SPR_CFAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_cfar, &spr_write_cfar, + 0x00000000); +#endif +} + +static void gen_spr_power5p_common(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_PPR, "PPR", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PPR, 0x00000000); +} + +static void gen_spr_power6_common(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_DSCR, 0x00000000); +#endif + /* + * Register PCR to report POWERPC_EXCP_PRIV_REG instead of + * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. + */ + spr_register_hv(env, SPR_PCR, "PCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pcr, + 0x00000000); +} + +static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_read_generic(ctx, gprn, sprn); +} + +static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_write_generic(ctx, sprn, gprn); +} + +static void gen_spr_power8_tce_address_control(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_TAR, "TAR", + &spr_read_tar, &spr_write_tar, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TAR, 0x00000000); +} + +static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) +{ + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_generic(ctx, gprn, sprn); +} + +static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) +{ + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_generic(ctx, sprn, gprn); +} + +static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) +{ + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_prev_upper32(ctx, gprn, sprn); +} + +static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) +{ + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_prev_upper32(ctx, sprn, gprn); +} + +static void gen_spr_power8_tm(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_TFHAR, "TFHAR", + &spr_read_tm, &spr_write_tm, + &spr_read_tm, &spr_write_tm, + KVM_REG_PPC_TFHAR, 0x00000000); + spr_register_kvm(env, SPR_TFIAR, "TFIAR", + &spr_read_tm, &spr_write_tm, + &spr_read_tm, &spr_write_tm, + KVM_REG_PPC_TFIAR, 0x00000000); + spr_register_kvm(env, SPR_TEXASR, "TEXASR", + &spr_read_tm, &spr_write_tm, + &spr_read_tm, &spr_write_tm, + KVM_REG_PPC_TEXASR, 0x00000000); + spr_register(env, SPR_TEXASRU, "TEXASRU", + &spr_read_tm_upper32, &spr_write_tm_upper32, + &spr_read_tm_upper32, &spr_write_tm_upper32, + 0x00000000); +} + +static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_generic(ctx, gprn, sprn); +} + +static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_generic(ctx, sprn, gprn); +} + +static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_prev_upper32(ctx, gprn, sprn); +} + +static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) +{ + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_prev_upper32(ctx, sprn, gprn); +} + +static void gen_spr_power8_ebb(CPUPPCState *env) +{ + spr_register(env, SPR_BESCRS, "BESCRS", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRSU, "BESCRSU", + &spr_read_ebb_upper32, &spr_write_ebb_upper32, + &spr_read_prev_upper32, &spr_write_prev_upper32, + 0x00000000); + spr_register(env, SPR_BESCRR, "BESCRR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRRU, "BESCRRU", + &spr_read_ebb_upper32, &spr_write_ebb_upper32, + &spr_read_prev_upper32, &spr_write_prev_upper32, + 0x00000000); + spr_register_kvm(env, SPR_EBBHR, "EBBHR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBHR, 0x00000000); + spr_register_kvm(env, SPR_EBBRR, "EBBRR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBRR, 0x00000000); + spr_register_kvm(env, SPR_BESCR, "BESCR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_BESCR, 0x00000000); +} + +/* Virtual Time Base */ +static void gen_spr_vtb(CPUPPCState *env) +{ + spr_register_kvm_hv(env, SPR_VTB, "VTB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_vtb, SPR_NOACCESS, + &spr_read_vtb, &spr_write_vtb, + KVM_REG_PPC_VTB, 0x00000000); +} + +static void gen_spr_power8_fscr(CPUPPCState *env) +{ +#if defined(CONFIG_USER_ONLY) + target_ulong initval = 1ULL << FSCR_TAR; +#else + target_ulong initval = 0; +#endif + spr_register_kvm(env, SPR_FSCR, "FSCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_FSCR, initval); +} + +static void gen_spr_power8_pspb(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_PSPB, "PSPB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, + KVM_REG_PPC_PSPB, 0); +} + +static void gen_spr_power8_dpdes(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* Directed Privileged Door-bell Exception State, used for IPI */ + spr_register_kvm_hv(env, SPR_DPDES, "DPDES", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_dpdes, SPR_NOACCESS, + &spr_read_dpdes, &spr_write_dpdes, + KVM_REG_PPC_DPDES, 0x00000000); +#endif +} + +static void gen_spr_power8_ic(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_IC, "IC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); +#endif +} + +static void gen_spr_power8_book4(CPUPPCState *env) +{ + /* Add a number of P8 book4 registers */ +#if !defined(CONFIG_USER_ONLY) + spr_register_kvm(env, SPR_ACOP, "ACOP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_ACOP, 0); + spr_register_kvm(env, SPR_BOOKS_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pidr, + KVM_REG_PPC_PID, 0); + spr_register_kvm(env, SPR_WORT, "WORT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_WORT, 0); +#endif +} + +static void gen_spr_power7_book4(CPUPPCState *env) +{ + /* Add a number of P7 book4 registers */ +#if !defined(CONFIG_USER_ONLY) + spr_register_kvm(env, SPR_ACOP, "ACOP", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_ACOP, 0); + spr_register_kvm(env, SPR_BOOKS_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_PID, 0); +#endif +} + +static void gen_spr_power8_rpr(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_RPR, "RPR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000103070F1F3F); +#endif +} + +static void gen_spr_power9_mmu(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + /* Partition Table Control */ + spr_register_kvm_hv(env, SPR_PTCR, "PTCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_ptcr, + KVM_REG_PPC_PTCR, 0x00000000); + /* Address Segment Descriptor Register */ + spr_register_hv(env, SPR_ASDR, "ASDR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x0000000000000000); +#endif +} + +static void init_proc_book3s_common(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_tbl(env); + gen_spr_usprg3(env); + gen_spr_book3s_altivec(env); + gen_spr_book3s_pmu_sup(env); + gen_spr_book3s_pmu_user(env); + gen_spr_book3s_ctrl(env); +} + +static void init_proc_970(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_sdr1(env); + gen_spr_book3s_dbg(env); + + /* 970 Specific Registers */ + gen_spr_970_hid(env); + gen_spr_970_hior(env); + gen_low_BATs(env); + gen_spr_970_pmu_sup(env); + gen_spr_970_pmu_user(env); + gen_spr_970_lpar(env); + gen_spr_970_dbg(env); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_970(env); + ppc970_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(970)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 970"; + pcc->init_proc = init_proc_970; + pcc->check_pow = check_pow_970; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI; + pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI); + pcc->mmu_model = POWERPC_MMU_64B; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->hash64_opts = &ppc_hash64_opts_basic; +#endif + pcc->excp_model = POWERPC_EXCP_970; + pcc->bus_model = PPC_FLAGS_INPUT_970; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x10000; +} + +static void init_proc_power5plus(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_sdr1(env); + gen_spr_book3s_dbg(env); + + /* POWER5+ Specific Registers */ + gen_spr_970_hid(env); + gen_spr_970_hior(env); + gen_low_BATs(env); + gen_spr_970_pmu_sup(env); + gen_spr_970_pmu_user(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_970(env); + ppc970_irq_init(env_archcpu(env)); +} + +POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER5"; + dc->desc = "POWER5+"; + pcc->init_proc = init_proc_power5plus; + pcc->check_pow = check_pow_970; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_STFIWX | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | + PPC_SEGMENT_64B | PPC_SLBI; + pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_VR) | + (1ull << MSR_POW) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI); + pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | + LPCR_RMI | LPCR_HDICE; + pcc->mmu_model = POWERPC_MMU_2_03; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->hash64_opts = &ppc_hash64_opts_basic; + pcc->lrg_decr_bits = 32; +#endif + pcc->excp_model = POWERPC_EXCP_970; + pcc->bus_model = PPC_FLAGS_INPUT_970; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x10000; +} + +static void init_proc_POWER7(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_sdr1(env); + gen_spr_book3s_dbg(env); + + /* POWER7 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_rmor(env); + gen_spr_amr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power7_book4(env); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER7(env); + ppcPOWER7_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { + return true; + } + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER7(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (cs->halted) { + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER7"; + dc->desc = "POWER7"; + pcc->pvr_match = ppc_pvr_match_power7; + pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; + pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER7; + pcc->check_pow = check_pow_nocheck; + cc->has_work = cpu_has_work_POWER7; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | + PPC2_PM_ISA206; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | + LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | + LPCR_MER | LPCR_TC | + LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; + pcc->mmu_model = POWERPC_MMU_2_06; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->lrg_decr_bits = 32; +#endif + pcc->excp_model = POWERPC_EXCP_POWER7; + pcc->bus_model = PPC_FLAGS_INPUT_POWER7; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} + +static void init_proc_POWER8(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_sdr1(env); + gen_spr_book3s_207_dbg(env); + + /* POWER8 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_rmor(env); + gen_spr_amr(env); + gen_spr_iamr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); + gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); + gen_spr_power8_tm(env); + gen_spr_power8_pspb(env); + gen_spr_power8_dpdes(env); + gen_spr_vtb(env); + gen_spr_power8_ic(env); + gen_spr_power8_book4(env); + gen_spr_power8_rpr(env); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER8(env); + ppcPOWER7_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { + return true; + } + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { + return true; + } + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER8(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (cs->halted) { + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { + return true; + } + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER8"; + dc->desc = "POWER8"; + pcc->pvr_match = ppc_pvr_match_power8; + pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER8; + pcc->check_pow = check_pow_nocheck; + cc->has_work = cpu_has_work_POWER8; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_PM_ISA206; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_HV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_TS0) | + (1ull << MSR_TS1) | + (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | + LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | + LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | + LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | + LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; + pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; + pcc->mmu_model = POWERPC_MMU_2_07; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->lrg_decr_bits = 32; + pcc->n_host_threads = 8; +#endif + pcc->excp_model = POWERPC_EXCP_POWER8; + pcc->bus_model = PPC_FLAGS_INPUT_POWER7; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} + +#ifdef CONFIG_SOFTMMU +/* + * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings + * Encoded as array of int_32s in the form: + * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy + * x -> AP encoding + * y -> radix mode supported page size (encoded as a shift) + */ +static struct ppc_radix_page_info POWER9_radix_page_info = { + .count = 4, + .entries = { + 0x0000000c, /* 4K - enc: 0x0 */ + 0xa0000010, /* 64K - enc: 0x5 */ + 0x20000015, /* 2M - enc: 0x1 */ + 0x4000001e /* 1G - enc: 0x2 */ + } +}; +#endif /* CONFIG_SOFTMMU */ + +static void init_proc_POWER9(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_book3s_207_dbg(env); + + /* POWER8 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_amr(env); + gen_spr_iamr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); + gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); + gen_spr_power8_tm(env); + gen_spr_power8_pspb(env); + gen_spr_power8_dpdes(env); + gen_spr_vtb(env); + gen_spr_power8_ic(env); + gen_spr_power8_book4(env); + gen_spr_power8_rpr(env); + gen_spr_power9_mmu(env); + + /* POWER9 Specific registers */ + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_TIDR, 0); + + /* FIXME: Filter fields properly based on privilege level */ + spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_PSSCR, 0); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER9(env); + ppcPOWER9_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER9(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (cs->halted) { + uint64_t psscr = env->spr[SPR_PSSCR]; + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + /* If EC is clear, just return true on any pending interrupt */ + if (!(psscr & PSSCR_EC)) { + return true; + } + /* External Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (heic == 0 || !msr_hv || msr_pr) { + return true; + } + } + /* Decrementer Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return true; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + return true; + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return true; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return true; + } + /* Hypervisor virtualization exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + (env->spr[SPR_LPCR] & LPCR_HVEE)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER9"; + dc->desc = "POWER9"; + pcc->pvr_match = ppc_pvr_match_power9; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; + pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | + PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER9; + pcc->check_pow = check_pow_nocheck; + cc->has_work = cpu_has_work_POWER9; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_HV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; + pcc->mmu_model = POWERPC_MMU_3_00; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER9_radix_page_info; + pcc->lrg_decr_bits = 56; + pcc->n_host_threads = 4; +#endif + pcc->excp_model = POWERPC_EXCP_POWER9; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} + +#ifdef CONFIG_SOFTMMU +/* + * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings + * Encoded as array of int_32s in the form: + * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy + * x -> AP encoding + * y -> radix mode supported page size (encoded as a shift) + */ +static struct ppc_radix_page_info POWER10_radix_page_info = { + .count = 4, + .entries = { + 0x0000000c, /* 4K - enc: 0x0 */ + 0xa0000010, /* 64K - enc: 0x5 */ + 0x20000015, /* 2M - enc: 0x1 */ + 0x4000001e /* 1G - enc: 0x2 */ + } +}; +#endif /* CONFIG_SOFTMMU */ + +static void init_proc_POWER10(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_book3s_207_dbg(env); + + /* POWER8 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_amr(env); + gen_spr_iamr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); + gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); + gen_spr_power8_tm(env); + gen_spr_power8_pspb(env); + gen_spr_vtb(env); + gen_spr_power8_ic(env); + gen_spr_power8_book4(env); + gen_spr_power8_rpr(env); + gen_spr_power9_mmu(env); + + /* FIXME: Filter fields properly based on privilege level */ + spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_PSSCR, 0); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER10(env); + ppcPOWER9_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER10(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (cs->halted) { + uint64_t psscr = env->spr[SPR_PSSCR]; + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + /* If EC is clear, just return true on any pending interrupt */ + if (!(psscr & PSSCR_EC)) { + return true; + } + /* External Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (heic == 0 || !msr_hv || msr_pr) { + return true; + } + } + /* Decrementer Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return true; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + return true; + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return true; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return true; + } + /* Hypervisor virtualization exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + (env->spr[SPR_LPCR] & LPCR_HVEE)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER10"; + dc->desc = "POWER10"; + pcc->pvr_match = ppc_pvr_match_power10; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | + PCR_COMPAT_3_00; + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER10; + pcc->check_pow = check_pow_nocheck; + cc->has_work = cpu_has_work_POWER10; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_HV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; + pcc->mmu_model = POWERPC_MMU_3_00; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER10_radix_page_info; + pcc->lrg_decr_bits = 56; +#endif + pcc->excp_model = POWERPC_EXCP_POWER9; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} + +#if !defined(CONFIG_USER_ONLY) +void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) +{ + CPUPPCState *env = &cpu->env; + + cpu->vhyp = vhyp; + + /* + * With a virtual hypervisor mode we never allow the CPU to go + * hypervisor mode itself + */ + env->msr_mask &= ~MSR_HVB; +} + +#endif /* !defined(CONFIG_USER_ONLY) */ + +#endif /* defined(TARGET_PPC64) */ + +/*****************************************************************************/ +/* Generic CPU instantiation routine */ +static void init_ppc_proc(PowerPCCPU *cpu) +{ + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env = &cpu->env; +#if !defined(CONFIG_USER_ONLY) + int i; + + env->irq_inputs = NULL; + /* Set all exception vectors to an invalid address */ + for (i = 0; i < POWERPC_EXCP_NB; i++) { + env->excp_vectors[i] = (target_ulong)(-1ULL); + } + env->ivor_mask = 0x00000000; + env->ivpr_mask = 0x00000000; + /* Default MMU definitions */ + env->nb_BATs = 0; + env->nb_tlb = 0; + env->nb_ways = 0; + env->tlb_type = TLB_NONE; +#endif + /* Register SPR common to all PowerPC implementations */ + gen_spr_generic(env); + spr_register(env, SPR_PVR, "PVR", + /* Linux permits userspace to read PVR */ +#if defined(CONFIG_LINUX_USER) + &spr_read_generic, +#else + SPR_NOACCESS, +#endif + SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + pcc->pvr); + /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ + if (pcc->svr != POWERPC_SVR_NONE) { + if (pcc->svr & POWERPC_SVR_E500) { + spr_register(env, SPR_E500_SVR, "SVR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + pcc->svr & ~POWERPC_SVR_E500); + } else { + spr_register(env, SPR_SVR, "SVR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + pcc->svr); + } + } + /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ + (*pcc->init_proc)(env); + +#if !defined(CONFIG_USER_ONLY) + ppc_gdb_gen_spr_xml(cpu); +#endif + + /* MSR bits & flags consistency checks */ + if (env->msr_mask & (1 << 25)) { + switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { + case POWERPC_FLAG_SPE: + case POWERPC_FLAG_VRE: + break; + default: + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); + exit(1); + } + } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); + exit(1); + } + if (env->msr_mask & (1 << 17)) { + switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + case POWERPC_FLAG_TGPR: + case POWERPC_FLAG_CE: + break; + default: + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); + exit(1); + } + } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); + exit(1); + } + if (env->msr_mask & (1 << 10)) { + switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | + POWERPC_FLAG_UBLE)) { + case POWERPC_FLAG_SE: + case POWERPC_FLAG_DWE: + case POWERPC_FLAG_UBLE: + break; + default: + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " + "POWERPC_FLAG_UBLE\n"); + exit(1); + } + } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | + POWERPC_FLAG_UBLE)) { + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " + "POWERPC_FLAG_UBLE\n"); + exit(1); + } + if (env->msr_mask & (1 << 9)) { + switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { + case POWERPC_FLAG_BE: + case POWERPC_FLAG_DE: + break; + default: + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); + exit(1); + } + } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); + exit(1); + } + if (env->msr_mask & (1 << 2)) { + switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + case POWERPC_FLAG_PX: + case POWERPC_FLAG_PMM: + break; + default: + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); + exit(1); + } + } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { + fprintf(stderr, "PowerPC MSR definition inconsistency\n" + "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); + exit(1); + } + if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { + fprintf(stderr, "PowerPC flags inconsistency\n" + "Should define the time-base and decrementer clock source\n"); + exit(1); + } + /* Allocate TLBs buffer when needed */ +#if !defined(CONFIG_USER_ONLY) + if (env->nb_tlb != 0) { + int nb_tlb = env->nb_tlb; + if (env->id_tlbs != 0) { + nb_tlb *= 2; + } + switch (env->tlb_type) { + case TLB_6XX: + env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); + break; + case TLB_EMB: + env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); + break; + case TLB_MAS: + env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); + break; + } + /* Pre-compute some useful values */ + env->tlb_per_way = env->nb_tlb / env->nb_ways; + } + if (env->irq_inputs == NULL) { + warn_report("no internal IRQ controller registered." + " Attempt QEMU to crash very soon !"); + } +#endif + if (env->check_pow == NULL) { + warn_report("no power management check handler registered." + " Attempt QEMU to crash very soon !"); + } +} + +#if defined(PPC_DUMP_CPU) +static void dump_ppc_sprs(CPUPPCState *env) +{ + ppc_spr_t *spr; +#if !defined(CONFIG_USER_ONLY) + uint32_t sr, sw; +#endif + uint32_t ur, uw; + int i, j, n; + + printf("Special purpose registers:\n"); + for (i = 0; i < 32; i++) { + for (j = 0; j < 32; j++) { + n = (i << 5) | j; + spr = &env->spr_cb[n]; + uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; + ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; +#if !defined(CONFIG_USER_ONLY) + sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; + sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; + if (sw || sr || uw || ur) { + printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", + (i << 5) | j, (i << 5) | j, spr->name, + sw ? 'w' : '-', sr ? 'r' : '-', + uw ? 'w' : '-', ur ? 'r' : '-'); + } +#else + if (uw || ur) { + printf("SPR: %4d (%03x) %-8s u%c%c\n", + (i << 5) | j, (i << 5) | j, spr->name, + uw ? 'w' : '-', ur ? 'r' : '-'); + } +#endif + } + } + fflush(stdout); + fflush(stderr); +} +#endif + +/*****************************************************************************/ + +/* Opcode types */ +enum { + PPC_DIRECT = 0, /* Opcode routine */ + PPC_INDIRECT = 1, /* Indirect opcode table */ +}; + +#define PPC_OPCODE_MASK 0x3 + +static inline int is_indirect_opcode(void *handler) +{ + return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; +} + +static inline opc_handler_t **ind_table(void *handler) +{ + return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); +} + +/* Instruction table creation */ +/* Opcodes tables creation */ +static void fill_new_table(opc_handler_t **table, int len) +{ + int i; + + for (i = 0; i < len; i++) { + table[i] = &invalid_handler; + } +} + +static int create_new_table(opc_handler_t **table, unsigned char idx) +{ + opc_handler_t **tmp; + + tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); + fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); + table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); + + return 0; +} + +static int insert_in_table(opc_handler_t **table, unsigned char idx, + opc_handler_t *handler) +{ + if (table[idx] != &invalid_handler) { + return -1; + } + table[idx] = handler; + + return 0; +} + +static int register_direct_insn(opc_handler_t **ppc_opcodes, + unsigned char idx, opc_handler_t *handler) +{ + if (insert_in_table(ppc_opcodes, idx, handler) < 0) { + printf("*** ERROR: opcode %02x already assigned in main " + "opcode table\n", idx); +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) + printf(" Registered handler '%s' - new handler '%s'\n", + ppc_opcodes[idx]->oname, handler->oname); +#endif + return -1; + } + + return 0; +} + +static int register_ind_in_table(opc_handler_t **table, + unsigned char idx1, unsigned char idx2, + opc_handler_t *handler) +{ + if (table[idx1] == &invalid_handler) { + if (create_new_table(table, idx1) < 0) { + printf("*** ERROR: unable to create indirect table " + "idx=%02x\n", idx1); + return -1; + } + } else { + if (!is_indirect_opcode(table[idx1])) { + printf("*** ERROR: idx %02x already assigned to a direct " + "opcode\n", idx1); +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) + printf(" Registered handler '%s' - new handler '%s'\n", + ind_table(table[idx1])[idx2]->oname, handler->oname); +#endif + return -1; + } + } + if (handler != NULL && + insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { + printf("*** ERROR: opcode %02x already assigned in " + "opcode table %02x\n", idx2, idx1); +#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) + printf(" Registered handler '%s' - new handler '%s'\n", + ind_table(table[idx1])[idx2]->oname, handler->oname); +#endif + return -1; + } + + return 0; +} + +static int register_ind_insn(opc_handler_t **ppc_opcodes, + unsigned char idx1, unsigned char idx2, + opc_handler_t *handler) +{ + return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); +} + +static int register_dblind_insn(opc_handler_t **ppc_opcodes, + unsigned char idx1, unsigned char idx2, + unsigned char idx3, opc_handler_t *handler) +{ + if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { + printf("*** ERROR: unable to join indirect table idx " + "[%02x-%02x]\n", idx1, idx2); + return -1; + } + if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, + handler) < 0) { + printf("*** ERROR: unable to insert opcode " + "[%02x-%02x-%02x]\n", idx1, idx2, idx3); + return -1; + } + + return 0; +} + +static int register_trplind_insn(opc_handler_t **ppc_opcodes, + unsigned char idx1, unsigned char idx2, + unsigned char idx3, unsigned char idx4, + opc_handler_t *handler) +{ + opc_handler_t **table; + + if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { + printf("*** ERROR: unable to join indirect table idx " + "[%02x-%02x]\n", idx1, idx2); + return -1; + } + table = ind_table(ppc_opcodes[idx1]); + if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { + printf("*** ERROR: unable to join 2nd-level indirect table idx " + "[%02x-%02x-%02x]\n", idx1, idx2, idx3); + return -1; + } + table = ind_table(table[idx2]); + if (register_ind_in_table(table, idx3, idx4, handler) < 0) { + printf("*** ERROR: unable to insert opcode " + "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); + return -1; + } + return 0; +} +static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) +{ + if (insn->opc2 != 0xFF) { + if (insn->opc3 != 0xFF) { + if (insn->opc4 != 0xFF) { + if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, + insn->opc3, insn->opc4, + &insn->handler) < 0) { + return -1; + } + } else { + if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, + insn->opc3, &insn->handler) < 0) { + return -1; + } + } + } else { + if (register_ind_insn(ppc_opcodes, insn->opc1, + insn->opc2, &insn->handler) < 0) { + return -1; + } + } + } else { + if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { + return -1; + } + } + + return 0; +} + +static int test_opcode_table(opc_handler_t **table, int len) +{ + int i, count, tmp; + + for (i = 0, count = 0; i < len; i++) { + /* Consistency fixup */ + if (table[i] == NULL) { + table[i] = &invalid_handler; + } + if (table[i] != &invalid_handler) { + if (is_indirect_opcode(table[i])) { + tmp = test_opcode_table(ind_table(table[i]), + PPC_CPU_INDIRECT_OPCODES_LEN); + if (tmp == 0) { + free(table[i]); + table[i] = &invalid_handler; + } else { + count++; + } + } else { + count++; + } + } + } + + return count; +} + +static void fix_opcode_tables(opc_handler_t **ppc_opcodes) +{ + if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { + printf("*** WARNING: no opcode defined !\n"); + } +} + +/*****************************************************************************/ +static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) +{ + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + opcode_t *opc; + + fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); + for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { + if (((opc->handler.type & pcc->insns_flags) != 0) || + ((opc->handler.type2 & pcc->insns_flags2) != 0)) { + if (register_insn(cpu->opcodes, opc) < 0) { + error_setg(errp, "ERROR initializing PowerPC instruction " + "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, + opc->opc3); + return; + } + } + } + fix_opcode_tables(cpu->opcodes); + fflush(stdout); + fflush(stderr); +} + +#if defined(PPC_DUMP_CPU) +static void dump_ppc_insns(CPUPPCState *env) +{ + opc_handler_t **table, *handler; + const char *p, *q; + uint8_t opc1, opc2, opc3, opc4; + + printf("Instructions set:\n"); + /* opc1 is 6 bits long */ + for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { + table = env->opcodes; + handler = table[opc1]; + if (is_indirect_opcode(handler)) { + /* opc2 is 5 bits long */ + for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { + table = env->opcodes; + handler = env->opcodes[opc1]; + table = ind_table(handler); + handler = table[opc2]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + /* opc3 is 5 bits long */ + for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; + opc3++) { + handler = table[opc3]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + /* opc4 is 5 bits long */ + for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; + opc4++) { + handler = table[opc4]; + if (handler->handler != &gen_invalid) { + printf("INSN: %02x %02x %02x %02x -- " + "(%02d %04d %02d) : %s\n", + opc1, opc2, opc3, opc4, + opc1, (opc3 << 5) | opc2, opc4, + handler->oname); + } + } + } else { + if (handler->handler != &gen_invalid) { + /* Special hack to properly dump SPE insns */ + p = strchr(handler->oname, '_'); + if (p == NULL) { + printf("INSN: %02x %02x %02x (%02d %04d) : " + "%s\n", + opc1, opc2, opc3, opc1, + (opc3 << 5) | opc2, + handler->oname); + } else { + q = "speundef"; + if ((p - handler->oname) != strlen(q) + || (memcmp(handler->oname, q, strlen(q)) + != 0)) { + /* First instruction */ + printf("INSN: %02x %02x %02x" + "(%02d %04d) : %.*s\n", + opc1, opc2 << 1, opc3, opc1, + (opc3 << 6) | (opc2 << 1), + (int)(p - handler->oname), + handler->oname); + } + if (strcmp(p + 1, q) != 0) { + /* Second instruction */ + printf("INSN: %02x %02x %02x " + "(%02d %04d) : %s\n", opc1, + (opc2 << 1) | 1, opc3, opc1, + (opc3 << 6) | (opc2 << 1) | 1, + p + 1); + } + } + } + } + } + } else { + if (handler->handler != &gen_invalid) { + printf("INSN: %02x %02x -- (%02d %04d) : %s\n", + opc1, opc2, opc1, opc2, handler->oname); + } + } + } + } else { + if (handler->handler != &gen_invalid) { + printf("INSN: %02x -- -- (%02d ----) : %s\n", + opc1, opc1, handler->oname); + } + } + } +} +#endif + +static bool avr_need_swap(CPUPPCState *env) +{ +#ifdef HOST_WORDS_BIGENDIAN + return msr_le; +#else + return !msr_le; +#endif +} + +#if !defined(CONFIG_USER_ONLY) +static int gdb_find_spr_idx(CPUPPCState *env, int n) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { + ppc_spr_t *spr = &env->spr_cb[i]; + + if (spr->name && spr->gdb_id == n) { + return i; + } + } + return -1; +} + +static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) +{ + int reg; + int len; + + reg = gdb_find_spr_idx(env, n); + if (reg < 0) { + return 0; + } + + len = TARGET_LONG_SIZE; + gdb_get_regl(buf, env->spr[reg]); + ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); + return len; +} + +static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +{ + int reg; + int len; + + reg = gdb_find_spr_idx(env, n); + if (reg < 0) { + return 0; + } + + len = TARGET_LONG_SIZE; + ppc_maybe_bswap_register(env, mem_buf, len); + env->spr[reg] = ldn_p(mem_buf, len); + + return len; +} +#endif + +static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) +{ + uint8_t *mem_buf; + if (n < 32) { + gdb_get_float64(buf, *cpu_fpr_ptr(env, n)); + mem_buf = gdb_get_reg_ptr(buf, 8); + ppc_maybe_bswap_register(env, mem_buf, 8); + return 8; + } + if (n == 32) { + gdb_get_reg32(buf, env->fpscr); + mem_buf = gdb_get_reg_ptr(buf, 4); + ppc_maybe_bswap_register(env, mem_buf, 4); + return 4; + } + return 0; +} + +static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + ppc_maybe_bswap_register(env, mem_buf, 8); + *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf); + return 8; + } + if (n == 32) { + ppc_maybe_bswap_register(env, mem_buf, 4); + helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff); + return 4; + } + return 0; +} + +static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) +{ + uint8_t *mem_buf; + + if (n < 32) { + ppc_avr_t *avr = cpu_avr_ptr(env, n); + if (!avr_need_swap(env)) { + gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); + } else { + gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); + } + mem_buf = gdb_get_reg_ptr(buf, 16); + ppc_maybe_bswap_register(env, mem_buf, 8); + ppc_maybe_bswap_register(env, mem_buf + 8, 8); + return 16; + } + if (n == 32) { + gdb_get_reg32(buf, helper_mfvscr(env)); + mem_buf = gdb_get_reg_ptr(buf, 4); + ppc_maybe_bswap_register(env, mem_buf, 4); + return 4; + } + if (n == 33) { + gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); + mem_buf = gdb_get_reg_ptr(buf, 4); + ppc_maybe_bswap_register(env, mem_buf, 4); + return 4; + } + return 0; +} + +static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + ppc_avr_t *avr = cpu_avr_ptr(env, n); + ppc_maybe_bswap_register(env, mem_buf, 8); + ppc_maybe_bswap_register(env, mem_buf + 8, 8); + if (!avr_need_swap(env)) { + avr->u64[0] = ldq_p(mem_buf); + avr->u64[1] = ldq_p(mem_buf + 8); + } else { + avr->u64[1] = ldq_p(mem_buf); + avr->u64[0] = ldq_p(mem_buf + 8); + } + return 16; + } + if (n == 32) { + ppc_maybe_bswap_register(env, mem_buf, 4); + helper_mtvscr(env, ldl_p(mem_buf)); + return 4; + } + if (n == 33) { + ppc_maybe_bswap_register(env, mem_buf, 4); + env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); + return 4; + } + return 0; +} + +static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) +{ + if (n < 32) { +#if defined(TARGET_PPC64) + gdb_get_reg32(buf, env->gpr[n] >> 32); + ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); +#else + gdb_get_reg32(buf, env->gprh[n]); +#endif + return 4; + } + if (n == 32) { + gdb_get_reg64(buf, env->spe_acc); + ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); + return 8; + } + if (n == 33) { + gdb_get_reg32(buf, env->spe_fscr); + ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); + return 4; + } + return 0; +} + +static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { +#if defined(TARGET_PPC64) + target_ulong lo = (uint32_t)env->gpr[n]; + target_ulong hi; + + ppc_maybe_bswap_register(env, mem_buf, 4); + + hi = (target_ulong)ldl_p(mem_buf) << 32; + env->gpr[n] = lo | hi; +#else + env->gprh[n] = ldl_p(mem_buf); +#endif + return 4; + } + if (n == 32) { + ppc_maybe_bswap_register(env, mem_buf, 8); + env->spe_acc = ldq_p(mem_buf); + return 8; + } + if (n == 33) { + ppc_maybe_bswap_register(env, mem_buf, 4); + env->spe_fscr = ldl_p(mem_buf); + return 4; + } + return 0; +} + +static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) +{ + if (n < 32) { + gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); + ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); + return 8; + } + return 0; +} + +static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + ppc_maybe_bswap_register(env, mem_buf, 8); + *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); + return 8; + } + return 0; +} + +static int ppc_fixup_cpu(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + /* + * TCG doesn't (yet) emulate some groups of instructions that are + * implemented on some otherwise supported CPUs (e.g. VSX and + * decimal floating point instructions on POWER7). We remove + * unsupported instruction groups from the cpu state's instruction + * masks and hope the guest can cope. For at least the pseries + * machine, the unavailability of these instructions can be + * advertised to the guest via the device tree. + */ + if ((env->insns_flags & ~PPC_TCG_INSNS) + || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { + warn_report("Disabling some instructions which are not " + "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", + env->insns_flags & ~PPC_TCG_INSNS, + env->insns_flags2 & ~PPC_TCG_INSNS2); + } + env->insns_flags &= PPC_TCG_INSNS; + env->insns_flags2 &= PPC_TCG_INSNS2; + return 0; +} + +static void ppc_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + PowerPCCPU *cpu = POWERPC_CPU(dev); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + Error *local_err = NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { + cpu->vcpu_id = cs->cpu_index; + } + + if (tcg_enabled()) { + if (ppc_fixup_cpu(cpu) != 0) { + error_setg(errp, "Unable to emulate selected CPU with TCG"); + goto unrealize; + } + } + + create_ppc_opcodes(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + goto unrealize; + } + init_ppc_proc(cpu); + + if (pcc->insns_flags & PPC_FLOAT) { + gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, + 33, "power-fpu.xml", 0); + } + if (pcc->insns_flags & PPC_ALTIVEC) { + gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, + 34, "power-altivec.xml", 0); + } + if (pcc->insns_flags & PPC_SPE) { + gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, + 34, "power-spe.xml", 0); + } + if (pcc->insns_flags2 & PPC2_VSX) { + gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, + 32, "power-vsx.xml", 0); + } +#ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, + pcc->gdb_num_sprs, "power-spr.xml", 0); +#endif + qemu_init_vcpu(cs); + + pcc->parent_realize(dev, errp); + +#if defined(PPC_DUMP_CPU) + { + CPUPPCState *env = &cpu->env; + const char *mmu_model, *excp_model, *bus_model; + switch (env->mmu_model) { + case POWERPC_MMU_32B: + mmu_model = "PowerPC 32"; + break; + case POWERPC_MMU_SOFT_6xx: + mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_74xx: + mmu_model = "PowerPC 74xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_4xx: + mmu_model = "PowerPC 4xx with software driven TLBs"; + break; + case POWERPC_MMU_SOFT_4xx_Z: + mmu_model = "PowerPC 4xx with software driven TLBs " + "and zones protections"; + break; + case POWERPC_MMU_REAL: + mmu_model = "PowerPC real mode only"; + break; + case POWERPC_MMU_MPC8xx: + mmu_model = "PowerPC MPC8xx"; + break; + case POWERPC_MMU_BOOKE: + mmu_model = "PowerPC BookE"; + break; + case POWERPC_MMU_BOOKE206: + mmu_model = "PowerPC BookE 2.06"; + break; + case POWERPC_MMU_601: + mmu_model = "PowerPC 601"; + break; +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + mmu_model = "PowerPC 64"; + break; +#endif + default: + mmu_model = "Unknown or invalid"; + break; + } + switch (env->excp_model) { + case POWERPC_EXCP_STD: + excp_model = "PowerPC"; + break; + case POWERPC_EXCP_40x: + excp_model = "PowerPC 40x"; + break; + case POWERPC_EXCP_601: + excp_model = "PowerPC 601"; + break; + case POWERPC_EXCP_602: + excp_model = "PowerPC 602"; + break; + case POWERPC_EXCP_603: + excp_model = "PowerPC 603"; + break; + case POWERPC_EXCP_603E: + excp_model = "PowerPC 603e"; + break; + case POWERPC_EXCP_604: + excp_model = "PowerPC 604"; + break; + case POWERPC_EXCP_7x0: + excp_model = "PowerPC 740/750"; + break; + case POWERPC_EXCP_7x5: + excp_model = "PowerPC 745/755"; + break; + case POWERPC_EXCP_74xx: + excp_model = "PowerPC 74xx"; + break; + case POWERPC_EXCP_BOOKE: + excp_model = "PowerPC BookE"; + break; +#if defined(TARGET_PPC64) + case POWERPC_EXCP_970: + excp_model = "PowerPC 970"; + break; +#endif + default: + excp_model = "Unknown or invalid"; + break; + } + switch (env->bus_model) { + case PPC_FLAGS_INPUT_6xx: + bus_model = "PowerPC 6xx"; + break; + case PPC_FLAGS_INPUT_BookE: + bus_model = "PowerPC BookE"; + break; + case PPC_FLAGS_INPUT_405: + bus_model = "PowerPC 405"; + break; + case PPC_FLAGS_INPUT_401: + bus_model = "PowerPC 401/403"; + break; + case PPC_FLAGS_INPUT_RCPU: + bus_model = "RCPU / MPC8xx"; + break; +#if defined(TARGET_PPC64) + case PPC_FLAGS_INPUT_970: + bus_model = "PowerPC 970"; + break; +#endif + default: + bus_model = "Unknown or invalid"; + break; + } + printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" + " MMU model : %s\n", + object_class_get_name(OBJECT_CLASS(pcc)), + pcc->pvr, pcc->msr_mask, mmu_model); +#if !defined(CONFIG_USER_ONLY) + if (env->tlb.tlb6) { + printf(" %d %s TLB in %d ways\n", + env->nb_tlb, env->id_tlbs ? "splitted" : "merged", + env->nb_ways); + } +#endif + printf(" Exceptions model : %s\n" + " Bus model : %s\n", + excp_model, bus_model); + printf(" MSR features :\n"); + if (env->flags & POWERPC_FLAG_SPE) { + printf(" signal processing engine enable" + "\n"); + } else if (env->flags & POWERPC_FLAG_VRE) { + printf(" vector processor enable\n"); + } + if (env->flags & POWERPC_FLAG_TGPR) { + printf(" temporary GPRs\n"); + } else if (env->flags & POWERPC_FLAG_CE) { + printf(" critical input enable\n"); + } + if (env->flags & POWERPC_FLAG_SE) { + printf(" single-step trace mode\n"); + } else if (env->flags & POWERPC_FLAG_DWE) { + printf(" debug wait enable\n"); + } else if (env->flags & POWERPC_FLAG_UBLE) { + printf(" user BTB lock enable\n"); + } + if (env->flags & POWERPC_FLAG_BE) { + printf(" branch-step trace mode\n"); + } else if (env->flags & POWERPC_FLAG_DE) { + printf(" debug interrupt enable\n"); + } + if (env->flags & POWERPC_FLAG_PX) { + printf(" inclusive protection\n"); + } else if (env->flags & POWERPC_FLAG_PMM) { + printf(" performance monitor mark\n"); + } + if (env->flags == POWERPC_FLAG_NONE) { + printf(" none\n"); + } + printf(" Time-base/decrementer clock source: %s\n", + env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); + dump_ppc_insns(env); + dump_ppc_sprs(env); + fflush(stdout); + } +#endif + return; + +unrealize: + cpu_exec_unrealizefn(cs); +} + +static void ppc_cpu_unrealize(DeviceState *dev) +{ + PowerPCCPU *cpu = POWERPC_CPU(dev); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + opc_handler_t **table, **table_2; + int i, j, k; + + pcc->parent_unrealize(dev); + + for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { + if (cpu->opcodes[i] == &invalid_handler) { + continue; + } + if (is_indirect_opcode(cpu->opcodes[i])) { + table = ind_table(cpu->opcodes[i]); + for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { + if (table[j] == &invalid_handler) { + continue; + } + if (is_indirect_opcode(table[j])) { + table_2 = ind_table(table[j]); + for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { + if (table_2[k] != &invalid_handler && + is_indirect_opcode(table_2[k])) { + g_free((opc_handler_t *)((uintptr_t)table_2[k] & + ~PPC_INDIRECT)); + } + } + g_free((opc_handler_t *)((uintptr_t)table[j] & + ~PPC_INDIRECT)); + } + } + g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & + ~PPC_INDIRECT)); + } + } +} + +static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) +{ + ObjectClass *oc = (ObjectClass *)a; + uint32_t pvr = *(uint32_t *)b; + PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; + + /* -cpu host does a PVR lookup during construction */ + if (unlikely(strcmp(object_class_get_name(oc), + TYPE_HOST_POWERPC_CPU) == 0)) { + return -1; + } + + return pcc->pvr == pvr ? 0 : -1; +} + +PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) +{ + GSList *list, *item; + PowerPCCPUClass *pcc = NULL; + + list = object_class_get_list(TYPE_POWERPC_CPU, false); + item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); + if (item != NULL) { + pcc = POWERPC_CPU_CLASS(item->data); + } + g_slist_free(list); + + return pcc; +} + +static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) +{ + ObjectClass *oc = (ObjectClass *)a; + uint32_t pvr = *(uint32_t *)b; + PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; + + /* -cpu host does a PVR lookup during construction */ + if (unlikely(strcmp(object_class_get_name(oc), + TYPE_HOST_POWERPC_CPU) == 0)) { + return -1; + } + + if (pcc->pvr_match(pcc, pvr)) { + return 0; + } + + return -1; +} + +PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) +{ + GSList *list, *item; + PowerPCCPUClass *pcc = NULL; + + list = object_class_get_list(TYPE_POWERPC_CPU, true); + item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); + if (item != NULL) { + pcc = POWERPC_CPU_CLASS(item->data); + } + g_slist_free(list); + + return pcc; +} + +static const char *ppc_cpu_lookup_alias(const char *alias) +{ + int ai; + + for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { + if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { + return ppc_cpu_aliases[ai].model; + } + } + + return NULL; +} + +static ObjectClass *ppc_cpu_class_by_name(const char *name) +{ + char *cpu_model, *typename; + ObjectClass *oc; + const char *p; + unsigned long pvr; + + /* + * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: + * 0x prefix if present) + */ + if (!qemu_strtoul(name, &p, 16, &pvr)) { + int len = p - name; + len = (len == 10) && (name[1] == 'x') ? len - 2 : len; + if ((len == 8) && (*p == '\0')) { + return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); + } + } + + cpu_model = g_ascii_strdown(name, -1); + p = ppc_cpu_lookup_alias(cpu_model); + if (p) { + g_free(cpu_model); + cpu_model = g_strdup(p); + } + + typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); + oc = object_class_by_name(typename); + g_free(typename); + g_free(cpu_model); + + return oc; +} + +static void ppc_cpu_parse_featurestr(const char *type, char *features, + Error **errp) +{ + Object *machine = qdev_get_machine(); + const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type)); + + if (!features) { + return; + } + + if (object_property_find(machine, "max-cpu-compat", NULL)) { + int i; + char **inpieces; + char *s = features; + Error *local_err = NULL; + char *compat_str = NULL; + + /* + * Backwards compatibility hack: + * + * CPUs had a "compat=" property which didn't make sense for + * anything except pseries. It was replaced by "max-cpu-compat" + * machine option. This supports old command lines like + * -cpu POWER8,compat=power7 + * By stripping the compat option and applying it to the machine + * before passing it on to the cpu level parser. + */ + inpieces = g_strsplit(features, ",", 0); + *s = '\0'; + for (i = 0; inpieces[i]; i++) { + if (g_str_has_prefix(inpieces[i], "compat=")) { + warn_report_once("CPU 'compat' property is deprecated; " + "use max-cpu-compat machine property instead"); + compat_str = inpieces[i]; + continue; + } + if ((i != 0) && (s != features)) { + s = g_stpcpy(s, ","); + } + s = g_stpcpy(s, inpieces[i]); + } + + if (compat_str) { + char *v = compat_str + strlen("compat="); + object_property_set_str(machine, "max-cpu-compat", v, &local_err); + } + g_strfreev(inpieces); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } + + /* do property processing with generic handler */ + pcc->parent_parse_features(type, features, errp); +} + +PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) +{ + ObjectClass *oc = OBJECT_CLASS(pcc); + + while (oc && !object_class_is_abstract(oc)) { + oc = object_class_get_parent(oc); + } + assert(oc); + + return POWERPC_CPU_CLASS(oc); +} + +/* Sort by PVR, ordering special case "host" last. */ +static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *oc_a = (ObjectClass *)a; + ObjectClass *oc_b = (ObjectClass *)b; + PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); + PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); + const char *name_a = object_class_get_name(oc_a); + const char *name_b = object_class_get_name(oc_b); + + if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { + return 1; + } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { + return -1; + } else { + /* Avoid an integer overflow during subtraction */ + if (pcc_a->pvr < pcc_b->pvr) { + return -1; + } else if (pcc_a->pvr > pcc_b->pvr) { + return 1; + } else { + return 0; + } + } +} + +static void ppc_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); + const char *typename = object_class_get_name(oc); + char *name; + int i; + + if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { + return; + } + + name = g_strndup(typename, + strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); + qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); + for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { + PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; + ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); + + if (alias_oc != oc) { + continue; + } + /* + * If running with KVM, we might update the family alias later, so + * avoid printing the wrong alias here and use "preferred" instead + */ + if (strcmp(alias->alias, family->desc) == 0) { + qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", + alias->alias, family->desc); + } else { + qemu_printf("PowerPC %-16s (alias for %s)\n", + alias->alias, name); + } + } + g_free(name); +} + +void ppc_cpu_list(void) +{ + GSList *list; + + list = object_class_get_list(TYPE_POWERPC_CPU, false); + list = g_slist_sort(list, ppc_cpu_list_compare); + g_slist_foreach(list, ppc_cpu_list_entry, NULL); + g_slist_free(list); + +#ifdef CONFIG_KVM + qemu_printf("\n"); + qemu_printf("PowerPC %-16s\n", "host"); +#endif +} + +static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + CpuDefinitionInfoList **first = user_data; + const char *typename; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + + typename = object_class_get_name(oc); + info = g_malloc0(sizeof(*info)); + info->name = g_strndup(typename, + strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); + + entry = g_malloc0(sizeof(*entry)); + entry->value = info; + entry->next = *first; + *first = entry; +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list = NULL; + GSList *list; + int i; + + list = object_class_get_list(TYPE_POWERPC_CPU, false); + g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); + g_slist_free(list); + + for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { + PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; + ObjectClass *oc; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + + oc = ppc_cpu_class_by_name(alias->model); + if (oc == NULL) { + continue; + } + + info = g_malloc0(sizeof(*info)); + info->name = g_strdup(alias->alias); + info->q_typename = g_strdup(object_class_get_name(oc)); + + entry = g_malloc0(sizeof(*entry)); + entry->value = info; + entry->next = cpu_list; + cpu_list = entry; + } + + return cpu_list; +} + +static void ppc_cpu_set_pc(CPUState *cs, vaddr value) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + + cpu->env.nip = value; +} + +static bool ppc_cpu_has_work(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); +} + +static void ppc_cpu_reset(DeviceState *dev) +{ + CPUState *s = CPU(dev); + PowerPCCPU *cpu = POWERPC_CPU(s); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env = &cpu->env; + target_ulong msr; + int i; + + pcc->parent_reset(dev); + + msr = (target_ulong)0; + msr |= (target_ulong)MSR_HVB; + msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ + msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ + msr |= (target_ulong)1 << MSR_EP; +#if defined(DO_SINGLE_STEP) && 0 + /* Single step trace mode */ + msr |= (target_ulong)1 << MSR_SE; + msr |= (target_ulong)1 << MSR_BE; +#endif +#if defined(CONFIG_USER_ONLY) + msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ + msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ + msr |= (target_ulong)1 << MSR_FE1; + msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ + msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ + msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ + msr |= (target_ulong)1 << MSR_PR; +#if defined(TARGET_PPC64) + msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ +#endif +#if !defined(TARGET_WORDS_BIGENDIAN) + msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ + if (!((env->msr_mask >> MSR_LE) & 1)) { + fprintf(stderr, "Selected CPU does not support little-endian.\n"); + exit(1); + } +#endif +#endif + +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) { + msr |= (1ULL << MSR_SF); + } +#endif + + hreg_store_msr(env, msr, 1); + +#if !defined(CONFIG_USER_ONLY) + env->nip = env->hreset_vector | env->excp_prefix; + if (env->mmu_model != POWERPC_MMU_REAL) { + ppc_tlb_invalidate_all(env); + } +#endif + + hreg_compute_hflags(env); + env->reserve_addr = (target_ulong)-1ULL; + /* Be sure no exception or interrupt is pending */ + env->pending_interrupts = 0; + s->exception_index = POWERPC_EXCP_NONE; + env->error_code = 0; + ppc_irq_reset(cpu); + + /* tininess for underflow is detected before rounding */ + set_float_detect_tininess(float_tininess_before_rounding, + &env->fp_status); + + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { + ppc_spr_t *spr = &env->spr_cb[i]; + + if (!spr->name) { + continue; + } + env->spr[i] = spr->default_value; + } +} + +#ifndef CONFIG_USER_ONLY +static bool ppc_cpu_is_big_endian(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + cpu_synchronize_state(cs); + + return !msr_le; +} + +static void ppc_cpu_exec_enter(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + + if (cpu->vhyp) { + PPCVirtualHypervisorClass *vhc = + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->cpu_exec_enter(cpu->vhyp, cpu); + } +} + +static void ppc_cpu_exec_exit(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + + if (cpu->vhyp) { + PPCVirtualHypervisorClass *vhc = + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->cpu_exec_exit(cpu->vhyp, cpu); + } +} +#endif + +static void ppc_cpu_instance_init(Object *obj) +{ + PowerPCCPU *cpu = POWERPC_CPU(obj); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *env = &cpu->env; + + cpu_set_cpustate_pointers(cpu); + cpu->vcpu_id = UNASSIGNED_CPU_INDEX; + + env->msr_mask = pcc->msr_mask; + env->mmu_model = pcc->mmu_model; + env->excp_model = pcc->excp_model; + env->bus_model = pcc->bus_model; + env->insns_flags = pcc->insns_flags; + env->insns_flags2 = pcc->insns_flags2; + env->flags = pcc->flags; + env->bfd_mach = pcc->bfd_mach; + env->check_pow = pcc->check_pow; + + /* + * Mark HV mode as supported if the CPU has an MSR_HV bit in the + * msr_mask. The mask can later be cleared by PAPR mode but the hv + * mode support will remain, thus enforcing that we cannot use + * priv. instructions in guest in PAPR mode. For 970 we currently + * simply don't set HV in msr_mask thus simulating an "Apple mode" + * 970. If we ever want to support 970 HV mode, we'll have to add + * a processor attribute of some sort. + */ +#if !defined(CONFIG_USER_ONLY) + env->has_hv_mode = !!(env->msr_mask & MSR_HVB); +#endif + + ppc_hash64_init(cpu); +} + +static void ppc_cpu_instance_finalize(Object *obj) +{ + PowerPCCPU *cpu = POWERPC_CPU(obj); + + ppc_hash64_finalize(cpu); +} + +static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) +{ + return pcc->pvr == pvr; +} + +static gchar *ppc_gdb_arch_name(CPUState *cs) +{ +#if defined(TARGET_PPC64) + return g_strdup("powerpc:common64"); +#else + return g_strdup("powerpc:common"); +#endif +} + +static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if ((env->hflags >> MSR_LE) & 1) { + info->endian = BFD_ENDIAN_LITTLE; + } + info->mach = env->bfd_mach; + if (!env->bfd_mach) { +#ifdef TARGET_PPC64 + info->mach = bfd_mach_ppc64; +#else + info->mach = bfd_mach_ppc; +#endif + } + info->disassembler_options = (char *)"any"; + info->print_insn = print_insn_ppc; + + info->cap_arch = CS_ARCH_PPC; +#ifdef TARGET_PPC64 + info->cap_mode = CS_MODE_64; +#endif +} + +static Property ppc_cpu_properties[] = { + DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), + DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, + false), + DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, + false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc_cpu_class_init(ObjectClass *oc, void *data) +{ + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + device_class_set_parent_realize(dc, ppc_cpu_realize, + &pcc->parent_realize); + device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, + &pcc->parent_unrealize); + pcc->pvr_match = ppc_pvr_match_default; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; + device_class_set_props(dc, ppc_cpu_properties); + + device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); + + cc->class_by_name = ppc_cpu_class_by_name; + pcc->parent_parse_features = cc->parse_features; + cc->parse_features = ppc_cpu_parse_featurestr; + cc->has_work = ppc_cpu_has_work; + cc->do_interrupt = ppc_cpu_do_interrupt; + cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; + cc->dump_state = ppc_cpu_dump_state; + cc->dump_statistics = ppc_cpu_dump_statistics; + cc->set_pc = ppc_cpu_set_pc; + cc->gdb_read_register = ppc_cpu_gdb_read_register; + cc->gdb_write_register = ppc_cpu_gdb_write_register; + cc->do_unaligned_access = ppc_cpu_do_unaligned_access; +#ifndef CONFIG_USER_ONLY + cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; + cc->vmsd = &vmstate_ppc_cpu; +#endif +#if defined(CONFIG_SOFTMMU) + cc->write_elf64_note = ppc64_cpu_write_elf64_note; + cc->write_elf32_note = ppc32_cpu_write_elf32_note; +#endif + + cc->gdb_num_core_regs = 71; +#ifndef CONFIG_USER_ONLY + cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; +#endif +#ifdef USE_APPLE_GDB + cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; + cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; + cc->gdb_num_core_regs = 71 + 32; +#endif + + cc->gdb_arch_name = ppc_gdb_arch_name; +#if defined(TARGET_PPC64) + cc->gdb_core_xml_file = "power64-core.xml"; +#else + cc->gdb_core_xml_file = "power-core.xml"; +#endif +#ifndef CONFIG_USER_ONLY + cc->virtio_is_big_endian = ppc_cpu_is_big_endian; +#endif +#ifdef CONFIG_TCG + cc->tcg_initialize = ppc_translate_init; + cc->tlb_fill = ppc_cpu_tlb_fill; +#endif +#ifndef CONFIG_USER_ONLY + cc->cpu_exec_enter = ppc_cpu_exec_enter; + cc->cpu_exec_exit = ppc_cpu_exec_exit; +#endif + + cc->disas_set_info = ppc_disas_set_info; + + dc->fw_name = "PowerPC,UNKNOWN"; +} + +static const TypeInfo ppc_cpu_type_info = { + .name = TYPE_POWERPC_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(PowerPCCPU), + .instance_init = ppc_cpu_instance_init, + .instance_finalize = ppc_cpu_instance_finalize, + .abstract = true, + .class_size = sizeof(PowerPCCPUClass), + .class_init = ppc_cpu_class_init, +}; + +#ifndef CONFIG_USER_ONLY +static const TypeInfo ppc_vhyp_type_info = { + .name = TYPE_PPC_VIRTUAL_HYPERVISOR, + .parent = TYPE_INTERFACE, + .class_size = sizeof(PPCVirtualHypervisorClass), +}; +#endif + +static void ppc_cpu_register_types(void) +{ + type_register_static(&ppc_cpu_type_info); +#ifndef CONFIG_USER_ONLY + type_register_static(&ppc_vhyp_type_info); +#endif +} + +type_init(ppc_cpu_register_types) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c deleted file mode 100644 index 7e66822b5d..0000000000 --- a/target/ppc/translate_init.inc.c +++ /dev/null @@ -1,10956 +0,0 @@ -/* - * PowerPC CPU initialization for qemu. - * - * Copyright (c) 2003-2007 Jocelyn Mayer - * Copyright 2011 Freescale Semiconductor, Inc. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "disas/dis-asm.h" -#include "exec/gdbstub.h" -#include "kvm_ppc.h" -#include "sysemu/arch_init.h" -#include "sysemu/cpus.h" -#include "sysemu/hw_accel.h" -#include "sysemu/tcg.h" -#include "cpu-models.h" -#include "mmu-hash32.h" -#include "mmu-hash64.h" -#include "qemu/error-report.h" -#include "qemu/module.h" -#include "qemu/qemu-print.h" -#include "qapi/error.h" -#include "qapi/qmp/qnull.h" -#include "qapi/visitor.h" -#include "hw/qdev-properties.h" -#include "hw/ppc/ppc.h" -#include "mmu-book3s-v3.h" -#include "sysemu/qtest.h" -#include "qemu/cutils.h" -#include "disas/capstone.h" -#include "fpu/softfloat.h" -#include "qapi/qapi-commands-machine-target.h" - -/* #define PPC_DUMP_CPU */ -/* #define PPC_DEBUG_SPR */ -/* #define PPC_DUMP_SPR_ACCESSES */ -/* #define USE_APPLE_GDB */ - -/* - * Generic callbacks: - * do nothing but store/retrieve spr value - */ -static void spr_load_dump_spr(int sprn) -{ -#ifdef PPC_DUMP_SPR_ACCESSES - TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_load_dump_spr(cpu_env, t0); - tcg_temp_free_i32(t0); -#endif -} - -static void spr_read_generic(DisasContext *ctx, int gprn, int sprn) -{ - gen_load_spr(cpu_gpr[gprn], sprn); - spr_load_dump_spr(sprn); -} - -static void spr_store_dump_spr(int sprn) -{ -#ifdef PPC_DUMP_SPR_ACCESSES - TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_store_dump_spr(cpu_env, t0); - tcg_temp_free_i32(t0); -#endif -} - -static void spr_write_generic(DisasContext *ctx, int sprn, int gprn) -{ - gen_store_spr(sprn, cpu_gpr[gprn]); - spr_store_dump_spr(sprn); -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) -{ -#ifdef TARGET_PPC64 - TCGv t0 = tcg_temp_new(); - tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); - spr_store_dump_spr(sprn); -#else - spr_write_generic(ctx, sprn, gprn); -#endif -} - -static void spr_write_clear(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - gen_load_spr(t0, sprn); - tcg_gen_neg_tl(t1, cpu_gpr[gprn]); - tcg_gen_and_tl(t0, t0, t1); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) -{ -} - -#endif - -/* SPR common to all PowerPC */ -/* XER */ -static void spr_read_xer(DisasContext *ctx, int gprn, int sprn) -{ - gen_read_xer(ctx, cpu_gpr[gprn]); -} - -static void spr_write_xer(DisasContext *ctx, int sprn, int gprn) -{ - gen_write_xer(cpu_gpr[gprn]); -} - -/* LR */ -static void spr_read_lr(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); -} - -static void spr_write_lr(DisasContext *ctx, int sprn, int gprn) -{ - tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); -} - -/* CFAR */ -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); -} - -static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) -{ - tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); -} -#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ - -/* CTR */ -static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); -} - -static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) -{ - tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); -} - -/* User read access to SPR */ -/* USPRx */ -/* UMMCRx */ -/* UPMCx */ -/* USIA */ -/* UDECR */ -static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) -{ - gen_load_spr(cpu_gpr[gprn], sprn + 0x10); -} - -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) -{ - gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); -} -#endif - -/* SPR common to all non-embedded PowerPC */ -/* DECR */ -#if !defined(CONFIG_USER_ONLY) -static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } -} - -static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } -} -#endif - -/* SPR common to all non-embedded PowerPC, except 601 */ -/* Time base */ -static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -ATTRIBUTE_UNUSED -static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); -} - -ATTRIBUTE_UNUSED -static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -ATTRIBUTE_UNUSED -static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); -} - -ATTRIBUTE_UNUSED -static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); -} - -#if defined(TARGET_PPC64) -ATTRIBUTE_UNUSED -static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_purr(cpu_gpr[gprn], cpu_env); -} - -static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); -} - -/* HDECR */ -static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) -{ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - gen_stop_exception(ctx); - } -} - -static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); -} - -static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); -} - -#endif -#endif - -#if !defined(CONFIG_USER_ONLY) -/* IBAT0U...IBAT0U */ -/* IBAT0L...IBAT7L */ -static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); -} - -static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, - IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); -} - -static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -/* DBAT0U...DBAT7U */ -/* DBAT0L...DBAT7L */ -static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, - DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); -} - -static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, - DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); -} - -static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -/* SDR1 */ -static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); -} - -#if defined(TARGET_PPC64) -/* 64 bits PowerPC specific SPRs */ -/* PIDR */ -static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); -} - -static void spr_read_hior(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); -} - -static void spr_write_hior(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); - tcg_temp_free(t0); -} -static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); -} - -/* DPDES */ -static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); -} - -static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); -} -#endif -#endif - -/* PowerPC 601 specific registers */ -/* RTC */ -static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); -} - -static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); - /* Must stop the translation as endianness may have changed */ - gen_stop_exception(ctx); -} -#endif - -/* Unified bats */ -#if !defined(CONFIG_USER_ONLY) -static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); -} - -static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} -#endif - -/* PowerPC 40x specific registers */ -#if !defined(CONFIG_USER_ONLY) -static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); -} - -static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) -{ - gen_store_spr(sprn, cpu_gpr[gprn]); - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); - /* We must stop translation as we may have rebooted */ - gen_stop_exception(ctx); -} - -static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); -} -#endif - -/* PowerPC 403 specific registers */ -/* PBL1 / PBU1 / PBL2 / PBU2 */ -#if !defined(CONFIG_USER_ONLY) -static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, - offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); -} - -static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); - gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} - -static void spr_write_pir(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); - gen_store_spr(SPR_PIR, t0); - tcg_temp_free(t0); -} -#endif - -/* SPE specific registers */ -static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); - tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); - tcg_temp_free_i32(t0); -} - -static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); - tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); - tcg_temp_free_i32(t0); -} - -#if !defined(CONFIG_USER_ONLY) -/* Callback used to write the exception vector base */ -static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); -} - -static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) -{ - int sprn_offs; - - if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { - sprn_offs = sprn - SPR_BOOKE_IVOR0; - } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { - sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; - } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { - sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; - } else { - printf("Trying to write an unknown exception vector %d %03x\n", - sprn, sprn); - gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); - return; - } - - TCGv t0 = tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); -} -#endif - -static inline void vscr_init(CPUPPCState *env, uint32_t val) -{ - /* Altivec always uses round-to-nearest */ - set_float_rounding_mode(float_round_nearest_even, &env->vec_status); - helper_mtvscr(env, val); -} - -#ifdef CONFIG_USER_ONLY -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, initial_value) -#else -#if !defined(CONFIG_KVM) -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, oea_read, oea_write, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, initial_value) -#else -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, oea_read, oea_write, \ - one_reg_id, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) -#endif -#endif - -#define spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, initial_value) \ - spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, 0, initial_value) - -#define spr_register_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - initial_value) \ - spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - 0, initial_value) - -static inline void _spr_register(CPUPPCState *env, int num, - const char *name, - void (*uea_read)(DisasContext *ctx, - int gprn, int sprn), - void (*uea_write)(DisasContext *ctx, - int sprn, int gprn), -#if !defined(CONFIG_USER_ONLY) - - void (*oea_read)(DisasContext *ctx, - int gprn, int sprn), - void (*oea_write)(DisasContext *ctx, - int sprn, int gprn), - void (*hea_read)(DisasContext *opaque, - int gprn, int sprn), - void (*hea_write)(DisasContext *opaque, - int sprn, int gprn), -#endif -#if defined(CONFIG_KVM) - uint64_t one_reg_id, -#endif - target_ulong initial_value) -{ - ppc_spr_t *spr; - - spr = &env->spr_cb[num]; - if (spr->name != NULL || env->spr[num] != 0x00000000 || -#if !defined(CONFIG_USER_ONLY) - spr->oea_read != NULL || spr->oea_write != NULL || -#endif - spr->uea_read != NULL || spr->uea_write != NULL) { - printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); - exit(1); - } -#if defined(PPC_DEBUG_SPR) - printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, - name, initial_value); -#endif - spr->name = name; - spr->uea_read = uea_read; - spr->uea_write = uea_write; -#if !defined(CONFIG_USER_ONLY) - spr->oea_read = oea_read; - spr->oea_write = oea_write; - spr->hea_read = hea_read; - spr->hea_write = hea_write; -#endif -#if defined(CONFIG_KVM) - spr->one_reg_id = one_reg_id, -#endif - env->spr[num] = spr->default_value = initial_value; -} - -/* Generic PowerPC SPRs */ -static void gen_spr_generic(CPUPPCState *env) -{ - /* Integer processing */ - spr_register(env, SPR_XER, "XER", - &spr_read_xer, &spr_write_xer, - &spr_read_xer, &spr_write_xer, - 0x00000000); - /* Branch contol */ - spr_register(env, SPR_LR, "LR", - &spr_read_lr, &spr_write_lr, - &spr_read_lr, &spr_write_lr, - 0x00000000); - spr_register(env, SPR_CTR, "CTR", - &spr_read_ctr, &spr_write_ctr, - &spr_read_ctr, &spr_write_ctr, - 0x00000000); - /* Interrupt processing */ - spr_register(env, SPR_SRR0, "SRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SRR1, "SRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Processor control */ - spr_register(env, SPR_SPRG0, "SPRG0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG1, "SPRG1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG2, "SPRG2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG3, "SPRG3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR common to all non-embedded PowerPC, including 601 */ -static void gen_spr_ne_601(CPUPPCState *env) -{ - /* Exception processing */ - spr_register_kvm(env, SPR_DSISR, "DSISR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DSISR, 0x00000000); - spr_register_kvm(env, SPR_DAR, "DAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DAR, 0x00000000); - /* Timer */ - spr_register(env, SPR_DECR, "DECR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_decr, &spr_write_decr, - 0x00000000); -} - -/* Storage Description Register 1 */ -static void gen_spr_sdr1(CPUPPCState *env) -{ -#ifndef CONFIG_USER_ONLY - if (env->has_hv_mode) { - /* - * SDR1 is a hypervisor resource on CPUs which have a - * hypervisor mode - */ - spr_register_hv(env, SPR_SDR1, "SDR1", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_sdr1, - 0x00000000); - } else { - spr_register(env, SPR_SDR1, "SDR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_sdr1, - 0x00000000); - } -#endif -} - -/* BATs 0-3 */ -static void gen_low_BATs(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register(env, SPR_IBAT0U, "IBAT0U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatu, - 0x00000000); - spr_register(env, SPR_IBAT0L, "IBAT0L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatl, - 0x00000000); - spr_register(env, SPR_IBAT1U, "IBAT1U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatu, - 0x00000000); - spr_register(env, SPR_IBAT1L, "IBAT1L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatl, - 0x00000000); - spr_register(env, SPR_IBAT2U, "IBAT2U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatu, - 0x00000000); - spr_register(env, SPR_IBAT2L, "IBAT2L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatl, - 0x00000000); - spr_register(env, SPR_IBAT3U, "IBAT3U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatu, - 0x00000000); - spr_register(env, SPR_IBAT3L, "IBAT3L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat, &spr_write_ibatl, - 0x00000000); - spr_register(env, SPR_DBAT0U, "DBAT0U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatu, - 0x00000000); - spr_register(env, SPR_DBAT0L, "DBAT0L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatl, - 0x00000000); - spr_register(env, SPR_DBAT1U, "DBAT1U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatu, - 0x00000000); - spr_register(env, SPR_DBAT1L, "DBAT1L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatl, - 0x00000000); - spr_register(env, SPR_DBAT2U, "DBAT2U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatu, - 0x00000000); - spr_register(env, SPR_DBAT2L, "DBAT2L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatl, - 0x00000000); - spr_register(env, SPR_DBAT3U, "DBAT3U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatu, - 0x00000000); - spr_register(env, SPR_DBAT3L, "DBAT3L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat, &spr_write_dbatl, - 0x00000000); - env->nb_BATs += 4; -#endif -} - -/* BATs 4-7 */ -static void gen_high_BATs(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register(env, SPR_IBAT4U, "IBAT4U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatu_h, - 0x00000000); - spr_register(env, SPR_IBAT4L, "IBAT4L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatl_h, - 0x00000000); - spr_register(env, SPR_IBAT5U, "IBAT5U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatu_h, - 0x00000000); - spr_register(env, SPR_IBAT5L, "IBAT5L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatl_h, - 0x00000000); - spr_register(env, SPR_IBAT6U, "IBAT6U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatu_h, - 0x00000000); - spr_register(env, SPR_IBAT6L, "IBAT6L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatl_h, - 0x00000000); - spr_register(env, SPR_IBAT7U, "IBAT7U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatu_h, - 0x00000000); - spr_register(env, SPR_IBAT7L, "IBAT7L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_ibat_h, &spr_write_ibatl_h, - 0x00000000); - spr_register(env, SPR_DBAT4U, "DBAT4U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatu_h, - 0x00000000); - spr_register(env, SPR_DBAT4L, "DBAT4L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatl_h, - 0x00000000); - spr_register(env, SPR_DBAT5U, "DBAT5U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatu_h, - 0x00000000); - spr_register(env, SPR_DBAT5L, "DBAT5L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatl_h, - 0x00000000); - spr_register(env, SPR_DBAT6U, "DBAT6U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatu_h, - 0x00000000); - spr_register(env, SPR_DBAT6L, "DBAT6L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatl_h, - 0x00000000); - spr_register(env, SPR_DBAT7U, "DBAT7U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatu_h, - 0x00000000); - spr_register(env, SPR_DBAT7L, "DBAT7L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dbat_h, &spr_write_dbatl_h, - 0x00000000); - env->nb_BATs += 4; -#endif -} - -/* Generic PowerPC time base */ -static void gen_tbl(CPUPPCState *env) -{ - spr_register(env, SPR_VTBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_TBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, &spr_write_tbl, - 0x00000000); - spr_register(env, SPR_VTBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_TBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, &spr_write_tbu, - 0x00000000); -} - -/* Softare table search registers */ -static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) -{ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = nb_tlbs; - env->nb_ways = nb_ways; - env->id_tlbs = 1; - env->tlb_type = TLB_6XX; - spr_register(env, SPR_DMISS, "DMISS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_DCMP, "DCMP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_HASH1, "HASH1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_HASH2, "HASH2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_IMISS, "IMISS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_ICMP, "ICMP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_RPA, "RPA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif -} - -/* SPR common to MPC755 and G2 */ -static void gen_spr_G2_755(CPUPPCState *env) -{ - /* SGPRs */ - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR common to all 7xx PowerPC implementations */ -static void gen_spr_7xx(CPUPPCState *env) -{ - /* Breakpoints */ - /* XXX : not implemented */ - spr_register_kvm(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DABR, 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Cache management */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTC, "ICTC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Performance monitors */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_MMCR0, "MMCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_MMCR1, "MMCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC1, "PMC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC2, "PMC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC3, "PMC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC4, "PMC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_SIAR, "SIAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC1, "UPMC1", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC2, "UPMC2", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC3, "UPMC3", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC4, "UPMC4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_USIAR, "USIAR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -#ifdef TARGET_PPC64 -#ifndef CONFIG_USER_ONLY -static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - - /* - * Note, the HV=1 PR=0 case is handled earlier by simply using - * spr_write_generic for HV mode in the SPR table - */ - - /* Build insertion mask into t1 based on context */ - if (ctx->pr) { - gen_load_spr(t1, SPR_UAMOR); - } else { - gen_load_spr(t1, SPR_AMOR); - } - - /* Mask new bits into t2 */ - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); - - /* Load AMR and clear new bits in t0 */ - gen_load_spr(t0, SPR_AMR); - tcg_gen_andc_tl(t0, t0, t1); - - /* Or'in new bits and write it out */ - tcg_gen_or_tl(t0, t0, t2); - gen_store_spr(SPR_AMR, t0); - spr_store_dump_spr(SPR_AMR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); -} - -static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - - /* - * Note, the HV=1 case is handled earlier by simply using - * spr_write_generic for HV mode in the SPR table - */ - - /* Build insertion mask into t1 based on context */ - gen_load_spr(t1, SPR_AMOR); - - /* Mask new bits into t2 */ - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); - - /* Load AMR and clear new bits in t0 */ - gen_load_spr(t0, SPR_UAMOR); - tcg_gen_andc_tl(t0, t0, t1); - - /* Or'in new bits and write it out */ - tcg_gen_or_tl(t0, t0, t2); - gen_store_spr(SPR_UAMOR, t0); - spr_store_dump_spr(SPR_UAMOR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); -} - -static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_temp_new(); - - /* - * Note, the HV=1 case is handled earlier by simply using - * spr_write_generic for HV mode in the SPR table - */ - - /* Build insertion mask into t1 based on context */ - gen_load_spr(t1, SPR_AMOR); - - /* Mask new bits into t2 */ - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); - - /* Load AMR and clear new bits in t0 */ - gen_load_spr(t0, SPR_IAMR); - tcg_gen_andc_tl(t0, t0, t1); - - /* Or'in new bits and write it out */ - tcg_gen_or_tl(t0, t0, t2); - gen_store_spr(SPR_IAMR, t0); - spr_store_dump_spr(SPR_IAMR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); -} -#endif /* CONFIG_USER_ONLY */ - -static void gen_spr_amr(CPUPPCState *env) -{ -#ifndef CONFIG_USER_ONLY - /* - * Virtual Page Class Key protection - * - * The AMR is accessible either via SPR 13 or SPR 29. 13 is - * userspace accessible, 29 is privileged. So we only need to set - * the kvm ONE_REG id on one of them, we use 29 - */ - spr_register(env, SPR_UAMR, "UAMR", - &spr_read_generic, &spr_write_amr, - &spr_read_generic, &spr_write_amr, - 0); - spr_register_kvm_hv(env, SPR_AMR, "AMR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_amr, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_AMR, 0); - spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_uamor, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_UAMOR, 0); - spr_register_hv(env, SPR_AMOR, "AMOR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0); -#endif /* !CONFIG_USER_ONLY */ -} - -static void gen_spr_iamr(CPUPPCState *env) -{ -#ifndef CONFIG_USER_ONLY - spr_register_kvm_hv(env, SPR_IAMR, "IAMR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_iamr, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_IAMR, 0); -#endif /* !CONFIG_USER_ONLY */ -} -#endif /* TARGET_PPC64 */ - -#ifndef CONFIG_USER_ONLY -static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) -{ - gen_helper_fixup_thrm(cpu_env); - gen_load_spr(cpu_gpr[gprn], sprn); - spr_load_dump_spr(sprn); -} -#endif /* !CONFIG_USER_ONLY */ - -static void gen_spr_thrm(CPUPPCState *env) -{ - /* Thermal management */ - /* XXX : not implemented */ - spr_register(env, SPR_THRM1, "THRM1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_thrm, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_THRM2, "THRM2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_thrm, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_THRM3, "THRM3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_thrm, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 604 implementation */ -static void gen_spr_604(CPUPPCState *env) -{ - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* Breakpoints */ - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register_kvm(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DABR, 0x00000000); - /* Performance counters */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_MMCR0, "MMCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC1, "PMC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC2, "PMC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_SIAR, "SIAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_SDA, "SDA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 603 implementation */ -static void gen_spr_603(CPUPPCState *env) -{ - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Breakpoints */ - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - -} - -/* SPR specific to PowerPC G2 implementation */ -static void gen_spr_G2(CPUPPCState *env) -{ - /* Memory base address */ - /* MBAR */ - /* XXX : not implemented */ - spr_register(env, SPR_MBAR, "MBAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Exception processing */ - spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Breakpoints */ - /* XXX : not implemented */ - spr_register(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_DABR2, "DABR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR2, "IABR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IBCR, "IBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_DBCR, "DBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 602 implementation */ -static void gen_spr_602(CPUPPCState *env) -{ - /* ESA registers */ - /* XXX : not implemented */ - spr_register(env, SPR_SER, "SER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_SEBR, "SEBR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_ESASRR, "ESASRR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Floating point status */ - /* XXX : not implemented */ - spr_register(env, SPR_SP, "SP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_LT, "LT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Watchdog timer */ - /* XXX : not implemented */ - spr_register(env, SPR_TCR, "TCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Interrupt base */ - spr_register(env, SPR_IBR, "IBR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 601 implementation */ -static void gen_spr_601(CPUPPCState *env) -{ - /* Multiplication/division register */ - /* MQ */ - spr_register(env, SPR_MQ, "MQ", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* RTC registers */ - spr_register(env, SPR_601_RTCU, "RTCU", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_601_rtcu, - 0x00000000); - spr_register(env, SPR_601_VRTCU, "RTCU", - &spr_read_601_rtcu, SPR_NOACCESS, - &spr_read_601_rtcu, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_601_RTCL, "RTCL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_601_rtcl, - 0x00000000); - spr_register(env, SPR_601_VRTCL, "RTCL", - &spr_read_601_rtcl, SPR_NOACCESS, - &spr_read_601_rtcl, SPR_NOACCESS, - 0x00000000); - /* Timer */ -#if 0 /* ? */ - spr_register(env, SPR_601_UDECR, "UDECR", - &spr_read_decr, SPR_NOACCESS, - &spr_read_decr, SPR_NOACCESS, - 0x00000000); -#endif - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - spr_register(env, SPR_IBAT0U, "IBAT0U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatu, - 0x00000000); - spr_register(env, SPR_IBAT0L, "IBAT0L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatl, - 0x00000000); - spr_register(env, SPR_IBAT1U, "IBAT1U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatu, - 0x00000000); - spr_register(env, SPR_IBAT1L, "IBAT1L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatl, - 0x00000000); - spr_register(env, SPR_IBAT2U, "IBAT2U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatu, - 0x00000000); - spr_register(env, SPR_IBAT2L, "IBAT2L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatl, - 0x00000000); - spr_register(env, SPR_IBAT3U, "IBAT3U", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatu, - 0x00000000); - spr_register(env, SPR_IBAT3L, "IBAT3L", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_601_ubat, &spr_write_601_ubatl, - 0x00000000); - env->nb_BATs = 4; -#endif -} - -static void gen_spr_74xx(CPUPPCState *env) -{ - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_74XX_MMCR2, "MMCR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX: not implemented */ - spr_register(env, SPR_BAMR, "BAMR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MSSCR0, "MSSCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Altivec */ - spr_register(env, SPR_VRSAVE, "VRSAVE", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Not strictly an SPR */ - vscr_init(env, 0x00010000); -} - -static void gen_l3_ctrl(CPUPPCState *env) -{ - /* L3CR */ - /* XXX : not implemented */ - spr_register(env, SPR_L3CR, "L3CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3ITCR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR0, "L3ITCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3PM */ - /* XXX : not implemented */ - spr_register(env, SPR_L3PM, "L3PM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) -{ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = nb_tlbs; - env->nb_ways = nb_ways; - env->id_tlbs = 1; - env->tlb_type = TLB_6XX; - /* XXX : not implemented */ - spr_register(env, SPR_PTEHI, "PTEHI", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_PTELO, "PTELO", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_TLBMISS, "TLBMISS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); -} - -static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) -{ - TCGv t0 = tcg_temp_new(); - - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); - gen_store_spr(sprn, t0); - tcg_temp_free(t0); -} - -static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); -} - -static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) -{ - TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); -} -static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); -} -static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); -} - -#endif - -static void gen_spr_usprg3(CPUPPCState *env) -{ - spr_register(env, SPR_USPRG3, "USPRG3", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); -} - -static void gen_spr_usprgh(CPUPPCState *env) -{ - spr_register(env, SPR_USPRG4, "USPRG4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_USPRG5, "USPRG5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_USPRG6, "USPRG6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_USPRG7, "USPRG7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); -} - -/* PowerPC BookE SPR */ -static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask) -{ - const char *ivor_names[64] = { - "IVOR0", "IVOR1", "IVOR2", "IVOR3", - "IVOR4", "IVOR5", "IVOR6", "IVOR7", - "IVOR8", "IVOR9", "IVOR10", "IVOR11", - "IVOR12", "IVOR13", "IVOR14", "IVOR15", - "IVOR16", "IVOR17", "IVOR18", "IVOR19", - "IVOR20", "IVOR21", "IVOR22", "IVOR23", - "IVOR24", "IVOR25", "IVOR26", "IVOR27", - "IVOR28", "IVOR29", "IVOR30", "IVOR31", - "IVOR32", "IVOR33", "IVOR34", "IVOR35", - "IVOR36", "IVOR37", "IVOR38", "IVOR39", - "IVOR40", "IVOR41", "IVOR42", "IVOR43", - "IVOR44", "IVOR45", "IVOR46", "IVOR47", - "IVOR48", "IVOR49", "IVOR50", "IVOR51", - "IVOR52", "IVOR53", "IVOR54", "IVOR55", - "IVOR56", "IVOR57", "IVOR58", "IVOR59", - "IVOR60", "IVOR61", "IVOR62", "IVOR63", - }; -#define SPR_BOOKE_IVORxx (-1) - int ivor_sprn[64] = { - SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, - SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, - SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, - SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, - SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, - SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, - }; - int i; - - /* Interrupt processing */ - spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Debug */ - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC1, "IAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC2, "IAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DAC1, "DAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - 0x00000000); - spr_register(env, SPR_BOOKE_DEAR, "DEAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_ESR, "ESR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_IVPR, "IVPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_excp_prefix, - 0x00000000); - /* Exception vectors */ - for (i = 0; i < 64; i++) { - if (ivor_mask & (1ULL << i)) { - if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { - fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); - exit(1); - } - spr_register(env, ivor_sprn[i], ivor_names[i], - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_excp_vector, - 0x00000000); - } - } - spr_register(env, SPR_BOOKE_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_pid, - 0x00000000); - spr_register(env, SPR_BOOKE_TCR, "TCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_tcr, - 0x00000000); - spr_register(env, SPR_BOOKE_TSR, "TSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_tsr, - 0x00000000); - /* Timer */ - spr_register(env, SPR_DECR, "DECR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_decr, &spr_write_decr, - 0x00000000); - spr_register(env, SPR_BOOKE_DECAR, "DECAR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - /* SPRGs */ - spr_register(env, SPR_USPRG0, "USPRG0", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, - uint32_t maxsize, uint32_t flags, - uint32_t nentries) -{ - return (assoc << TLBnCFG_ASSOC_SHIFT) | - (minsize << TLBnCFG_MINSIZE_SHIFT) | - (maxsize << TLBnCFG_MAXSIZE_SHIFT) | - flags | nentries; -} - -/* BookE 2.06 storage control registers */ -static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, - uint32_t *tlbncfg, uint32_t mmucfg) -{ -#if !defined(CONFIG_USER_ONLY) - const char *mas_names[8] = { - "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", - }; - int mas_sprn[8] = { - SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, - SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, - }; - int i; - - /* TLB assist registers */ - /* XXX : not implemented */ - for (i = 0; i < 8; i++) { - void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = - &spr_write_generic32; - if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { - uea_write = &spr_write_generic; - } - if (mas_mask & (1 << i)) { - spr_register(env, mas_sprn[i], mas_names[i], - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, uea_write, - 0x00000000); - } - } - if (env->nb_pids > 1) { - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_PID1, "PID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_pid, - 0x00000000); - } - if (env->nb_pids > 2) { - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_PID2, "PID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_pid, - 0x00000000); - } - - spr_register(env, SPR_BOOKE_EPLC, "EPLC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_eplc, - 0x00000000); - spr_register(env, SPR_BOOKE_EPSC, "EPSC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_epsc, - 0x00000000); - - /* XXX : not implemented */ - spr_register(env, SPR_MMUCFG, "MMUCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - mmucfg); - switch (env->nb_ways) { - case 4: - spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[3]); - /* Fallthru */ - case 3: - spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[2]); - /* Fallthru */ - case 2: - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[1]); - /* Fallthru */ - case 1: - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - tlbncfg[0]); - /* Fallthru */ - case 0: - default: - break; - } -#endif - - gen_spr_usprgh(env); -} - -/* SPR specific to PowerPC 440 implementation */ -static void gen_spr_440(CPUPPCState *env) -{ - /* Cache control */ - /* XXX : not implemented */ - spr_register(env, SPR_440_DNV0, "DNV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DNV1, "DNV1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DNV2, "DNV2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DNV3, "DNV3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DTV0, "DTV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DTV1, "DTV1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DTV2, "DTV2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DTV3, "DTV3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DVLIM, "DVLIM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_INV0, "INV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_INV1, "INV1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_INV2, "INV2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_INV3, "INV3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_ITV0, "ITV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_ITV1, "ITV1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_ITV2, "ITV2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_ITV3, "ITV3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_IVLIM, "IVLIM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Cache debug */ - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_DBDR, "DBDR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Processor control */ - spr_register(env, SPR_4xx_CCR0, "CCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_440_RSTCFG, "RSTCFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* Storage control */ - spr_register(env, SPR_440_MMUCR, "MMUCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR shared between PowerPC 40x implementations */ -static void gen_spr_40x(CPUPPCState *env) -{ - /* Cache */ - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCCR, "DCCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_ICCR, "ICCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* Exception */ - spr_register(env, SPR_40x_DEAR, "DEAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ESR, "ESR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_EVPR, "EVPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_excp_prefix, - 0x00000000); - spr_register(env, SPR_40x_SRR2, "SRR2", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_SRR3, "SRR3", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Timers */ - spr_register(env, SPR_40x_PIT, "PIT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_40x_pit, &spr_write_40x_pit, - 0x00000000); - spr_register(env, SPR_40x_TCR, "TCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_tcr, - 0x00000000); - spr_register(env, SPR_40x_TSR, "TSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke_tsr, - 0x00000000); -} - -/* SPR specific to PowerPC 405 implementation */ -static void gen_spr_405(CPUPPCState *env) -{ - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_4xx_CCR0, "CCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00700000); - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_DBCR1, "DBCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_DVC1, "DVC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_DVC2, "DVC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_IAC2, "IAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Storage control */ - /* XXX: TODO: not implemented */ - spr_register(env, SPR_405_SLER, "SLER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_sler, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_SU0R, "SU0R", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* SPRG */ - spr_register(env, SPR_USPRG0, "USPRG0", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - spr_read_generic, &spr_write_generic, - 0x00000000); - gen_spr_usprgh(env); -} - -/* SPR shared between PowerPC 401 & 403 implementations */ -static void gen_spr_401_403(CPUPPCState *env) -{ - /* Time base */ - spr_register(env, SPR_403_VTBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBL, "TBL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbl, - 0x00000000); - spr_register(env, SPR_403_VTBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBU, "TBU", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbu, - 0x00000000); - /* Debug */ - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_403_CDBCR, "CDBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 401 implementation */ -static void gen_spr_401(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Storage control */ - /* XXX: TODO: not implemented */ - spr_register(env, SPR_405_SLER, "SLER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_sler, - 0x00000000); - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_401x2(CPUPPCState *env) -{ - gen_spr_401(env); - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 403 implementation */ -static void gen_spr_403(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC2, "IAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_403_real(CPUPPCState *env) -{ - spr_register(env, SPR_403_PBL1, "PBL1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU1, "PBU1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBL2, "PBL2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU2, "PBU2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); -} - -static void gen_spr_403_mmu(CPUPPCState *env) -{ - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC compression coprocessor extension */ -static void gen_spr_compress(CPUPPCState *env) -{ - /* XXX : not implemented */ - spr_register(env, SPR_401_SKR, "SKR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_5xx_8xx(CPUPPCState *env) -{ - /* Exception processing */ - spr_register_kvm(env, SPR_DSISR, "DSISR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DSISR, 0x00000000); - spr_register_kvm(env, SPR_DAR, "DAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DAR, 0x00000000); - /* Timer */ - spr_register(env, SPR_DECR, "DECR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_decr, &spr_write_decr, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_EIE, "EIE", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_EID, "EID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_NRI, "NRI", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPA, "CMPA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPB, "CMPB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPC, "CMPC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPD, "CMPD", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_ECR, "ECR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_DER, "DER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_COUNTA, "COUNTA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_COUNTB, "COUNTB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPE, "CMPE", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPF, "CMPF", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPG, "CMPG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_CMPH, "CMPH", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_BAR, "BAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_DPDR, "DPDR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_IMMR, "IMMR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_5xx(CPUPPCState *env) -{ - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_RCPU_FPECR, "FPECR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_8xx(CPUPPCState *env) -{ - /* XXX : not implemented */ - spr_register(env, SPR_MPC_IC_CST, "IC_CST", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_DC_CST, "DC_CST", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_AP, "MI_AP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_AP, "MD_AP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_TW, "MD_TW", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* - * AMR => SPR 29 (Power 2.04) - * CTRL => SPR 136 (Power 2.04) - * CTRL => SPR 152 (Power 2.04) - * SCOMC => SPR 276 (64 bits ?) - * SCOMD => SPR 277 (64 bits ?) - * TBU40 => SPR 286 (Power 2.04 hypv) - * HSPRG0 => SPR 304 (Power 2.04 hypv) - * HSPRG1 => SPR 305 (Power 2.04 hypv) - * HDSISR => SPR 306 (Power 2.04 hypv) - * HDAR => SPR 307 (Power 2.04 hypv) - * PURR => SPR 309 (Power 2.04 hypv) - * HDEC => SPR 310 (Power 2.04 hypv) - * HIOR => SPR 311 (hypv) - * RMOR => SPR 312 (970) - * HRMOR => SPR 313 (Power 2.04 hypv) - * HSRR0 => SPR 314 (Power 2.04 hypv) - * HSRR1 => SPR 315 (Power 2.04 hypv) - * LPIDR => SPR 317 (970) - * EPR => SPR 702 (Power 2.04 emb) - * perf => 768-783 (Power 2.04) - * perf => 784-799 (Power 2.04) - * PPR => SPR 896 (Power 2.04) - * DABRX => 1015 (Power 2.04 hypv) - * FPECR => SPR 1022 (?) - * ... and more (thermal management, performance counters, ...) - */ - -/*****************************************************************************/ -/* Exception vectors models */ -static void init_excp_4xx_real(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - -static void init_excp_4xx_softmmu(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - -static void init_excp_MPC5xx(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; - env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; - env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; - env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_MPC8xx(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; - env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; - env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; - env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_G2(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; - env->ivor_mask = 0x0000FFF7UL; - env->ivpr_mask = ivpr_mask; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - -static void init_excp_BookE(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - -static void init_excp_601(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_602(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* XXX: exception prefix has a special behavior on 602 */ - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; - env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_603(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_604(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_7x0(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_750cl(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_750cx(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -/* XXX: Check if this is correct */ -static void init_excp_7x5(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_7400(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -static void init_excp_7450(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; - /* Hardware reset vector */ - env->hreset_vector = 0x00000100UL; -#endif -} - -#if defined(TARGET_PPC64) -static void init_excp_970(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; - env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; - env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; - /* Hardware reset vector */ - env->hreset_vector = 0x0000000000000100ULL; -#endif -} - -static void init_excp_POWER7(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; - env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; - env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; - env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; - /* Hardware reset vector */ - env->hreset_vector = 0x0000000000000100ULL; -#endif -} - -static void init_excp_POWER8(CPUPPCState *env) -{ - init_excp_POWER7(env); - -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; - env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; - env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; - env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; -#endif -} - -static void init_excp_POWER9(CPUPPCState *env) -{ - init_excp_POWER8(env); - -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; - env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000; -#endif -} - -static void init_excp_POWER10(CPUPPCState *env) -{ - init_excp_POWER9(env); -} - -#endif - -/*****************************************************************************/ -/* Power management enable checks */ -static int check_pow_none(CPUPPCState *env) -{ - return 0; -} - -static int check_pow_nocheck(CPUPPCState *env) -{ - return 1; -} - -static int check_pow_hid0(CPUPPCState *env) -{ - if (env->spr[SPR_HID0] & 0x00E00000) { - return 1; - } - - return 0; -} - -static int check_pow_hid0_74xx(CPUPPCState *env) -{ - if (env->spr[SPR_HID0] & 0x00600000) { - return 1; - } - - return 0; -} - -static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) -{ - return true; -} - -#ifdef TARGET_PPC64 -static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) -{ - return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); -} -#endif - -/*****************************************************************************/ -/* PowerPC implementations definitions */ - -#define POWERPC_FAMILY(_name) \ - static void \ - glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ - \ - static const TypeInfo \ - glue(glue(ppc_, _name), _cpu_family_type_info) = { \ - .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ - .parent = TYPE_POWERPC_CPU, \ - .abstract = true, \ - .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ - }; \ - \ - static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ - { \ - type_register_static( \ - &glue(glue(ppc_, _name), _cpu_family_type_info)); \ - } \ - \ - type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ - \ - static void glue(glue(ppc_, _name), _cpu_family_class_init) - -static void init_proc_401(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_401(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401"; - pcc->init_proc = init_proc_401; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_WRTEE | PPC_DCR | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x2(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_401x2(env); - gen_spr_compress(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x2"; - pcc->init_proc = init_proc_401x2; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x3(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_401(env); - gen_spr_401x2(env); - gen_spr_compress(env); - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x3"; - pcc->init_proc = init_proc_401x3; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_IOP480(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_401x2(env); - gen_spr_compress(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "IOP480"; - pcc->init_proc = init_proc_IOP480; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_403(env); - gen_spr_403_real(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403"; - pcc->init_proc = init_proc_403; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403GCX(CPUPPCState *env) -{ - gen_spr_40x(env); - gen_spr_401_403(env); - gen_spr_403(env); - gen_spr_403_real(env); - gen_spr_403_mmu(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403 GCX"; - pcc->init_proc = init_proc_403GCX; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_405(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_40x(env); - gen_spr_405(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(405)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 405"; - pcc->init_proc = init_proc_405; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_405; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_440EP(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env, 0x000000000000FFFFULL); - gen_spr_440(env); - gen_spr_usprgh(env); - /* Processor identification */ - spr_register(env, SPR_BOOKE_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC1, "DVC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC2, "DVC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_MCSR, "MCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_CCR1, "CCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_BookE(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(20, 24, 28, 32); -} - -POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 440 EP"; - pcc->init_proc = init_proc_440EP; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_DCR | PPC_WRTEE | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 460 EX"; - pcc->init_proc = init_proc_440EP; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_440GP(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env, 0x000000000000FFFFULL); - gen_spr_440(env); - gen_spr_usprgh(env); - /* Processor identification */ - spr_register(env, SPR_BOOKE_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC1, "DVC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC2, "DVC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_BookE(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* XXX: TODO: allocate internal IRQ controller */ - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(20, 24, 28, 32); -} - -POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 440 GP"; - pcc->init_proc = init_proc_440GP; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_440x4(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env, 0x000000000000FFFFULL); - gen_spr_440(env); - gen_spr_usprgh(env); - /* Processor identification */ - spr_register(env, SPR_BOOKE_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC1, "DVC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC2, "DVC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_BookE(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* XXX: TODO: allocate internal IRQ controller */ - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(20, 24, 28, 32); -} - -POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 440x4"; - pcc->init_proc = init_proc_440x4; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_440x5(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env, 0x000000000000FFFFULL); - gen_spr_440(env); - gen_spr_usprgh(env); - /* Processor identification */ - spr_register(env, SPR_BOOKE_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC1, "DVC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DVC2, "DVC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_MCSR, "MCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_440_CCR1, "CCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_BookE(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(20, 24, 28, 32); -} - -POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 440x5"; - pcc->init_proc = init_proc_440x5; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 440x5 with double precision FPU"; - pcc->init_proc = init_proc_440x5; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_FLOAT | PPC_FLOAT_FSQRT | - PPC_FLOAT_STFIWX | - PPC_DCR | PPC_WRTEE | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_MFTB | - PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | - PPC_440_SPEC; - pcc->insns_flags2 = PPC2_FP_CVT_S64; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | - POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_MPC5xx(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_5xx_8xx(env); - gen_spr_5xx(env); - init_excp_MPC5xx(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* XXX: TODO: allocate internal IRQ controller */ -} - -POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "Freescale 5xx cores (aka RCPU)"; - pcc->init_proc = init_proc_MPC5xx; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_MEM_EIEIO | PPC_MEM_SYNC | - PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | - PPC_MFTB; - pcc->msr_mask = (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_603; - pcc->bus_model = PPC_FLAGS_INPUT_RCPU; - pcc->bfd_mach = bfd_mach_ppc_505; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_MPC8xx(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_5xx_8xx(env); - gen_spr_8xx(env); - init_excp_MPC8xx(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* XXX: TODO: allocate internal IRQ controller */ -} - -POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; - pcc->init_proc = init_proc_MPC8xx; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_MEM_EIEIO | PPC_MEM_SYNC | - PPC_CACHE_ICBI | PPC_MFTB; - pcc->msr_mask = (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_MPC8xx; - pcc->excp_model = POWERPC_EXCP_603; - pcc->bus_model = PPC_FLAGS_INPUT_RCPU; - pcc->bfd_mach = bfd_mach_ppc_860; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_BUS_CLK; -} - -/* Freescale 82xx cores (aka PowerQUICC-II) */ - -static void init_proc_G2(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_G2_755(env); - gen_spr_G2(env); - /* Time base */ - gen_tbl(env); - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation register */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_G2(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC G2"; - pcc->init_proc = init_proc_G2; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_AL) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_G2; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_ec603e; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_G2LE(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_G2_755(env); - gen_spr_G2(env); - /* Time base */ - gen_tbl(env); - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation register */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_G2(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC G2LE"; - pcc->init_proc = init_proc_G2LE; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_AL) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_G2; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_ec603e; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e200(CPUPPCState *env) -{ - /* Time base */ - gen_tbl(env); - gen_spr_BookE(env, 0x000000070000FFFFULL); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", - &spr_read_spefscr, &spr_write_spefscr, - &spr_read_spefscr, &spr_write_spefscr, - 0x00000000); - /* Memory management */ - gen_spr_BookE206(env, 0x0000005D, NULL, 0); - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_BUCSR, "BUCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_CTXCR, "CTXCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_DBCNT, "DBCNT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_DBCR3, "DBCR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC3, "IAC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_IAC4, "IAC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); /* TOFIX */ - spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_e200(env, 0xFFFF0000UL); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* XXX: TODO: allocate internal IRQ controller */ -} - -POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e200 core"; - pcc->init_proc = init_proc_e200; - pcc->check_pow = check_pow_hid0; - /* - * XXX: unimplemented instructions: - * dcblc - * dcbtlst - * dcbtstls - * icblc - * icbtls - * tlbivax - * all SPE multiply-accumulate instructions - */ - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | - PPC_SPE | PPC_SPE_SINGLE | - PPC_WRTEE | PPC_RFDI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | - PPC_BOOKE; - pcc->msr_mask = (1ull << MSR_UCLE) | - (1ull << MSR_SPE) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_860; - pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e300(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_603(env); - /* Time base */ - gen_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Breakpoints */ - /* XXX : not implemented */ - spr_register(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_DABR2, "DABR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IABR2, "IABR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_IBCR, "IBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_DBCR, "DBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_603(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e300 core"; - pcc->init_proc = init_proc_e300; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_AL) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_603; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_603; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) -{ - TCGv val = tcg_temp_new(); - tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); - gen_store_spr(SPR_BOOKE_MAS3, val); - tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); - gen_store_spr(SPR_BOOKE_MAS7, val); - tcg_temp_free(val); -} - -static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) -{ - TCGv mas7 = tcg_temp_new(); - TCGv mas3 = tcg_temp_new(); - gen_load_spr(mas7, SPR_BOOKE_MAS7); - tcg_gen_shli_tl(mas7, mas7, 32); - gen_load_spr(mas3, SPR_BOOKE_MAS3); - tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); - tcg_temp_free(mas3); - tcg_temp_free(mas7); -} - -#endif - -enum fsl_e500_version { - fsl_e500v1, - fsl_e500v2, - fsl_e500mc, - fsl_e5500, - fsl_e6500, -}; - -static void init_proc_e500(CPUPPCState *env, int version) -{ - uint32_t tlbncfg[2]; - uint64_t ivor_mask; - uint64_t ivpr_mask = 0xFFFF0000ULL; - uint32_t l1cfg0 = 0x3800 /* 8 ways */ - | 0x0020; /* 32 kb */ - uint32_t l1cfg1 = 0x3800 /* 8 ways */ - | 0x0020; /* 32 kb */ - uint32_t mmucfg = 0; -#if !defined(CONFIG_USER_ONLY) - int i; -#endif - - /* Time base */ - gen_tbl(env); - /* - * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't - * complain when accessing them. - * gen_spr_BookE(env, 0x0000000F0000FD7FULL); - */ - switch (version) { - case fsl_e500v1: - case fsl_e500v2: - default: - ivor_mask = 0x0000000F0000FFFFULL; - break; - case fsl_e500mc: - case fsl_e5500: - ivor_mask = 0x000003FE0000FFFFULL; - break; - case fsl_e6500: - ivor_mask = 0x000003FF0000FFFFULL; - break; - } - gen_spr_BookE(env, ivor_mask); - gen_spr_usprg3(env); - /* Processor identification */ - spr_register(env, SPR_BOOKE_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", - &spr_read_spefscr, &spr_write_spefscr, - &spr_read_spefscr, &spr_write_spefscr, - 0x00000000); -#if !defined(CONFIG_USER_ONLY) - /* Memory management */ - env->nb_pids = 3; - env->nb_ways = 2; - env->id_tlbs = 0; - switch (version) { - case fsl_e500v1: - tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); - tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - break; - case fsl_e500v2: - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); - tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - break; - case fsl_e500mc: - case fsl_e5500: - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); - tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); - break; - case fsl_e6500: - mmucfg = 0x6510B45; - env->nb_pids = 1; - tlbncfg[0] = 0x08052400; - tlbncfg[1] = 0x40028040; - break; - default: - cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", - env->spr[SPR_PVR]); - } -#endif - /* Cache sizes */ - switch (version) { - case fsl_e500v1: - case fsl_e500v2: - env->dcache_line_size = 32; - env->icache_line_size = 32; - break; - case fsl_e500mc: - case fsl_e5500: - env->dcache_line_size = 64; - env->icache_line_size = 64; - l1cfg0 |= 0x1000000; /* 64 byte cache block size */ - l1cfg1 |= 0x1000000; /* 64 byte cache block size */ - break; - case fsl_e6500: - env->dcache_line_size = 32; - env->icache_line_size = 32; - l1cfg0 |= 0x0F83820; - l1cfg1 |= 0x0B83820; - break; - default: - cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", - env->spr[SPR_PVR]); - } - gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_BBEAR, "BBEAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_BBTAR, "BBTAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_MCAR, "MCAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_MCSR, "MCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_NPIDR, "NPIDR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_BUCSR, "BUCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - l1cfg0); - spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - l1cfg1); - spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_e500_l1csr0, - 0x00000000); - spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_e500_l1csr1, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_MMUCSR0, "MMUCSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_booke206_mmucsr0, - 0x00000000); - spr_register(env, SPR_BOOKE_EPR, "EPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX better abstract into Emb.xxx features */ - if ((version == fsl_e5500) || (version == fsl_e6500)) { - spr_register(env, SPR_BOOKE_EPCR, "EPCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_mas73, &spr_write_mas73, - 0x00000000); - ivpr_mask = (target_ulong)~0xFFFFULL; - } - - if (version == fsl_e6500) { - /* Thread identification */ - spr_register(env, SPR_TIR, "TIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000004); - spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x7FFFFFFC); - } - -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 0; - env->tlb_type = TLB_MAS; - for (i = 0; i < BOOKE206_MAX_TLBN; i++) { - env->nb_tlb += booke206_tlb_size(env, i); - } -#endif - - init_excp_e200(env, ivpr_mask); - /* Allocate hardware IRQ controller */ - ppce500_irq_init(env_archcpu(env)); -} - -static void init_proc_e500v1(CPUPPCState *env) -{ - init_proc_e500(env, fsl_e500v1); -} - -POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e500v1 core"; - pcc->init_proc = init_proc_e500v1; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | - PPC_SPE | PPC_SPE_SINGLE | - PPC_WRTEE | PPC_RFDI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206; - pcc->msr_mask = (1ull << MSR_UCLE) | - (1ull << MSR_SPE) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_860; - pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e500v2(CPUPPCState *env) -{ - init_proc_e500(env, fsl_e500v2); -} - -POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e500v2 core"; - pcc->init_proc = init_proc_e500v2; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | - PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | - PPC_WRTEE | PPC_RFDI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206; - pcc->msr_mask = (1ull << MSR_UCLE) | - (1ull << MSR_SPE) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_860; - pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | - POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e500mc(CPUPPCState *env) -{ - init_proc_e500(env, fsl_e500mc); -} - -POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e500mc core"; - pcc->init_proc = init_proc_e500mc; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | - PPC_WRTEE | PPC_RFDI | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_FLOAT | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | - PPC_FLOAT_STFIWX | PPC_WAIT | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; - pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; - pcc->msr_mask = (1ull << MSR_GS) | - (1ull << MSR_UCLE) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PX) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - /* FIXME: figure out the correct flag for e500mc */ - pcc->bfd_mach = bfd_mach_ppc_e500; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -#ifdef TARGET_PPC64 -static void init_proc_e5500(CPUPPCState *env) -{ - init_proc_e500(env, fsl_e5500); -} - -POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e5500 core"; - pcc->init_proc = init_proc_e5500; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | - PPC_WRTEE | PPC_RFDI | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_FLOAT | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | - PPC_FLOAT_STFIWX | PPC_WAIT | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | - PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; - pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | - PPC2_FP_CVT_S64; - pcc->msr_mask = (1ull << MSR_CM) | - (1ull << MSR_GS) | - (1ull << MSR_UCLE) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PX) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - /* FIXME: figure out the correct flag for e5500 */ - pcc->bfd_mach = bfd_mach_ppc_e500; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e6500(CPUPPCState *env) -{ - init_proc_e500(env, fsl_e6500); -} - -POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "e6500 core"; - pcc->init_proc = init_proc_e6500; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | - PPC_WRTEE | PPC_RFDI | PPC_RFMCI | - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_FLOAT | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | - PPC_FLOAT_STFIWX | PPC_WAIT | - PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | - PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; - pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | - PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; - pcc->msr_mask = (1ull << MSR_CM) | - (1ull << MSR_GS) | - (1ull << MSR_UCLE) | - (1ull << MSR_CE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IS) | - (1ull << MSR_DS) | - (1ull << MSR_PX) | - (1ull << MSR_RI) | - (1ull << MSR_VR); - pcc->mmu_model = POWERPC_MMU_BOOKE206; - pcc->excp_model = POWERPC_EXCP_BOOKE; - pcc->bus_model = PPC_FLAGS_INPUT_BookE; - pcc->bfd_mach = bfd_mach_ppc_e500; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; -} - -#endif - -/* Non-embedded PowerPC */ - -#define POWERPC_MSRR_601 (0x0000000000001040ULL) - -static void init_proc_601(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_601(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_hid0_601, - 0x80010080); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_601_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_601_HID5, "HID5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - init_excp_601(env); - /* - * XXX: beware that dcache line size is 64 - * but dcbz uses 32 bytes "sectors" - * XXX: this breaks clcs instruction ! - */ - env->dcache_line_size = 32; - env->icache_line_size = 64; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(601)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 601"; - pcc->init_proc = init_proc_601; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | - PPC_FLOAT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_601; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; -} - -#define POWERPC_MSRR_601v (0x0000000000001040ULL) - -static void init_proc_601v(CPUPPCState *env) -{ - init_proc_601(env); - /* XXX : not implemented */ - spr_register(env, SPR_601_HID15, "HID15", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 601v"; - pcc->init_proc = init_proc_601v; - pcc->check_pow = check_pow_none; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | - PPC_FLOAT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR); - pcc->mmu_model = POWERPC_MMU_601; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; -} - -static void init_proc_602(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_602(env); - /* Time base */ - gen_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_602(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(602)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 602"; - pcc->init_proc = init_proc_602; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_602_SPEC; - pcc->msr_mask = (1ull << MSR_VSX) | - (1ull << MSR_SA) | - (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - /* XXX: 602 MMU is quite specific. Should add a special case */ - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_602; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_602; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_603(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_603(env); - /* Time base */ - gen_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_603(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(603)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 603"; - pcc->init_proc = init_proc_603; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_603; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_603; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_603E(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_603(env); - /* Time base */ - gen_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_603(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 603e"; - pcc->init_proc = init_proc_603E; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_TGPR) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_603E; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_ec603e; - pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_604(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_604(env); - /* Time base */ - gen_tbl(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - init_excp_604(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(604)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 604"; - pcc->init_proc = init_proc_604; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_604; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_604; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_604E(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_604(env); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_MMCR1, "MMCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC3, "PMC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC4, "PMC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - init_excp_604(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 604E"; - pcc->init_proc = init_proc_604E; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_604; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_604; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_740(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - init_excp_7x0(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(740)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 740"; - pcc->init_proc = init_proc_740; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_750(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - /* - * XXX: high BATs are also present but are known to be bugged on - * die version 1.x - */ - init_excp_7x0(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(750)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 750"; - pcc->init_proc = init_proc_750; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_750cl(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - /* Those registers are fake on 750CL */ - spr_register(env, SPR_THRM1, "THRM1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_THRM2, "THRM2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_THRM3, "THRM3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX: not implemented */ - spr_register(env, SPR_750_TDCL, "TDCL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_750_TDCH, "TDCH", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* DMA */ - /* XXX : not implemented */ - spr_register(env, SPR_750_WPAR, "WPAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_750_DMAL, "DMAL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_750_DMAU, "DMAU", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750CL_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750CL_HID4, "HID4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Quantization registers */ - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR0, "GQR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR1, "GQR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR2, "GQR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR3, "GQR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR4, "GQR4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR5, "GQR5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR6, "GQR6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750_GQR7, "GQR7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - /* PowerPC 750cl has 8 DBATs and 8 IBATs */ - gen_high_BATs(env); - init_excp_750cl(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 750 CL"; - pcc->init_proc = init_proc_750cl; - pcc->check_pow = check_pow_hid0; - /* - * XXX: not implemented: - * cache lock instructions: - * dcbz_l - * floating point paired instructions - * psq_lux - * psq_lx - * psq_stux - * psq_stx - * ps_abs - * ps_add - * ps_cmpo0 - * ps_cmpo1 - * ps_cmpu0 - * ps_cmpu1 - * ps_div - * ps_madd - * ps_madds0 - * ps_madds1 - * ps_merge00 - * ps_merge01 - * ps_merge10 - * ps_merge11 - * ps_mr - * ps_msub - * ps_mul - * ps_muls0 - * ps_muls1 - * ps_nabs - * ps_neg - * ps_nmadd - * ps_nmsub - * ps_res - * ps_rsqrte - * ps_sel - * ps_sub - * ps_sum0 - * ps_sum1 - */ - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_750cx(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* This register is not implemented but is present for compatibility */ - spr_register(env, SPR_SDA, "SDA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - /* PowerPC 750cx has 8 DBATs and 8 IBATs */ - gen_high_BATs(env); - init_excp_750cx(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 750CX"; - pcc->init_proc = init_proc_750cx; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_750fx(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* XXX : not implemented */ - spr_register(env, SPR_750_THRM4, "THRM4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ - gen_high_BATs(env); - init_excp_7x0(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 750FX"; - pcc->init_proc = init_proc_750fx; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_750gx(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* XXX : not implemented (XXX: different from 750fx) */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* XXX : not implemented */ - spr_register(env, SPR_750_THRM4, "THRM4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Hardware implementation registers */ - /* XXX : not implemented (XXX: different from 750fx) */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented (XXX: different from 750fx) */ - spr_register(env, SPR_750FX_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ - gen_high_BATs(env); - init_excp_7x0(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 750GX"; - pcc->init_proc = init_proc_750gx; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_7x0; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_745(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - gen_spr_G2_755(env); - /* Time base */ - gen_tbl(env); - /* Thermal management */ - gen_spr_thrm(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_7x5(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(745)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 745"; - pcc->init_proc = init_proc_745; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_7x5; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_755(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - gen_spr_G2_755(env); - /* Time base */ - gen_tbl(env); - /* L2 cache control */ - /* XXX : not implemented */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_L2PMCR, "L2PMCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Thermal management */ - gen_spr_thrm(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID2, "HID2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_7x5(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(755)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 755"; - pcc->init_proc = init_proc_755; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | - PPC_SEGMENT | PPC_EXTERN; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_7x5; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_750; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7400(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_UBAMR, "UBAMR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX: this seems not implemented on all revisions. */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSCR1, "MSSCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Thermal management */ - gen_spr_thrm(env); - /* Memory management */ - gen_low_BATs(env); - init_excp_7400(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7400 (aka G4)"; - pcc->init_proc = init_proc_7400; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7410(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_UBAMR, "UBAMR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Thermal management */ - gen_spr_thrm(env); - /* L2PMCR */ - /* XXX : not implemented */ - spr_register(env, SPR_L2PMCR, "L2PMCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* LDSTDB */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTDB, "LDSTDB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - init_excp_7400(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7410 (aka G4)"; - pcc->init_proc = init_proc_7410; - pcc->check_pow = check_pow_hid0; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7440(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_UBAMR, "UBAMR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* LDSTCR */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* ICTRL */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MSSSR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* PMC */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7440 (aka G4)"; - pcc->init_proc = init_proc_7440; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7450(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* Level 3 cache control */ - gen_l3_ctrl(env); - /* L3ITCR1 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR1, "L3ITCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3ITCR2 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR2, "L3ITCR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3ITCR3 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR3, "L3ITCR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3OHCR */ - /* XXX : not implemented */ - spr_register(env, SPR_L3OHCR, "L3OHCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_UBAMR, "UBAMR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* LDSTCR */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* ICTRL */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MSSSR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* PMC */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7450 (aka G4)"; - pcc->init_proc = init_proc_7450; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7445(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* LDSTCR */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* ICTRL */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MSSSR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* PMC */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* SPRGs */ - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG4, "USPRG4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG5, "USPRG5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG6, "USPRG6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG7, "USPRG7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7445 (aka G4)"; - pcc->init_proc = init_proc_7445; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7455(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* Level 3 cache control */ - gen_l3_ctrl(env); - /* LDSTCR */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* ICTRL */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MSSSR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* PMC */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* SPRGs */ - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG4, "USPRG4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG5, "USPRG5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG6, "USPRG6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG7, "USPRG7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7455 (aka G4)"; - pcc->init_proc = init_proc_7455; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_7457(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* Level 3 cache control */ - gen_l3_ctrl(env); - /* L3ITCR1 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR1, "L3ITCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3ITCR2 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR2, "L3ITCR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3ITCR3 */ - /* XXX : not implemented */ - spr_register(env, SPR_L3ITCR3, "L3ITCR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* L3OHCR */ - /* XXX : not implemented */ - spr_register(env, SPR_L3OHCR, "L3OHCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* LDSTCR */ - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* ICTRL */ - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MSSSR0 */ - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* PMC */ - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* SPRGs */ - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG4, "USPRG4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG5, "USPRG5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG6, "USPRG6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG7, "USPRG7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 7457 (aka G4)"; - pcc->init_proc = init_proc_7457; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_e600(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_sdr1(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - /* 74xx specific SPR */ - gen_spr_74xx(env); - /* XXX : not implemented */ - spr_register(env, SPR_UBAMR, "UBAMR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_LDSTCR, "LDSTCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_ICTRL, "ICTRL", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_MSSSR0, "MSSSR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_7XX_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* SPRGs */ - spr_register(env, SPR_SPRG4, "SPRG4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG4, "USPRG4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG5, "SPRG5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG5, "USPRG5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG6, "SPRG6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG6, "USPRG6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_SPRG7, "SPRG7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_USPRG7, "USPRG7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - gen_high_BATs(env); - gen_74xx_soft_tlb(env, 128, 2); - init_excp_7450(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC e600"; - pcc->init_proc = init_proc_e600; - pcc->check_pow = check_pow_hid0_74xx; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | - PPC_CACHE_DCBA | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | - PPC_SEGMENT | PPC_EXTERN | - PPC_ALTIVEC; - pcc->insns_flags2 = PPC_NONE; - pcc->msr_mask = (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_EP) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_32B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; -#endif - pcc->excp_model = POWERPC_EXCP_74xx; - pcc->bus_model = PPC_FLAGS_INPUT_6xx; - pcc->bfd_mach = bfd_mach_ppc_7400; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; -} - -#if defined(TARGET_PPC64) -#if defined(CONFIG_USER_ONLY) -#define POWERPC970_HID5_INIT 0x00000080 -#else -#define POWERPC970_HID5_INIT 0x00000000 -#endif - -static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, - int bit, int sprn, int cause) -{ - TCGv_i32 t1 = tcg_const_i32(bit); - TCGv_i32 t2 = tcg_const_i32(sprn); - TCGv_i32 t3 = tcg_const_i32(cause); - - gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); -} - -static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, - int bit, int sprn, int cause) -{ - TCGv_i32 t1 = tcg_const_i32(bit); - TCGv_i32 t2 = tcg_const_i32(sprn); - TCGv_i32 t3 = tcg_const_i32(cause); - - gen_helper_msr_facility_check(cpu_env, t1, t2, t3); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); -} - -static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) -{ - TCGv spr_up = tcg_temp_new(); - TCGv spr = tcg_temp_new(); - - gen_load_spr(spr, sprn - 1); - tcg_gen_shri_tl(spr_up, spr, 32); - tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); - - tcg_temp_free(spr); - tcg_temp_free(spr_up); -} - -static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) -{ - TCGv spr = tcg_temp_new(); - - gen_load_spr(spr, sprn - 1); - tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); - gen_store_spr(sprn - 1, spr); - - tcg_temp_free(spr); -} - -static int check_pow_970(CPUPPCState *env) -{ - if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { - return 1; - } - - return 0; -} - -static void gen_spr_970_hid(CPUPPCState *env) -{ - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - 0x60000000); - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_970_HID5, "HID5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - POWERPC970_HID5_INIT); -} - -static void gen_spr_970_hior(CPUPPCState *env) -{ - spr_register(env, SPR_HIOR, "SPR_HIOR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_hior, &spr_write_hior, - 0x00000000); -} - -static void gen_spr_book3s_ctrl(CPUPPCState *env) -{ - spr_register(env, SPR_CTRL, "SPR_CTRL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_UCTRL, "SPR_UCTRL", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, SPR_NOACCESS, - 0x00000000); -} - -static void gen_spr_book3s_altivec(CPUPPCState *env) -{ - if (!(env->insns_flags & PPC_ALTIVEC)) { - return; - } - - spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_VRSAVE, 0x00000000); - - /* - * Can't find information on what this should be on reset. This - * value is the one used by 74xx processors. - */ - vscr_init(env, 0x00010000); -} - -static void gen_spr_book3s_dbg(CPUPPCState *env) -{ - /* - * TODO: different specs define different scopes for these, - * will have to address this: - * 970: super/write and super/read - * powerisa 2.03..2.04: hypv/write and super/read. - * powerisa 2.05 and newer: hypv/write and hypv/read. - */ - spr_register_kvm(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DABR, 0x00000000); - spr_register_kvm(env, SPR_DABRX, "DABRX", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DABRX, 0x00000000); -} - -static void gen_spr_book3s_207_dbg(CPUPPCState *env) -{ - spr_register_kvm_hv(env, SPR_DAWR, "DAWR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DAWR, 0x00000000); - spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DAWRX, 0x00000000); - spr_register_kvm_hv(env, SPR_CIABR, "CIABR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_CIABR, 0x00000000); -} - -static void gen_spr_970_dbg(CPUPPCState *env) -{ - /* Breakpoints */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_book3s_pmu_sup(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR0, 0x00000000); - spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR1, 0x00000000); - spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCRA, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC1, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC2, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC3, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC4, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC5, 0x00000000); - spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC6, 0x00000000); - spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_SIAR, 0x00000000); - spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_SDAR, 0x00000000); -} - -static void gen_spr_book3s_pmu_user(CPUPPCState *env) -{ - spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC1, "UPMC1", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC2, "UPMC2", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC3, "UPMC3", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC4, "UPMC4", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_USIAR, "USIAR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_USDAR, "USDAR", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); -} - -static void gen_spr_970_pmu_sup(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_970_PMC7, "PMC7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC7, 0x00000000); - spr_register_kvm(env, SPR_970_PMC8, "PMC8", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PMC8, 0x00000000); -} - -static void gen_spr_970_pmu_user(CPUPPCState *env) -{ - spr_register(env, SPR_970_UPMC7, "UPMC7", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_970_UPMC8, "UPMC8", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); -} - -static void gen_spr_power8_pmu_sup(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR2, 0x00000000); - spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCRS, 0x00000000); - spr_register_kvm(env, SPR_POWER_SIER, "SIER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_SIER, 0x00000000); - spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_SPMC1, 0x00000000); - spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_SPMC2, 0x00000000); - spr_register_kvm(env, SPR_TACR, "TACR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_TACR, 0x00000000); - spr_register_kvm(env, SPR_TCSCR, "TCSCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_TCSCR, 0x00000000); - spr_register_kvm(env, SPR_CSIGR, "CSIGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_CSIGR, 0x00000000); -} - -static void gen_spr_power8_pmu_user(CPUPPCState *env) -{ - spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", - &spr_read_ureg, SPR_NOACCESS, - &spr_read_ureg, &spr_write_ureg, - 0x00000000); - spr_register(env, SPR_POWER_USIER, "USIER", - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_power5p_ear(CPUPPCState *env) -{ - /* External access control */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_power5p_tb(CPUPPCState *env) -{ - /* TBU40 (High 40 bits of the Timebase register */ - spr_register_hv(env, SPR_TBU40, "TBU40", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbu40, - 0x00000000); -} - -#if !defined(CONFIG_USER_ONLY) -static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) -{ - TCGv hmer = tcg_temp_new(); - - gen_load_spr(hmer, sprn); - tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); - gen_store_spr(sprn, hmer); - spr_store_dump_spr(sprn); - tcg_temp_free(hmer); -} - -static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) -{ - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -} -#endif /* !defined(CONFIG_USER_ONLY) */ - -static void gen_spr_970_lpar(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* - * PPC970: HID4 covers things later controlled by the LPCR and - * RMOR in later CPUs, but with a different encoding. We only - * support the 970 in "Apple mode" which has all hypervisor - * facilities disabled by strapping, so we can basically just - * ignore it - */ - spr_register(env, SPR_970_HID4, "HID4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif -} - -static void gen_spr_power5p_lpar(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* Logical partitionning */ - spr_register_kvm_hv(env, SPR_LPCR, "LPCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_lpcr, - KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); - spr_register_hv(env, SPR_HDEC, "HDEC", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_hdecr, &spr_write_hdecr, 0); -#endif -} - -static void gen_spr_book3s_ids(CPUPPCState *env) -{ - /* FIXME: Will need to deal with thread vs core only SPRs */ - - /* Processor identification */ - spr_register_hv(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, NULL, - 0x00000000); - spr_register_hv(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TSCR, "TSCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HMER, "HMER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_hmer, - 0x00000000); - spr_register_hv(env, SPR_HMEER, "HMEER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TFMR, "TFMR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_LPIDR, "LPIDR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_lpidr, - 0x00000000); - spr_register_hv(env, SPR_HFSCR, "HFSCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_MMCRC, "MMCRC", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_MMCRH, "MMCRH", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HSPRG0, "HSPRG0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HSPRG1, "HSPRG1", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HSRR0, "HSRR0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HSRR1, "HSRR1", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HDAR, "HDAR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HDSISR, "HDSISR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_HRMOR, "HRMOR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_rmor(CPUPPCState *env) -{ - spr_register_hv(env, SPR_RMOR, "RMOR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void gen_spr_power8_ids(CPUPPCState *env) -{ - /* Thread identification */ - spr_register(env, SPR_TIR, "TIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); -} - -static void gen_spr_book3s_purr(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ - spr_register_kvm_hv(env, SPR_PURR, "PURR", - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, &spr_write_purr, - KVM_REG_PPC_PURR, 0x00000000); - spr_register_kvm_hv(env, SPR_SPURR, "SPURR", - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, &spr_write_purr, - KVM_REG_PPC_SPURR, 0x00000000); -#endif -} - -static void gen_spr_power6_dbg(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register(env, SPR_CFAR, "SPR_CFAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_cfar, &spr_write_cfar, - 0x00000000); -#endif -} - -static void gen_spr_power5p_common(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_PPR, "PPR", - &spr_read_generic, &spr_write_generic, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PPR, 0x00000000); -} - -static void gen_spr_power6_common(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_DSCR, 0x00000000); -#endif - /* - * Register PCR to report POWERPC_EXCP_PRIV_REG instead of - * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. - */ - spr_register_hv(env, SPR_PCR, "PCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pcr, - 0x00000000); -} - -static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_read_generic(ctx, gprn, sprn); -} - -static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_write_generic(ctx, sprn, gprn); -} - -static void gen_spr_power8_tce_address_control(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_TAR, "TAR", - &spr_read_tar, &spr_write_tar, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_TAR, 0x00000000); -} - -static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) -{ - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_generic(ctx, gprn, sprn); -} - -static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) -{ - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_generic(ctx, sprn, gprn); -} - -static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) -{ - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_prev_upper32(ctx, gprn, sprn); -} - -static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) -{ - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_prev_upper32(ctx, sprn, gprn); -} - -static void gen_spr_power8_tm(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_TFHAR, "TFHAR", - &spr_read_tm, &spr_write_tm, - &spr_read_tm, &spr_write_tm, - KVM_REG_PPC_TFHAR, 0x00000000); - spr_register_kvm(env, SPR_TFIAR, "TFIAR", - &spr_read_tm, &spr_write_tm, - &spr_read_tm, &spr_write_tm, - KVM_REG_PPC_TFIAR, 0x00000000); - spr_register_kvm(env, SPR_TEXASR, "TEXASR", - &spr_read_tm, &spr_write_tm, - &spr_read_tm, &spr_write_tm, - KVM_REG_PPC_TEXASR, 0x00000000); - spr_register(env, SPR_TEXASRU, "TEXASRU", - &spr_read_tm_upper32, &spr_write_tm_upper32, - &spr_read_tm_upper32, &spr_write_tm_upper32, - 0x00000000); -} - -static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_generic(ctx, gprn, sprn); -} - -static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_generic(ctx, sprn, gprn); -} - -static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_prev_upper32(ctx, gprn, sprn); -} - -static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) -{ - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_prev_upper32(ctx, sprn, gprn); -} - -static void gen_spr_power8_ebb(CPUPPCState *env) -{ - spr_register(env, SPR_BESCRS, "BESCRS", - &spr_read_ebb, &spr_write_ebb, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BESCRSU, "BESCRSU", - &spr_read_ebb_upper32, &spr_write_ebb_upper32, - &spr_read_prev_upper32, &spr_write_prev_upper32, - 0x00000000); - spr_register(env, SPR_BESCRR, "BESCRR", - &spr_read_ebb, &spr_write_ebb, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_BESCRRU, "BESCRRU", - &spr_read_ebb_upper32, &spr_write_ebb_upper32, - &spr_read_prev_upper32, &spr_write_prev_upper32, - 0x00000000); - spr_register_kvm(env, SPR_EBBHR, "EBBHR", - &spr_read_ebb, &spr_write_ebb, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_EBBHR, 0x00000000); - spr_register_kvm(env, SPR_EBBRR, "EBBRR", - &spr_read_ebb, &spr_write_ebb, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_EBBRR, 0x00000000); - spr_register_kvm(env, SPR_BESCR, "BESCR", - &spr_read_ebb, &spr_write_ebb, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_BESCR, 0x00000000); -} - -/* Virtual Time Base */ -static void gen_spr_vtb(CPUPPCState *env) -{ - spr_register_kvm_hv(env, SPR_VTB, "VTB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_vtb, SPR_NOACCESS, - &spr_read_vtb, &spr_write_vtb, - KVM_REG_PPC_VTB, 0x00000000); -} - -static void gen_spr_power8_fscr(CPUPPCState *env) -{ -#if defined(CONFIG_USER_ONLY) - target_ulong initval = 1ULL << FSCR_TAR; -#else - target_ulong initval = 0; -#endif - spr_register_kvm(env, SPR_FSCR, "FSCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_FSCR, initval); -} - -static void gen_spr_power8_pspb(CPUPPCState *env) -{ - spr_register_kvm(env, SPR_PSPB, "PSPB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, - KVM_REG_PPC_PSPB, 0); -} - -static void gen_spr_power8_dpdes(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* Directed Privileged Door-bell Exception State, used for IPI */ - spr_register_kvm_hv(env, SPR_DPDES, "DPDES", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_dpdes, SPR_NOACCESS, - &spr_read_dpdes, &spr_write_dpdes, - KVM_REG_PPC_DPDES, 0x00000000); -#endif -} - -static void gen_spr_power8_ic(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register_hv(env, SPR_IC, "IC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0); -#endif -} - -static void gen_spr_power8_book4(CPUPPCState *env) -{ - /* Add a number of P8 book4 registers */ -#if !defined(CONFIG_USER_ONLY) - spr_register_kvm(env, SPR_ACOP, "ACOP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_ACOP, 0); - spr_register_kvm(env, SPR_BOOKS_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pidr, - KVM_REG_PPC_PID, 0); - spr_register_kvm(env, SPR_WORT, "WORT", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_WORT, 0); -#endif -} - -static void gen_spr_power7_book4(CPUPPCState *env) -{ - /* Add a number of P7 book4 registers */ -#if !defined(CONFIG_USER_ONLY) - spr_register_kvm(env, SPR_ACOP, "ACOP", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_ACOP, 0); - spr_register_kvm(env, SPR_BOOKS_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_PID, 0); -#endif -} - -static void gen_spr_power8_rpr(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - spr_register_hv(env, SPR_RPR, "RPR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000103070F1F3F); -#endif -} - -static void gen_spr_power9_mmu(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - /* Partition Table Control */ - spr_register_kvm_hv(env, SPR_PTCR, "PTCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_ptcr, - KVM_REG_PPC_PTCR, 0x00000000); - /* Address Segment Descriptor Register */ - spr_register_hv(env, SPR_ASDR, "ASDR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x0000000000000000); -#endif -} - -static void init_proc_book3s_common(CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_tbl(env); - gen_spr_usprg3(env); - gen_spr_book3s_altivec(env); - gen_spr_book3s_pmu_sup(env); - gen_spr_book3s_pmu_user(env); - gen_spr_book3s_ctrl(env); -} - -static void init_proc_970(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_sdr1(env); - gen_spr_book3s_dbg(env); - - /* 970 Specific Registers */ - gen_spr_970_hid(env); - gen_spr_970_hior(env); - gen_low_BATs(env); - gen_spr_970_pmu_sup(env); - gen_spr_970_pmu_user(env); - gen_spr_970_lpar(env); - gen_spr_970_dbg(env); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_970(env); - ppc970_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(970)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 970"; - pcc->init_proc = init_proc_970; - pcc->check_pow = check_pow_970; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI); - pcc->mmu_model = POWERPC_MMU_64B; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; - pcc->hash64_opts = &ppc_hash64_opts_basic; -#endif - pcc->excp_model = POWERPC_EXCP_970; - pcc->bus_model = PPC_FLAGS_INPUT_970; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x10000; -} - -static void init_proc_power5plus(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_sdr1(env); - gen_spr_book3s_dbg(env); - - /* POWER5+ Specific Registers */ - gen_spr_970_hid(env); - gen_spr_970_hior(env); - gen_low_BATs(env); - gen_spr_970_pmu_sup(env); - gen_spr_970_pmu_user(env); - gen_spr_power5p_common(env); - gen_spr_power5p_lpar(env); - gen_spr_power5p_ear(env); - gen_spr_power5p_tb(env); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_970(env); - ppc970_irq_init(env_archcpu(env)); -} - -POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER5"; - dc->desc = "POWER5+"; - pcc->init_proc = init_proc_power5plus; - pcc->check_pow = check_pow_970; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_STFIWX | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | - PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_VR) | - (1ull << MSR_POW) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI); - pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | - LPCR_RMI | LPCR_HDICE; - pcc->mmu_model = POWERPC_MMU_2_03; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; - pcc->hash64_opts = &ppc_hash64_opts_basic; - pcc->lrg_decr_bits = 32; -#endif - pcc->excp_model = POWERPC_EXCP_970; - pcc->bus_model = PPC_FLAGS_INPUT_970; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x10000; -} - -static void init_proc_POWER7(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_sdr1(env); - gen_spr_book3s_dbg(env); - - /* POWER7 Specific Registers */ - gen_spr_book3s_ids(env); - gen_spr_rmor(env); - gen_spr_amr(env); - gen_spr_book3s_purr(env); - gen_spr_power5p_common(env); - gen_spr_power5p_lpar(env); - gen_spr_power5p_ear(env); - gen_spr_power5p_tb(env); - gen_spr_power6_common(env); - gen_spr_power6_dbg(env); - gen_spr_power7_book4(env); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_POWER7(env); - ppcPOWER7_irq_init(env_archcpu(env)); -} - -static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) -{ - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { - return true; - } - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { - return true; - } - return false; -} - -static bool cpu_has_work_POWER7(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - if (cs->halted) { - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { - return true; - } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { - return true; - } - return false; - } else { - return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - -POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER7"; - dc->desc = "POWER7"; - pcc->pvr_match = ppc_pvr_match_power7; - pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; - pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; - pcc->init_proc = init_proc_POWER7; - pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER7; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | - PPC2_PM_ISA206; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | - LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | - LPCR_MER | LPCR_TC | - LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; - pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; - pcc->mmu_model = POWERPC_MMU_2_06; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; - pcc->hash64_opts = &ppc_hash64_opts_POWER7; - pcc->lrg_decr_bits = 32; -#endif - pcc->excp_model = POWERPC_EXCP_POWER7; - pcc->bus_model = PPC_FLAGS_INPUT_POWER7; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x8000; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -} - -static void init_proc_POWER8(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_sdr1(env); - gen_spr_book3s_207_dbg(env); - - /* POWER8 Specific Registers */ - gen_spr_book3s_ids(env); - gen_spr_rmor(env); - gen_spr_amr(env); - gen_spr_iamr(env); - gen_spr_book3s_purr(env); - gen_spr_power5p_common(env); - gen_spr_power5p_lpar(env); - gen_spr_power5p_ear(env); - gen_spr_power5p_tb(env); - gen_spr_power6_common(env); - gen_spr_power6_dbg(env); - gen_spr_power8_tce_address_control(env); - gen_spr_power8_ids(env); - gen_spr_power8_ebb(env); - gen_spr_power8_fscr(env); - gen_spr_power8_pmu_sup(env); - gen_spr_power8_pmu_user(env); - gen_spr_power8_tm(env); - gen_spr_power8_pspb(env); - gen_spr_power8_dpdes(env); - gen_spr_vtb(env); - gen_spr_power8_ic(env); - gen_spr_power8_book4(env); - gen_spr_power8_rpr(env); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_POWER8(env); - ppcPOWER7_irq_init(env_archcpu(env)); -} - -static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) -{ - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { - return true; - } - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { - return true; - } - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { - return true; - } - return false; -} - -static bool cpu_has_work_POWER8(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - if (cs->halted) { - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { - return true; - } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { - return true; - } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { - return true; - } - return false; - } else { - return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - -POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER8"; - dc->desc = "POWER8"; - pcc->pvr_match = ppc_pvr_match_power8; - pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; - pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; - pcc->init_proc = init_proc_POWER8; - pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER8; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_PM_ISA206; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_TS0) | - (1ull << MSR_TS1) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | - LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | - LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | - LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | - LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; - pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; - pcc->mmu_model = POWERPC_MMU_2_07; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; - pcc->hash64_opts = &ppc_hash64_opts_POWER7; - pcc->lrg_decr_bits = 32; - pcc->n_host_threads = 8; -#endif - pcc->excp_model = POWERPC_EXCP_POWER8; - pcc->bus_model = PPC_FLAGS_INPUT_POWER7; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x8000; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -} - -#ifdef CONFIG_SOFTMMU -/* - * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings - * Encoded as array of int_32s in the form: - * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy - * x -> AP encoding - * y -> radix mode supported page size (encoded as a shift) - */ -static struct ppc_radix_page_info POWER9_radix_page_info = { - .count = 4, - .entries = { - 0x0000000c, /* 4K - enc: 0x0 */ - 0xa0000010, /* 64K - enc: 0x5 */ - 0x20000015, /* 2M - enc: 0x1 */ - 0x4000001e /* 1G - enc: 0x2 */ - } -}; -#endif /* CONFIG_SOFTMMU */ - -static void init_proc_POWER9(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_book3s_207_dbg(env); - - /* POWER8 Specific Registers */ - gen_spr_book3s_ids(env); - gen_spr_amr(env); - gen_spr_iamr(env); - gen_spr_book3s_purr(env); - gen_spr_power5p_common(env); - gen_spr_power5p_lpar(env); - gen_spr_power5p_ear(env); - gen_spr_power5p_tb(env); - gen_spr_power6_common(env); - gen_spr_power6_dbg(env); - gen_spr_power8_tce_address_control(env); - gen_spr_power8_ids(env); - gen_spr_power8_ebb(env); - gen_spr_power8_fscr(env); - gen_spr_power8_pmu_sup(env); - gen_spr_power8_pmu_user(env); - gen_spr_power8_tm(env); - gen_spr_power8_pspb(env); - gen_spr_power8_dpdes(env); - gen_spr_vtb(env); - gen_spr_power8_ic(env); - gen_spr_power8_book4(env); - gen_spr_power8_rpr(env); - gen_spr_power9_mmu(env); - - /* POWER9 Specific registers */ - spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_TIDR, 0); - - /* FIXME: Filter fields properly based on privilege level */ - spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_PSSCR, 0); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_POWER9(env); - ppcPOWER9_irq_init(env_archcpu(env)); -} - -static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) -{ - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { - return true; - } - return false; -} - -static bool cpu_has_work_POWER9(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - if (cs->halted) { - uint64_t psscr = env->spr[SPR_PSSCR]; - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - /* If EC is clear, just return true on any pending interrupt */ - if (!(psscr & PSSCR_EC)) { - return true; - } - /* External Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && - (env->spr[SPR_LPCR] & LPCR_EEE)) { - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (heic == 0 || !msr_hv || msr_pr) { - return true; - } - } - /* Decrementer Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && - (env->spr[SPR_LPCR] & LPCR_DEE)) { - return true; - } - /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | - 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { - return true; - } - /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_PDEE)) { - return true; - } - /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_HDEE)) { - return true; - } - /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && - (env->spr[SPR_LPCR] & LPCR_HVEE)) { - return true; - } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { - return true; - } - return false; - } else { - return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - -POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER9"; - dc->desc = "POWER9"; - pcc->pvr_match = ppc_pvr_match_power9; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; - pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | - PCR_COMPAT_2_05; - pcc->init_proc = init_proc_POWER9; - pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER9; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; - pcc->mmu_model = POWERPC_MMU_3_00; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; - /* segment page size remain the same */ - pcc->hash64_opts = &ppc_hash64_opts_POWER7; - pcc->radix_page_info = &POWER9_radix_page_info; - pcc->lrg_decr_bits = 56; - pcc->n_host_threads = 4; -#endif - pcc->excp_model = POWERPC_EXCP_POWER9; - pcc->bus_model = PPC_FLAGS_INPUT_POWER9; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x8000; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -} - -#ifdef CONFIG_SOFTMMU -/* - * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings - * Encoded as array of int_32s in the form: - * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy - * x -> AP encoding - * y -> radix mode supported page size (encoded as a shift) - */ -static struct ppc_radix_page_info POWER10_radix_page_info = { - .count = 4, - .entries = { - 0x0000000c, /* 4K - enc: 0x0 */ - 0xa0000010, /* 64K - enc: 0x5 */ - 0x20000015, /* 2M - enc: 0x1 */ - 0x4000001e /* 1G - enc: 0x2 */ - } -}; -#endif /* CONFIG_SOFTMMU */ - -static void init_proc_POWER10(CPUPPCState *env) -{ - /* Common Registers */ - init_proc_book3s_common(env); - gen_spr_book3s_207_dbg(env); - - /* POWER8 Specific Registers */ - gen_spr_book3s_ids(env); - gen_spr_amr(env); - gen_spr_iamr(env); - gen_spr_book3s_purr(env); - gen_spr_power5p_common(env); - gen_spr_power5p_lpar(env); - gen_spr_power5p_ear(env); - gen_spr_power6_common(env); - gen_spr_power6_dbg(env); - gen_spr_power8_tce_address_control(env); - gen_spr_power8_ids(env); - gen_spr_power8_ebb(env); - gen_spr_power8_fscr(env); - gen_spr_power8_pmu_sup(env); - gen_spr_power8_pmu_user(env); - gen_spr_power8_tm(env); - gen_spr_power8_pspb(env); - gen_spr_vtb(env); - gen_spr_power8_ic(env); - gen_spr_power8_book4(env); - gen_spr_power8_rpr(env); - gen_spr_power9_mmu(env); - - /* FIXME: Filter fields properly based on privilege level */ - spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_PSSCR, 0); - - /* env variables */ - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - init_excp_POWER10(env); - ppcPOWER9_irq_init(env_archcpu(env)); -} - -static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) -{ - if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { - return true; - } - return false; -} - -static bool cpu_has_work_POWER10(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - if (cs->halted) { - uint64_t psscr = env->spr[SPR_PSSCR]; - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - /* If EC is clear, just return true on any pending interrupt */ - if (!(psscr & PSSCR_EC)) { - return true; - } - /* External Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && - (env->spr[SPR_LPCR] & LPCR_EEE)) { - bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (heic == 0 || !msr_hv || msr_pr) { - return true; - } - } - /* Decrementer Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && - (env->spr[SPR_LPCR] & LPCR_DEE)) { - return true; - } - /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | - 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { - return true; - } - /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_PDEE)) { - return true; - } - /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && - (env->spr[SPR_LPCR] & LPCR_HDEE)) { - return true; - } - /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && - (env->spr[SPR_LPCR] & LPCR_HVEE)) { - return true; - } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { - return true; - } - return false; - } else { - return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - -POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - - dc->fw_name = "PowerPC,POWER10"; - dc->desc = "POWER10"; - pcc->pvr_match = ppc_pvr_match_power10; - pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | - PCR_COMPAT_3_00; - pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | - PCR_COMPAT_2_06 | PCR_COMPAT_2_05; - pcc->init_proc = init_proc_POWER10; - pcc->check_pow = check_pow_nocheck; - cc->has_work = cpu_has_work_POWER10; - pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; - pcc->msr_mask = (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; - pcc->mmu_model = POWERPC_MMU_3_00; -#if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; - /* segment page size remain the same */ - pcc->hash64_opts = &ppc_hash64_opts_POWER7; - pcc->radix_page_info = &POWER10_radix_page_info; - pcc->lrg_decr_bits = 56; -#endif - pcc->excp_model = POWERPC_EXCP_POWER9; - pcc->bus_model = PPC_FLAGS_INPUT_POWER9; - pcc->bfd_mach = bfd_mach_ppc64; - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM; - pcc->l1_dcache_size = 0x8000; - pcc->l1_icache_size = 0x8000; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -} - -#if !defined(CONFIG_USER_ONLY) -void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) -{ - CPUPPCState *env = &cpu->env; - - cpu->vhyp = vhyp; - - /* - * With a virtual hypervisor mode we never allow the CPU to go - * hypervisor mode itself - */ - env->msr_mask &= ~MSR_HVB; -} - -#endif /* !defined(CONFIG_USER_ONLY) */ - -#endif /* defined(TARGET_PPC64) */ - -/*****************************************************************************/ -/* Generic CPU instantiation routine */ -static void init_ppc_proc(PowerPCCPU *cpu) -{ - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - CPUPPCState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) - int i; - - env->irq_inputs = NULL; - /* Set all exception vectors to an invalid address */ - for (i = 0; i < POWERPC_EXCP_NB; i++) { - env->excp_vectors[i] = (target_ulong)(-1ULL); - } - env->ivor_mask = 0x00000000; - env->ivpr_mask = 0x00000000; - /* Default MMU definitions */ - env->nb_BATs = 0; - env->nb_tlb = 0; - env->nb_ways = 0; - env->tlb_type = TLB_NONE; -#endif - /* Register SPR common to all PowerPC implementations */ - gen_spr_generic(env); - spr_register(env, SPR_PVR, "PVR", - /* Linux permits userspace to read PVR */ -#if defined(CONFIG_LINUX_USER) - &spr_read_generic, -#else - SPR_NOACCESS, -#endif - SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - pcc->pvr); - /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ - if (pcc->svr != POWERPC_SVR_NONE) { - if (pcc->svr & POWERPC_SVR_E500) { - spr_register(env, SPR_E500_SVR, "SVR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - pcc->svr & ~POWERPC_SVR_E500); - } else { - spr_register(env, SPR_SVR, "SVR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - pcc->svr); - } - } - /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ - (*pcc->init_proc)(env); - -#if !defined(CONFIG_USER_ONLY) - ppc_gdb_gen_spr_xml(cpu); -#endif - - /* MSR bits & flags consistency checks */ - if (env->msr_mask & (1 << 25)) { - switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { - case POWERPC_FLAG_SPE: - case POWERPC_FLAG_VRE: - break; - default: - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); - exit(1); - } - } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); - exit(1); - } - if (env->msr_mask & (1 << 17)) { - switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { - case POWERPC_FLAG_TGPR: - case POWERPC_FLAG_CE: - break; - default: - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); - exit(1); - } - } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); - exit(1); - } - if (env->msr_mask & (1 << 10)) { - switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { - case POWERPC_FLAG_SE: - case POWERPC_FLAG_DWE: - case POWERPC_FLAG_UBLE: - break; - default: - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " - "POWERPC_FLAG_UBLE\n"); - exit(1); - } - } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | - POWERPC_FLAG_UBLE)) { - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " - "POWERPC_FLAG_UBLE\n"); - exit(1); - } - if (env->msr_mask & (1 << 9)) { - switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { - case POWERPC_FLAG_BE: - case POWERPC_FLAG_DE: - break; - default: - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); - exit(1); - } - } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); - exit(1); - } - if (env->msr_mask & (1 << 2)) { - switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { - case POWERPC_FLAG_PX: - case POWERPC_FLAG_PMM: - break; - default: - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); - exit(1); - } - } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { - fprintf(stderr, "PowerPC MSR definition inconsistency\n" - "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); - exit(1); - } - if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { - fprintf(stderr, "PowerPC flags inconsistency\n" - "Should define the time-base and decrementer clock source\n"); - exit(1); - } - /* Allocate TLBs buffer when needed */ -#if !defined(CONFIG_USER_ONLY) - if (env->nb_tlb != 0) { - int nb_tlb = env->nb_tlb; - if (env->id_tlbs != 0) { - nb_tlb *= 2; - } - switch (env->tlb_type) { - case TLB_6XX: - env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); - break; - case TLB_EMB: - env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); - break; - case TLB_MAS: - env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); - break; - } - /* Pre-compute some useful values */ - env->tlb_per_way = env->nb_tlb / env->nb_ways; - } - if (env->irq_inputs == NULL) { - warn_report("no internal IRQ controller registered." - " Attempt QEMU to crash very soon !"); - } -#endif - if (env->check_pow == NULL) { - warn_report("no power management check handler registered." - " Attempt QEMU to crash very soon !"); - } -} - -#if defined(PPC_DUMP_CPU) -static void dump_ppc_sprs(CPUPPCState *env) -{ - ppc_spr_t *spr; -#if !defined(CONFIG_USER_ONLY) - uint32_t sr, sw; -#endif - uint32_t ur, uw; - int i, j, n; - - printf("Special purpose registers:\n"); - for (i = 0; i < 32; i++) { - for (j = 0; j < 32; j++) { - n = (i << 5) | j; - spr = &env->spr_cb[n]; - uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; - ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; -#if !defined(CONFIG_USER_ONLY) - sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; - sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; - if (sw || sr || uw || ur) { - printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", - (i << 5) | j, (i << 5) | j, spr->name, - sw ? 'w' : '-', sr ? 'r' : '-', - uw ? 'w' : '-', ur ? 'r' : '-'); - } -#else - if (uw || ur) { - printf("SPR: %4d (%03x) %-8s u%c%c\n", - (i << 5) | j, (i << 5) | j, spr->name, - uw ? 'w' : '-', ur ? 'r' : '-'); - } -#endif - } - } - fflush(stdout); - fflush(stderr); -} -#endif - -/*****************************************************************************/ - -/* Opcode types */ -enum { - PPC_DIRECT = 0, /* Opcode routine */ - PPC_INDIRECT = 1, /* Indirect opcode table */ -}; - -#define PPC_OPCODE_MASK 0x3 - -static inline int is_indirect_opcode(void *handler) -{ - return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; -} - -static inline opc_handler_t **ind_table(void *handler) -{ - return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); -} - -/* Instruction table creation */ -/* Opcodes tables creation */ -static void fill_new_table(opc_handler_t **table, int len) -{ - int i; - - for (i = 0; i < len; i++) { - table[i] = &invalid_handler; - } -} - -static int create_new_table(opc_handler_t **table, unsigned char idx) -{ - opc_handler_t **tmp; - - tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); - fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); - table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); - - return 0; -} - -static int insert_in_table(opc_handler_t **table, unsigned char idx, - opc_handler_t *handler) -{ - if (table[idx] != &invalid_handler) { - return -1; - } - table[idx] = handler; - - return 0; -} - -static int register_direct_insn(opc_handler_t **ppc_opcodes, - unsigned char idx, opc_handler_t *handler) -{ - if (insert_in_table(ppc_opcodes, idx, handler) < 0) { - printf("*** ERROR: opcode %02x already assigned in main " - "opcode table\n", idx); -#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) - printf(" Registered handler '%s' - new handler '%s'\n", - ppc_opcodes[idx]->oname, handler->oname); -#endif - return -1; - } - - return 0; -} - -static int register_ind_in_table(opc_handler_t **table, - unsigned char idx1, unsigned char idx2, - opc_handler_t *handler) -{ - if (table[idx1] == &invalid_handler) { - if (create_new_table(table, idx1) < 0) { - printf("*** ERROR: unable to create indirect table " - "idx=%02x\n", idx1); - return -1; - } - } else { - if (!is_indirect_opcode(table[idx1])) { - printf("*** ERROR: idx %02x already assigned to a direct " - "opcode\n", idx1); -#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) - printf(" Registered handler '%s' - new handler '%s'\n", - ind_table(table[idx1])[idx2]->oname, handler->oname); -#endif - return -1; - } - } - if (handler != NULL && - insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { - printf("*** ERROR: opcode %02x already assigned in " - "opcode table %02x\n", idx2, idx1); -#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) - printf(" Registered handler '%s' - new handler '%s'\n", - ind_table(table[idx1])[idx2]->oname, handler->oname); -#endif - return -1; - } - - return 0; -} - -static int register_ind_insn(opc_handler_t **ppc_opcodes, - unsigned char idx1, unsigned char idx2, - opc_handler_t *handler) -{ - return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); -} - -static int register_dblind_insn(opc_handler_t **ppc_opcodes, - unsigned char idx1, unsigned char idx2, - unsigned char idx3, opc_handler_t *handler) -{ - if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { - printf("*** ERROR: unable to join indirect table idx " - "[%02x-%02x]\n", idx1, idx2); - return -1; - } - if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, - handler) < 0) { - printf("*** ERROR: unable to insert opcode " - "[%02x-%02x-%02x]\n", idx1, idx2, idx3); - return -1; - } - - return 0; -} - -static int register_trplind_insn(opc_handler_t **ppc_opcodes, - unsigned char idx1, unsigned char idx2, - unsigned char idx3, unsigned char idx4, - opc_handler_t *handler) -{ - opc_handler_t **table; - - if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { - printf("*** ERROR: unable to join indirect table idx " - "[%02x-%02x]\n", idx1, idx2); - return -1; - } - table = ind_table(ppc_opcodes[idx1]); - if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { - printf("*** ERROR: unable to join 2nd-level indirect table idx " - "[%02x-%02x-%02x]\n", idx1, idx2, idx3); - return -1; - } - table = ind_table(table[idx2]); - if (register_ind_in_table(table, idx3, idx4, handler) < 0) { - printf("*** ERROR: unable to insert opcode " - "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); - return -1; - } - return 0; -} -static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) -{ - if (insn->opc2 != 0xFF) { - if (insn->opc3 != 0xFF) { - if (insn->opc4 != 0xFF) { - if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, - insn->opc3, insn->opc4, - &insn->handler) < 0) { - return -1; - } - } else { - if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, - insn->opc3, &insn->handler) < 0) { - return -1; - } - } - } else { - if (register_ind_insn(ppc_opcodes, insn->opc1, - insn->opc2, &insn->handler) < 0) { - return -1; - } - } - } else { - if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { - return -1; - } - } - - return 0; -} - -static int test_opcode_table(opc_handler_t **table, int len) -{ - int i, count, tmp; - - for (i = 0, count = 0; i < len; i++) { - /* Consistency fixup */ - if (table[i] == NULL) { - table[i] = &invalid_handler; - } - if (table[i] != &invalid_handler) { - if (is_indirect_opcode(table[i])) { - tmp = test_opcode_table(ind_table(table[i]), - PPC_CPU_INDIRECT_OPCODES_LEN); - if (tmp == 0) { - free(table[i]); - table[i] = &invalid_handler; - } else { - count++; - } - } else { - count++; - } - } - } - - return count; -} - -static void fix_opcode_tables(opc_handler_t **ppc_opcodes) -{ - if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { - printf("*** WARNING: no opcode defined !\n"); - } -} - -/*****************************************************************************/ -static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) -{ - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - opcode_t *opc; - - fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); - for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { - if (((opc->handler.type & pcc->insns_flags) != 0) || - ((opc->handler.type2 & pcc->insns_flags2) != 0)) { - if (register_insn(cpu->opcodes, opc) < 0) { - error_setg(errp, "ERROR initializing PowerPC instruction " - "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, - opc->opc3); - return; - } - } - } - fix_opcode_tables(cpu->opcodes); - fflush(stdout); - fflush(stderr); -} - -#if defined(PPC_DUMP_CPU) -static void dump_ppc_insns(CPUPPCState *env) -{ - opc_handler_t **table, *handler; - const char *p, *q; - uint8_t opc1, opc2, opc3, opc4; - - printf("Instructions set:\n"); - /* opc1 is 6 bits long */ - for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { - table = env->opcodes; - handler = table[opc1]; - if (is_indirect_opcode(handler)) { - /* opc2 is 5 bits long */ - for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { - table = env->opcodes; - handler = env->opcodes[opc1]; - table = ind_table(handler); - handler = table[opc2]; - if (is_indirect_opcode(handler)) { - table = ind_table(handler); - /* opc3 is 5 bits long */ - for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; - opc3++) { - handler = table[opc3]; - if (is_indirect_opcode(handler)) { - table = ind_table(handler); - /* opc4 is 5 bits long */ - for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; - opc4++) { - handler = table[opc4]; - if (handler->handler != &gen_invalid) { - printf("INSN: %02x %02x %02x %02x -- " - "(%02d %04d %02d) : %s\n", - opc1, opc2, opc3, opc4, - opc1, (opc3 << 5) | opc2, opc4, - handler->oname); - } - } - } else { - if (handler->handler != &gen_invalid) { - /* Special hack to properly dump SPE insns */ - p = strchr(handler->oname, '_'); - if (p == NULL) { - printf("INSN: %02x %02x %02x (%02d %04d) : " - "%s\n", - opc1, opc2, opc3, opc1, - (opc3 << 5) | opc2, - handler->oname); - } else { - q = "speundef"; - if ((p - handler->oname) != strlen(q) - || (memcmp(handler->oname, q, strlen(q)) - != 0)) { - /* First instruction */ - printf("INSN: %02x %02x %02x" - "(%02d %04d) : %.*s\n", - opc1, opc2 << 1, opc3, opc1, - (opc3 << 6) | (opc2 << 1), - (int)(p - handler->oname), - handler->oname); - } - if (strcmp(p + 1, q) != 0) { - /* Second instruction */ - printf("INSN: %02x %02x %02x " - "(%02d %04d) : %s\n", opc1, - (opc2 << 1) | 1, opc3, opc1, - (opc3 << 6) | (opc2 << 1) | 1, - p + 1); - } - } - } - } - } - } else { - if (handler->handler != &gen_invalid) { - printf("INSN: %02x %02x -- (%02d %04d) : %s\n", - opc1, opc2, opc1, opc2, handler->oname); - } - } - } - } else { - if (handler->handler != &gen_invalid) { - printf("INSN: %02x -- -- (%02d ----) : %s\n", - opc1, opc1, handler->oname); - } - } - } -} -#endif - -static bool avr_need_swap(CPUPPCState *env) -{ -#ifdef HOST_WORDS_BIGENDIAN - return msr_le; -#else - return !msr_le; -#endif -} - -#if !defined(CONFIG_USER_ONLY) -static int gdb_find_spr_idx(CPUPPCState *env, int n) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { - ppc_spr_t *spr = &env->spr_cb[i]; - - if (spr->name && spr->gdb_id == n) { - return i; - } - } - return -1; -} - -static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) -{ - int reg; - int len; - - reg = gdb_find_spr_idx(env, n); - if (reg < 0) { - return 0; - } - - len = TARGET_LONG_SIZE; - gdb_get_regl(buf, env->spr[reg]); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); - return len; -} - -static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - int reg; - int len; - - reg = gdb_find_spr_idx(env, n); - if (reg < 0) { - return 0; - } - - len = TARGET_LONG_SIZE; - ppc_maybe_bswap_register(env, mem_buf, len); - env->spr[reg] = ldn_p(mem_buf, len); - - return len; -} -#endif - -static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) -{ - uint8_t *mem_buf; - if (n < 32) { - gdb_get_float64(buf, *cpu_fpr_ptr(env, n)); - mem_buf = gdb_get_reg_ptr(buf, 8); - ppc_maybe_bswap_register(env, mem_buf, 8); - return 8; - } - if (n == 32) { - gdb_get_reg32(buf, env->fpscr); - mem_buf = gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; - } - return 0; -} - -static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - ppc_maybe_bswap_register(env, mem_buf, 8); - *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf); - return 8; - } - if (n == 32) { - ppc_maybe_bswap_register(env, mem_buf, 4); - helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff); - return 4; - } - return 0; -} - -static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) -{ - uint8_t *mem_buf; - - if (n < 32) { - ppc_avr_t *avr = cpu_avr_ptr(env, n); - if (!avr_need_swap(env)) { - gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); - } else { - gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); - } - mem_buf = gdb_get_reg_ptr(buf, 16); - ppc_maybe_bswap_register(env, mem_buf, 8); - ppc_maybe_bswap_register(env, mem_buf + 8, 8); - return 16; - } - if (n == 32) { - gdb_get_reg32(buf, helper_mfvscr(env)); - mem_buf = gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; - } - if (n == 33) { - gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); - mem_buf = gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; - } - return 0; -} - -static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - ppc_avr_t *avr = cpu_avr_ptr(env, n); - ppc_maybe_bswap_register(env, mem_buf, 8); - ppc_maybe_bswap_register(env, mem_buf + 8, 8); - if (!avr_need_swap(env)) { - avr->u64[0] = ldq_p(mem_buf); - avr->u64[1] = ldq_p(mem_buf + 8); - } else { - avr->u64[1] = ldq_p(mem_buf); - avr->u64[0] = ldq_p(mem_buf + 8); - } - return 16; - } - if (n == 32) { - ppc_maybe_bswap_register(env, mem_buf, 4); - helper_mtvscr(env, ldl_p(mem_buf)); - return 4; - } - if (n == 33) { - ppc_maybe_bswap_register(env, mem_buf, 4); - env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); - return 4; - } - return 0; -} - -static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) -{ - if (n < 32) { -#if defined(TARGET_PPC64) - gdb_get_reg32(buf, env->gpr[n] >> 32); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); -#else - gdb_get_reg32(buf, env->gprh[n]); -#endif - return 4; - } - if (n == 32) { - gdb_get_reg64(buf, env->spe_acc); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); - return 8; - } - if (n == 33) { - gdb_get_reg32(buf, env->spe_fscr); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); - return 4; - } - return 0; -} - -static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { -#if defined(TARGET_PPC64) - target_ulong lo = (uint32_t)env->gpr[n]; - target_ulong hi; - - ppc_maybe_bswap_register(env, mem_buf, 4); - - hi = (target_ulong)ldl_p(mem_buf) << 32; - env->gpr[n] = lo | hi; -#else - env->gprh[n] = ldl_p(mem_buf); -#endif - return 4; - } - if (n == 32) { - ppc_maybe_bswap_register(env, mem_buf, 8); - env->spe_acc = ldq_p(mem_buf); - return 8; - } - if (n == 33) { - ppc_maybe_bswap_register(env, mem_buf, 4); - env->spe_fscr = ldl_p(mem_buf); - return 4; - } - return 0; -} - -static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) -{ - if (n < 32) { - gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); - return 8; - } - return 0; -} - -static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) -{ - if (n < 32) { - ppc_maybe_bswap_register(env, mem_buf, 8); - *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); - return 8; - } - return 0; -} - -static int ppc_fixup_cpu(PowerPCCPU *cpu) -{ - CPUPPCState *env = &cpu->env; - - /* - * TCG doesn't (yet) emulate some groups of instructions that are - * implemented on some otherwise supported CPUs (e.g. VSX and - * decimal floating point instructions on POWER7). We remove - * unsupported instruction groups from the cpu state's instruction - * masks and hope the guest can cope. For at least the pseries - * machine, the unavailability of these instructions can be - * advertised to the guest via the device tree. - */ - if ((env->insns_flags & ~PPC_TCG_INSNS) - || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { - warn_report("Disabling some instructions which are not " - "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", - env->insns_flags & ~PPC_TCG_INSNS, - env->insns_flags2 & ~PPC_TCG_INSNS2); - } - env->insns_flags &= PPC_TCG_INSNS; - env->insns_flags2 &= PPC_TCG_INSNS2; - return 0; -} - -static void ppc_cpu_realize(DeviceState *dev, Error **errp) -{ - CPUState *cs = CPU(dev); - PowerPCCPU *cpu = POWERPC_CPU(dev); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - Error *local_err = NULL; - - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { - cpu->vcpu_id = cs->cpu_index; - } - - if (tcg_enabled()) { - if (ppc_fixup_cpu(cpu) != 0) { - error_setg(errp, "Unable to emulate selected CPU with TCG"); - goto unrealize; - } - } - - create_ppc_opcodes(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - goto unrealize; - } - init_ppc_proc(cpu); - - if (pcc->insns_flags & PPC_FLOAT) { - gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, - 33, "power-fpu.xml", 0); - } - if (pcc->insns_flags & PPC_ALTIVEC) { - gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, - 34, "power-altivec.xml", 0); - } - if (pcc->insns_flags & PPC_SPE) { - gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, - 34, "power-spe.xml", 0); - } - if (pcc->insns_flags2 & PPC2_VSX) { - gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, - 32, "power-vsx.xml", 0); - } -#ifndef CONFIG_USER_ONLY - gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_num_sprs, "power-spr.xml", 0); -#endif - qemu_init_vcpu(cs); - - pcc->parent_realize(dev, errp); - -#if defined(PPC_DUMP_CPU) - { - CPUPPCState *env = &cpu->env; - const char *mmu_model, *excp_model, *bus_model; - switch (env->mmu_model) { - case POWERPC_MMU_32B: - mmu_model = "PowerPC 32"; - break; - case POWERPC_MMU_SOFT_6xx: - mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_74xx: - mmu_model = "PowerPC 74xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_4xx: - mmu_model = "PowerPC 4xx with software driven TLBs"; - break; - case POWERPC_MMU_SOFT_4xx_Z: - mmu_model = "PowerPC 4xx with software driven TLBs " - "and zones protections"; - break; - case POWERPC_MMU_REAL: - mmu_model = "PowerPC real mode only"; - break; - case POWERPC_MMU_MPC8xx: - mmu_model = "PowerPC MPC8xx"; - break; - case POWERPC_MMU_BOOKE: - mmu_model = "PowerPC BookE"; - break; - case POWERPC_MMU_BOOKE206: - mmu_model = "PowerPC BookE 2.06"; - break; - case POWERPC_MMU_601: - mmu_model = "PowerPC 601"; - break; -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - mmu_model = "PowerPC 64"; - break; -#endif - default: - mmu_model = "Unknown or invalid"; - break; - } - switch (env->excp_model) { - case POWERPC_EXCP_STD: - excp_model = "PowerPC"; - break; - case POWERPC_EXCP_40x: - excp_model = "PowerPC 40x"; - break; - case POWERPC_EXCP_601: - excp_model = "PowerPC 601"; - break; - case POWERPC_EXCP_602: - excp_model = "PowerPC 602"; - break; - case POWERPC_EXCP_603: - excp_model = "PowerPC 603"; - break; - case POWERPC_EXCP_603E: - excp_model = "PowerPC 603e"; - break; - case POWERPC_EXCP_604: - excp_model = "PowerPC 604"; - break; - case POWERPC_EXCP_7x0: - excp_model = "PowerPC 740/750"; - break; - case POWERPC_EXCP_7x5: - excp_model = "PowerPC 745/755"; - break; - case POWERPC_EXCP_74xx: - excp_model = "PowerPC 74xx"; - break; - case POWERPC_EXCP_BOOKE: - excp_model = "PowerPC BookE"; - break; -#if defined(TARGET_PPC64) - case POWERPC_EXCP_970: - excp_model = "PowerPC 970"; - break; -#endif - default: - excp_model = "Unknown or invalid"; - break; - } - switch (env->bus_model) { - case PPC_FLAGS_INPUT_6xx: - bus_model = "PowerPC 6xx"; - break; - case PPC_FLAGS_INPUT_BookE: - bus_model = "PowerPC BookE"; - break; - case PPC_FLAGS_INPUT_405: - bus_model = "PowerPC 405"; - break; - case PPC_FLAGS_INPUT_401: - bus_model = "PowerPC 401/403"; - break; - case PPC_FLAGS_INPUT_RCPU: - bus_model = "RCPU / MPC8xx"; - break; -#if defined(TARGET_PPC64) - case PPC_FLAGS_INPUT_970: - bus_model = "PowerPC 970"; - break; -#endif - default: - bus_model = "Unknown or invalid"; - break; - } - printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" - " MMU model : %s\n", - object_class_get_name(OBJECT_CLASS(pcc)), - pcc->pvr, pcc->msr_mask, mmu_model); -#if !defined(CONFIG_USER_ONLY) - if (env->tlb.tlb6) { - printf(" %d %s TLB in %d ways\n", - env->nb_tlb, env->id_tlbs ? "splitted" : "merged", - env->nb_ways); - } -#endif - printf(" Exceptions model : %s\n" - " Bus model : %s\n", - excp_model, bus_model); - printf(" MSR features :\n"); - if (env->flags & POWERPC_FLAG_SPE) { - printf(" signal processing engine enable" - "\n"); - } else if (env->flags & POWERPC_FLAG_VRE) { - printf(" vector processor enable\n"); - } - if (env->flags & POWERPC_FLAG_TGPR) { - printf(" temporary GPRs\n"); - } else if (env->flags & POWERPC_FLAG_CE) { - printf(" critical input enable\n"); - } - if (env->flags & POWERPC_FLAG_SE) { - printf(" single-step trace mode\n"); - } else if (env->flags & POWERPC_FLAG_DWE) { - printf(" debug wait enable\n"); - } else if (env->flags & POWERPC_FLAG_UBLE) { - printf(" user BTB lock enable\n"); - } - if (env->flags & POWERPC_FLAG_BE) { - printf(" branch-step trace mode\n"); - } else if (env->flags & POWERPC_FLAG_DE) { - printf(" debug interrupt enable\n"); - } - if (env->flags & POWERPC_FLAG_PX) { - printf(" inclusive protection\n"); - } else if (env->flags & POWERPC_FLAG_PMM) { - printf(" performance monitor mark\n"); - } - if (env->flags == POWERPC_FLAG_NONE) { - printf(" none\n"); - } - printf(" Time-base/decrementer clock source: %s\n", - env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); - dump_ppc_insns(env); - dump_ppc_sprs(env); - fflush(stdout); - } -#endif - return; - -unrealize: - cpu_exec_unrealizefn(cs); -} - -static void ppc_cpu_unrealize(DeviceState *dev) -{ - PowerPCCPU *cpu = POWERPC_CPU(dev); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - opc_handler_t **table, **table_2; - int i, j, k; - - pcc->parent_unrealize(dev); - - for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { - if (cpu->opcodes[i] == &invalid_handler) { - continue; - } - if (is_indirect_opcode(cpu->opcodes[i])) { - table = ind_table(cpu->opcodes[i]); - for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { - if (table[j] == &invalid_handler) { - continue; - } - if (is_indirect_opcode(table[j])) { - table_2 = ind_table(table[j]); - for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { - if (table_2[k] != &invalid_handler && - is_indirect_opcode(table_2[k])) { - g_free((opc_handler_t *)((uintptr_t)table_2[k] & - ~PPC_INDIRECT)); - } - } - g_free((opc_handler_t *)((uintptr_t)table[j] & - ~PPC_INDIRECT)); - } - } - g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & - ~PPC_INDIRECT)); - } - } -} - -static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) -{ - ObjectClass *oc = (ObjectClass *)a; - uint32_t pvr = *(uint32_t *)b; - PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; - - /* -cpu host does a PVR lookup during construction */ - if (unlikely(strcmp(object_class_get_name(oc), - TYPE_HOST_POWERPC_CPU) == 0)) { - return -1; - } - - return pcc->pvr == pvr ? 0 : -1; -} - -PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) -{ - GSList *list, *item; - PowerPCCPUClass *pcc = NULL; - - list = object_class_get_list(TYPE_POWERPC_CPU, false); - item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); - if (item != NULL) { - pcc = POWERPC_CPU_CLASS(item->data); - } - g_slist_free(list); - - return pcc; -} - -static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) -{ - ObjectClass *oc = (ObjectClass *)a; - uint32_t pvr = *(uint32_t *)b; - PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; - - /* -cpu host does a PVR lookup during construction */ - if (unlikely(strcmp(object_class_get_name(oc), - TYPE_HOST_POWERPC_CPU) == 0)) { - return -1; - } - - if (pcc->pvr_match(pcc, pvr)) { - return 0; - } - - return -1; -} - -PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) -{ - GSList *list, *item; - PowerPCCPUClass *pcc = NULL; - - list = object_class_get_list(TYPE_POWERPC_CPU, true); - item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); - if (item != NULL) { - pcc = POWERPC_CPU_CLASS(item->data); - } - g_slist_free(list); - - return pcc; -} - -static const char *ppc_cpu_lookup_alias(const char *alias) -{ - int ai; - - for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { - if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { - return ppc_cpu_aliases[ai].model; - } - } - - return NULL; -} - -static ObjectClass *ppc_cpu_class_by_name(const char *name) -{ - char *cpu_model, *typename; - ObjectClass *oc; - const char *p; - unsigned long pvr; - - /* - * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: - * 0x prefix if present) - */ - if (!qemu_strtoul(name, &p, 16, &pvr)) { - int len = p - name; - len = (len == 10) && (name[1] == 'x') ? len - 2 : len; - if ((len == 8) && (*p == '\0')) { - return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); - } - } - - cpu_model = g_ascii_strdown(name, -1); - p = ppc_cpu_lookup_alias(cpu_model); - if (p) { - g_free(cpu_model); - cpu_model = g_strdup(p); - } - - typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); - oc = object_class_by_name(typename); - g_free(typename); - g_free(cpu_model); - - return oc; -} - -static void ppc_cpu_parse_featurestr(const char *type, char *features, - Error **errp) -{ - Object *machine = qdev_get_machine(); - const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type)); - - if (!features) { - return; - } - - if (object_property_find(machine, "max-cpu-compat", NULL)) { - int i; - char **inpieces; - char *s = features; - Error *local_err = NULL; - char *compat_str = NULL; - - /* - * Backwards compatibility hack: - * - * CPUs had a "compat=" property which didn't make sense for - * anything except pseries. It was replaced by "max-cpu-compat" - * machine option. This supports old command lines like - * -cpu POWER8,compat=power7 - * By stripping the compat option and applying it to the machine - * before passing it on to the cpu level parser. - */ - inpieces = g_strsplit(features, ",", 0); - *s = '\0'; - for (i = 0; inpieces[i]; i++) { - if (g_str_has_prefix(inpieces[i], "compat=")) { - warn_report_once("CPU 'compat' property is deprecated; " - "use max-cpu-compat machine property instead"); - compat_str = inpieces[i]; - continue; - } - if ((i != 0) && (s != features)) { - s = g_stpcpy(s, ","); - } - s = g_stpcpy(s, inpieces[i]); - } - - if (compat_str) { - char *v = compat_str + strlen("compat="); - object_property_set_str(machine, "max-cpu-compat", v, &local_err); - } - g_strfreev(inpieces); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } - - /* do property processing with generic handler */ - pcc->parent_parse_features(type, features, errp); -} - -PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) -{ - ObjectClass *oc = OBJECT_CLASS(pcc); - - while (oc && !object_class_is_abstract(oc)) { - oc = object_class_get_parent(oc); - } - assert(oc); - - return POWERPC_CPU_CLASS(oc); -} - -/* Sort by PVR, ordering special case "host" last. */ -static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *oc_a = (ObjectClass *)a; - ObjectClass *oc_b = (ObjectClass *)b; - PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); - PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); - const char *name_a = object_class_get_name(oc_a); - const char *name_b = object_class_get_name(oc_b); - - if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { - return 1; - } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { - return -1; - } else { - /* Avoid an integer overflow during subtraction */ - if (pcc_a->pvr < pcc_b->pvr) { - return -1; - } else if (pcc_a->pvr > pcc_b->pvr) { - return 1; - } else { - return 0; - } - } -} - -static void ppc_cpu_list_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); - const char *typename = object_class_get_name(oc); - char *name; - int i; - - if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { - return; - } - - name = g_strndup(typename, - strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); - qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); - for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { - PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; - ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); - - if (alias_oc != oc) { - continue; - } - /* - * If running with KVM, we might update the family alias later, so - * avoid printing the wrong alias here and use "preferred" instead - */ - if (strcmp(alias->alias, family->desc) == 0) { - qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", - alias->alias, family->desc); - } else { - qemu_printf("PowerPC %-16s (alias for %s)\n", - alias->alias, name); - } - } - g_free(name); -} - -void ppc_cpu_list(void) -{ - GSList *list; - - list = object_class_get_list(TYPE_POWERPC_CPU, false); - list = g_slist_sort(list, ppc_cpu_list_compare); - g_slist_foreach(list, ppc_cpu_list_entry, NULL); - g_slist_free(list); - -#ifdef CONFIG_KVM - qemu_printf("\n"); - qemu_printf("PowerPC %-16s\n", "host"); -#endif -} - -static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - CpuDefinitionInfoList **first = user_data; - const char *typename; - CpuDefinitionInfoList *entry; - CpuDefinitionInfo *info; - - typename = object_class_get_name(oc); - info = g_malloc0(sizeof(*info)); - info->name = g_strndup(typename, - strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); - - entry = g_malloc0(sizeof(*entry)); - entry->value = info; - entry->next = *first; - *first = entry; -} - -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) -{ - CpuDefinitionInfoList *cpu_list = NULL; - GSList *list; - int i; - - list = object_class_get_list(TYPE_POWERPC_CPU, false); - g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); - g_slist_free(list); - - for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { - PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; - ObjectClass *oc; - CpuDefinitionInfoList *entry; - CpuDefinitionInfo *info; - - oc = ppc_cpu_class_by_name(alias->model); - if (oc == NULL) { - continue; - } - - info = g_malloc0(sizeof(*info)); - info->name = g_strdup(alias->alias); - info->q_typename = g_strdup(object_class_get_name(oc)); - - entry = g_malloc0(sizeof(*entry)); - entry->value = info; - entry->next = cpu_list; - cpu_list = entry; - } - - return cpu_list; -} - -static void ppc_cpu_set_pc(CPUState *cs, vaddr value) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - - cpu->env.nip = value; -} - -static bool ppc_cpu_has_work(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); -} - -static void ppc_cpu_reset(DeviceState *dev) -{ - CPUState *s = CPU(dev); - PowerPCCPU *cpu = POWERPC_CPU(s); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - CPUPPCState *env = &cpu->env; - target_ulong msr; - int i; - - pcc->parent_reset(dev); - - msr = (target_ulong)0; - msr |= (target_ulong)MSR_HVB; - msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ - msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ - msr |= (target_ulong)1 << MSR_EP; -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr |= (target_ulong)1 << MSR_SE; - msr |= (target_ulong)1 << MSR_BE; -#endif -#if defined(CONFIG_USER_ONLY) - msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ - msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ - msr |= (target_ulong)1 << MSR_FE1; - msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ - msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ - msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ - msr |= (target_ulong)1 << MSR_PR; -#if defined(TARGET_PPC64) - msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ -#endif -#if !defined(TARGET_WORDS_BIGENDIAN) - msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ - if (!((env->msr_mask >> MSR_LE) & 1)) { - fprintf(stderr, "Selected CPU does not support little-endian.\n"); - exit(1); - } -#endif -#endif - -#if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { - msr |= (1ULL << MSR_SF); - } -#endif - - hreg_store_msr(env, msr, 1); - -#if !defined(CONFIG_USER_ONLY) - env->nip = env->hreset_vector | env->excp_prefix; - if (env->mmu_model != POWERPC_MMU_REAL) { - ppc_tlb_invalidate_all(env); - } -#endif - - hreg_compute_hflags(env); - env->reserve_addr = (target_ulong)-1ULL; - /* Be sure no exception or interrupt is pending */ - env->pending_interrupts = 0; - s->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; - ppc_irq_reset(cpu); - - /* tininess for underflow is detected before rounding */ - set_float_detect_tininess(float_tininess_before_rounding, - &env->fp_status); - - for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { - ppc_spr_t *spr = &env->spr_cb[i]; - - if (!spr->name) { - continue; - } - env->spr[i] = spr->default_value; - } -} - -#ifndef CONFIG_USER_ONLY -static bool ppc_cpu_is_big_endian(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - cpu_synchronize_state(cs); - - return !msr_le; -} - -static void ppc_cpu_exec_enter(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - - if (cpu->vhyp) { - PPCVirtualHypervisorClass *vhc = - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); - vhc->cpu_exec_enter(cpu->vhyp, cpu); - } -} - -static void ppc_cpu_exec_exit(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - - if (cpu->vhyp) { - PPCVirtualHypervisorClass *vhc = - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); - vhc->cpu_exec_exit(cpu->vhyp, cpu); - } -} -#endif - -static void ppc_cpu_instance_init(Object *obj) -{ - PowerPCCPU *cpu = POWERPC_CPU(obj); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); - CPUPPCState *env = &cpu->env; - - cpu_set_cpustate_pointers(cpu); - cpu->vcpu_id = UNASSIGNED_CPU_INDEX; - - env->msr_mask = pcc->msr_mask; - env->mmu_model = pcc->mmu_model; - env->excp_model = pcc->excp_model; - env->bus_model = pcc->bus_model; - env->insns_flags = pcc->insns_flags; - env->insns_flags2 = pcc->insns_flags2; - env->flags = pcc->flags; - env->bfd_mach = pcc->bfd_mach; - env->check_pow = pcc->check_pow; - - /* - * Mark HV mode as supported if the CPU has an MSR_HV bit in the - * msr_mask. The mask can later be cleared by PAPR mode but the hv - * mode support will remain, thus enforcing that we cannot use - * priv. instructions in guest in PAPR mode. For 970 we currently - * simply don't set HV in msr_mask thus simulating an "Apple mode" - * 970. If we ever want to support 970 HV mode, we'll have to add - * a processor attribute of some sort. - */ -#if !defined(CONFIG_USER_ONLY) - env->has_hv_mode = !!(env->msr_mask & MSR_HVB); -#endif - - ppc_hash64_init(cpu); -} - -static void ppc_cpu_instance_finalize(Object *obj) -{ - PowerPCCPU *cpu = POWERPC_CPU(obj); - - ppc_hash64_finalize(cpu); -} - -static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) -{ - return pcc->pvr == pvr; -} - -static gchar *ppc_gdb_arch_name(CPUState *cs) -{ -#if defined(TARGET_PPC64) - return g_strdup("powerpc:common64"); -#else - return g_strdup("powerpc:common"); -#endif -} - -static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - - if ((env->hflags >> MSR_LE) & 1) { - info->endian = BFD_ENDIAN_LITTLE; - } - info->mach = env->bfd_mach; - if (!env->bfd_mach) { -#ifdef TARGET_PPC64 - info->mach = bfd_mach_ppc64; -#else - info->mach = bfd_mach_ppc; -#endif - } - info->disassembler_options = (char *)"any"; - info->print_insn = print_insn_ppc; - - info->cap_arch = CS_ARCH_PPC; -#ifdef TARGET_PPC64 - info->cap_mode = CS_MODE_64; -#endif -} - -static Property ppc_cpu_properties[] = { - DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), - DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, - false), - DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, - false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void ppc_cpu_class_init(ObjectClass *oc, void *data) -{ - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - CPUClass *cc = CPU_CLASS(oc); - DeviceClass *dc = DEVICE_CLASS(oc); - - device_class_set_parent_realize(dc, ppc_cpu_realize, - &pcc->parent_realize); - device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, - &pcc->parent_unrealize); - pcc->pvr_match = ppc_pvr_match_default; - pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; - device_class_set_props(dc, ppc_cpu_properties); - - device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); - - cc->class_by_name = ppc_cpu_class_by_name; - pcc->parent_parse_features = cc->parse_features; - cc->parse_features = ppc_cpu_parse_featurestr; - cc->has_work = ppc_cpu_has_work; - cc->do_interrupt = ppc_cpu_do_interrupt; - cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; - cc->dump_state = ppc_cpu_dump_state; - cc->dump_statistics = ppc_cpu_dump_statistics; - cc->set_pc = ppc_cpu_set_pc; - cc->gdb_read_register = ppc_cpu_gdb_read_register; - cc->gdb_write_register = ppc_cpu_gdb_write_register; - cc->do_unaligned_access = ppc_cpu_do_unaligned_access; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; - cc->vmsd = &vmstate_ppc_cpu; -#endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note = ppc64_cpu_write_elf64_note; - cc->write_elf32_note = ppc32_cpu_write_elf32_note; -#endif - - cc->gdb_num_core_regs = 71; -#ifndef CONFIG_USER_ONLY - cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; -#endif -#ifdef USE_APPLE_GDB - cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; - cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; - cc->gdb_num_core_regs = 71 + 32; -#endif - - cc->gdb_arch_name = ppc_gdb_arch_name; -#if defined(TARGET_PPC64) - cc->gdb_core_xml_file = "power64-core.xml"; -#else - cc->gdb_core_xml_file = "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian = ppc_cpu_is_big_endian; -#endif -#ifdef CONFIG_TCG - cc->tcg_initialize = ppc_translate_init; - cc->tlb_fill = ppc_cpu_tlb_fill; -#endif -#ifndef CONFIG_USER_ONLY - cc->cpu_exec_enter = ppc_cpu_exec_enter; - cc->cpu_exec_exit = ppc_cpu_exec_exit; -#endif - - cc->disas_set_info = ppc_disas_set_info; - - dc->fw_name = "PowerPC,UNKNOWN"; -} - -static const TypeInfo ppc_cpu_type_info = { - .name = TYPE_POWERPC_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(PowerPCCPU), - .instance_init = ppc_cpu_instance_init, - .instance_finalize = ppc_cpu_instance_finalize, - .abstract = true, - .class_size = sizeof(PowerPCCPUClass), - .class_init = ppc_cpu_class_init, -}; - -#ifndef CONFIG_USER_ONLY -static const TypeInfo ppc_vhyp_type_info = { - .name = TYPE_PPC_VIRTUAL_HYPERVISOR, - .parent = TYPE_INTERFACE, - .class_size = sizeof(PPCVirtualHypervisorClass), -}; -#endif - -static void ppc_cpu_register_types(void) -{ - type_register_static(&ppc_cpu_type_info); -#ifndef CONFIG_USER_ONLY - type_register_static(&ppc_vhyp_type_info); -#endif -} - -type_init(ppc_cpu_register_types) diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index ff38df6219..1cd4c58005 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -14,15 +14,15 @@ decode16-y = $(SRC_PATH)/target/riscv/insn16.decode decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode -target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) +target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ $(decode32-y), "GEN", $(TARGET_DIR)$@) -target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) +target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) -target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ - target/riscv/decode_insn16.inc.c +target/riscv/translate.o: target/riscv/decode_insn32.c.inc \ + target/riscv/decode_insn16.c.inc diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc new file mode 100644 index 0000000000..2a61a853bf --- /dev/null +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -0,0 +1,97 @@ +/* + * RISC-V translation routines for the RISC-V privileged instructions. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_ecall(DisasContext *ctx, arg_ecall *a) +{ + /* always generates U-level ECALL, fixed in do_interrupt handler */ + generate_exception(ctx, RISCV_EXCP_U_ECALL); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) +{ + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +static bool trans_uret(DisasContext *ctx, arg_uret *a) +{ + return false; +} + +static bool trans_sret(DisasContext *ctx, arg_sret *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + + if (has_ext(ctx, RVS)) { + gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + } else { + return false; + } + return true; +#else + return false; +#endif +} + +static bool trans_mret(DisasContext *ctx, arg_mret *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +#else + return false; +#endif +} + +static bool trans_wfi(DisasContext *ctx, arg_wfi *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_helper_wfi(cpu_env); + return true; +#else + return false; +#endif +} + +static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) +{ + return false; +} diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c deleted file mode 100644 index 2a61a853bf..0000000000 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * RISC-V translation routines for the RISC-V privileged instructions. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static bool trans_ecall(DisasContext *ctx, arg_ecall *a) -{ - /* always generates U-level ECALL, fixed in do_interrupt handler */ - generate_exception(ctx, RISCV_EXCP_U_ECALL); - exit_tb(ctx); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - return true; -} - -static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) -{ - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); - exit_tb(ctx); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - return true; -} - -static bool trans_uret(DisasContext *ctx, arg_uret *a) -{ - return false; -} - -static bool trans_sret(DisasContext *ctx, arg_sret *a) -{ -#ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); - exit_tb(ctx); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - } else { - return false; - } - return true; -#else - return false; -#endif -} - -static bool trans_mret(DisasContext *ctx, arg_mret *a) -{ -#ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); - exit_tb(ctx); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - return true; -#else - return false; -#endif -} - -static bool trans_wfi(DisasContext *ctx, arg_wfi *a) -{ -#ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - gen_helper_wfi(cpu_env); - return true; -#else - return false; -#endif -} - -static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) -{ -#ifndef CONFIG_USER_ONLY - gen_helper_tlb_flush(cpu_env); - return true; -#endif - return false; -} - -static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) -{ - return false; -} diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc new file mode 100644 index 0000000000..be8a9f06dd --- /dev/null +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -0,0 +1,224 @@ +/* + * RISC-V translation routines for the RV64A Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) +{ + TCGv src1 = tcg_temp_new(); + /* Put addr in load_res, data in load_val. */ + gen_get_gpr(src1, a->rs1); + if (a->rl) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); + if (a->aq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + tcg_gen_mov_tl(load_res, src1); + gen_set_gpr(a->rd, load_val); + + tcg_temp_free(src1); + return true; +} + +static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) +{ + TCGv src1 = tcg_temp_new(); + TCGv src2 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + TCGLabel *l1 = gen_new_label(); + TCGLabel *l2 = gen_new_label(); + + gen_get_gpr(src1, a->rs1); + tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); + + gen_get_gpr(src2, a->rs2); + /* + * Note that the TCG atomic primitives are SC, + * so we can ignore AQ/RL along this path. + */ + tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, + ctx->mem_idx, mop); + tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); + gen_set_gpr(a->rd, dat); + tcg_gen_br(l2); + + gen_set_label(l1); + /* + * Address comparison failure. However, we still need to + * provide the memory barrier implied by AQ/RL. + */ + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); + tcg_gen_movi_tl(dat, 1); + gen_set_gpr(a->rd, dat); + + gen_set_label(l2); + /* + * Clear the load reservation, since an SC must fail if there is + * an SC to any address, in between an LR and SC pair. + */ + tcg_gen_movi_tl(load_res, -1); + + tcg_temp_free(dat); + tcg_temp_free(src1); + tcg_temp_free(src2); + return true; +} + +static bool gen_amo(DisasContext *ctx, arg_atomic *a, + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), + MemOp mop) +{ + TCGv src1 = tcg_temp_new(); + TCGv src2 = tcg_temp_new(); + + gen_get_gpr(src1, a->rs1); + gen_get_gpr(src2, a->rs2); + + (*func)(src2, src1, src2, ctx->mem_idx, mop); + + gen_set_gpr(a->rd, src2); + tcg_temp_free(src1); + tcg_temp_free(src2); + return true; +} + +static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_sc(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) +{ + REQUIRE_EXT(ctx, RVA); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL)); +} + +#ifdef TARGET_RISCV64 + +static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) +{ + return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); +} + +static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) +{ + return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ)); +} +#endif diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c deleted file mode 100644 index be8a9f06dd..0000000000 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * RISC-V translation routines for the RV64A Standard Extension. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) -{ - TCGv src1 = tcg_temp_new(); - /* Put addr in load_res, data in load_val. */ - gen_get_gpr(src1, a->rs1); - if (a->rl) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); - if (a->aq) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - tcg_gen_mov_tl(load_res, src1); - gen_set_gpr(a->rd, load_val); - - tcg_temp_free(src1); - return true; -} - -static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) -{ - TCGv src1 = tcg_temp_new(); - TCGv src2 = tcg_temp_new(); - TCGv dat = tcg_temp_new(); - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - - gen_get_gpr(src1, a->rs1); - tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); - - gen_get_gpr(src2, a->rs2); - /* - * Note that the TCG atomic primitives are SC, - * so we can ignore AQ/RL along this path. - */ - tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, - ctx->mem_idx, mop); - tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); - gen_set_gpr(a->rd, dat); - tcg_gen_br(l2); - - gen_set_label(l1); - /* - * Address comparison failure. However, we still need to - * provide the memory barrier implied by AQ/RL. - */ - tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); - tcg_gen_movi_tl(dat, 1); - gen_set_gpr(a->rd, dat); - - gen_set_label(l2); - /* - * Clear the load reservation, since an SC must fail if there is - * an SC to any address, in between an LR and SC pair. - */ - tcg_gen_movi_tl(load_res, -1); - - tcg_temp_free(dat); - tcg_temp_free(src1); - tcg_temp_free(src2); - return true; -} - -static bool gen_amo(DisasContext *ctx, arg_atomic *a, - void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), - MemOp mop) -{ - TCGv src1 = tcg_temp_new(); - TCGv src2 = tcg_temp_new(); - - gen_get_gpr(src1, a->rs1); - gen_get_gpr(src2, a->rs2); - - (*func)(src2, src1, src2, ctx->mem_idx, mop); - - gen_set_gpr(a->rd, src2); - tcg_temp_free(src1); - tcg_temp_free(src2); - return true; -} - -static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); -} - -static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_sc(ctx, a, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL)); -} - -static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) -{ - REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL)); -} - -#ifdef TARGET_RISCV64 - -static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) -{ - return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); -} - -static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) -{ - return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ)); -} - -static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) -{ - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ)); -} -#endif diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc new file mode 100644 index 0000000000..ea1044f13b --- /dev/null +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -0,0 +1,441 @@ +/* + * RISC-V translation routines for the RV64D Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_fld(DisasContext *ctx, arg_fld *a) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + return true; +} + +static bool trans_fsd(DisasContext *ctx, arg_fsd *a) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) +{ + if (a->rs1 == a->rs2) { /* FMOV */ + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], + cpu_fpr[a->rs1], 0, 63); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + if (a->rs1 == a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); + tcg_temp_free_i64(t0); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + if (a->rs1 == a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_temp_free_i64(t0); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + mark_fs_dirty(ctx); + return true; +} + +#ifdef TARGET_RISCV64 + +static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + gen_set_gpr(a->rd, cpu_fpr[a->rs1]); + return true; +} + +static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + tcg_gen_mov_tl(cpu_fpr[a->rd], t0); + tcg_temp_free(t0); + mark_fs_dirty(ctx); + return true; +} +#endif diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c deleted file mode 100644 index ea1044f13b..0000000000 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * RISC-V translation routines for the RV64D Standard Extension. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static bool trans_fld(DisasContext *ctx, arg_fld *a) -{ - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; -} - -static bool trans_fsd(DisasContext *ctx, arg_fsd *a) -{ - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); - - tcg_temp_free(t0); - return true; -} - -static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - gen_set_rm(ctx, a->rm); - gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - gen_set_rm(ctx, a->rm); - gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) -{ - if (a->rs1 == a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); - } else { - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], - cpu_fpr[a->rs1], 0, 63); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - if (a->rs1 == a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); - tcg_temp_free_i64(t0); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - if (a->rs1 == a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); - tcg_temp_free_i64(t0); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); - - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); - - mark_fs_dirty(ctx); - return true; -} - -#ifdef TARGET_RISCV64 - -static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - gen_set_gpr(a->rd, cpu_fpr[a->rs1]); - return true; -} - -static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); - tcg_temp_free(t0); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - tcg_gen_mov_tl(cpu_fpr[a->rd], t0); - tcg_temp_free(t0); - mark_fs_dirty(ctx); - return true; -} -#endif diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc new file mode 100644 index 0000000000..3bfd8881e7 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -0,0 +1,451 @@ +/* + * RISC-V translation routines for the RV64F Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_FPU do {\ + if (ctx->mstatus_fs == 0) \ + return false; \ +} while (0) + +/* + * RISC-V requires NaN-boxing of narrower width floating + * point values. This applies when a 32-bit value is + * assigned to a 64-bit FP register. Thus this does not + * apply when the RVD extension is not present. + */ +static void gen_nanbox_fpr(DisasContext *ctx, int regno) +{ + if (has_ext(ctx, RVD)) { + tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], + MAKE_64BIT_MASK(32, 32)); + } +} + +static bool trans_flw(DisasContext *ctx, arg_flw *a) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); + gen_nanbox_fpr(ctx, a->rd); + + tcg_temp_free(t0); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsw(DisasContext *ctx, arg_fsw *a) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + if (a->rs1 == a->rs2) { /* FMOV */ + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { /* FSGNJ */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], + 0, 31); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + if (a->rs1 == a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); + tcg_temp_free_i64(t0); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + if (a->rs1 == a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_temp_free_i64(t0); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) +{ + /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + +#if defined(TARGET_RISCV64) + tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); +#else + tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); +#endif + + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + + gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); + + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) +{ + /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + +#if defined(TARGET_RISCV64) + tcg_gen_mov_i64(cpu_fpr[a->rd], t0); +#else + tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); +#endif + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + + return true; +} + +#ifdef TARGET_RISCV64 +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) +{ + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + tcg_temp_free(t0); + return true; +} +#endif diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c deleted file mode 100644 index 3bfd8881e7..0000000000 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * RISC-V translation routines for the RV64F Standard Extension. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#define REQUIRE_FPU do {\ - if (ctx->mstatus_fs == 0) \ - return false; \ -} while (0) - -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - -static bool trans_flw(DisasContext *ctx, arg_flw *a) -{ - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_fpr(ctx, a->rd); - - tcg_temp_free(t0); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsw(DisasContext *ctx, arg_fsw *a) -{ - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); - - tcg_temp_free(t0); - return true; -} - -static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - gen_set_rm(ctx, a->rm); - gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - gen_set_rm(ctx, a->rm); - gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_set_rm(ctx, a->rm); - gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - if (a->rs1 == a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); - } else { /* FSGNJ */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], - 0, 31); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - if (a->rs1 == a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); - tcg_temp_free_i64(t0); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - if (a->rs1 == a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); - } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); - tcg_temp_free_i64(t0); - } - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); - mark_fs_dirty(ctx); - return true; -} - -static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) -{ - /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - -#if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); -#else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); -#endif - - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - TCGv t0 = tcg_temp_new(); - gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - TCGv t0 = tcg_temp_new(); - gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - TCGv t0 = tcg_temp_new(); - gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - - gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); - - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - - return true; -} - -static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) -{ - /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - -#if defined(TARGET_RISCV64) - tcg_gen_mov_i64(cpu_fpr[a->rd], t0); -#else - tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); -#endif - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - - return true; -} - -#ifdef TARGET_RISCV64 -static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; -} - -static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; -} - -static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) -{ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); - - mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; -} -#endif diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc new file mode 100644 index 0000000000..263b652d90 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -0,0 +1,37 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2020 Western Digital + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_tlb_flush(cpu_env); + return true; +#endif + return false; +} diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c deleted file mode 100644 index 263b652d90..0000000000 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * RISC-V translation routines for the RVXI Base Integer Instruction Set. - * - * Copyright (c) 2020 Western Digital - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) -{ - REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - gen_helper_hyp_tlb_flush(cpu_env); - return true; -#endif - return false; -} - -static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a) -{ - REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - gen_helper_hyp_tlb_flush(cpu_env); - return true; -#endif - return false; -} diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc new file mode 100644 index 0000000000..d04ca0394c --- /dev/null +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -0,0 +1,577 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_illegal(DisasContext *ctx, arg_empty *a) +{ + gen_exception_illegal(ctx); + return true; +} + +static bool trans_lui(DisasContext *ctx, arg_lui *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) +{ + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} + +static bool trans_jal(DisasContext *ctx, arg_jal *a) +{ + gen_jal(ctx, a->rd, a->imm); + return true; +} + +static bool trans_jalr(DisasContext *ctx, arg_jalr *a) +{ + /* no chaining with JALR */ + TCGLabel *misaligned = NULL; + TCGv t0 = tcg_temp_new(); + + + gen_get_gpr(cpu_pc, a->rs1); + tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); + + if (!has_ext(ctx, RVC)) { + misaligned = gen_new_label(); + tcg_gen_andi_tl(t0, cpu_pc, 0x2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + } + + if (a->rd != 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); + } + lookup_and_goto_ptr(ctx); + + if (misaligned) { + gen_set_label(misaligned); + gen_exception_inst_addr_mis(ctx); + } + ctx->base.is_jmp = DISAS_NORETURN; + + tcg_temp_free(t0); + return true; +} + +static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) +{ + TCGLabel *l = gen_new_label(); + TCGv source1, source2; + source1 = tcg_temp_new(); + source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_brcond_tl(cond, source1, source2, l); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ + + if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + /* misaligned */ + gen_exception_inst_addr_mis(ctx); + } else { + gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); + } + ctx->base.is_jmp = DISAS_NORETURN; + + tcg_temp_free(source1); + tcg_temp_free(source2); + + return true; +} + +static bool trans_beq(DisasContext *ctx, arg_beq *a) +{ + return gen_branch(ctx, a, TCG_COND_EQ); +} + +static bool trans_bne(DisasContext *ctx, arg_bne *a) +{ + return gen_branch(ctx, a, TCG_COND_NE); +} + +static bool trans_blt(DisasContext *ctx, arg_blt *a) +{ + return gen_branch(ctx, a, TCG_COND_LT); +} + +static bool trans_bge(DisasContext *ctx, arg_bge *a) +{ + return gen_branch(ctx, a, TCG_COND_GE); +} + +static bool trans_bltu(DisasContext *ctx, arg_bltu *a) +{ + return gen_branch(ctx, a, TCG_COND_LTU); +} + +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) +{ + return gen_branch(ctx, a, TCG_COND_GEU); +} + +static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); + gen_set_gpr(a->rd, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + return true; +} + +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + return gen_load(ctx, a, MO_SB); +} + +static bool trans_lh(DisasContext *ctx, arg_lh *a) +{ + return gen_load(ctx, a, MO_TESW); +} + +static bool trans_lw(DisasContext *ctx, arg_lw *a) +{ + return gen_load(ctx, a, MO_TESL); +} + +static bool trans_lbu(DisasContext *ctx, arg_lbu *a) +{ + return gen_load(ctx, a, MO_UB); +} + +static bool trans_lhu(DisasContext *ctx, arg_lhu *a) +{ + return gen_load(ctx, a, MO_TEUW); +} + +static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) +{ + TCGv t0 = tcg_temp_new(); + TCGv dat = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + gen_get_gpr(dat, a->rs2); + + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); + tcg_temp_free(t0); + tcg_temp_free(dat); + return true; +} + + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + return gen_store(ctx, a, MO_SB); +} + +static bool trans_sh(DisasContext *ctx, arg_sh *a) +{ + return gen_store(ctx, a, MO_TESW); +} + +static bool trans_sw(DisasContext *ctx, arg_sw *a) +{ + return gen_store(ctx, a, MO_TESL); +} + +#ifdef TARGET_RISCV64 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + return gen_load(ctx, a, MO_TEUL); +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + return gen_load(ctx, a, MO_TEQ); +} + +static bool trans_sd(DisasContext *ctx, arg_sd *a) +{ + return gen_store(ctx, a, MO_TEQ); +} +#endif + +static bool trans_addi(DisasContext *ctx, arg_addi *a) +{ + return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl); +} + +static void gen_slt(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2); +} + +static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); +} + + +static bool trans_slti(DisasContext *ctx, arg_slti *a) +{ + return gen_arith_imm_tl(ctx, a, &gen_slt); +} + +static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) +{ + return gen_arith_imm_tl(ctx, a, &gen_sltu); +} + +static bool trans_xori(DisasContext *ctx, arg_xori *a) +{ + return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl); +} +static bool trans_ori(DisasContext *ctx, arg_ori *a) +{ + return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl); +} +static bool trans_andi(DisasContext *ctx, arg_andi *a) +{ + return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl); +} +static bool trans_slli(DisasContext *ctx, arg_slli *a) +{ + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + if (a->rd != 0) { + TCGv t = tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_shli_tl(t, t, a->shamt); + + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ + return true; +} + +static bool trans_srli(DisasContext *ctx, arg_srli *a) +{ + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + if (a->rd != 0) { + TCGv t = tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_shri_tl(t, t, a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ + return true; +} + +static bool trans_srai(DisasContext *ctx, arg_srai *a) +{ + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + if (a->rd != 0) { + TCGv t = tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_sari_tl(t, t, a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ + return true; +} + +static bool trans_add(DisasContext *ctx, arg_add *a) +{ + return gen_arith(ctx, a, &tcg_gen_add_tl); +} + +static bool trans_sub(DisasContext *ctx, arg_sub *a) +{ + return gen_arith(ctx, a, &tcg_gen_sub_tl); +} + +static bool trans_sll(DisasContext *ctx, arg_sll *a) +{ + return gen_shift(ctx, a, &tcg_gen_shl_tl); +} + +static bool trans_slt(DisasContext *ctx, arg_slt *a) +{ + return gen_arith(ctx, a, &gen_slt); +} + +static bool trans_sltu(DisasContext *ctx, arg_sltu *a) +{ + return gen_arith(ctx, a, &gen_sltu); +} + +static bool trans_xor(DisasContext *ctx, arg_xor *a) +{ + return gen_arith(ctx, a, &tcg_gen_xor_tl); +} + +static bool trans_srl(DisasContext *ctx, arg_srl *a) +{ + return gen_shift(ctx, a, &tcg_gen_shr_tl); +} + +static bool trans_sra(DisasContext *ctx, arg_sra *a) +{ + return gen_shift(ctx, a, &tcg_gen_sar_tl); +} + +static bool trans_or(DisasContext *ctx, arg_or *a) +{ + return gen_arith(ctx, a, &tcg_gen_or_tl); +} + +static bool trans_and(DisasContext *ctx, arg_and *a) +{ + return gen_arith(ctx, a, &tcg_gen_and_tl); +} + +#ifdef TARGET_RISCV64 +static bool trans_addiw(DisasContext *ctx, arg_addiw *a) +{ + return gen_arith_imm_tl(ctx, a, &gen_addw); +} + +static bool trans_slliw(DisasContext *ctx, arg_slliw *a) +{ + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_shli_tl(source1, source1, a->shamt); + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + + tcg_temp_free(source1); + return true; +} + +static bool trans_srliw(DisasContext *ctx, arg_srliw *a) +{ + TCGv t = tcg_temp_new(); + gen_get_gpr(t, a->rs1); + tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); + /* sign-extend for W instructions */ + tcg_gen_ext32s_tl(t, t); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + return true; +} + +static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) +{ + TCGv t = tcg_temp_new(); + gen_get_gpr(t, a->rs1); + tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + return true; +} + +static bool trans_addw(DisasContext *ctx, arg_addw *a) +{ + return gen_arith(ctx, a, &gen_addw); +} + +static bool trans_subw(DisasContext *ctx, arg_subw *a) +{ + return gen_arith(ctx, a, &gen_subw); +} + +static bool trans_sllw(DisasContext *ctx, arg_sllw *a) +{ + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shl_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +static bool trans_srlw(DisasContext *ctx, arg_srlw *a) +{ + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* clear upper 32 */ + tcg_gen_ext32u_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shr_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +static bool trans_sraw(DisasContext *ctx, arg_sraw *a) +{ + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* + * first, trick to get it to act like working on 32 bits (get rid of + * upper 32, sign extend to fill space) + */ + tcg_gen_ext32s_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_sar_tl(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + + return true; +} +#endif + +static bool trans_fence(DisasContext *ctx, arg_fence *a) +{ + /* FENCE is a full memory barrier. */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) +{ + if (!ctx->ext_ifencei) { + return false; + } + + /* + * FENCE_I is a no-op in QEMU, + * however we need to end the translation block + */ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + exit_tb(ctx); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} + +#define RISCV_OP_CSR_PRE do {\ + source1 = tcg_temp_new(); \ + csr_store = tcg_temp_new(); \ + dest = tcg_temp_new(); \ + rs1_pass = tcg_temp_new(); \ + gen_get_gpr(source1, a->rs1); \ + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \ + tcg_gen_movi_tl(rs1_pass, a->rs1); \ + tcg_gen_movi_tl(csr_store, a->csr); \ + gen_io_start();\ +} while (0) + +#define RISCV_OP_CSR_POST do {\ + gen_set_gpr(a->rd, dest); \ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \ + exit_tb(ctx); \ + ctx->base.is_jmp = DISAS_NORETURN; \ + tcg_temp_free(source1); \ + tcg_temp_free(csr_store); \ + tcg_temp_free(dest); \ + tcg_temp_free(rs1_pass); \ +} while (0) + + +static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrw(dest, cpu_env, source1, csr_store); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c deleted file mode 100644 index d04ca0394c..0000000000 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * RISC-V translation routines for the RVXI Base Integer Instruction Set. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -static bool trans_illegal(DisasContext *ctx, arg_empty *a) -{ - gen_exception_illegal(ctx); - return true; -} - -static bool trans_lui(DisasContext *ctx, arg_lui *a) -{ - if (a->rd != 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); - } - return true; -} - -static bool trans_auipc(DisasContext *ctx, arg_auipc *a) -{ - if (a->rd != 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); - } - return true; -} - -static bool trans_jal(DisasContext *ctx, arg_jal *a) -{ - gen_jal(ctx, a->rd, a->imm); - return true; -} - -static bool trans_jalr(DisasContext *ctx, arg_jalr *a) -{ - /* no chaining with JALR */ - TCGLabel *misaligned = NULL; - TCGv t0 = tcg_temp_new(); - - - gen_get_gpr(cpu_pc, a->rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); - tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); - - if (!has_ext(ctx, RVC)) { - misaligned = gen_new_label(); - tcg_gen_andi_tl(t0, cpu_pc, 0x2); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); - } - - if (a->rd != 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); - } - lookup_and_goto_ptr(ctx); - - if (misaligned) { - gen_set_label(misaligned); - gen_exception_inst_addr_mis(ctx); - } - ctx->base.is_jmp = DISAS_NORETURN; - - tcg_temp_free(t0); - return true; -} - -static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) -{ - TCGLabel *l = gen_new_label(); - TCGv source1, source2; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_brcond_tl(cond, source1, source2, l); - gen_goto_tb(ctx, 1, ctx->pc_succ_insn); - gen_set_label(l); /* branch taken */ - - if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { - /* misaligned */ - gen_exception_inst_addr_mis(ctx); - } else { - gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); - } - ctx->base.is_jmp = DISAS_NORETURN; - - tcg_temp_free(source1); - tcg_temp_free(source2); - - return true; -} - -static bool trans_beq(DisasContext *ctx, arg_beq *a) -{ - return gen_branch(ctx, a, TCG_COND_EQ); -} - -static bool trans_bne(DisasContext *ctx, arg_bne *a) -{ - return gen_branch(ctx, a, TCG_COND_NE); -} - -static bool trans_blt(DisasContext *ctx, arg_blt *a) -{ - return gen_branch(ctx, a, TCG_COND_LT); -} - -static bool trans_bge(DisasContext *ctx, arg_bge *a) -{ - return gen_branch(ctx, a, TCG_COND_GE); -} - -static bool trans_bltu(DisasContext *ctx, arg_bltu *a) -{ - return gen_branch(ctx, a, TCG_COND_LTU); -} - -static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) -{ - return gen_branch(ctx, a, TCG_COND_GEU); -} - -static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(a->rd, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; -} - -static bool trans_lb(DisasContext *ctx, arg_lb *a) -{ - return gen_load(ctx, a, MO_SB); -} - -static bool trans_lh(DisasContext *ctx, arg_lh *a) -{ - return gen_load(ctx, a, MO_TESW); -} - -static bool trans_lw(DisasContext *ctx, arg_lw *a) -{ - return gen_load(ctx, a, MO_TESL); -} - -static bool trans_lbu(DisasContext *ctx, arg_lbu *a) -{ - return gen_load(ctx, a, MO_UB); -} - -static bool trans_lhu(DisasContext *ctx, arg_lhu *a) -{ - return gen_load(ctx, a, MO_TEUW); -} - -static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) -{ - TCGv t0 = tcg_temp_new(); - TCGv dat = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); - gen_get_gpr(dat, a->rs2); - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); - tcg_temp_free(t0); - tcg_temp_free(dat); - return true; -} - - -static bool trans_sb(DisasContext *ctx, arg_sb *a) -{ - return gen_store(ctx, a, MO_SB); -} - -static bool trans_sh(DisasContext *ctx, arg_sh *a) -{ - return gen_store(ctx, a, MO_TESW); -} - -static bool trans_sw(DisasContext *ctx, arg_sw *a) -{ - return gen_store(ctx, a, MO_TESL); -} - -#ifdef TARGET_RISCV64 -static bool trans_lwu(DisasContext *ctx, arg_lwu *a) -{ - return gen_load(ctx, a, MO_TEUL); -} - -static bool trans_ld(DisasContext *ctx, arg_ld *a) -{ - return gen_load(ctx, a, MO_TEQ); -} - -static bool trans_sd(DisasContext *ctx, arg_sd *a) -{ - return gen_store(ctx, a, MO_TEQ); -} -#endif - -static bool trans_addi(DisasContext *ctx, arg_addi *a) -{ - return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl); -} - -static void gen_slt(TCGv ret, TCGv s1, TCGv s2) -{ - tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2); -} - -static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) -{ - tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); -} - - -static bool trans_slti(DisasContext *ctx, arg_slti *a) -{ - return gen_arith_imm_tl(ctx, a, &gen_slt); -} - -static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) -{ - return gen_arith_imm_tl(ctx, a, &gen_sltu); -} - -static bool trans_xori(DisasContext *ctx, arg_xori *a) -{ - return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl); -} -static bool trans_ori(DisasContext *ctx, arg_ori *a) -{ - return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl); -} -static bool trans_andi(DisasContext *ctx, arg_andi *a) -{ - return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl); -} -static bool trans_slli(DisasContext *ctx, arg_slli *a) -{ - if (a->shamt >= TARGET_LONG_BITS) { - return false; - } - - if (a->rd != 0) { - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - - tcg_gen_shli_tl(t, t, a->shamt); - - gen_set_gpr(a->rd, t); - tcg_temp_free(t); - } /* NOP otherwise */ - return true; -} - -static bool trans_srli(DisasContext *ctx, arg_srli *a) -{ - if (a->shamt >= TARGET_LONG_BITS) { - return false; - } - - if (a->rd != 0) { - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - - tcg_gen_shri_tl(t, t, a->shamt); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); - } /* NOP otherwise */ - return true; -} - -static bool trans_srai(DisasContext *ctx, arg_srai *a) -{ - if (a->shamt >= TARGET_LONG_BITS) { - return false; - } - - if (a->rd != 0) { - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - - tcg_gen_sari_tl(t, t, a->shamt); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); - } /* NOP otherwise */ - return true; -} - -static bool trans_add(DisasContext *ctx, arg_add *a) -{ - return gen_arith(ctx, a, &tcg_gen_add_tl); -} - -static bool trans_sub(DisasContext *ctx, arg_sub *a) -{ - return gen_arith(ctx, a, &tcg_gen_sub_tl); -} - -static bool trans_sll(DisasContext *ctx, arg_sll *a) -{ - return gen_shift(ctx, a, &tcg_gen_shl_tl); -} - -static bool trans_slt(DisasContext *ctx, arg_slt *a) -{ - return gen_arith(ctx, a, &gen_slt); -} - -static bool trans_sltu(DisasContext *ctx, arg_sltu *a) -{ - return gen_arith(ctx, a, &gen_sltu); -} - -static bool trans_xor(DisasContext *ctx, arg_xor *a) -{ - return gen_arith(ctx, a, &tcg_gen_xor_tl); -} - -static bool trans_srl(DisasContext *ctx, arg_srl *a) -{ - return gen_shift(ctx, a, &tcg_gen_shr_tl); -} - -static bool trans_sra(DisasContext *ctx, arg_sra *a) -{ - return gen_shift(ctx, a, &tcg_gen_sar_tl); -} - -static bool trans_or(DisasContext *ctx, arg_or *a) -{ - return gen_arith(ctx, a, &tcg_gen_or_tl); -} - -static bool trans_and(DisasContext *ctx, arg_and *a) -{ - return gen_arith(ctx, a, &tcg_gen_and_tl); -} - -#ifdef TARGET_RISCV64 -static bool trans_addiw(DisasContext *ctx, arg_addiw *a) -{ - return gen_arith_imm_tl(ctx, a, &gen_addw); -} - -static bool trans_slliw(DisasContext *ctx, arg_slliw *a) -{ - TCGv source1; - source1 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - - tcg_gen_shli_tl(source1, source1, a->shamt); - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - - tcg_temp_free(source1); - return true; -} - -static bool trans_srliw(DisasContext *ctx, arg_srliw *a) -{ - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); - /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(t, t); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); - return true; -} - -static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) -{ - TCGv t = tcg_temp_new(); - gen_get_gpr(t, a->rs1); - tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); - gen_set_gpr(a->rd, t); - tcg_temp_free(t); - return true; -} - -static bool trans_addw(DisasContext *ctx, arg_addw *a) -{ - return gen_arith(ctx, a, &gen_addw); -} - -static bool trans_subw(DisasContext *ctx, arg_subw *a) -{ - return gen_arith(ctx, a, &gen_subw); -} - -static bool trans_sllw(DisasContext *ctx, arg_sllw *a) -{ - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static bool trans_srlw(DisasContext *ctx, arg_srlw *a) -{ - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); - - tcg_gen_ext32s_tl(source1, source1); - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static bool trans_sraw(DisasContext *ctx, arg_sraw *a) -{ - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - /* - * first, trick to get it to act like working on 32 bits (get rid of - * upper 32, sign extend to fill space) - */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - - return true; -} -#endif - -static bool trans_fence(DisasContext *ctx, arg_fence *a) -{ - /* FENCE is a full memory barrier. */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return true; -} - -static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) -{ - if (!ctx->ext_ifencei) { - return false; - } - - /* - * FENCE_I is a no-op in QEMU, - * however we need to end the translation block - */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - exit_tb(ctx); - ctx->base.is_jmp = DISAS_NORETURN; - return true; -} - -#define RISCV_OP_CSR_PRE do {\ - source1 = tcg_temp_new(); \ - csr_store = tcg_temp_new(); \ - dest = tcg_temp_new(); \ - rs1_pass = tcg_temp_new(); \ - gen_get_gpr(source1, a->rs1); \ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \ - tcg_gen_movi_tl(rs1_pass, a->rs1); \ - tcg_gen_movi_tl(csr_store, a->csr); \ - gen_io_start();\ -} while (0) - -#define RISCV_OP_CSR_POST do {\ - gen_set_gpr(a->rd, dest); \ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \ - exit_tb(ctx); \ - ctx->base.is_jmp = DISAS_NORETURN; \ - tcg_temp_free(source1); \ - tcg_temp_free(csr_store); \ - tcg_temp_free(dest); \ - tcg_temp_free(rs1_pass); \ -} while (0) - - -static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrw(dest, cpu_env, source1, csr_store); - RISCV_OP_CSR_POST; - return true; -} - -static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; -} - -static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; -} - -static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store); - RISCV_OP_CSR_POST; - return true; -} - -static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; -} - -static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) -{ - TCGv source1, csr_store, dest, rs1_pass; - RISCV_OP_CSR_PRE; - gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass); - RISCV_OP_CSR_POST; - return true; -} diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc new file mode 100644 index 0000000000..47cd6edc72 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -0,0 +1,120 @@ +/* + * RISC-V translation routines for the RV64M Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + + +static bool trans_mul(DisasContext *ctx, arg_mul *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &tcg_gen_mul_tl); +} + +static bool trans_mulh(DisasContext *ctx, arg_mulh *a) +{ + REQUIRE_EXT(ctx, RVM); + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_muls2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_mulhsu); +} + +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) +{ + REQUIRE_EXT(ctx, RVM); + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_mulu2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +static bool trans_div(DisasContext *ctx, arg_div *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_div); +} + +static bool trans_divu(DisasContext *ctx, arg_divu *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_divu); +} + +static bool trans_rem(DisasContext *ctx, arg_rem *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_rem); +} + +static bool trans_remu(DisasContext *ctx, arg_remu *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_remu); +} + +#ifdef TARGET_RISCV64 +static bool trans_mulw(DisasContext *ctx, arg_mulw *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith(ctx, a, &gen_mulw); +} + +static bool trans_divw(DisasContext *ctx, arg_divw *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_div); +} + +static bool trans_divuw(DisasContext *ctx, arg_divuw *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_divu); +} + +static bool trans_remw(DisasContext *ctx, arg_remw *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith_div_w(ctx, a, &gen_rem); +} + +static bool trans_remuw(DisasContext *ctx, arg_remuw *a) +{ + REQUIRE_EXT(ctx, RVM); + return gen_arith_div_uw(ctx, a, &gen_remu); +} +#endif diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c deleted file mode 100644 index 47cd6edc72..0000000000 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * RISC-V translation routines for the RV64M Standard Extension. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - - -static bool trans_mul(DisasContext *ctx, arg_mul *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &tcg_gen_mul_tl); -} - -static bool trans_mulh(DisasContext *ctx, arg_mulh *a) -{ - REQUIRE_EXT(ctx, RVM); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_muls2_tl(source2, source1, source1, source2); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_mulhsu); -} - -static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) -{ - REQUIRE_EXT(ctx, RVM); - TCGv source1 = tcg_temp_new(); - TCGv source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); - - tcg_gen_mulu2_tl(source2, source1, source1, source2); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; -} - -static bool trans_div(DisasContext *ctx, arg_div *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_div); -} - -static bool trans_divu(DisasContext *ctx, arg_divu *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_divu); -} - -static bool trans_rem(DisasContext *ctx, arg_rem *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_rem); -} - -static bool trans_remu(DisasContext *ctx, arg_remu *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_remu); -} - -#ifdef TARGET_RISCV64 -static bool trans_mulw(DisasContext *ctx, arg_mulw *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith(ctx, a, &gen_mulw); -} - -static bool trans_divw(DisasContext *ctx, arg_divw *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith_div_w(ctx, a, &gen_div); -} - -static bool trans_divuw(DisasContext *ctx, arg_divuw *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith_div_uw(ctx, a, &gen_divu); -} - -static bool trans_remw(DisasContext *ctx, arg_remw *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith_div_w(ctx, a, &gen_rem); -} - -static bool trans_remuw(DisasContext *ctx, arg_remuw *a) -{ - REQUIRE_EXT(ctx, RVM); - return gen_arith_div_uw(ctx, a, &gen_remu); -} -#endif diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc new file mode 100644 index 0000000000..887c6b8883 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -0,0 +1,2902 @@ +/* + * RISC-V translation routines for the RVV Standard Extension. + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +{ + TCGv s1, s2, dst; + + if (!has_ext(ctx, RVV)) { + return false; + } + + s2 = tcg_temp_new(); + dst = tcg_temp_new(); + + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ + if (a->rs1 == 0) { + /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ + s1 = tcg_const_tl(RV_VLEN_MAX); + } else { + s1 = tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + } + gen_get_gpr(s2, a->rs2); + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(a->rd, dst); + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + lookup_and_goto_ptr(ctx); + ctx->base.is_jmp = DISAS_NORETURN; + + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(dst); + return true; +} + +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) +{ + TCGv s1, s2, dst; + + if (!has_ext(ctx, RVV)) { + return false; + } + + s2 = tcg_const_tl(a->zimm); + dst = tcg_temp_new(); + + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ + if (a->rs1 == 0) { + /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ + s1 = tcg_const_tl(RV_VLEN_MAX); + } else { + s1 = tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + } + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(a->rd, dst); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); + ctx->base.is_jmp = DISAS_NORETURN; + + tcg_temp_free(s1); + tcg_temp_free(s2); + tcg_temp_free(dst); + return true; +} + +/* vector register offset from env */ +static uint32_t vreg_ofs(DisasContext *s, int reg) +{ + return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8; +} + +/* check functions */ + +/* + * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. + * So RVV is also be checked in this function. + */ +static bool vext_check_isa_ill(DisasContext *s) +{ + return !s->vill; +} + +/* + * There are two rules check here. + * + * 1. Vector register numbers are multiples of LMUL. (Section 3.2) + * + * 2. For all widening instructions, the destination LMUL value must also be + * a supported LMUL value. (Section 11.2) + */ +static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) +{ + /* + * The destination vector register group results are arranged as if both + * SEW and LMUL were at twice their current settings. (Section 11.2). + */ + int legal = widen ? 2 << s->lmul : 1 << s->lmul; + + return !((s->lmul == 0x3 && widen) || (reg % legal)); +} + +/* + * There are two rules check here. + * + * 1. The destination vector register group for a masked vector instruction can + * only overlap the source mask register (v0) when LMUL=1. (Section 5.3) + * + * 2. In widen instructions and some other insturctions, like vslideup.vx, + * there is no need to check whether LMUL=1. + */ +static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm, + bool force) +{ + return (vm != 0 || vd != 0) || (!force && (s->lmul == 0)); +} + +/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */ +static bool vext_check_nf(DisasContext *s, uint32_t nf) +{ + return (1 << s->lmul) * nf <= 8; +} + +/* + * The destination vector register group cannot overlap a source vector register + * group of a different element width. (Section 11.2) + */ +static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen) +{ + return ((rd >= rs + slen) || (rs >= rd + dlen)); +} +/* common translation macro */ +#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ +{ \ + if (CHECK(s, a)) { \ + return OP(s, a, SEQ); \ + } \ + return false; \ +} + +/* + *** unit stride load and store + */ +typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, + TCGv_env, TCGv_i32); + +static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, + gen_helper_ldst_us *fn, DisasContext *s) +{ + TCGv_ptr dest, mask; + TCGv base; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + base = tcg_temp_new(); + + /* + * As simd_desc supports at most 256 bytes, and in this implementation, + * the max vector group length is 2048 bytes. So split it into two parts. + * + * The first part is vlen in bytes, encoded in maxsz of simd_desc. + * The second part is lmul, encoded in data of simd_desc. + */ + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn; + static gen_helper_ldst_us * const fns[2][7][4] = { + /* masked unit stride load */ + { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask, + gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask }, + { NULL, gen_helper_vlh_v_h_mask, + gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask }, + { NULL, NULL, + gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask }, + { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask, + gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask }, + { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask, + gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask }, + { NULL, gen_helper_vlhu_v_h_mask, + gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask }, + { NULL, NULL, + gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } }, + /* unmasked unit stride load */ + { { gen_helper_vlb_v_b, gen_helper_vlb_v_h, + gen_helper_vlb_v_w, gen_helper_vlb_v_d }, + { NULL, gen_helper_vlh_v_h, + gen_helper_vlh_v_w, gen_helper_vlh_v_d }, + { NULL, NULL, + gen_helper_vlw_v_w, gen_helper_vlw_v_d }, + { gen_helper_vle_v_b, gen_helper_vle_v_h, + gen_helper_vle_v_w, gen_helper_vle_v_d }, + { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h, + gen_helper_vlbu_v_w, gen_helper_vlbu_v_d }, + { NULL, gen_helper_vlhu_v_h, + gen_helper_vlhu_v_w, gen_helper_vlhu_v_d }, + { NULL, NULL, + gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } } + }; + + fn = fns[a->vm][seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); +} + +static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_nf(s, a->nf)); +} + +GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check) + +static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn; + static gen_helper_ldst_us * const fns[2][4][4] = { + /* masked unit stride load and store */ + { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask, + gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask }, + { NULL, gen_helper_vsh_v_h_mask, + gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask }, + { NULL, NULL, + gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask }, + { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask, + gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } }, + /* unmasked unit stride store */ + { { gen_helper_vsb_v_b, gen_helper_vsb_v_h, + gen_helper_vsb_v_w, gen_helper_vsb_v_d }, + { NULL, gen_helper_vsh_v_h, + gen_helper_vsh_v_w, gen_helper_vsh_v_d }, + { NULL, NULL, + gen_helper_vsw_v_w, gen_helper_vsw_v_d }, + { gen_helper_vse_v_b, gen_helper_vse_v_h, + gen_helper_vse_v_w, gen_helper_vse_v_d } } + }; + + fn = fns[a->vm][seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); +} + +static bool st_us_check(DisasContext *s, arg_r2nfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_nf(s, a->nf)); +} + +GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check) + +/* + *** stride load and store + */ +typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, + TCGv, TCGv_env, TCGv_i32); + +static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, + uint32_t data, gen_helper_ldst_stride *fn, + DisasContext *s) +{ + TCGv_ptr dest, mask; + TCGv base, stride; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + base = tcg_temp_new(); + stride = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + gen_get_gpr(stride, rs2); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, stride, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free(base); + tcg_temp_free(stride); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_stride *fn; + static gen_helper_ldst_stride * const fns[7][4] = { + { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h, + gen_helper_vlsb_v_w, gen_helper_vlsb_v_d }, + { NULL, gen_helper_vlsh_v_h, + gen_helper_vlsh_v_w, gen_helper_vlsh_v_d }, + { NULL, NULL, + gen_helper_vlsw_v_w, gen_helper_vlsw_v_d }, + { gen_helper_vlse_v_b, gen_helper_vlse_v_h, + gen_helper_vlse_v_w, gen_helper_vlse_v_d }, + { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h, + gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d }, + { NULL, gen_helper_vlshu_v_h, + gen_helper_vlshu_v_w, gen_helper_vlshu_v_d }, + { NULL, NULL, + gen_helper_vlswu_v_w, gen_helper_vlswu_v_d }, + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); +} + +static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_nf(s, a->nf)); +} + +GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check) + +static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_stride *fn; + static gen_helper_ldst_stride * const fns[4][4] = { + /* masked stride store */ + { gen_helper_vssb_v_b, gen_helper_vssb_v_h, + gen_helper_vssb_v_w, gen_helper_vssb_v_d }, + { NULL, gen_helper_vssh_v_h, + gen_helper_vssh_v_w, gen_helper_vssh_v_d }, + { NULL, NULL, + gen_helper_vssw_v_w, gen_helper_vssw_v_d }, + { gen_helper_vsse_v_b, gen_helper_vsse_v_h, + gen_helper_vsse_v_w, gen_helper_vsse_v_d } + }; + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); +} + +static bool st_stride_check(DisasContext *s, arg_rnfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_nf(s, a->nf)); +} + +GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) + +/* + *** index load and store + */ +typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, + TCGv_ptr, TCGv_env, TCGv_i32); + +static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, + uint32_t data, gen_helper_ldst_index *fn, + DisasContext *s) +{ + TCGv_ptr dest, mask, index; + TCGv base; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + index = tcg_temp_new_ptr(); + base = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, index, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(index); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_index *fn; + static gen_helper_ldst_index * const fns[7][4] = { + { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h, + gen_helper_vlxb_v_w, gen_helper_vlxb_v_d }, + { NULL, gen_helper_vlxh_v_h, + gen_helper_vlxh_v_w, gen_helper_vlxh_v_d }, + { NULL, NULL, + gen_helper_vlxw_v_w, gen_helper_vlxw_v_d }, + { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h, + gen_helper_vlxe_v_w, gen_helper_vlxe_v_d }, + { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h, + gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d }, + { NULL, gen_helper_vlxhu_v_h, + gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d }, + { NULL, NULL, + gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d }, + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); +} + +/* + * For vector indexed segment loads, the destination vector register + * groups cannot overlap the source vector register group (specified by + * `vs2`), else an illegal instruction exception is raised. + */ +static bool ld_index_check(DisasContext *s, arg_rnfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_nf(s, a->nf) && + ((a->nf == 1) || + vext_check_overlap_group(a->rd, a->nf << s->lmul, + a->rs2, 1 << s->lmul))); +} + +GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check) + +static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_index *fn; + static gen_helper_ldst_index * const fns[4][4] = { + { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h, + gen_helper_vsxb_v_w, gen_helper_vsxb_v_d }, + { NULL, gen_helper_vsxh_v_h, + gen_helper_vsxh_v_w, gen_helper_vsxh_v_d }, + { NULL, NULL, + gen_helper_vsxw_v_w, gen_helper_vsxw_v_d }, + { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h, + gen_helper_vsxe_v_w, gen_helper_vsxe_v_d } + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); +} + +static bool st_index_check(DisasContext *s, arg_rnfvm* a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_nf(s, a->nf)); +} + +GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check) + +/* + *** unit stride fault-only-first load + */ +static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, + gen_helper_ldst_us *fn, DisasContext *s) +{ + TCGv_ptr dest, mask; + TCGv base; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + base = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn; + static gen_helper_ldst_us * const fns[7][4] = { + { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, + gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, + { NULL, gen_helper_vlhff_v_h, + gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, + { NULL, NULL, + gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, + { gen_helper_vleff_v_b, gen_helper_vleff_v_h, + gen_helper_vleff_v_w, gen_helper_vleff_v_d }, + { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, + gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, + { NULL, gen_helper_vlhuff_v_h, + gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, + { NULL, NULL, + gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldff_trans(a->rd, a->rs1, data, fn, s); +} + +GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) + +/* + *** vector atomic operation + */ +typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, + TCGv_env, TCGv_i32); + +static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, + uint32_t data, gen_helper_amo *fn, DisasContext *s) +{ + TCGv_ptr dest, mask, index; + TCGv base; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + index = tcg_temp_new_ptr(); + base = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, index, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(index); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_amo *fn; + static gen_helper_amo *const fnsw[9] = { + /* no atomic operation */ + gen_helper_vamoswapw_v_w, + gen_helper_vamoaddw_v_w, + gen_helper_vamoxorw_v_w, + gen_helper_vamoandw_v_w, + gen_helper_vamoorw_v_w, + gen_helper_vamominw_v_w, + gen_helper_vamomaxw_v_w, + gen_helper_vamominuw_v_w, + gen_helper_vamomaxuw_v_w + }; +#ifdef TARGET_RISCV64 + static gen_helper_amo *const fnsd[18] = { + gen_helper_vamoswapw_v_d, + gen_helper_vamoaddw_v_d, + gen_helper_vamoxorw_v_d, + gen_helper_vamoandw_v_d, + gen_helper_vamoorw_v_d, + gen_helper_vamominw_v_d, + gen_helper_vamomaxw_v_d, + gen_helper_vamominuw_v_d, + gen_helper_vamomaxuw_v_d, + gen_helper_vamoswapd_v_d, + gen_helper_vamoaddd_v_d, + gen_helper_vamoxord_v_d, + gen_helper_vamoandd_v_d, + gen_helper_vamoord_v_d, + gen_helper_vamomind_v_d, + gen_helper_vamomaxd_v_d, + gen_helper_vamominud_v_d, + gen_helper_vamomaxud_v_d + }; +#endif + + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp = DISAS_NORETURN; + return true; + } else { + if (s->sew == 3) { +#ifdef TARGET_RISCV64 + fn = fnsd[seq]; +#else + /* Check done in amo_check(). */ + g_assert_not_reached(); +#endif + } else { + assert(seq < ARRAY_SIZE(fnsw)); + fn = fnsw[seq]; + } + } + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, WD, a->wd); + return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); +} +/* + * There are two rules check here. + * + * 1. SEW must be at least as wide as the AMO memory element size. + * + * 2. If SEW is greater than XLEN, an illegal instruction exception is raised. + */ +static bool amo_check(DisasContext *s, arg_rwdvm* a) +{ + return (!s->vill && has_ext(s, RVA) && + (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + ((1 << s->sew) <= sizeof(target_ulong)) && + ((1 << s->sew) >= 4)); +} + +GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) +#ifdef TARGET_RISCV64 +GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) +GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) +#endif + +/* + *** Vector Integer Arithmetic Instructions + */ +#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +static bool opivv_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false)); +} + +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t); + +static inline bool +do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, + gen_helper_gvec_4_ptr *fn) +{ + TCGLabel *over = gen_new_label(); + if (!opivv_check(s, a)) { + return false; + } + + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + if (a->vm && s->vl_eq_vlmax) { + gvec_fn(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), + MAXSZ(s), MAXSZ(s)); + } else { + uint32_t data = 0; + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), + cpu_env, 0, s->vlen / 8, data, fn); + } + gen_set_label(over); + return true; +} + +/* OPIVV with GVEC IR */ +#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_gvec_4_ptr * const fns[4] = { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ +} + +GEN_OPIVV_GVEC_TRANS(vadd_vv, add) +GEN_OPIVV_GVEC_TRANS(vsub_vv, sub) + +typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, + TCGv_env, TCGv_i32); + +static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, + gen_helper_opivx *fn, DisasContext *s) +{ + TCGv_ptr dest, src2, mask; + TCGv src1; + TCGv_i32 desc; + uint32_t data = 0; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + src2 = tcg_temp_new_ptr(); + src1 = tcg_temp_new(); + gen_get_gpr(src1, rs1); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, src1, src2, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(src2); + tcg_temp_free(src1); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool opivx_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false)); +} + +typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, + uint32_t, uint32_t); + +static inline bool +do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, + gen_helper_opivx *fn) +{ + if (!opivx_check(s, a)) { + return false; + } + + if (a->vm && s->vl_eq_vlmax) { + TCGv_i64 src1 = tcg_temp_new_i64(); + TCGv tmp = tcg_temp_new(); + + gen_get_gpr(tmp, a->rs1); + tcg_gen_ext_tl_i64(src1, tmp); + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + src1, MAXSZ(s), MAXSZ(s)); + + tcg_temp_free_i64(src1); + tcg_temp_free(tmp); + return true; + } + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); +} + +/* OPIVX with GVEC IR */ +#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[4] = { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ +} + +GEN_OPIVX_GVEC_TRANS(vadd_vx, adds) +GEN_OPIVX_GVEC_TRANS(vsub_vx, subs) + +static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_vec_sub8_i64(d, b, a); +} + +static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_vec_sub16_i64(d, b, a); +} + +static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_sub_i32(ret, arg2, arg1); +} + +static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_sub_i64(ret, arg2, arg1); +} + +static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_sub_vec(vece, r, b, a); +} + +static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 }; + static const GVecGen2s rsub_op[4] = { + { .fni8 = gen_vec_rsub8_i64, + .fniv = gen_rsub_vec, + .fno = gen_helper_vec_rsubs8, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fni8 = gen_vec_rsub16_i64, + .fniv = gen_rsub_vec, + .fno = gen_helper_vec_rsubs16, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = gen_rsub_i32, + .fniv = gen_rsub_vec, + .fno = gen_helper_vec_rsubs32, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = gen_rsub_i64, + .fniv = gen_rsub_vec, + .fno = gen_helper_vec_rsubs64, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]); +} + +GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) + +static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, + gen_helper_opivx *fn, DisasContext *s, int zx) +{ + TCGv_ptr dest, src2, mask; + TCGv src1; + TCGv_i32 desc; + uint32_t data = 0; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + src2 = tcg_temp_new_ptr(); + if (zx) { + src1 = tcg_const_tl(imm); + } else { + src1 = tcg_const_tl(sextract64(imm, 0, 5)); + } + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, src1, src2, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(src2); + tcg_temp_free(src1); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, + uint32_t, uint32_t); + +static inline bool +do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, + gen_helper_opivx *fn, int zx) +{ + if (!opivx_check(s, a)) { + return false; + } + + if (a->vm && s->vl_eq_vlmax) { + if (zx) { + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); + } else { + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); + } + } else { + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + } + return true; +} + +/* OPIVI with GVEC IR */ +#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[4] = { \ + gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ + }; \ + return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ + fns[s->sew], ZX); \ +} + +GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) + +static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz) +{ + TCGv_i64 tmp = tcg_const_i64(c); + tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); + tcg_temp_free_i64(tmp); +} + +GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) + +/* Vector Widening Integer Add/Subtract */ + +/* OPIVV with WIDEN */ +static bool opivv_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, + 1 << s->lmul) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, + gen_helper_gvec_4_ptr *fn, + bool (*checkfn)(DisasContext *, arg_rmrr *)) +{ + if (checkfn(s, a)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), + cpu_env, 0, s->vlen / 8, + data, fn); + gen_set_label(over); + return true; + } + return false; +} + +#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_gvec_4_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return do_opivv_widen(s, a, fns[s->sew], CHECK); \ +} + +GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check) + +/* OPIVX with WIDEN */ +static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, + gen_helper_opivx *fn) +{ + if (opivx_widen_check(s, a)) { + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + } + return false; +} + +#define GEN_OPIVX_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return do_opivx_widen(s, a, fns[s->sew]); \ +} + +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) +GEN_OPIVX_WIDEN_TRANS(vwadd_vx) +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) +GEN_OPIVX_WIDEN_TRANS(vwsub_vx) + +/* WIDEN OPIVV with WIDEN */ +static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, true) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, + gen_helper_gvec_4_ptr *fn) +{ + if (opiwv_widen_check(s, a)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), + cpu_env, 0, s->vlen / 8, data, fn); + gen_set_label(over); + return true; + } + return false; +} + +#define GEN_OPIWV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_gvec_4_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return do_opiwv_widen(s, a, fns[s->sew]); \ +} + +GEN_OPIWV_WIDEN_TRANS(vwaddu_wv) +GEN_OPIWV_WIDEN_TRANS(vwadd_wv) +GEN_OPIWV_WIDEN_TRANS(vwsubu_wv) +GEN_OPIWV_WIDEN_TRANS(vwsub_wv) + +/* WIDEN OPIVX with WIDEN */ +static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, true) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a, + gen_helper_opivx *fn) +{ + if (opiwx_widen_check(s, a)) { + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); + } + return false; +} + +#define GEN_OPIWX_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return do_opiwx_widen(s, a, fns[s->sew]); \ +} + +GEN_OPIWX_WIDEN_TRANS(vwaddu_wx) +GEN_OPIWX_WIDEN_TRANS(vwadd_wx) +GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) +GEN_OPIWX_WIDEN_TRANS(vwsub_wx) + +/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ +/* OPIVV without GVEC IR */ +#define GEN_OPIVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[4] = { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +/* + * For vadc and vsbc, an illegal instruction exception is raised if the + * destination vector register is v0 and LMUL > 1. (Section 12.3) + */ +static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + ((a->rd != 0) || (s->lmul == 0))); +} + +GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check) +GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check) + +/* + * For vmadc and vmsbc, an illegal instruction exception is raised if the + * destination vector register overlaps a source vector register group. + */ +static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && + vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); +} + +GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) +GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check) + +static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + ((a->rd != 0) || (s->lmul == 0))); +} + +/* OPIVX without GVEC IR */ +#define GEN_OPIVX_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[4] = { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + } \ + return false; \ +} + +GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check) +GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check) + +static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); +} + +GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) +GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) + +/* OPIVI without GVEC IR */ +#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[4] = { \ + gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ + }; \ + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, ZX); \ + } \ + return false; \ +} + +GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) + +/* Vector Bitwise Logical Instructions */ +GEN_OPIVV_GVEC_TRANS(vand_vv, and) +GEN_OPIVV_GVEC_TRANS(vor_vv, or) +GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) +GEN_OPIVX_GVEC_TRANS(vand_vx, ands) +GEN_OPIVX_GVEC_TRANS(vor_vx, ors) +GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) +GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) + +/* Vector Single-Width Bit Shift Instructions */ +GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv) +GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv) +GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv) + +typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32, + uint32_t, uint32_t); + +static inline bool +do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, + gen_helper_opivx *fn) +{ + if (!opivx_check(s, a)) { + return false; + } + + if (a->vm && s->vl_eq_vlmax) { + TCGv_i32 src1 = tcg_temp_new_i32(); + TCGv tmp = tcg_temp_new(); + + gen_get_gpr(tmp, a->rs1); + tcg_gen_trunc_tl_i32(src1, tmp); + tcg_gen_extract_i32(src1, src1, 0, s->sew + 3); + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + src1, MAXSZ(s), MAXSZ(s)); + + tcg_temp_free_i32(src1); + tcg_temp_free(tmp); + return true; + } + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); +} + +#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + static gen_helper_opivx * const fns[4] = { \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + \ + return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ +} + +GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) +GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) +GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) + +GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) + +/* Vector Narrowing Integer Right Shift Instructions */ +static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, true) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, + 2 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +/* OPIVV with NARROW */ +#define GEN_OPIVV_NARROW_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opivv_narrow_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} +GEN_OPIVV_NARROW_TRANS(vnsra_vv) +GEN_OPIVV_NARROW_TRANS(vnsrl_vv) + +static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, true) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, + 2 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3)); +} + +/* OPIVX with NARROW */ +#define GEN_OPIVX_NARROW_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opivx_narrow_check(s, a)) { \ + static gen_helper_opivx * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + } \ + return false; \ +} + +GEN_OPIVX_NARROW_TRANS(vnsra_vx) +GEN_OPIVX_NARROW_TRANS(vnsrl_vx) + +/* OPIVI with NARROW */ +#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opivx_narrow_check(s, a)) { \ + static gen_helper_opivx * const fns[3] = { \ + gen_helper_##OPIVX##_b, \ + gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, \ + }; \ + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ + fns[s->sew], s, ZX); \ + } \ + return false; \ +} + +GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx) +GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) + +/* Vector Integer Comparison Instructions */ +/* + * For all comparison instructions, an illegal instruction exception is raised + * if the destination vector register overlaps a source vector register group + * and LMUL > 1. + */ +static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && + vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || + (s->lmul == 0))); +} +GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) +GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check) +GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check) +GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check) +GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check) +GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check) + +static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || + (s->lmul == 0))); +} + +GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check) +GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) + +GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) + +/* Vector Integer Min/Max Instructions */ +GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) +GEN_OPIVV_GVEC_TRANS(vmin_vv, smin) +GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax) +GEN_OPIVV_GVEC_TRANS(vmax_vv, smax) +GEN_OPIVX_TRANS(vminu_vx, opivx_check) +GEN_OPIVX_TRANS(vmin_vx, opivx_check) +GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) +GEN_OPIVX_TRANS(vmax_vx, opivx_check) + +/* Vector Single-Width Integer Multiply Instructions */ +GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) +GEN_OPIVV_TRANS(vmulh_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) +GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) +GEN_OPIVX_TRANS(vmulh_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) + +/* Vector Integer Divide Instructions */ +GEN_OPIVV_TRANS(vdivu_vv, opivv_check) +GEN_OPIVV_TRANS(vdiv_vv, opivv_check) +GEN_OPIVV_TRANS(vremu_vv, opivv_check) +GEN_OPIVV_TRANS(vrem_vv, opivv_check) +GEN_OPIVX_TRANS(vdivu_vx, opivx_check) +GEN_OPIVX_TRANS(vdiv_vx, opivx_check) +GEN_OPIVX_TRANS(vremu_vx, opivx_check) +GEN_OPIVX_TRANS(vrem_vx, opivx_check) + +/* Vector Widening Integer Multiply Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +GEN_OPIVV_TRANS(vmacc_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsac_vv, opivv_check) +GEN_OPIVV_TRANS(vmadd_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsub_vv, opivv_check) +GEN_OPIVX_TRANS(vmacc_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) +GEN_OPIVX_TRANS(vmadd_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) + +/* Vector Widening Integer Multiply-Add Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) + +/* Vector Integer Merge and Move Instructions */ +static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs1, false)) { + + if (s->vl_eq_vlmax) { + tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rs1), + MAXSZ(s), MAXSZ(s)); + } else { + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_gvec_2_ptr * const fns[4] = { + gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, + gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, + }; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + gen_set_label(over); + } + return true; + } + return false; +} + +typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); +static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false)) { + + TCGv s1; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + s1 = tcg_temp_new(); + gen_get_gpr(s1, a->rs1); + + if (s->vl_eq_vlmax) { + tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), s1); + } else { + TCGv_i32 desc ; + TCGv_i64 s1_i64 = tcg_temp_new_i64(); + TCGv_ptr dest = tcg_temp_new_ptr(); + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_vmv_vx * const fns[4] = { + gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, + gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, + }; + + tcg_gen_ext_tl_i64(s1_i64, s1); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); + fns[s->sew](dest, s1_i64, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_i32(desc); + tcg_temp_free_i64(s1_i64); + } + + tcg_temp_free(s1); + gen_set_label(over); + return true; + } + return false; +} + +static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false)) { + + int64_t simm = sextract64(a->rs1, 0, 5); + if (s->vl_eq_vlmax) { + tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), simm); + } else { + TCGv_i32 desc; + TCGv_i64 s1; + TCGv_ptr dest; + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_vmv_vx * const fns[4] = { + gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, + gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, + }; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + s1 = tcg_const_i64(simm); + dest = tcg_temp_new_ptr(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); + fns[s->sew](dest, s1, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_i32(desc); + tcg_temp_free_i64(s1); + gen_set_label(over); + } + return true; + } + return false; +} + +GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) +GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +GEN_OPIVV_TRANS(vsaddu_vv, opivv_check) +GEN_OPIVV_TRANS(vsadd_vv, opivv_check) +GEN_OPIVV_TRANS(vssubu_vv, opivv_check) +GEN_OPIVV_TRANS(vssub_vv, opivv_check) +GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) +GEN_OPIVX_TRANS(vsadd_vx, opivx_check) +GEN_OPIVX_TRANS(vssubu_vx, opivx_check) +GEN_OPIVX_TRANS(vssub_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) + +/* Vector Single-Width Averaging Add and Subtract */ +GEN_OPIVV_TRANS(vaadd_vv, opivv_check) +GEN_OPIVV_TRANS(vasub_vv, opivv_check) +GEN_OPIVX_TRANS(vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vasub_vx, opivx_check) +GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) + +/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ +GEN_OPIVV_TRANS(vsmul_vv, opivv_check) +GEN_OPIVX_TRANS(vsmul_vx, opivx_check) + +/* Vector Widening Saturating Scaled Multiply-Add */ +GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) + +/* Vector Single-Width Scaling Shift Instructions */ +GEN_OPIVV_TRANS(vssrl_vv, opivv_check) +GEN_OPIVV_TRANS(vssra_vv, opivv_check) +GEN_OPIVX_TRANS(vssrl_vx, opivx_check) +GEN_OPIVX_TRANS(vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check) + +/* Vector Narrowing Fixed-Point Clip Instructions */ +GEN_OPIVV_NARROW_TRANS(vnclipu_vv) +GEN_OPIVV_NARROW_TRANS(vnclip_vv) +GEN_OPIVX_NARROW_TRANS(vnclipu_vx) +GEN_OPIVX_NARROW_TRANS(vnclip_vx) +GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx) +GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) + +/* + *** Vector Float Point Arithmetic Instructions + */ +/* Vector Single-Width Floating-Point Add/Subtract Instructions */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised. + */ +static bool opfvv_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + (s->sew != 0)); +} + +/* OPFVV without GVEC IR */ +#define GEN_OPFVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} +GEN_OPFVV_TRANS(vfadd_vv, opfvv_check) +GEN_OPFVV_TRANS(vfsub_vv, opfvv_check) + +typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr, + TCGv_env, TCGv_i32); + +static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, + uint32_t data, gen_helper_opfvf *fn, DisasContext *s) +{ + TCGv_ptr dest, src2, mask; + TCGv_i32 desc; + + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + mask = tcg_temp_new_ptr(); + src2 = tcg_temp_new_ptr(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(src2); + tcg_temp_free_i32(desc); + gen_set_label(over); + return true; +} + +static bool opfvf_check(DisasContext *s, arg_rmrr *a) +{ +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (s->sew != 0)); +} + +/* OPFVF without GVEC IR */ +#define GEN_OPFVF_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_opfvf *const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + gen_set_rm(s, 7); \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + fns[s->sew - 1], s); \ + } \ + return false; \ +} + +GEN_OPFVF_TRANS(vfadd_vf, opfvf_check) +GEN_OPFVF_TRANS(vfsub_vf, opfvf_check) +GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) + +/* Vector Widening Floating-Point Add/Subtract Instructions */ +static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, + 1 << s->lmul) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +/* OPFVV with WIDEN */ +#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[2] = { \ + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) + +static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +/* OPFVF with WIDEN */ +#define GEN_OPFVF_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opfvf_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_opfvf *const fns[2] = { \ + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ + }; \ + gen_set_rm(s, 7); \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + fns[s->sew - 1], s); \ + } \ + return false; \ +} + +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) + +static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, true) && + vext_check_reg(s, a->rs1, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +/* WIDEN OPFVV with WIDEN */ +#define GEN_OPFWV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opfwv_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_4_ptr * const fns[2] = { \ + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFWV_WIDEN_TRANS(vfwadd_wv) +GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) + +static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, true) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +/* WIDEN OPFVF with WIDEN */ +#define GEN_OPFWF_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opfwf_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_opfvf *const fns[2] = { \ + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ + }; \ + gen_set_rm(s, 7); \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + fns[s->sew - 1], s); \ + } \ + return false; \ +} + +GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) +GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) + +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) +GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) +GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) +GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) + +/* Vector Widening Floating-Point Multiply */ +GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) + +/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ +GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) +GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check) +GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check) +GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check) +GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check) +GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check) +GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check) +GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check) +GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check) + +/* Vector Widening Floating-Point Fused Multiply-Add Instructions */ +GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) + +/* Vector Floating-Point Square-Root Instruction */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ +static bool opfv_check(DisasContext *s, arg_rmr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (s->sew != 0)); +} + +#define GEN_OPFV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFV_TRANS(vfsqrt_v, opfv_check) + +/* Vector Floating-Point MIN/MAX Instructions */ +GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) + +/* Vector Floating-Point Sign-Injection Instructions */ +GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check) +GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check) +GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check) +GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check) +GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check) +GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) + +/* Vector Floating-Point Compare Instructions */ +static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + vext_check_reg(s, a->rs1, false) && + (s->sew != 0) && + ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && + vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || + (s->lmul == 0))); +} + +GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) +GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) +GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) +GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) +GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) + +static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rs2, false) && + (s->sew != 0) && + (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || + (s->lmul == 0))); +} + +GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) +GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) + +/* Vector Floating-Point Classify Instruction */ +GEN_OPFV_TRANS(vfclass_v, opfv_check) + +/* Vector Floating-Point Merge Instruction */ +GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) + +static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + (s->sew != 0)) { + + if (s->vl_eq_vlmax) { + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + } else { + TCGv_ptr dest; + TCGv_i32 desc; + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_vmv_vx * const fns[3] = { + gen_helper_vmv_v_x_h, + gen_helper_vmv_v_x_w, + gen_helper_vmv_v_x_d, + }; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + dest = tcg_temp_new_ptr(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); + fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_i32(desc); + gen_set_label(over); + } + return true; + } + return false; +} + +/* Single-Width Floating-Point/Integer Type-Convert Instructions */ +GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) + +/* Widening Floating-Point/Integer Type-Convert Instructions */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ +static bool opfv_widen_check(DisasContext *s, arg_rmr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, true) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, + 1 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +#define GEN_OPFV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfv_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[2] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) + +/* Narrowing Floating-Point/Integer Type-Convert Instructions */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ +static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, true) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, + 2 << s->lmul) && + (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); +} + +#define GEN_OPFV_NARROW_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfv_narrow_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[2] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) + +/* + *** Vector Reduction Operations + */ +/* Vector Single-Width Integer Reduction Instructions */ +static bool reduction_check(DisasContext *s, arg_rmrr *a) +{ + return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); +} + +GEN_OPIVV_TRANS(vredsum_vs, reduction_check) +GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check) +GEN_OPIVV_TRANS(vredmax_vs, reduction_check) +GEN_OPIVV_TRANS(vredminu_vs, reduction_check) +GEN_OPIVV_TRANS(vredmin_vs, reduction_check) +GEN_OPIVV_TRANS(vredand_vs, reduction_check) +GEN_OPIVV_TRANS(vredor_vs, reduction_check) +GEN_OPIVV_TRANS(vredxor_vs, reduction_check) + +/* Vector Widening Integer Reduction Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) + +/* Vector Single-Width Floating-Point Reduction Instructions */ +GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) +GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) +GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) + +/* Vector Widening Floating-Point Reduction Instructions */ +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) + +/* + *** Vector Mask Operations + */ + +/* Vector Mask-Register Logical Instructions */ +#define GEN_MM_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + if (vext_check_isa_ill(s)) { \ + uint32_t data = 0; \ + gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fn); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_MM_TRANS(vmand_mm) +GEN_MM_TRANS(vmnand_mm) +GEN_MM_TRANS(vmandnot_mm) +GEN_MM_TRANS(vmxor_mm) +GEN_MM_TRANS(vmor_mm) +GEN_MM_TRANS(vmnor_mm) +GEN_MM_TRANS(vmornot_mm) +GEN_MM_TRANS(vmxnor_mm) + +/* Vector mask population count vmpopc */ +static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +{ + if (vext_check_isa_ill(s)) { + TCGv_ptr src2, mask; + TCGv dst; + TCGv_i32 desc; + uint32_t data = 0; + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + + mask = tcg_temp_new_ptr(); + src2 = tcg_temp_new_ptr(); + dst = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_set_gpr(a->rd, dst); + + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(src2); + tcg_temp_free(dst); + tcg_temp_free_i32(desc); + return true; + } + return false; +} + +/* vmfirst find-first-set mask bit */ +static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) +{ + if (vext_check_isa_ill(s)) { + TCGv_ptr src2, mask; + TCGv dst; + TCGv_i32 desc; + uint32_t data = 0; + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + + mask = tcg_temp_new_ptr(); + src2 = tcg_temp_new_ptr(); + dst = tcg_temp_new(); + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); + gen_set_gpr(a->rd, dst); + + tcg_temp_free_ptr(mask); + tcg_temp_free_ptr(src2); + tcg_temp_free(dst); + tcg_temp_free_i32(desc); + return true; + } + return false; +} + +/* vmsbf.m set-before-first mask bit */ +/* vmsif.m set-includ-first mask bit */ +/* vmsof.m set-only-first mask bit */ +#define GEN_M_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (vext_check_isa_ill(s)) { \ + uint32_t data = 0; \ + gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ + vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ + cpu_env, 0, s->vlen / 8, data, fn); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_M_TRANS(vmsbf_m) +GEN_M_TRANS(vmsif_m) +GEN_M_TRANS(vmsof_m) + +/* Vector Iota Instruction */ +static bool trans_viota_m(DisasContext *s, arg_viota_m *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && + (a->vm != 0 || a->rd != 0)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + static gen_helper_gvec_3_ptr * const fns[4] = { + gen_helper_viota_m_b, gen_helper_viota_m_h, + gen_helper_viota_m_w, gen_helper_viota_m_d, + }; + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, 0, + s->vlen / 8, data, fns[s->sew]); + gen_set_label(over); + return true; + } + return false; +} + +/* Vector Element Index Instruction */ +static bool trans_vid_v(DisasContext *s, arg_vid_v *a) +{ + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_overlap_mask(s, a->rd, a->vm, false)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + static gen_helper_gvec_2_ptr * const fns[4] = { + gen_helper_vid_v_b, gen_helper_vid_v_h, + gen_helper_vid_v_w, gen_helper_vid_v_d, + }; + tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + gen_set_label(over); + return true; + } + return false; +} + +/* + *** Vector Permutation Instructions + */ + +/* Integer Extract Instruction */ + +static void load_element(TCGv_i64 dest, TCGv_ptr base, + int ofs, int sew) +{ + switch (sew) { + case MO_8: + tcg_gen_ld8u_i64(dest, base, ofs); + break; + case MO_16: + tcg_gen_ld16u_i64(dest, base, ofs); + break; + case MO_32: + tcg_gen_ld32u_i64(dest, base, ofs); + break; + case MO_64: + tcg_gen_ld_i64(dest, base, ofs); + break; + default: + g_assert_not_reached(); + break; + } +} + +/* offset of the idx element with base regsiter r */ +static uint32_t endian_ofs(DisasContext *s, int r, int idx) +{ +#ifdef HOST_WORDS_BIGENDIAN + return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew); +#else + return vreg_ofs(s, r) + (idx << s->sew); +#endif +} + +/* adjust the index according to the endian */ +static void endian_adjust(TCGv_i32 ofs, int sew) +{ +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_xori_i32(ofs, ofs, 7 >> sew); +#endif +} + +/* Load idx >= VLMAX ? 0 : vreg[idx] */ +static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, + int vreg, TCGv idx, int vlmax) +{ + TCGv_i32 ofs = tcg_temp_new_i32(); + TCGv_ptr base = tcg_temp_new_ptr(); + TCGv_i64 t_idx = tcg_temp_new_i64(); + TCGv_i64 t_vlmax, t_zero; + + /* + * Mask the index to the length so that we do + * not produce an out-of-range load. + */ + tcg_gen_trunc_tl_i32(ofs, idx); + tcg_gen_andi_i32(ofs, ofs, vlmax - 1); + + /* Convert the index to an offset. */ + endian_adjust(ofs, s->sew); + tcg_gen_shli_i32(ofs, ofs, s->sew); + + /* Convert the index to a pointer. */ + tcg_gen_ext_i32_ptr(base, ofs); + tcg_gen_add_ptr(base, base, cpu_env); + + /* Perform the load. */ + load_element(dest, base, + vreg_ofs(s, vreg), s->sew); + tcg_temp_free_ptr(base); + tcg_temp_free_i32(ofs); + + /* Flush out-of-range indexing to zero. */ + t_vlmax = tcg_const_i64(vlmax); + t_zero = tcg_const_i64(0); + tcg_gen_extu_tl_i64(t_idx, idx); + + tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx, + t_vlmax, dest, t_zero); + + tcg_temp_free_i64(t_vlmax); + tcg_temp_free_i64(t_zero); + tcg_temp_free_i64(t_idx); +} + +static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, + int vreg, int idx) +{ + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); +} + +static bool trans_vext_x_v(DisasContext *s, arg_r *a) +{ + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv dest = tcg_temp_new(); + + if (a->rs1 == 0) { + /* Special case vmv.x.s rd, vs2. */ + vec_element_loadi(s, tmp, a->rs2, 0); + } else { + /* This instruction ignores LMUL and vector register groups */ + int vlmax = s->vlen >> (3 + s->sew); + vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); + } + tcg_gen_trunc_i64_tl(dest, tmp); + gen_set_gpr(a->rd, dest); + + tcg_temp_free(dest); + tcg_temp_free_i64(tmp); + return true; +} + +/* Integer Scalar Move Instruction */ + +static void store_element(TCGv_i64 val, TCGv_ptr base, + int ofs, int sew) +{ + switch (sew) { + case MO_8: + tcg_gen_st8_i64(val, base, ofs); + break; + case MO_16: + tcg_gen_st16_i64(val, base, ofs); + break; + case MO_32: + tcg_gen_st32_i64(val, base, ofs); + break; + case MO_64: + tcg_gen_st_i64(val, base, ofs); + break; + default: + g_assert_not_reached(); + break; + } +} + +/* + * Store vreg[idx] = val. + * The index must be in range of VLMAX. + */ +static void vec_element_storei(DisasContext *s, int vreg, + int idx, TCGv_i64 val) +{ + store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); +} + +/* vmv.s.x vd, rs1 # vd[0] = rs1 */ +static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) +{ + if (vext_check_isa_ill(s)) { + /* This instruction ignores LMUL and vector register groups */ + int maxsz = s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); + if (a->rs1 == 0) { + goto done; + } + + t1 = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); + tcg_temp_free_i64(t1); + done: + gen_set_label(over); + return true; + } + return false; +} + +/* Floating-Point Scalar Move Instructions */ +static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) +{ + if (!s->vill && has_ext(s, RVF) && + (s->mstatus_fs != 0) && (s->sew != 0)) { + unsigned int len = 8 << s->sew; + + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); + if (len < 64) { + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + MAKE_64BIT_MASK(len, 64 - len)); + } + + mark_fs_dirty(s); + return true; + } + return false; +} + +/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ +static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) +{ + if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { + TCGv_i64 t1; + /* The instructions ignore LMUL and vector register group. */ + uint32_t vlmax = s->vlen >> 3; + + /* if vl == 0, skip vector register write back */ + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + /* zeroed all elements */ + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); + + /* NaN-box f[rs1] as necessary for SEW */ + t1 = tcg_temp_new_i64(); + if (s->sew == MO_64 && !has_ext(s, RVD)) { + tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); + } else { + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + } + vec_element_storei(s, a->rd, 0, t1); + tcg_temp_free_i64(t1); + gen_set_label(over); + return true; + } + return false; +} + +/* Vector Slide Instructions */ +static bool slideup_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (a->rd != a->rs2)); +} + +GEN_OPIVX_TRANS(vslideup_vx, slideup_check) +GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) +GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) + +GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) +GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) +GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) + +/* Vector Register Gather Instruction */ +static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs1, false) && + vext_check_reg(s, a->rs2, false) && + (a->rd != a->rs2) && (a->rd != a->rs1)); +} + +GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) + +static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, true) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (a->rd != a->rs2)); +} + +/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ +static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) +{ + if (!vrgather_vx_check(s, a)) { + return false; + } + + if (a->vm && s->vl_eq_vlmax) { + int vlmax = s->vlen / s->mlen; + TCGv_i64 dest = tcg_temp_new_i64(); + + if (a->rs1 == 0) { + vec_element_loadi(s, dest, a->rs2, 0); + } else { + vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); + } + + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), dest); + tcg_temp_free_i64(dest); + } else { + static gen_helper_opivx * const fns[4] = { + gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, + gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d + }; + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); + } + return true; +} + +/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */ +static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) +{ + if (!vrgather_vx_check(s, a)) { + return false; + } + + if (a->vm && s->vl_eq_vlmax) { + if (a->rs1 >= s->vlen / s->mlen) { + tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), 0); + } else { + tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd), + endian_ofs(s, a->rs2, a->rs1), + MAXSZ(s), MAXSZ(s)); + } + } else { + static gen_helper_opivx * const fns[4] = { + gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, + gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d + }; + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1); + } + return true; +} + +/* Vector Compress Instruction */ +static bool vcompress_vm_check(DisasContext *s, arg_r *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && + (a->rd != a->rs2)); +} + +static bool trans_vcompress_vm(DisasContext *s, arg_r *a) +{ + if (vcompress_vm_check(s, a)) { + uint32_t data = 0; + static gen_helper_gvec_4_ptr * const fns[4] = { + gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h, + gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d, + }; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), + cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + gen_set_label(over); + return true; + } + return false; +} diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c deleted file mode 100644 index 887c6b8883..0000000000 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ /dev/null @@ -1,2902 +0,0 @@ -/* - * RISC-V translation routines for the RVV Standard Extension. - * - * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ -#include "tcg/tcg-op-gvec.h" -#include "tcg/tcg-gvec-desc.h" -#include "internals.h" - -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) -{ - TCGv s1, s2, dst; - - if (!has_ext(ctx, RVV)) { - return false; - } - - s2 = tcg_temp_new(); - dst = tcg_temp_new(); - - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ - s1 = tcg_const_tl(RV_VLEN_MAX); - } else { - s1 = tcg_temp_new(); - gen_get_gpr(s1, a->rs1); - } - gen_get_gpr(s2, a->rs2); - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - lookup_and_goto_ptr(ctx); - ctx->base.is_jmp = DISAS_NORETURN; - - tcg_temp_free(s1); - tcg_temp_free(s2); - tcg_temp_free(dst); - return true; -} - -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) -{ - TCGv s1, s2, dst; - - if (!has_ext(ctx, RVV)) { - return false; - } - - s2 = tcg_const_tl(a->zimm); - dst = tcg_temp_new(); - - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ - s1 = tcg_const_tl(RV_VLEN_MAX); - } else { - s1 = tcg_temp_new(); - gen_get_gpr(s1, a->rs1); - } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp = DISAS_NORETURN; - - tcg_temp_free(s1); - tcg_temp_free(s2); - tcg_temp_free(dst); - return true; -} - -/* vector register offset from env */ -static uint32_t vreg_ofs(DisasContext *s, int reg) -{ - return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8; -} - -/* check functions */ - -/* - * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. - * So RVV is also be checked in this function. - */ -static bool vext_check_isa_ill(DisasContext *s) -{ - return !s->vill; -} - -/* - * There are two rules check here. - * - * 1. Vector register numbers are multiples of LMUL. (Section 3.2) - * - * 2. For all widening instructions, the destination LMUL value must also be - * a supported LMUL value. (Section 11.2) - */ -static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) -{ - /* - * The destination vector register group results are arranged as if both - * SEW and LMUL were at twice their current settings. (Section 11.2). - */ - int legal = widen ? 2 << s->lmul : 1 << s->lmul; - - return !((s->lmul == 0x3 && widen) || (reg % legal)); -} - -/* - * There are two rules check here. - * - * 1. The destination vector register group for a masked vector instruction can - * only overlap the source mask register (v0) when LMUL=1. (Section 5.3) - * - * 2. In widen instructions and some other insturctions, like vslideup.vx, - * there is no need to check whether LMUL=1. - */ -static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm, - bool force) -{ - return (vm != 0 || vd != 0) || (!force && (s->lmul == 0)); -} - -/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */ -static bool vext_check_nf(DisasContext *s, uint32_t nf) -{ - return (1 << s->lmul) * nf <= 8; -} - -/* - * The destination vector register group cannot overlap a source vector register - * group of a different element width. (Section 11.2) - */ -static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen) -{ - return ((rd >= rs + slen) || (rs >= rd + dlen)); -} -/* common translation macro */ -#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ -{ \ - if (CHECK(s, a)) { \ - return OP(s, a, SEQ); \ - } \ - return false; \ -} - -/* - *** unit stride load and store - */ -typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, - TCGv_env, TCGv_i32); - -static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) -{ - TCGv_ptr dest, mask; - TCGv base; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - base = tcg_temp_new(); - - /* - * As simd_desc supports at most 256 bytes, and in this implementation, - * the max vector group length is 2048 bytes. So split it into two parts. - * - * The first part is vlen in bytes, encoded in maxsz of simd_desc. - * The second part is lmul, encoded in data of simd_desc. - */ - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - gen_get_gpr(base, rs1); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free(base); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][7][4] = { - /* masked unit stride load */ - { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask, - gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask }, - { NULL, gen_helper_vlh_v_h_mask, - gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask }, - { NULL, NULL, - gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask }, - { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask, - gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask }, - { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask, - gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask }, - { NULL, gen_helper_vlhu_v_h_mask, - gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask }, - { NULL, NULL, - gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } }, - /* unmasked unit stride load */ - { { gen_helper_vlb_v_b, gen_helper_vlb_v_h, - gen_helper_vlb_v_w, gen_helper_vlb_v_d }, - { NULL, gen_helper_vlh_v_h, - gen_helper_vlh_v_w, gen_helper_vlh_v_d }, - { NULL, NULL, - gen_helper_vlw_v_w, gen_helper_vlw_v_d }, - { gen_helper_vle_v_b, gen_helper_vle_v_h, - gen_helper_vle_v_w, gen_helper_vle_v_d }, - { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h, - gen_helper_vlbu_v_w, gen_helper_vlbu_v_d }, - { NULL, gen_helper_vlhu_v_h, - gen_helper_vlhu_v_w, gen_helper_vlhu_v_d }, - { NULL, NULL, - gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } } - }; - - fn = fns[a->vm][seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); -} - -static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); -} - -GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check) - -static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][4][4] = { - /* masked unit stride load and store */ - { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask, - gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask }, - { NULL, gen_helper_vsh_v_h_mask, - gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask }, - { NULL, NULL, - gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask }, - { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask, - gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } }, - /* unmasked unit stride store */ - { { gen_helper_vsb_v_b, gen_helper_vsb_v_h, - gen_helper_vsb_v_w, gen_helper_vsb_v_d }, - { NULL, gen_helper_vsh_v_h, - gen_helper_vsh_v_w, gen_helper_vsh_v_d }, - { NULL, NULL, - gen_helper_vsw_v_w, gen_helper_vsw_v_d }, - { gen_helper_vse_v_b, gen_helper_vse_v_h, - gen_helper_vse_v_w, gen_helper_vse_v_d } } - }; - - fn = fns[a->vm][seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); -} - -static bool st_us_check(DisasContext *s, arg_r2nfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); -} - -GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check) - -/* - *** stride load and store - */ -typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, - TCGv, TCGv_env, TCGv_i32); - -static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, - uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) -{ - TCGv_ptr dest, mask; - TCGv base, stride; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - base = tcg_temp_new(); - stride = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - gen_get_gpr(base, rs1); - gen_get_gpr(stride, rs2); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, stride, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free(base); - tcg_temp_free(stride); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[7][4] = { - { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h, - gen_helper_vlsb_v_w, gen_helper_vlsb_v_d }, - { NULL, gen_helper_vlsh_v_h, - gen_helper_vlsh_v_w, gen_helper_vlsh_v_d }, - { NULL, NULL, - gen_helper_vlsw_v_w, gen_helper_vlsw_v_d }, - { gen_helper_vlse_v_b, gen_helper_vlse_v_h, - gen_helper_vlse_v_w, gen_helper_vlse_v_d }, - { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h, - gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d }, - { NULL, gen_helper_vlshu_v_h, - gen_helper_vlshu_v_w, gen_helper_vlshu_v_d }, - { NULL, NULL, - gen_helper_vlswu_v_w, gen_helper_vlswu_v_d }, - }; - - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} - -static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); -} - -GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check) - -static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[4][4] = { - /* masked stride store */ - { gen_helper_vssb_v_b, gen_helper_vssb_v_h, - gen_helper_vssb_v_w, gen_helper_vssb_v_d }, - { NULL, gen_helper_vssh_v_h, - gen_helper_vssh_v_w, gen_helper_vssh_v_d }, - { NULL, NULL, - gen_helper_vssw_v_w, gen_helper_vssw_v_d }, - { gen_helper_vsse_v_b, gen_helper_vsse_v_h, - gen_helper_vsse_v_w, gen_helper_vsse_v_d } - }; - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} - -static bool st_stride_check(DisasContext *s, arg_rnfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); -} - -GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) - -/* - *** index load and store - */ -typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, - TCGv_ptr, TCGv_env, TCGv_i32); - -static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, - uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s) -{ - TCGv_ptr dest, mask, index; - TCGv base; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - index = tcg_temp_new_ptr(); - base = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - gen_get_gpr(base, rs1); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, index, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(index); - tcg_temp_free(base); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_index *fn; - static gen_helper_ldst_index * const fns[7][4] = { - { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h, - gen_helper_vlxb_v_w, gen_helper_vlxb_v_d }, - { NULL, gen_helper_vlxh_v_h, - gen_helper_vlxh_v_w, gen_helper_vlxh_v_d }, - { NULL, NULL, - gen_helper_vlxw_v_w, gen_helper_vlxw_v_d }, - { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h, - gen_helper_vlxe_v_w, gen_helper_vlxe_v_d }, - { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h, - gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d }, - { NULL, gen_helper_vlxhu_v_h, - gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d }, - { NULL, NULL, - gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d }, - }; - - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} - -/* - * For vector indexed segment loads, the destination vector register - * groups cannot overlap the source vector register group (specified by - * `vs2`), else an illegal instruction exception is raised. - */ -static bool ld_index_check(DisasContext *s, arg_rnfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf) && - ((a->nf == 1) || - vext_check_overlap_group(a->rd, a->nf << s->lmul, - a->rs2, 1 << s->lmul))); -} - -GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check) - -static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_index *fn; - static gen_helper_ldst_index * const fns[4][4] = { - { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h, - gen_helper_vsxb_v_w, gen_helper_vsxb_v_d }, - { NULL, gen_helper_vsxh_v_h, - gen_helper_vsxh_v_w, gen_helper_vsxh_v_d }, - { NULL, NULL, - gen_helper_vsxw_v_w, gen_helper_vsxw_v_d }, - { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h, - gen_helper_vsxe_v_w, gen_helper_vsxe_v_d } - }; - - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} - -static bool st_index_check(DisasContext *s, arg_rnfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); -} - -GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check) - -/* - *** unit stride fault-only-first load - */ -static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) -{ - TCGv_ptr dest, mask; - TCGv base; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - base = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - gen_get_gpr(base, rs1); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free(base); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[7][4] = { - { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, - gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, - { NULL, gen_helper_vlhff_v_h, - gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, - { NULL, NULL, - gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, - { gen_helper_vleff_v_b, gen_helper_vleff_v_h, - gen_helper_vleff_v_w, gen_helper_vleff_v_d }, - { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, - gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, - { NULL, gen_helper_vlhuff_v_h, - gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, - { NULL, NULL, - gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } - }; - - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldff_trans(a->rd, a->rs1, data, fn, s); -} - -GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) - -/* - *** vector atomic operation - */ -typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, - TCGv_env, TCGv_i32); - -static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, - uint32_t data, gen_helper_amo *fn, DisasContext *s) -{ - TCGv_ptr dest, mask, index; - TCGv base; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - index = tcg_temp_new_ptr(); - base = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - gen_get_gpr(base, rs1); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, index, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(index); - tcg_temp_free(base); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_amo *fn; - static gen_helper_amo *const fnsw[9] = { - /* no atomic operation */ - gen_helper_vamoswapw_v_w, - gen_helper_vamoaddw_v_w, - gen_helper_vamoxorw_v_w, - gen_helper_vamoandw_v_w, - gen_helper_vamoorw_v_w, - gen_helper_vamominw_v_w, - gen_helper_vamomaxw_v_w, - gen_helper_vamominuw_v_w, - gen_helper_vamomaxuw_v_w - }; -#ifdef TARGET_RISCV64 - static gen_helper_amo *const fnsd[18] = { - gen_helper_vamoswapw_v_d, - gen_helper_vamoaddw_v_d, - gen_helper_vamoxorw_v_d, - gen_helper_vamoandw_v_d, - gen_helper_vamoorw_v_d, - gen_helper_vamominw_v_d, - gen_helper_vamomaxw_v_d, - gen_helper_vamominuw_v_d, - gen_helper_vamomaxuw_v_d, - gen_helper_vamoswapd_v_d, - gen_helper_vamoaddd_v_d, - gen_helper_vamoxord_v_d, - gen_helper_vamoandd_v_d, - gen_helper_vamoord_v_d, - gen_helper_vamomind_v_d, - gen_helper_vamomaxd_v_d, - gen_helper_vamominud_v_d, - gen_helper_vamomaxud_v_d - }; -#endif - - if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp = DISAS_NORETURN; - return true; - } else { - if (s->sew == 3) { -#ifdef TARGET_RISCV64 - fn = fnsd[seq]; -#else - /* Check done in amo_check(). */ - g_assert_not_reached(); -#endif - } else { - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - } - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, WD, a->wd); - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} -/* - * There are two rules check here. - * - * 1. SEW must be at least as wide as the AMO memory element size. - * - * 2. If SEW is greater than XLEN, an illegal instruction exception is raised. - */ -static bool amo_check(DisasContext *s, arg_rwdvm* a) -{ - return (!s->vill && has_ext(s, RVA) && - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && - ((1 << s->sew) >= 4)); -} - -GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -#ifdef TARGET_RISCV64 -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check) -#endif - -/* - *** Vector Integer Arithmetic Instructions - */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) - -static bool opivv_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false)); -} - -typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, - uint32_t, uint32_t, uint32_t); - -static inline bool -do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, - gen_helper_gvec_4_ptr *fn) -{ - TCGLabel *over = gen_new_label(); - if (!opivv_check(s, a)) { - return false; - } - - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - if (a->vm && s->vl_eq_vlmax) { - gvec_fn(s->sew, vreg_ofs(s, a->rd), - vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), - MAXSZ(s), MAXSZ(s)); - } else { - uint32_t data = 0; - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, 0, s->vlen / 8, data, fn); - } - gen_set_label(over); - return true; -} - -/* OPIVV with GVEC IR */ -#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_gvec_4_ptr * const fns[4] = { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ -} - -GEN_OPIVV_GVEC_TRANS(vadd_vv, add) -GEN_OPIVV_GVEC_TRANS(vsub_vv, sub) - -typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, - TCGv_env, TCGv_i32); - -static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, - gen_helper_opivx *fn, DisasContext *s) -{ - TCGv_ptr dest, src2, mask; - TCGv src1; - TCGv_i32 desc; - uint32_t data = 0; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - src2 = tcg_temp_new_ptr(); - src1 = tcg_temp_new(); - gen_get_gpr(src1, rs1); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, src1, src2, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free(src1); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool opivx_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false)); -} - -typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, - uint32_t, uint32_t); - -static inline bool -do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, - gen_helper_opivx *fn) -{ - if (!opivx_check(s, a)) { - return false; - } - - if (a->vm && s->vl_eq_vlmax) { - TCGv_i64 src1 = tcg_temp_new_i64(); - TCGv tmp = tcg_temp_new(); - - gen_get_gpr(tmp, a->rs1); - tcg_gen_ext_tl_i64(src1, tmp); - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - src1, MAXSZ(s), MAXSZ(s)); - - tcg_temp_free_i64(src1); - tcg_temp_free(tmp); - return true; - } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); -} - -/* OPIVX with GVEC IR */ -#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[4] = { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ -} - -GEN_OPIVX_GVEC_TRANS(vadd_vx, adds) -GEN_OPIVX_GVEC_TRANS(vsub_vx, subs) - -static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_vec_sub8_i64(d, b, a); -} - -static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_vec_sub16_i64(d, b, a); -} - -static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_sub_i32(ret, arg2, arg1); -} - -static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_sub_i64(ret, arg2, arg1); -} - -static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - tcg_gen_sub_vec(vece, r, b, a); -} - -static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) -{ - static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 }; - static const GVecGen2s rsub_op[4] = { - { .fni8 = gen_vec_rsub8_i64, - .fniv = gen_rsub_vec, - .fno = gen_helper_vec_rsubs8, - .opt_opc = vecop_list, - .vece = MO_8 }, - { .fni8 = gen_vec_rsub16_i64, - .fniv = gen_rsub_vec, - .fno = gen_helper_vec_rsubs16, - .opt_opc = vecop_list, - .vece = MO_16 }, - { .fni4 = gen_rsub_i32, - .fniv = gen_rsub_vec, - .fno = gen_helper_vec_rsubs32, - .opt_opc = vecop_list, - .vece = MO_32 }, - { .fni8 = gen_rsub_i64, - .fniv = gen_rsub_vec, - .fno = gen_helper_vec_rsubs64, - .opt_opc = vecop_list, - .prefer_i64 = TCG_TARGET_REG_BITS == 64, - .vece = MO_64 }, - }; - - tcg_debug_assert(vece <= MO_64); - tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]); -} - -GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) - -static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, - gen_helper_opivx *fn, DisasContext *s, int zx) -{ - TCGv_ptr dest, src2, mask; - TCGv src1; - TCGv_i32 desc; - uint32_t data = 0; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - src2 = tcg_temp_new_ptr(); - if (zx) { - src1 = tcg_const_tl(imm); - } else { - src1 = tcg_const_tl(sextract64(imm, 0, 5)); - } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, src1, src2, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free(src1); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, - uint32_t, uint32_t); - -static inline bool -do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, - gen_helper_opivx *fn, int zx) -{ - if (!opivx_check(s, a)) { - return false; - } - - if (a->vm && s->vl_eq_vlmax) { - if (zx) { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } else { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } - } else { - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); - } - return true; -} - -/* OPIVI with GVEC IR */ -#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[4] = { \ - gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ - gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ - }; \ - return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ - fns[s->sew], ZX); \ -} - -GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) - -static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz) -{ - TCGv_i64 tmp = tcg_const_i64(c); - tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); - tcg_temp_free_i64(tmp); -} - -GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) - -/* Vector Widening Integer Add/Subtract */ - -/* OPIVV with WIDEN */ -static bool opivv_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, - gen_helper_gvec_4_ptr *fn, - bool (*checkfn)(DisasContext *, arg_rmrr *)) -{ - if (checkfn(s, a)) { - uint32_t data = 0; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs1), - vreg_ofs(s, a->rs2), - cpu_env, 0, s->vlen / 8, - data, fn); - gen_set_label(over); - return true; - } - return false; -} - -#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_gvec_4_ptr * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opivv_widen(s, a, fns[s->sew], CHECK); \ -} - -GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check) - -/* OPIVX with WIDEN */ -static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, - gen_helper_opivx *fn) -{ - if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); - } - return false; -} - -#define GEN_OPIVX_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opivx_widen(s, a, fns[s->sew]); \ -} - -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) -GEN_OPIVX_WIDEN_TRANS(vwadd_vx) -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsub_vx) - -/* WIDEN OPIVV with WIDEN */ -static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, - gen_helper_gvec_4_ptr *fn) -{ - if (opiwv_widen_check(s, a)) { - uint32_t data = 0; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs1), - vreg_ofs(s, a->rs2), - cpu_env, 0, s->vlen / 8, data, fn); - gen_set_label(over); - return true; - } - return false; -} - -#define GEN_OPIWV_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_gvec_4_ptr * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opiwv_widen(s, a, fns[s->sew]); \ -} - -GEN_OPIWV_WIDEN_TRANS(vwaddu_wv) -GEN_OPIWV_WIDEN_TRANS(vwadd_wv) -GEN_OPIWV_WIDEN_TRANS(vwsubu_wv) -GEN_OPIWV_WIDEN_TRANS(vwsub_wv) - -/* WIDEN OPIVX with WIDEN */ -static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a, - gen_helper_opivx *fn) -{ - if (opiwx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); - } - return false; -} - -#define GEN_OPIWX_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opiwx_widen(s, a, fns[s->sew]); \ -} - -GEN_OPIWX_WIDEN_TRANS(vwaddu_wx) -GEN_OPIWX_WIDEN_TRANS(vwadd_wx) -GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) -GEN_OPIWX_WIDEN_TRANS(vwsub_wx) - -/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ -/* OPIVV without GVEC IR */ -#define GEN_OPIVV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_4_ptr * const fns[4] = { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over = gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -/* - * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.3) - */ -static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((a->rd != 0) || (s->lmul == 0))); -} - -GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check) -GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check) - -/* - * For vmadc and vmsbc, an illegal instruction exception is raised if the - * destination vector register overlaps a source vector register group. - */ -static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); -} - -GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) -GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check) - -static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((a->rd != 0) || (s->lmul == 0))); -} - -/* OPIVX without GVEC IR */ -#define GEN_OPIVX_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - static gen_helper_opivx * const fns[4] = { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ - } \ - return false; \ -} - -GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check) -GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check) - -static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); -} - -GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) -GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) - -/* OPIVI without GVEC IR */ -#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - static gen_helper_opivx * const fns[4] = { \ - gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ - gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ - }; \ - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ - } \ - return false; \ -} - -GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) - -/* Vector Bitwise Logical Instructions */ -GEN_OPIVV_GVEC_TRANS(vand_vv, and) -GEN_OPIVV_GVEC_TRANS(vor_vv, or) -GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) -GEN_OPIVX_GVEC_TRANS(vand_vx, ands) -GEN_OPIVX_GVEC_TRANS(vor_vx, ors) -GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) -GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) -GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) -GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) - -/* Vector Single-Width Bit Shift Instructions */ -GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv) -GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv) -GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv) - -typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32, - uint32_t, uint32_t); - -static inline bool -do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, - gen_helper_opivx *fn) -{ - if (!opivx_check(s, a)) { - return false; - } - - if (a->vm && s->vl_eq_vlmax) { - TCGv_i32 src1 = tcg_temp_new_i32(); - TCGv tmp = tcg_temp_new(); - - gen_get_gpr(tmp, a->rs1); - tcg_gen_trunc_tl_i32(src1, tmp); - tcg_gen_extract_i32(src1, src1, 0, s->sew + 3); - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - src1, MAXSZ(s), MAXSZ(s)); - - tcg_temp_free_i32(src1); - tcg_temp_free(tmp); - return true; - } - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); -} - -#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[4] = { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - \ - return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ -} - -GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) -GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) -GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) - -GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) - -/* Vector Narrowing Integer Right Shift Instructions */ -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -/* OPIVV with NARROW */ -#define GEN_OPIVV_NARROW_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opivv_narrow_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_4_ptr * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - }; \ - TCGLabel *over = gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} -GEN_OPIVV_NARROW_TRANS(vnsra_vv) -GEN_OPIVV_NARROW_TRANS(vnsrl_vv) - -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); -} - -/* OPIVX with NARROW */ -#define GEN_OPIVX_NARROW_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opivx_narrow_check(s, a)) { \ - static gen_helper_opivx * const fns[3] = { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - }; \ - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ - } \ - return false; \ -} - -GEN_OPIVX_NARROW_TRANS(vnsra_vx) -GEN_OPIVX_NARROW_TRANS(vnsrl_vx) - -/* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opivx_narrow_check(s, a)) { \ - static gen_helper_opivx * const fns[3] = { \ - gen_helper_##OPIVX##_b, \ - gen_helper_##OPIVX##_h, \ - gen_helper_##OPIVX##_w, \ - }; \ - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ - } \ - return false; \ -} - -GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) - -/* Vector Integer Comparison Instructions */ -/* - * For all comparison instructions, an illegal instruction exception is raised - * if the destination vector register overlaps a source vector register group - * and LMUL > 1. - */ -static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); -} -GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) -GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check) -GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check) -GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check) -GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check) -GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check) - -static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); -} - -GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check) -GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) - -GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) - -/* Vector Integer Min/Max Instructions */ -GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) -GEN_OPIVV_GVEC_TRANS(vmin_vv, smin) -GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax) -GEN_OPIVV_GVEC_TRANS(vmax_vv, smax) -GEN_OPIVX_TRANS(vminu_vx, opivx_check) -GEN_OPIVX_TRANS(vmin_vx, opivx_check) -GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) -GEN_OPIVX_TRANS(vmax_vx, opivx_check) - -/* Vector Single-Width Integer Multiply Instructions */ -GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) -GEN_OPIVV_TRANS(vmulh_vv, opivv_check) -GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) -GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) -GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) -GEN_OPIVX_TRANS(vmulh_vx, opivx_check) -GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) -GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) - -/* Vector Integer Divide Instructions */ -GEN_OPIVV_TRANS(vdivu_vv, opivv_check) -GEN_OPIVV_TRANS(vdiv_vv, opivv_check) -GEN_OPIVV_TRANS(vremu_vv, opivv_check) -GEN_OPIVV_TRANS(vrem_vv, opivv_check) -GEN_OPIVX_TRANS(vdivu_vx, opivx_check) -GEN_OPIVX_TRANS(vdiv_vx, opivx_check) -GEN_OPIVX_TRANS(vremu_vx, opivx_check) -GEN_OPIVX_TRANS(vrem_vx, opivx_check) - -/* Vector Widening Integer Multiply Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmul_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) - -/* Vector Single-Width Integer Multiply-Add Instructions */ -GEN_OPIVV_TRANS(vmacc_vv, opivv_check) -GEN_OPIVV_TRANS(vnmsac_vv, opivv_check) -GEN_OPIVV_TRANS(vmadd_vv, opivv_check) -GEN_OPIVV_TRANS(vnmsub_vv, opivv_check) -GEN_OPIVX_TRANS(vmacc_vx, opivx_check) -GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) -GEN_OPIVX_TRANS(vmadd_vx, opivx_check) -GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) - -/* Vector Widening Integer Multiply-Add Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) - -/* Vector Integer Merge and Move Instructions */ -static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false)) { - - if (s->vl_eq_vlmax) { - tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), - vreg_ofs(s, a->rs1), - MAXSZ(s), MAXSZ(s)); - } else { - uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); - static gen_helper_gvec_2_ptr * const fns[4] = { - gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, - gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, - }; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, 0, s->vlen / 8, data, fns[s->sew]); - gen_set_label(over); - } - return true; - } - return false; -} - -typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); -static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - - TCGv s1; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - s1 = tcg_temp_new(); - gen_get_gpr(s1, a->rs1); - - if (s->vl_eq_vlmax) { - tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), s1); - } else { - TCGv_i32 desc ; - TCGv_i64 s1_i64 = tcg_temp_new_i64(); - TCGv_ptr dest = tcg_temp_new_ptr(); - uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); - static gen_helper_vmv_vx * const fns[4] = { - gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, - gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, - }; - - tcg_gen_ext_tl_i64(s1_i64, s1); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew](dest, s1_i64, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); - tcg_temp_free_i64(s1_i64); - } - - tcg_temp_free(s1); - gen_set_label(over); - return true; - } - return false; -} - -static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - - int64_t simm = sextract64(a->rs1, 0, 5); - if (s->vl_eq_vlmax) { - tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), simm); - } else { - TCGv_i32 desc; - TCGv_i64 s1; - TCGv_ptr dest; - uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); - static gen_helper_vmv_vx * const fns[4] = { - gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, - gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, - }; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - s1 = tcg_const_i64(simm); - dest = tcg_temp_new_ptr(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew](dest, s1, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); - tcg_temp_free_i64(s1); - gen_set_label(over); - } - return true; - } - return false; -} - -GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) -GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) - -/* - *** Vector Fixed-Point Arithmetic Instructions - */ - -/* Vector Single-Width Saturating Add and Subtract */ -GEN_OPIVV_TRANS(vsaddu_vv, opivv_check) -GEN_OPIVV_TRANS(vsadd_vv, opivv_check) -GEN_OPIVV_TRANS(vssubu_vv, opivv_check) -GEN_OPIVV_TRANS(vssub_vv, opivv_check) -GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) -GEN_OPIVX_TRANS(vsadd_vx, opivx_check) -GEN_OPIVX_TRANS(vssubu_vx, opivx_check) -GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) -GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) - -/* Vector Single-Width Averaging Add and Subtract */ -GEN_OPIVV_TRANS(vaadd_vv, opivv_check) -GEN_OPIVV_TRANS(vasub_vv, opivv_check) -GEN_OPIVX_TRANS(vaadd_vx, opivx_check) -GEN_OPIVX_TRANS(vasub_vx, opivx_check) -GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) - -/* Vector Single-Width Fractional Multiply with Rounding and Saturation */ -GEN_OPIVV_TRANS(vsmul_vv, opivv_check) -GEN_OPIVX_TRANS(vsmul_vx, opivx_check) - -/* Vector Widening Saturating Scaled Multiply-Add */ -GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) - -/* Vector Single-Width Scaling Shift Instructions */ -GEN_OPIVV_TRANS(vssrl_vv, opivv_check) -GEN_OPIVV_TRANS(vssra_vv, opivv_check) -GEN_OPIVX_TRANS(vssrl_vx, opivx_check) -GEN_OPIVX_TRANS(vssra_vx, opivx_check) -GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check) - -/* Vector Narrowing Fixed-Point Clip Instructions */ -GEN_OPIVV_NARROW_TRANS(vnclipu_vv) -GEN_OPIVV_NARROW_TRANS(vnclip_vv) -GEN_OPIVX_NARROW_TRANS(vnclipu_vx) -GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) - -/* - *** Vector Float Point Arithmetic Instructions - */ -/* Vector Single-Width Floating-Point Add/Subtract Instructions */ - -/* - * If the current SEW does not correspond to a supported IEEE floating-point - * type, an illegal instruction exception is raised. - */ -static bool opfvv_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0)); -} - -/* OPFVV without GVEC IR */ -#define GEN_OPFVV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_4_ptr * const fns[3] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} -GEN_OPFVV_TRANS(vfadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsub_vv, opfvv_check) - -typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr, - TCGv_env, TCGv_i32); - -static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, - uint32_t data, gen_helper_opfvf *fn, DisasContext *s) -{ - TCGv_ptr dest, src2, mask; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - src2 = tcg_temp_new_ptr(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free_i32(desc); - gen_set_label(over); - return true; -} - -static bool opfvf_check(DisasContext *s, arg_rmrr *a) -{ -/* - * If the current SEW does not correspond to a supported IEEE floating-point - * type, an illegal instruction exception is raised - */ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); -} - -/* OPFVF without GVEC IR */ -#define GEN_OPFVF_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_opfvf *const fns[3] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFVF_TRANS(vfadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsub_vf, opfvf_check) -GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) - -/* Vector Widening Floating-Point Add/Subtract Instructions */ -static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -/* OPFVV with WIDEN */ -#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_4_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) - -static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -/* OPFVF with WIDEN */ -#define GEN_OPFVF_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opfvf_widen_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_opfvf *const fns[2] = { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) - -static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -/* WIDEN OPFVV with WIDEN */ -#define GEN_OPFWV_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opfwv_widen_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_4_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFWV_WIDEN_TRANS(vfwadd_wv) -GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) - -static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -/* WIDEN OPFVF with WIDEN */ -#define GEN_OPFWF_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opfwf_widen_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_opfvf *const fns[2] = { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) -GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) - -/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ -GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) -GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) -GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) -GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) - -/* Vector Widening Floating-Point Multiply */ -GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) - -/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ -GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check) - -/* Vector Widening Floating-Point Fused Multiply-Add Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) - -/* Vector Floating-Point Square-Root Instruction */ - -/* - * If the current SEW does not correspond to a supported IEEE floating-point - * type, an illegal instruction exception is raised - */ -static bool opfv_check(DisasContext *s, arg_rmr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); -} - -#define GEN_OPFV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_3_ptr * const fns[3] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFV_TRANS(vfsqrt_v, opfv_check) - -/* Vector Floating-Point MIN/MAX Instructions */ -GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) - -/* Vector Floating-Point Sign-Injection Instructions */ -GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check) -GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) - -/* Vector Floating-Point Compare Instructions */ -static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); -} - -GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) - -static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); -} - -GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) - -/* Vector Floating-Point Classify Instruction */ -GEN_OPFV_TRANS(vfclass_v, opfv_check) - -/* Vector Floating-Point Merge Instruction */ -GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) - -static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - (s->sew != 0)) { - - if (s->vl_eq_vlmax) { - tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); - } else { - TCGv_ptr dest; - TCGv_i32 desc; - uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); - static gen_helper_vmv_vx * const fns[3] = { - gen_helper_vmv_v_x_h, - gen_helper_vmv_v_x_w, - gen_helper_vmv_v_x_d, - }; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_i32(desc); - gen_set_label(over); - } - return true; - } - return false; -} - -/* Single-Width Floating-Point/Integer Type-Convert Instructions */ -GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) - -/* Widening Floating-Point/Integer Type-Convert Instructions */ - -/* - * If the current SEW does not correspond to a supported IEEE floating-point - * type, an illegal instruction exception is raised - */ -static bool opfv_widen_check(DisasContext *s, arg_rmr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -#define GEN_OPFV_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (opfv_widen_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) - -/* Narrowing Floating-Point/Integer Type-Convert Instructions */ - -/* - * If the current SEW does not correspond to a supported IEEE floating-point - * type, an illegal instruction exception is raised - */ -static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); -} - -#define GEN_OPFV_NARROW_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (opfv_narrow_check(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) - -/* - *** Vector Reduction Operations - */ -/* Vector Single-Width Integer Reduction Instructions */ -static bool reduction_check(DisasContext *s, arg_rmrr *a) -{ - return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); -} - -GEN_OPIVV_TRANS(vredsum_vs, reduction_check) -GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check) -GEN_OPIVV_TRANS(vredmax_vs, reduction_check) -GEN_OPIVV_TRANS(vredminu_vs, reduction_check) -GEN_OPIVV_TRANS(vredmin_vs, reduction_check) -GEN_OPIVV_TRANS(vredand_vs, reduction_check) -GEN_OPIVV_TRANS(vredor_vs, reduction_check) -GEN_OPIVV_TRANS(vredxor_vs, reduction_check) - -/* Vector Widening Integer Reduction Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) -GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) - -/* Vector Single-Width Floating-Point Reduction Instructions */ -GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) - -/* Vector Widening Floating-Point Reduction Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) - -/* - *** Vector Mask Operations - */ - -/* Vector Mask-Register Logical Instructions */ -#define GEN_MM_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_r *a) \ -{ \ - if (vext_check_isa_ill(s)) { \ - uint32_t data = 0; \ - gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ - TCGLabel *over = gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, 0, \ - s->vlen / 8, data, fn); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_MM_TRANS(vmand_mm) -GEN_MM_TRANS(vmnand_mm) -GEN_MM_TRANS(vmandnot_mm) -GEN_MM_TRANS(vmxor_mm) -GEN_MM_TRANS(vmor_mm) -GEN_MM_TRANS(vmnor_mm) -GEN_MM_TRANS(vmornot_mm) -GEN_MM_TRANS(vmxnor_mm) - -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) -{ - if (vext_check_isa_ill(s)) { - TCGv_ptr src2, mask; - TCGv dst; - TCGv_i32 desc; - uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - - mask = tcg_temp_new_ptr(); - src2 = tcg_temp_new_ptr(); - dst = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); - gen_set_gpr(a->rd, dst); - - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free(dst); - tcg_temp_free_i32(desc); - return true; - } - return false; -} - -/* vmfirst find-first-set mask bit */ -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) -{ - if (vext_check_isa_ill(s)) { - TCGv_ptr src2, mask; - TCGv dst; - TCGv_i32 desc; - uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - - mask = tcg_temp_new_ptr(); - src2 = tcg_temp_new_ptr(); - dst = tcg_temp_new(); - desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data)); - - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); - gen_set_gpr(a->rd, dst); - - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free(dst); - tcg_temp_free_i32(desc); - return true; - } - return false; -} - -/* vmsbf.m set-before-first mask bit */ -/* vmsif.m set-includ-first mask bit */ -/* vmsof.m set-only-first mask bit */ -#define GEN_M_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (vext_check_isa_ill(s)) { \ - uint32_t data = 0; \ - gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ - TCGLabel *over = gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ - vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ - cpu_env, 0, s->vlen / 8, data, fn); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ -} - -GEN_M_TRANS(vmsbf_m) -GEN_M_TRANS(vmsif_m) -GEN_M_TRANS(vmsof_m) - -/* Vector Iota Instruction */ -static bool trans_viota_m(DisasContext *s, arg_viota_m *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && - (a->vm != 0 || a->rd != 0)) { - uint32_t data = 0; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - static gen_helper_gvec_3_ptr * const fns[4] = { - gen_helper_viota_m_b, gen_helper_viota_m_h, - gen_helper_viota_m_w, gen_helper_viota_m_d, - }; - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs2), cpu_env, 0, - s->vlen / 8, data, fns[s->sew]); - gen_set_label(over); - return true; - } - return false; -} - -/* Vector Element Index Instruction */ -static bool trans_vid_v(DisasContext *s, arg_vid_v *a) -{ - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_mask(s, a->rd, a->vm, false)) { - uint32_t data = 0; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - static gen_helper_gvec_2_ptr * const fns[4] = { - gen_helper_vid_v_b, gen_helper_vid_v_h, - gen_helper_vid_v_w, gen_helper_vid_v_d, - }; - tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - cpu_env, 0, s->vlen / 8, data, fns[s->sew]); - gen_set_label(over); - return true; - } - return false; -} - -/* - *** Vector Permutation Instructions - */ - -/* Integer Extract Instruction */ - -static void load_element(TCGv_i64 dest, TCGv_ptr base, - int ofs, int sew) -{ - switch (sew) { - case MO_8: - tcg_gen_ld8u_i64(dest, base, ofs); - break; - case MO_16: - tcg_gen_ld16u_i64(dest, base, ofs); - break; - case MO_32: - tcg_gen_ld32u_i64(dest, base, ofs); - break; - case MO_64: - tcg_gen_ld_i64(dest, base, ofs); - break; - default: - g_assert_not_reached(); - break; - } -} - -/* offset of the idx element with base regsiter r */ -static uint32_t endian_ofs(DisasContext *s, int r, int idx) -{ -#ifdef HOST_WORDS_BIGENDIAN - return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew); -#else - return vreg_ofs(s, r) + (idx << s->sew); -#endif -} - -/* adjust the index according to the endian */ -static void endian_adjust(TCGv_i32 ofs, int sew) -{ -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_xori_i32(ofs, ofs, 7 >> sew); -#endif -} - -/* Load idx >= VLMAX ? 0 : vreg[idx] */ -static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, - int vreg, TCGv idx, int vlmax) -{ - TCGv_i32 ofs = tcg_temp_new_i32(); - TCGv_ptr base = tcg_temp_new_ptr(); - TCGv_i64 t_idx = tcg_temp_new_i64(); - TCGv_i64 t_vlmax, t_zero; - - /* - * Mask the index to the length so that we do - * not produce an out-of-range load. - */ - tcg_gen_trunc_tl_i32(ofs, idx); - tcg_gen_andi_i32(ofs, ofs, vlmax - 1); - - /* Convert the index to an offset. */ - endian_adjust(ofs, s->sew); - tcg_gen_shli_i32(ofs, ofs, s->sew); - - /* Convert the index to a pointer. */ - tcg_gen_ext_i32_ptr(base, ofs); - tcg_gen_add_ptr(base, base, cpu_env); - - /* Perform the load. */ - load_element(dest, base, - vreg_ofs(s, vreg), s->sew); - tcg_temp_free_ptr(base); - tcg_temp_free_i32(ofs); - - /* Flush out-of-range indexing to zero. */ - t_vlmax = tcg_const_i64(vlmax); - t_zero = tcg_const_i64(0); - tcg_gen_extu_tl_i64(t_idx, idx); - - tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx, - t_vlmax, dest, t_zero); - - tcg_temp_free_i64(t_vlmax); - tcg_temp_free_i64(t_zero); - tcg_temp_free_i64(t_idx); -} - -static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, - int vreg, int idx) -{ - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); -} - -static bool trans_vext_x_v(DisasContext *s, arg_r *a) -{ - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv dest = tcg_temp_new(); - - if (a->rs1 == 0) { - /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0); - } else { - /* This instruction ignores LMUL and vector register groups */ - int vlmax = s->vlen >> (3 + s->sew); - vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); - } - tcg_gen_trunc_i64_tl(dest, tmp); - gen_set_gpr(a->rd, dest); - - tcg_temp_free(dest); - tcg_temp_free_i64(tmp); - return true; -} - -/* Integer Scalar Move Instruction */ - -static void store_element(TCGv_i64 val, TCGv_ptr base, - int ofs, int sew) -{ - switch (sew) { - case MO_8: - tcg_gen_st8_i64(val, base, ofs); - break; - case MO_16: - tcg_gen_st16_i64(val, base, ofs); - break; - case MO_32: - tcg_gen_st32_i64(val, base, ofs); - break; - case MO_64: - tcg_gen_st_i64(val, base, ofs); - break; - default: - g_assert_not_reached(); - break; - } -} - -/* - * Store vreg[idx] = val. - * The index must be in range of VLMAX. - */ -static void vec_element_storei(DisasContext *s, int vreg, - int idx, TCGv_i64 val) -{ - store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); -} - -/* vmv.s.x vd, rs1 # vd[0] = rs1 */ -static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) -{ - if (vext_check_isa_ill(s)) { - /* This instruction ignores LMUL and vector register groups */ - int maxsz = s->vlen >> 3; - TCGv_i64 t1; - TCGLabel *over = gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); - if (a->rs1 == 0) { - goto done; - } - - t1 = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); - vec_element_storei(s, a->rd, 0, t1); - tcg_temp_free_i64(t1); - done: - gen_set_label(over); - return true; - } - return false; -} - -/* Floating-Point Scalar Move Instructions */ -static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) -{ - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; - - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); - } - - mark_fs_dirty(s); - return true; - } - return false; -} - -/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ -static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) -{ - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; - /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; - - /* if vl == 0, skip vector register write back */ - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ - t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } - vec_element_storei(s, a->rd, 0, t1); - tcg_temp_free_i64(t1); - gen_set_label(over); - return true; - } - return false; -} - -/* Vector Slide Instructions */ -static bool slideup_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); -} - -GEN_OPIVX_TRANS(vslideup_vx, slideup_check) -GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) -GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) - -GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) - -/* Vector Register Gather Instruction */ -static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2) && (a->rd != a->rs1)); -} - -GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) - -static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); -} - -/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ -static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) -{ - if (!vrgather_vx_check(s, a)) { - return false; - } - - if (a->vm && s->vl_eq_vlmax) { - int vlmax = s->vlen / s->mlen; - TCGv_i64 dest = tcg_temp_new_i64(); - - if (a->rs1 == 0) { - vec_element_loadi(s, dest, a->rs2, 0); - } else { - vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); - } - - tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), dest); - tcg_temp_free_i64(dest); - } else { - static gen_helper_opivx * const fns[4] = { - gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, - gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d - }; - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); - } - return true; -} - -/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */ -static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) -{ - if (!vrgather_vx_check(s, a)) { - return false; - } - - if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >= s->vlen / s->mlen) { - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), 0); - } else { - tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd), - endian_ofs(s, a->rs2, a->rs1), - MAXSZ(s), MAXSZ(s)); - } - } else { - static gen_helper_opivx * const fns[4] = { - gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, - gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d - }; - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1); - } - return true; -} - -/* Vector Compress Instruction */ -static bool vcompress_vm_check(DisasContext *s, arg_r *a) -{ - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && - (a->rd != a->rs2)); -} - -static bool trans_vcompress_vm(DisasContext *s, arg_r *a) -{ - if (vcompress_vm_check(s, a)) { - uint32_t data = 0; - static gen_helper_gvec_4_ptr * const fns[4] = { - gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h, - gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d, - }; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, 0, s->vlen / 8, data, fns[s->sew]); - gen_set_label(over); - return true; - } - return false; -} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..5ef5613909 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) } /* Include the auto-generated decoder for 32 bit insn */ -#include "decode_insn32.inc.c" +#include "decode_insn32.c.inc" static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, void (*func)(TCGv, TCGv, target_long)) @@ -718,17 +718,17 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, } /* Include insn module translation function */ -#include "insn_trans/trans_rvi.inc.c" -#include "insn_trans/trans_rvm.inc.c" -#include "insn_trans/trans_rva.inc.c" -#include "insn_trans/trans_rvf.inc.c" -#include "insn_trans/trans_rvd.inc.c" -#include "insn_trans/trans_rvh.inc.c" -#include "insn_trans/trans_rvv.inc.c" -#include "insn_trans/trans_privileged.inc.c" +#include "insn_trans/trans_rvi.c.inc" +#include "insn_trans/trans_rvm.c.inc" +#include "insn_trans/trans_rva.c.inc" +#include "insn_trans/trans_rvf.c.inc" +#include "insn_trans/trans_rvd.c.inc" +#include "insn_trans/trans_rvh.c.inc" +#include "insn_trans/trans_rvv.c.inc" +#include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */ -#include "decode_insn16.inc.c" +#include "decode_insn16.c.inc" static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs index a0018d5bc5..cc3c4204a1 100644 --- a/target/rx/Makefile.objs +++ b/target/rx/Makefile.objs @@ -2,10 +2,10 @@ obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py -target/rx/decode.inc.c: \ +target/rx/decode.c.inc: \ $(SRC_PATH)/target/rx/insns.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@) -target/rx/translate.o: target/rx/decode.inc.c -target/rx/disas.o: target/rx/decode.inc.c +target/rx/translate.o: target/rx/decode.c.inc +target/rx/disas.o: target/rx/decode.c.inc diff --git a/target/rx/disas.c b/target/rx/disas.c index 6dee7a0342..60eff6f55f 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -100,7 +100,7 @@ static int bdsp_s(DisasContext *ctx, int d) } /* Include the auto-generated decoder. */ -#include "decode.inc.c" +#include "decode.c.inc" static void dump_bytes(DisasContext *ctx) { diff --git a/target/rx/translate.c b/target/rx/translate.c index 61e86653a4..bc49614cbb 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -124,7 +124,7 @@ static int bdsp_s(DisasContext *ctx, int d) } /* Include the auto-generated decoder. */ -#include "decode.inc.c" +#include "decode.c.inc" void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4f6f1e31cd..a777343821 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5120,7 +5120,7 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o) } #endif -#include "translate_vx.inc.c" +#include "translate_vx.c.inc" /* ====================================================================== */ /* The "Cc OUTput" generators. Given the generated output (and in some cases diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc new file mode 100644 index 0000000000..eb767f5288 --- /dev/null +++ b/target/s390x/translate_vx.c.inc @@ -0,0 +1,2718 @@ +/* + * QEMU TCG support -- s390x vector instruction translation functions + * + * Copyright (C) 2019 Red Hat Inc + * + * Authors: + * David Hildenbrand + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +/* + * For most instructions that use the same element size for reads and + * writes, we can use real gvec vector expansion, which potantially uses + * real host vector instructions. As they only work up to 64 bit elements, + * 128 bit elements (vector is a single element) have to be handled + * differently. Operations that are too complicated to encode via TCG ops + * are handled via gvec ool (out-of-line) handlers. + * + * As soon as instructions use different element sizes for reads and writes + * or access elements "out of their element scope" we expand them manually + * in fancy loops, as gvec expansion does not deal with actual element + * numbers and does also not support access to other elements. + * + * 128 bit elements: + * As we only have i32/i64, such elements have to be loaded into two + * i64 values and can then be processed e.g. by tcg_gen_add2_i64. + * + * Sizes: + * On s390x, the operand size (oprsz) and the maximum size (maxsz) are + * always 16 (128 bit). What gvec code calls "vece", s390x calls "es", + * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only + * 128 bit element size has to be treated in a special way (MO_64 + 1). + * We will use ES_* instead of MO_* for this reason in this file. + * + * CC handling: + * As gvec ool-helpers can currently not return values (besides via + * pointers like vectors or cpu_env), whenever we have to set the CC and + * can't conclude the value from the result vector, we will directly + * set it in "env->cc_op" and mark it as static via set_cc_static()". + * Whenever this is done, the helper writes globals (cc_op). + */ + +#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es)) +#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es)) +#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE) + +#define ES_8 MO_8 +#define ES_16 MO_16 +#define ES_32 MO_32 +#define ES_64 MO_64 +#define ES_128 4 + +/* Floating-Point Format */ +#define FPF_SHORT 2 +#define FPF_LONG 3 +#define FPF_EXT 4 + +static inline bool valid_vec_element(uint8_t enr, MemOp es) +{ + return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1)); +} + +static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr, + MemOp memop) +{ + const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_ld8u_i64(dst, cpu_env, offs); + break; + case ES_16: + tcg_gen_ld16u_i64(dst, cpu_env, offs); + break; + case ES_32: + tcg_gen_ld32u_i64(dst, cpu_env, offs); + break; + case ES_8 | MO_SIGN: + tcg_gen_ld8s_i64(dst, cpu_env, offs); + break; + case ES_16 | MO_SIGN: + tcg_gen_ld16s_i64(dst, cpu_env, offs); + break; + case ES_32 | MO_SIGN: + tcg_gen_ld32s_i64(dst, cpu_env, offs); + break; + case ES_64: + case ES_64 | MO_SIGN: + tcg_gen_ld_i64(dst, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} + +static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr, + MemOp memop) +{ + const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_ld8u_i32(dst, cpu_env, offs); + break; + case ES_16: + tcg_gen_ld16u_i32(dst, cpu_env, offs); + break; + case ES_8 | MO_SIGN: + tcg_gen_ld8s_i32(dst, cpu_env, offs); + break; + case ES_16 | MO_SIGN: + tcg_gen_ld16s_i32(dst, cpu_env, offs); + break; + case ES_32: + case ES_32 | MO_SIGN: + tcg_gen_ld_i32(dst, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} + +static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, + MemOp memop) +{ + const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_st8_i64(src, cpu_env, offs); + break; + case ES_16: + tcg_gen_st16_i64(src, cpu_env, offs); + break; + case ES_32: + tcg_gen_st32_i64(src, cpu_env, offs); + break; + case ES_64: + tcg_gen_st_i64(src, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} + +static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr, + MemOp memop) +{ + const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_st8_i32(src, cpu_env, offs); + break; + case ES_16: + tcg_gen_st16_i32(src, cpu_env, offs); + break; + case ES_32: + tcg_gen_st_i32(src, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} + +static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, + uint8_t es) +{ + TCGv_i64 tmp = tcg_temp_new_i64(); + + /* mask off invalid parts from the element nr */ + tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1); + + /* convert it to an element offset relative to cpu_env (vec_reg_offset() */ + tcg_gen_shli_i64(tmp, tmp, es); +#ifndef HOST_WORDS_BIGENDIAN + tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es)); +#endif + tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg)); + + /* generate the final ptr by adding cpu_env */ + tcg_gen_trunc_i64_ptr(ptr, tmp); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + + tcg_temp_free_i64(tmp); +} + +#define gen_gvec_2(v1, v2, gen) \ + tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, gen) +#define gen_gvec_2s(v1, v2, c, gen) \ + tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, c, gen) +#define gen_gvec_2_ool(v1, v2, data, fn) \ + tcg_gen_gvec_2_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, data, fn) +#define gen_gvec_2i_ool(v1, v2, c, data, fn) \ + tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + c, 16, 16, data, fn) +#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \ + tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + ptr, 16, 16, data, fn) +#define gen_gvec_3(v1, v2, v3, gen) \ + tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), 16, 16, gen) +#define gen_gvec_3_ool(v1, v2, v3, data, fn) \ + tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), 16, 16, data, fn) +#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \ + tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), ptr, 16, 16, data, fn) +#define gen_gvec_3i(v1, v2, v3, c, gen) \ + tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), 16, 16, c, gen) +#define gen_gvec_4(v1, v2, v3, v4, gen) \ + tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ + 16, 16, gen) +#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \ + tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ + 16, 16, data, fn) +#define gen_gvec_4_ptr(v1, v2, v3, v4, ptr, data, fn) \ + tcg_gen_gvec_4_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ + ptr, 16, 16, data, fn) +#define gen_gvec_dup_i64(es, v1, c) \ + tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c) +#define gen_gvec_mov(v1, v2) \ + tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \ + 16) +#define gen_gvec_dup_imm(es, v1, c) \ + tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c); +#define gen_gvec_fn_2(fn, es, v1, v2) \ + tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16) +#define gen_gvec_fn_2i(fn, es, v1, v2, c) \ + tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + c, 16, 16) +#define gen_gvec_fn_2s(fn, es, v1, v2, s) \ + tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + s, 16, 16) +#define gen_gvec_fn_3(fn, es, v1, v2, v3) \ + tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), 16, 16) +#define gen_gvec_fn_4(fn, es, v1, v2, v3, v4) \ + tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + vec_full_reg_offset(v3), vec_full_reg_offset(v4), 16, 16) + +/* + * Helper to carry out a 128 bit vector computation using 2 i64 values per + * vector. + */ +typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a, + uint8_t b) +{ + TCGv_i64 dh = tcg_temp_new_i64(); + TCGv_i64 dl = tcg_temp_new_i64(); + TCGv_i64 ah = tcg_temp_new_i64(); + TCGv_i64 al = tcg_temp_new_i64(); + TCGv_i64 bh = tcg_temp_new_i64(); + TCGv_i64 bl = tcg_temp_new_i64(); + + read_vec_element_i64(ah, a, 0, ES_64); + read_vec_element_i64(al, a, 1, ES_64); + read_vec_element_i64(bh, b, 0, ES_64); + read_vec_element_i64(bl, b, 1, ES_64); + fn(dl, dh, al, ah, bl, bh); + write_vec_element_i64(dh, d, 0, ES_64); + write_vec_element_i64(dl, d, 1, ES_64); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(dl); + tcg_temp_free_i64(ah); + tcg_temp_free_i64(al); + tcg_temp_free_i64(bh); + tcg_temp_free_i64(bl); +} + +typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, + TCGv_i64 cl, TCGv_i64 ch); +static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, + uint8_t b, uint8_t c) +{ + TCGv_i64 dh = tcg_temp_new_i64(); + TCGv_i64 dl = tcg_temp_new_i64(); + TCGv_i64 ah = tcg_temp_new_i64(); + TCGv_i64 al = tcg_temp_new_i64(); + TCGv_i64 bh = tcg_temp_new_i64(); + TCGv_i64 bl = tcg_temp_new_i64(); + TCGv_i64 ch = tcg_temp_new_i64(); + TCGv_i64 cl = tcg_temp_new_i64(); + + read_vec_element_i64(ah, a, 0, ES_64); + read_vec_element_i64(al, a, 1, ES_64); + read_vec_element_i64(bh, b, 0, ES_64); + read_vec_element_i64(bl, b, 1, ES_64); + read_vec_element_i64(ch, c, 0, ES_64); + read_vec_element_i64(cl, c, 1, ES_64); + fn(dl, dh, al, ah, bl, bh, cl, ch); + write_vec_element_i64(dh, d, 0, ES_64); + write_vec_element_i64(dl, d, 1, ES_64); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(dl); + tcg_temp_free_i64(ah); + tcg_temp_free_i64(al); + tcg_temp_free_i64(bh); + tcg_temp_free_i64(bl); + tcg_temp_free_i64(ch); + tcg_temp_free_i64(cl); +} + +static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, + uint64_t b) +{ + TCGv_i64 bl = tcg_const_i64(b); + TCGv_i64 bh = tcg_const_i64(0); + + tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); + tcg_temp_free_i64(bl); + tcg_temp_free_i64(bh); +} + +static DisasJumpType op_vge(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s, v2), enr, es); + tcg_gen_add_i64(o->addr1, o->addr1, tmp); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); + + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + write_vec_element_i64(tmp, get_field(s, v1), enr, es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static uint64_t generate_byte_mask(uint8_t mask) +{ + uint64_t r = 0; + int i; + + for (i = 0; i < 8; i++) { + if ((mask >> i) & 1) { + r |= 0xffull << (i * 8); + } + } + return r; +} + +static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o) +{ + const uint16_t i2 = get_field(s, i2); + + if (i2 == (i2 & 0xff) * 0x0101) { + /* + * Masks for both 64 bit elements of the vector are the same. + * Trust tcg to produce a good constant loading. + */ + gen_gvec_dup_imm(ES_64, get_field(s, v1), + generate_byte_mask(i2 & 0xff)); + } else { + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8)); + write_vec_element_i64(t, get_field(s, v1), 0, ES_64); + tcg_gen_movi_i64(t, generate_byte_mask(i2)); + write_vec_element_i64(t, get_field(s, v1), 1, ES_64); + tcg_temp_free_i64(t); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vgm(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t bits = NUM_VEC_ELEMENT_BITS(es); + const uint8_t i2 = get_field(s, i2) & (bits - 1); + const uint8_t i3 = get_field(s, i3) & (bits - 1); + uint64_t mask = 0; + int i; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* generate the mask - take care of wrapping */ + for (i = i2; ; i = (i + 1) % bits) { + mask |= 1ull << (bits - i - 1); + if (i == i3) { + break; + } + } + + gen_gvec_dup_imm(es, get_field(s, v1), mask); + return DISAS_NEXT; +} + +static DisasJumpType op_vl(DisasContext *s, DisasOps *o) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); + write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); + write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); + tcg_temp_free(t0); + tcg_temp_free(t1); + return DISAS_NEXT; +} + +static DisasJumpType op_vlr(DisasContext *s, DisasOps *o) +{ + gen_gvec_mov(get_field(s, v1), get_field(s, v2)); + return DISAS_NEXT; +} + +static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + TCGv_i64 tmp; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + gen_gvec_dup_i64(es, get_field(s, v1), tmp); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vle(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + write_vec_element_i64(tmp, get_field(s, v1), enr, es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vlei(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_const_i64((int16_t)get_field(s, i2)); + write_vec_element_i64(tmp, get_field(s, v1), enr, es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + TCGv_ptr ptr; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* fast path if we don't need the register content */ + if (!get_field(s, b2)) { + uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1); + + read_vec_element_i64(o->out, get_field(s, v3), enr, es); + return DISAS_NEXT; + } + + ptr = tcg_temp_new_ptr(); + get_vec_element_ptr_i64(ptr, get_field(s, v3), o->addr1, es); + switch (es) { + case ES_8: + tcg_gen_ld8u_i64(o->out, ptr, 0); + break; + case ES_16: + tcg_gen_ld16u_i64(o->out, ptr, 0); + break; + case ES_32: + tcg_gen_ld32u_i64(o->out, ptr, 0); + break; + case ES_64: + tcg_gen_ld_i64(o->out, ptr, 0); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_ptr(ptr); + + return DISAS_NEXT; +} + +static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) +{ + uint8_t es = get_field(s, m3); + uint8_t enr; + TCGv_i64 t; + + switch (es) { + /* rightmost sub-element of leftmost doubleword */ + case ES_8: + enr = 7; + break; + case ES_16: + enr = 3; + break; + case ES_32: + enr = 1; + break; + case ES_64: + enr = 0; + break; + /* leftmost sub-element of leftmost doubleword */ + case 6: + if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { + es = ES_32; + enr = 0; + break; + } + /* fallthrough */ + default: + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + t = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); + gen_gvec_dup_imm(es, get_field(s, v1), 0); + write_vec_element_i64(t, get_field(s, v1), enr, es); + tcg_temp_free_i64(t); + return DISAS_NEXT; +} + +static DisasJumpType op_vlm(DisasContext *s, DisasOps *o) +{ + const uint8_t v3 = get_field(s, v3); + uint8_t v1 = get_field(s, v1); + TCGv_i64 t0, t1; + + if (v3 < v1 || (v3 - v1 + 1) > 16) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* + * Check for possible access exceptions by trying to load the last + * element. The first element will be checked first next. + */ + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8); + tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ); + + for (;; v1++) { + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); + write_vec_element_i64(t1, v1, 0, ES_64); + if (v1 == v3) { + break; + } + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); + write_vec_element_i64(t1, v1, 1, ES_64); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + } + + /* Store the last element, loaded first */ + write_vec_element_i64(t0, v1, 1, ES_64); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + return DISAS_NEXT; +} + +static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o) +{ + const int64_t block_size = (1ull << (get_field(s, m3) + 6)); + const int v1_offs = vec_full_reg_offset(get_field(s, v1)); + TCGv_ptr a0; + TCGv_i64 bytes; + + if (get_field(s, m3) > 6) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + bytes = tcg_temp_new_i64(); + a0 = tcg_temp_new_ptr(); + /* calculate the number of bytes until the next block boundary */ + tcg_gen_ori_i64(bytes, o->addr1, -block_size); + tcg_gen_neg_i64(bytes, bytes); + + tcg_gen_addi_ptr(a0, cpu_env, v1_offs); + gen_helper_vll(cpu_env, a0, o->addr1, bytes); + tcg_temp_free_i64(bytes); + tcg_temp_free_ptr(a0); + return DISAS_NEXT; +} + +static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + TCGv_ptr ptr; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* fast path if we don't need the register content */ + if (!get_field(s, b2)) { + uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1); + + write_vec_element_i64(o->in2, get_field(s, v1), enr, es); + return DISAS_NEXT; + } + + ptr = tcg_temp_new_ptr(); + get_vec_element_ptr_i64(ptr, get_field(s, v1), o->addr1, es); + switch (es) { + case ES_8: + tcg_gen_st8_i64(o->in2, ptr, 0); + break; + case ES_16: + tcg_gen_st16_i64(o->in2, ptr, 0); + break; + case ES_32: + tcg_gen_st32_i64(o->in2, ptr, 0); + break; + case ES_64: + tcg_gen_st_i64(o->in2, ptr, 0); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_ptr(ptr); + + return DISAS_NEXT; +} + +static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o) +{ + write_vec_element_i64(o->in1, get_field(s, v1), 0, ES_64); + write_vec_element_i64(o->in2, get_field(s, v1), 1, ES_64); + return DISAS_NEXT; +} + +static DisasJumpType op_vll(DisasContext *s, DisasOps *o) +{ + const int v1_offs = vec_full_reg_offset(get_field(s, v1)); + TCGv_ptr a0 = tcg_temp_new_ptr(); + + /* convert highest index into an actual length */ + tcg_gen_addi_i64(o->in2, o->in2, 1); + tcg_gen_addi_ptr(a0, cpu_env, v1_offs); + gen_helper_vll(cpu_env, a0, o->addr1, o->in2); + tcg_temp_free_ptr(a0); + return DISAS_NEXT; +} + +static DisasJumpType op_vmr(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t v3 = get_field(s, v3); + const uint8_t es = get_field(s, m4); + int dst_idx, src_idx; + TCGv_i64 tmp; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + if (s->fields.op2 == 0x61) { + /* iterate backwards to avoid overwriting data we might need later */ + for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) { + src_idx = dst_idx / 2; + if (dst_idx % 2 == 0) { + read_vec_element_i64(tmp, v2, src_idx, es); + } else { + read_vec_element_i64(tmp, v3, src_idx, es); + } + write_vec_element_i64(tmp, v1, dst_idx, es); + } + } else { + /* iterate forward to avoid overwriting data we might need later */ + for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) { + src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2; + if (dst_idx % 2 == 0) { + read_vec_element_i64(tmp, v2, src_idx, es); + } else { + read_vec_element_i64(tmp, v3, src_idx, es); + } + write_vec_element_i64(tmp, v1, dst_idx, es); + } + } + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vpk(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t v3 = get_field(s, v3); + const uint8_t es = get_field(s, m4); + static gen_helper_gvec_3 * const vpk[3] = { + gen_helper_gvec_vpk16, + gen_helper_gvec_vpk32, + gen_helper_gvec_vpk64, + }; + static gen_helper_gvec_3 * const vpks[3] = { + gen_helper_gvec_vpks16, + gen_helper_gvec_vpks32, + gen_helper_gvec_vpks64, + }; + static gen_helper_gvec_3_ptr * const vpks_cc[3] = { + gen_helper_gvec_vpks_cc16, + gen_helper_gvec_vpks_cc32, + gen_helper_gvec_vpks_cc64, + }; + static gen_helper_gvec_3 * const vpkls[3] = { + gen_helper_gvec_vpkls16, + gen_helper_gvec_vpkls32, + gen_helper_gvec_vpkls64, + }; + static gen_helper_gvec_3_ptr * const vpkls_cc[3] = { + gen_helper_gvec_vpkls_cc16, + gen_helper_gvec_vpkls_cc32, + gen_helper_gvec_vpkls_cc64, + }; + + if (es == ES_8 || es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0x97: + if (get_field(s, m5) & 0x1) { + gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]); + set_cc_static(s); + } else { + gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]); + } + break; + case 0x95: + if (get_field(s, m5) & 0x1) { + gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]); + set_cc_static(s); + } else { + gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]); + } + break; + case 0x94: + /* If sources and destination dont't overlap -> fast path */ + if (v1 != v2 && v1 != v3) { + const uint8_t src_es = get_field(s, m4); + const uint8_t dst_es = src_es - 1; + TCGv_i64 tmp = tcg_temp_new_i64(); + int dst_idx, src_idx; + + for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) { + src_idx = dst_idx; + if (src_idx < NUM_VEC_ELEMENTS(src_es)) { + read_vec_element_i64(tmp, v2, src_idx, src_es); + } else { + src_idx -= NUM_VEC_ELEMENTS(src_es); + read_vec_element_i64(tmp, v3, src_idx, src_es); + } + write_vec_element_i64(tmp, v1, dst_idx, dst_es); + } + tcg_temp_free_i64(tmp); + } else { + gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]); + } + break; + default: + g_assert_not_reached(); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vperm(DisasContext *s, DisasOps *o) +{ + gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), + 0, gen_helper_gvec_vperm); + return DISAS_NEXT; +} + +static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o) +{ + const uint8_t i2 = extract32(get_field(s, m4), 2, 1); + const uint8_t i3 = extract32(get_field(s, m4), 0, 1); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + read_vec_element_i64(t0, get_field(s, v2), i2, ES_64); + read_vec_element_i64(t1, get_field(s, v3), i3, ES_64); + write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); + write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + return DISAS_NEXT; +} + +static DisasJumpType op_vrep(DisasContext *s, DisasOps *o) +{ + const uint8_t enr = get_field(s, i2); + const uint8_t es = get_field(s, m4); + + if (es > ES_64 || !valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s, v1)), + vec_reg_offset(get_field(s, v3), enr, es), + 16, 16); + return DISAS_NEXT; +} + +static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o) +{ + const int64_t data = (int16_t)get_field(s, i2); + const uint8_t es = get_field(s, m3); + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_dup_imm(es, get_field(s, v1), data); + return DISAS_NEXT; +} + +static DisasJumpType op_vsce(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s, v2), enr, es); + tcg_gen_add_i64(o->addr1, o->addr1, tmp); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); + + read_vec_element_i64(tmp, get_field(s, v1), enr, es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vsel(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_4(bitsel, ES_8, get_field(s, v1), + get_field(s, v4), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + int idx1, idx2; + TCGv_i64 tmp; + + switch (es) { + case ES_8: + idx1 = 7; + idx2 = 15; + break; + case ES_16: + idx1 = 3; + idx2 = 7; + break; + case ES_32: + idx1 = 1; + idx2 = 3; + break; + default: + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s, v2), idx1, es | MO_SIGN); + write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); + read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN); + write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vst(DisasContext *s, DisasOps *o) +{ + TCGv_i64 tmp = tcg_const_i64(16); + + /* Probe write access before actually modifying memory */ + gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + + read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vste(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s, v1), enr, es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) +{ + const uint8_t v3 = get_field(s, v3); + uint8_t v1 = get_field(s, v1); + TCGv_i64 tmp; + + while (v3 < v1 || (v3 - v1 + 1) > 16) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + /* Probe write access before actually modifying memory */ + tmp = tcg_const_i64((v3 - v1 + 1) * 16); + gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + + for (;; v1++) { + read_vec_element_i64(tmp, v1, 0, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + read_vec_element_i64(tmp, v1, 1, ES_64); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); + if (v1 == v3) { + break; + } + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); + } + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vstl(DisasContext *s, DisasOps *o) +{ + const int v1_offs = vec_full_reg_offset(get_field(s, v1)); + TCGv_ptr a0 = tcg_temp_new_ptr(); + + /* convert highest index into an actual length */ + tcg_gen_addi_i64(o->in2, o->in2, 1); + tcg_gen_addi_ptr(a0, cpu_env, v1_offs); + gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); + tcg_temp_free_ptr(a0); + return DISAS_NEXT; +} + +static DisasJumpType op_vup(DisasContext *s, DisasOps *o) +{ + const bool logical = s->fields.op2 == 0xd4 || s->fields.op2 == 0xd5; + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t src_es = get_field(s, m3); + const uint8_t dst_es = src_es + 1; + int dst_idx, src_idx; + TCGv_i64 tmp; + + if (src_es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + if (s->fields.op2 == 0xd7 || s->fields.op2 == 0xd5) { + /* iterate backwards to avoid overwriting data we might need later */ + for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) { + src_idx = dst_idx; + read_vec_element_i64(tmp, v2, src_idx, + src_es | (logical ? 0 : MO_SIGN)); + write_vec_element_i64(tmp, v1, dst_idx, dst_es); + } + + } else { + /* iterate forward to avoid overwriting data we might need later */ + for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) { + src_idx = dst_idx + NUM_VEC_ELEMENTS(src_es) / 2; + read_vec_element_i64(tmp, v2, src_idx, + src_es | (logical ? 0 : MO_SIGN)); + write_vec_element_i64(tmp, v1, dst_idx, dst_es); + } + } + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_va(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + + if (es > ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } else if (es == ES_128) { + gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; + } + gen_gvec_fn_3(add, es, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) +{ + const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; + TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + /* Calculate the carry into the MSB, ignoring the old MSBs */ + tcg_gen_andc_i64(t1, a, msb_mask); + tcg_gen_andc_i64(t2, b, msb_mask); + tcg_gen_add_i64(t1, t1, t2); + /* Calculate the MSB without any carry into it */ + tcg_gen_xor_i64(t3, a, b); + /* Calculate the carry out of the MSB in the MSB bit position */ + tcg_gen_and_i64(d, a, b); + tcg_gen_and_i64(t1, t1, t3); + tcg_gen_or_i64(d, d, t1); + /* Isolate and shift the carry into position */ + tcg_gen_and_i64(d, d, msb_mask); + tcg_gen_shri_i64(d, d, msb_bit_nr); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); +} + +static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + gen_acc(d, a, b, ES_8); +} + +static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + gen_acc(d, a, b, ES_16); +} + +static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(); + + tcg_gen_add_i32(t, a, b); + tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b); + tcg_temp_free_i32(t); +} + +static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_add_i64(t, a, b); + tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); + tcg_temp_free_i64(t); +} + +static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) +{ + TCGv_i64 th = tcg_temp_new_i64(); + TCGv_i64 tl = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_add2_i64(tl, th, al, zero, bl, zero); + tcg_gen_add2_i64(tl, th, th, zero, ah, zero); + tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); + tcg_gen_mov_i64(dh, zero); + + tcg_temp_free_i64(th); + tcg_temp_free_i64(tl); + tcg_temp_free_i64(zero); +} + +static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g[4] = { + { .fni8 = gen_acc8_i64, }, + { .fni8 = gen_acc16_i64, }, + { .fni4 = gen_acc_i32, }, + { .fni8 = gen_acc_i64, }, + }; + + if (es > ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } else if (es == ES_128) { + gen_gvec128_3_i64(gen_acc2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; + } + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), &g[es]); + return DISAS_NEXT; +} + +static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) +{ + TCGv_i64 tl = tcg_temp_new_i64(); + TCGv_i64 th = tcg_const_i64(0); + + /* extract the carry only */ + tcg_gen_extract_i64(tl, cl, 0, 1); + tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); +} + +static DisasJumpType op_vac(DisasContext *s, DisasOps *o) +{ + if (get_field(s, m5) != ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_ac2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3), + get_field(s, v4)); + return DISAS_NEXT; +} + +static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) +{ + TCGv_i64 tl = tcg_temp_new_i64(); + TCGv_i64 th = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_andi_i64(tl, cl, 1); + tcg_gen_add2_i64(tl, th, tl, zero, al, zero); + tcg_gen_add2_i64(tl, th, tl, th, bl, zero); + tcg_gen_add2_i64(tl, th, th, zero, ah, zero); + tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); + tcg_gen_mov_i64(dh, zero); + + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); + tcg_temp_free_i64(zero); +} + +static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) +{ + if (get_field(s, m5) != ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_accc2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3), + get_field(s, v4)); + return DISAS_NEXT; +} + +static DisasJumpType op_vn(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(and, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vnc(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(andc, ES_8, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; +} + +static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(t0, a); + tcg_gen_ext_i32_i64(t1, b); + tcg_gen_add_i64(t0, t0, t1); + tcg_gen_addi_i64(t0, t0, 1); + tcg_gen_shri_i64(t0, t0, 1); + tcg_gen_extrl_i64_i32(d, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) +{ + TCGv_i64 dh = tcg_temp_new_i64(); + TCGv_i64 ah = tcg_temp_new_i64(); + TCGv_i64 bh = tcg_temp_new_i64(); + + /* extending the sign by one bit is sufficient */ + tcg_gen_extract_i64(ah, al, 63, 1); + tcg_gen_extract_i64(bh, bl, 63, 1); + tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); + gen_addi2_i64(dl, dh, dl, dh, 1); + tcg_gen_extract2_i64(dl, dl, dh, 1); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(ah); + tcg_temp_free_i64(bh); +} + +static DisasJumpType op_vavg(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_vavg8, }, + { .fno = gen_helper_gvec_vavg16, }, + { .fni4 = gen_avg_i32, }, + { .fni8 = gen_avg_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), &g[es]); + return DISAS_NEXT; +} + +static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(t0, a); + tcg_gen_extu_i32_i64(t1, b); + tcg_gen_add_i64(t0, t0, t1); + tcg_gen_addi_i64(t0, t0, 1); + tcg_gen_shri_i64(t0, t0, 1); + tcg_gen_extrl_i64_i32(d, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) +{ + TCGv_i64 dh = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); + gen_addi2_i64(dl, dh, dl, dh, 1); + tcg_gen_extract2_i64(dl, dl, dh, 1); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(zero); +} + +static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_vavgl8, }, + { .fno = gen_helper_gvec_vavgl16, }, + { .fni4 = gen_avgl_i32, }, + { .fni8 = gen_avgl_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + TCGv_i32 sum = tcg_temp_new_i32(); + int i; + + read_vec_element_i32(sum, get_field(s, v3), 1, ES_32); + for (i = 0; i < 4; i++) { + read_vec_element_i32(tmp, get_field(s, v2), i, ES_32); + tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp); + } + gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); + write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(sum); + return DISAS_NEXT; +} + +static DisasJumpType op_vec(DisasContext *s, DisasOps *o) +{ + uint8_t es = get_field(s, m3); + const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + if (s->fields.op2 == 0xdb) { + es |= MO_SIGN; + } + + o->in1 = tcg_temp_new_i64(); + o->in2 = tcg_temp_new_i64(); + read_vec_element_i64(o->in1, get_field(s, v1), enr, es); + read_vec_element_i64(o->in2, get_field(s, v2), enr, es); + return DISAS_NEXT; +} + +static DisasJumpType op_vc(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + TCGCond cond = s->insn->data; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tcg_gen_gvec_cmp(cond, es, + vec_full_reg_offset(get_field(s, v1)), + vec_full_reg_offset(get_field(s, v2)), + vec_full_reg_offset(get_field(s, v3)), 16, 16); + if (get_field(s, m5) & 0x1) { + TCGv_i64 low = tcg_temp_new_i64(); + TCGv_i64 high = tcg_temp_new_i64(); + + read_vec_element_i64(high, get_field(s, v1), 0, ES_64); + read_vec_element_i64(low, get_field(s, v1), 1, ES_64); + gen_op_update2_cc_i64(s, CC_OP_VC, low, high); + + tcg_temp_free_i64(low); + tcg_temp_free_i64(high); + } + return DISAS_NEXT; +} + +static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_clzi_i32(d, a, 32); +} + +static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_clzi_i64(d, a, 64); +} + +static DisasJumpType op_vclz(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + static const GVecGen2 g[4] = { + { .fno = gen_helper_gvec_vclz8, }, + { .fno = gen_helper_gvec_vclz16, }, + { .fni4 = gen_clz_i32, }, + { .fni8 = gen_clz_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); + return DISAS_NEXT; +} + +static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_ctzi_i32(d, a, 32); +} + +static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_ctzi_i64(d, a, 64); +} + +static DisasJumpType op_vctz(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + static const GVecGen2 g[4] = { + { .fno = gen_helper_gvec_vctz8, }, + { .fno = gen_helper_gvec_vctz16, }, + { .fni4 = gen_ctz_i32, }, + { .fni8 = gen_ctz_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_vx(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(xor, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_vgfm8, }, + { .fno = gen_helper_gvec_vgfm16, }, + { .fno = gen_helper_gvec_vgfm32, }, + { .fno = gen_helper_gvec_vgfm64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m5); + static const GVecGen4 g[4] = { + { .fno = gen_helper_gvec_vgfma8, }, + { .fno = gen_helper_gvec_vgfma16, }, + { .fno = gen_helper_gvec_vgfma32, }, + { .fno = gen_helper_gvec_vgfma64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_4(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_vlc(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_fn_2(neg, es, get_field(s, v1), get_field(s, v2)); + return DISAS_NEXT; +} + +static DisasJumpType op_vlp(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_fn_2(abs, es, get_field(s, v1), get_field(s, v2)); + return DISAS_NEXT; +} + +static DisasJumpType op_vmx(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t v3 = get_field(s, v3); + const uint8_t es = get_field(s, m4); + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0xff: + gen_gvec_fn_3(smax, es, v1, v2, v3); + break; + case 0xfd: + gen_gvec_fn_3(umax, es, v1, v2, v3); + break; + case 0xfe: + gen_gvec_fn_3(smin, es, v1, v2, v3); + break; + case 0xfc: + gen_gvec_fn_3(umin, es, v1, v2, v3); + break; + default: + g_assert_not_reached(); + } + return DISAS_NEXT; +} + +static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_mul_i32(t0, a, b); + tcg_gen_add_i32(d, t0, c); + + tcg_temp_free_i32(t0); +} + +static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(t0, a); + tcg_gen_ext_i32_i64(t1, b); + tcg_gen_ext_i32_i64(t2, c); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_add_i64(t0, t0, t2); + tcg_gen_extrh_i64_i32(d, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} + +static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(t0, a); + tcg_gen_extu_i32_i64(t1, b); + tcg_gen_extu_i32_i64(t2, c); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_add_i64(t0, t0, t2); + tcg_gen_extrh_i64_i32(d, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); +} + +static DisasJumpType op_vma(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m5); + static const GVecGen4 g_vmal[3] = { + { .fno = gen_helper_gvec_vmal8, }, + { .fno = gen_helper_gvec_vmal16, }, + { .fni4 = gen_mal_i32, }, + }; + static const GVecGen4 g_vmah[3] = { + { .fno = gen_helper_gvec_vmah8, }, + { .fno = gen_helper_gvec_vmah16, }, + { .fni4 = gen_mah_i32, }, + }; + static const GVecGen4 g_vmalh[3] = { + { .fno = gen_helper_gvec_vmalh8, }, + { .fno = gen_helper_gvec_vmalh16, }, + { .fni4 = gen_malh_i32, }, + }; + static const GVecGen4 g_vmae[3] = { + { .fno = gen_helper_gvec_vmae8, }, + { .fno = gen_helper_gvec_vmae16, }, + { .fno = gen_helper_gvec_vmae32, }, + }; + static const GVecGen4 g_vmale[3] = { + { .fno = gen_helper_gvec_vmale8, }, + { .fno = gen_helper_gvec_vmale16, }, + { .fno = gen_helper_gvec_vmale32, }, + }; + static const GVecGen4 g_vmao[3] = { + { .fno = gen_helper_gvec_vmao8, }, + { .fno = gen_helper_gvec_vmao16, }, + { .fno = gen_helper_gvec_vmao32, }, + }; + static const GVecGen4 g_vmalo[3] = { + { .fno = gen_helper_gvec_vmalo8, }, + { .fno = gen_helper_gvec_vmalo16, }, + { .fno = gen_helper_gvec_vmalo32, }, + }; + const GVecGen4 *fn; + + if (es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0xaa: + fn = &g_vmal[es]; + break; + case 0xab: + fn = &g_vmah[es]; + break; + case 0xa9: + fn = &g_vmalh[es]; + break; + case 0xae: + fn = &g_vmae[es]; + break; + case 0xac: + fn = &g_vmale[es]; + break; + case 0xaf: + fn = &g_vmao[es]; + break; + case 0xad: + fn = &g_vmalo[es]; + break; + default: + g_assert_not_reached(); + } + + gen_gvec_4(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), fn); + return DISAS_NEXT; +} + +static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(); + + tcg_gen_muls2_i32(t, d, a, b); + tcg_temp_free_i32(t); +} + +static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(); + + tcg_gen_mulu2_i32(t, d, a, b); + tcg_temp_free_i32(t); +} + +static DisasJumpType op_vm(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g_vmh[3] = { + { .fno = gen_helper_gvec_vmh8, }, + { .fno = gen_helper_gvec_vmh16, }, + { .fni4 = gen_mh_i32, }, + }; + static const GVecGen3 g_vmlh[3] = { + { .fno = gen_helper_gvec_vmlh8, }, + { .fno = gen_helper_gvec_vmlh16, }, + { .fni4 = gen_mlh_i32, }, + }; + static const GVecGen3 g_vme[3] = { + { .fno = gen_helper_gvec_vme8, }, + { .fno = gen_helper_gvec_vme16, }, + { .fno = gen_helper_gvec_vme32, }, + }; + static const GVecGen3 g_vmle[3] = { + { .fno = gen_helper_gvec_vmle8, }, + { .fno = gen_helper_gvec_vmle16, }, + { .fno = gen_helper_gvec_vmle32, }, + }; + static const GVecGen3 g_vmo[3] = { + { .fno = gen_helper_gvec_vmo8, }, + { .fno = gen_helper_gvec_vmo16, }, + { .fno = gen_helper_gvec_vmo32, }, + }; + static const GVecGen3 g_vmlo[3] = { + { .fno = gen_helper_gvec_vmlo8, }, + { .fno = gen_helper_gvec_vmlo16, }, + { .fno = gen_helper_gvec_vmlo32, }, + }; + const GVecGen3 *fn; + + if (es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0xa2: + gen_gvec_fn_3(mul, es, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; + case 0xa3: + fn = &g_vmh[es]; + break; + case 0xa1: + fn = &g_vmlh[es]; + break; + case 0xa6: + fn = &g_vme[es]; + break; + case 0xa4: + fn = &g_vmle[es]; + break; + case 0xa7: + fn = &g_vmo[es]; + break; + case 0xa5: + fn = &g_vmlo[es]; + break; + default: + g_assert_not_reached(); + } + + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), fn); + return DISAS_NEXT; +} + +static DisasJumpType op_vnn(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(nand, ES_8, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vno(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(nor, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vnx(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(eqv, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vo(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(or, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_voc(DisasContext *s, DisasOps *o) +{ + gen_gvec_fn_3(orc, ES_8, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m3); + static const GVecGen2 g[4] = { + { .fno = gen_helper_gvec_vpopct8, }, + { .fno = gen_helper_gvec_vpopct16, }, + { .fni4 = tcg_gen_ctpop_i32, }, + { .fni8 = tcg_gen_ctpop_i64, }, + }; + + if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); + return DISAS_NEXT; +} + +static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) +{ + TCGv_i32 t = tcg_temp_new_i32(); + + tcg_gen_rotli_i32(t, a, c & 31); + tcg_gen_and_i32(t, t, b); + tcg_gen_andc_i32(d, d, b); + tcg_gen_or_i32(d, d, t); + + tcg_temp_free_i32(t); +} + +static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) +{ + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_rotli_i64(t, a, c & 63); + tcg_gen_and_i64(t, t, b); + tcg_gen_andc_i64(d, d, b); + tcg_gen_or_i64(d, d, t); + + tcg_temp_free_i64(t); +} + +static DisasJumpType op_verim(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m5); + const uint8_t i4 = get_field(s, i4) & + (NUM_VEC_ELEMENT_BITS(es) - 1); + static const GVecGen3i g[4] = { + { .fno = gen_helper_gvec_verim8, }, + { .fno = gen_helper_gvec_verim16, }, + { .fni4 = gen_rim_i32, + .load_dest = true, }, + { .fni8 = gen_rim_i64, + .load_dest = true, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_3i(get_field(s, v1), get_field(s, v2), + get_field(s, v3), i4, &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_vesv(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t v3 = get_field(s, v3); + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0x70: + gen_gvec_fn_3(shlv, es, v1, v2, v3); + break; + case 0x73: + gen_gvec_fn_3(rotlv, es, v1, v2, v3); + break; + case 0x7a: + gen_gvec_fn_3(sarv, es, v1, v2, v3); + break; + case 0x78: + gen_gvec_fn_3(shrv, es, v1, v2, v3); + break; + default: + g_assert_not_reached(); + } + return DISAS_NEXT; +} + +static DisasJumpType op_ves(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t d2 = get_field(s, d2) & + (NUM_VEC_ELEMENT_BITS(es) - 1); + const uint8_t v1 = get_field(s, v1); + const uint8_t v3 = get_field(s, v3); + TCGv_i32 shift; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (likely(!get_field(s, b2))) { + switch (s->fields.op2) { + case 0x30: + gen_gvec_fn_2i(shli, es, v1, v3, d2); + break; + case 0x33: + gen_gvec_fn_2i(rotli, es, v1, v3, d2); + break; + case 0x3a: + gen_gvec_fn_2i(sari, es, v1, v3, d2); + break; + case 0x38: + gen_gvec_fn_2i(shri, es, v1, v3, d2); + break; + default: + g_assert_not_reached(); + } + } else { + shift = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(shift, o->addr1); + tcg_gen_andi_i32(shift, shift, NUM_VEC_ELEMENT_BITS(es) - 1); + switch (s->fields.op2) { + case 0x30: + gen_gvec_fn_2s(shls, es, v1, v3, shift); + break; + case 0x33: + gen_gvec_fn_2s(rotls, es, v1, v3, shift); + break; + case 0x3a: + gen_gvec_fn_2s(sars, es, v1, v3, shift); + break; + case 0x38: + gen_gvec_fn_2s(shrs, es, v1, v3, shift); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_i32(shift); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vsl(DisasContext *s, DisasOps *o) +{ + TCGv_i64 shift = tcg_temp_new_i64(); + + read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); + if (s->fields.op2 == 0x74) { + tcg_gen_andi_i64(shift, shift, 0x7); + } else { + tcg_gen_andi_i64(shift, shift, 0x78); + } + + gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), + shift, 0, gen_helper_gvec_vsl); + tcg_temp_free_i64(shift); + return DISAS_NEXT; +} + +static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o) +{ + const uint8_t i4 = get_field(s, i4) & 0xf; + const int left_shift = (i4 & 7) * 8; + const int right_shift = 64 - left_shift; + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + if ((i4 & 8) == 0) { + read_vec_element_i64(t0, get_field(s, v2), 0, ES_64); + read_vec_element_i64(t1, get_field(s, v2), 1, ES_64); + read_vec_element_i64(t2, get_field(s, v3), 0, ES_64); + } else { + read_vec_element_i64(t0, get_field(s, v2), 1, ES_64); + read_vec_element_i64(t1, get_field(s, v3), 0, ES_64); + read_vec_element_i64(t2, get_field(s, v3), 1, ES_64); + } + tcg_gen_extract2_i64(t0, t1, t0, right_shift); + tcg_gen_extract2_i64(t1, t2, t1, right_shift); + write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); + write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + return DISAS_NEXT; +} + +static DisasJumpType op_vsra(DisasContext *s, DisasOps *o) +{ + TCGv_i64 shift = tcg_temp_new_i64(); + + read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); + if (s->fields.op2 == 0x7e) { + tcg_gen_andi_i64(shift, shift, 0x7); + } else { + tcg_gen_andi_i64(shift, shift, 0x78); + } + + gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), + shift, 0, gen_helper_gvec_vsra); + tcg_temp_free_i64(shift); + return DISAS_NEXT; +} + +static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o) +{ + TCGv_i64 shift = tcg_temp_new_i64(); + + read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); + if (s->fields.op2 == 0x7c) { + tcg_gen_andi_i64(shift, shift, 0x7); + } else { + tcg_gen_andi_i64(shift, shift, 0x78); + } + + gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), + shift, 0, gen_helper_gvec_vsrl); + tcg_temp_free_i64(shift); + return DISAS_NEXT; +} + +static DisasJumpType op_vs(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + + if (es > ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } else if (es == ES_128) { + gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; + } + gen_gvec_fn_3(sub, es, get_field(s, v1), get_field(s, v2), + get_field(s, v3)); + return DISAS_NEXT; +} + +static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b); +} + +static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_setcond_i64(TCG_COND_GEU, d, a, b); +} + +static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) +{ + TCGv_i64 th = tcg_temp_new_i64(); + TCGv_i64 tl = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); + tcg_gen_andi_i64(th, th, 1); + tcg_gen_sub2_i64(tl, th, ah, zero, th, zero); + tcg_gen_sub2_i64(tl, th, tl, th, bh, zero); + /* "invert" the result: -1 -> 0; 0 -> 1 */ + tcg_gen_addi_i64(dl, th, 1); + tcg_gen_mov_i64(dh, zero); + + tcg_temp_free_i64(th); + tcg_temp_free_i64(tl); + tcg_temp_free_i64(zero); +} + +static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_vscbi8, }, + { .fno = gen_helper_gvec_vscbi16, }, + { .fni4 = gen_scbi_i32, }, + { .fni8 = gen_scbi_i64, }, + }; + + if (es > ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } else if (es == ES_128) { + gen_gvec128_3_i64(gen_scbi2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3)); + return DISAS_NEXT; + } + gen_gvec_3(get_field(s, v1), get_field(s, v2), + get_field(s, v3), &g[es]); + return DISAS_NEXT; +} + +static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) +{ + TCGv_i64 tl = tcg_temp_new_i64(); + TCGv_i64 th = tcg_temp_new_i64(); + + tcg_gen_not_i64(tl, bl); + tcg_gen_not_i64(th, bh); + gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); +} + +static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) +{ + if (get_field(s, m5) != ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_sbi2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3), + get_field(s, v4)); + return DISAS_NEXT; +} + +static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) +{ + TCGv_i64 th = tcg_temp_new_i64(); + TCGv_i64 tl = tcg_temp_new_i64(); + + tcg_gen_not_i64(tl, bl); + tcg_gen_not_i64(th, bh); + gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); + + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); +} + +static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) +{ + if (get_field(s, m5) != ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s, v1), + get_field(s, v2), get_field(s, v3), + get_field(s, v4)); + return DISAS_NEXT; +} + +static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + TCGv_i64 sum, tmp; + uint8_t dst_idx; + + if (es == ES_8 || es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + sum = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); + for (dst_idx = 0; dst_idx < 2; dst_idx++) { + uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2; + const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1; + + read_vec_element_i64(sum, get_field(s, v3), max_idx, es); + for (; idx <= max_idx; idx++) { + read_vec_element_i64(tmp, get_field(s, v2), idx, es); + tcg_gen_add_i64(sum, sum, tmp); + } + write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64); + } + tcg_temp_free_i64(sum); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1; + TCGv_i64 sumh, suml, zero, tmpl; + uint8_t idx; + + if (es < ES_32 || es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + sumh = tcg_const_i64(0); + suml = tcg_temp_new_i64(); + zero = tcg_const_i64(0); + tmpl = tcg_temp_new_i64(); + + read_vec_element_i64(suml, get_field(s, v3), max_idx, es); + for (idx = 0; idx <= max_idx; idx++) { + read_vec_element_i64(tmpl, get_field(s, v2), idx, es); + tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero); + } + write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64); + write_vec_element_i64(suml, get_field(s, v1), 1, ES_64); + + tcg_temp_free_i64(sumh); + tcg_temp_free_i64(suml); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(tmpl); + return DISAS_NEXT; +} + +static DisasJumpType op_vsum(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + TCGv_i32 sum, tmp; + uint8_t dst_idx; + + if (es > ES_16) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + sum = tcg_temp_new_i32(); + tmp = tcg_temp_new_i32(); + for (dst_idx = 0; dst_idx < 4; dst_idx++) { + uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4; + const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1; + + read_vec_element_i32(sum, get_field(s, v3), max_idx, es); + for (; idx <= max_idx; idx++) { + read_vec_element_i32(tmp, get_field(s, v2), idx, es); + tcg_gen_add_i32(sum, sum, tmp); + } + write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32); + } + tcg_temp_free_i32(sum); + tcg_temp_free_i32(tmp); + return DISAS_NEXT; +} + +static DisasJumpType op_vtm(DisasContext *s, DisasOps *o) +{ + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), + cpu_env, 0, gen_helper_gvec_vtm); + set_cc_static(s); + return DISAS_NEXT; +} + +static DisasJumpType op_vfae(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + static gen_helper_gvec_3 * const g[3] = { + gen_helper_gvec_vfae8, + gen_helper_gvec_vfae16, + gen_helper_gvec_vfae32, + }; + static gen_helper_gvec_3_ptr * const g_cc[3] = { + gen_helper_gvec_vfae_cc8, + gen_helper_gvec_vfae_cc16, + gen_helper_gvec_vfae_cc32, + }; + if (es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m5, 0, 1)) { + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), cpu_env, m5, g_cc[es]); + set_cc_static(s); + } else { + gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), m5, g[es]); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vfee(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + static gen_helper_gvec_3 * const g[3] = { + gen_helper_gvec_vfee8, + gen_helper_gvec_vfee16, + gen_helper_gvec_vfee32, + }; + static gen_helper_gvec_3_ptr * const g_cc[3] = { + gen_helper_gvec_vfee_cc8, + gen_helper_gvec_vfee_cc16, + gen_helper_gvec_vfee_cc32, + }; + + if (es > ES_32 || m5 & ~0x3) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m5, 0, 1)) { + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), cpu_env, m5, g_cc[es]); + set_cc_static(s); + } else { + gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), m5, g[es]); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vfene(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + static gen_helper_gvec_3 * const g[3] = { + gen_helper_gvec_vfene8, + gen_helper_gvec_vfene16, + gen_helper_gvec_vfene32, + }; + static gen_helper_gvec_3_ptr * const g_cc[3] = { + gen_helper_gvec_vfene_cc8, + gen_helper_gvec_vfene_cc16, + gen_helper_gvec_vfene_cc32, + }; + + if (es > ES_32 || m5 & ~0x3) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m5, 0, 1)) { + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), cpu_env, m5, g_cc[es]); + set_cc_static(s); + } else { + gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), m5, g[es]); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vistr(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + static gen_helper_gvec_2 * const g[3] = { + gen_helper_gvec_vistr8, + gen_helper_gvec_vistr16, + gen_helper_gvec_vistr32, + }; + static gen_helper_gvec_2_ptr * const g_cc[3] = { + gen_helper_gvec_vistr_cc8, + gen_helper_gvec_vistr_cc16, + gen_helper_gvec_vistr_cc32, + }; + + if (es > ES_32 || m5 & ~0x1) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m5, 0, 1)) { + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), + cpu_env, 0, g_cc[es]); + set_cc_static(s); + } else { + gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0, + g[es]); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s, m5); + const uint8_t m6 = get_field(s, m6); + static gen_helper_gvec_4 * const g[3] = { + gen_helper_gvec_vstrc8, + gen_helper_gvec_vstrc16, + gen_helper_gvec_vstrc32, + }; + static gen_helper_gvec_4 * const g_rt[3] = { + gen_helper_gvec_vstrc_rt8, + gen_helper_gvec_vstrc_rt16, + gen_helper_gvec_vstrc_rt32, + }; + static gen_helper_gvec_4_ptr * const g_cc[3] = { + gen_helper_gvec_vstrc_cc8, + gen_helper_gvec_vstrc_cc16, + gen_helper_gvec_vstrc_cc32, + }; + static gen_helper_gvec_4_ptr * const g_cc_rt[3] = { + gen_helper_gvec_vstrc_cc_rt8, + gen_helper_gvec_vstrc_cc_rt16, + gen_helper_gvec_vstrc_cc_rt32, + }; + + if (es > ES_32) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m6, 0, 1)) { + if (extract32(m6, 2, 1)) { + gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), + cpu_env, m6, g_cc_rt[es]); + } else { + gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), + cpu_env, m6, g_cc[es]); + } + set_cc_static(s); + } else { + if (extract32(m6, 2, 1)) { + gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), + m6, g_rt[es]); + } else { + gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), + m6, g[es]); + } + } + return DISAS_NEXT; +} + +static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + const bool se = extract32(m5, 3, 1); + gen_helper_gvec_3_ptr *fn; + + if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0xe3: + fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64; + break; + case 0xe5: + fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64; + break; + case 0xe7: + fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64; + break; + case 0xe2: + fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64; + break; + default: + g_assert_not_reached(); + } + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), cpu_env, 0, fn); + return DISAS_NEXT; +} + +static DisasJumpType op_wfc(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m3); + const uint8_t m4 = get_field(s, m4); + + if (fpf != FPF_LONG || m4) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (s->fields.op2 == 0xcb) { + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), + cpu_env, 0, gen_helper_gvec_wfc64); + } else { + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), + cpu_env, 0, gen_helper_gvec_wfk64); + } + set_cc_static(s); + return DISAS_NEXT; +} + +static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + const uint8_t m6 = get_field(s, m6); + const bool se = extract32(m5, 3, 1); + const bool cs = extract32(m6, 0, 1); + gen_helper_gvec_3_ptr *fn; + + if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (cs) { + switch (s->fields.op2) { + case 0xe8: + fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc; + break; + case 0xeb: + fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc; + break; + case 0xea: + fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc; + break; + default: + g_assert_not_reached(); + } + } else { + switch (s->fields.op2) { + case 0xe8: + fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64; + break; + case 0xeb: + fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64; + break; + case 0xea: + fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64; + break; + default: + g_assert_not_reached(); + } + } + gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), cpu_env, 0, fn); + if (cs) { + set_cc_static(s); + } + return DISAS_NEXT; +} + +static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m3); + const uint8_t m4 = get_field(s, m4); + const uint8_t erm = get_field(s, m5); + const bool se = extract32(m4, 3, 1); + gen_helper_gvec_2_ptr *fn; + + if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields.op2) { + case 0xc3: + fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; + break; + case 0xc1: + fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64; + break; + case 0xc2: + fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64; + break; + case 0xc0: + fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64; + break; + case 0xc7: + fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64; + break; + case 0xc5: + fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64; + break; + default: + g_assert_not_reached(); + } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, + deposit32(m4, 4, 4, erm), fn); + return DISAS_NEXT; +} + +static DisasJumpType op_vfll(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m3); + const uint8_t m4 = get_field(s, m4); + gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32; + + if (fpf != FPF_SHORT || extract32(m4, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m4, 3, 1)) { + fn = gen_helper_gvec_vfll32s; + } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, + 0, fn); + return DISAS_NEXT; +} + +static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) +{ + const uint8_t m5 = get_field(s, m5); + const uint8_t fpf = get_field(s, m6); + const bool se = extract32(m5, 3, 1); + gen_helper_gvec_4_ptr *fn; + + if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (s->fields.op2 == 0x8f) { + fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64; + } else { + fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64; + } + gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), + get_field(s, v3), get_field(s, v4), cpu_env, + 0, fn); + return DISAS_NEXT; +} + +static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o) +{ + const uint8_t v1 = get_field(s, v1); + const uint8_t v2 = get_field(s, v2); + const uint8_t fpf = get_field(s, m3); + const uint8_t m4 = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + TCGv_i64 tmp; + + if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m4, 3, 1)) { + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, v2, 0, ES_64); + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + tcg_gen_xori_i64(tmp, tmp, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + tcg_gen_ori_i64(tmp, tmp, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1); + break; + } + write_vec_element_i64(tmp, v1, 0, ES_64); + tcg_temp_free_i64(tmp); + } else { + switch (m5) { + case 0: + /* sign bit is inverted (complement) */ + gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63); + break; + case 1: + /* sign bit is set to one (negative) */ + gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63); + break; + case 2: + /* sign bit is set to zero (positive) */ + gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1); + break; + } + } + return DISAS_NEXT; +} + +static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s, m3); + const uint8_t m4 = get_field(s, m4); + gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64; + + if (fpf != FPF_LONG || extract32(m4, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m4, 3, 1)) { + fn = gen_helper_gvec_vfsq64s; + } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, + 0, fn); + return DISAS_NEXT; +} + +static DisasJumpType op_vftci(DisasContext *s, DisasOps *o) +{ + const uint16_t i3 = get_field(s, i3); + const uint8_t fpf = get_field(s, m4); + const uint8_t m5 = get_field(s, m5); + gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64; + + if (fpf != FPF_LONG || extract32(m5, 0, 3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (extract32(m5, 3, 1)) { + fn = gen_helper_gvec_vftci64s; + } + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn); + set_cc_static(s); + return DISAS_NEXT; +} diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c deleted file mode 100644 index eb767f5288..0000000000 --- a/target/s390x/translate_vx.inc.c +++ /dev/null @@ -1,2718 +0,0 @@ -/* - * QEMU TCG support -- s390x vector instruction translation functions - * - * Copyright (C) 2019 Red Hat Inc - * - * Authors: - * David Hildenbrand - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -/* - * For most instructions that use the same element size for reads and - * writes, we can use real gvec vector expansion, which potantially uses - * real host vector instructions. As they only work up to 64 bit elements, - * 128 bit elements (vector is a single element) have to be handled - * differently. Operations that are too complicated to encode via TCG ops - * are handled via gvec ool (out-of-line) handlers. - * - * As soon as instructions use different element sizes for reads and writes - * or access elements "out of their element scope" we expand them manually - * in fancy loops, as gvec expansion does not deal with actual element - * numbers and does also not support access to other elements. - * - * 128 bit elements: - * As we only have i32/i64, such elements have to be loaded into two - * i64 values and can then be processed e.g. by tcg_gen_add2_i64. - * - * Sizes: - * On s390x, the operand size (oprsz) and the maximum size (maxsz) are - * always 16 (128 bit). What gvec code calls "vece", s390x calls "es", - * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only - * 128 bit element size has to be treated in a special way (MO_64 + 1). - * We will use ES_* instead of MO_* for this reason in this file. - * - * CC handling: - * As gvec ool-helpers can currently not return values (besides via - * pointers like vectors or cpu_env), whenever we have to set the CC and - * can't conclude the value from the result vector, we will directly - * set it in "env->cc_op" and mark it as static via set_cc_static()". - * Whenever this is done, the helper writes globals (cc_op). - */ - -#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es)) -#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es)) -#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE) - -#define ES_8 MO_8 -#define ES_16 MO_16 -#define ES_32 MO_32 -#define ES_64 MO_64 -#define ES_128 4 - -/* Floating-Point Format */ -#define FPF_SHORT 2 -#define FPF_LONG 3 -#define FPF_EXT 4 - -static inline bool valid_vec_element(uint8_t enr, MemOp es) -{ - return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1)); -} - -static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr, - MemOp memop) -{ - const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); - - switch (memop) { - case ES_8: - tcg_gen_ld8u_i64(dst, cpu_env, offs); - break; - case ES_16: - tcg_gen_ld16u_i64(dst, cpu_env, offs); - break; - case ES_32: - tcg_gen_ld32u_i64(dst, cpu_env, offs); - break; - case ES_8 | MO_SIGN: - tcg_gen_ld8s_i64(dst, cpu_env, offs); - break; - case ES_16 | MO_SIGN: - tcg_gen_ld16s_i64(dst, cpu_env, offs); - break; - case ES_32 | MO_SIGN: - tcg_gen_ld32s_i64(dst, cpu_env, offs); - break; - case ES_64: - case ES_64 | MO_SIGN: - tcg_gen_ld_i64(dst, cpu_env, offs); - break; - default: - g_assert_not_reached(); - } -} - -static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr, - MemOp memop) -{ - const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); - - switch (memop) { - case ES_8: - tcg_gen_ld8u_i32(dst, cpu_env, offs); - break; - case ES_16: - tcg_gen_ld16u_i32(dst, cpu_env, offs); - break; - case ES_8 | MO_SIGN: - tcg_gen_ld8s_i32(dst, cpu_env, offs); - break; - case ES_16 | MO_SIGN: - tcg_gen_ld16s_i32(dst, cpu_env, offs); - break; - case ES_32: - case ES_32 | MO_SIGN: - tcg_gen_ld_i32(dst, cpu_env, offs); - break; - default: - g_assert_not_reached(); - } -} - -static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, - MemOp memop) -{ - const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); - - switch (memop) { - case ES_8: - tcg_gen_st8_i64(src, cpu_env, offs); - break; - case ES_16: - tcg_gen_st16_i64(src, cpu_env, offs); - break; - case ES_32: - tcg_gen_st32_i64(src, cpu_env, offs); - break; - case ES_64: - tcg_gen_st_i64(src, cpu_env, offs); - break; - default: - g_assert_not_reached(); - } -} - -static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr, - MemOp memop) -{ - const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE); - - switch (memop) { - case ES_8: - tcg_gen_st8_i32(src, cpu_env, offs); - break; - case ES_16: - tcg_gen_st16_i32(src, cpu_env, offs); - break; - case ES_32: - tcg_gen_st_i32(src, cpu_env, offs); - break; - default: - g_assert_not_reached(); - } -} - -static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, - uint8_t es) -{ - TCGv_i64 tmp = tcg_temp_new_i64(); - - /* mask off invalid parts from the element nr */ - tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1); - - /* convert it to an element offset relative to cpu_env (vec_reg_offset() */ - tcg_gen_shli_i64(tmp, tmp, es); -#ifndef HOST_WORDS_BIGENDIAN - tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es)); -#endif - tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg)); - - /* generate the final ptr by adding cpu_env */ - tcg_gen_trunc_i64_ptr(ptr, tmp); - tcg_gen_add_ptr(ptr, ptr, cpu_env); - - tcg_temp_free_i64(tmp); -} - -#define gen_gvec_2(v1, v2, gen) \ - tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - 16, 16, gen) -#define gen_gvec_2s(v1, v2, c, gen) \ - tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - 16, 16, c, gen) -#define gen_gvec_2_ool(v1, v2, data, fn) \ - tcg_gen_gvec_2_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - 16, 16, data, fn) -#define gen_gvec_2i_ool(v1, v2, c, data, fn) \ - tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - c, 16, 16, data, fn) -#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \ - tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - ptr, 16, 16, data, fn) -#define gen_gvec_3(v1, v2, v3, gen) \ - tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), 16, 16, gen) -#define gen_gvec_3_ool(v1, v2, v3, data, fn) \ - tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), 16, 16, data, fn) -#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \ - tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), ptr, 16, 16, data, fn) -#define gen_gvec_3i(v1, v2, v3, c, gen) \ - tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), 16, 16, c, gen) -#define gen_gvec_4(v1, v2, v3, v4, gen) \ - tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ - 16, 16, gen) -#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \ - tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ - 16, 16, data, fn) -#define gen_gvec_4_ptr(v1, v2, v3, v4, ptr, data, fn) \ - tcg_gen_gvec_4_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), vec_full_reg_offset(v4), \ - ptr, 16, 16, data, fn) -#define gen_gvec_dup_i64(es, v1, c) \ - tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c) -#define gen_gvec_mov(v1, v2) \ - tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \ - 16) -#define gen_gvec_dup_imm(es, v1, c) \ - tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c); -#define gen_gvec_fn_2(fn, es, v1, v2) \ - tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - 16, 16) -#define gen_gvec_fn_2i(fn, es, v1, v2, c) \ - tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - c, 16, 16) -#define gen_gvec_fn_2s(fn, es, v1, v2, s) \ - tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - s, 16, 16) -#define gen_gvec_fn_3(fn, es, v1, v2, v3) \ - tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), 16, 16) -#define gen_gvec_fn_4(fn, es, v1, v2, v3, v4) \ - tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ - vec_full_reg_offset(v3), vec_full_reg_offset(v4), 16, 16) - -/* - * Helper to carry out a 128 bit vector computation using 2 i64 values per - * vector. - */ -typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a, - uint8_t b) -{ - TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 dl = tcg_temp_new_i64(); - TCGv_i64 ah = tcg_temp_new_i64(); - TCGv_i64 al = tcg_temp_new_i64(); - TCGv_i64 bh = tcg_temp_new_i64(); - TCGv_i64 bl = tcg_temp_new_i64(); - - read_vec_element_i64(ah, a, 0, ES_64); - read_vec_element_i64(al, a, 1, ES_64); - read_vec_element_i64(bh, b, 0, ES_64); - read_vec_element_i64(bl, b, 1, ES_64); - fn(dl, dh, al, ah, bl, bh); - write_vec_element_i64(dh, d, 0, ES_64); - write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); -} - -typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, - TCGv_i64 cl, TCGv_i64 ch); -static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, - uint8_t b, uint8_t c) -{ - TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 dl = tcg_temp_new_i64(); - TCGv_i64 ah = tcg_temp_new_i64(); - TCGv_i64 al = tcg_temp_new_i64(); - TCGv_i64 bh = tcg_temp_new_i64(); - TCGv_i64 bl = tcg_temp_new_i64(); - TCGv_i64 ch = tcg_temp_new_i64(); - TCGv_i64 cl = tcg_temp_new_i64(); - - read_vec_element_i64(ah, a, 0, ES_64); - read_vec_element_i64(al, a, 1, ES_64); - read_vec_element_i64(bh, b, 0, ES_64); - read_vec_element_i64(bl, b, 1, ES_64); - read_vec_element_i64(ch, c, 0, ES_64); - read_vec_element_i64(cl, c, 1, ES_64); - fn(dl, dh, al, ah, bl, bh, cl, ch); - write_vec_element_i64(dh, d, 0, ES_64); - write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(ch); - tcg_temp_free_i64(cl); -} - -static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, - uint64_t b) -{ - TCGv_i64 bl = tcg_const_i64(b); - TCGv_i64 bh = tcg_const_i64(0); - - tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(bh); -} - -static DisasJumpType op_vge(DisasContext *s, DisasOps *o) -{ - const uint8_t es = s->insn->data; - const uint8_t enr = get_field(s, m3); - TCGv_i64 tmp; - - if (!valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, get_field(s, v2), enr, es); - tcg_gen_add_i64(o->addr1, o->addr1, tmp); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); - - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static uint64_t generate_byte_mask(uint8_t mask) -{ - uint64_t r = 0; - int i; - - for (i = 0; i < 8; i++) { - if ((mask >> i) & 1) { - r |= 0xffull << (i * 8); - } - } - return r; -} - -static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o) -{ - const uint16_t i2 = get_field(s, i2); - - if (i2 == (i2 & 0xff) * 0x0101) { - /* - * Masks for both 64 bit elements of the vector are the same. - * Trust tcg to produce a good constant loading. - */ - gen_gvec_dup_imm(ES_64, get_field(s, v1), - generate_byte_mask(i2 & 0xff)); - } else { - TCGv_i64 t = tcg_temp_new_i64(); - - tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8)); - write_vec_element_i64(t, get_field(s, v1), 0, ES_64); - tcg_gen_movi_i64(t, generate_byte_mask(i2)); - write_vec_element_i64(t, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vgm(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t bits = NUM_VEC_ELEMENT_BITS(es); - const uint8_t i2 = get_field(s, i2) & (bits - 1); - const uint8_t i3 = get_field(s, i3) & (bits - 1); - uint64_t mask = 0; - int i; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - /* generate the mask - take care of wrapping */ - for (i = i2; ; i = (i + 1) % bits) { - mask |= 1ull << (bits - i - 1); - if (i == i3) { - break; - } - } - - gen_gvec_dup_imm(es, get_field(s, v1), mask); - return DISAS_NEXT; -} - -static DisasJumpType op_vl(DisasContext *s, DisasOps *o) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); - write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); - write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); - return DISAS_NEXT; -} - -static DisasJumpType op_vlr(DisasContext *s, DisasOps *o) -{ - gen_gvec_mov(get_field(s, v1), get_field(s, v2)); - return DISAS_NEXT; -} - -static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - TCGv_i64 tmp; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vle(DisasContext *s, DisasOps *o) -{ - const uint8_t es = s->insn->data; - const uint8_t enr = get_field(s, m3); - TCGv_i64 tmp; - - if (!valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vlei(DisasContext *s, DisasOps *o) -{ - const uint8_t es = s->insn->data; - const uint8_t enr = get_field(s, m3); - TCGv_i64 tmp; - - if (!valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_const_i64((int16_t)get_field(s, i2)); - write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - TCGv_ptr ptr; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - /* fast path if we don't need the register content */ - if (!get_field(s, b2)) { - uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1); - - read_vec_element_i64(o->out, get_field(s, v3), enr, es); - return DISAS_NEXT; - } - - ptr = tcg_temp_new_ptr(); - get_vec_element_ptr_i64(ptr, get_field(s, v3), o->addr1, es); - switch (es) { - case ES_8: - tcg_gen_ld8u_i64(o->out, ptr, 0); - break; - case ES_16: - tcg_gen_ld16u_i64(o->out, ptr, 0); - break; - case ES_32: - tcg_gen_ld32u_i64(o->out, ptr, 0); - break; - case ES_64: - tcg_gen_ld_i64(o->out, ptr, 0); - break; - default: - g_assert_not_reached(); - } - tcg_temp_free_ptr(ptr); - - return DISAS_NEXT; -} - -static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) -{ - uint8_t es = get_field(s, m3); - uint8_t enr; - TCGv_i64 t; - - switch (es) { - /* rightmost sub-element of leftmost doubleword */ - case ES_8: - enr = 7; - break; - case ES_16: - enr = 3; - break; - case ES_32: - enr = 1; - break; - case ES_64: - enr = 0; - break; - /* leftmost sub-element of leftmost doubleword */ - case 6: - if (s390_has_feat(S390_FEAT_VECTOR_ENH)) { - es = ES_32; - enr = 0; - break; - } - /* fallthrough */ - default: - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - t = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); - gen_gvec_dup_imm(es, get_field(s, v1), 0); - write_vec_element_i64(t, get_field(s, v1), enr, es); - tcg_temp_free_i64(t); - return DISAS_NEXT; -} - -static DisasJumpType op_vlm(DisasContext *s, DisasOps *o) -{ - const uint8_t v3 = get_field(s, v3); - uint8_t v1 = get_field(s, v1); - TCGv_i64 t0, t1; - - if (v3 < v1 || (v3 - v1 + 1) > 16) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - /* - * Check for possible access exceptions by trying to load the last - * element. The first element will be checked first next. - */ - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8); - tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ); - - for (;; v1++) { - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); - write_vec_element_i64(t1, v1, 0, ES_64); - if (v1 == v3) { - break; - } - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ); - write_vec_element_i64(t1, v1, 1, ES_64); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - } - - /* Store the last element, loaded first */ - write_vec_element_i64(t0, v1, 1, ES_64); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return DISAS_NEXT; -} - -static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o) -{ - const int64_t block_size = (1ull << (get_field(s, m3) + 6)); - const int v1_offs = vec_full_reg_offset(get_field(s, v1)); - TCGv_ptr a0; - TCGv_i64 bytes; - - if (get_field(s, m3) > 6) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - bytes = tcg_temp_new_i64(); - a0 = tcg_temp_new_ptr(); - /* calculate the number of bytes until the next block boundary */ - tcg_gen_ori_i64(bytes, o->addr1, -block_size); - tcg_gen_neg_i64(bytes, bytes); - - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vll(cpu_env, a0, o->addr1, bytes); - tcg_temp_free_i64(bytes); - tcg_temp_free_ptr(a0); - return DISAS_NEXT; -} - -static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - TCGv_ptr ptr; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - /* fast path if we don't need the register content */ - if (!get_field(s, b2)) { - uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1); - - write_vec_element_i64(o->in2, get_field(s, v1), enr, es); - return DISAS_NEXT; - } - - ptr = tcg_temp_new_ptr(); - get_vec_element_ptr_i64(ptr, get_field(s, v1), o->addr1, es); - switch (es) { - case ES_8: - tcg_gen_st8_i64(o->in2, ptr, 0); - break; - case ES_16: - tcg_gen_st16_i64(o->in2, ptr, 0); - break; - case ES_32: - tcg_gen_st32_i64(o->in2, ptr, 0); - break; - case ES_64: - tcg_gen_st_i64(o->in2, ptr, 0); - break; - default: - g_assert_not_reached(); - } - tcg_temp_free_ptr(ptr); - - return DISAS_NEXT; -} - -static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o) -{ - write_vec_element_i64(o->in1, get_field(s, v1), 0, ES_64); - write_vec_element_i64(o->in2, get_field(s, v1), 1, ES_64); - return DISAS_NEXT; -} - -static DisasJumpType op_vll(DisasContext *s, DisasOps *o) -{ - const int v1_offs = vec_full_reg_offset(get_field(s, v1)); - TCGv_ptr a0 = tcg_temp_new_ptr(); - - /* convert highest index into an actual length */ - tcg_gen_addi_i64(o->in2, o->in2, 1); - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vll(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); - return DISAS_NEXT; -} - -static DisasJumpType op_vmr(DisasContext *s, DisasOps *o) -{ - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t v3 = get_field(s, v3); - const uint8_t es = get_field(s, m4); - int dst_idx, src_idx; - TCGv_i64 tmp; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - if (s->fields.op2 == 0x61) { - /* iterate backwards to avoid overwriting data we might need later */ - for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) { - src_idx = dst_idx / 2; - if (dst_idx % 2 == 0) { - read_vec_element_i64(tmp, v2, src_idx, es); - } else { - read_vec_element_i64(tmp, v3, src_idx, es); - } - write_vec_element_i64(tmp, v1, dst_idx, es); - } - } else { - /* iterate forward to avoid overwriting data we might need later */ - for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) { - src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2; - if (dst_idx % 2 == 0) { - read_vec_element_i64(tmp, v2, src_idx, es); - } else { - read_vec_element_i64(tmp, v3, src_idx, es); - } - write_vec_element_i64(tmp, v1, dst_idx, es); - } - } - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vpk(DisasContext *s, DisasOps *o) -{ - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t v3 = get_field(s, v3); - const uint8_t es = get_field(s, m4); - static gen_helper_gvec_3 * const vpk[3] = { - gen_helper_gvec_vpk16, - gen_helper_gvec_vpk32, - gen_helper_gvec_vpk64, - }; - static gen_helper_gvec_3 * const vpks[3] = { - gen_helper_gvec_vpks16, - gen_helper_gvec_vpks32, - gen_helper_gvec_vpks64, - }; - static gen_helper_gvec_3_ptr * const vpks_cc[3] = { - gen_helper_gvec_vpks_cc16, - gen_helper_gvec_vpks_cc32, - gen_helper_gvec_vpks_cc64, - }; - static gen_helper_gvec_3 * const vpkls[3] = { - gen_helper_gvec_vpkls16, - gen_helper_gvec_vpkls32, - gen_helper_gvec_vpkls64, - }; - static gen_helper_gvec_3_ptr * const vpkls_cc[3] = { - gen_helper_gvec_vpkls_cc16, - gen_helper_gvec_vpkls_cc32, - gen_helper_gvec_vpkls_cc64, - }; - - if (es == ES_8 || es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0x97: - if (get_field(s, m5) & 0x1) { - gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]); - set_cc_static(s); - } else { - gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]); - } - break; - case 0x95: - if (get_field(s, m5) & 0x1) { - gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]); - set_cc_static(s); - } else { - gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]); - } - break; - case 0x94: - /* If sources and destination dont't overlap -> fast path */ - if (v1 != v2 && v1 != v3) { - const uint8_t src_es = get_field(s, m4); - const uint8_t dst_es = src_es - 1; - TCGv_i64 tmp = tcg_temp_new_i64(); - int dst_idx, src_idx; - - for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) { - src_idx = dst_idx; - if (src_idx < NUM_VEC_ELEMENTS(src_es)) { - read_vec_element_i64(tmp, v2, src_idx, src_es); - } else { - src_idx -= NUM_VEC_ELEMENTS(src_es); - read_vec_element_i64(tmp, v3, src_idx, src_es); - } - write_vec_element_i64(tmp, v1, dst_idx, dst_es); - } - tcg_temp_free_i64(tmp); - } else { - gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]); - } - break; - default: - g_assert_not_reached(); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vperm(DisasContext *s, DisasOps *o) -{ - gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), - 0, gen_helper_gvec_vperm); - return DISAS_NEXT; -} - -static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o) -{ - const uint8_t i2 = extract32(get_field(s, m4), 2, 1); - const uint8_t i3 = extract32(get_field(s, m4), 0, 1); - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - read_vec_element_i64(t0, get_field(s, v2), i2, ES_64); - read_vec_element_i64(t1, get_field(s, v3), i3, ES_64); - write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); - write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return DISAS_NEXT; -} - -static DisasJumpType op_vrep(DisasContext *s, DisasOps *o) -{ - const uint8_t enr = get_field(s, i2); - const uint8_t es = get_field(s, m4); - - if (es > ES_64 || !valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s, v1)), - vec_reg_offset(get_field(s, v3), enr, es), - 16, 16); - return DISAS_NEXT; -} - -static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o) -{ - const int64_t data = (int16_t)get_field(s, i2); - const uint8_t es = get_field(s, m3); - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_dup_imm(es, get_field(s, v1), data); - return DISAS_NEXT; -} - -static DisasJumpType op_vsce(DisasContext *s, DisasOps *o) -{ - const uint8_t es = s->insn->data; - const uint8_t enr = get_field(s, m3); - TCGv_i64 tmp; - - if (!valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, get_field(s, v2), enr, es); - tcg_gen_add_i64(o->addr1, o->addr1, tmp); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); - - read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vsel(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_4(bitsel, ES_8, get_field(s, v1), - get_field(s, v4), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - int idx1, idx2; - TCGv_i64 tmp; - - switch (es) { - case ES_8: - idx1 = 7; - idx2 = 15; - break; - case ES_16: - idx1 = 3; - idx2 = 7; - break; - case ES_32: - idx1 = 1; - idx2 = 3; - break; - default: - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, get_field(s, v2), idx1, es | MO_SIGN); - write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); - read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN); - write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vst(DisasContext *s, DisasOps *o) -{ - TCGv_i64 tmp = tcg_const_i64(16); - - /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); - - read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vste(DisasContext *s, DisasOps *o) -{ - const uint8_t es = s->insn->data; - const uint8_t enr = get_field(s, m3); - TCGv_i64 tmp; - - if (!valid_vec_element(enr, es)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) -{ - const uint8_t v3 = get_field(s, v3); - uint8_t v1 = get_field(s, v1); - TCGv_i64 tmp; - - while (v3 < v1 || (v3 - v1 + 1) > 16) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - /* Probe write access before actually modifying memory */ - tmp = tcg_const_i64((v3 - v1 + 1) * 16); - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); - - for (;; v1++) { - read_vec_element_i64(tmp, v1, 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - read_vec_element_i64(tmp, v1, 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ); - if (v1 == v3) { - break; - } - gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - } - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vstl(DisasContext *s, DisasOps *o) -{ - const int v1_offs = vec_full_reg_offset(get_field(s, v1)); - TCGv_ptr a0 = tcg_temp_new_ptr(); - - /* convert highest index into an actual length */ - tcg_gen_addi_i64(o->in2, o->in2, 1); - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); - return DISAS_NEXT; -} - -static DisasJumpType op_vup(DisasContext *s, DisasOps *o) -{ - const bool logical = s->fields.op2 == 0xd4 || s->fields.op2 == 0xd5; - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t src_es = get_field(s, m3); - const uint8_t dst_es = src_es + 1; - int dst_idx, src_idx; - TCGv_i64 tmp; - - if (src_es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tmp = tcg_temp_new_i64(); - if (s->fields.op2 == 0xd7 || s->fields.op2 == 0xd5) { - /* iterate backwards to avoid overwriting data we might need later */ - for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) { - src_idx = dst_idx; - read_vec_element_i64(tmp, v2, src_idx, - src_es | (logical ? 0 : MO_SIGN)); - write_vec_element_i64(tmp, v1, dst_idx, dst_es); - } - - } else { - /* iterate forward to avoid overwriting data we might need later */ - for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) { - src_idx = dst_idx + NUM_VEC_ELEMENTS(src_es) / 2; - read_vec_element_i64(tmp, v2, src_idx, - src_es | (logical ? 0 : MO_SIGN)); - write_vec_element_i64(tmp, v1, dst_idx, dst_es); - } - } - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_va(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - - if (es > ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } else if (es == ES_128) { - gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; - } - gen_gvec_fn_3(add, es, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) -{ - const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - TCGv_i64 t3 = tcg_temp_new_i64(); - - /* Calculate the carry into the MSB, ignoring the old MSBs */ - tcg_gen_andc_i64(t1, a, msb_mask); - tcg_gen_andc_i64(t2, b, msb_mask); - tcg_gen_add_i64(t1, t1, t2); - /* Calculate the MSB without any carry into it */ - tcg_gen_xor_i64(t3, a, b); - /* Calculate the carry out of the MSB in the MSB bit position */ - tcg_gen_and_i64(d, a, b); - tcg_gen_and_i64(t1, t1, t3); - tcg_gen_or_i64(d, d, t1); - /* Isolate and shift the carry into position */ - tcg_gen_and_i64(d, d, msb_mask); - tcg_gen_shri_i64(d, d, msb_bit_nr); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); -} - -static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - gen_acc(d, a, b, ES_8); -} - -static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - gen_acc(d, a, b, ES_16); -} - -static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t = tcg_temp_new_i32(); - - tcg_gen_add_i32(t, a, b); - tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b); - tcg_temp_free_i32(t); -} - -static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - TCGv_i64 t = tcg_temp_new_i64(); - - tcg_gen_add_i64(t, a, b); - tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); - tcg_temp_free_i64(t); -} - -static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); - - tcg_gen_add2_i64(tl, th, al, zero, bl, zero); - tcg_gen_add2_i64(tl, th, th, zero, ah, zero); - tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); - tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); -} - -static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g[4] = { - { .fni8 = gen_acc8_i64, }, - { .fni8 = gen_acc16_i64, }, - { .fni4 = gen_acc_i32, }, - { .fni8 = gen_acc_i64, }, - }; - - if (es > ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } else if (es == ES_128) { - gen_gvec128_3_i64(gen_acc2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; - } - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, - TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) -{ - TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_const_i64(0); - - /* extract the carry only */ - tcg_gen_extract_i64(tl, cl, 0, 1); - tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); -} - -static DisasJumpType op_vac(DisasContext *s, DisasOps *o) -{ - if (get_field(s, m5) != ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec128_4_i64(gen_ac2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3), - get_field(s, v4)); - return DISAS_NEXT; -} - -static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, - TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) -{ - TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); - - tcg_gen_andi_i64(tl, cl, 1); - tcg_gen_add2_i64(tl, th, tl, zero, al, zero); - tcg_gen_add2_i64(tl, th, tl, th, bl, zero); - tcg_gen_add2_i64(tl, th, th, zero, ah, zero); - tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); - tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); -} - -static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) -{ - if (get_field(s, m5) != ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec128_4_i64(gen_accc2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3), - get_field(s, v4)); - return DISAS_NEXT; -} - -static DisasJumpType op_vn(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(and, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vnc(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(andc, ES_8, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; -} - -static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - tcg_gen_ext_i32_i64(t0, a); - tcg_gen_ext_i32_i64(t1, b); - tcg_gen_add_i64(t0, t0, t1); - tcg_gen_addi_i64(t0, t0, 1); - tcg_gen_shri_i64(t0, t0, 1); - tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) -{ - TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 ah = tcg_temp_new_i64(); - TCGv_i64 bh = tcg_temp_new_i64(); - - /* extending the sign by one bit is sufficient */ - tcg_gen_extract_i64(ah, al, 63, 1); - tcg_gen_extract_i64(bh, bl, 63, 1); - tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - gen_addi2_i64(dl, dh, dl, dh, 1); - tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(bh); -} - -static DisasJumpType op_vavg(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g[4] = { - { .fno = gen_helper_gvec_vavg8, }, - { .fno = gen_helper_gvec_vavg16, }, - { .fni4 = gen_avg_i32, }, - { .fni8 = gen_avg_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(t0, a); - tcg_gen_extu_i32_i64(t1, b); - tcg_gen_add_i64(t0, t0, t1); - tcg_gen_addi_i64(t0, t0, 1); - tcg_gen_shri_i64(t0, t0, 1); - tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) -{ - TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); - - tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); - gen_addi2_i64(dl, dh, dl, dh, 1); - tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(zero); -} - -static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g[4] = { - { .fno = gen_helper_gvec_vavgl8, }, - { .fno = gen_helper_gvec_vavgl16, }, - { .fni4 = gen_avgl_i32, }, - { .fni8 = gen_avgl_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - TCGv_i32 sum = tcg_temp_new_i32(); - int i; - - read_vec_element_i32(sum, get_field(s, v3), 1, ES_32); - for (i = 0; i < 4; i++) { - read_vec_element_i32(tmp, get_field(s, v2), i, ES_32); - tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp); - } - gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); - write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sum); - return DISAS_NEXT; -} - -static DisasJumpType op_vec(DisasContext *s, DisasOps *o) -{ - uint8_t es = get_field(s, m3); - const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - if (s->fields.op2 == 0xdb) { - es |= MO_SIGN; - } - - o->in1 = tcg_temp_new_i64(); - o->in2 = tcg_temp_new_i64(); - read_vec_element_i64(o->in1, get_field(s, v1), enr, es); - read_vec_element_i64(o->in2, get_field(s, v2), enr, es); - return DISAS_NEXT; -} - -static DisasJumpType op_vc(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - TCGCond cond = s->insn->data; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - tcg_gen_gvec_cmp(cond, es, - vec_full_reg_offset(get_field(s, v1)), - vec_full_reg_offset(get_field(s, v2)), - vec_full_reg_offset(get_field(s, v3)), 16, 16); - if (get_field(s, m5) & 0x1) { - TCGv_i64 low = tcg_temp_new_i64(); - TCGv_i64 high = tcg_temp_new_i64(); - - read_vec_element_i64(high, get_field(s, v1), 0, ES_64); - read_vec_element_i64(low, get_field(s, v1), 1, ES_64); - gen_op_update2_cc_i64(s, CC_OP_VC, low, high); - - tcg_temp_free_i64(low); - tcg_temp_free_i64(high); - } - return DISAS_NEXT; -} - -static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a) -{ - tcg_gen_clzi_i32(d, a, 32); -} - -static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a) -{ - tcg_gen_clzi_i64(d, a, 64); -} - -static DisasJumpType op_vclz(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - static const GVecGen2 g[4] = { - { .fno = gen_helper_gvec_vclz8, }, - { .fno = gen_helper_gvec_vclz16, }, - { .fni4 = gen_clz_i32, }, - { .fni8 = gen_clz_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); - return DISAS_NEXT; -} - -static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a) -{ - tcg_gen_ctzi_i32(d, a, 32); -} - -static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a) -{ - tcg_gen_ctzi_i64(d, a, 64); -} - -static DisasJumpType op_vctz(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - static const GVecGen2 g[4] = { - { .fno = gen_helper_gvec_vctz8, }, - { .fno = gen_helper_gvec_vctz16, }, - { .fni4 = gen_ctz_i32, }, - { .fni8 = gen_ctz_i64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_vx(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(xor, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g[4] = { - { .fno = gen_helper_gvec_vgfm8, }, - { .fno = gen_helper_gvec_vgfm16, }, - { .fno = gen_helper_gvec_vgfm32, }, - { .fno = gen_helper_gvec_vgfm64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m5); - static const GVecGen4 g[4] = { - { .fno = gen_helper_gvec_vgfma8, }, - { .fno = gen_helper_gvec_vgfma16, }, - { .fno = gen_helper_gvec_vgfma32, }, - { .fno = gen_helper_gvec_vgfma64, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - gen_gvec_4(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_vlc(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_fn_2(neg, es, get_field(s, v1), get_field(s, v2)); - return DISAS_NEXT; -} - -static DisasJumpType op_vlp(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_fn_2(abs, es, get_field(s, v1), get_field(s, v2)); - return DISAS_NEXT; -} - -static DisasJumpType op_vmx(DisasContext *s, DisasOps *o) -{ - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t v3 = get_field(s, v3); - const uint8_t es = get_field(s, m4); - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0xff: - gen_gvec_fn_3(smax, es, v1, v2, v3); - break; - case 0xfd: - gen_gvec_fn_3(umax, es, v1, v2, v3); - break; - case 0xfe: - gen_gvec_fn_3(smin, es, v1, v2, v3); - break; - case 0xfc: - gen_gvec_fn_3(umin, es, v1, v2, v3); - break; - default: - g_assert_not_reached(); - } - return DISAS_NEXT; -} - -static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) -{ - TCGv_i32 t0 = tcg_temp_new_i32(); - - tcg_gen_mul_i32(t0, a, b); - tcg_gen_add_i32(d, t0, c); - - tcg_temp_free_i32(t0); -} - -static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - - tcg_gen_ext_i32_i64(t0, a); - tcg_gen_ext_i32_i64(t1, b); - tcg_gen_ext_i32_i64(t2, c); - tcg_gen_mul_i64(t0, t0, t1); - tcg_gen_add_i64(t0, t0, t2); - tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); -} - -static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) -{ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(t0, a); - tcg_gen_extu_i32_i64(t1, b); - tcg_gen_extu_i32_i64(t2, c); - tcg_gen_mul_i64(t0, t0, t1); - tcg_gen_add_i64(t0, t0, t2); - tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); -} - -static DisasJumpType op_vma(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m5); - static const GVecGen4 g_vmal[3] = { - { .fno = gen_helper_gvec_vmal8, }, - { .fno = gen_helper_gvec_vmal16, }, - { .fni4 = gen_mal_i32, }, - }; - static const GVecGen4 g_vmah[3] = { - { .fno = gen_helper_gvec_vmah8, }, - { .fno = gen_helper_gvec_vmah16, }, - { .fni4 = gen_mah_i32, }, - }; - static const GVecGen4 g_vmalh[3] = { - { .fno = gen_helper_gvec_vmalh8, }, - { .fno = gen_helper_gvec_vmalh16, }, - { .fni4 = gen_malh_i32, }, - }; - static const GVecGen4 g_vmae[3] = { - { .fno = gen_helper_gvec_vmae8, }, - { .fno = gen_helper_gvec_vmae16, }, - { .fno = gen_helper_gvec_vmae32, }, - }; - static const GVecGen4 g_vmale[3] = { - { .fno = gen_helper_gvec_vmale8, }, - { .fno = gen_helper_gvec_vmale16, }, - { .fno = gen_helper_gvec_vmale32, }, - }; - static const GVecGen4 g_vmao[3] = { - { .fno = gen_helper_gvec_vmao8, }, - { .fno = gen_helper_gvec_vmao16, }, - { .fno = gen_helper_gvec_vmao32, }, - }; - static const GVecGen4 g_vmalo[3] = { - { .fno = gen_helper_gvec_vmalo8, }, - { .fno = gen_helper_gvec_vmalo16, }, - { .fno = gen_helper_gvec_vmalo32, }, - }; - const GVecGen4 *fn; - - if (es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0xaa: - fn = &g_vmal[es]; - break; - case 0xab: - fn = &g_vmah[es]; - break; - case 0xa9: - fn = &g_vmalh[es]; - break; - case 0xae: - fn = &g_vmae[es]; - break; - case 0xac: - fn = &g_vmale[es]; - break; - case 0xaf: - fn = &g_vmao[es]; - break; - case 0xad: - fn = &g_vmalo[es]; - break; - default: - g_assert_not_reached(); - } - - gen_gvec_4(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), fn); - return DISAS_NEXT; -} - -static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t = tcg_temp_new_i32(); - - tcg_gen_muls2_i32(t, d, a, b); - tcg_temp_free_i32(t); -} - -static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t = tcg_temp_new_i32(); - - tcg_gen_mulu2_i32(t, d, a, b); - tcg_temp_free_i32(t); -} - -static DisasJumpType op_vm(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g_vmh[3] = { - { .fno = gen_helper_gvec_vmh8, }, - { .fno = gen_helper_gvec_vmh16, }, - { .fni4 = gen_mh_i32, }, - }; - static const GVecGen3 g_vmlh[3] = { - { .fno = gen_helper_gvec_vmlh8, }, - { .fno = gen_helper_gvec_vmlh16, }, - { .fni4 = gen_mlh_i32, }, - }; - static const GVecGen3 g_vme[3] = { - { .fno = gen_helper_gvec_vme8, }, - { .fno = gen_helper_gvec_vme16, }, - { .fno = gen_helper_gvec_vme32, }, - }; - static const GVecGen3 g_vmle[3] = { - { .fno = gen_helper_gvec_vmle8, }, - { .fno = gen_helper_gvec_vmle16, }, - { .fno = gen_helper_gvec_vmle32, }, - }; - static const GVecGen3 g_vmo[3] = { - { .fno = gen_helper_gvec_vmo8, }, - { .fno = gen_helper_gvec_vmo16, }, - { .fno = gen_helper_gvec_vmo32, }, - }; - static const GVecGen3 g_vmlo[3] = { - { .fno = gen_helper_gvec_vmlo8, }, - { .fno = gen_helper_gvec_vmlo16, }, - { .fno = gen_helper_gvec_vmlo32, }, - }; - const GVecGen3 *fn; - - if (es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0xa2: - gen_gvec_fn_3(mul, es, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; - case 0xa3: - fn = &g_vmh[es]; - break; - case 0xa1: - fn = &g_vmlh[es]; - break; - case 0xa6: - fn = &g_vme[es]; - break; - case 0xa4: - fn = &g_vmle[es]; - break; - case 0xa7: - fn = &g_vmo[es]; - break; - case 0xa5: - fn = &g_vmlo[es]; - break; - default: - g_assert_not_reached(); - } - - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), fn); - return DISAS_NEXT; -} - -static DisasJumpType op_vnn(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(nand, ES_8, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vno(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(nor, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vnx(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(eqv, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vo(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(or, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_voc(DisasContext *s, DisasOps *o) -{ - gen_gvec_fn_3(orc, ES_8, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m3); - static const GVecGen2 g[4] = { - { .fno = gen_helper_gvec_vpopct8, }, - { .fno = gen_helper_gvec_vpopct16, }, - { .fni4 = tcg_gen_ctpop_i32, }, - { .fni8 = tcg_gen_ctpop_i64, }, - }; - - if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]); - return DISAS_NEXT; -} - -static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) -{ - TCGv_i32 t = tcg_temp_new_i32(); - - tcg_gen_rotli_i32(t, a, c & 31); - tcg_gen_and_i32(t, t, b); - tcg_gen_andc_i32(d, d, b); - tcg_gen_or_i32(d, d, t); - - tcg_temp_free_i32(t); -} - -static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) -{ - TCGv_i64 t = tcg_temp_new_i64(); - - tcg_gen_rotli_i64(t, a, c & 63); - tcg_gen_and_i64(t, t, b); - tcg_gen_andc_i64(d, d, b); - tcg_gen_or_i64(d, d, t); - - tcg_temp_free_i64(t); -} - -static DisasJumpType op_verim(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m5); - const uint8_t i4 = get_field(s, i4) & - (NUM_VEC_ELEMENT_BITS(es) - 1); - static const GVecGen3i g[4] = { - { .fno = gen_helper_gvec_verim8, }, - { .fno = gen_helper_gvec_verim16, }, - { .fni4 = gen_rim_i32, - .load_dest = true, }, - { .fni8 = gen_rim_i64, - .load_dest = true, }, - }; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec_3i(get_field(s, v1), get_field(s, v2), - get_field(s, v3), i4, &g[es]); - return DISAS_NEXT; -} - -static DisasJumpType op_vesv(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t v3 = get_field(s, v3); - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0x70: - gen_gvec_fn_3(shlv, es, v1, v2, v3); - break; - case 0x73: - gen_gvec_fn_3(rotlv, es, v1, v2, v3); - break; - case 0x7a: - gen_gvec_fn_3(sarv, es, v1, v2, v3); - break; - case 0x78: - gen_gvec_fn_3(shrv, es, v1, v2, v3); - break; - default: - g_assert_not_reached(); - } - return DISAS_NEXT; -} - -static DisasJumpType op_ves(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t d2 = get_field(s, d2) & - (NUM_VEC_ELEMENT_BITS(es) - 1); - const uint8_t v1 = get_field(s, v1); - const uint8_t v3 = get_field(s, v3); - TCGv_i32 shift; - - if (es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (likely(!get_field(s, b2))) { - switch (s->fields.op2) { - case 0x30: - gen_gvec_fn_2i(shli, es, v1, v3, d2); - break; - case 0x33: - gen_gvec_fn_2i(rotli, es, v1, v3, d2); - break; - case 0x3a: - gen_gvec_fn_2i(sari, es, v1, v3, d2); - break; - case 0x38: - gen_gvec_fn_2i(shri, es, v1, v3, d2); - break; - default: - g_assert_not_reached(); - } - } else { - shift = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(shift, o->addr1); - tcg_gen_andi_i32(shift, shift, NUM_VEC_ELEMENT_BITS(es) - 1); - switch (s->fields.op2) { - case 0x30: - gen_gvec_fn_2s(shls, es, v1, v3, shift); - break; - case 0x33: - gen_gvec_fn_2s(rotls, es, v1, v3, shift); - break; - case 0x3a: - gen_gvec_fn_2s(sars, es, v1, v3, shift); - break; - case 0x38: - gen_gvec_fn_2s(shrs, es, v1, v3, shift); - break; - default: - g_assert_not_reached(); - } - tcg_temp_free_i32(shift); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vsl(DisasContext *s, DisasOps *o) -{ - TCGv_i64 shift = tcg_temp_new_i64(); - - read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields.op2 == 0x74) { - tcg_gen_andi_i64(shift, shift, 0x7); - } else { - tcg_gen_andi_i64(shift, shift, 0x78); - } - - gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), - shift, 0, gen_helper_gvec_vsl); - tcg_temp_free_i64(shift); - return DISAS_NEXT; -} - -static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o) -{ - const uint8_t i4 = get_field(s, i4) & 0xf; - const int left_shift = (i4 & 7) * 8; - const int right_shift = 64 - left_shift; - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); - - if ((i4 & 8) == 0) { - read_vec_element_i64(t0, get_field(s, v2), 0, ES_64); - read_vec_element_i64(t1, get_field(s, v2), 1, ES_64); - read_vec_element_i64(t2, get_field(s, v3), 0, ES_64); - } else { - read_vec_element_i64(t0, get_field(s, v2), 1, ES_64); - read_vec_element_i64(t1, get_field(s, v3), 0, ES_64); - read_vec_element_i64(t2, get_field(s, v3), 1, ES_64); - } - tcg_gen_extract2_i64(t0, t1, t0, right_shift); - tcg_gen_extract2_i64(t1, t2, t1, right_shift); - write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); - write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - return DISAS_NEXT; -} - -static DisasJumpType op_vsra(DisasContext *s, DisasOps *o) -{ - TCGv_i64 shift = tcg_temp_new_i64(); - - read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields.op2 == 0x7e) { - tcg_gen_andi_i64(shift, shift, 0x7); - } else { - tcg_gen_andi_i64(shift, shift, 0x78); - } - - gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), - shift, 0, gen_helper_gvec_vsra); - tcg_temp_free_i64(shift); - return DISAS_NEXT; -} - -static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o) -{ - TCGv_i64 shift = tcg_temp_new_i64(); - - read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); - if (s->fields.op2 == 0x7c) { - tcg_gen_andi_i64(shift, shift, 0x7); - } else { - tcg_gen_andi_i64(shift, shift, 0x78); - } - - gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), - shift, 0, gen_helper_gvec_vsrl); - tcg_temp_free_i64(shift); - return DISAS_NEXT; -} - -static DisasJumpType op_vs(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - - if (es > ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } else if (es == ES_128) { - gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; - } - gen_gvec_fn_3(sub, es, get_field(s, v1), get_field(s, v2), - get_field(s, v3)); - return DISAS_NEXT; -} - -static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b); -} - -static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_setcond_i64(TCG_COND_GEU, d, a, b); -} - -static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); - - tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); - tcg_gen_andi_i64(th, th, 1); - tcg_gen_sub2_i64(tl, th, ah, zero, th, zero); - tcg_gen_sub2_i64(tl, th, tl, th, bh, zero); - /* "invert" the result: -1 -> 0; 0 -> 1 */ - tcg_gen_addi_i64(dl, th, 1); - tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); -} - -static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - static const GVecGen3 g[4] = { - { .fno = gen_helper_gvec_vscbi8, }, - { .fno = gen_helper_gvec_vscbi16, }, - { .fni4 = gen_scbi_i32, }, - { .fni8 = gen_scbi_i64, }, - }; - - if (es > ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } else if (es == ES_128) { - gen_gvec128_3_i64(gen_scbi2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3)); - return DISAS_NEXT; - } - gen_gvec_3(get_field(s, v1), get_field(s, v2), - get_field(s, v3), &g[es]); - return DISAS_NEXT; -} - -static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, - TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) -{ - TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_temp_new_i64(); - - tcg_gen_not_i64(tl, bl); - tcg_gen_not_i64(th, bh); - gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); -} - -static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) -{ - if (get_field(s, m5) != ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec128_4_i64(gen_sbi2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3), - get_field(s, v4)); - return DISAS_NEXT; -} - -static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, - TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) -{ - TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 tl = tcg_temp_new_i64(); - - tcg_gen_not_i64(tl, bl); - tcg_gen_not_i64(th, bh); - gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); -} - -static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) -{ - if (get_field(s, m5) != ES_128) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s, v1), - get_field(s, v2), get_field(s, v3), - get_field(s, v4)); - return DISAS_NEXT; -} - -static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - TCGv_i64 sum, tmp; - uint8_t dst_idx; - - if (es == ES_8 || es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - sum = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - for (dst_idx = 0; dst_idx < 2; dst_idx++) { - uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2; - const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1; - - read_vec_element_i64(sum, get_field(s, v3), max_idx, es); - for (; idx <= max_idx; idx++) { - read_vec_element_i64(tmp, get_field(s, v2), idx, es); - tcg_gen_add_i64(sum, sum, tmp); - } - write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64); - } - tcg_temp_free_i64(sum); - tcg_temp_free_i64(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1; - TCGv_i64 sumh, suml, zero, tmpl; - uint8_t idx; - - if (es < ES_32 || es > ES_64) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - sumh = tcg_const_i64(0); - suml = tcg_temp_new_i64(); - zero = tcg_const_i64(0); - tmpl = tcg_temp_new_i64(); - - read_vec_element_i64(suml, get_field(s, v3), max_idx, es); - for (idx = 0; idx <= max_idx; idx++) { - read_vec_element_i64(tmpl, get_field(s, v2), idx, es); - tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero); - } - write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64); - write_vec_element_i64(suml, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(sumh); - tcg_temp_free_i64(suml); - tcg_temp_free_i64(zero); - tcg_temp_free_i64(tmpl); - return DISAS_NEXT; -} - -static DisasJumpType op_vsum(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - TCGv_i32 sum, tmp; - uint8_t dst_idx; - - if (es > ES_16) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - sum = tcg_temp_new_i32(); - tmp = tcg_temp_new_i32(); - for (dst_idx = 0; dst_idx < 4; dst_idx++) { - uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4; - const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1; - - read_vec_element_i32(sum, get_field(s, v3), max_idx, es); - for (; idx <= max_idx; idx++) { - read_vec_element_i32(tmp, get_field(s, v2), idx, es); - tcg_gen_add_i32(sum, sum, tmp); - } - write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32); - } - tcg_temp_free_i32(sum); - tcg_temp_free_i32(tmp); - return DISAS_NEXT; -} - -static DisasJumpType op_vtm(DisasContext *s, DisasOps *o) -{ - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_vtm); - set_cc_static(s); - return DISAS_NEXT; -} - -static DisasJumpType op_vfae(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - static gen_helper_gvec_3 * const g[3] = { - gen_helper_gvec_vfae8, - gen_helper_gvec_vfae16, - gen_helper_gvec_vfae32, - }; - static gen_helper_gvec_3_ptr * const g_cc[3] = { - gen_helper_gvec_vfae_cc8, - gen_helper_gvec_vfae_cc16, - gen_helper_gvec_vfae_cc32, - }; - if (es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m5, 0, 1)) { - gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); - set_cc_static(s); - } else { - gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), m5, g[es]); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vfee(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - static gen_helper_gvec_3 * const g[3] = { - gen_helper_gvec_vfee8, - gen_helper_gvec_vfee16, - gen_helper_gvec_vfee32, - }; - static gen_helper_gvec_3_ptr * const g_cc[3] = { - gen_helper_gvec_vfee_cc8, - gen_helper_gvec_vfee_cc16, - gen_helper_gvec_vfee_cc32, - }; - - if (es > ES_32 || m5 & ~0x3) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m5, 0, 1)) { - gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); - set_cc_static(s); - } else { - gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), m5, g[es]); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vfene(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - static gen_helper_gvec_3 * const g[3] = { - gen_helper_gvec_vfene8, - gen_helper_gvec_vfene16, - gen_helper_gvec_vfene32, - }; - static gen_helper_gvec_3_ptr * const g_cc[3] = { - gen_helper_gvec_vfene_cc8, - gen_helper_gvec_vfene_cc16, - gen_helper_gvec_vfene_cc32, - }; - - if (es > ES_32 || m5 & ~0x3) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m5, 0, 1)) { - gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); - set_cc_static(s); - } else { - gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), m5, g[es]); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vistr(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - static gen_helper_gvec_2 * const g[3] = { - gen_helper_gvec_vistr8, - gen_helper_gvec_vistr16, - gen_helper_gvec_vistr32, - }; - static gen_helper_gvec_2_ptr * const g_cc[3] = { - gen_helper_gvec_vistr_cc8, - gen_helper_gvec_vistr_cc16, - gen_helper_gvec_vistr_cc32, - }; - - if (es > ES_32 || m5 & ~0x1) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m5, 0, 1)) { - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, g_cc[es]); - set_cc_static(s); - } else { - gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0, - g[es]); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o) -{ - const uint8_t es = get_field(s, m5); - const uint8_t m6 = get_field(s, m6); - static gen_helper_gvec_4 * const g[3] = { - gen_helper_gvec_vstrc8, - gen_helper_gvec_vstrc16, - gen_helper_gvec_vstrc32, - }; - static gen_helper_gvec_4 * const g_rt[3] = { - gen_helper_gvec_vstrc_rt8, - gen_helper_gvec_vstrc_rt16, - gen_helper_gvec_vstrc_rt32, - }; - static gen_helper_gvec_4_ptr * const g_cc[3] = { - gen_helper_gvec_vstrc_cc8, - gen_helper_gvec_vstrc_cc16, - gen_helper_gvec_vstrc_cc32, - }; - static gen_helper_gvec_4_ptr * const g_cc_rt[3] = { - gen_helper_gvec_vstrc_cc_rt8, - gen_helper_gvec_vstrc_cc_rt16, - gen_helper_gvec_vstrc_cc_rt32, - }; - - if (es > ES_32) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m6, 0, 1)) { - if (extract32(m6, 2, 1)) { - gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), - cpu_env, m6, g_cc_rt[es]); - } else { - gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), - cpu_env, m6, g_cc[es]); - } - set_cc_static(s); - } else { - if (extract32(m6, 2, 1)) { - gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), - m6, g_rt[es]); - } else { - gen_gvec_4_ool(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), - m6, g[es]); - } - } - return DISAS_NEXT; -} - -static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - const bool se = extract32(m5, 3, 1); - gen_helper_gvec_3_ptr *fn; - - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0xe3: - fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64; - break; - case 0xe5: - fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64; - break; - case 0xe7: - fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64; - break; - case 0xe2: - fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64; - break; - default: - g_assert_not_reached(); - } - gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, 0, fn); - return DISAS_NEXT; -} - -static DisasJumpType op_wfc(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m3); - const uint8_t m4 = get_field(s, m4); - - if (fpf != FPF_LONG || m4) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (s->fields.op2 == 0xcb) { - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_wfc64); - } else { - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_wfk64); - } - set_cc_static(s); - return DISAS_NEXT; -} - -static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - const uint8_t m6 = get_field(s, m6); - const bool se = extract32(m5, 3, 1); - const bool cs = extract32(m6, 0, 1); - gen_helper_gvec_3_ptr *fn; - - if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (cs) { - switch (s->fields.op2) { - case 0xe8: - fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc; - break; - case 0xeb: - fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc; - break; - case 0xea: - fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc; - break; - default: - g_assert_not_reached(); - } - } else { - switch (s->fields.op2) { - case 0xe8: - fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64; - break; - case 0xeb: - fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64; - break; - case 0xea: - fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64; - break; - default: - g_assert_not_reached(); - } - } - gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, 0, fn); - if (cs) { - set_cc_static(s); - } - return DISAS_NEXT; -} - -static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m3); - const uint8_t m4 = get_field(s, m4); - const uint8_t erm = get_field(s, m5); - const bool se = extract32(m4, 3, 1); - gen_helper_gvec_2_ptr *fn; - - if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - switch (s->fields.op2) { - case 0xc3: - fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; - break; - case 0xc1: - fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64; - break; - case 0xc2: - fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64; - break; - case 0xc0: - fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64; - break; - case 0xc7: - fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64; - break; - case 0xc5: - fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64; - break; - default: - g_assert_not_reached(); - } - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, - deposit32(m4, 4, 4, erm), fn); - return DISAS_NEXT; -} - -static DisasJumpType op_vfll(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m3); - const uint8_t m4 = get_field(s, m4); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32; - - if (fpf != FPF_SHORT || extract32(m4, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m4, 3, 1)) { - fn = gen_helper_gvec_vfll32s; - } - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, - 0, fn); - return DISAS_NEXT; -} - -static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) -{ - const uint8_t m5 = get_field(s, m5); - const uint8_t fpf = get_field(s, m6); - const bool se = extract32(m5, 3, 1); - gen_helper_gvec_4_ptr *fn; - - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (s->fields.op2 == 0x8f) { - fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64; - } else { - fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64; - } - gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), cpu_env, - 0, fn); - return DISAS_NEXT; -} - -static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o) -{ - const uint8_t v1 = get_field(s, v1); - const uint8_t v2 = get_field(s, v2); - const uint8_t fpf = get_field(s, m3); - const uint8_t m4 = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - TCGv_i64 tmp; - - if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m4, 3, 1)) { - tmp = tcg_temp_new_i64(); - read_vec_element_i64(tmp, v2, 0, ES_64); - switch (m5) { - case 0: - /* sign bit is inverted (complement) */ - tcg_gen_xori_i64(tmp, tmp, 1ull << 63); - break; - case 1: - /* sign bit is set to one (negative) */ - tcg_gen_ori_i64(tmp, tmp, 1ull << 63); - break; - case 2: - /* sign bit is set to zero (positive) */ - tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1); - break; - } - write_vec_element_i64(tmp, v1, 0, ES_64); - tcg_temp_free_i64(tmp); - } else { - switch (m5) { - case 0: - /* sign bit is inverted (complement) */ - gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63); - break; - case 1: - /* sign bit is set to one (negative) */ - gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63); - break; - case 2: - /* sign bit is set to zero (positive) */ - gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1); - break; - } - } - return DISAS_NEXT; -} - -static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o) -{ - const uint8_t fpf = get_field(s, m3); - const uint8_t m4 = get_field(s, m4); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64; - - if (fpf != FPF_LONG || extract32(m4, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m4, 3, 1)) { - fn = gen_helper_gvec_vfsq64s; - } - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, - 0, fn); - return DISAS_NEXT; -} - -static DisasJumpType op_vftci(DisasContext *s, DisasOps *o) -{ - const uint16_t i3 = get_field(s, i3); - const uint8_t fpf = get_field(s, m4); - const uint8_t m5 = get_field(s, m5); - gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64; - - if (fpf != FPF_LONG || extract32(m5, 0, 3)) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - - if (extract32(m5, 3, 1)) { - fn = gen_helper_gvec_vftci64s; - } - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn); - set_cc_static(s); - return DISAS_NEXT; -} diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c index 7851bcb636..c982d09c24 100644 --- a/target/xtensa/core-dc232b.c +++ b/target/xtensa/core-dc232b.c @@ -35,13 +35,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_dc232b -#include "core-dc232b/xtensa-modules.inc.c" +#include "core-dc232b/xtensa-modules.c.inc" static XtensaConfig dc232b __attribute__((unused)) = { .name = "dc232b", .gdb_regmap = { .reg = { -#include "core-dc232b/gdb-config.inc.c" +#include "core-dc232b/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-dc232b/gdb-config.c.inc b/target/xtensa/core-dc232b/gdb-config.c.inc new file mode 100644 index 0000000000..d87168628b --- /dev/null +++ b/target/xtensa/core-dc232b/gdb-config.c.inc @@ -0,0 +1,262 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + + XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, + 0, 0, 0, 0, 0, 0) + XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, + 0, 0, 0, 0, 0, 0) + XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, + 0, 0, 0, 0, 0, 0) + XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, + 0, 0, 0, 0, 0, 0) + XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, + 0, 0, 0, 0, 0, 0) + XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, + 0, 0, 0, 0, 0, 0) + XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, + 0, 0, 0, 0, 0, 0) + XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, + 0, 0, 0, 0, 0, 0) + XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, + 0, 0, 0, 0, 0, 0) + XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, + 0, 0, 0, 0, 0, 0) + XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, + 0, 0, 0, 0, 0, 0) + XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, + 0, 0, 0, 0, 0, 0) + XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, + 0, 0, 0, 0, 0, 0) + XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, + 0, 0, 0, 0, 0, 0) + XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, + 0, 0, 0, 0, 0, 0) + XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, + 0, 0, 0, 0, 0, 0) + XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, + 0, 0, 0, 0, 0, 0) + XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, + 0, 0, 0, 0, 0, 0) + XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, + 0, 0, 0, 0, 0, 0) + XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, + 0, 0, 0, 0, 0, 0) + XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, + 0, 0, 0, 0, 0, 0) + XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, + 0, 0, 0, 0, 0, 0) + XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, + 0, 0, 0, 0, 0, 0) + XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, + 0, 0, 0, 0, 0, 0) + XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, + 0, 0, 0, 0, 0, 0) + XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, + 0, 0, 0, 0, 0, 0) + XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, + 0, 0, 0, 0, 0, 0) + XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, + 0, 0, 0, 0, 0, 0) + XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, + 0, 0, 0, 0, 0, 0) + XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, + 0, 0, 0, 0, 0, 0) + XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, + 0, 0, 0, 0, 0, 0) + XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, + 0, 0, 0, 0, 0, 0) + XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, + 0, 0, 0, 0, 0, 0) + XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, + 0, 0, 0, 0, 0, 0) + XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, + 0, 0, 0, 0, 0, 0) + XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, + 0, 0, 0, 0, 0, 0) + XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, + 0, 0, 0, 0, 0, 0) + XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, + 0, 0, 0, 0, 0, 0) + XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, + 0, 0, 0, 0, 0, 0) + XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, + 0, 0, 0, 0, 0, 0) + XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, + 0, 0, 0, 0, 0, 0) + XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, + 0, 0, 0, 0, 0, 0) + XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, + 0, 0, 0, 0, 0, 0) + XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, + 0, 0, 0, 0, 0, 0) + XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, + 0, 0, 0, 0, 0, 0) + XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, + 0, 0, 0, 0, 0, 0) + XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, + 0, 0, 0, 0, 0, 0) + XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, + 0, 0, 0, 0, 0, 0) + XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, + 0, 0, 0, 0, 0, 0) + XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, + 0, 0, 0, 0, 0, 0) + XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, + 0, 0, 0, 0, 0, 0) + XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, + 0, 0, 0, 0, 0, 0) + XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, + 0, 0, 0, 0, 0, 0) + XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, + 0, 0, 0, 0, 0, 0) + XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, + 0, 0, 0, 0, 0, 0) + XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, + 0, 0, 0, 0, 0, 0) + XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, + 0, 0, 0, 0, 0, 0) + XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, + 0, 0, 0, 0, 0, 0) + XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, + 0, 0, 0, 0, 0, 0) + XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, + 0, 0, 0, 0, 0, 0) + XTREG(60, 240, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, + 0, 0, 0, 0, 0, 0) + XTREG(61, 244, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, + 0, 0, 0, 0, 0, 0) + XTREG(62, 248, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, + 0, 0, 0, 0, 0, 0) + XTREG(63, 252, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, + 0, 0, 0, 0, 0, 0) + XTREG(64, 256, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, + 0, 0, 0, 0, 0, 0) + XTREG(65, 260, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, + 0, 0, 0, 0, 0, 0) + XTREG(66, 264, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, + 0, 0, 0, 0, 0, 0) + XTREG(67, 268, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, + 0, 0, 0, 0, 0, 0) + XTREG(68, 272, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, + 0, 0, 0, 0, 0, 0) + XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, + 0, 0, 0, 0, 0, 0) + XTREG(70, 280, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, + 0, 0, 0, 0, 0, 0) + XTREG(71, 284, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, + 0, 0, 0, 0, 0, 0) + XTREG(72, 288, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, + 0, 0, 0, 0, 0, 0) + XTREG(73, 292, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, + 0, 0, 0, 0, 0, 0) + XTREG(74, 296, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, + 0, 0, 0, 0, 0, 0) + XTREG(75, 300, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, + 0, 0, 0, 0, 0, 0) + XTREG(76, 304, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, + 0, 0, 0, 0, 0, 0) + XTREG(77, 308, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, + 0, 0, 0, 0, 0, 0) + XTREG(78, 312, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, + 0, 0, 0, 0, 0, 0) + XTREG(79, 316, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, + 0, 0, 0, 0, 0, 0) + XTREG(80, 320, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, + 0, 0, 0, 0, 0, 0) + XTREG(81, 324, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, + 0, 0, 0, 0, 0, 0) + XTREG(82, 328, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, + 0, 0, 0, 0, 0, 0) + XTREG(83, 332, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, + 0, 0, 0, 0, 0, 0) + XTREG(84, 336, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, + 0, 0, 0, 0, 0, 0) + XTREG(85, 340, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, + 0, 0, 0, 0, 0, 0) + XTREG(86, 344, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, + 0, 0, 0, 0, 0, 0) + XTREG(87, 348, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, + 0, 0, 0, 0, 0, 0) + XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, + 0, 0, 0, 0, 0, 0) + XTREG(89, 356, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, + 0, 0, 0, 0, 0, 0) + XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, + 0, 0, 0, 0, 0, 0) + XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, + 0, 0, 0, 0, 0, 0) + XTREG(92, 368, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, + 0, 0, 0, 0, 0, 0) + XTREG(93, 372, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, + 0, 0, 0, 0, 0, 0) + XTREG(94, 376, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, + 0, 0, 0, 0, 0, 0) + XTREG(95, 380, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, + 0, 0, 0, 0, 0, 0) + XTREG(96, 384, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, + 0, 0, 0, 0, 0, 0) + XTREG(97, 388, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, + 0, 0, 0, 0, 0, 0) + XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, + 0, 0, 0, 0, 0, 0) + XTREG(99, 396, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, + 0, 0, 0, 0, 0, 0) + XTREG(100, 400, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, + 0, 0, 0, 0, 0, 0) + XTREG(101, 404, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, + 0, 0, 0, 0, 0, 0) + XTREG(102, 408, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, + 0, 0, 0, 0, 0, 0) + XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, + 0, 0, 0, 0, 0, 0) + XTREG(104, 416, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, + 0, 0, 0, 0, 0, 0) + XTREG(105, 420, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, + 0, 0, 0, 0, 0, 0) + XTREG(106, 424, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, + 0, 0, 0, 0, 0, 0) + XTREG(107, 428, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, + 0, 0, 0, 0, 0, 0) + XTREG(108, 432, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, + 0, 0, 0, 0, 0, 0) + XTREG(109, 436, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, + 0, 0, 0, 0, 0, 0) + XTREG(110, 440, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, + 0, 0, 0, 0, 0, 0) + XTREG(111, 444, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, + 0, 0, 0, 0, 0, 0) + XTREG(112, 448, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, + 0, 0, 0, 0, 0, 0) + XTREG(113, 452, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, + 0, 0, 0, 0, 0, 0) + XTREG(114, 456, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, + 0, 0, 0, 0, 0, 0) + XTREG(115, 460, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, + 0, 0, 0, 0, 0, 0) + XTREG(116, 464, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, + 0, 0, 0, 0, 0, 0) + XTREG(117, 468, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, + 0, 0, 0, 0, 0, 0) + XTREG(118, 472, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, + 0, 0, 0, 0, 0, 0) + XTREG(119, 476, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, + 0, 0, 0, 0, 0, 0) + XTREG_END diff --git a/target/xtensa/core-dc232b/gdb-config.inc.c b/target/xtensa/core-dc232b/gdb-config.inc.c deleted file mode 100644 index d87168628b..0000000000 --- a/target/xtensa/core-dc232b/gdb-config.inc.c +++ /dev/null @@ -1,262 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street, Fifth Floor, - Boston, MA 02110-1301, USA. */ - - XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, - 0, 0, 0, 0, 0, 0) - XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, - 0, 0, 0, 0, 0, 0) - XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, - 0, 0, 0, 0, 0, 0) - XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, - 0, 0, 0, 0, 0, 0) - XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, - 0, 0, 0, 0, 0, 0) - XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, - 0, 0, 0, 0, 0, 0) - XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, - 0, 0, 0, 0, 0, 0) - XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, - 0, 0, 0, 0, 0, 0) - XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, - 0, 0, 0, 0, 0, 0) - XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, - 0, 0, 0, 0, 0, 0) - XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, - 0, 0, 0, 0, 0, 0) - XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, - 0, 0, 0, 0, 0, 0) - XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, - 0, 0, 0, 0, 0, 0) - XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, - 0, 0, 0, 0, 0, 0) - XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, - 0, 0, 0, 0, 0, 0) - XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, - 0, 0, 0, 0, 0, 0) - XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, - 0, 0, 0, 0, 0, 0) - XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, - 0, 0, 0, 0, 0, 0) - XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, - 0, 0, 0, 0, 0, 0) - XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, - 0, 0, 0, 0, 0, 0) - XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, - 0, 0, 0, 0, 0, 0) - XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, - 0, 0, 0, 0, 0, 0) - XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, - 0, 0, 0, 0, 0, 0) - XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, - 0, 0, 0, 0, 0, 0) - XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, - 0, 0, 0, 0, 0, 0) - XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, - 0, 0, 0, 0, 0, 0) - XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, - 0, 0, 0, 0, 0, 0) - XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, - 0, 0, 0, 0, 0, 0) - XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, - 0, 0, 0, 0, 0, 0) - XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, - 0, 0, 0, 0, 0, 0) - XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, - 0, 0, 0, 0, 0, 0) - XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, - 0, 0, 0, 0, 0, 0) - XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, - 0, 0, 0, 0, 0, 0) - XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, - 0, 0, 0, 0, 0, 0) - XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, - 0, 0, 0, 0, 0, 0) - XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, - 0, 0, 0, 0, 0, 0) - XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, - 0, 0, 0, 0, 0, 0) - XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, - 0, 0, 0, 0, 0, 0) - XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, - 0, 0, 0, 0, 0, 0) - XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, - 0, 0, 0, 0, 0, 0) - XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, - 0, 0, 0, 0, 0, 0) - XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, - 0, 0, 0, 0, 0, 0) - XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, - 0, 0, 0, 0, 0, 0) - XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, - 0, 0, 0, 0, 0, 0) - XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, - 0, 0, 0, 0, 0, 0) - XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, - 0, 0, 0, 0, 0, 0) - XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, - 0, 0, 0, 0, 0, 0) - XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, - 0, 0, 0, 0, 0, 0) - XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, - 0, 0, 0, 0, 0, 0) - XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, - 0, 0, 0, 0, 0, 0) - XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, - 0, 0, 0, 0, 0, 0) - XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, - 0, 0, 0, 0, 0, 0) - XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, - 0, 0, 0, 0, 0, 0) - XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, - 0, 0, 0, 0, 0, 0) - XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, - 0, 0, 0, 0, 0, 0) - XTREG(55, 220, 18, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, - 0, 0, 0, 0, 0, 0) - XTREG(56, 224, 18, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, - 0, 0, 0, 0, 0, 0) - XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, - 0, 0, 0, 0, 0, 0) - XTREG(58, 232, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, - 0, 0, 0, 0, 0, 0) - XTREG(59, 236, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, - 0, 0, 0, 0, 0, 0) - XTREG(60, 240, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, - 0, 0, 0, 0, 0, 0) - XTREG(61, 244, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, - 0, 0, 0, 0, 0, 0) - XTREG(62, 248, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, - 0, 0, 0, 0, 0, 0) - XTREG(63, 252, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, - 0, 0, 0, 0, 0, 0) - XTREG(64, 256, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, - 0, 0, 0, 0, 0, 0) - XTREG(65, 260, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, - 0, 0, 0, 0, 0, 0) - XTREG(66, 264, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, - 0, 0, 0, 0, 0, 0) - XTREG(67, 268, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, - 0, 0, 0, 0, 0, 0) - XTREG(68, 272, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, - 0, 0, 0, 0, 0, 0) - XTREG(69, 276, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, - 0, 0, 0, 0, 0, 0) - XTREG(70, 280, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, - 0, 0, 0, 0, 0, 0) - XTREG(71, 284, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, - 0, 0, 0, 0, 0, 0) - XTREG(72, 288, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, - 0, 0, 0, 0, 0, 0) - XTREG(73, 292, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, - 0, 0, 0, 0, 0, 0) - XTREG(74, 296, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, - 0, 0, 0, 0, 0, 0) - XTREG(75, 300, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, - 0, 0, 0, 0, 0, 0) - XTREG(76, 304, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, - 0, 0, 0, 0, 0, 0) - XTREG(77, 308, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, - 0, 0, 0, 0, 0, 0) - XTREG(78, 312, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, - 0, 0, 0, 0, 0, 0) - XTREG(79, 316, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, - 0, 0, 0, 0, 0, 0) - XTREG(80, 320, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, - 0, 0, 0, 0, 0, 0) - XTREG(81, 324, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, - 0, 0, 0, 0, 0, 0) - XTREG(82, 328, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, - 0, 0, 0, 0, 0, 0) - XTREG(83, 332, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, - 0, 0, 0, 0, 0, 0) - XTREG(84, 336, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, - 0, 0, 0, 0, 0, 0) - XTREG(85, 340, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, - 0, 0, 0, 0, 0, 0) - XTREG(86, 344, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, - 0, 0, 0, 0, 0, 0) - XTREG(87, 348, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, - 0, 0, 0, 0, 0, 0) - XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, - 0, 0, 0, 0, 0, 0) - XTREG(89, 356, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, - 0, 0, 0, 0, 0, 0) - XTREG(90, 360, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, - 0, 0, 0, 0, 0, 0) - XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, - 0, 0, 0, 0, 0, 0) - XTREG(92, 368, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, - 0, 0, 0, 0, 0, 0) - XTREG(93, 372, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, - 0, 0, 0, 0, 0, 0) - XTREG(94, 376, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, - 0, 0, 0, 0, 0, 0) - XTREG(95, 380, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, - 0, 0, 0, 0, 0, 0) - XTREG(96, 384, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, - 0, 0, 0, 0, 0, 0) - XTREG(97, 388, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, - 0, 0, 0, 0, 0, 0) - XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, - 0, 0, 0, 0, 0, 0) - XTREG(99, 396, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, - 0, 0, 0, 0, 0, 0) - XTREG(100, 400, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, - 0, 0, 0, 0, 0, 0) - XTREG(101, 404, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, - 0, 0, 0, 0, 0, 0) - XTREG(102, 408, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, - 0, 0, 0, 0, 0, 0) - XTREG(103, 412, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, - 0, 0, 0, 0, 0, 0) - XTREG(104, 416, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, - 0, 0, 0, 0, 0, 0) - XTREG(105, 420, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, - 0, 0, 0, 0, 0, 0) - XTREG(106, 424, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, - 0, 0, 0, 0, 0, 0) - XTREG(107, 428, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, - 0, 0, 0, 0, 0, 0) - XTREG(108, 432, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, - 0, 0, 0, 0, 0, 0) - XTREG(109, 436, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, - 0, 0, 0, 0, 0, 0) - XTREG(110, 440, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, - 0, 0, 0, 0, 0, 0) - XTREG(111, 444, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, - 0, 0, 0, 0, 0, 0) - XTREG(112, 448, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, - 0, 0, 0, 0, 0, 0) - XTREG(113, 452, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, - 0, 0, 0, 0, 0, 0) - XTREG(114, 456, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, - 0, 0, 0, 0, 0, 0) - XTREG(115, 460, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, - 0, 0, 0, 0, 0, 0) - XTREG(116, 464, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, - 0, 0, 0, 0, 0, 0) - XTREG(117, 468, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, - 0, 0, 0, 0, 0, 0) - XTREG(118, 472, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, - 0, 0, 0, 0, 0, 0) - XTREG(119, 476, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, - 0, 0, 0, 0, 0, 0) - XTREG_END diff --git a/target/xtensa/core-dc232b/xtensa-modules.c.inc b/target/xtensa/core-dc232b/xtensa-modules.c.inc new file mode 100644 index 0000000000..164df3b1a4 --- /dev/null +++ b/target/xtensa/core-dc232b/xtensa-modules.c.inc @@ -0,0 +1,14078 @@ +/* Xtensa configuration-specific ISA information. + Copyright 2003, 2004, 2005 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "qemu/osdep.h" +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "THREADPTR", 231, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 70 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 73 + +/* Macros for xtensa_state numbers (for use in iclasses because the + state numbers are not available when the iclass table is generated). */ + +#define STATE_LCOUNT 0 +#define STATE_PC 1 +#define STATE_ICOUNT 2 +#define STATE_DDR 3 +#define STATE_INTERRUPT 4 +#define STATE_CCOUNT 5 +#define STATE_XTSYNC 6 +#define STATE_VECBASE 7 +#define STATE_EPC1 8 +#define STATE_EPC2 9 +#define STATE_EPC3 10 +#define STATE_EPC4 11 +#define STATE_EPC5 12 +#define STATE_EPC6 13 +#define STATE_EPC7 14 +#define STATE_EXCSAVE1 15 +#define STATE_EXCSAVE2 16 +#define STATE_EXCSAVE3 17 +#define STATE_EXCSAVE4 18 +#define STATE_EXCSAVE5 19 +#define STATE_EXCSAVE6 20 +#define STATE_EXCSAVE7 21 +#define STATE_EPS2 22 +#define STATE_EPS3 23 +#define STATE_EPS4 24 +#define STATE_EPS5 25 +#define STATE_EPS6 26 +#define STATE_EPS7 27 +#define STATE_EXCCAUSE 28 +#define STATE_PSINTLEVEL 29 +#define STATE_PSUM 30 +#define STATE_PSWOE 31 +#define STATE_PSRING 32 +#define STATE_PSEXCM 33 +#define STATE_DEPC 34 +#define STATE_EXCVADDR 35 +#define STATE_WindowBase 36 +#define STATE_WindowStart 37 +#define STATE_PSCALLINC 38 +#define STATE_PSOWB 39 +#define STATE_LBEG 40 +#define STATE_LEND 41 +#define STATE_SAR 42 +#define STATE_THREADPTR 43 +#define STATE_LITBADDR 44 +#define STATE_LITBEN 45 +#define STATE_MISC0 46 +#define STATE_MISC1 47 +#define STATE_ACC 48 +#define STATE_InOCDMode 49 +#define STATE_INTENABLE 50 +#define STATE_DBREAKA0 51 +#define STATE_DBREAKC0 52 +#define STATE_DBREAKA1 53 +#define STATE_DBREAKC1 54 +#define STATE_IBREAKA0 55 +#define STATE_IBREAKA1 56 +#define STATE_IBREAKENABLE 57 +#define STATE_ICOUNTLEVEL 58 +#define STATE_DEBUGCAUSE 59 +#define STATE_DBNUM 60 +#define STATE_CCOMPARE0 61 +#define STATE_CCOMPARE1 62 +#define STATE_CCOMPARE2 63 +#define STATE_ASID3 64 +#define STATE_ASID2 65 +#define STATE_ASID1 66 +#define STATE_INSTPGSZID4 67 +#define STATE_DATAPGSZID4 68 +#define STATE_PTBASE 69 +#define STATE_CPENABLE 70 +#define STATE_SCOMPARE1 71 +#define STATE_EXPSTATE 72 + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", 0, 32, 32 }, + { "MR", "m", 1, 32, 4 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mx_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_my_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +Operand_my_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mw_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr0_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr1_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr2_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr3_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static int +Operand_tp7_decode (uint32 *valp) +{ + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; +} + +static int +Operand_tp7_encode (uint32 *valp) +{ + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; +} + +static int +Operand_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; +} + +static int +Operand_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", 3, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", 26, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", 14, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", 0, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", 48, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", 49, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", 50, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", 51, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", 14, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", 14, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", 34, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", 33, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", 0, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", 14, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", 14, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", 4, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", 4, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", 4, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", 13, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", 4, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", 4, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", 6, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", 18, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", 13, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", 3, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", 7, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "mx", 43, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_mx_encode, Operand_mx_decode, + 0, 0 }, + { "my", 42, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_my_encode, Operand_my_decode, + 0, 0 }, + { "mw", 41, 1, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_mw_encode, Operand_mw_decode, + 0, 0 }, + { "mr0", 52, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr0_encode, Operand_mr0_decode, + 0, 0 }, + { "mr1", 53, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr1_encode, Operand_mr1_decode, + 0, 0 }, + { "mr2", 54, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr2_encode, Operand_mr2_decode, + 0, 0 }, + { "mr3", 55, 1, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr3_encode, Operand_mr3_decode, + 0, 0 }, + { "immt", 0, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", 5, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "tp7", 0, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", 44, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", 45, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, + { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, + { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, + { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, + { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, + { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, + { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, + { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, + { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, + { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, + { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 }, + { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 } +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { 11 /* ars_entry */ }, 's' }, + { { 4 /* ars */ }, 'i' }, + { { 1 /* uimm12x8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { 2 /* simm4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 16 /* ai4const */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 15 /* uimm6 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { 4 /* ars */ }, 'o' }, + { { 14 /* simm7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { 3 /* arr */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 23 /* simm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 24 /* simm8x256 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 17 /* b4const */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 47 /* bbi */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 18 /* b4constu */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 30 /* label12 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 62 /* sae */ }, 'i' }, + { { 27 /* op2p1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { 31 /* soffset */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { 6 /* art */ }, 'o' }, + { { 32 /* uimm16x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 25 /* simm12b */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { 3 /* arr */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { 66 /* sas */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 26 /* msalp32 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 64 /* sargt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { 6 /* art */ }, 'o' }, + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' }, + { { 33 /* mx */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' }, + { { 33 /* mx */ }, 'i' }, + { { 34 /* my */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { 35 /* mw */ }, 'o' }, + { { 4 /* ars */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { 6 /* art */ }, 'o' }, + { { 36 /* mr0 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { 6 /* art */ }, 'i' }, + { { 36 /* mr0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { 6 /* art */ }, 'm' }, + { { 36 /* mr0 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { 6 /* art */ }, 'o' }, + { { 37 /* mr1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { 6 /* art */ }, 'i' }, + { { 37 /* mr1 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { 6 /* art */ }, 'm' }, + { { 37 /* mr1 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { 6 /* art */ }, 'o' }, + { { 38 /* mr2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { 6 /* art */ }, 'i' }, + { { 38 /* mr2 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { 6 /* art */ }, 'm' }, + { { 38 /* mr2 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { 6 /* art */ }, 'o' }, + { { 39 /* mr3 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { 6 /* art */ }, 'i' }, + { { 39 /* mr3 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { 6 /* art */ }, 'm' }, + { { 39 /* mr3 */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { 50 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { 41 /* imms */ }, 'i' }, + { { 40 /* immt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { 41 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { 41 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 42 /* tp7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 42 /* tp7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { 6 /* art */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { 3 /* arr */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + 0 /* IMPWIRE */ +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { 91 /* bitindex */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { 91 /* bitindex */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_mul16_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", 0 /* xt_iclass_excw */, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", 1 /* xt_iclass_rfe */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", 2 /* xt_iclass_rfde */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", 3 /* xt_iclass_syscall */, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", 4 /* xt_iclass_simcall */, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", 5 /* xt_iclass_call12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", 6 /* xt_iclass_call8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", 7 /* xt_iclass_call4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", 8 /* xt_iclass_callx12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", 9 /* xt_iclass_callx8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", 10 /* xt_iclass_callx4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", 11 /* xt_iclass_entry */, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", 12 /* xt_iclass_movsp */, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", 13 /* xt_iclass_rotw */, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", 16 /* xt_iclass_l32e */, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", 17 /* xt_iclass_s32e */, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", 24 /* xt_iclass_add.n */, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", 25 /* xt_iclass_addi.n */, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", 27 /* xt_iclass_ill.n */, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", 28 /* xt_iclass_loadi4 */, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", 29 /* xt_iclass_mov.n */, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", 30 /* xt_iclass_movi.n */, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", 31 /* xt_iclass_nopn */, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", 32 /* xt_iclass_retn */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", 33 /* xt_iclass_storei4 */, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", 34 /* rur_threadptr */, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", 35 /* wur_threadptr */, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", 36 /* xt_iclass_addi */, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", 37 /* xt_iclass_addmi */, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", 38 /* xt_iclass_addsub */, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", 38 /* xt_iclass_addsub */, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", 38 /* xt_iclass_addsub */, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", 39 /* xt_iclass_bit */, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", 39 /* xt_iclass_bit */, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", 39 /* xt_iclass_bit */, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", 40 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", 41 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", 42 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", 43 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", 44 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", 45 /* xt_iclass_call0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", 46 /* xt_iclass_callx0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", 47 /* xt_iclass_exti */, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", 48 /* xt_iclass_ill */, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", 49 /* xt_iclass_jump */, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", 50 /* xt_iclass_jumpx */, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", 51 /* xt_iclass_l16ui */, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", 52 /* xt_iclass_l16si */, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", 53 /* xt_iclass_l32i */, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", 54 /* xt_iclass_l32r */, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", 55 /* xt_iclass_l8i */, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", 56 /* xt_iclass_loop */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", 57 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", 58 /* xt_iclass_movi */, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", 59 /* xt_iclass_movz */, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", 59 /* xt_iclass_movz */, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", 59 /* xt_iclass_movz */, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", 59 /* xt_iclass_movz */, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", 60 /* xt_iclass_neg */, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", 60 /* xt_iclass_neg */, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", 61 /* xt_iclass_nop */, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", 62 /* xt_iclass_return */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", 63 /* xt_iclass_s16i */, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", 64 /* xt_iclass_s32i */, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", 65 /* xt_iclass_s8i */, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", 66 /* xt_iclass_sar */, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", 66 /* xt_iclass_sar */, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", 66 /* xt_iclass_sar */, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", 67 /* xt_iclass_sari */, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", 68 /* xt_iclass_shifts */, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", 69 /* xt_iclass_shiftst */, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", 70 /* xt_iclass_shiftt */, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", 70 /* xt_iclass_shiftt */, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", 71 /* xt_iclass_slli */, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", 72 /* xt_iclass_srai */, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", 73 /* xt_iclass_srli */, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", 74 /* xt_iclass_memw */, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", 75 /* xt_iclass_extw */, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", 76 /* xt_iclass_isync */, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", 77 /* xt_iclass_sync */, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", 77 /* xt_iclass_sync */, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", 77 /* xt_iclass_sync */, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", 78 /* xt_iclass_rsil */, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", 79 /* xt_iclass_rsr.lend */, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", 80 /* xt_iclass_wsr.lend */, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", 81 /* xt_iclass_xsr.lend */, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", 88 /* xt_iclass_rsr.sar */, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", 89 /* xt_iclass_wsr.sar */, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", 90 /* xt_iclass_xsr.sar */, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", 94 /* xt_iclass_rsr.176 */, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "rsr.208", 95 /* xt_iclass_rsr.208 */, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", 96 /* xt_iclass_rsr.ps */, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", 97 /* xt_iclass_wsr.ps */, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", 98 /* xt_iclass_xsr.ps */, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", 162 /* xt_iclass_rsr.depc */, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", 163 /* xt_iclass_wsr.depc */, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", 164 /* xt_iclass_xsr.depc */, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", 174 /* xt_iclass_rsr.prid */, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", 180 /* xt_iclass_mac16_da */, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", 184 /* xt_iclass_mac16a_da */, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", 188 /* xt_iclass_mac16_l */, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", 188 /* xt_iclass_mac16_l */, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "mul16u", 189 /* xt_iclass_mul16 */, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", 189 /* xt_iclass_mul16 */, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "rsr.m0", 190 /* xt_iclass_rsr.m0 */, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", 191 /* xt_iclass_wsr.m0 */, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", 192 /* xt_iclass_xsr.m0 */, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", 193 /* xt_iclass_rsr.m1 */, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", 194 /* xt_iclass_wsr.m1 */, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", 195 /* xt_iclass_xsr.m1 */, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", 196 /* xt_iclass_rsr.m2 */, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", 197 /* xt_iclass_wsr.m2 */, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", 198 /* xt_iclass_xsr.m2 */, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", 199 /* xt_iclass_rsr.m3 */, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", 200 /* xt_iclass_wsr.m3 */, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", 201 /* xt_iclass_xsr.m3 */, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", 208 /* xt_iclass_rfi */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", 209 /* xt_iclass_wait */, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", 211 /* xt_iclass_wsr.intset */, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", 216 /* xt_iclass_break */, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", 217 /* xt_iclass_break.n */, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", 242 /* xt_iclass_rsr.icount */, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", 243 /* xt_iclass_wsr.icount */, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", 244 /* xt_iclass_xsr.icount */, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", 251 /* xt_iclass_rfdo */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", 252 /* xt_iclass_rfdd */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", 266 /* xt_iclass_icache */, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", 266 /* xt_iclass_icache */, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", 267 /* xt_iclass_icache_lock */, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", 268 /* xt_iclass_icache_inv */, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", 269 /* xt_iclass_licx */, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", 269 /* xt_iclass_licx */, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", 270 /* xt_iclass_sicx */, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", 270 /* xt_iclass_sicx */, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", 271 /* xt_iclass_dcache */, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", 271 /* xt_iclass_dcache */, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", 272 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", 272 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", 273 /* xt_iclass_dcache_inv */, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", 273 /* xt_iclass_dcache_inv */, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", 274 /* xt_iclass_dpf */, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", 275 /* xt_iclass_dcache_lock */, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", 276 /* xt_iclass_sdct */, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", 277 /* xt_iclass_ldct */, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", 290 /* xt_iclass_idtlb */, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", 291 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", 292 /* xt_iclass_wdtlb */, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", 293 /* xt_iclass_iitlb */, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", 294 /* xt_iclass_ritlb */, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", 294 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", 294 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", 295 /* xt_iclass_witlb */, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", 296 /* xt_iclass_ldpte */, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", 297 /* xt_iclass_hwwitlba */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", 302 /* xt_iclass_clamp */, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", 303 /* xt_iclass_minmax */, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", 303 /* xt_iclass_minmax */, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", 303 /* xt_iclass_minmax */, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", 303 /* xt_iclass_minmax */, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", 304 /* xt_iclass_nsa */, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", 304 /* xt_iclass_nsa */, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", 305 /* xt_iclass_sx */, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", 306 /* xt_iclass_l32ai */, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", 307 /* xt_iclass_s32ri */, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", 308 /* xt_iclass_s32c1i */, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "quou", 312 /* xt_iclass_div */, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", 312 /* xt_iclass_div */, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", 312 /* xt_iclass_div */, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", 312 /* xt_iclass_div */, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "mull", 313 /* xt_mul32 */, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rur.expstate", 314 /* rur_expstate */, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", 315 /* wur_expstate */, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", 316 /* iclass_READ_IMPWIRE */, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 79; /* ill */ + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 98; /* ret */ + case 1: + return 14; /* retw */ + case 2: + return 81; /* jx */ + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 77; /* callx0 */ + case 1: + return 10; /* callx4 */ + case 2: + return 9; /* callx8 */ + case 3: + return 8; /* callx12 */ + } + break; + } + break; + case 1: + return 12; /* movsp */ + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 116; /* isync */ + case 1: + return 117; /* rsync */ + case 2: + return 118; /* esync */ + case 3: + return 119; /* dsync */ + case 8: + return 0; /* excw */ + case 12: + return 114; /* memw */ + case 13: + return 115; /* extw */ + case 15: + return 97; /* nop */ + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 1; /* rfe */ + case 2: + return 2; /* rfde */ + case 4: + return 16; /* rfwo */ + case 5: + return 17; /* rfwu */ + } + break; + case 1: + return 310; /* rfi */ + } + break; + case 4: + return 318; /* break */ + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 3; /* syscall */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 4; /* simcall */ + break; + } + break; + case 6: + return 120; /* rsil */ + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return 311; /* waiti */ + break; + } + break; + case 1: + return 49; /* and */ + case 2: + return 50; /* or */ + case 3: + return 51; /* xor */ + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 102; /* ssr */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 103; /* ssl */ + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return 104; /* ssa8l */ + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return 105; /* ssa8b */ + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return 106; /* ssai */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return 13; /* rotw */ + break; + case 14: + return 426; /* nsa */ + case 15: + return 427; /* nsau */ + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return 416; /* hwwitlba */ + case 3: + return 412; /* ritlb0 */ + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return 410; /* iitlb */ + break; + case 5: + return 411; /* pitlb */ + case 6: + return 414; /* witlb */ + case 7: + return 413; /* ritlb1 */ + case 9: + return 417; /* hwwdtlba */ + case 11: + return 407; /* rdtlb0 */ + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return 405; /* idtlb */ + break; + case 13: + return 406; /* pdtlb */ + case 14: + return 409; /* wdtlb */ + case 15: + return 408; /* rdtlb1 */ + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 95; /* neg */ + case 1: + return 96; /* abs */ + } + break; + case 8: + return 41; /* add */ + case 9: + return 43; /* addx2 */ + case 10: + return 44; /* addx4 */ + case 11: + return 45; /* addx8 */ + case 12: + return 42; /* sub */ + case 13: + return 46; /* subx2 */ + case 14: + return 47; /* subx4 */ + case 15: + return 48; /* subx8 */ + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return 111; /* slli */ + case 2: + case 3: + return 112; /* srai */ + case 4: + return 113; /* srli */ + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 129; /* xsr.lbeg */ + case 1: + return 123; /* xsr.lend */ + case 2: + return 126; /* xsr.lcount */ + case 3: + return 132; /* xsr.sar */ + case 5: + return 135; /* xsr.litbase */ + case 12: + return 434; /* xsr.scompare1 */ + case 16: + return 306; /* xsr.acclo */ + case 17: + return 309; /* xsr.acchi */ + case 32: + return 294; /* xsr.m0 */ + case 33: + return 297; /* xsr.m1 */ + case 34: + return 300; /* xsr.m2 */ + case 35: + return 303; /* xsr.m3 */ + case 72: + return 22; /* xsr.windowbase */ + case 73: + return 25; /* xsr.windowstart */ + case 83: + return 395; /* xsr.ptevaddr */ + case 90: + return 398; /* xsr.rasid */ + case 91: + return 401; /* xsr.itlbcfg */ + case 92: + return 404; /* xsr.dtlbcfg */ + case 96: + return 340; /* xsr.ibreakenable */ + case 104: + return 352; /* xsr.ddr */ + case 128: + return 334; /* xsr.ibreaka0 */ + case 129: + return 337; /* xsr.ibreaka1 */ + case 144: + return 322; /* xsr.dbreaka0 */ + case 145: + return 328; /* xsr.dbreaka1 */ + case 160: + return 325; /* xsr.dbreakc0 */ + case 161: + return 331; /* xsr.dbreakc1 */ + case 177: + return 143; /* xsr.epc1 */ + case 178: + return 149; /* xsr.epc2 */ + case 179: + return 155; /* xsr.epc3 */ + case 180: + return 161; /* xsr.epc4 */ + case 181: + return 167; /* xsr.epc5 */ + case 182: + return 173; /* xsr.epc6 */ + case 183: + return 179; /* xsr.epc7 */ + case 192: + return 206; /* xsr.depc */ + case 194: + return 185; /* xsr.eps2 */ + case 195: + return 188; /* xsr.eps3 */ + case 196: + return 191; /* xsr.eps4 */ + case 197: + return 194; /* xsr.eps5 */ + case 198: + return 197; /* xsr.eps6 */ + case 199: + return 200; /* xsr.eps7 */ + case 209: + return 146; /* xsr.excsave1 */ + case 210: + return 152; /* xsr.excsave2 */ + case 211: + return 158; /* xsr.excsave3 */ + case 212: + return 164; /* xsr.excsave4 */ + case 213: + return 170; /* xsr.excsave5 */ + case 214: + return 176; /* xsr.excsave6 */ + case 215: + return 182; /* xsr.excsave7 */ + case 224: + return 420; /* xsr.cpenable */ + case 228: + return 317; /* xsr.intenable */ + case 230: + return 140; /* xsr.ps */ + case 231: + return 219; /* xsr.vecbase */ + case 232: + return 209; /* xsr.exccause */ + case 233: + return 343; /* xsr.debugcause */ + case 234: + return 358; /* xsr.ccount */ + case 236: + return 346; /* xsr.icount */ + case 237: + return 349; /* xsr.icountlevel */ + case 238: + return 203; /* xsr.excvaddr */ + case 240: + return 361; /* xsr.ccompare0 */ + case 241: + return 364; /* xsr.ccompare1 */ + case 242: + return 367; /* xsr.ccompare2 */ + case 244: + return 212; /* xsr.misc0 */ + case 245: + return 215; /* xsr.misc1 */ + } + break; + case 8: + return 108; /* src */ + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return 109; /* srl */ + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return 107; /* sll */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return 110; /* sra */ + break; + case 12: + return 290; /* mul16u */ + case 13: + return 291; /* mul16s */ + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 374; /* lict */ + case 1: + return 376; /* sict */ + case 2: + return 375; /* licw */ + case 3: + return 377; /* sicw */ + case 8: + return 392; /* ldct */ + case 9: + return 391; /* sdct */ + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return 353; /* rfdo */ + if (Field_t_Slot_inst_get (insn) == 1) + return 354; /* rfdd */ + break; + case 15: + return 415; /* ldpte */ + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 8: + return 439; /* mull */ + case 12: + return 435; /* quou */ + case 13: + return 436; /* quos */ + case 14: + return 437; /* remu */ + case 15: + return 438; /* rems */ + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 127; /* rsr.lbeg */ + case 1: + return 121; /* rsr.lend */ + case 2: + return 124; /* rsr.lcount */ + case 3: + return 130; /* rsr.sar */ + case 5: + return 133; /* rsr.litbase */ + case 12: + return 432; /* rsr.scompare1 */ + case 16: + return 304; /* rsr.acclo */ + case 17: + return 307; /* rsr.acchi */ + case 32: + return 292; /* rsr.m0 */ + case 33: + return 295; /* rsr.m1 */ + case 34: + return 298; /* rsr.m2 */ + case 35: + return 301; /* rsr.m3 */ + case 72: + return 20; /* rsr.windowbase */ + case 73: + return 23; /* rsr.windowstart */ + case 83: + return 394; /* rsr.ptevaddr */ + case 90: + return 396; /* rsr.rasid */ + case 91: + return 399; /* rsr.itlbcfg */ + case 92: + return 402; /* rsr.dtlbcfg */ + case 96: + return 338; /* rsr.ibreakenable */ + case 104: + return 350; /* rsr.ddr */ + case 128: + return 332; /* rsr.ibreaka0 */ + case 129: + return 335; /* rsr.ibreaka1 */ + case 144: + return 320; /* rsr.dbreaka0 */ + case 145: + return 326; /* rsr.dbreaka1 */ + case 160: + return 323; /* rsr.dbreakc0 */ + case 161: + return 329; /* rsr.dbreakc1 */ + case 176: + return 136; /* rsr.176 */ + case 177: + return 141; /* rsr.epc1 */ + case 178: + return 147; /* rsr.epc2 */ + case 179: + return 153; /* rsr.epc3 */ + case 180: + return 159; /* rsr.epc4 */ + case 181: + return 165; /* rsr.epc5 */ + case 182: + return 171; /* rsr.epc6 */ + case 183: + return 177; /* rsr.epc7 */ + case 192: + return 204; /* rsr.depc */ + case 194: + return 183; /* rsr.eps2 */ + case 195: + return 186; /* rsr.eps3 */ + case 196: + return 189; /* rsr.eps4 */ + case 197: + return 192; /* rsr.eps5 */ + case 198: + return 195; /* rsr.eps6 */ + case 199: + return 198; /* rsr.eps7 */ + case 208: + return 137; /* rsr.208 */ + case 209: + return 144; /* rsr.excsave1 */ + case 210: + return 150; /* rsr.excsave2 */ + case 211: + return 156; /* rsr.excsave3 */ + case 212: + return 162; /* rsr.excsave4 */ + case 213: + return 168; /* rsr.excsave5 */ + case 214: + return 174; /* rsr.excsave6 */ + case 215: + return 180; /* rsr.excsave7 */ + case 224: + return 418; /* rsr.cpenable */ + case 226: + return 312; /* rsr.interrupt */ + case 228: + return 315; /* rsr.intenable */ + case 230: + return 138; /* rsr.ps */ + case 231: + return 217; /* rsr.vecbase */ + case 232: + return 207; /* rsr.exccause */ + case 233: + return 341; /* rsr.debugcause */ + case 234: + return 356; /* rsr.ccount */ + case 235: + return 216; /* rsr.prid */ + case 236: + return 344; /* rsr.icount */ + case 237: + return 347; /* rsr.icountlevel */ + case 238: + return 201; /* rsr.excvaddr */ + case 240: + return 359; /* rsr.ccompare0 */ + case 241: + return 362; /* rsr.ccompare1 */ + case 242: + return 365; /* rsr.ccompare2 */ + case 244: + return 210; /* rsr.misc0 */ + case 245: + return 213; /* rsr.misc1 */ + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 128; /* wsr.lbeg */ + case 1: + return 122; /* wsr.lend */ + case 2: + return 125; /* wsr.lcount */ + case 3: + return 131; /* wsr.sar */ + case 5: + return 134; /* wsr.litbase */ + case 12: + return 433; /* wsr.scompare1 */ + case 16: + return 305; /* wsr.acclo */ + case 17: + return 308; /* wsr.acchi */ + case 32: + return 293; /* wsr.m0 */ + case 33: + return 296; /* wsr.m1 */ + case 34: + return 299; /* wsr.m2 */ + case 35: + return 302; /* wsr.m3 */ + case 72: + return 21; /* wsr.windowbase */ + case 73: + return 24; /* wsr.windowstart */ + case 83: + return 393; /* wsr.ptevaddr */ + case 89: + return 355; /* wsr.mmid */ + case 90: + return 397; /* wsr.rasid */ + case 91: + return 400; /* wsr.itlbcfg */ + case 92: + return 403; /* wsr.dtlbcfg */ + case 96: + return 339; /* wsr.ibreakenable */ + case 104: + return 351; /* wsr.ddr */ + case 128: + return 333; /* wsr.ibreaka0 */ + case 129: + return 336; /* wsr.ibreaka1 */ + case 144: + return 321; /* wsr.dbreaka0 */ + case 145: + return 327; /* wsr.dbreaka1 */ + case 160: + return 324; /* wsr.dbreakc0 */ + case 161: + return 330; /* wsr.dbreakc1 */ + case 177: + return 142; /* wsr.epc1 */ + case 178: + return 148; /* wsr.epc2 */ + case 179: + return 154; /* wsr.epc3 */ + case 180: + return 160; /* wsr.epc4 */ + case 181: + return 166; /* wsr.epc5 */ + case 182: + return 172; /* wsr.epc6 */ + case 183: + return 178; /* wsr.epc7 */ + case 192: + return 205; /* wsr.depc */ + case 194: + return 184; /* wsr.eps2 */ + case 195: + return 187; /* wsr.eps3 */ + case 196: + return 190; /* wsr.eps4 */ + case 197: + return 193; /* wsr.eps5 */ + case 198: + return 196; /* wsr.eps6 */ + case 199: + return 199; /* wsr.eps7 */ + case 209: + return 145; /* wsr.excsave1 */ + case 210: + return 151; /* wsr.excsave2 */ + case 211: + return 157; /* wsr.excsave3 */ + case 212: + return 163; /* wsr.excsave4 */ + case 213: + return 169; /* wsr.excsave5 */ + case 214: + return 175; /* wsr.excsave6 */ + case 215: + return 181; /* wsr.excsave7 */ + case 224: + return 419; /* wsr.cpenable */ + case 226: + return 313; /* wsr.intset */ + case 227: + return 314; /* wsr.intclear */ + case 228: + return 316; /* wsr.intenable */ + case 230: + return 139; /* wsr.ps */ + case 231: + return 218; /* wsr.vecbase */ + case 232: + return 208; /* wsr.exccause */ + case 233: + return 342; /* wsr.debugcause */ + case 234: + return 357; /* wsr.ccount */ + case 236: + return 345; /* wsr.icount */ + case 237: + return 348; /* wsr.icountlevel */ + case 238: + return 202; /* wsr.excvaddr */ + case 240: + return 360; /* wsr.ccompare0 */ + case 241: + return 363; /* wsr.ccompare1 */ + case 242: + return 366; /* wsr.ccompare2 */ + case 244: + return 211; /* wsr.misc0 */ + case 245: + return 214; /* wsr.misc1 */ + } + break; + case 2: + return 428; /* sext */ + case 3: + return 421; /* clamps */ + case 4: + return 422; /* min */ + case 5: + return 423; /* max */ + case 6: + return 424; /* minu */ + case 7: + return 425; /* maxu */ + case 8: + return 91; /* moveqz */ + case 9: + return 92; /* movnez */ + case 10: + return 93; /* movltz */ + case 11: + return 94; /* movgez */ + case 14: + switch (Field_st_Slot_inst_get (insn)) + { + case 230: + return 440; /* rur.expstate */ + case 231: + return 37; /* rur.threadptr */ + } + break; + case 15: + switch (Field_sr_Slot_inst_get (insn)) + { + case 230: + return 441; /* wur.expstate */ + case 231: + return 38; /* wur.threadptr */ + } + break; + } + break; + case 4: + case 5: + return 78; /* extui */ + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return 18; /* l32e */ + case 4: + return 19; /* s32e */ + } + break; + } + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 442; /* read_impwire */ + break; + case 1: + if (Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 443; /* setb_expstate */ + if (Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 444; /* clrb_expstate */ + break; + case 2: + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return 445; /* wrmsk_expstate */ + break; + } + break; + case 1: + return 85; /* l32r */ + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 86; /* l8ui */ + case 1: + return 82; /* l16ui */ + case 2: + return 84; /* l32i */ + case 4: + return 101; /* s8i */ + case 5: + return 99; /* s16i */ + case 6: + return 100; /* s32i */ + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 384; /* dpfr */ + case 1: + return 385; /* dpfw */ + case 2: + return 386; /* dpfro */ + case 3: + return 387; /* dpfwo */ + case 4: + return 378; /* dhwb */ + case 5: + return 379; /* dhwbi */ + case 6: + return 382; /* dhi */ + case 7: + return 383; /* dii */ + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return 388; /* dpfl */ + case 2: + return 389; /* dhu */ + case 3: + return 390; /* diu */ + case 4: + return 380; /* diwb */ + case 5: + return 381; /* diwbi */ + } + break; + case 12: + return 368; /* ipf */ + case 13: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return 370; /* ipfl */ + case 2: + return 371; /* ihu */ + case 3: + return 372; /* iiu */ + } + break; + case 14: + return 369; /* ihi */ + case 15: + return 373; /* iii */ + } + break; + case 9: + return 83; /* l16si */ + case 10: + return 90; /* movi */ + case 11: + return 429; /* l32ai */ + case 12: + return 39; /* addi */ + case 13: + return 40; /* addmi */ + case 14: + return 431; /* s32c1i */ + case 15: + return 430; /* s32ri */ + } + break; + case 4: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 281; /* mula.dd.ll.ldinc */ + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 283; /* mula.dd.hl.ldinc */ + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 285; /* mula.dd.lh.ldinc */ + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 287; /* mula.dd.hh.ldinc */ + break; + } + break; + case 1: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 280; /* mula.dd.ll.lddec */ + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 282; /* mula.dd.hl.lddec */ + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 284; /* mula.dd.lh.lddec */ + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 286; /* mula.dd.hh.lddec */ + break; + } + break; + case 2: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 236; /* mul.dd.ll */ + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 237; /* mul.dd.hl */ + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 238; /* mul.dd.lh */ + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 239; /* mul.dd.hh */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 264; /* mula.dd.ll */ + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 265; /* mula.dd.hl */ + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 266; /* mula.dd.lh */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 267; /* mula.dd.hh */ + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 268; /* muls.dd.ll */ + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 269; /* muls.dd.hl */ + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 270; /* muls.dd.lh */ + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 271; /* muls.dd.hh */ + break; + } + break; + case 3: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 228; /* mul.ad.ll */ + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 229; /* mul.ad.hl */ + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 230; /* mul.ad.lh */ + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 231; /* mul.ad.hh */ + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 248; /* mula.ad.ll */ + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 249; /* mula.ad.hl */ + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 250; /* mula.ad.lh */ + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 251; /* mula.ad.hh */ + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 252; /* muls.ad.ll */ + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 253; /* muls.ad.hl */ + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 254; /* muls.ad.lh */ + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return 255; /* muls.ad.hh */ + break; + } + break; + case 4: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return 273; /* mula.da.ll.ldinc */ + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return 275; /* mula.da.hl.ldinc */ + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return 277; /* mula.da.lh.ldinc */ + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return 279; /* mula.da.hh.ldinc */ + break; + } + break; + case 5: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return 272; /* mula.da.ll.lddec */ + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return 274; /* mula.da.hl.lddec */ + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return 276; /* mula.da.lh.lddec */ + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return 278; /* mula.da.hh.lddec */ + break; + } + break; + case 6: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 232; /* mul.da.ll */ + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 233; /* mul.da.hl */ + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 234; /* mul.da.lh */ + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 235; /* mul.da.hh */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 256; /* mula.da.ll */ + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 257; /* mula.da.hl */ + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 258; /* mula.da.lh */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 259; /* mula.da.hh */ + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 260; /* muls.da.ll */ + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 261; /* muls.da.hl */ + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 262; /* muls.da.lh */ + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return 263; /* muls.da.hh */ + break; + } + break; + case 7: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + if (Field_r_Slot_inst_get (insn) == 0) + return 224; /* umul.aa.ll */ + break; + case 1: + if (Field_r_Slot_inst_get (insn) == 0) + return 225; /* umul.aa.hl */ + break; + case 2: + if (Field_r_Slot_inst_get (insn) == 0) + return 226; /* umul.aa.lh */ + break; + case 3: + if (Field_r_Slot_inst_get (insn) == 0) + return 227; /* umul.aa.hh */ + break; + case 4: + if (Field_r_Slot_inst_get (insn) == 0) + return 220; /* mul.aa.ll */ + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0) + return 221; /* mul.aa.hl */ + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0) + return 222; /* mul.aa.lh */ + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0) + return 223; /* mul.aa.hh */ + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0) + return 240; /* mula.aa.ll */ + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0) + return 241; /* mula.aa.hl */ + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0) + return 242; /* mula.aa.lh */ + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0) + return 243; /* mula.aa.hh */ + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0) + return 244; /* muls.aa.ll */ + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0) + return 245; /* muls.aa.hl */ + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0) + return 246; /* muls.aa.lh */ + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0) + return 247; /* muls.aa.hh */ + break; + } + break; + case 8: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return 289; /* ldinc */ + break; + case 9: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return 288; /* lddec */ + break; + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 76; /* call0 */ + case 1: + return 7; /* call4 */ + case 2: + return 6; /* call8 */ + case 3: + return 5; /* call12 */ + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 80; /* j */ + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 72; /* beqz */ + case 1: + return 73; /* bnez */ + case 2: + return 75; /* bltz */ + case 3: + return 74; /* bgez */ + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 52; /* beqi */ + case 1: + return 53; /* bnei */ + case 2: + return 55; /* blti */ + case 3: + return 54; /* bgei */ + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 11; /* entry */ + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return 87; /* loop */ + case 9: + return 88; /* loopnez */ + case 10: + return 89; /* loopgtz */ + } + break; + case 2: + return 59; /* bltui */ + case 3: + return 58; /* bgeui */ + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 67; /* bnone */ + case 1: + return 60; /* beq */ + case 2: + return 63; /* blt */ + case 3: + return 65; /* bltu */ + case 4: + return 68; /* ball */ + case 5: + return 70; /* bbc */ + case 6: + case 7: + return 56; /* bbci */ + case 8: + return 66; /* bany */ + case 9: + return 61; /* bne */ + case 10: + return 62; /* bge */ + case 11: + return 64; /* bgeu */ + case 12: + return 69; /* bnall */ + case 13: + return 71; /* bbs */ + case 14: + case 15: + return 57; /* bbsi */ + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return 33; /* movi.n */ + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return 28; /* beqz.n */ + case 1: + return 29; /* bnez.n */ + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return 32; /* mov.n */ + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return 35; /* ret.n */ + case 1: + return 15; /* retw.n */ + case 2: + return 319; /* break.n */ + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 34; /* nop.n */ + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return 31; /* l32i.n */ + case 9: + return 36; /* s32i.n */ + case 10: + return 26; /* add.n */ + case 11: + return 27; /* addi.n */ + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = insn[0] & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 56 /* num_fields */, + 93, operands, + 320, iclasses, + 446, opcodes, 0, + 2, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-dc232b/xtensa-modules.inc.c b/target/xtensa/core-dc232b/xtensa-modules.inc.c deleted file mode 100644 index 164df3b1a4..0000000000 --- a/target/xtensa/core-dc232b/xtensa-modules.inc.c +++ /dev/null @@ -1,14078 +0,0 @@ -/* Xtensa configuration-specific ISA information. - Copyright 2003, 2004, 2005 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#include "qemu/osdep.h" -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "PTEVADDR", 83, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "176", 176, 0 }, - { "208", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "LITBASE", 5, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "THREADPTR", 231, 1 }, - { "EXPSTATE", 230, 1 } -}; - -#define NUM_SYSREGS 70 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 231 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 15, 0 }, - { "EPS3", 15, 0 }, - { "EPS4", 15, 0 }, - { "EPS5", 15, 0 }, - { "EPS6", 15, 0 }, - { "EPS7", 15, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "LITBADDR", 20, 0 }, - { "LITBEN", 1, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 }, - { "CPENABLE", 8, 0 }, - { "SCOMPARE1", 32, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } -}; - -#define NUM_STATES 73 - -/* Macros for xtensa_state numbers (for use in iclasses because the - state numbers are not available when the iclass table is generated). */ - -#define STATE_LCOUNT 0 -#define STATE_PC 1 -#define STATE_ICOUNT 2 -#define STATE_DDR 3 -#define STATE_INTERRUPT 4 -#define STATE_CCOUNT 5 -#define STATE_XTSYNC 6 -#define STATE_VECBASE 7 -#define STATE_EPC1 8 -#define STATE_EPC2 9 -#define STATE_EPC3 10 -#define STATE_EPC4 11 -#define STATE_EPC5 12 -#define STATE_EPC6 13 -#define STATE_EPC7 14 -#define STATE_EXCSAVE1 15 -#define STATE_EXCSAVE2 16 -#define STATE_EXCSAVE3 17 -#define STATE_EXCSAVE4 18 -#define STATE_EXCSAVE5 19 -#define STATE_EXCSAVE6 20 -#define STATE_EXCSAVE7 21 -#define STATE_EPS2 22 -#define STATE_EPS3 23 -#define STATE_EPS4 24 -#define STATE_EPS5 25 -#define STATE_EPS6 26 -#define STATE_EPS7 27 -#define STATE_EXCCAUSE 28 -#define STATE_PSINTLEVEL 29 -#define STATE_PSUM 30 -#define STATE_PSWOE 31 -#define STATE_PSRING 32 -#define STATE_PSEXCM 33 -#define STATE_DEPC 34 -#define STATE_EXCVADDR 35 -#define STATE_WindowBase 36 -#define STATE_WindowStart 37 -#define STATE_PSCALLINC 38 -#define STATE_PSOWB 39 -#define STATE_LBEG 40 -#define STATE_LEND 41 -#define STATE_SAR 42 -#define STATE_THREADPTR 43 -#define STATE_LITBADDR 44 -#define STATE_LITBEN 45 -#define STATE_MISC0 46 -#define STATE_MISC1 47 -#define STATE_ACC 48 -#define STATE_InOCDMode 49 -#define STATE_INTENABLE 50 -#define STATE_DBREAKA0 51 -#define STATE_DBREAKC0 52 -#define STATE_DBREAKA1 53 -#define STATE_DBREAKC1 54 -#define STATE_IBREAKA0 55 -#define STATE_IBREAKA1 56 -#define STATE_IBREAKENABLE 57 -#define STATE_ICOUNTLEVEL 58 -#define STATE_DEBUGCAUSE 59 -#define STATE_DBNUM 60 -#define STATE_CCOMPARE0 61 -#define STATE_CCOMPARE1 62 -#define STATE_CCOMPARE2 63 -#define STATE_ASID3 64 -#define STATE_ASID2 65 -#define STATE_ASID1 66 -#define STATE_INSTPGSZID4 67 -#define STATE_DATAPGSZID4 68 -#define STATE_PTBASE 69 -#define STATE_CPENABLE 70 -#define STATE_SCOMPARE1 71 -#define STATE_EXPSTATE 72 - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - -}; - - -/* Register files. */ - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", 0, 32, 32 }, - { "MR", "m", 1, 32, 4 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "IMPWIRE", 32, 0, 0, 'i' } -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0, soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0, imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} - -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0, uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} - -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0, mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} - -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0, simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} - -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_arr_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_art_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar0_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar4_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar8_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar12_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_entry_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0, r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} - -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0, immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0, r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} - -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0, lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0, imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} - -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0, simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} - -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0, imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} - -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0, uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0, t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0, ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} - -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0, r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} - -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0, b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0, r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} - -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0, b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} - -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} - -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0, op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} - -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0, uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} - -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} - -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0, simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} - -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0, simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0, imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0, simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0, sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0, msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0, op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0, op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0, imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0, label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0, imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} - -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0, ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0, imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} - -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0, label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} - -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0, soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0, imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} - -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0, uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mx_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_my_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -Operand_my_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mw_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr0_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr1_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr2_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr3_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0, t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} - -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0, immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0, s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} - -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0, imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} - -static int -Operand_tp7_decode (uint32 *valp) -{ - unsigned tp7_0, t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; - return 0; -} - -static int -Operand_tp7_encode (uint32 *valp) -{ - unsigned t_0, tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_0, xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; - return 0; -} - -static int -Operand_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_imm_0, xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_0, xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; - return 0; -} - -static int -Operand_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_imm_0, xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", 3, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", 26, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", 14, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", 0, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", 48, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", 49, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", 50, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", 51, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", 14, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", 14, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", 34, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", 33, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", 0, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", 14, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", 14, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", 4, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", 4, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", 4, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", 13, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", 4, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", 4, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", 6, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", 18, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", 13, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", 3, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", 7, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "mx", 43, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_mx_encode, Operand_mx_decode, - 0, 0 }, - { "my", 42, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_my_encode, Operand_my_decode, - 0, 0 }, - { "mw", 41, 1, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mw_encode, Operand_mw_decode, - 0, 0 }, - { "mr0", 52, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr0_encode, Operand_mr0_decode, - 0, 0 }, - { "mr1", 53, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr1_encode, Operand_mr1_decode, - 0, 0 }, - { "mr2", 54, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr2_encode, Operand_mr2_decode, - 0, 0 }, - { "mr3", 55, 1, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr3_encode, Operand_mr3_decode, - 0, 0 }, - { "immt", 0, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", 5, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "tp7", 0, -1, 0, - 0, - Operand_tp7_encode, Operand_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", 44, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", 45, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, - { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, - { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, - { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, - { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, - { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, - { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, - { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, - { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, - { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, - { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 }, - { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 } -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { 11 /* ars_entry */ }, 's' }, - { { 4 /* ars */ }, 'i' }, - { { 1 /* uimm12x8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { 2 /* simm4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 16 /* ai4const */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 15 /* uimm6 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { 4 /* ars */ }, 'o' }, - { { 14 /* simm7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { 3 /* arr */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 23 /* simm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 24 /* simm8x256 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 17 /* b4const */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 47 /* bbi */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 18 /* b4constu */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 30 /* label12 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 62 /* sae */ }, 'i' }, - { { 27 /* op2p1 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { 31 /* soffset */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { 6 /* art */ }, 'o' }, - { { 32 /* uimm16x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 25 /* simm12b */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { 3 /* arr */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { 66 /* sas */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 26 /* msalp32 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 64 /* sargt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 50 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { 6 /* art */ }, 'o' }, - { { 50 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'o' }, - { { STATE_LITBEN }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'm' }, - { { STATE_LITBEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 33 /* mx */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' }, - { { 33 /* mx */ }, 'i' }, - { { 34 /* my */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { 35 /* mw */ }, 'o' }, - { { 4 /* ars */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { 6 /* art */ }, 'o' }, - { { 36 /* mr0 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { 6 /* art */ }, 'i' }, - { { 36 /* mr0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { 6 /* art */ }, 'm' }, - { { 36 /* mr0 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { 6 /* art */ }, 'o' }, - { { 37 /* mr1 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { 6 /* art */ }, 'i' }, - { { 37 /* mr1 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { 6 /* art */ }, 'm' }, - { { 37 /* mr1 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { 6 /* art */ }, 'o' }, - { { 38 /* mr2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { 6 /* art */ }, 'i' }, - { { 38 /* mr2 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { 6 /* art */ }, 'm' }, - { { 38 /* mr2 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { 6 /* art */ }, 'o' }, - { { 39 /* mr3 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { 6 /* art */ }, 'i' }, - { { 39 /* mr3 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { 6 /* art */ }, 'm' }, - { { 39 /* mr3 */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { 50 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { 50 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { 41 /* imms */ }, 'i' }, - { { 40 /* immt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { 41 /* imms */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { 41 /* imms */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 42 /* tp7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 42 /* tp7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { 6 /* art */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { 3 /* arr */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - 0 /* IMPWIRE */ -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { 91 /* bitindex */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { 91 /* bitindex */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_176_args, - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_208_args, - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_mul16_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_expstate_args, - 2, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 2, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135300; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35300; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615300; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35a00; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135a00; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615a00; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35b00; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135b00; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615b00; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35c00; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135c00; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615c00; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f000; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501000; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x509000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { - Opcode_rsr_176_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { - Opcode_rsr_208_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 -}; - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", 0 /* xt_iclass_excw */, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", 1 /* xt_iclass_rfe */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", 2 /* xt_iclass_rfde */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", 3 /* xt_iclass_syscall */, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "simcall", 4 /* xt_iclass_simcall */, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "call12", 5 /* xt_iclass_call12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", 6 /* xt_iclass_call8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", 7 /* xt_iclass_call4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", 8 /* xt_iclass_callx12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", 9 /* xt_iclass_callx8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", 10 /* xt_iclass_callx4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", 11 /* xt_iclass_entry */, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", 12 /* xt_iclass_movsp */, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", 13 /* xt_iclass_rotw */, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", 16 /* xt_iclass_l32e */, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", 17 /* xt_iclass_s32e */, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", 24 /* xt_iclass_add.n */, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", 25 /* xt_iclass_addi.n */, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", 27 /* xt_iclass_ill.n */, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", 28 /* xt_iclass_loadi4 */, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", 29 /* xt_iclass_mov.n */, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", 30 /* xt_iclass_movi.n */, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", 31 /* xt_iclass_nopn */, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", 32 /* xt_iclass_retn */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", 33 /* xt_iclass_storei4 */, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", 34 /* rur_threadptr */, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", 35 /* wur_threadptr */, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", 36 /* xt_iclass_addi */, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", 37 /* xt_iclass_addmi */, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", 38 /* xt_iclass_addsub */, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", 38 /* xt_iclass_addsub */, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", 38 /* xt_iclass_addsub */, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", 38 /* xt_iclass_addsub */, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", 39 /* xt_iclass_bit */, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", 39 /* xt_iclass_bit */, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", 39 /* xt_iclass_bit */, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", 40 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", 41 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", 41 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", 42 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", 42 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", 43 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", 44 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", 45 /* xt_iclass_call0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", 46 /* xt_iclass_callx0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", 47 /* xt_iclass_exti */, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", 48 /* xt_iclass_ill */, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", 49 /* xt_iclass_jump */, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", 50 /* xt_iclass_jumpx */, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", 51 /* xt_iclass_l16ui */, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", 52 /* xt_iclass_l16si */, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", 53 /* xt_iclass_l32i */, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", 54 /* xt_iclass_l32r */, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", 55 /* xt_iclass_l8i */, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", 56 /* xt_iclass_loop */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", 57 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", 57 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", 58 /* xt_iclass_movi */, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", 59 /* xt_iclass_movz */, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", 59 /* xt_iclass_movz */, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", 59 /* xt_iclass_movz */, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", 59 /* xt_iclass_movz */, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", 60 /* xt_iclass_neg */, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", 60 /* xt_iclass_neg */, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", 61 /* xt_iclass_nop */, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", 62 /* xt_iclass_return */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "s16i", 63 /* xt_iclass_s16i */, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", 64 /* xt_iclass_s32i */, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", 65 /* xt_iclass_s8i */, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", 66 /* xt_iclass_sar */, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", 66 /* xt_iclass_sar */, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", 66 /* xt_iclass_sar */, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", 66 /* xt_iclass_sar */, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", 67 /* xt_iclass_sari */, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", 68 /* xt_iclass_shifts */, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", 69 /* xt_iclass_shiftst */, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", 70 /* xt_iclass_shiftt */, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", 70 /* xt_iclass_shiftt */, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", 71 /* xt_iclass_slli */, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", 72 /* xt_iclass_srai */, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", 73 /* xt_iclass_srli */, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", 74 /* xt_iclass_memw */, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", 75 /* xt_iclass_extw */, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", 76 /* xt_iclass_isync */, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", 77 /* xt_iclass_sync */, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", 77 /* xt_iclass_sync */, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", 77 /* xt_iclass_sync */, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", 78 /* xt_iclass_rsil */, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", 79 /* xt_iclass_rsr.lend */, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", 80 /* xt_iclass_wsr.lend */, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", 81 /* xt_iclass_xsr.lend */, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", 88 /* xt_iclass_rsr.sar */, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", 89 /* xt_iclass_wsr.sar */, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", 90 /* xt_iclass_xsr.sar */, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.176", 94 /* xt_iclass_rsr.176 */, - 0, - Opcode_rsr_176_encode_fns, 0, 0 }, - { "rsr.208", 95 /* xt_iclass_rsr.208 */, - 0, - Opcode_rsr_208_encode_fns, 0, 0 }, - { "rsr.ps", 96 /* xt_iclass_rsr.ps */, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", 97 /* xt_iclass_wsr.ps */, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", 98 /* xt_iclass_xsr.ps */, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", 162 /* xt_iclass_rsr.depc */, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", 163 /* xt_iclass_wsr.depc */, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", 164 /* xt_iclass_xsr.depc */, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", 174 /* xt_iclass_rsr.prid */, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", 180 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", 180 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", 180 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", 180 /* xt_iclass_mac16_da */, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", 184 /* xt_iclass_mac16a_da */, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", 188 /* xt_iclass_mac16_l */, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", 188 /* xt_iclass_mac16_l */, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "mul16u", 189 /* xt_iclass_mul16 */, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", 189 /* xt_iclass_mul16 */, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "rsr.m0", 190 /* xt_iclass_rsr.m0 */, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", 191 /* xt_iclass_wsr.m0 */, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", 192 /* xt_iclass_xsr.m0 */, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", 193 /* xt_iclass_rsr.m1 */, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", 194 /* xt_iclass_wsr.m1 */, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", 195 /* xt_iclass_xsr.m1 */, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", 196 /* xt_iclass_rsr.m2 */, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", 197 /* xt_iclass_wsr.m2 */, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", 198 /* xt_iclass_xsr.m2 */, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", 199 /* xt_iclass_rsr.m3 */, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", 200 /* xt_iclass_wsr.m3 */, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", 201 /* xt_iclass_xsr.m3 */, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", 208 /* xt_iclass_rfi */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", 209 /* xt_iclass_wait */, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", 211 /* xt_iclass_wsr.intset */, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", 216 /* xt_iclass_break */, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", 217 /* xt_iclass_break.n */, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", 242 /* xt_iclass_rsr.icount */, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", 243 /* xt_iclass_wsr.icount */, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", 244 /* xt_iclass_xsr.icount */, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", 251 /* xt_iclass_rfdo */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", 252 /* xt_iclass_rfdd */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", 266 /* xt_iclass_icache */, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", 266 /* xt_iclass_icache */, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", 267 /* xt_iclass_icache_lock */, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", 267 /* xt_iclass_icache_lock */, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", 267 /* xt_iclass_icache_lock */, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", 268 /* xt_iclass_icache_inv */, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", 269 /* xt_iclass_licx */, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", 269 /* xt_iclass_licx */, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", 270 /* xt_iclass_sicx */, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", 270 /* xt_iclass_sicx */, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", 271 /* xt_iclass_dcache */, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", 271 /* xt_iclass_dcache */, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", 272 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", 272 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", 273 /* xt_iclass_dcache_inv */, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", 273 /* xt_iclass_dcache_inv */, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", 274 /* xt_iclass_dpf */, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", 274 /* xt_iclass_dpf */, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", 274 /* xt_iclass_dpf */, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", 274 /* xt_iclass_dpf */, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", 275 /* xt_iclass_dcache_lock */, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", 275 /* xt_iclass_dcache_lock */, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", 275 /* xt_iclass_dcache_lock */, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", 276 /* xt_iclass_sdct */, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", 277 /* xt_iclass_ldct */, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", 290 /* xt_iclass_idtlb */, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", 291 /* xt_iclass_rdtlb */, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", 291 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", 291 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", 292 /* xt_iclass_wdtlb */, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", 293 /* xt_iclass_iitlb */, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", 294 /* xt_iclass_ritlb */, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", 294 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", 294 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", 295 /* xt_iclass_witlb */, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", 296 /* xt_iclass_ldpte */, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", 297 /* xt_iclass_hwwitlba */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", 302 /* xt_iclass_clamp */, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", 303 /* xt_iclass_minmax */, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", 303 /* xt_iclass_minmax */, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", 303 /* xt_iclass_minmax */, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", 303 /* xt_iclass_minmax */, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", 304 /* xt_iclass_nsa */, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", 304 /* xt_iclass_nsa */, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", 305 /* xt_iclass_sx */, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", 306 /* xt_iclass_l32ai */, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", 307 /* xt_iclass_s32ri */, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", 308 /* xt_iclass_s32c1i */, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "quou", 312 /* xt_iclass_div */, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", 312 /* xt_iclass_div */, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", 312 /* xt_iclass_div */, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", 312 /* xt_iclass_div */, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "mull", 313 /* xt_mul32 */, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "rur.expstate", 314 /* rur_expstate */, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", 315 /* wur_expstate */, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", 316 /* iclass_READ_IMPWIRE */, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return 79; /* ill */ - break; - case 2: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 98; /* ret */ - case 1: - return 14; /* retw */ - case 2: - return 81; /* jx */ - } - break; - case 3: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 77; /* callx0 */ - case 1: - return 10; /* callx4 */ - case 2: - return 9; /* callx8 */ - case 3: - return 8; /* callx12 */ - } - break; - } - break; - case 1: - return 12; /* movsp */ - case 2: - if (Field_s_Slot_inst_get (insn) == 0) - { - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 116; /* isync */ - case 1: - return 117; /* rsync */ - case 2: - return 118; /* esync */ - case 3: - return 119; /* dsync */ - case 8: - return 0; /* excw */ - case 12: - return 114; /* memw */ - case 13: - return 115; /* extw */ - case 15: - return 97; /* nop */ - } - } - break; - case 3: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 1; /* rfe */ - case 2: - return 2; /* rfde */ - case 4: - return 16; /* rfwo */ - case 5: - return 17; /* rfwu */ - } - break; - case 1: - return 310; /* rfi */ - } - break; - case 4: - return 318; /* break */ - case 5: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 3; /* syscall */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 4; /* simcall */ - break; - } - break; - case 6: - return 120; /* rsil */ - case 7: - if (Field_t_Slot_inst_get (insn) == 0) - return 311; /* waiti */ - break; - } - break; - case 1: - return 49; /* and */ - case 2: - return 50; /* or */ - case 3: - return 51; /* xor */ - case 4: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 102; /* ssr */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 103; /* ssl */ - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 0) - return 104; /* ssa8l */ - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 0) - return 105; /* ssa8b */ - break; - case 4: - if (Field_thi3_Slot_inst_get (insn) == 0) - return 106; /* ssai */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0) - return 13; /* rotw */ - break; - case 14: - return 426; /* nsa */ - case 15: - return 427; /* nsau */ - } - break; - case 5: - switch (Field_r_Slot_inst_get (insn)) - { - case 1: - return 416; /* hwwitlba */ - case 3: - return 412; /* ritlb0 */ - case 4: - if (Field_t_Slot_inst_get (insn) == 0) - return 410; /* iitlb */ - break; - case 5: - return 411; /* pitlb */ - case 6: - return 414; /* witlb */ - case 7: - return 413; /* ritlb1 */ - case 9: - return 417; /* hwwdtlba */ - case 11: - return 407; /* rdtlb0 */ - case 12: - if (Field_t_Slot_inst_get (insn) == 0) - return 405; /* idtlb */ - break; - case 13: - return 406; /* pdtlb */ - case 14: - return 409; /* wdtlb */ - case 15: - return 408; /* rdtlb1 */ - } - break; - case 6: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 95; /* neg */ - case 1: - return 96; /* abs */ - } - break; - case 8: - return 41; /* add */ - case 9: - return 43; /* addx2 */ - case 10: - return 44; /* addx4 */ - case 11: - return 45; /* addx8 */ - case 12: - return 42; /* sub */ - case 13: - return 46; /* subx2 */ - case 14: - return 47; /* subx4 */ - case 15: - return 48; /* subx8 */ - } - break; - case 1: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - case 1: - return 111; /* slli */ - case 2: - case 3: - return 112; /* srai */ - case 4: - return 113; /* srli */ - case 6: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 129; /* xsr.lbeg */ - case 1: - return 123; /* xsr.lend */ - case 2: - return 126; /* xsr.lcount */ - case 3: - return 132; /* xsr.sar */ - case 5: - return 135; /* xsr.litbase */ - case 12: - return 434; /* xsr.scompare1 */ - case 16: - return 306; /* xsr.acclo */ - case 17: - return 309; /* xsr.acchi */ - case 32: - return 294; /* xsr.m0 */ - case 33: - return 297; /* xsr.m1 */ - case 34: - return 300; /* xsr.m2 */ - case 35: - return 303; /* xsr.m3 */ - case 72: - return 22; /* xsr.windowbase */ - case 73: - return 25; /* xsr.windowstart */ - case 83: - return 395; /* xsr.ptevaddr */ - case 90: - return 398; /* xsr.rasid */ - case 91: - return 401; /* xsr.itlbcfg */ - case 92: - return 404; /* xsr.dtlbcfg */ - case 96: - return 340; /* xsr.ibreakenable */ - case 104: - return 352; /* xsr.ddr */ - case 128: - return 334; /* xsr.ibreaka0 */ - case 129: - return 337; /* xsr.ibreaka1 */ - case 144: - return 322; /* xsr.dbreaka0 */ - case 145: - return 328; /* xsr.dbreaka1 */ - case 160: - return 325; /* xsr.dbreakc0 */ - case 161: - return 331; /* xsr.dbreakc1 */ - case 177: - return 143; /* xsr.epc1 */ - case 178: - return 149; /* xsr.epc2 */ - case 179: - return 155; /* xsr.epc3 */ - case 180: - return 161; /* xsr.epc4 */ - case 181: - return 167; /* xsr.epc5 */ - case 182: - return 173; /* xsr.epc6 */ - case 183: - return 179; /* xsr.epc7 */ - case 192: - return 206; /* xsr.depc */ - case 194: - return 185; /* xsr.eps2 */ - case 195: - return 188; /* xsr.eps3 */ - case 196: - return 191; /* xsr.eps4 */ - case 197: - return 194; /* xsr.eps5 */ - case 198: - return 197; /* xsr.eps6 */ - case 199: - return 200; /* xsr.eps7 */ - case 209: - return 146; /* xsr.excsave1 */ - case 210: - return 152; /* xsr.excsave2 */ - case 211: - return 158; /* xsr.excsave3 */ - case 212: - return 164; /* xsr.excsave4 */ - case 213: - return 170; /* xsr.excsave5 */ - case 214: - return 176; /* xsr.excsave6 */ - case 215: - return 182; /* xsr.excsave7 */ - case 224: - return 420; /* xsr.cpenable */ - case 228: - return 317; /* xsr.intenable */ - case 230: - return 140; /* xsr.ps */ - case 231: - return 219; /* xsr.vecbase */ - case 232: - return 209; /* xsr.exccause */ - case 233: - return 343; /* xsr.debugcause */ - case 234: - return 358; /* xsr.ccount */ - case 236: - return 346; /* xsr.icount */ - case 237: - return 349; /* xsr.icountlevel */ - case 238: - return 203; /* xsr.excvaddr */ - case 240: - return 361; /* xsr.ccompare0 */ - case 241: - return 364; /* xsr.ccompare1 */ - case 242: - return 367; /* xsr.ccompare2 */ - case 244: - return 212; /* xsr.misc0 */ - case 245: - return 215; /* xsr.misc1 */ - } - break; - case 8: - return 108; /* src */ - case 9: - if (Field_s_Slot_inst_get (insn) == 0) - return 109; /* srl */ - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0) - return 107; /* sll */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0) - return 110; /* sra */ - break; - case 12: - return 290; /* mul16u */ - case 13: - return 291; /* mul16s */ - case 15: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 374; /* lict */ - case 1: - return 376; /* sict */ - case 2: - return 375; /* licw */ - case 3: - return 377; /* sicw */ - case 8: - return 392; /* ldct */ - case 9: - return 391; /* sdct */ - case 14: - if (Field_t_Slot_inst_get (insn) == 0) - return 353; /* rfdo */ - if (Field_t_Slot_inst_get (insn) == 1) - return 354; /* rfdd */ - break; - case 15: - return 415; /* ldpte */ - } - break; - } - break; - case 2: - switch (Field_op2_Slot_inst_get (insn)) - { - case 8: - return 439; /* mull */ - case 12: - return 435; /* quou */ - case 13: - return 436; /* quos */ - case 14: - return 437; /* remu */ - case 15: - return 438; /* rems */ - } - break; - case 3: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 127; /* rsr.lbeg */ - case 1: - return 121; /* rsr.lend */ - case 2: - return 124; /* rsr.lcount */ - case 3: - return 130; /* rsr.sar */ - case 5: - return 133; /* rsr.litbase */ - case 12: - return 432; /* rsr.scompare1 */ - case 16: - return 304; /* rsr.acclo */ - case 17: - return 307; /* rsr.acchi */ - case 32: - return 292; /* rsr.m0 */ - case 33: - return 295; /* rsr.m1 */ - case 34: - return 298; /* rsr.m2 */ - case 35: - return 301; /* rsr.m3 */ - case 72: - return 20; /* rsr.windowbase */ - case 73: - return 23; /* rsr.windowstart */ - case 83: - return 394; /* rsr.ptevaddr */ - case 90: - return 396; /* rsr.rasid */ - case 91: - return 399; /* rsr.itlbcfg */ - case 92: - return 402; /* rsr.dtlbcfg */ - case 96: - return 338; /* rsr.ibreakenable */ - case 104: - return 350; /* rsr.ddr */ - case 128: - return 332; /* rsr.ibreaka0 */ - case 129: - return 335; /* rsr.ibreaka1 */ - case 144: - return 320; /* rsr.dbreaka0 */ - case 145: - return 326; /* rsr.dbreaka1 */ - case 160: - return 323; /* rsr.dbreakc0 */ - case 161: - return 329; /* rsr.dbreakc1 */ - case 176: - return 136; /* rsr.176 */ - case 177: - return 141; /* rsr.epc1 */ - case 178: - return 147; /* rsr.epc2 */ - case 179: - return 153; /* rsr.epc3 */ - case 180: - return 159; /* rsr.epc4 */ - case 181: - return 165; /* rsr.epc5 */ - case 182: - return 171; /* rsr.epc6 */ - case 183: - return 177; /* rsr.epc7 */ - case 192: - return 204; /* rsr.depc */ - case 194: - return 183; /* rsr.eps2 */ - case 195: - return 186; /* rsr.eps3 */ - case 196: - return 189; /* rsr.eps4 */ - case 197: - return 192; /* rsr.eps5 */ - case 198: - return 195; /* rsr.eps6 */ - case 199: - return 198; /* rsr.eps7 */ - case 208: - return 137; /* rsr.208 */ - case 209: - return 144; /* rsr.excsave1 */ - case 210: - return 150; /* rsr.excsave2 */ - case 211: - return 156; /* rsr.excsave3 */ - case 212: - return 162; /* rsr.excsave4 */ - case 213: - return 168; /* rsr.excsave5 */ - case 214: - return 174; /* rsr.excsave6 */ - case 215: - return 180; /* rsr.excsave7 */ - case 224: - return 418; /* rsr.cpenable */ - case 226: - return 312; /* rsr.interrupt */ - case 228: - return 315; /* rsr.intenable */ - case 230: - return 138; /* rsr.ps */ - case 231: - return 217; /* rsr.vecbase */ - case 232: - return 207; /* rsr.exccause */ - case 233: - return 341; /* rsr.debugcause */ - case 234: - return 356; /* rsr.ccount */ - case 235: - return 216; /* rsr.prid */ - case 236: - return 344; /* rsr.icount */ - case 237: - return 347; /* rsr.icountlevel */ - case 238: - return 201; /* rsr.excvaddr */ - case 240: - return 359; /* rsr.ccompare0 */ - case 241: - return 362; /* rsr.ccompare1 */ - case 242: - return 365; /* rsr.ccompare2 */ - case 244: - return 210; /* rsr.misc0 */ - case 245: - return 213; /* rsr.misc1 */ - } - break; - case 1: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 128; /* wsr.lbeg */ - case 1: - return 122; /* wsr.lend */ - case 2: - return 125; /* wsr.lcount */ - case 3: - return 131; /* wsr.sar */ - case 5: - return 134; /* wsr.litbase */ - case 12: - return 433; /* wsr.scompare1 */ - case 16: - return 305; /* wsr.acclo */ - case 17: - return 308; /* wsr.acchi */ - case 32: - return 293; /* wsr.m0 */ - case 33: - return 296; /* wsr.m1 */ - case 34: - return 299; /* wsr.m2 */ - case 35: - return 302; /* wsr.m3 */ - case 72: - return 21; /* wsr.windowbase */ - case 73: - return 24; /* wsr.windowstart */ - case 83: - return 393; /* wsr.ptevaddr */ - case 89: - return 355; /* wsr.mmid */ - case 90: - return 397; /* wsr.rasid */ - case 91: - return 400; /* wsr.itlbcfg */ - case 92: - return 403; /* wsr.dtlbcfg */ - case 96: - return 339; /* wsr.ibreakenable */ - case 104: - return 351; /* wsr.ddr */ - case 128: - return 333; /* wsr.ibreaka0 */ - case 129: - return 336; /* wsr.ibreaka1 */ - case 144: - return 321; /* wsr.dbreaka0 */ - case 145: - return 327; /* wsr.dbreaka1 */ - case 160: - return 324; /* wsr.dbreakc0 */ - case 161: - return 330; /* wsr.dbreakc1 */ - case 177: - return 142; /* wsr.epc1 */ - case 178: - return 148; /* wsr.epc2 */ - case 179: - return 154; /* wsr.epc3 */ - case 180: - return 160; /* wsr.epc4 */ - case 181: - return 166; /* wsr.epc5 */ - case 182: - return 172; /* wsr.epc6 */ - case 183: - return 178; /* wsr.epc7 */ - case 192: - return 205; /* wsr.depc */ - case 194: - return 184; /* wsr.eps2 */ - case 195: - return 187; /* wsr.eps3 */ - case 196: - return 190; /* wsr.eps4 */ - case 197: - return 193; /* wsr.eps5 */ - case 198: - return 196; /* wsr.eps6 */ - case 199: - return 199; /* wsr.eps7 */ - case 209: - return 145; /* wsr.excsave1 */ - case 210: - return 151; /* wsr.excsave2 */ - case 211: - return 157; /* wsr.excsave3 */ - case 212: - return 163; /* wsr.excsave4 */ - case 213: - return 169; /* wsr.excsave5 */ - case 214: - return 175; /* wsr.excsave6 */ - case 215: - return 181; /* wsr.excsave7 */ - case 224: - return 419; /* wsr.cpenable */ - case 226: - return 313; /* wsr.intset */ - case 227: - return 314; /* wsr.intclear */ - case 228: - return 316; /* wsr.intenable */ - case 230: - return 139; /* wsr.ps */ - case 231: - return 218; /* wsr.vecbase */ - case 232: - return 208; /* wsr.exccause */ - case 233: - return 342; /* wsr.debugcause */ - case 234: - return 357; /* wsr.ccount */ - case 236: - return 345; /* wsr.icount */ - case 237: - return 348; /* wsr.icountlevel */ - case 238: - return 202; /* wsr.excvaddr */ - case 240: - return 360; /* wsr.ccompare0 */ - case 241: - return 363; /* wsr.ccompare1 */ - case 242: - return 366; /* wsr.ccompare2 */ - case 244: - return 211; /* wsr.misc0 */ - case 245: - return 214; /* wsr.misc1 */ - } - break; - case 2: - return 428; /* sext */ - case 3: - return 421; /* clamps */ - case 4: - return 422; /* min */ - case 5: - return 423; /* max */ - case 6: - return 424; /* minu */ - case 7: - return 425; /* maxu */ - case 8: - return 91; /* moveqz */ - case 9: - return 92; /* movnez */ - case 10: - return 93; /* movltz */ - case 11: - return 94; /* movgez */ - case 14: - switch (Field_st_Slot_inst_get (insn)) - { - case 230: - return 440; /* rur.expstate */ - case 231: - return 37; /* rur.threadptr */ - } - break; - case 15: - switch (Field_sr_Slot_inst_get (insn)) - { - case 230: - return 441; /* wur.expstate */ - case 231: - return 38; /* wur.threadptr */ - } - break; - } - break; - case 4: - case 5: - return 78; /* extui */ - case 9: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 18; /* l32e */ - case 4: - return 19; /* s32e */ - } - break; - } - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return 442; /* read_impwire */ - break; - case 1: - if (Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return 443; /* setb_expstate */ - if (Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return 444; /* clrb_expstate */ - break; - case 2: - if (Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return 445; /* wrmsk_expstate */ - break; - } - break; - case 1: - return 85; /* l32r */ - case 2: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 86; /* l8ui */ - case 1: - return 82; /* l16ui */ - case 2: - return 84; /* l32i */ - case 4: - return 101; /* s8i */ - case 5: - return 99; /* s16i */ - case 6: - return 100; /* s32i */ - case 7: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 384; /* dpfr */ - case 1: - return 385; /* dpfw */ - case 2: - return 386; /* dpfro */ - case 3: - return 387; /* dpfwo */ - case 4: - return 378; /* dhwb */ - case 5: - return 379; /* dhwbi */ - case 6: - return 382; /* dhi */ - case 7: - return 383; /* dii */ - case 8: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return 388; /* dpfl */ - case 2: - return 389; /* dhu */ - case 3: - return 390; /* diu */ - case 4: - return 380; /* diwb */ - case 5: - return 381; /* diwbi */ - } - break; - case 12: - return 368; /* ipf */ - case 13: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return 370; /* ipfl */ - case 2: - return 371; /* ihu */ - case 3: - return 372; /* iiu */ - } - break; - case 14: - return 369; /* ihi */ - case 15: - return 373; /* iii */ - } - break; - case 9: - return 83; /* l16si */ - case 10: - return 90; /* movi */ - case 11: - return 429; /* l32ai */ - case 12: - return 39; /* addi */ - case 13: - return 40; /* addmi */ - case 14: - return 431; /* s32c1i */ - case 15: - return 430; /* s32ri */ - } - break; - case 4: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 281; /* mula.dd.ll.ldinc */ - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 283; /* mula.dd.hl.ldinc */ - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 285; /* mula.dd.lh.ldinc */ - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 287; /* mula.dd.hh.ldinc */ - break; - } - break; - case 1: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 280; /* mula.dd.ll.lddec */ - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 282; /* mula.dd.hl.lddec */ - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 284; /* mula.dd.lh.lddec */ - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 286; /* mula.dd.hh.lddec */ - break; - } - break; - case 2: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 236; /* mul.dd.ll */ - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 237; /* mul.dd.hl */ - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 238; /* mul.dd.lh */ - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 239; /* mul.dd.hh */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 264; /* mula.dd.ll */ - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 265; /* mula.dd.hl */ - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 266; /* mula.dd.lh */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 267; /* mula.dd.hh */ - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 268; /* muls.dd.ll */ - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 269; /* muls.dd.hl */ - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 270; /* muls.dd.lh */ - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 271; /* muls.dd.hh */ - break; - } - break; - case 3: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 228; /* mul.ad.ll */ - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 229; /* mul.ad.hl */ - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 230; /* mul.ad.lh */ - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 231; /* mul.ad.hh */ - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 248; /* mula.ad.ll */ - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 249; /* mula.ad.hl */ - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 250; /* mula.ad.lh */ - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 251; /* mula.ad.hh */ - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 252; /* muls.ad.ll */ - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 253; /* muls.ad.hl */ - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 254; /* muls.ad.lh */ - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return 255; /* muls.ad.hh */ - break; - } - break; - case 4: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return 273; /* mula.da.ll.ldinc */ - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return 275; /* mula.da.hl.ldinc */ - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return 277; /* mula.da.lh.ldinc */ - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return 279; /* mula.da.hh.ldinc */ - break; - } - break; - case 5: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return 272; /* mula.da.ll.lddec */ - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return 274; /* mula.da.hl.lddec */ - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return 276; /* mula.da.lh.lddec */ - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return 278; /* mula.da.hh.lddec */ - break; - } - break; - case 6: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 232; /* mul.da.ll */ - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 233; /* mul.da.hl */ - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 234; /* mul.da.lh */ - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 235; /* mul.da.hh */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 256; /* mula.da.ll */ - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 257; /* mula.da.hl */ - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 258; /* mula.da.lh */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 259; /* mula.da.hh */ - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 260; /* muls.da.ll */ - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 261; /* muls.da.hl */ - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 262; /* muls.da.lh */ - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return 263; /* muls.da.hh */ - break; - } - break; - case 7: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - if (Field_r_Slot_inst_get (insn) == 0) - return 224; /* umul.aa.ll */ - break; - case 1: - if (Field_r_Slot_inst_get (insn) == 0) - return 225; /* umul.aa.hl */ - break; - case 2: - if (Field_r_Slot_inst_get (insn) == 0) - return 226; /* umul.aa.lh */ - break; - case 3: - if (Field_r_Slot_inst_get (insn) == 0) - return 227; /* umul.aa.hh */ - break; - case 4: - if (Field_r_Slot_inst_get (insn) == 0) - return 220; /* mul.aa.ll */ - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0) - return 221; /* mul.aa.hl */ - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0) - return 222; /* mul.aa.lh */ - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0) - return 223; /* mul.aa.hh */ - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0) - return 240; /* mula.aa.ll */ - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0) - return 241; /* mula.aa.hl */ - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0) - return 242; /* mula.aa.lh */ - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0) - return 243; /* mula.aa.hh */ - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0) - return 244; /* muls.aa.ll */ - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0) - return 245; /* muls.aa.hl */ - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0) - return 246; /* muls.aa.lh */ - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0) - return 247; /* muls.aa.hh */ - break; - } - break; - case 8: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return 289; /* ldinc */ - break; - case 9: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return 288; /* lddec */ - break; - } - break; - case 5: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 76; /* call0 */ - case 1: - return 7; /* call4 */ - case 2: - return 6; /* call8 */ - case 3: - return 5; /* call12 */ - } - break; - case 6: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 80; /* j */ - case 1: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 72; /* beqz */ - case 1: - return 73; /* bnez */ - case 2: - return 75; /* bltz */ - case 3: - return 74; /* bgez */ - } - break; - case 2: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 52; /* beqi */ - case 1: - return 53; /* bnei */ - case 2: - return 55; /* blti */ - case 3: - return 54; /* bgei */ - } - break; - case 3: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 11; /* entry */ - case 1: - switch (Field_r_Slot_inst_get (insn)) - { - case 8: - return 87; /* loop */ - case 9: - return 88; /* loopnez */ - case 10: - return 89; /* loopgtz */ - } - break; - case 2: - return 59; /* bltui */ - case 3: - return 58; /* bgeui */ - } - break; - } - break; - case 7: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 67; /* bnone */ - case 1: - return 60; /* beq */ - case 2: - return 63; /* blt */ - case 3: - return 65; /* bltu */ - case 4: - return 68; /* ball */ - case 5: - return 70; /* bbc */ - case 6: - case 7: - return 56; /* bbci */ - case 8: - return 66; /* bany */ - case 9: - return 61; /* bne */ - case 10: - return 62; /* bge */ - case 11: - return 64; /* bgeu */ - case 12: - return 69; /* bnall */ - case 13: - return 71; /* bbs */ - case 14: - case 15: - return 57; /* bbsi */ - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16b_get (insn)) - { - case 12: - switch (Field_i_Slot_inst16b_get (insn)) - { - case 0: - return 33; /* movi.n */ - case 1: - switch (Field_z_Slot_inst16b_get (insn)) - { - case 0: - return 28; /* beqz.n */ - case 1: - return 29; /* bnez.n */ - } - break; - } - break; - case 13: - switch (Field_r_Slot_inst16b_get (insn)) - { - case 0: - return 32; /* mov.n */ - case 15: - switch (Field_t_Slot_inst16b_get (insn)) - { - case 0: - return 35; /* ret.n */ - case 1: - return 15; /* retw.n */ - case 2: - return 319; /* break.n */ - case 3: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 34; /* nop.n */ - break; - case 6: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 30; /* ill.n */ - break; - } - break; - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16a_get (insn)) - { - case 8: - return 31; /* l32i.n */ - case 9: - return 36; /* s32i.n */ - case 10: - return 26; /* add.n */ - case 11: - return 27; /* addi.n */ - } - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc) - return 2; /* x16b */ - return -1; -} - -static int length_table[16] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int op0 = insn[0] & 0xf; - return length_table[op0]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 3 /* insn_size */, 0, - 3, formats, format_decoder, length_decoder, - 3, slots, - 56 /* num_fields */, - 93, operands, - 320, iclasses, - 446, opcodes, 0, - 2, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 1, interfaces, 0, - 0, funcUnits, 0 -}; diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c index f8204f7045..595ab9a90f 100644 --- a/target/xtensa/core-dc233c.c +++ b/target/xtensa/core-dc233c.c @@ -34,13 +34,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_dc233c -#include "core-dc233c/xtensa-modules.inc.c" +#include "core-dc233c/xtensa-modules.c.inc" static XtensaConfig dc233c __attribute__((unused)) = { .name = "dc233c", .gdb_regmap = { .reg = { -#include "core-dc233c/gdb-config.inc.c" +#include "core-dc233c/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-dc233c/gdb-config.c.inc b/target/xtensa/core-dc233c/gdb-config.c.inc new file mode 100644 index 0000000000..7e8963227f --- /dev/null +++ b/target/xtensa/core-dc233c/gdb-config.c.inc @@ -0,0 +1,146 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* idx ofs bi sz al targno flags cp typ group name */ +XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0) +XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0) +XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0) +XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0) +XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0) +XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0) +XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0) +XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0) +XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0) +XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0) +XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, 0, 0, 0, 0, 0, 0) +XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, 0, 0, 0, 0, 0, 0) +XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, 0, 0, 0, 0, 0, 0) +XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, 0, 0, 0, 0, 0, 0) +XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, 0, 0, 0, 0, 0, 0) +XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, 0, 0, 0, 0, 0, 0) +XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, 0, 0, 0, 0, 0, 0) +XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, 0, 0, 0, 0, 0, 0) +XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, 0, 0, 0, 0, 0, 0) +XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, 0, 0, 0, 0, 0, 0) +XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, 0, 0, 0, 0, 0, 0) +XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, 0, 0, 0, 0, 0, 0) +XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, 0, 0, 0, 0, 0, 0) +XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, 0, 0, 0, 0, 0, 0) +XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, 0, 0, 0, 0, 0, 0) +XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, 0, 0, 0, 0, 0, 0) +XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, 0, 0, 0, 0, 0, 0) +XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, 0, 0, 0, 0, 0, 0) +XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, 0, 0, 0, 0, 0, 0) +XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, 0, 0, 0, 0, 0, 0) +XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, 0, 0, 0, 0, 0, 0) +XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, 0, 0, 0, 0, 0, 0) +XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, 0, 0, 0, 0, 0, 0) +XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, 0, 0, 0, 0, 0, 0) +XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, 0, 0, 0, 0, 0, 0) +XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, 0, 0, 0, 0, 0, 0) +XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, 0, 0, 0, 0, 0, 0) +XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, 0, 0, 0, 0, 0, 0) +XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, 0, 0, 0, 0, 0, 0) +XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, 0, 0, 0, 0, 0, 0) +XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, 0, 0, 0, 0, 0, 0) +XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, 0, 0, 0, 0, 0, 0) +XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, 0, 0, 0, 0, 0, 0) +XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, 0, 0, 0, 0, 0, 0) +XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, 0, 0, 0, 0, 0, 0) +XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, 0, 0, 0, 0, 0, 0) +XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, 0, 0, 0, 0, 0, 0) +XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, 0, 0, 0, 0, 0, 0) +XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, 0, 0, 0, 0, 0, 0) +XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, 0, 0, 0, 0, 0, 0) +XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, 0, 0, 0, 0, 0, 0) +XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, 0, 0, 0, 0, 0, 0) +XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, 0, 0, 0, 0, 0, 0) +XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, 0, 0, 0, 0, 0, 0) +XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, 0, 0, 0, 0, 0, 0) +XTREG(55, 220, 25, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, 0, 0, 0, 0, 0, 0) +XTREG(56, 224, 25, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, 0, 0, 0, 0, 0, 0) +XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, 0, 0, 0, 0, 0, 0) +XTREG(58, 232, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, 0, 0, 0, 0, 0, 0) +XTREG(59, 236, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, 0, 0, 0, 0, 0, 0) +XTREG(60, 240, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, 0, 0, 0, 0, 0, 0) +XTREG(61, 244, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, 0, 0, 0, 0, 0, 0) +XTREG(62, 248, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, 0, 0, 0, 0, 0, 0) +XTREG(63, 252, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, 0, 0, 0, 0, 0, 0) +XTREG(64, 256, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, 0, 0, 0, 0, 0, 0) +XTREG(65, 260, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, 0, 0, 0, 0, 0, 0) +XTREG(66, 264, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, 0, 0, 0, 0, 0, 0) +XTREG(67, 268, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, 0, 0, 0, 0, 0, 0) +XTREG(68, 272, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, 0, 0, 0, 0, 0, 0) +XTREG(69, 276, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, 0, 0, 0, 0, 0, 0) +XTREG(70, 280, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, 0, 0, 0, 0, 0, 0) +XTREG(71, 284, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, 0, 0, 0, 0, 0, 0) +XTREG(72, 288, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, 0, 0, 0, 0, 0, 0) +XTREG(73, 292, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, 0, 0, 0, 0, 0, 0) +XTREG(74, 296, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, 0, 0, 0, 0, 0, 0) +XTREG(75, 300, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, 0, 0, 0, 0, 0, 0) +XTREG(76, 304, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, 0, 0, 0, 0, 0, 0) +XTREG(77, 308, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, 0, 0, 0, 0, 0, 0) +XTREG(78, 312, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, 0, 0, 0, 0, 0, 0) +XTREG(79, 316, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, 0, 0, 0, 0, 0, 0) +XTREG(80, 320, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, 0, 0, 0, 0, 0, 0) +XTREG(81, 324, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, 0, 0, 0, 0, 0, 0) +XTREG(82, 328, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, 0, 0, 0, 0, 0, 0) +XTREG(83, 332, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, 0, 0, 0, 0, 0, 0) +XTREG(84, 336, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, 0, 0, 0, 0, 0, 0) +XTREG(85, 340, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, 0, 0, 0, 0, 0, 0) +XTREG(86, 344, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, 0, 0, 0, 0, 0, 0) +XTREG(87, 348, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, 0, 0, 0, 0, 0, 0) +XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, 0, 0, 0, 0, 0, 0) +XTREG(89, 356, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, 0, 0, 0, 0, 0, 0) +XTREG(90, 360, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, 0, 0, 0, 0, 0, 0) +XTREG(91, 364, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, 0, 0, 0, 0, 0, 0) +XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0) +XTREG(93, 372, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, 0, 0, 0, 0, 0, 0) +XTREG(94, 376, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, 0, 0, 0, 0, 0, 0) +XTREG(95, 380, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, 0, 0, 0, 0, 0, 0) +XTREG(96, 384, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, 0, 0, 0, 0, 0, 0) +XTREG(97, 388, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, 0, 0, 0, 0, 0, 0) +XTREG(98, 392, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, 0, 0, 0, 0, 0, 0) +XTREG(99, 396, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, 0, 0, 0, 0, 0, 0) +XTREG(100, 400, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, 0, 0, 0, 0, 0, 0) +XTREG(101, 404, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, 0, 0, 0, 0, 0, 0) +XTREG(102, 408, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, 0, 0, 0, 0, 0, 0) +XTREG(103, 412, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, 0, 0, 0, 0, 0, 0) +XTREG(104, 416, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, 0, 0, 0, 0, 0, 0) +XTREG(105, 420, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, 0, 0, 0, 0, 0, 0) +XTREG(106, 424, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, 0, 0, 0, 0, 0, 0) +XTREG(107, 428, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, 0, 0, 0, 0, 0, 0) +XTREG(108, 432, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, 0, 0, 0, 0, 0, 0) +XTREG(109, 436, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, 0, 0, 0, 0, 0, 0) +XTREG(110, 440, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, 0, 0, 0, 0, 0, 0) +XTREG(111, 444, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, 0, 0, 0, 0, 0, 0) +XTREG(112, 448, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, 0, 0, 0, 0, 0, 0) +XTREG(113, 452, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, 0, 0, 0, 0, 0, 0) +XTREG(114, 456, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, 0, 0, 0, 0, 0, 0) +XTREG(115, 460, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, 0, 0, 0, 0, 0, 0) +XTREG(116, 464, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, 0, 0, 0, 0, 0, 0) +XTREG(117, 468, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, 0, 0, 0, 0, 0, 0) +XTREG(118, 472, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, 0, 0, 0, 0, 0, 0) +XTREG(119, 476, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, 0, 0, 0, 0, 0, 0) +XTREG(120, 480, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, 0, 0, 0, 0, 0, 0) +XTREG_END diff --git a/target/xtensa/core-dc233c/gdb-config.inc.c b/target/xtensa/core-dc233c/gdb-config.inc.c deleted file mode 100644 index 7e8963227f..0000000000 --- a/target/xtensa/core-dc233c/gdb-config.inc.c +++ /dev/null @@ -1,146 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -/* idx ofs bi sz al targno flags cp typ group name */ -XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0) -XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0) -XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0) -XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0) -XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0) -XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0) -XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0) -XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0) -XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0) -XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0) -XTREG(10, 40, 32, 4, 4, 0x0109, 0x0006, -2, 1, 0x0002, ar9, 0, 0, 0, 0, 0, 0) -XTREG(11, 44, 32, 4, 4, 0x010a, 0x0006, -2, 1, 0x0002, ar10, 0, 0, 0, 0, 0, 0) -XTREG(12, 48, 32, 4, 4, 0x010b, 0x0006, -2, 1, 0x0002, ar11, 0, 0, 0, 0, 0, 0) -XTREG(13, 52, 32, 4, 4, 0x010c, 0x0006, -2, 1, 0x0002, ar12, 0, 0, 0, 0, 0, 0) -XTREG(14, 56, 32, 4, 4, 0x010d, 0x0006, -2, 1, 0x0002, ar13, 0, 0, 0, 0, 0, 0) -XTREG(15, 60, 32, 4, 4, 0x010e, 0x0006, -2, 1, 0x0002, ar14, 0, 0, 0, 0, 0, 0) -XTREG(16, 64, 32, 4, 4, 0x010f, 0x0006, -2, 1, 0x0002, ar15, 0, 0, 0, 0, 0, 0) -XTREG(17, 68, 32, 4, 4, 0x0110, 0x0006, -2, 1, 0x0002, ar16, 0, 0, 0, 0, 0, 0) -XTREG(18, 72, 32, 4, 4, 0x0111, 0x0006, -2, 1, 0x0002, ar17, 0, 0, 0, 0, 0, 0) -XTREG(19, 76, 32, 4, 4, 0x0112, 0x0006, -2, 1, 0x0002, ar18, 0, 0, 0, 0, 0, 0) -XTREG(20, 80, 32, 4, 4, 0x0113, 0x0006, -2, 1, 0x0002, ar19, 0, 0, 0, 0, 0, 0) -XTREG(21, 84, 32, 4, 4, 0x0114, 0x0006, -2, 1, 0x0002, ar20, 0, 0, 0, 0, 0, 0) -XTREG(22, 88, 32, 4, 4, 0x0115, 0x0006, -2, 1, 0x0002, ar21, 0, 0, 0, 0, 0, 0) -XTREG(23, 92, 32, 4, 4, 0x0116, 0x0006, -2, 1, 0x0002, ar22, 0, 0, 0, 0, 0, 0) -XTREG(24, 96, 32, 4, 4, 0x0117, 0x0006, -2, 1, 0x0002, ar23, 0, 0, 0, 0, 0, 0) -XTREG(25, 100, 32, 4, 4, 0x0118, 0x0006, -2, 1, 0x0002, ar24, 0, 0, 0, 0, 0, 0) -XTREG(26, 104, 32, 4, 4, 0x0119, 0x0006, -2, 1, 0x0002, ar25, 0, 0, 0, 0, 0, 0) -XTREG(27, 108, 32, 4, 4, 0x011a, 0x0006, -2, 1, 0x0002, ar26, 0, 0, 0, 0, 0, 0) -XTREG(28, 112, 32, 4, 4, 0x011b, 0x0006, -2, 1, 0x0002, ar27, 0, 0, 0, 0, 0, 0) -XTREG(29, 116, 32, 4, 4, 0x011c, 0x0006, -2, 1, 0x0002, ar28, 0, 0, 0, 0, 0, 0) -XTREG(30, 120, 32, 4, 4, 0x011d, 0x0006, -2, 1, 0x0002, ar29, 0, 0, 0, 0, 0, 0) -XTREG(31, 124, 32, 4, 4, 0x011e, 0x0006, -2, 1, 0x0002, ar30, 0, 0, 0, 0, 0, 0) -XTREG(32, 128, 32, 4, 4, 0x011f, 0x0006, -2, 1, 0x0002, ar31, 0, 0, 0, 0, 0, 0) -XTREG(33, 132, 32, 4, 4, 0x0200, 0x0006, -2, 2, 0x1100, lbeg, 0, 0, 0, 0, 0, 0) -XTREG(34, 136, 32, 4, 4, 0x0201, 0x0006, -2, 2, 0x1100, lend, 0, 0, 0, 0, 0, 0) -XTREG(35, 140, 32, 4, 4, 0x0202, 0x0006, -2, 2, 0x1100, lcount, 0, 0, 0, 0, 0, 0) -XTREG(36, 144, 6, 4, 4, 0x0203, 0x0006, -2, 2, 0x1100, sar, 0, 0, 0, 0, 0, 0) -XTREG(37, 148, 32, 4, 4, 0x0205, 0x0006, -2, 2, 0x1100, litbase, 0, 0, 0, 0, 0, 0) -XTREG(38, 152, 3, 4, 4, 0x0248, 0x0006, -2, 2, 0x1002, windowbase, 0, 0, 0, 0, 0, 0) -XTREG(39, 156, 8, 4, 4, 0x0249, 0x0006, -2, 2, 0x1002, windowstart, 0, 0, 0, 0, 0, 0) -XTREG(40, 160, 32, 4, 4, 0x02b0, 0x0002, -2, 2, 0x1000, sr176, 0, 0, 0, 0, 0, 0) -XTREG(41, 164, 32, 4, 4, 0x02d0, 0x0002, -2, 2, 0x1000, sr208, 0, 0, 0, 0, 0, 0) -XTREG(42, 168, 19, 4, 4, 0x02e6, 0x0006, -2, 2, 0x1100, ps, 0, 0, 0, 0, 0, 0) -XTREG(43, 172, 32, 4, 4, 0x03e7, 0x0006, -2, 3, 0x0110, threadptr, 0, 0, 0, 0, 0, 0) -XTREG(44, 176, 32, 4, 4, 0x020c, 0x0006, -1, 2, 0x1100, scompare1, 0, 0, 0, 0, 0, 0) -XTREG(45, 180, 32, 4, 4, 0x0210, 0x0006, -1, 2, 0x1100, acclo, 0, 0, 0, 0, 0, 0) -XTREG(46, 184, 8, 4, 4, 0x0211, 0x0006, -1, 2, 0x1100, acchi, 0, 0, 0, 0, 0, 0) -XTREG(47, 188, 32, 4, 4, 0x0220, 0x0006, -1, 2, 0x1100, m0, 0, 0, 0, 0, 0, 0) -XTREG(48, 192, 32, 4, 4, 0x0221, 0x0006, -1, 2, 0x1100, m1, 0, 0, 0, 0, 0, 0) -XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, 0, 0, 0, 0, 0, 0) -XTREG(50, 200, 32, 4, 4, 0x0223, 0x0006, -1, 2, 0x1100, m3, 0, 0, 0, 0, 0, 0) -XTREG(51, 204, 32, 4, 4, 0x03e6, 0x000e, -1, 3, 0x0110, expstate, 0, 0, 0, 0, 0, 0) -XTREG(52, 208, 32, 4, 4, 0x0253, 0x0007, -2, 2, 0x1000, ptevaddr, 0, 0, 0, 0, 0, 0) -XTREG(53, 212, 32, 4, 4, 0x0259, 0x000d, -2, 2, 0x1000, mmid, 0, 0, 0, 0, 0, 0) -XTREG(54, 216, 32, 4, 4, 0x025a, 0x0007, -2, 2, 0x1000, rasid, 0, 0, 0, 0, 0, 0) -XTREG(55, 220, 25, 4, 4, 0x025b, 0x0007, -2, 2, 0x1000, itlbcfg, 0, 0, 0, 0, 0, 0) -XTREG(56, 224, 25, 4, 4, 0x025c, 0x0007, -2, 2, 0x1000, dtlbcfg, 0, 0, 0, 0, 0, 0) -XTREG(57, 228, 2, 4, 4, 0x0260, 0x0007, -2, 2, 0x1000, ibreakenable, 0, 0, 0, 0, 0, 0) -XTREG(58, 232, 6, 4, 4, 0x0263, 0x0007, -2, 2, 0x1000, atomctl, 0, 0, 0, 0, 0, 0) -XTREG(59, 236, 32, 4, 4, 0x0268, 0x0007, -2, 2, 0x1000, ddr, 0, 0, 0, 0, 0, 0) -XTREG(60, 240, 32, 4, 4, 0x0280, 0x0007, -2, 2, 0x1000, ibreaka0, 0, 0, 0, 0, 0, 0) -XTREG(61, 244, 32, 4, 4, 0x0281, 0x0007, -2, 2, 0x1000, ibreaka1, 0, 0, 0, 0, 0, 0) -XTREG(62, 248, 32, 4, 4, 0x0290, 0x0007, -2, 2, 0x1000, dbreaka0, 0, 0, 0, 0, 0, 0) -XTREG(63, 252, 32, 4, 4, 0x0291, 0x0007, -2, 2, 0x1000, dbreaka1, 0, 0, 0, 0, 0, 0) -XTREG(64, 256, 32, 4, 4, 0x02a0, 0x0007, -2, 2, 0x1000, dbreakc0, 0, 0, 0, 0, 0, 0) -XTREG(65, 260, 32, 4, 4, 0x02a1, 0x0007, -2, 2, 0x1000, dbreakc1, 0, 0, 0, 0, 0, 0) -XTREG(66, 264, 32, 4, 4, 0x02b1, 0x0007, -2, 2, 0x1000, epc1, 0, 0, 0, 0, 0, 0) -XTREG(67, 268, 32, 4, 4, 0x02b2, 0x0007, -2, 2, 0x1000, epc2, 0, 0, 0, 0, 0, 0) -XTREG(68, 272, 32, 4, 4, 0x02b3, 0x0007, -2, 2, 0x1000, epc3, 0, 0, 0, 0, 0, 0) -XTREG(69, 276, 32, 4, 4, 0x02b4, 0x0007, -2, 2, 0x1000, epc4, 0, 0, 0, 0, 0, 0) -XTREG(70, 280, 32, 4, 4, 0x02b5, 0x0007, -2, 2, 0x1000, epc5, 0, 0, 0, 0, 0, 0) -XTREG(71, 284, 32, 4, 4, 0x02b6, 0x0007, -2, 2, 0x1000, epc6, 0, 0, 0, 0, 0, 0) -XTREG(72, 288, 32, 4, 4, 0x02b7, 0x0007, -2, 2, 0x1000, epc7, 0, 0, 0, 0, 0, 0) -XTREG(73, 292, 32, 4, 4, 0x02c0, 0x0007, -2, 2, 0x1000, depc, 0, 0, 0, 0, 0, 0) -XTREG(74, 296, 19, 4, 4, 0x02c2, 0x0007, -2, 2, 0x1000, eps2, 0, 0, 0, 0, 0, 0) -XTREG(75, 300, 19, 4, 4, 0x02c3, 0x0007, -2, 2, 0x1000, eps3, 0, 0, 0, 0, 0, 0) -XTREG(76, 304, 19, 4, 4, 0x02c4, 0x0007, -2, 2, 0x1000, eps4, 0, 0, 0, 0, 0, 0) -XTREG(77, 308, 19, 4, 4, 0x02c5, 0x0007, -2, 2, 0x1000, eps5, 0, 0, 0, 0, 0, 0) -XTREG(78, 312, 19, 4, 4, 0x02c6, 0x0007, -2, 2, 0x1000, eps6, 0, 0, 0, 0, 0, 0) -XTREG(79, 316, 19, 4, 4, 0x02c7, 0x0007, -2, 2, 0x1000, eps7, 0, 0, 0, 0, 0, 0) -XTREG(80, 320, 32, 4, 4, 0x02d1, 0x0007, -2, 2, 0x1000, excsave1, 0, 0, 0, 0, 0, 0) -XTREG(81, 324, 32, 4, 4, 0x02d2, 0x0007, -2, 2, 0x1000, excsave2, 0, 0, 0, 0, 0, 0) -XTREG(82, 328, 32, 4, 4, 0x02d3, 0x0007, -2, 2, 0x1000, excsave3, 0, 0, 0, 0, 0, 0) -XTREG(83, 332, 32, 4, 4, 0x02d4, 0x0007, -2, 2, 0x1000, excsave4, 0, 0, 0, 0, 0, 0) -XTREG(84, 336, 32, 4, 4, 0x02d5, 0x0007, -2, 2, 0x1000, excsave5, 0, 0, 0, 0, 0, 0) -XTREG(85, 340, 32, 4, 4, 0x02d6, 0x0007, -2, 2, 0x1000, excsave6, 0, 0, 0, 0, 0, 0) -XTREG(86, 344, 32, 4, 4, 0x02d7, 0x0007, -2, 2, 0x1000, excsave7, 0, 0, 0, 0, 0, 0) -XTREG(87, 348, 8, 4, 4, 0x02e0, 0x0007, -2, 2, 0x1000, cpenable, 0, 0, 0, 0, 0, 0) -XTREG(88, 352, 22, 4, 4, 0x02e2, 0x000b, -2, 2, 0x1000, interrupt, 0, 0, 0, 0, 0, 0) -XTREG(89, 356, 22, 4, 4, 0x02e2, 0x000d, -2, 2, 0x1000, intset, 0, 0, 0, 0, 0, 0) -XTREG(90, 360, 22, 4, 4, 0x02e3, 0x000d, -2, 2, 0x1000, intclear, 0, 0, 0, 0, 0, 0) -XTREG(91, 364, 22, 4, 4, 0x02e4, 0x0007, -2, 2, 0x1000, intenable, 0, 0, 0, 0, 0, 0) -XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0) -XTREG(93, 372, 6, 4, 4, 0x02e8, 0x0007, -2, 2, 0x1000, exccause, 0, 0, 0, 0, 0, 0) -XTREG(94, 376, 12, 4, 4, 0x02e9, 0x0003, -2, 2, 0x1000, debugcause, 0, 0, 0, 0, 0, 0) -XTREG(95, 380, 32, 4, 4, 0x02ea, 0x000f, -2, 2, 0x1000, ccount, 0, 0, 0, 0, 0, 0) -XTREG(96, 384, 32, 4, 4, 0x02eb, 0x0003, -2, 2, 0x1000, prid, 0, 0, 0, 0, 0, 0) -XTREG(97, 388, 32, 4, 4, 0x02ec, 0x000f, -2, 2, 0x1000, icount, 0, 0, 0, 0, 0, 0) -XTREG(98, 392, 4, 4, 4, 0x02ed, 0x0007, -2, 2, 0x1000, icountlevel, 0, 0, 0, 0, 0, 0) -XTREG(99, 396, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, 0, 0, 0, 0, 0, 0) -XTREG(100, 400, 32, 4, 4, 0x02f0, 0x000f, -2, 2, 0x1000, ccompare0, 0, 0, 0, 0, 0, 0) -XTREG(101, 404, 32, 4, 4, 0x02f1, 0x000f, -2, 2, 0x1000, ccompare1, 0, 0, 0, 0, 0, 0) -XTREG(102, 408, 32, 4, 4, 0x02f2, 0x000f, -2, 2, 0x1000, ccompare2, 0, 0, 0, 0, 0, 0) -XTREG(103, 412, 32, 4, 4, 0x02f4, 0x0007, -2, 2, 0x1000, misc0, 0, 0, 0, 0, 0, 0) -XTREG(104, 416, 32, 4, 4, 0x02f5, 0x0007, -2, 2, 0x1000, misc1, 0, 0, 0, 0, 0, 0) -XTREG(105, 420, 32, 4, 4, 0x0000, 0x0006, -2, 8, 0x0100, a0, 0, 0, 0, 0, 0, 0) -XTREG(106, 424, 32, 4, 4, 0x0001, 0x0006, -2, 8, 0x0100, a1, 0, 0, 0, 0, 0, 0) -XTREG(107, 428, 32, 4, 4, 0x0002, 0x0006, -2, 8, 0x0100, a2, 0, 0, 0, 0, 0, 0) -XTREG(108, 432, 32, 4, 4, 0x0003, 0x0006, -2, 8, 0x0100, a3, 0, 0, 0, 0, 0, 0) -XTREG(109, 436, 32, 4, 4, 0x0004, 0x0006, -2, 8, 0x0100, a4, 0, 0, 0, 0, 0, 0) -XTREG(110, 440, 32, 4, 4, 0x0005, 0x0006, -2, 8, 0x0100, a5, 0, 0, 0, 0, 0, 0) -XTREG(111, 444, 32, 4, 4, 0x0006, 0x0006, -2, 8, 0x0100, a6, 0, 0, 0, 0, 0, 0) -XTREG(112, 448, 32, 4, 4, 0x0007, 0x0006, -2, 8, 0x0100, a7, 0, 0, 0, 0, 0, 0) -XTREG(113, 452, 32, 4, 4, 0x0008, 0x0006, -2, 8, 0x0100, a8, 0, 0, 0, 0, 0, 0) -XTREG(114, 456, 32, 4, 4, 0x0009, 0x0006, -2, 8, 0x0100, a9, 0, 0, 0, 0, 0, 0) -XTREG(115, 460, 32, 4, 4, 0x000a, 0x0006, -2, 8, 0x0100, a10, 0, 0, 0, 0, 0, 0) -XTREG(116, 464, 32, 4, 4, 0x000b, 0x0006, -2, 8, 0x0100, a11, 0, 0, 0, 0, 0, 0) -XTREG(117, 468, 32, 4, 4, 0x000c, 0x0006, -2, 8, 0x0100, a12, 0, 0, 0, 0, 0, 0) -XTREG(118, 472, 32, 4, 4, 0x000d, 0x0006, -2, 8, 0x0100, a13, 0, 0, 0, 0, 0, 0) -XTREG(119, 476, 32, 4, 4, 0x000e, 0x0006, -2, 8, 0x0100, a14, 0, 0, 0, 0, 0, 0) -XTREG(120, 480, 32, 4, 4, 0x000f, 0x0006, -2, 8, 0x0100, a15, 0, 0, 0, 0, 0, 0) -XTREG_END diff --git a/target/xtensa/core-dc233c/xtensa-modules.c.inc b/target/xtensa/core-dc233c/xtensa-modules.c.inc new file mode 100644 index 0000000000..0f32f0804a --- /dev/null +++ b/target/xtensa/core-dc233c/xtensa-modules.c.inc @@ -0,0 +1,15205 @@ +/* Xtensa configuration-specific ISA information. + + Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "qemu/osdep.h" +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 71 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 231 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID6", 1, 0 }, + { "INSTPGSZID5", 1, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID6", 1, 0 }, + { "DATAPGSZID5", 1, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 78 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_LITBADDR, + STATE_LITBEN, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_ASID3, + STATE_ASID2, + STATE_ASID1, + STATE_INSTPGSZID6, + STATE_INSTPGSZID5, + STATE_INSTPGSZID4, + STATE_DATAPGSZID6, + STATE_DATAPGSZID5, + STATE_DATAPGSZID4, + STATE_PTBASE, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3 +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + return (*valp & ~0x1f) != 0; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mx_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_my_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +Operand_my_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mw_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr0_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr1_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr2_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_mr3_encode (uint32 *valp) +{ + return (*valp & ~0x3) != 0; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static int +Operand_tp7_decode (uint32 *valp) +{ + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; +} + +static int +Operand_tp7_encode (uint32 *valp) +{ + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; +} + +static int +Operand_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; +} + +static int +Operand_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_mx_encode, Operand_mx_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + Operand_my_encode, Operand_my_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_mw_encode, Operand_mw_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr0_encode, Operand_mr0_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr1_encode, Operand_mr1_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr2_encode, Operand_mr2_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_mr3_encode, Operand_mr3_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_immt, + OPERAND_imms, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_t, + OPERAND_bbi4, + OPERAND_bbi, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sae, + OPERAND_sal, + OPERAND_sargt, + OPERAND_sas4, + OPERAND_sas, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_bitindex, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'i' }, + { { STATE_INSTPGSZID5 }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'o' }, + { { STATE_INSTPGSZID5 }, 'o' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'm' }, + { { STATE_INSTPGSZID5 }, 'm' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'i' }, + { { STATE_DATAPGSZID5 }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'o' }, + { { STATE_DATAPGSZID5 }, 'o' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'm' }, + { { STATE_DATAPGSZID5 }, 'm' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_176_args, + 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rer */, + 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_wer */, + 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_176, + ICLASS_xt_iclass_wsr_176, + ICLASS_xt_iclass_rsr_208, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_wsr_ptevaddr, + ICLASS_xt_iclass_rsr_ptevaddr, + ICLASS_xt_iclass_xsr_ptevaddr, + ICLASS_xt_iclass_rsr_rasid, + ICLASS_xt_iclass_wsr_rasid, + ICLASS_xt_iclass_xsr_rasid, + ICLASS_xt_iclass_rsr_itlbcfg, + ICLASS_xt_iclass_wsr_itlbcfg, + ICLASS_xt_iclass_xsr_itlbcfg, + ICLASS_xt_iclass_rsr_dtlbcfg, + ICLASS_xt_iclass_wsr_dtlbcfg, + ICLASS_xt_iclass_xsr_dtlbcfg, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_ldpte, + ICLASS_xt_iclass_hwwitlba, + ICLASS_xt_iclass_hwwdtlba, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { + Opcode_wsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", ICLASS_xt_iclass_rsr_176, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "wsr.176", ICLASS_xt_iclass_wsr_176, + 0, + Opcode_wsr_176_encode_fns, 0, 0 }, + { "rsr.208", ICLASS_xt_iclass_rsr_208, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", ICLASS_xt_iclass_ldpte, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", ICLASS_xt_iclass_hwwitlba, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_SIMCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_176, + OPCODE_WSR_176, + OPCODE_RSR_208, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MUL_AA_LL, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_HH, + OPCODE_UMUL_AA_LL, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_HH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_HH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DD_LL, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_HH, + OPCODE_MULA_AA_LL, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_HH, + OPCODE_MULS_AA_LL, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_HH, + OPCODE_MULA_AD_LL, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_HH, + OPCODE_MULS_AD_LL, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_HH, + OPCODE_MULA_DA_LL, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_HH, + OPCODE_MULS_DA_LL, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_HH, + OPCODE_MULA_DD_LL, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_HH, + OPCODE_MULS_DD_LL, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_HH, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_DPFL, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_WSR_PTEVADDR, + OPCODE_RSR_PTEVADDR, + OPCODE_XSR_PTEVADDR, + OPCODE_RSR_RASID, + OPCODE_WSR_RASID, + OPCODE_XSR_RASID, + OPCODE_RSR_ITLBCFG, + OPCODE_WSR_ITLBCFG, + OPCODE_XSR_ITLBCFG, + OPCODE_RSR_DTLBCFG, + OPCODE_WSR_DTLBCFG, + OPCODE_XSR_DTLBCFG, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_LDPTE, + OPCODE_HWWITLBA, + OPCODE_HWWDTLBA, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RET; + case 1: + return OPCODE_RETW; + case 2: + return OPCODE_JX; + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALLX0; + case 1: + return OPCODE_CALLX4; + case 2: + return OPCODE_CALLX8; + case 3: + return OPCODE_CALLX12; + } + break; + } + break; + case 1: + return OPCODE_MOVSP; + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ISYNC; + case 1: + return OPCODE_RSYNC; + case 2: + return OPCODE_ESYNC; + case 3: + return OPCODE_DSYNC; + case 8: + return OPCODE_EXCW; + case 12: + return OPCODE_MEMW; + case 13: + return OPCODE_EXTW; + case 15: + return OPCODE_NOP; + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RFE; + case 2: + return OPCODE_RFDE; + case 4: + return OPCODE_RFWO; + case 5: + return OPCODE_RFWU; + } + break; + case 1: + return OPCODE_RFI; + } + break; + case 4: + return OPCODE_BREAK; + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + break; + } + break; + case 6: + return OPCODE_RSIL; + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + break; + } + break; + case 1: + return OPCODE_AND; + case 2: + return OPCODE_OR; + case 3: + return OPCODE_XOR; + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + break; + case 6: + return OPCODE_RER; + case 7: + return OPCODE_WER; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + break; + case 14: + return OPCODE_NSA; + case 15: + return OPCODE_NSAU; + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return OPCODE_HWWITLBA; + case 3: + return OPCODE_RITLB0; + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + break; + case 5: + return OPCODE_PITLB; + case 6: + return OPCODE_WITLB; + case 7: + return OPCODE_RITLB1; + case 9: + return OPCODE_HWWDTLBA; + case 11: + return OPCODE_RDTLB0; + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + break; + case 13: + return OPCODE_PDTLB; + case 14: + return OPCODE_WDTLB; + case 15: + return OPCODE_RDTLB1; + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_NEG; + case 1: + return OPCODE_ABS; + } + break; + case 8: + return OPCODE_ADD; + case 9: + return OPCODE_ADDX2; + case 10: + return OPCODE_ADDX4; + case 11: + return OPCODE_ADDX8; + case 12: + return OPCODE_SUB; + case 13: + return OPCODE_SUBX2; + case 14: + return OPCODE_SUBX4; + case 15: + return OPCODE_SUBX8; + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return OPCODE_SLLI; + case 2: + case 3: + return OPCODE_SRAI; + case 4: + return OPCODE_SRLI; + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_XSR_LBEG; + case 1: + return OPCODE_XSR_LEND; + case 2: + return OPCODE_XSR_LCOUNT; + case 3: + return OPCODE_XSR_SAR; + case 5: + return OPCODE_XSR_LITBASE; + case 12: + return OPCODE_XSR_SCOMPARE1; + case 16: + return OPCODE_XSR_ACCLO; + case 17: + return OPCODE_XSR_ACCHI; + case 32: + return OPCODE_XSR_M0; + case 33: + return OPCODE_XSR_M1; + case 34: + return OPCODE_XSR_M2; + case 35: + return OPCODE_XSR_M3; + case 72: + return OPCODE_XSR_WINDOWBASE; + case 73: + return OPCODE_XSR_WINDOWSTART; + case 83: + return OPCODE_XSR_PTEVADDR; + case 90: + return OPCODE_XSR_RASID; + case 91: + return OPCODE_XSR_ITLBCFG; + case 92: + return OPCODE_XSR_DTLBCFG; + case 96: + return OPCODE_XSR_IBREAKENABLE; + case 99: + return OPCODE_XSR_ATOMCTL; + case 104: + return OPCODE_XSR_DDR; + case 128: + return OPCODE_XSR_IBREAKA0; + case 129: + return OPCODE_XSR_IBREAKA1; + case 144: + return OPCODE_XSR_DBREAKA0; + case 145: + return OPCODE_XSR_DBREAKA1; + case 160: + return OPCODE_XSR_DBREAKC0; + case 161: + return OPCODE_XSR_DBREAKC1; + case 177: + return OPCODE_XSR_EPC1; + case 178: + return OPCODE_XSR_EPC2; + case 179: + return OPCODE_XSR_EPC3; + case 180: + return OPCODE_XSR_EPC4; + case 181: + return OPCODE_XSR_EPC5; + case 182: + return OPCODE_XSR_EPC6; + case 183: + return OPCODE_XSR_EPC7; + case 192: + return OPCODE_XSR_DEPC; + case 194: + return OPCODE_XSR_EPS2; + case 195: + return OPCODE_XSR_EPS3; + case 196: + return OPCODE_XSR_EPS4; + case 197: + return OPCODE_XSR_EPS5; + case 198: + return OPCODE_XSR_EPS6; + case 199: + return OPCODE_XSR_EPS7; + case 209: + return OPCODE_XSR_EXCSAVE1; + case 210: + return OPCODE_XSR_EXCSAVE2; + case 211: + return OPCODE_XSR_EXCSAVE3; + case 212: + return OPCODE_XSR_EXCSAVE4; + case 213: + return OPCODE_XSR_EXCSAVE5; + case 214: + return OPCODE_XSR_EXCSAVE6; + case 215: + return OPCODE_XSR_EXCSAVE7; + case 224: + return OPCODE_XSR_CPENABLE; + case 228: + return OPCODE_XSR_INTENABLE; + case 230: + return OPCODE_XSR_PS; + case 231: + return OPCODE_XSR_VECBASE; + case 232: + return OPCODE_XSR_EXCCAUSE; + case 233: + return OPCODE_XSR_DEBUGCAUSE; + case 234: + return OPCODE_XSR_CCOUNT; + case 236: + return OPCODE_XSR_ICOUNT; + case 237: + return OPCODE_XSR_ICOUNTLEVEL; + case 238: + return OPCODE_XSR_EXCVADDR; + case 240: + return OPCODE_XSR_CCOMPARE0; + case 241: + return OPCODE_XSR_CCOMPARE1; + case 242: + return OPCODE_XSR_CCOMPARE2; + case 244: + return OPCODE_XSR_MISC0; + case 245: + return OPCODE_XSR_MISC1; + } + break; + case 8: + return OPCODE_SRC; + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + break; + case 12: + return OPCODE_MUL16U; + case 13: + return OPCODE_MUL16S; + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_LICT; + case 1: + return OPCODE_SICT; + case 2: + return OPCODE_LICW; + case 3: + return OPCODE_SICW; + case 8: + return OPCODE_LDCT; + case 9: + return OPCODE_SDCT; + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + break; + case 15: + return OPCODE_LDPTE; + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 8: + return OPCODE_MULL; + case 12: + return OPCODE_QUOU; + case 13: + return OPCODE_QUOS; + case 14: + return OPCODE_REMU; + case 15: + return OPCODE_REMS; + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RSR_LBEG; + case 1: + return OPCODE_RSR_LEND; + case 2: + return OPCODE_RSR_LCOUNT; + case 3: + return OPCODE_RSR_SAR; + case 5: + return OPCODE_RSR_LITBASE; + case 12: + return OPCODE_RSR_SCOMPARE1; + case 16: + return OPCODE_RSR_ACCLO; + case 17: + return OPCODE_RSR_ACCHI; + case 32: + return OPCODE_RSR_M0; + case 33: + return OPCODE_RSR_M1; + case 34: + return OPCODE_RSR_M2; + case 35: + return OPCODE_RSR_M3; + case 72: + return OPCODE_RSR_WINDOWBASE; + case 73: + return OPCODE_RSR_WINDOWSTART; + case 83: + return OPCODE_RSR_PTEVADDR; + case 90: + return OPCODE_RSR_RASID; + case 91: + return OPCODE_RSR_ITLBCFG; + case 92: + return OPCODE_RSR_DTLBCFG; + case 96: + return OPCODE_RSR_IBREAKENABLE; + case 99: + return OPCODE_RSR_ATOMCTL; + case 104: + return OPCODE_RSR_DDR; + case 128: + return OPCODE_RSR_IBREAKA0; + case 129: + return OPCODE_RSR_IBREAKA1; + case 144: + return OPCODE_RSR_DBREAKA0; + case 145: + return OPCODE_RSR_DBREAKA1; + case 160: + return OPCODE_RSR_DBREAKC0; + case 161: + return OPCODE_RSR_DBREAKC1; + case 176: + return OPCODE_RSR_176; + case 177: + return OPCODE_RSR_EPC1; + case 178: + return OPCODE_RSR_EPC2; + case 179: + return OPCODE_RSR_EPC3; + case 180: + return OPCODE_RSR_EPC4; + case 181: + return OPCODE_RSR_EPC5; + case 182: + return OPCODE_RSR_EPC6; + case 183: + return OPCODE_RSR_EPC7; + case 192: + return OPCODE_RSR_DEPC; + case 194: + return OPCODE_RSR_EPS2; + case 195: + return OPCODE_RSR_EPS3; + case 196: + return OPCODE_RSR_EPS4; + case 197: + return OPCODE_RSR_EPS5; + case 198: + return OPCODE_RSR_EPS6; + case 199: + return OPCODE_RSR_EPS7; + case 208: + return OPCODE_RSR_208; + case 209: + return OPCODE_RSR_EXCSAVE1; + case 210: + return OPCODE_RSR_EXCSAVE2; + case 211: + return OPCODE_RSR_EXCSAVE3; + case 212: + return OPCODE_RSR_EXCSAVE4; + case 213: + return OPCODE_RSR_EXCSAVE5; + case 214: + return OPCODE_RSR_EXCSAVE6; + case 215: + return OPCODE_RSR_EXCSAVE7; + case 224: + return OPCODE_RSR_CPENABLE; + case 226: + return OPCODE_RSR_INTERRUPT; + case 228: + return OPCODE_RSR_INTENABLE; + case 230: + return OPCODE_RSR_PS; + case 231: + return OPCODE_RSR_VECBASE; + case 232: + return OPCODE_RSR_EXCCAUSE; + case 233: + return OPCODE_RSR_DEBUGCAUSE; + case 234: + return OPCODE_RSR_CCOUNT; + case 235: + return OPCODE_RSR_PRID; + case 236: + return OPCODE_RSR_ICOUNT; + case 237: + return OPCODE_RSR_ICOUNTLEVEL; + case 238: + return OPCODE_RSR_EXCVADDR; + case 240: + return OPCODE_RSR_CCOMPARE0; + case 241: + return OPCODE_RSR_CCOMPARE1; + case 242: + return OPCODE_RSR_CCOMPARE2; + case 244: + return OPCODE_RSR_MISC0; + case 245: + return OPCODE_RSR_MISC1; + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_WSR_LBEG; + case 1: + return OPCODE_WSR_LEND; + case 2: + return OPCODE_WSR_LCOUNT; + case 3: + return OPCODE_WSR_SAR; + case 5: + return OPCODE_WSR_LITBASE; + case 12: + return OPCODE_WSR_SCOMPARE1; + case 16: + return OPCODE_WSR_ACCLO; + case 17: + return OPCODE_WSR_ACCHI; + case 32: + return OPCODE_WSR_M0; + case 33: + return OPCODE_WSR_M1; + case 34: + return OPCODE_WSR_M2; + case 35: + return OPCODE_WSR_M3; + case 72: + return OPCODE_WSR_WINDOWBASE; + case 73: + return OPCODE_WSR_WINDOWSTART; + case 83: + return OPCODE_WSR_PTEVADDR; + case 89: + return OPCODE_WSR_MMID; + case 90: + return OPCODE_WSR_RASID; + case 91: + return OPCODE_WSR_ITLBCFG; + case 92: + return OPCODE_WSR_DTLBCFG; + case 96: + return OPCODE_WSR_IBREAKENABLE; + case 99: + return OPCODE_WSR_ATOMCTL; + case 104: + return OPCODE_WSR_DDR; + case 128: + return OPCODE_WSR_IBREAKA0; + case 129: + return OPCODE_WSR_IBREAKA1; + case 144: + return OPCODE_WSR_DBREAKA0; + case 145: + return OPCODE_WSR_DBREAKA1; + case 160: + return OPCODE_WSR_DBREAKC0; + case 161: + return OPCODE_WSR_DBREAKC1; + case 176: + return OPCODE_WSR_176; + case 177: + return OPCODE_WSR_EPC1; + case 178: + return OPCODE_WSR_EPC2; + case 179: + return OPCODE_WSR_EPC3; + case 180: + return OPCODE_WSR_EPC4; + case 181: + return OPCODE_WSR_EPC5; + case 182: + return OPCODE_WSR_EPC6; + case 183: + return OPCODE_WSR_EPC7; + case 192: + return OPCODE_WSR_DEPC; + case 194: + return OPCODE_WSR_EPS2; + case 195: + return OPCODE_WSR_EPS3; + case 196: + return OPCODE_WSR_EPS4; + case 197: + return OPCODE_WSR_EPS5; + case 198: + return OPCODE_WSR_EPS6; + case 199: + return OPCODE_WSR_EPS7; + case 209: + return OPCODE_WSR_EXCSAVE1; + case 210: + return OPCODE_WSR_EXCSAVE2; + case 211: + return OPCODE_WSR_EXCSAVE3; + case 212: + return OPCODE_WSR_EXCSAVE4; + case 213: + return OPCODE_WSR_EXCSAVE5; + case 214: + return OPCODE_WSR_EXCSAVE6; + case 215: + return OPCODE_WSR_EXCSAVE7; + case 224: + return OPCODE_WSR_CPENABLE; + case 226: + return OPCODE_WSR_INTSET; + case 227: + return OPCODE_WSR_INTCLEAR; + case 228: + return OPCODE_WSR_INTENABLE; + case 230: + return OPCODE_WSR_PS; + case 231: + return OPCODE_WSR_VECBASE; + case 232: + return OPCODE_WSR_EXCCAUSE; + case 233: + return OPCODE_WSR_DEBUGCAUSE; + case 234: + return OPCODE_WSR_CCOUNT; + case 236: + return OPCODE_WSR_ICOUNT; + case 237: + return OPCODE_WSR_ICOUNTLEVEL; + case 238: + return OPCODE_WSR_EXCVADDR; + case 240: + return OPCODE_WSR_CCOMPARE0; + case 241: + return OPCODE_WSR_CCOMPARE1; + case 242: + return OPCODE_WSR_CCOMPARE2; + case 244: + return OPCODE_WSR_MISC0; + case 245: + return OPCODE_WSR_MISC1; + } + break; + case 2: + return OPCODE_SEXT; + case 3: + return OPCODE_CLAMPS; + case 4: + return OPCODE_MIN; + case 5: + return OPCODE_MAX; + case 6: + return OPCODE_MINU; + case 7: + return OPCODE_MAXU; + case 8: + return OPCODE_MOVEQZ; + case 9: + return OPCODE_MOVNEZ; + case 10: + return OPCODE_MOVLTZ; + case 11: + return OPCODE_MOVGEZ; + case 14: + switch (Field_st_Slot_inst_get (insn)) + { + case 230: + return OPCODE_RUR_EXPSTATE; + case 231: + return OPCODE_RUR_THREADPTR; + } + break; + case 15: + switch (Field_sr_Slot_inst_get (insn)) + { + case 230: + return OPCODE_WUR_EXPSTATE; + case 231: + return OPCODE_WUR_THREADPTR; + } + break; + } + break; + case 4: + case 5: + return OPCODE_EXTUI; + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L32E; + case 4: + return OPCODE_S32E; + } + break; + } + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + break; + case 1: + if (Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + break; + case 2: + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + break; + } + break; + case 1: + return OPCODE_L32R; + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L8UI; + case 1: + return OPCODE_L16UI; + case 2: + return OPCODE_L32I; + case 4: + return OPCODE_S8I; + case 5: + return OPCODE_S16I; + case 6: + return OPCODE_S32I; + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFR; + case 1: + return OPCODE_DPFW; + case 2: + return OPCODE_DPFRO; + case 3: + return OPCODE_DPFWO; + case 4: + return OPCODE_DHWB; + case 5: + return OPCODE_DHWBI; + case 6: + return OPCODE_DHI; + case 7: + return OPCODE_DII; + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFL; + case 2: + return OPCODE_DHU; + case 3: + return OPCODE_DIU; + case 4: + return OPCODE_DIWB; + case 5: + return OPCODE_DIWBI; + } + break; + case 12: + return OPCODE_IPF; + case 13: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_IPFL; + case 2: + return OPCODE_IHU; + case 3: + return OPCODE_IIU; + } + break; + case 14: + return OPCODE_IHI; + case 15: + return OPCODE_III; + } + break; + case 9: + return OPCODE_L16SI; + case 10: + return OPCODE_MOVI; + case 11: + return OPCODE_L32AI; + case 12: + return OPCODE_ADDI; + case 13: + return OPCODE_ADDMI; + case 14: + return OPCODE_S32C1I; + case 15: + return OPCODE_S32RI; + } + break; + case 4: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + break; + } + break; + case 1: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + break; + case 9: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + break; + case 10: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + break; + case 11: + if (Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + break; + } + break; + case 2: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + break; + } + break; + case 3: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + break; + } + break; + case 4: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + break; + } + break; + case 5: + switch (Field_op1_Slot_inst_get (insn)) + { + case 8: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + break; + case 9: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + break; + case 10: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + break; + case 11: + if (Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + break; + } + break; + case 6: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + break; + case 5: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + break; + case 6: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + break; + case 7: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + break; + case 9: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + break; + case 10: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + break; + case 12: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + break; + case 13: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + break; + case 14: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + break; + case 15: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + break; + } + break; + case 7: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + break; + case 1: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + break; + case 2: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + break; + case 3: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + break; + case 4: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + break; + case 5: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + break; + case 6: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + break; + case 7: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + break; + case 8: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + break; + case 9: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + break; + case 10: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + break; + case 11: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + break; + case 12: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + break; + case 13: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + break; + case 14: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + break; + case 15: + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + break; + } + break; + case 8: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + break; + case 9: + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + break; + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALL0; + case 1: + return OPCODE_CALL4; + case 2: + return OPCODE_CALL8; + case 3: + return OPCODE_CALL12; + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_J; + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQZ; + case 1: + return OPCODE_BNEZ; + case 2: + return OPCODE_BLTZ; + case 3: + return OPCODE_BGEZ; + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQI; + case 1: + return OPCODE_BNEI; + case 2: + return OPCODE_BLTI; + case 3: + return OPCODE_BGEI; + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ENTRY; + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return OPCODE_LOOP; + case 9: + return OPCODE_LOOPNEZ; + case 10: + return OPCODE_LOOPGTZ; + } + break; + case 2: + return OPCODE_BLTUI; + case 3: + return OPCODE_BGEUI; + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BNONE; + case 1: + return OPCODE_BEQ; + case 2: + return OPCODE_BLT; + case 3: + return OPCODE_BLTU; + case 4: + return OPCODE_BALL; + case 5: + return OPCODE_BBC; + case 6: + case 7: + return OPCODE_BBCI; + case 8: + return OPCODE_BANY; + case 9: + return OPCODE_BNE; + case 10: + return OPCODE_BGE; + case 11: + return OPCODE_BGEU; + case 12: + return OPCODE_BNALL; + case 13: + return OPCODE_BBS; + case 14: + case 15: + return OPCODE_BBSI; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOVI_N; + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_BEQZ_N; + case 1: + return OPCODE_BNEZ_N; + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOV_N; + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_RET_N; + case 1: + return OPCODE_RETW_N; + case 2: + return OPCODE_BREAK_N; + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return OPCODE_L32I_N; + case 9: + return OPCODE_S32I_N; + case 10: + return OPCODE_ADD_N; + case 11: + return OPCODE_ADDI_N; + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = insn[0] & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 56 /* num_fields */, + 93, operands, + 326, iclasses, + 452, opcodes, 0, + 2, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-dc233c/xtensa-modules.inc.c b/target/xtensa/core-dc233c/xtensa-modules.inc.c deleted file mode 100644 index 0f32f0804a..0000000000 --- a/target/xtensa/core-dc233c/xtensa-modules.inc.c +++ /dev/null @@ -1,15205 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "qemu/osdep.h" -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "PTEVADDR", 83, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "176", 176, 0 }, - { "208", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "LITBASE", 5, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "THREADPTR", 231, 1 }, - { "EXPSTATE", 230, 1 } -}; - -#define NUM_SYSREGS 71 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 231 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 15, 0 }, - { "EPS3", 15, 0 }, - { "EPS4", 15, 0 }, - { "EPS5", 15, 0 }, - { "EPS6", 15, 0 }, - { "EPS7", 15, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "LITBADDR", 20, 0 }, - { "LITBEN", 1, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID6", 1, 0 }, - { "INSTPGSZID5", 1, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID6", 1, 0 }, - { "DATAPGSZID5", 1, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 }, - { "CPENABLE", 8, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } -}; - -#define NUM_STATES 78 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSRING, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_THREADPTR, - STATE_LITBADDR, - STATE_LITBEN, - STATE_MISC0, - STATE_MISC1, - STATE_ACC, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_ASID3, - STATE_ASID2, - STATE_ASID1, - STATE_INSTPGSZID6, - STATE_INSTPGSZID5, - STATE_INSTPGSZID4, - STATE_DATAPGSZID6, - STATE_DATAPGSZID5, - STATE_DATAPGSZID4, - STATE_PTBASE, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_EXPSTATE -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_r3, - FIELD_rbit2, - FIELD_rhi, - FIELD_t3, - FIELD_tbit2, - FIELD_tlo, - FIELD_w, - FIELD_y, - FIELD_x, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__mr0, - FIELD__mr1, - FIELD__mr2, - FIELD__mr3 -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_MR -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "MR", "m", REGFILE_MR, 32, 4 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "IMPWIRE", 32, 0, 0, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0, soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0, imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} - -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0, uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} - -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0, mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} - -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0, simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} - -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_arr_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_art_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar0_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar4_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar8_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar12_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_entry_encode (uint32 *valp) -{ - return (*valp & ~0x1f) != 0; -} - -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0, r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} - -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0, immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0, r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} - -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0, lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0, imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} - -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0, simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} - -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0, imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} - -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0, uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0, t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0, ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} - -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0, r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} - -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0, b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0, r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} - -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0, b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} - -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} - -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0, op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} - -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0, uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} - -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} - -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0, simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} - -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0, simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0, imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0, simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0, sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0, msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0, op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0, op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0, imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0, label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0, imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} - -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0, ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0, imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} - -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0, label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} - -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0, soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0, imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} - -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0, uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mx_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_my_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -Operand_my_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mw_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr0_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr1_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr2_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_mr3_encode (uint32 *valp) -{ - return (*valp & ~0x3) != 0; -} - -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0, t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} - -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0, immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0, s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} - -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0, imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} - -static int -Operand_tp7_decode (uint32 *valp) -{ - unsigned tp7_0, t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; - return 0; -} - -static int -Operand_tp7_encode (uint32 *valp) -{ - unsigned t_0, tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_0, xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; - return 0; -} - -static int -Operand_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_imm_0, xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_0, xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; - return 0; -} - -static int -Operand_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_imm_0, xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "mx", FIELD_x, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_mx_encode, Operand_mx_decode, - 0, 0 }, - { "my", FIELD_y, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - Operand_my_encode, Operand_my_decode, - 0, 0 }, - { "mw", FIELD_w, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_mw_encode, Operand_mw_decode, - 0, 0 }, - { "mr0", FIELD__mr0, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr0_encode, Operand_mr0_decode, - 0, 0 }, - { "mr1", FIELD__mr1, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr1_encode, Operand_mr1_decode, - 0, 0 }, - { "mr2", FIELD__mr2, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr2_encode, Operand_mr2_decode, - 0, 0 }, - { "mr3", FIELD__mr3, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_mr3_encode, Operand_mr3_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - Operand_tp7_encode, Operand_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, - { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, - { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, - { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_mx, - OPERAND_my, - OPERAND_mw, - OPERAND_mr0, - OPERAND_mr1, - OPERAND_mr2, - OPERAND_mr3, - OPERAND_immt, - OPERAND_imms, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_t, - OPERAND_bbi4, - OPERAND_bbi, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_s, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sae, - OPERAND_sal, - OPERAND_sargt, - OPERAND_sas4, - OPERAND_sas, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_r3, - OPERAND_rbit2, - OPERAND_rhi, - OPERAND_t3, - OPERAND_tbit2, - OPERAND_tlo, - OPERAND_w, - OPERAND_y, - OPERAND_x, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_bitindex, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'o' }, - { { STATE_LITBEN }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'm' }, - { { STATE_LITBEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'i' }, - { { STATE_INSTPGSZID5 }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'o' }, - { { STATE_INSTPGSZID5 }, 'o' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'm' }, - { { STATE_INSTPGSZID5 }, 'm' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'i' }, - { { STATE_DATAPGSZID5 }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'o' }, - { { STATE_DATAPGSZID5 }, 'o' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'm' }, - { { STATE_DATAPGSZID5 }, 'm' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_176_args, - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_176_args, - 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_208_args, - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rer */, - 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_wer */, - 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, - { 1, Iclass_rur_expstate_args, - 2, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 2, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_rur_threadptr, - ICLASS_wur_threadptr, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_176, - ICLASS_xt_iclass_wsr_176, - ICLASS_xt_iclass_rsr_208, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_mac16_aa, - ICLASS_xt_iclass_mac16_ad, - ICLASS_xt_iclass_mac16_da, - ICLASS_xt_iclass_mac16_dd, - ICLASS_xt_iclass_mac16a_aa, - ICLASS_xt_iclass_mac16a_ad, - ICLASS_xt_iclass_mac16a_da, - ICLASS_xt_iclass_mac16a_dd, - ICLASS_xt_iclass_mac16al_da, - ICLASS_xt_iclass_mac16al_dd, - ICLASS_xt_iclass_mac16_l, - ICLASS_xt_iclass_rsr_m0, - ICLASS_xt_iclass_wsr_m0, - ICLASS_xt_iclass_xsr_m0, - ICLASS_xt_iclass_rsr_m1, - ICLASS_xt_iclass_wsr_m1, - ICLASS_xt_iclass_xsr_m1, - ICLASS_xt_iclass_rsr_m2, - ICLASS_xt_iclass_wsr_m2, - ICLASS_xt_iclass_xsr_m2, - ICLASS_xt_iclass_rsr_m3, - ICLASS_xt_iclass_wsr_m3, - ICLASS_xt_iclass_xsr_m3, - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_wsr_ptevaddr, - ICLASS_xt_iclass_rsr_ptevaddr, - ICLASS_xt_iclass_xsr_ptevaddr, - ICLASS_xt_iclass_rsr_rasid, - ICLASS_xt_iclass_wsr_rasid, - ICLASS_xt_iclass_xsr_rasid, - ICLASS_xt_iclass_rsr_itlbcfg, - ICLASS_xt_iclass_wsr_itlbcfg, - ICLASS_xt_iclass_xsr_itlbcfg, - ICLASS_xt_iclass_rsr_dtlbcfg, - ICLASS_xt_iclass_wsr_dtlbcfg, - ICLASS_xt_iclass_xsr_dtlbcfg, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_ldpte, - ICLASS_xt_iclass_hwwitlba, - ICLASS_xt_iclass_hwwdtlba, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135300; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35300; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615300; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35a00; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135a00; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615a00; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35b00; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135b00; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615b00; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35c00; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135c00; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615c00; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f000; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501000; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x509000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { - Opcode_rsr_176_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { - Opcode_wsr_176_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { - Opcode_rsr_208_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 -}; - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.176", ICLASS_xt_iclass_rsr_176, - 0, - Opcode_rsr_176_encode_fns, 0, 0 }, - { "wsr.176", ICLASS_xt_iclass_wsr_176, - 0, - Opcode_wsr_176_encode_fns, 0, 0 }, - { "rsr.208", ICLASS_xt_iclass_rsr_208, - 0, - Opcode_rsr_208_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "rsr.m0", ICLASS_xt_iclass_rsr_m0, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", ICLASS_xt_iclass_wsr_m0, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", ICLASS_xt_iclass_xsr_m0, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", ICLASS_xt_iclass_rsr_m1, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", ICLASS_xt_iclass_wsr_m1, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", ICLASS_xt_iclass_xsr_m1, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", ICLASS_xt_iclass_rsr_m2, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", ICLASS_xt_iclass_wsr_m2, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", ICLASS_xt_iclass_xsr_m2, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", ICLASS_xt_iclass_rsr_m3, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", ICLASS_xt_iclass_wsr_m3, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", ICLASS_xt_iclass_xsr_m3, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", ICLASS_xt_iclass_ldpte, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", ICLASS_xt_iclass_hwwitlba, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_SIMCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_176, - OPCODE_WSR_176, - OPCODE_RSR_208, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_MUL_AA_LL, - OPCODE_MUL_AA_HL, - OPCODE_MUL_AA_LH, - OPCODE_MUL_AA_HH, - OPCODE_UMUL_AA_LL, - OPCODE_UMUL_AA_HL, - OPCODE_UMUL_AA_LH, - OPCODE_UMUL_AA_HH, - OPCODE_MUL_AD_LL, - OPCODE_MUL_AD_HL, - OPCODE_MUL_AD_LH, - OPCODE_MUL_AD_HH, - OPCODE_MUL_DA_LL, - OPCODE_MUL_DA_HL, - OPCODE_MUL_DA_LH, - OPCODE_MUL_DA_HH, - OPCODE_MUL_DD_LL, - OPCODE_MUL_DD_HL, - OPCODE_MUL_DD_LH, - OPCODE_MUL_DD_HH, - OPCODE_MULA_AA_LL, - OPCODE_MULA_AA_HL, - OPCODE_MULA_AA_LH, - OPCODE_MULA_AA_HH, - OPCODE_MULS_AA_LL, - OPCODE_MULS_AA_HL, - OPCODE_MULS_AA_LH, - OPCODE_MULS_AA_HH, - OPCODE_MULA_AD_LL, - OPCODE_MULA_AD_HL, - OPCODE_MULA_AD_LH, - OPCODE_MULA_AD_HH, - OPCODE_MULS_AD_LL, - OPCODE_MULS_AD_HL, - OPCODE_MULS_AD_LH, - OPCODE_MULS_AD_HH, - OPCODE_MULA_DA_LL, - OPCODE_MULA_DA_HL, - OPCODE_MULA_DA_LH, - OPCODE_MULA_DA_HH, - OPCODE_MULS_DA_LL, - OPCODE_MULS_DA_HL, - OPCODE_MULS_DA_LH, - OPCODE_MULS_DA_HH, - OPCODE_MULA_DD_LL, - OPCODE_MULA_DD_HL, - OPCODE_MULA_DD_LH, - OPCODE_MULA_DD_HH, - OPCODE_MULS_DD_LL, - OPCODE_MULS_DD_HL, - OPCODE_MULS_DD_LH, - OPCODE_MULS_DD_HH, - OPCODE_MULA_DA_LL_LDDEC, - OPCODE_MULA_DA_LL_LDINC, - OPCODE_MULA_DA_HL_LDDEC, - OPCODE_MULA_DA_HL_LDINC, - OPCODE_MULA_DA_LH_LDDEC, - OPCODE_MULA_DA_LH_LDINC, - OPCODE_MULA_DA_HH_LDDEC, - OPCODE_MULA_DA_HH_LDINC, - OPCODE_MULA_DD_LL_LDDEC, - OPCODE_MULA_DD_LL_LDINC, - OPCODE_MULA_DD_HL_LDDEC, - OPCODE_MULA_DD_HL_LDINC, - OPCODE_MULA_DD_LH_LDDEC, - OPCODE_MULA_DD_LH_LDINC, - OPCODE_MULA_DD_HH_LDDEC, - OPCODE_MULA_DD_HH_LDINC, - OPCODE_LDDEC, - OPCODE_LDINC, - OPCODE_RSR_M0, - OPCODE_WSR_M0, - OPCODE_XSR_M0, - OPCODE_RSR_M1, - OPCODE_WSR_M1, - OPCODE_XSR_M1, - OPCODE_RSR_M2, - OPCODE_WSR_M2, - OPCODE_XSR_M2, - OPCODE_RSR_M3, - OPCODE_WSR_M3, - OPCODE_XSR_M3, - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_WSR_PTEVADDR, - OPCODE_RSR_PTEVADDR, - OPCODE_XSR_PTEVADDR, - OPCODE_RSR_RASID, - OPCODE_WSR_RASID, - OPCODE_XSR_RASID, - OPCODE_RSR_ITLBCFG, - OPCODE_WSR_ITLBCFG, - OPCODE_XSR_ITLBCFG, - OPCODE_RSR_DTLBCFG, - OPCODE_WSR_DTLBCFG, - OPCODE_XSR_DTLBCFG, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_LDPTE, - OPCODE_HWWITLBA, - OPCODE_HWWDTLBA, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - break; - case 2: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RET; - case 1: - return OPCODE_RETW; - case 2: - return OPCODE_JX; - } - break; - case 3: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_CALLX0; - case 1: - return OPCODE_CALLX4; - case 2: - return OPCODE_CALLX8; - case 3: - return OPCODE_CALLX12; - } - break; - } - break; - case 1: - return OPCODE_MOVSP; - case 2: - if (Field_s_Slot_inst_get (insn) == 0) - { - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return OPCODE_ISYNC; - case 1: - return OPCODE_RSYNC; - case 2: - return OPCODE_ESYNC; - case 3: - return OPCODE_DSYNC; - case 8: - return OPCODE_EXCW; - case 12: - return OPCODE_MEMW; - case 13: - return OPCODE_EXTW; - case 15: - return OPCODE_NOP; - } - } - break; - case 3: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RFE; - case 2: - return OPCODE_RFDE; - case 4: - return OPCODE_RFWO; - case 5: - return OPCODE_RFWU; - } - break; - case 1: - return OPCODE_RFI; - } - break; - case 4: - return OPCODE_BREAK; - case 5: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - break; - } - break; - case 6: - return OPCODE_RSIL; - case 7: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - break; - } - break; - case 1: - return OPCODE_AND; - case 2: - return OPCODE_OR; - case 3: - return OPCODE_XOR; - case 4: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - break; - case 4: - if (Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - break; - case 6: - return OPCODE_RER; - case 7: - return OPCODE_WER; - case 8: - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - break; - case 14: - return OPCODE_NSA; - case 15: - return OPCODE_NSAU; - } - break; - case 5: - switch (Field_r_Slot_inst_get (insn)) - { - case 1: - return OPCODE_HWWITLBA; - case 3: - return OPCODE_RITLB0; - case 4: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - break; - case 5: - return OPCODE_PITLB; - case 6: - return OPCODE_WITLB; - case 7: - return OPCODE_RITLB1; - case 9: - return OPCODE_HWWDTLBA; - case 11: - return OPCODE_RDTLB0; - case 12: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - break; - case 13: - return OPCODE_PDTLB; - case 14: - return OPCODE_WDTLB; - case 15: - return OPCODE_RDTLB1; - } - break; - case 6: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return OPCODE_NEG; - case 1: - return OPCODE_ABS; - } - break; - case 8: - return OPCODE_ADD; - case 9: - return OPCODE_ADDX2; - case 10: - return OPCODE_ADDX4; - case 11: - return OPCODE_ADDX8; - case 12: - return OPCODE_SUB; - case 13: - return OPCODE_SUBX2; - case 14: - return OPCODE_SUBX4; - case 15: - return OPCODE_SUBX8; - } - break; - case 1: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - case 1: - return OPCODE_SLLI; - case 2: - case 3: - return OPCODE_SRAI; - case 4: - return OPCODE_SRLI; - case 6: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_XSR_LBEG; - case 1: - return OPCODE_XSR_LEND; - case 2: - return OPCODE_XSR_LCOUNT; - case 3: - return OPCODE_XSR_SAR; - case 5: - return OPCODE_XSR_LITBASE; - case 12: - return OPCODE_XSR_SCOMPARE1; - case 16: - return OPCODE_XSR_ACCLO; - case 17: - return OPCODE_XSR_ACCHI; - case 32: - return OPCODE_XSR_M0; - case 33: - return OPCODE_XSR_M1; - case 34: - return OPCODE_XSR_M2; - case 35: - return OPCODE_XSR_M3; - case 72: - return OPCODE_XSR_WINDOWBASE; - case 73: - return OPCODE_XSR_WINDOWSTART; - case 83: - return OPCODE_XSR_PTEVADDR; - case 90: - return OPCODE_XSR_RASID; - case 91: - return OPCODE_XSR_ITLBCFG; - case 92: - return OPCODE_XSR_DTLBCFG; - case 96: - return OPCODE_XSR_IBREAKENABLE; - case 99: - return OPCODE_XSR_ATOMCTL; - case 104: - return OPCODE_XSR_DDR; - case 128: - return OPCODE_XSR_IBREAKA0; - case 129: - return OPCODE_XSR_IBREAKA1; - case 144: - return OPCODE_XSR_DBREAKA0; - case 145: - return OPCODE_XSR_DBREAKA1; - case 160: - return OPCODE_XSR_DBREAKC0; - case 161: - return OPCODE_XSR_DBREAKC1; - case 177: - return OPCODE_XSR_EPC1; - case 178: - return OPCODE_XSR_EPC2; - case 179: - return OPCODE_XSR_EPC3; - case 180: - return OPCODE_XSR_EPC4; - case 181: - return OPCODE_XSR_EPC5; - case 182: - return OPCODE_XSR_EPC6; - case 183: - return OPCODE_XSR_EPC7; - case 192: - return OPCODE_XSR_DEPC; - case 194: - return OPCODE_XSR_EPS2; - case 195: - return OPCODE_XSR_EPS3; - case 196: - return OPCODE_XSR_EPS4; - case 197: - return OPCODE_XSR_EPS5; - case 198: - return OPCODE_XSR_EPS6; - case 199: - return OPCODE_XSR_EPS7; - case 209: - return OPCODE_XSR_EXCSAVE1; - case 210: - return OPCODE_XSR_EXCSAVE2; - case 211: - return OPCODE_XSR_EXCSAVE3; - case 212: - return OPCODE_XSR_EXCSAVE4; - case 213: - return OPCODE_XSR_EXCSAVE5; - case 214: - return OPCODE_XSR_EXCSAVE6; - case 215: - return OPCODE_XSR_EXCSAVE7; - case 224: - return OPCODE_XSR_CPENABLE; - case 228: - return OPCODE_XSR_INTENABLE; - case 230: - return OPCODE_XSR_PS; - case 231: - return OPCODE_XSR_VECBASE; - case 232: - return OPCODE_XSR_EXCCAUSE; - case 233: - return OPCODE_XSR_DEBUGCAUSE; - case 234: - return OPCODE_XSR_CCOUNT; - case 236: - return OPCODE_XSR_ICOUNT; - case 237: - return OPCODE_XSR_ICOUNTLEVEL; - case 238: - return OPCODE_XSR_EXCVADDR; - case 240: - return OPCODE_XSR_CCOMPARE0; - case 241: - return OPCODE_XSR_CCOMPARE1; - case 242: - return OPCODE_XSR_CCOMPARE2; - case 244: - return OPCODE_XSR_MISC0; - case 245: - return OPCODE_XSR_MISC1; - } - break; - case 8: - return OPCODE_SRC; - case 9: - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - break; - case 12: - return OPCODE_MUL16U; - case 13: - return OPCODE_MUL16S; - case 15: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_LICT; - case 1: - return OPCODE_SICT; - case 2: - return OPCODE_LICW; - case 3: - return OPCODE_SICW; - case 8: - return OPCODE_LDCT; - case 9: - return OPCODE_SDCT; - case 14: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - break; - case 15: - return OPCODE_LDPTE; - } - break; - } - break; - case 2: - switch (Field_op2_Slot_inst_get (insn)) - { - case 8: - return OPCODE_MULL; - case 12: - return OPCODE_QUOU; - case 13: - return OPCODE_QUOS; - case 14: - return OPCODE_REMU; - case 15: - return OPCODE_REMS; - } - break; - case 3: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RSR_LBEG; - case 1: - return OPCODE_RSR_LEND; - case 2: - return OPCODE_RSR_LCOUNT; - case 3: - return OPCODE_RSR_SAR; - case 5: - return OPCODE_RSR_LITBASE; - case 12: - return OPCODE_RSR_SCOMPARE1; - case 16: - return OPCODE_RSR_ACCLO; - case 17: - return OPCODE_RSR_ACCHI; - case 32: - return OPCODE_RSR_M0; - case 33: - return OPCODE_RSR_M1; - case 34: - return OPCODE_RSR_M2; - case 35: - return OPCODE_RSR_M3; - case 72: - return OPCODE_RSR_WINDOWBASE; - case 73: - return OPCODE_RSR_WINDOWSTART; - case 83: - return OPCODE_RSR_PTEVADDR; - case 90: - return OPCODE_RSR_RASID; - case 91: - return OPCODE_RSR_ITLBCFG; - case 92: - return OPCODE_RSR_DTLBCFG; - case 96: - return OPCODE_RSR_IBREAKENABLE; - case 99: - return OPCODE_RSR_ATOMCTL; - case 104: - return OPCODE_RSR_DDR; - case 128: - return OPCODE_RSR_IBREAKA0; - case 129: - return OPCODE_RSR_IBREAKA1; - case 144: - return OPCODE_RSR_DBREAKA0; - case 145: - return OPCODE_RSR_DBREAKA1; - case 160: - return OPCODE_RSR_DBREAKC0; - case 161: - return OPCODE_RSR_DBREAKC1; - case 176: - return OPCODE_RSR_176; - case 177: - return OPCODE_RSR_EPC1; - case 178: - return OPCODE_RSR_EPC2; - case 179: - return OPCODE_RSR_EPC3; - case 180: - return OPCODE_RSR_EPC4; - case 181: - return OPCODE_RSR_EPC5; - case 182: - return OPCODE_RSR_EPC6; - case 183: - return OPCODE_RSR_EPC7; - case 192: - return OPCODE_RSR_DEPC; - case 194: - return OPCODE_RSR_EPS2; - case 195: - return OPCODE_RSR_EPS3; - case 196: - return OPCODE_RSR_EPS4; - case 197: - return OPCODE_RSR_EPS5; - case 198: - return OPCODE_RSR_EPS6; - case 199: - return OPCODE_RSR_EPS7; - case 208: - return OPCODE_RSR_208; - case 209: - return OPCODE_RSR_EXCSAVE1; - case 210: - return OPCODE_RSR_EXCSAVE2; - case 211: - return OPCODE_RSR_EXCSAVE3; - case 212: - return OPCODE_RSR_EXCSAVE4; - case 213: - return OPCODE_RSR_EXCSAVE5; - case 214: - return OPCODE_RSR_EXCSAVE6; - case 215: - return OPCODE_RSR_EXCSAVE7; - case 224: - return OPCODE_RSR_CPENABLE; - case 226: - return OPCODE_RSR_INTERRUPT; - case 228: - return OPCODE_RSR_INTENABLE; - case 230: - return OPCODE_RSR_PS; - case 231: - return OPCODE_RSR_VECBASE; - case 232: - return OPCODE_RSR_EXCCAUSE; - case 233: - return OPCODE_RSR_DEBUGCAUSE; - case 234: - return OPCODE_RSR_CCOUNT; - case 235: - return OPCODE_RSR_PRID; - case 236: - return OPCODE_RSR_ICOUNT; - case 237: - return OPCODE_RSR_ICOUNTLEVEL; - case 238: - return OPCODE_RSR_EXCVADDR; - case 240: - return OPCODE_RSR_CCOMPARE0; - case 241: - return OPCODE_RSR_CCOMPARE1; - case 242: - return OPCODE_RSR_CCOMPARE2; - case 244: - return OPCODE_RSR_MISC0; - case 245: - return OPCODE_RSR_MISC1; - } - break; - case 1: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_WSR_LBEG; - case 1: - return OPCODE_WSR_LEND; - case 2: - return OPCODE_WSR_LCOUNT; - case 3: - return OPCODE_WSR_SAR; - case 5: - return OPCODE_WSR_LITBASE; - case 12: - return OPCODE_WSR_SCOMPARE1; - case 16: - return OPCODE_WSR_ACCLO; - case 17: - return OPCODE_WSR_ACCHI; - case 32: - return OPCODE_WSR_M0; - case 33: - return OPCODE_WSR_M1; - case 34: - return OPCODE_WSR_M2; - case 35: - return OPCODE_WSR_M3; - case 72: - return OPCODE_WSR_WINDOWBASE; - case 73: - return OPCODE_WSR_WINDOWSTART; - case 83: - return OPCODE_WSR_PTEVADDR; - case 89: - return OPCODE_WSR_MMID; - case 90: - return OPCODE_WSR_RASID; - case 91: - return OPCODE_WSR_ITLBCFG; - case 92: - return OPCODE_WSR_DTLBCFG; - case 96: - return OPCODE_WSR_IBREAKENABLE; - case 99: - return OPCODE_WSR_ATOMCTL; - case 104: - return OPCODE_WSR_DDR; - case 128: - return OPCODE_WSR_IBREAKA0; - case 129: - return OPCODE_WSR_IBREAKA1; - case 144: - return OPCODE_WSR_DBREAKA0; - case 145: - return OPCODE_WSR_DBREAKA1; - case 160: - return OPCODE_WSR_DBREAKC0; - case 161: - return OPCODE_WSR_DBREAKC1; - case 176: - return OPCODE_WSR_176; - case 177: - return OPCODE_WSR_EPC1; - case 178: - return OPCODE_WSR_EPC2; - case 179: - return OPCODE_WSR_EPC3; - case 180: - return OPCODE_WSR_EPC4; - case 181: - return OPCODE_WSR_EPC5; - case 182: - return OPCODE_WSR_EPC6; - case 183: - return OPCODE_WSR_EPC7; - case 192: - return OPCODE_WSR_DEPC; - case 194: - return OPCODE_WSR_EPS2; - case 195: - return OPCODE_WSR_EPS3; - case 196: - return OPCODE_WSR_EPS4; - case 197: - return OPCODE_WSR_EPS5; - case 198: - return OPCODE_WSR_EPS6; - case 199: - return OPCODE_WSR_EPS7; - case 209: - return OPCODE_WSR_EXCSAVE1; - case 210: - return OPCODE_WSR_EXCSAVE2; - case 211: - return OPCODE_WSR_EXCSAVE3; - case 212: - return OPCODE_WSR_EXCSAVE4; - case 213: - return OPCODE_WSR_EXCSAVE5; - case 214: - return OPCODE_WSR_EXCSAVE6; - case 215: - return OPCODE_WSR_EXCSAVE7; - case 224: - return OPCODE_WSR_CPENABLE; - case 226: - return OPCODE_WSR_INTSET; - case 227: - return OPCODE_WSR_INTCLEAR; - case 228: - return OPCODE_WSR_INTENABLE; - case 230: - return OPCODE_WSR_PS; - case 231: - return OPCODE_WSR_VECBASE; - case 232: - return OPCODE_WSR_EXCCAUSE; - case 233: - return OPCODE_WSR_DEBUGCAUSE; - case 234: - return OPCODE_WSR_CCOUNT; - case 236: - return OPCODE_WSR_ICOUNT; - case 237: - return OPCODE_WSR_ICOUNTLEVEL; - case 238: - return OPCODE_WSR_EXCVADDR; - case 240: - return OPCODE_WSR_CCOMPARE0; - case 241: - return OPCODE_WSR_CCOMPARE1; - case 242: - return OPCODE_WSR_CCOMPARE2; - case 244: - return OPCODE_WSR_MISC0; - case 245: - return OPCODE_WSR_MISC1; - } - break; - case 2: - return OPCODE_SEXT; - case 3: - return OPCODE_CLAMPS; - case 4: - return OPCODE_MIN; - case 5: - return OPCODE_MAX; - case 6: - return OPCODE_MINU; - case 7: - return OPCODE_MAXU; - case 8: - return OPCODE_MOVEQZ; - case 9: - return OPCODE_MOVNEZ; - case 10: - return OPCODE_MOVLTZ; - case 11: - return OPCODE_MOVGEZ; - case 14: - switch (Field_st_Slot_inst_get (insn)) - { - case 230: - return OPCODE_RUR_EXPSTATE; - case 231: - return OPCODE_RUR_THREADPTR; - } - break; - case 15: - switch (Field_sr_Slot_inst_get (insn)) - { - case 230: - return OPCODE_WUR_EXPSTATE; - case 231: - return OPCODE_WUR_THREADPTR; - } - break; - } - break; - case 4: - case 5: - return OPCODE_EXTUI; - case 9: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return OPCODE_L32E; - case 4: - return OPCODE_S32E; - } - break; - } - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - break; - case 1: - if (Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - break; - case 2: - if (Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - break; - } - break; - case 1: - return OPCODE_L32R; - case 2: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_L8UI; - case 1: - return OPCODE_L16UI; - case 2: - return OPCODE_L32I; - case 4: - return OPCODE_S8I; - case 5: - return OPCODE_S16I; - case 6: - return OPCODE_S32I; - case 7: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return OPCODE_DPFR; - case 1: - return OPCODE_DPFW; - case 2: - return OPCODE_DPFRO; - case 3: - return OPCODE_DPFWO; - case 4: - return OPCODE_DHWB; - case 5: - return OPCODE_DHWBI; - case 6: - return OPCODE_DHI; - case 7: - return OPCODE_DII; - case 8: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return OPCODE_DPFL; - case 2: - return OPCODE_DHU; - case 3: - return OPCODE_DIU; - case 4: - return OPCODE_DIWB; - case 5: - return OPCODE_DIWBI; - } - break; - case 12: - return OPCODE_IPF; - case 13: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - return OPCODE_IPFL; - case 2: - return OPCODE_IHU; - case 3: - return OPCODE_IIU; - } - break; - case 14: - return OPCODE_IHI; - case 15: - return OPCODE_III; - } - break; - case 9: - return OPCODE_L16SI; - case 10: - return OPCODE_MOVI; - case 11: - return OPCODE_L32AI; - case 12: - return OPCODE_ADDI; - case 13: - return OPCODE_ADDMI; - case 14: - return OPCODE_S32C1I; - case 15: - return OPCODE_S32RI; - } - break; - case 4: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDINC; - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDINC; - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDINC; - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDINC; - break; - } - break; - case 1: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDDEC; - break; - case 9: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDDEC; - break; - case 10: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDDEC; - break; - case 11: - if (Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDDEC; - break; - } - break; - case 2: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LL; - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HL; - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LH; - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HH; - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL; - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL; - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH; - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH; - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LL; - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HL; - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LH; - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HH; - break; - } - break; - case 3: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LL; - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HL; - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LH; - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HH; - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LL; - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HL; - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LH; - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HH; - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LL; - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HL; - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LH; - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HH; - break; - } - break; - case 4: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDINC; - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDINC; - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDINC; - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDINC; - break; - } - break; - case 5: - switch (Field_op1_Slot_inst_get (insn)) - { - case 8: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDDEC; - break; - case 9: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDDEC; - break; - case 10: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDDEC; - break; - case 11: - if (Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDDEC; - break; - } - break; - case 6: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LL; - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HL; - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LH; - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HH; - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL; - break; - case 9: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL; - break; - case 10: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH; - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH; - break; - case 12: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LL; - break; - case 13: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HL; - break; - case 14: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LH; - break; - case 15: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HH; - break; - } - break; - case 7: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LL; - break; - case 1: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HL; - break; - case 2: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LH; - break; - case 3: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HH; - break; - case 4: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LL; - break; - case 5: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HL; - break; - case 6: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LH; - break; - case 7: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HH; - break; - case 8: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LL; - break; - case 9: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HL; - break; - case 10: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LH; - break; - case 11: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HH; - break; - case 12: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LL; - break; - case 13: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HL; - break; - case 14: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LH; - break; - case 15: - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HH; - break; - } - break; - case 8: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDINC; - break; - case 9: - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDDEC; - break; - } - break; - case 5: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_CALL0; - case 1: - return OPCODE_CALL4; - case 2: - return OPCODE_CALL8; - case 3: - return OPCODE_CALL12; - } - break; - case 6: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_J; - case 1: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BEQZ; - case 1: - return OPCODE_BNEZ; - case 2: - return OPCODE_BLTZ; - case 3: - return OPCODE_BGEZ; - } - break; - case 2: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BEQI; - case 1: - return OPCODE_BNEI; - case 2: - return OPCODE_BLTI; - case 3: - return OPCODE_BGEI; - } - break; - case 3: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return OPCODE_ENTRY; - case 1: - switch (Field_r_Slot_inst_get (insn)) - { - case 8: - return OPCODE_LOOP; - case 9: - return OPCODE_LOOPNEZ; - case 10: - return OPCODE_LOOPGTZ; - } - break; - case 2: - return OPCODE_BLTUI; - case 3: - return OPCODE_BGEUI; - } - break; - } - break; - case 7: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BNONE; - case 1: - return OPCODE_BEQ; - case 2: - return OPCODE_BLT; - case 3: - return OPCODE_BLTU; - case 4: - return OPCODE_BALL; - case 5: - return OPCODE_BBC; - case 6: - case 7: - return OPCODE_BBCI; - case 8: - return OPCODE_BANY; - case 9: - return OPCODE_BNE; - case 10: - return OPCODE_BGE; - case 11: - return OPCODE_BGEU; - case 12: - return OPCODE_BNALL; - case 13: - return OPCODE_BBS; - case 14: - case 15: - return OPCODE_BBSI; - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16b_get (insn)) - { - case 12: - switch (Field_i_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_MOVI_N; - case 1: - switch (Field_z_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_BEQZ_N; - case 1: - return OPCODE_BNEZ_N; - } - break; - } - break; - case 13: - switch (Field_r_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_MOV_N; - case 15: - switch (Field_t_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_RET_N; - case 1: - return OPCODE_RETW_N; - case 2: - return OPCODE_BREAK_N; - case 3: - if (Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - break; - case 6: - if (Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - break; - } - break; - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16a_get (insn)) - { - case 8: - return OPCODE_L32I_N; - case 9: - return OPCODE_S32I_N; - case 10: - return OPCODE_ADD_N; - case 11: - return OPCODE_ADDI_N; - } - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc) - return 2; /* x16b */ - return -1; -} - -static int length_table[16] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int op0 = insn[0] & 0xf; - return length_table[op0]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 3 /* insn_size */, 0, - 3, formats, format_decoder, length_decoder, - 3, slots, - 56 /* num_fields */, - 93, operands, - 326, iclasses, - 452, opcodes, 0, - 2, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 1, interfaces, 0, - 0, funcUnits, 0 -}; diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c index a061158f6e..50c995ba79 100644 --- a/target/xtensa/core-de212.c +++ b/target/xtensa/core-de212.c @@ -34,13 +34,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_de212 -#include "core-de212/xtensa-modules.inc.c" +#include "core-de212/xtensa-modules.c.inc" static XtensaConfig de212 __attribute__((unused)) = { .name = "de212", .gdb_regmap = { .reg = { -#include "core-de212/gdb-config.inc.c" +#include "core-de212/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-de212/gdb-config.c.inc b/target/xtensa/core-de212/gdb-config.c.inc new file mode 100644 index 0000000000..25510fc34c --- /dev/null +++ b/target/xtensa/core-de212/gdb-config.c.inc @@ -0,0 +1,198 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) + XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) + XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask0,0,0,0) + XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask1,0,0,0) + XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask2,0,0,0) + XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask3,0,0,0) + XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask4,0,0,0) + XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask5,0,0,0) + XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask6,0,0,0) + XTREG_END diff --git a/target/xtensa/core-de212/gdb-config.inc.c b/target/xtensa/core-de212/gdb-config.inc.c deleted file mode 100644 index 25510fc34c..0000000000 --- a/target/xtensa/core-de212/gdb-config.inc.c +++ /dev/null @@ -1,198 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) - XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) - XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) - XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) - XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) - XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) - XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) - XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) - XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) - XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) - XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) - XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) - XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) - XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) - XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) - XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) - XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) - XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) - XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) - XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) - XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) - XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) - XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) - XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) - XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) - XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) - XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) - XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) - XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) - XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) - XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) - XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) - XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) - XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) - XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) - XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl, - "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat, - "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat, - "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus, - "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend, - "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid, - "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr, - "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset, - "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr, - "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) - XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask0,0,0,0) - XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask1,0,0,0) - XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask2,0,0,0) - XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask3,0,0,0) - XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask4,0,0,0) - XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask5,0,0,0) - XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc, - 0,0,&xtensa_mask6,0,0,0) - XTREG_END diff --git a/target/xtensa/core-de212/xtensa-modules.c.inc b/target/xtensa/core-de212/xtensa-modules.c.inc new file mode 100644 index 0000000000..480c68d3c6 --- /dev/null +++ b/target/xtensa/core-de212/xtensa-modules.c.inc @@ -0,0 +1,14543 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "qemu/osdep.h" +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 64 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 230 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EPS6", 13, 0 }, + { "EPS7", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 64 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3 +}; + + +/* Functional units. */ + +#define funcUnits 0 + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = uimmrx4_in_0 << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + return (*valp >= 4); +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_immt, + OPERAND_imms, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'o' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + + + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MUL_AA_LL, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_HH, + OPCODE_UMUL_AA_LL, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_HH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_HH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DD_LL, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_HH, + OPCODE_MULA_AA_LL, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_HH, + OPCODE_MULS_AA_LL, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_HH, + OPCODE_MULA_AD_LL, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_HH, + OPCODE_MULS_AD_LL, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_HH, + OPCODE_MULA_DA_LL, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_HH, + OPCODE_MULS_DA_LL, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_HH, + OPCODE_MULA_DD_LL, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_HH, + OPCODE_MULS_DD_LL, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_HH, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_DPFL, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_XSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_XSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_XSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_RSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_RSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_RSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_WSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_WSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_WSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 56 /* num_fields */, + 94, operands, + 313, iclasses, + 439, opcodes, 0, + 2, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-de212/xtensa-modules.inc.c b/target/xtensa/core-de212/xtensa-modules.inc.c deleted file mode 100644 index 480c68d3c6..0000000000 --- a/target/xtensa/core-de212/xtensa-modules.inc.c +++ /dev/null @@ -1,14543 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "qemu/osdep.h" -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "EXPSTATE", 230, 1 } -}; - -#define NUM_SYSREGS 64 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 230 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "ERI_RAW_INTERLOCK", 1, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } -}; - -#define NUM_STATES 64 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_MISC0, - STATE_MISC1, - STATE_ACC, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_ERI_RAW_INTERLOCK, - STATE_EXPSTATE -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_r3, - FIELD_rbit2, - FIELD_rhi, - FIELD_t3, - FIELD_tbit2, - FIELD_tlo, - FIELD_w, - FIELD_y, - FIELD_x, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__mr0, - FIELD__mr1, - FIELD__mr2, - FIELD__mr3 -}; - - -/* Functional units. */ - -#define funcUnits 0 - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_MR -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "MR", "m", REGFILE_MR, 32, 4 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "ERI_RD_Out", 14, 0, 0, 'o' }, - { "ERI_RD_In", 32, 0, 1, 'i' }, - { "ERI_RD_Rdy", 1, 0, 0, 'i' }, - { "ERI_WR_Out", 46, 0, 2, 'o' }, - { "ERI_WR_In", 1, 0, 3, 'i' }, - { "IMPWIRE", 32, 0, 4, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_ERI_RD_Out, - INTERFACE_ERI_RD_In, - INTERFACE_ERI_RD_Rdy, - INTERFACE_ERI_WR_Out, - INTERFACE_ERI_WR_In, - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_MR_0_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -OperandSem_opnd_sem_MR_0_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) -{ - unsigned uimmrx4_out_0; - unsigned uimmrx4_in_0; - uimmrx4_in_0 = *valp & 0xf; - uimmrx4_out_0 = uimmrx4_in_0 << 2; - *valp = uimmrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) -{ - unsigned uimmrx4_in_0; - unsigned uimmrx4_out_0; - uimmrx4_out_0 = *valp; - uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); - *valp = uimmrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_out_0; - unsigned ulabel8_in_0; - ulabel8_in_0 = *valp & 0xff; - ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); - *valp = ulabel8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) -{ - unsigned ulabel8_in_0; - unsigned ulabel8_out_0; - ulabel8_out_0 = *valp; - ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; - *valp = ulabel8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_1_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_2_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_3_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_4_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_5_encode (uint32 *valp) -{ - return (*valp >= 4); -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_out_0; - unsigned xt_wbr18_label_in_0; - xt_wbr18_label_in_0 = *valp & 0x3ffff; - xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); - *valp = xt_wbr18_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_label_in_0; - unsigned xt_wbr18_label_out_0; - xt_wbr18_label_out_0 = *valp; - xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bitindex_decode (uint32 *valp) -{ - unsigned bitindex_out_0; - unsigned bitindex_in_0; - bitindex_in_0 = *valp & 0x1f; - bitindex_out_0 = (0 << 5) | bitindex_in_0; - *valp = bitindex_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bitindex_encode (uint32 *valp) -{ - unsigned bitindex_in_0; - unsigned bitindex_out_0; - bitindex_out_0 = *valp; - bitindex_in_0 = (bitindex_out_0 & 0x1f); - *valp = bitindex_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "mx", FIELD_x, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, - 0, 0 }, - { "my", FIELD_y, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, - 0, 0 }, - { "mw", FIELD_w, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, - 0, 0 }, - { "mr0", FIELD__mr0, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, - 0, 0 }, - { "mr1", FIELD__mr1, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, - 0, 0 }, - { "mr2", FIELD__mr2, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, - 0, 0 }, - { "mr3", FIELD__mr3, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "bitindex", FIELD_bitindex, -1, 0, - 0, - OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, - { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, - { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, - { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_mx, - OPERAND_my, - OPERAND_mw, - OPERAND_mr0, - OPERAND_mr1, - OPERAND_mr2, - OPERAND_mr3, - OPERAND_immt, - OPERAND_imms, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_bitindex, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_r3, - OPERAND_rbit2, - OPERAND_rhi, - OPERAND_t3, - OPERAND_tbit2, - OPERAND_tlo, - OPERAND_w, - OPERAND_y, - OPERAND_x, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimmrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { - { { STATE_ERI_RAW_INTERLOCK }, 'i' } -}; - -static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { - INTERFACE_ERI_RD_In, - INTERFACE_ERI_RD_Out -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { - { { STATE_ERI_RAW_INTERLOCK }, 'o' } -}; - -static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { - INTERFACE_ERI_WR_In, - INTERFACE_ERI_WR_Out -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32nb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_lddr32_p_args, - 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sddr32_p_args, - 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_dcache_dyn_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, - { 2, Iclass_xt_iclass_wer_args, - 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, - { 1, Iclass_rur_expstate_args, - 1, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 1, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s32nb, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_memctl, - ICLASS_xt_iclass_wsr_memctl, - ICLASS_xt_iclass_xsr_memctl, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_mac16_aa, - ICLASS_xt_iclass_mac16_ad, - ICLASS_xt_iclass_mac16_da, - ICLASS_xt_iclass_mac16_dd, - ICLASS_xt_iclass_mac16a_aa, - ICLASS_xt_iclass_mac16a_ad, - ICLASS_xt_iclass_mac16a_da, - ICLASS_xt_iclass_mac16a_dd, - ICLASS_xt_iclass_mac16al_da, - ICLASS_xt_iclass_mac16al_dd, - ICLASS_xt_iclass_mac16_l, - ICLASS_xt_iclass_rsr_m0, - ICLASS_xt_iclass_wsr_m0, - ICLASS_xt_iclass_xsr_m0, - ICLASS_xt_iclass_rsr_m1, - ICLASS_xt_iclass_wsr_m1, - ICLASS_xt_iclass_xsr_m1, - ICLASS_xt_iclass_rsr_m2, - ICLASS_xt_iclass_wsr_m2, - ICLASS_xt_iclass_xsr_m2, - ICLASS_xt_iclass_rsr_m3, - ICLASS_xt_iclass_wsr_m3, - ICLASS_xt_iclass_xsr_m3, - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_lddr32_p, - ICLASS_xt_iclass_sddr32_p, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_dyn, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590000; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36100; -} - -static void -Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136100; -} - -static void -Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616100; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x740004; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x750004; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x760004; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x770004; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x710004; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720004; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730004; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x340004; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x350004; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x360004; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370004; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640004; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650004; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660004; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670004; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240004; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250004; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260004; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270004; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x790004; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7a0004; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b0004; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7c0004; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d0004; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e0004; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f0004; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390004; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0004; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b0004; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0004; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d0004; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e0004; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f0004; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690004; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0004; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0004; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0004; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0004; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0004; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0004; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x290004; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a0004; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b0004; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0004; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0004; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0004; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0004; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590004; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490004; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a0004; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4a0004; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b0004; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b0004; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190004; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90004; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0004; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0004; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0004; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0004; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900004; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800004; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32000; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132000; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612000; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32100; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132100; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612100; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32200; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132200; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612200; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32300; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x132300; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x612300; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31000; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131000; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611000; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31100; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131100; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x611100; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e0; -} - -static void -Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f0; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70d2; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270d2; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x370d2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf7082; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7082; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x27082; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37082; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { - Opcode_s32nb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { - Opcode_rsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { - Opcode_wsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { - Opcode_xsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { - Opcode_lddr32_p_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { - Opcode_sddr32_p_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { - Opcode_diwbui_p_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 -}; - - - - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s32nb", ICLASS_xt_iclass_s32nb, - 0, - Opcode_s32nb_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, - 0, - Opcode_rsr_memctl_encode_fns, 0, 0 }, - { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, - 0, - Opcode_wsr_memctl_encode_fns, 0, 0 }, - { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, - 0, - Opcode_xsr_memctl_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "rsr.m0", ICLASS_xt_iclass_rsr_m0, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", ICLASS_xt_iclass_wsr_m0, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", ICLASS_xt_iclass_xsr_m0, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", ICLASS_xt_iclass_rsr_m1, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", ICLASS_xt_iclass_wsr_m1, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", ICLASS_xt_iclass_xsr_m1, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", ICLASS_xt_iclass_rsr_m2, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", ICLASS_xt_iclass_wsr_m2, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", ICLASS_xt_iclass_xsr_m2, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", ICLASS_xt_iclass_rsr_m3, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", ICLASS_xt_iclass_wsr_m3, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", ICLASS_xt_iclass_xsr_m3, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "lddr32.p", ICLASS_xt_iclass_lddr32_p, - 0, - Opcode_lddr32_p_encode_fns, 0, 0 }, - { "sddr32.p", ICLASS_xt_iclass_sddr32_p, - 0, - Opcode_sddr32_p_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, - 0, - Opcode_diwbui_p_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S32NB, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_MEMCTL, - OPCODE_WSR_MEMCTL, - OPCODE_XSR_MEMCTL, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_MUL_AA_LL, - OPCODE_MUL_AA_HL, - OPCODE_MUL_AA_LH, - OPCODE_MUL_AA_HH, - OPCODE_UMUL_AA_LL, - OPCODE_UMUL_AA_HL, - OPCODE_UMUL_AA_LH, - OPCODE_UMUL_AA_HH, - OPCODE_MUL_AD_LL, - OPCODE_MUL_AD_HL, - OPCODE_MUL_AD_LH, - OPCODE_MUL_AD_HH, - OPCODE_MUL_DA_LL, - OPCODE_MUL_DA_HL, - OPCODE_MUL_DA_LH, - OPCODE_MUL_DA_HH, - OPCODE_MUL_DD_LL, - OPCODE_MUL_DD_HL, - OPCODE_MUL_DD_LH, - OPCODE_MUL_DD_HH, - OPCODE_MULA_AA_LL, - OPCODE_MULA_AA_HL, - OPCODE_MULA_AA_LH, - OPCODE_MULA_AA_HH, - OPCODE_MULS_AA_LL, - OPCODE_MULS_AA_HL, - OPCODE_MULS_AA_LH, - OPCODE_MULS_AA_HH, - OPCODE_MULA_AD_LL, - OPCODE_MULA_AD_HL, - OPCODE_MULA_AD_LH, - OPCODE_MULA_AD_HH, - OPCODE_MULS_AD_LL, - OPCODE_MULS_AD_HL, - OPCODE_MULS_AD_LH, - OPCODE_MULS_AD_HH, - OPCODE_MULA_DA_LL, - OPCODE_MULA_DA_HL, - OPCODE_MULA_DA_LH, - OPCODE_MULA_DA_HH, - OPCODE_MULS_DA_LL, - OPCODE_MULS_DA_HL, - OPCODE_MULS_DA_LH, - OPCODE_MULS_DA_HH, - OPCODE_MULA_DD_LL, - OPCODE_MULA_DD_HL, - OPCODE_MULA_DD_LH, - OPCODE_MULA_DD_HH, - OPCODE_MULS_DD_LL, - OPCODE_MULS_DD_HL, - OPCODE_MULS_DD_LH, - OPCODE_MULS_DD_HH, - OPCODE_MULA_DA_LL_LDDEC, - OPCODE_MULA_DA_LL_LDINC, - OPCODE_MULA_DA_HL_LDDEC, - OPCODE_MULA_DA_HL_LDINC, - OPCODE_MULA_DA_LH_LDDEC, - OPCODE_MULA_DA_LH_LDINC, - OPCODE_MULA_DA_HH_LDDEC, - OPCODE_MULA_DA_HH_LDINC, - OPCODE_MULA_DD_LL_LDDEC, - OPCODE_MULA_DD_LL_LDINC, - OPCODE_MULA_DD_HL_LDDEC, - OPCODE_MULA_DD_HL_LDINC, - OPCODE_MULA_DD_LH_LDDEC, - OPCODE_MULA_DD_LH_LDINC, - OPCODE_MULA_DD_HH_LDDEC, - OPCODE_MULA_DD_HH_LDINC, - OPCODE_LDDEC, - OPCODE_LDINC, - OPCODE_RSR_M0, - OPCODE_WSR_M0, - OPCODE_XSR_M0, - OPCODE_RSR_M1, - OPCODE_WSR_M1, - OPCODE_XSR_M1, - OPCODE_RSR_M2, - OPCODE_WSR_M2, - OPCODE_XSR_M2, - OPCODE_RSR_M3, - OPCODE_WSR_M3, - OPCODE_XSR_M3, - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_LDDR32_P, - OPCODE_SDDR32_P, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWBUI_P, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_LDDR32_P; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_SDDR32_P; - } - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_XSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_XSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_XSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_XSR_M3; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_XSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_QUOU; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_QUOS; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_REMU; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_REMS; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_RSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_RSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_RSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_RSR_M3; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_RSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_WSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_WSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_WSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_WSR_M3; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 89) - return OPCODE_WSR_MMID; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_WSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 230) - return OPCODE_RUR_EXPSTATE; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WUR_EXPSTATE; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_S32NB; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_DIWBUI_P; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 2) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 3) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 7) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 9) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDDEC; - } - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc) - return 2; /* x16b */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 3 /* insn_size */, 0, - 3, formats, format_decoder, length_decoder, - 3, slots, - 56 /* num_fields */, - 94, operands, - 313, iclasses, - 439, opcodes, 0, - 2, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 6, interfaces, 0, - 0, funcUnits, 0 -}; diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c index 1221a296fa..3327c50b4f 100644 --- a/target/xtensa/core-fsf.c +++ b/target/xtensa/core-fsf.c @@ -34,7 +34,7 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_fsf -#include "core-fsf/xtensa-modules.inc.c" +#include "core-fsf/xtensa-modules.c.inc" static XtensaConfig fsf __attribute__((unused)) = { .name = "fsf", diff --git a/target/xtensa/core-fsf/xtensa-modules.c.inc b/target/xtensa/core-fsf/xtensa-modules.c.inc new file mode 100644 index 0000000000..c32683ff77 --- /dev/null +++ b/target/xtensa/core-fsf/xtensa-modules.c.inc @@ -0,0 +1,9826 @@ +/* Xtensa configuration-specific ISA information. + Copyright 2003, 2004, 2005 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "qemu/osdep.h" +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "PTEVADDR", 83, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 } +}; + +#define NUM_SYSREGS 49 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 0 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 17, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 17, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 } +}; + +#define NUM_STATES 58 + +/* Macros for xtensa_state numbers (for use in iclasses because the + state numbers are not available when the iclass table is generated). */ + +#define STATE_LCOUNT 0 +#define STATE_PC 1 +#define STATE_ICOUNT 2 +#define STATE_DDR 3 +#define STATE_INTERRUPT 4 +#define STATE_CCOUNT 5 +#define STATE_XTSYNC 6 +#define STATE_EPC1 7 +#define STATE_EPC2 8 +#define STATE_EPC3 9 +#define STATE_EPC4 10 +#define STATE_EXCSAVE1 11 +#define STATE_EXCSAVE2 12 +#define STATE_EXCSAVE3 13 +#define STATE_EXCSAVE4 14 +#define STATE_EPS2 15 +#define STATE_EPS3 16 +#define STATE_EPS4 17 +#define STATE_EXCCAUSE 18 +#define STATE_PSINTLEVEL 19 +#define STATE_PSUM 20 +#define STATE_PSWOE 21 +#define STATE_PSRING 22 +#define STATE_PSEXCM 23 +#define STATE_DEPC 24 +#define STATE_EXCVADDR 25 +#define STATE_WindowBase 26 +#define STATE_WindowStart 27 +#define STATE_PSCALLINC 28 +#define STATE_PSOWB 29 +#define STATE_LBEG 30 +#define STATE_LEND 31 +#define STATE_SAR 32 +#define STATE_LITBADDR 33 +#define STATE_LITBEN 34 +#define STATE_MISC0 35 +#define STATE_MISC1 36 +#define STATE_InOCDMode 37 +#define STATE_INTENABLE 38 +#define STATE_DBREAKA0 39 +#define STATE_DBREAKC0 40 +#define STATE_DBREAKA1 41 +#define STATE_DBREAKC1 42 +#define STATE_IBREAKA0 43 +#define STATE_IBREAKA1 44 +#define STATE_IBREAKENABLE 45 +#define STATE_ICOUNTLEVEL 46 +#define STATE_DEBUGCAUSE 47 +#define STATE_DBNUM 48 +#define STATE_CCOMPARE0 49 +#define STATE_CCOMPARE1 50 +#define STATE_CCOMPARE2 51 +#define STATE_ASID3 52 +#define STATE_ASID2 53 +#define STATE_ASID1 54 +#define STATE_INSTPGSZID4 55 +#define STATE_DATAPGSZID4 56 +#define STATE_PTBASE 57 + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", 0, 32, 64 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + return (*valp & ~0xf) != 0; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + return (*valp & ~0x3f) != 0; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + return (*valp & ~0x3f) != 0; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + return (*valp & ~0x3f) != 0; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + return (*valp & ~0x3f) != 0; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + return (*valp & ~0x3f) != 0; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", 3, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", 26, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", 14, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", 0, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", 35, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", 36, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", 37, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", 38, 0, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", 5, 0, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", 14, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", 14, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", 34, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", 33, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", 0, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", 14, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", 14, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", 4, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", 4, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", 4, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", 13, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", 4, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", 4, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", 6, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", 18, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", 13, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", 4, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", 3, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", 10, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", 7, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "immt", 0, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", 5, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, + { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, + { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, + { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, + { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, + { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, + { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, + { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 10 /* ar12 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 9 /* ar8 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 8 /* ar4 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { 11 /* ars_entry */ }, 's' }, + { { 4 /* ars */ }, 'i' }, + { { 1 /* uimm12x8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { 2 /* simm4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 12 /* immrx4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 16 /* ai4const */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 15 /* uimm6 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { 4 /* ars */ }, 'o' }, + { { 14 /* simm7 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 13 /* lsi4x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 23 /* simm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 24 /* simm8x256 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 17 /* b4const */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 37 /* bbi */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 18 /* b4constu */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' }, + { { 28 /* label8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 30 /* label12 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { 0 /* soffsetx4 */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 7 /* ar0 */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 52 /* sae */ }, 'i' }, + { { 27 /* op2p1 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { 31 /* soffset */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { 6 /* art */ }, 'o' }, + { { 32 /* uimm16x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 29 /* ulabel8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { 6 /* art */ }, 'o' }, + { { 25 /* simm12b */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { 3 /* arr */ }, 'm' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { 5 /* *ars_invisible */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 20 /* uimm8x2 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' }, + { { 19 /* uimm8 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { 56 /* sas */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 4 /* ars */ }, 'i' }, + { { 26 /* msalp32 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 54 /* sargt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { 3 /* arr */ }, 'o' }, + { { 6 /* art */ }, 'i' }, + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { 6 /* art */ }, 'o' }, + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { 40 /* s */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { 34 /* imms */ }, 'i' }, + { { 33 /* immt */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { 34 /* imms */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 22 /* uimm4x16 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { 4 /* ars */ }, 'i' }, + { { 21 /* uimm8x4 */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { 6 /* art */ }, 'i' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { 6 /* art */ }, 'o' }, + { { 4 /* ars */ }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdo */, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 } +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80200; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10f; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4830; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4831; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4816; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4930; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4931; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4916; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc00; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60f; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30f; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00f; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200c00; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d00; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700600; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700e00; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700100; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700900; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700a00; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700200; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700b00; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700300; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700800; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700400; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700c00; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700500; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700d00; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200100; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200900; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200200; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0800; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0900; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0a00; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200a00; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1006; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200500; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200600; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200400; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x304; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x331; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x316; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x531; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x516; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb030; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd030; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe630; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe631; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe616; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb130; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb131; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb116; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd130; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd131; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd116; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb230; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb231; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb216; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd230; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd231; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd216; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb330; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb331; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb316; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd330; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd331; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd316; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb430; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb431; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb416; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd430; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd431; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd416; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc230; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc231; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc216; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc330; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc331; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc316; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc430; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc431; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc416; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee30; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee31; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee16; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc030; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc031; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc016; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe830; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe831; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe816; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf430; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf431; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf416; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf530; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf531; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf516; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb30; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe230; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe231; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe331; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe430; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe431; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe416; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20f; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9030; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9031; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9016; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa031; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa016; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9130; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9131; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9116; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa130; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa131; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa116; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8031; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8016; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8131; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8116; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6030; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6031; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6016; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe930; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe931; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe916; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec30; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec31; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec16; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed30; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed31; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed16; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6830; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6831; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1f; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e1f; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea30; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea31; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea16; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf030; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf031; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf016; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf130; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf131; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf116; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf230; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf231; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf216; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0700; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0700; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0700; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31f; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240700; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250700; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280740; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280750; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260700; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270700; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200700; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210700; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220700; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230700; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91f; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5331; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5330; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5316; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a30; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a31; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a16; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b30; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b31; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b16; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c30; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c31; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c16; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc05; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd05; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb05; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf05; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe05; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x405; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x705; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x605; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe04; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf04; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", 0 /* xt_iclass_excw */, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", 1 /* xt_iclass_rfe */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", 2 /* xt_iclass_rfde */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", 3 /* xt_iclass_syscall */, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", 4 /* xt_iclass_simcall */, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", 5 /* xt_iclass_call12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", 6 /* xt_iclass_call8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", 7 /* xt_iclass_call4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", 8 /* xt_iclass_callx12 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", 9 /* xt_iclass_callx8 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", 10 /* xt_iclass_callx4 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", 11 /* xt_iclass_entry */, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", 12 /* xt_iclass_movsp */, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", 13 /* xt_iclass_rotw */, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", 14 /* xt_iclass_retw */, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", 15 /* xt_iclass_rfwou */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", 16 /* xt_iclass_l32e */, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", 17 /* xt_iclass_s32e */, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", 24 /* xt_iclass_add.n */, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", 25 /* xt_iclass_addi.n */, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", 26 /* xt_iclass_bz6 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", 27 /* xt_iclass_ill.n */, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", 28 /* xt_iclass_loadi4 */, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", 29 /* xt_iclass_mov.n */, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", 30 /* xt_iclass_movi.n */, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", 31 /* xt_iclass_nopn */, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", 32 /* xt_iclass_retn */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", 33 /* xt_iclass_storei4 */, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "addi", 34 /* xt_iclass_addi */, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", 35 /* xt_iclass_addmi */, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", 36 /* xt_iclass_addsub */, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", 36 /* xt_iclass_addsub */, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", 36 /* xt_iclass_addsub */, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", 36 /* xt_iclass_addsub */, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", 37 /* xt_iclass_bit */, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", 37 /* xt_iclass_bit */, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", 37 /* xt_iclass_bit */, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", 38 /* xt_iclass_bsi8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", 39 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", 39 /* xt_iclass_bsi8b */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", 40 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", 40 /* xt_iclass_bsi8u */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", 41 /* xt_iclass_bst8 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", 42 /* xt_iclass_bsz12 */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", 43 /* xt_iclass_call0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", 44 /* xt_iclass_callx0 */, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", 45 /* xt_iclass_exti */, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", 46 /* xt_iclass_ill */, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", 47 /* xt_iclass_jump */, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", 48 /* xt_iclass_jumpx */, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", 49 /* xt_iclass_l16ui */, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", 50 /* xt_iclass_l16si */, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", 51 /* xt_iclass_l32i */, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", 52 /* xt_iclass_l32r */, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", 53 /* xt_iclass_l8i */, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", 54 /* xt_iclass_loop */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", 55 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", 55 /* xt_iclass_loopz */, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", 56 /* xt_iclass_movi */, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", 57 /* xt_iclass_movz */, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", 57 /* xt_iclass_movz */, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", 57 /* xt_iclass_movz */, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", 57 /* xt_iclass_movz */, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", 58 /* xt_iclass_neg */, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", 58 /* xt_iclass_neg */, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", 59 /* xt_iclass_nop */, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", 60 /* xt_iclass_return */, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", 61 /* xt_iclass_s16i */, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", 62 /* xt_iclass_s32i */, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", 63 /* xt_iclass_s8i */, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", 64 /* xt_iclass_sar */, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", 64 /* xt_iclass_sar */, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", 64 /* xt_iclass_sar */, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", 64 /* xt_iclass_sar */, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", 65 /* xt_iclass_sari */, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", 66 /* xt_iclass_shifts */, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", 67 /* xt_iclass_shiftst */, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", 68 /* xt_iclass_shiftt */, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", 68 /* xt_iclass_shiftt */, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", 69 /* xt_iclass_slli */, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", 70 /* xt_iclass_srai */, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", 71 /* xt_iclass_srli */, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", 72 /* xt_iclass_memw */, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", 73 /* xt_iclass_extw */, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", 74 /* xt_iclass_isync */, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", 75 /* xt_iclass_sync */, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", 75 /* xt_iclass_sync */, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", 75 /* xt_iclass_sync */, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", 76 /* xt_iclass_rsil */, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", 77 /* xt_iclass_rsr.lend */, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", 78 /* xt_iclass_wsr.lend */, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", 79 /* xt_iclass_xsr.lend */, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", 86 /* xt_iclass_rsr.sar */, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", 87 /* xt_iclass_wsr.sar */, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", 88 /* xt_iclass_xsr.sar */, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", 92 /* xt_iclass_rsr.176 */, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "rsr.208", 93 /* xt_iclass_rsr.208 */, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", 94 /* xt_iclass_rsr.ps */, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", 95 /* xt_iclass_wsr.ps */, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", 96 /* xt_iclass_xsr.ps */, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", 133 /* xt_iclass_rsr.depc */, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", 134 /* xt_iclass_wsr.depc */, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", 135 /* xt_iclass_xsr.depc */, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", 145 /* xt_iclass_rsr.prid */, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rfi", 146 /* xt_iclass_rfi */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", 147 /* xt_iclass_wait */, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", 149 /* xt_iclass_wsr.intset */, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", 154 /* xt_iclass_break */, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", 155 /* xt_iclass_break.n */, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", 180 /* xt_iclass_rsr.icount */, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", 181 /* xt_iclass_wsr.icount */, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", 182 /* xt_iclass_xsr.icount */, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", 189 /* xt_iclass_rfdo */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", 190 /* xt_iclass_rfdd */, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", 203 /* xt_iclass_icache */, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", 203 /* xt_iclass_icache */, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "iii", 204 /* xt_iclass_icache_inv */, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", 205 /* xt_iclass_licx */, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", 205 /* xt_iclass_licx */, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", 206 /* xt_iclass_sicx */, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", 206 /* xt_iclass_sicx */, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", 207 /* xt_iclass_dcache */, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", 207 /* xt_iclass_dcache */, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", 208 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", 208 /* xt_iclass_dcache_ind */, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", 209 /* xt_iclass_dcache_inv */, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", 209 /* xt_iclass_dcache_inv */, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", 210 /* xt_iclass_dpf */, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "sdct", 211 /* xt_iclass_sdct */, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", 212 /* xt_iclass_ldct */, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", 225 /* xt_iclass_idtlb */, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", 226 /* xt_iclass_rdtlb */, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", 227 /* xt_iclass_wdtlb */, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", 228 /* xt_iclass_iitlb */, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", 229 /* xt_iclass_ritlb */, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", 229 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", 229 /* xt_iclass_ritlb */, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", 230 /* xt_iclass_witlb */, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", 231 /* xt_iclass_ldpte */, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", 232 /* xt_iclass_hwwitlba */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "nsa", 234 /* xt_iclass_nsa */, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", 234 /* xt_iclass_nsa */, + 0, + Opcode_nsau_encode_fns, 0, 0 } +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 77; /* ill */ + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 96; /* ret */ + case 1: + return 14; /* retw */ + case 2: + return 79; /* jx */ + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 75; /* callx0 */ + case 1: + return 10; /* callx4 */ + case 2: + return 9; /* callx8 */ + case 3: + return 8; /* callx12 */ + } + break; + } + break; + case 1: + return 12; /* movsp */ + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 114; /* isync */ + case 1: + return 115; /* rsync */ + case 2: + return 116; /* esync */ + case 3: + return 117; /* dsync */ + case 8: + return 0; /* excw */ + case 12: + return 112; /* memw */ + case 13: + return 113; /* extw */ + case 15: + return 95; /* nop */ + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 1; /* rfe */ + case 2: + return 2; /* rfde */ + case 4: + return 16; /* rfwo */ + case 5: + return 17; /* rfwu */ + } + break; + case 1: + return 188; /* rfi */ + } + break; + case 4: + return 196; /* break */ + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 3; /* syscall */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 4; /* simcall */ + break; + } + break; + case 6: + return 118; /* rsil */ + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return 189; /* waiti */ + break; + } + break; + case 1: + return 47; /* and */ + case 2: + return 48; /* or */ + case 3: + return 49; /* xor */ + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return 100; /* ssr */ + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return 101; /* ssl */ + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return 102; /* ssa8l */ + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return 103; /* ssa8b */ + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return 104; /* ssai */ + break; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return 13; /* rotw */ + break; + case 14: + return 289; /* nsa */ + case 15: + return 290; /* nsau */ + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 1: + return 287; /* hwwitlba */ + case 3: + return 283; /* ritlb0 */ + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return 281; /* iitlb */ + break; + case 5: + return 282; /* pitlb */ + case 6: + return 285; /* witlb */ + case 7: + return 284; /* ritlb1 */ + case 9: + return 288; /* hwwdtlba */ + case 11: + return 278; /* rdtlb0 */ + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return 276; /* idtlb */ + break; + case 13: + return 277; /* pdtlb */ + case 14: + return 280; /* wdtlb */ + case 15: + return 279; /* rdtlb1 */ + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return 93; /* neg */ + case 1: + return 94; /* abs */ + } + break; + case 8: + return 39; /* add */ + case 9: + return 41; /* addx2 */ + case 10: + return 42; /* addx4 */ + case 11: + return 43; /* addx8 */ + case 12: + return 40; /* sub */ + case 13: + return 44; /* subx2 */ + case 14: + return 45; /* subx4 */ + case 15: + return 46; /* subx8 */ + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return 109; /* slli */ + case 2: + case 3: + return 110; /* srai */ + case 4: + return 111; /* srli */ + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 127; /* xsr.lbeg */ + case 1: + return 121; /* xsr.lend */ + case 2: + return 124; /* xsr.lcount */ + case 3: + return 130; /* xsr.sar */ + case 5: + return 133; /* xsr.litbase */ + case 72: + return 22; /* xsr.windowbase */ + case 73: + return 25; /* xsr.windowstart */ + case 83: + return 266; /* xsr.ptevaddr */ + case 90: + return 269; /* xsr.rasid */ + case 91: + return 272; /* xsr.itlbcfg */ + case 92: + return 275; /* xsr.dtlbcfg */ + case 96: + return 218; /* xsr.ibreakenable */ + case 104: + return 230; /* xsr.ddr */ + case 128: + return 212; /* xsr.ibreaka0 */ + case 129: + return 215; /* xsr.ibreaka1 */ + case 144: + return 200; /* xsr.dbreaka0 */ + case 145: + return 206; /* xsr.dbreaka1 */ + case 160: + return 203; /* xsr.dbreakc0 */ + case 161: + return 209; /* xsr.dbreakc1 */ + case 177: + return 141; /* xsr.epc1 */ + case 178: + return 147; /* xsr.epc2 */ + case 179: + return 153; /* xsr.epc3 */ + case 180: + return 159; /* xsr.epc4 */ + case 192: + return 177; /* xsr.depc */ + case 194: + return 165; /* xsr.eps2 */ + case 195: + return 168; /* xsr.eps3 */ + case 196: + return 171; /* xsr.eps4 */ + case 209: + return 144; /* xsr.excsave1 */ + case 210: + return 150; /* xsr.excsave2 */ + case 211: + return 156; /* xsr.excsave3 */ + case 212: + return 162; /* xsr.excsave4 */ + case 228: + return 195; /* xsr.intenable */ + case 230: + return 138; /* xsr.ps */ + case 232: + return 180; /* xsr.exccause */ + case 233: + return 221; /* xsr.debugcause */ + case 234: + return 235; /* xsr.ccount */ + case 236: + return 224; /* xsr.icount */ + case 237: + return 227; /* xsr.icountlevel */ + case 238: + return 174; /* xsr.excvaddr */ + case 240: + return 238; /* xsr.ccompare0 */ + case 241: + return 241; /* xsr.ccompare1 */ + case 242: + return 244; /* xsr.ccompare2 */ + case 244: + return 183; /* xsr.misc0 */ + case 245: + return 186; /* xsr.misc1 */ + } + break; + case 8: + return 106; /* src */ + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return 107; /* srl */ + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return 105; /* sll */ + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return 108; /* sra */ + break; + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 248; /* lict */ + case 1: + return 250; /* sict */ + case 2: + return 249; /* licw */ + case 3: + return 251; /* sicw */ + case 8: + return 263; /* ldct */ + case 9: + return 262; /* sdct */ + case 14: + if (Field_t_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0) + return 231; /* rfdo */ + if (Field_t_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0) + return 232; /* rfdd */ + break; + case 15: + return 286; /* ldpte */ + } + break; + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 125; /* rsr.lbeg */ + case 1: + return 119; /* rsr.lend */ + case 2: + return 122; /* rsr.lcount */ + case 3: + return 128; /* rsr.sar */ + case 5: + return 131; /* rsr.litbase */ + case 72: + return 20; /* rsr.windowbase */ + case 73: + return 23; /* rsr.windowstart */ + case 83: + return 265; /* rsr.ptevaddr */ + case 90: + return 267; /* rsr.rasid */ + case 91: + return 270; /* rsr.itlbcfg */ + case 92: + return 273; /* rsr.dtlbcfg */ + case 96: + return 216; /* rsr.ibreakenable */ + case 104: + return 228; /* rsr.ddr */ + case 128: + return 210; /* rsr.ibreaka0 */ + case 129: + return 213; /* rsr.ibreaka1 */ + case 144: + return 198; /* rsr.dbreaka0 */ + case 145: + return 204; /* rsr.dbreaka1 */ + case 160: + return 201; /* rsr.dbreakc0 */ + case 161: + return 207; /* rsr.dbreakc1 */ + case 176: + return 134; /* rsr.176 */ + case 177: + return 139; /* rsr.epc1 */ + case 178: + return 145; /* rsr.epc2 */ + case 179: + return 151; /* rsr.epc3 */ + case 180: + return 157; /* rsr.epc4 */ + case 192: + return 175; /* rsr.depc */ + case 194: + return 163; /* rsr.eps2 */ + case 195: + return 166; /* rsr.eps3 */ + case 196: + return 169; /* rsr.eps4 */ + case 208: + return 135; /* rsr.208 */ + case 209: + return 142; /* rsr.excsave1 */ + case 210: + return 148; /* rsr.excsave2 */ + case 211: + return 154; /* rsr.excsave3 */ + case 212: + return 160; /* rsr.excsave4 */ + case 226: + return 190; /* rsr.interrupt */ + case 228: + return 193; /* rsr.intenable */ + case 230: + return 136; /* rsr.ps */ + case 232: + return 178; /* rsr.exccause */ + case 233: + return 219; /* rsr.debugcause */ + case 234: + return 233; /* rsr.ccount */ + case 235: + return 187; /* rsr.prid */ + case 236: + return 222; /* rsr.icount */ + case 237: + return 225; /* rsr.icountlevel */ + case 238: + return 172; /* rsr.excvaddr */ + case 240: + return 236; /* rsr.ccompare0 */ + case 241: + return 239; /* rsr.ccompare1 */ + case 242: + return 242; /* rsr.ccompare2 */ + case 244: + return 181; /* rsr.misc0 */ + case 245: + return 184; /* rsr.misc1 */ + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return 126; /* wsr.lbeg */ + case 1: + return 120; /* wsr.lend */ + case 2: + return 123; /* wsr.lcount */ + case 3: + return 129; /* wsr.sar */ + case 5: + return 132; /* wsr.litbase */ + case 72: + return 21; /* wsr.windowbase */ + case 73: + return 24; /* wsr.windowstart */ + case 83: + return 264; /* wsr.ptevaddr */ + case 90: + return 268; /* wsr.rasid */ + case 91: + return 271; /* wsr.itlbcfg */ + case 92: + return 274; /* wsr.dtlbcfg */ + case 96: + return 217; /* wsr.ibreakenable */ + case 104: + return 229; /* wsr.ddr */ + case 128: + return 211; /* wsr.ibreaka0 */ + case 129: + return 214; /* wsr.ibreaka1 */ + case 144: + return 199; /* wsr.dbreaka0 */ + case 145: + return 205; /* wsr.dbreaka1 */ + case 160: + return 202; /* wsr.dbreakc0 */ + case 161: + return 208; /* wsr.dbreakc1 */ + case 177: + return 140; /* wsr.epc1 */ + case 178: + return 146; /* wsr.epc2 */ + case 179: + return 152; /* wsr.epc3 */ + case 180: + return 158; /* wsr.epc4 */ + case 192: + return 176; /* wsr.depc */ + case 194: + return 164; /* wsr.eps2 */ + case 195: + return 167; /* wsr.eps3 */ + case 196: + return 170; /* wsr.eps4 */ + case 209: + return 143; /* wsr.excsave1 */ + case 210: + return 149; /* wsr.excsave2 */ + case 211: + return 155; /* wsr.excsave3 */ + case 212: + return 161; /* wsr.excsave4 */ + case 226: + return 191; /* wsr.intset */ + case 227: + return 192; /* wsr.intclear */ + case 228: + return 194; /* wsr.intenable */ + case 230: + return 137; /* wsr.ps */ + case 232: + return 179; /* wsr.exccause */ + case 233: + return 220; /* wsr.debugcause */ + case 234: + return 234; /* wsr.ccount */ + case 236: + return 223; /* wsr.icount */ + case 237: + return 226; /* wsr.icountlevel */ + case 238: + return 173; /* wsr.excvaddr */ + case 240: + return 237; /* wsr.ccompare0 */ + case 241: + return 240; /* wsr.ccompare1 */ + case 242: + return 243; /* wsr.ccompare2 */ + case 244: + return 182; /* wsr.misc0 */ + case 245: + return 185; /* wsr.misc1 */ + } + break; + case 8: + return 89; /* moveqz */ + case 9: + return 90; /* movnez */ + case 10: + return 91; /* movltz */ + case 11: + return 92; /* movgez */ + } + break; + case 4: + case 5: + return 76; /* extui */ + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return 18; /* l32e */ + case 4: + return 19; /* s32e */ + } + break; + } + break; + case 1: + return 83; /* l32r */ + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 84; /* l8ui */ + case 1: + return 80; /* l16ui */ + case 2: + return 82; /* l32i */ + case 4: + return 99; /* s8i */ + case 5: + return 97; /* s16i */ + case 6: + return 98; /* s32i */ + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return 258; /* dpfr */ + case 1: + return 259; /* dpfw */ + case 2: + return 260; /* dpfro */ + case 3: + return 261; /* dpfwo */ + case 4: + return 252; /* dhwb */ + case 5: + return 253; /* dhwbi */ + case 6: + return 256; /* dhi */ + case 7: + return 257; /* dii */ + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 4: + return 254; /* diwb */ + case 5: + return 255; /* diwbi */ + } + break; + case 12: + return 245; /* ipf */ + case 14: + return 246; /* ihi */ + case 15: + return 247; /* iii */ + } + break; + case 9: + return 81; /* l16si */ + case 10: + return 88; /* movi */ + case 12: + return 37; /* addi */ + case 13: + return 38; /* addmi */ + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 74; /* call0 */ + case 1: + return 7; /* call4 */ + case 2: + return 6; /* call8 */ + case 3: + return 5; /* call12 */ + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return 78; /* j */ + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 70; /* beqz */ + case 1: + return 71; /* bnez */ + case 2: + return 73; /* bltz */ + case 3: + return 72; /* bgez */ + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 50; /* beqi */ + case 1: + return 51; /* bnei */ + case 2: + return 53; /* blti */ + case 3: + return 52; /* bgei */ + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return 11; /* entry */ + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 8: + return 85; /* loop */ + case 9: + return 86; /* loopnez */ + case 10: + return 87; /* loopgtz */ + } + break; + case 2: + return 57; /* bltui */ + case 3: + return 56; /* bgeui */ + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return 65; /* bnone */ + case 1: + return 58; /* beq */ + case 2: + return 61; /* blt */ + case 3: + return 63; /* bltu */ + case 4: + return 66; /* ball */ + case 5: + return 68; /* bbc */ + case 6: + case 7: + return 54; /* bbci */ + case 8: + return 64; /* bany */ + case 9: + return 59; /* bne */ + case 10: + return 60; /* bge */ + case 11: + return 62; /* bgeu */ + case 12: + return 67; /* bnall */ + case 13: + return 69; /* bbs */ + case 14: + case 15: + return 55; /* bbsi */ + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return 33; /* movi.n */ + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return 28; /* beqz.n */ + case 1: + return 29; /* bnez.n */ + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return 32; /* mov.n */ + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return 35; /* ret.n */ + case 1: + return 15; /* retw.n */ + case 2: + return 197; /* break.n */ + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 34; /* nop.n */ + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return 31; /* l32i.n */ + case 9: + return 36; /* s32i.n */ + case 10: + return 26; /* add.n */ + case 11: + return 27; /* addi.n */ + } + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = ((insn[0] & 0xffff00) >> 8); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x800000; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc00000; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x800000) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc00000) == 0x800000) + return 1; /* x16a */ + if ((insn[0] & 0xe00000) == 0xc00000) + return 2; /* x16b */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = (insn[0] >> 4) & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 1 /* big-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 39 /* num_fields */, + 70, operands, + 235, iclasses, + 291, opcodes, 0, + 1, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 0, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-fsf/xtensa-modules.inc.c b/target/xtensa/core-fsf/xtensa-modules.inc.c deleted file mode 100644 index c32683ff77..0000000000 --- a/target/xtensa/core-fsf/xtensa-modules.inc.c +++ /dev/null @@ -1,9826 +0,0 @@ -/* Xtensa configuration-specific ISA information. - Copyright 2003, 2004, 2005 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#include "qemu/osdep.h" -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "PTEVADDR", 83, 0 }, - { "DDR", 104, 0 }, - { "176", 176, 0 }, - { "208", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "LITBASE", 5, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 } -}; - -#define NUM_SYSREGS 49 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 0 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 17, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EPS2", 15, 0 }, - { "EPS3", 15, 0 }, - { "EPS4", 15, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 4, 0 }, - { "WindowStart", 16, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "LITBADDR", 20, 0 }, - { "LITBEN", 1, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 17, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 } -}; - -#define NUM_STATES 58 - -/* Macros for xtensa_state numbers (for use in iclasses because the - state numbers are not available when the iclass table is generated). */ - -#define STATE_LCOUNT 0 -#define STATE_PC 1 -#define STATE_ICOUNT 2 -#define STATE_DDR 3 -#define STATE_INTERRUPT 4 -#define STATE_CCOUNT 5 -#define STATE_XTSYNC 6 -#define STATE_EPC1 7 -#define STATE_EPC2 8 -#define STATE_EPC3 9 -#define STATE_EPC4 10 -#define STATE_EXCSAVE1 11 -#define STATE_EXCSAVE2 12 -#define STATE_EXCSAVE3 13 -#define STATE_EXCSAVE4 14 -#define STATE_EPS2 15 -#define STATE_EPS3 16 -#define STATE_EPS4 17 -#define STATE_EXCCAUSE 18 -#define STATE_PSINTLEVEL 19 -#define STATE_PSUM 20 -#define STATE_PSWOE 21 -#define STATE_PSRING 22 -#define STATE_PSEXCM 23 -#define STATE_DEPC 24 -#define STATE_EXCVADDR 25 -#define STATE_WindowBase 26 -#define STATE_WindowStart 27 -#define STATE_PSCALLINC 28 -#define STATE_PSOWB 29 -#define STATE_LBEG 30 -#define STATE_LEND 31 -#define STATE_SAR 32 -#define STATE_LITBADDR 33 -#define STATE_LITBEN 34 -#define STATE_MISC0 35 -#define STATE_MISC1 36 -#define STATE_InOCDMode 37 -#define STATE_INTENABLE 38 -#define STATE_DBREAKA0 39 -#define STATE_DBREAKC0 40 -#define STATE_DBREAKA1 41 -#define STATE_DBREAKC1 42 -#define STATE_IBREAKA0 43 -#define STATE_IBREAKA1 44 -#define STATE_IBREAKENABLE 45 -#define STATE_ICOUNTLEVEL 46 -#define STATE_DEBUGCAUSE 47 -#define STATE_DBNUM 48 -#define STATE_CCOMPARE0 49 -#define STATE_CCOMPARE1 50 -#define STATE_CCOMPARE2 51 -#define STATE_ASID3 52 -#define STATE_ASID2 53 -#define STATE_ASID1 54 -#define STATE_INSTPGSZID4 55 -#define STATE_DATAPGSZID4 56 -#define STATE_PTBASE 57 - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - -}; - - -/* Register files. */ - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", 0, 32, 64 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0, soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_0, imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; - return 0; -} - -static int -Operand_uimm12x8_encode (uint32 *valp) -{ - unsigned imm12_0, uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; - return 0; -} - -static int -Operand_simm4_decode (uint32 *valp) -{ - unsigned simm4_0, mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; - return 0; -} - -static int -Operand_simm4_encode (uint32 *valp) -{ - unsigned mn_0, simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; - return 0; -} - -static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_arr_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_art_encode (uint32 *valp) -{ - return (*valp & ~0xf) != 0; -} - -static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar0_encode (uint32 *valp) -{ - return (*valp & ~0x3f) != 0; -} - -static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar4_encode (uint32 *valp) -{ - return (*valp & ~0x3f) != 0; -} - -static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar8_encode (uint32 *valp) -{ - return (*valp & ~0x3f) != 0; -} - -static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ar12_encode (uint32 *valp) -{ - return (*valp & ~0x3f) != 0; -} - -static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -Operand_ars_entry_encode (uint32 *valp) -{ - return (*valp & ~0x3f) != 0; -} - -static int -Operand_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_0, r_0; - r_0 = *valp & 0xf; - immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; - *valp = immrx4_0; - return 0; -} - -static int -Operand_immrx4_encode (uint32 *valp) -{ - unsigned r_0, immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_0, r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; - return 0; -} - -static int -Operand_lsi4x4_encode (uint32 *valp) -{ - unsigned r_0, lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; - return 0; -} - -static int -Operand_simm7_decode (uint32 *valp) -{ - unsigned simm7_0, imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; - return 0; -} - -static int -Operand_simm7_encode (uint32 *valp) -{ - unsigned imm7_0, simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; - return 0; -} - -static int -Operand_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_0, imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); - *valp = uimm6_0; - return 0; -} - -static int -Operand_uimm6_encode (uint32 *valp) -{ - unsigned imm6_0, uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0, t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0, ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) - { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; - } - *valp = t_0; - return 0; -} - -static int -Operand_b4const_decode (uint32 *valp) -{ - unsigned b4const_0, r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; - return 0; -} - -static int -Operand_b4const_encode (uint32 *valp) -{ - unsigned r_0, b4const_0; - b4const_0 = *valp; - switch (b4const_0) - { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_0, r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; - return 0; -} - -static int -Operand_b4constu_encode (uint32 *valp) -{ - unsigned r_0, b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) - { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; - } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; - return 0; -} - -static int -Operand_uimm8x2_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; - return 0; -} - -static int -Operand_uimm8x4_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_0, op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; - return 0; -} - -static int -Operand_uimm4x16_encode (uint32 *valp) -{ - unsigned op2_0, uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; - return 0; -} - -static int -Operand_simm8_decode (uint32 *valp) -{ - unsigned simm8_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; - return 0; -} - -static int -Operand_simm8_encode (uint32 *valp) -{ - unsigned imm8_0, simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; - return 0; -} - -static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0, simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0, imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0, simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0, sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0, msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0, op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0, op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0, imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0, label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_0, imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); - *valp = ulabel8_0; - return 0; -} - -static int -Operand_ulabel8_encode (uint32 *valp) -{ - unsigned imm8_0, ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_decode (uint32 *valp) -{ - unsigned label12_0, imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; - return 0; -} - -static int -Operand_label12_encode (uint32 *valp) -{ - unsigned imm12_0, label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_decode (uint32 *valp) -{ - unsigned soffset_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; - return 0; -} - -static int -Operand_soffset_encode (uint32 *valp) -{ - unsigned offset_0, soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_0, imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; - return 0; -} - -static int -Operand_uimm16x4_encode (uint32 *valp) -{ - unsigned imm16_0, uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_immt_decode (uint32 *valp) -{ - unsigned immt_0, t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; - return 0; -} - -static int -Operand_immt_encode (uint32 *valp) -{ - unsigned t_0, immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; - return 0; -} - -static int -Operand_imms_decode (uint32 *valp) -{ - unsigned imms_0, s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; - return 0; -} - -static int -Operand_imms_encode (uint32 *valp) -{ - unsigned s_0, imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", 3, -1, 0, - 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, - 0, 0 }, - { "simm4", 26, -1, 0, - 0, - Operand_simm4_encode, Operand_simm4_decode, - 0, 0 }, - { "arr", 14, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, - 0, 0 }, - { "ars", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "*ars_invisible", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, - 0, 0 }, - { "art", 0, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, - 0, 0 }, - { "ar0", 35, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, - 0, 0 }, - { "ar4", 36, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, - 0, 0 }, - { "ar8", 37, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, - 0, 0 }, - { "ar12", 38, 0, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, - 0, 0 }, - { "ars_entry", 5, 0, 1, - XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, - 0, 0 }, - { "immrx4", 14, -1, 0, - 0, - Operand_immrx4_encode, Operand_immrx4_decode, - 0, 0 }, - { "lsi4x4", 14, -1, 0, - 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, - 0, 0 }, - { "simm7", 34, -1, 0, - 0, - Operand_simm7_encode, Operand_simm7_decode, - 0, 0 }, - { "uimm6", 33, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", 0, -1, 0, - 0, - Operand_ai4const_encode, Operand_ai4const_decode, - 0, 0 }, - { "b4const", 14, -1, 0, - 0, - Operand_b4const_encode, Operand_b4const_decode, - 0, 0 }, - { "b4constu", 14, -1, 0, - 0, - Operand_b4constu_encode, Operand_b4constu_decode, - 0, 0 }, - { "uimm8", 4, -1, 0, - 0, - Operand_uimm8_encode, Operand_uimm8_decode, - 0, 0 }, - { "uimm8x2", 4, -1, 0, - 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", 4, -1, 0, - 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", 13, -1, 0, - 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, - 0, 0 }, - { "simm8", 4, -1, 0, - 0, - Operand_simm8_encode, Operand_simm8_decode, - 0, 0 }, - { "simm8x256", 4, -1, 0, - 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, - 0, 0 }, - { "simm12b", 6, -1, 0, - 0, - Operand_simm12b_encode, Operand_simm12b_decode, - 0, 0 }, - { "msalp32", 18, -1, 0, - 0, - Operand_msalp32_encode, Operand_msalp32_decode, - 0, 0 }, - { "op2p1", 13, -1, 0, - 0, - Operand_op2p1_encode, Operand_op2p1_decode, - 0, 0 }, - { "label8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", 4, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", 3, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", 10, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", 7, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "immt", 0, -1, 0, - 0, - Operand_immt_encode, Operand_immt_decode, - 0, 0 }, - { "imms", 5, -1, 0, - 0, - Operand_imms_encode, Operand_imms_decode, - 0, 0 }, - { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, - { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, - { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, - { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, - { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, - { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, - { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, - { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 10 /* ar12 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 9 /* ar8 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 8 /* ar4 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { 11 /* ars_entry */ }, 's' }, - { { 4 /* ars */ }, 'i' }, - { { 1 /* uimm12x8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { 2 /* simm4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 12 /* immrx4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 16 /* ai4const */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 15 /* uimm6 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { 4 /* ars */ }, 'o' }, - { { 14 /* simm7 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 13 /* lsi4x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 23 /* simm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 24 /* simm8x256 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 17 /* b4const */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 37 /* bbi */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 18 /* b4constu */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' }, - { { 28 /* label8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 30 /* label12 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { 0 /* soffsetx4 */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 7 /* ar0 */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 52 /* sae */ }, 'i' }, - { { 27 /* op2p1 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { 31 /* soffset */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { 6 /* art */ }, 'o' }, - { { 32 /* uimm16x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 29 /* ulabel8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { 6 /* art */ }, 'o' }, - { { 25 /* simm12b */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { 3 /* arr */ }, 'm' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { 5 /* *ars_invisible */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 20 /* uimm8x2 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' }, - { { 19 /* uimm8 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { 56 /* sas */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 4 /* ars */ }, 'i' }, - { { 26 /* msalp32 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 54 /* sargt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { 3 /* arr */ }, 'o' }, - { { 6 /* art */ }, 'i' }, - { { 40 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { 6 /* art */ }, 'o' }, - { { 40 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'o' }, - { { STATE_LITBEN }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'm' }, - { { STATE_LITBEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { 40 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { 40 /* s */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { 34 /* imms */ }, 'i' }, - { { 33 /* immt */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { 34 /* imms */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 22 /* uimm4x16 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { 4 /* ars */ }, 'i' }, - { { 21 /* uimm8x4 */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { 6 /* art */ }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { 6 /* art */ }, 'i' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { 6 /* art */ }, 'o' }, - { { 4 /* ars */ }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_176_args, - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_208_args, - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdo */, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 } -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80200; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2300; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1500; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c0000; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580000; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x540000; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0000; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0000; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70000; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0000; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x804; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10f; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4300; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5300; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x94; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4830; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4831; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4816; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4930; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4931; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4916; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc800; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc00; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd60f; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd000; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc000; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30f; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00f; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200c00; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200d00; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690000; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0000; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0000; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700600; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700e00; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0000; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0000; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700100; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700900; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700a00; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700200; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700b00; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700300; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700800; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700400; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700c00; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700500; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700d00; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200100; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200900; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200200; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0800; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0900; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0a00; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200a00; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1006; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0200; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200500; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200600; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200400; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x304; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x12; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0200; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0200; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20200; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x116; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x231; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x216; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x331; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x316; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x531; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x516; -} - -static void -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb030; -} - -static void -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd030; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe630; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe631; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe616; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb130; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb131; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb116; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd130; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd131; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd116; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb230; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb231; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb216; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd230; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd231; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd216; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb330; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb331; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb316; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd330; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd331; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd316; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb430; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb431; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb416; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd430; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd431; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd416; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc230; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc231; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc216; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc330; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc331; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc316; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc430; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc431; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc416; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee30; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee31; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee16; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc030; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc031; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc016; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe830; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe831; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe816; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf430; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf431; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf416; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf530; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf531; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf516; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xeb30; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10300; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe230; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe231; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe331; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe430; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe431; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe416; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20f; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9030; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9031; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9016; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa030; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa031; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa016; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9130; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9131; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9116; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa130; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa131; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa116; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8030; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8031; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8016; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8130; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8131; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8116; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6030; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6031; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6016; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe930; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe931; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe916; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec30; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec31; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec16; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed30; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed31; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed16; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6830; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6831; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6816; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1f; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10e1f; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea30; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea31; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea16; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf030; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf031; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf016; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf130; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf131; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf116; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf230; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf231; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf216; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0700; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0700; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0700; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x21f; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x11f; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31f; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240700; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250700; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280740; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280750; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260700; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270700; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200700; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210700; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220700; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230700; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x91f; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81f; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5331; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5330; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5316; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a30; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a31; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a16; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b30; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b31; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b16; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c30; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c31; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c16; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc05; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd05; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb05; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf05; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe05; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x405; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x305; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x705; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x605; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x105; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x905; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe04; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf04; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { - Opcode_rsr_176_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { - Opcode_rsr_208_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0 -}; - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", 0 /* xt_iclass_excw */, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", 1 /* xt_iclass_rfe */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", 2 /* xt_iclass_rfde */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", 3 /* xt_iclass_syscall */, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "simcall", 4 /* xt_iclass_simcall */, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "call12", 5 /* xt_iclass_call12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", 6 /* xt_iclass_call8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", 7 /* xt_iclass_call4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", 8 /* xt_iclass_callx12 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", 9 /* xt_iclass_callx8 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", 10 /* xt_iclass_callx4 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", 11 /* xt_iclass_entry */, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", 12 /* xt_iclass_movsp */, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", 13 /* xt_iclass_rotw */, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", 14 /* xt_iclass_retw */, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", 15 /* xt_iclass_rfwou */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", 16 /* xt_iclass_l32e */, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", 17 /* xt_iclass_s32e */, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", 24 /* xt_iclass_add.n */, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", 25 /* xt_iclass_addi.n */, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", 26 /* xt_iclass_bz6 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", 27 /* xt_iclass_ill.n */, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", 28 /* xt_iclass_loadi4 */, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", 29 /* xt_iclass_mov.n */, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", 30 /* xt_iclass_movi.n */, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", 31 /* xt_iclass_nopn */, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", 32 /* xt_iclass_retn */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", 33 /* xt_iclass_storei4 */, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "addi", 34 /* xt_iclass_addi */, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", 35 /* xt_iclass_addmi */, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", 36 /* xt_iclass_addsub */, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", 36 /* xt_iclass_addsub */, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", 36 /* xt_iclass_addsub */, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", 36 /* xt_iclass_addsub */, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", 36 /* xt_iclass_addsub */, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", 36 /* xt_iclass_addsub */, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", 36 /* xt_iclass_addsub */, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", 36 /* xt_iclass_addsub */, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", 37 /* xt_iclass_bit */, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", 37 /* xt_iclass_bit */, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", 37 /* xt_iclass_bit */, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", 38 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", 38 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", 38 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", 38 /* xt_iclass_bsi8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", 39 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", 39 /* xt_iclass_bsi8b */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", 40 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", 40 /* xt_iclass_bsi8u */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", 41 /* xt_iclass_bst8 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", 42 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", 42 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", 42 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", 42 /* xt_iclass_bsz12 */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", 43 /* xt_iclass_call0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", 44 /* xt_iclass_callx0 */, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", 45 /* xt_iclass_exti */, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", 46 /* xt_iclass_ill */, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", 47 /* xt_iclass_jump */, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", 48 /* xt_iclass_jumpx */, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", 49 /* xt_iclass_l16ui */, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", 50 /* xt_iclass_l16si */, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", 51 /* xt_iclass_l32i */, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", 52 /* xt_iclass_l32r */, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", 53 /* xt_iclass_l8i */, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", 54 /* xt_iclass_loop */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", 55 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", 55 /* xt_iclass_loopz */, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", 56 /* xt_iclass_movi */, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", 57 /* xt_iclass_movz */, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", 57 /* xt_iclass_movz */, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", 57 /* xt_iclass_movz */, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", 57 /* xt_iclass_movz */, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", 58 /* xt_iclass_neg */, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", 58 /* xt_iclass_neg */, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", 59 /* xt_iclass_nop */, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", 60 /* xt_iclass_return */, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "s16i", 61 /* xt_iclass_s16i */, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", 62 /* xt_iclass_s32i */, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", 63 /* xt_iclass_s8i */, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", 64 /* xt_iclass_sar */, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", 64 /* xt_iclass_sar */, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", 64 /* xt_iclass_sar */, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", 64 /* xt_iclass_sar */, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", 65 /* xt_iclass_sari */, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", 66 /* xt_iclass_shifts */, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", 67 /* xt_iclass_shiftst */, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", 68 /* xt_iclass_shiftt */, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", 68 /* xt_iclass_shiftt */, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", 69 /* xt_iclass_slli */, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", 70 /* xt_iclass_srai */, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", 71 /* xt_iclass_srli */, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", 72 /* xt_iclass_memw */, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", 73 /* xt_iclass_extw */, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", 74 /* xt_iclass_isync */, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", 75 /* xt_iclass_sync */, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", 75 /* xt_iclass_sync */, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", 75 /* xt_iclass_sync */, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", 76 /* xt_iclass_rsil */, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", 77 /* xt_iclass_rsr.lend */, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", 78 /* xt_iclass_wsr.lend */, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", 79 /* xt_iclass_xsr.lend */, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", 86 /* xt_iclass_rsr.sar */, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", 87 /* xt_iclass_wsr.sar */, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", 88 /* xt_iclass_xsr.sar */, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.176", 92 /* xt_iclass_rsr.176 */, - 0, - Opcode_rsr_176_encode_fns, 0, 0 }, - { "rsr.208", 93 /* xt_iclass_rsr.208 */, - 0, - Opcode_rsr_208_encode_fns, 0, 0 }, - { "rsr.ps", 94 /* xt_iclass_rsr.ps */, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", 95 /* xt_iclass_wsr.ps */, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", 96 /* xt_iclass_xsr.ps */, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", 133 /* xt_iclass_rsr.depc */, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", 134 /* xt_iclass_wsr.depc */, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", 135 /* xt_iclass_xsr.depc */, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", 145 /* xt_iclass_rsr.prid */, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rfi", 146 /* xt_iclass_rfi */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", 147 /* xt_iclass_wait */, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", 149 /* xt_iclass_wsr.intset */, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", 154 /* xt_iclass_break */, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", 155 /* xt_iclass_break.n */, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", 180 /* xt_iclass_rsr.icount */, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", 181 /* xt_iclass_wsr.icount */, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", 182 /* xt_iclass_xsr.icount */, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", 189 /* xt_iclass_rfdo */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", 190 /* xt_iclass_rfdd */, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", 203 /* xt_iclass_icache */, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", 203 /* xt_iclass_icache */, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "iii", 204 /* xt_iclass_icache_inv */, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", 205 /* xt_iclass_licx */, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", 205 /* xt_iclass_licx */, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", 206 /* xt_iclass_sicx */, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", 206 /* xt_iclass_sicx */, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", 207 /* xt_iclass_dcache */, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", 207 /* xt_iclass_dcache */, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", 208 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", 208 /* xt_iclass_dcache_ind */, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", 209 /* xt_iclass_dcache_inv */, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", 209 /* xt_iclass_dcache_inv */, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", 210 /* xt_iclass_dpf */, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", 210 /* xt_iclass_dpf */, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", 210 /* xt_iclass_dpf */, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", 210 /* xt_iclass_dpf */, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "sdct", 211 /* xt_iclass_sdct */, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", 212 /* xt_iclass_ldct */, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", 225 /* xt_iclass_idtlb */, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", 226 /* xt_iclass_rdtlb */, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", 226 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", 226 /* xt_iclass_rdtlb */, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", 227 /* xt_iclass_wdtlb */, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", 228 /* xt_iclass_iitlb */, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", 229 /* xt_iclass_ritlb */, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", 229 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", 229 /* xt_iclass_ritlb */, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", 230 /* xt_iclass_witlb */, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", 231 /* xt_iclass_ldpte */, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", 232 /* xt_iclass_hwwitlba */, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "nsa", 234 /* xt_iclass_nsa */, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", 234 /* xt_iclass_nsa */, - 0, - Opcode_nsau_encode_fns, 0, 0 } -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst_get (insn)) - { - case 0: - switch (Field_op1_Slot_inst_get (insn)) - { - case 0: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return 77; /* ill */ - break; - case 2: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 96; /* ret */ - case 1: - return 14; /* retw */ - case 2: - return 79; /* jx */ - } - break; - case 3: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 75; /* callx0 */ - case 1: - return 10; /* callx4 */ - case 2: - return 9; /* callx8 */ - case 3: - return 8; /* callx12 */ - } - break; - } - break; - case 1: - return 12; /* movsp */ - case 2: - if (Field_s_Slot_inst_get (insn) == 0) - { - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 114; /* isync */ - case 1: - return 115; /* rsync */ - case 2: - return 116; /* esync */ - case 3: - return 117; /* dsync */ - case 8: - return 0; /* excw */ - case 12: - return 112; /* memw */ - case 13: - return 113; /* extw */ - case 15: - return 95; /* nop */ - } - } - break; - case 3: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 1; /* rfe */ - case 2: - return 2; /* rfde */ - case 4: - return 16; /* rfwo */ - case 5: - return 17; /* rfwu */ - } - break; - case 1: - return 188; /* rfi */ - } - break; - case 4: - return 196; /* break */ - case 5: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 3; /* syscall */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 4; /* simcall */ - break; - } - break; - case 6: - return 118; /* rsil */ - case 7: - if (Field_t_Slot_inst_get (insn) == 0) - return 189; /* waiti */ - break; - } - break; - case 1: - return 47; /* and */ - case 2: - return 48; /* or */ - case 3: - return 49; /* xor */ - case 4: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return 100; /* ssr */ - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return 101; /* ssl */ - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 0) - return 102; /* ssa8l */ - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 0) - return 103; /* ssa8b */ - break; - case 4: - if (Field_thi3_Slot_inst_get (insn) == 0) - return 104; /* ssai */ - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0) - return 13; /* rotw */ - break; - case 14: - return 289; /* nsa */ - case 15: - return 290; /* nsau */ - } - break; - case 5: - switch (Field_r_Slot_inst_get (insn)) - { - case 1: - return 287; /* hwwitlba */ - case 3: - return 283; /* ritlb0 */ - case 4: - if (Field_t_Slot_inst_get (insn) == 0) - return 281; /* iitlb */ - break; - case 5: - return 282; /* pitlb */ - case 6: - return 285; /* witlb */ - case 7: - return 284; /* ritlb1 */ - case 9: - return 288; /* hwwdtlba */ - case 11: - return 278; /* rdtlb0 */ - case 12: - if (Field_t_Slot_inst_get (insn) == 0) - return 276; /* idtlb */ - break; - case 13: - return 277; /* pdtlb */ - case 14: - return 280; /* wdtlb */ - case 15: - return 279; /* rdtlb1 */ - } - break; - case 6: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return 93; /* neg */ - case 1: - return 94; /* abs */ - } - break; - case 8: - return 39; /* add */ - case 9: - return 41; /* addx2 */ - case 10: - return 42; /* addx4 */ - case 11: - return 43; /* addx8 */ - case 12: - return 40; /* sub */ - case 13: - return 44; /* subx2 */ - case 14: - return 45; /* subx4 */ - case 15: - return 46; /* subx8 */ - } - break; - case 1: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - case 1: - return 109; /* slli */ - case 2: - case 3: - return 110; /* srai */ - case 4: - return 111; /* srli */ - case 6: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 127; /* xsr.lbeg */ - case 1: - return 121; /* xsr.lend */ - case 2: - return 124; /* xsr.lcount */ - case 3: - return 130; /* xsr.sar */ - case 5: - return 133; /* xsr.litbase */ - case 72: - return 22; /* xsr.windowbase */ - case 73: - return 25; /* xsr.windowstart */ - case 83: - return 266; /* xsr.ptevaddr */ - case 90: - return 269; /* xsr.rasid */ - case 91: - return 272; /* xsr.itlbcfg */ - case 92: - return 275; /* xsr.dtlbcfg */ - case 96: - return 218; /* xsr.ibreakenable */ - case 104: - return 230; /* xsr.ddr */ - case 128: - return 212; /* xsr.ibreaka0 */ - case 129: - return 215; /* xsr.ibreaka1 */ - case 144: - return 200; /* xsr.dbreaka0 */ - case 145: - return 206; /* xsr.dbreaka1 */ - case 160: - return 203; /* xsr.dbreakc0 */ - case 161: - return 209; /* xsr.dbreakc1 */ - case 177: - return 141; /* xsr.epc1 */ - case 178: - return 147; /* xsr.epc2 */ - case 179: - return 153; /* xsr.epc3 */ - case 180: - return 159; /* xsr.epc4 */ - case 192: - return 177; /* xsr.depc */ - case 194: - return 165; /* xsr.eps2 */ - case 195: - return 168; /* xsr.eps3 */ - case 196: - return 171; /* xsr.eps4 */ - case 209: - return 144; /* xsr.excsave1 */ - case 210: - return 150; /* xsr.excsave2 */ - case 211: - return 156; /* xsr.excsave3 */ - case 212: - return 162; /* xsr.excsave4 */ - case 228: - return 195; /* xsr.intenable */ - case 230: - return 138; /* xsr.ps */ - case 232: - return 180; /* xsr.exccause */ - case 233: - return 221; /* xsr.debugcause */ - case 234: - return 235; /* xsr.ccount */ - case 236: - return 224; /* xsr.icount */ - case 237: - return 227; /* xsr.icountlevel */ - case 238: - return 174; /* xsr.excvaddr */ - case 240: - return 238; /* xsr.ccompare0 */ - case 241: - return 241; /* xsr.ccompare1 */ - case 242: - return 244; /* xsr.ccompare2 */ - case 244: - return 183; /* xsr.misc0 */ - case 245: - return 186; /* xsr.misc1 */ - } - break; - case 8: - return 106; /* src */ - case 9: - if (Field_s_Slot_inst_get (insn) == 0) - return 107; /* srl */ - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0) - return 105; /* sll */ - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0) - return 108; /* sra */ - break; - case 15: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 248; /* lict */ - case 1: - return 250; /* sict */ - case 2: - return 249; /* licw */ - case 3: - return 251; /* sicw */ - case 8: - return 263; /* ldct */ - case 9: - return 262; /* sdct */ - case 14: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0) - return 231; /* rfdo */ - if (Field_t_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0) - return 232; /* rfdd */ - break; - case 15: - return 286; /* ldpte */ - } - break; - } - break; - case 3: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 125; /* rsr.lbeg */ - case 1: - return 119; /* rsr.lend */ - case 2: - return 122; /* rsr.lcount */ - case 3: - return 128; /* rsr.sar */ - case 5: - return 131; /* rsr.litbase */ - case 72: - return 20; /* rsr.windowbase */ - case 73: - return 23; /* rsr.windowstart */ - case 83: - return 265; /* rsr.ptevaddr */ - case 90: - return 267; /* rsr.rasid */ - case 91: - return 270; /* rsr.itlbcfg */ - case 92: - return 273; /* rsr.dtlbcfg */ - case 96: - return 216; /* rsr.ibreakenable */ - case 104: - return 228; /* rsr.ddr */ - case 128: - return 210; /* rsr.ibreaka0 */ - case 129: - return 213; /* rsr.ibreaka1 */ - case 144: - return 198; /* rsr.dbreaka0 */ - case 145: - return 204; /* rsr.dbreaka1 */ - case 160: - return 201; /* rsr.dbreakc0 */ - case 161: - return 207; /* rsr.dbreakc1 */ - case 176: - return 134; /* rsr.176 */ - case 177: - return 139; /* rsr.epc1 */ - case 178: - return 145; /* rsr.epc2 */ - case 179: - return 151; /* rsr.epc3 */ - case 180: - return 157; /* rsr.epc4 */ - case 192: - return 175; /* rsr.depc */ - case 194: - return 163; /* rsr.eps2 */ - case 195: - return 166; /* rsr.eps3 */ - case 196: - return 169; /* rsr.eps4 */ - case 208: - return 135; /* rsr.208 */ - case 209: - return 142; /* rsr.excsave1 */ - case 210: - return 148; /* rsr.excsave2 */ - case 211: - return 154; /* rsr.excsave3 */ - case 212: - return 160; /* rsr.excsave4 */ - case 226: - return 190; /* rsr.interrupt */ - case 228: - return 193; /* rsr.intenable */ - case 230: - return 136; /* rsr.ps */ - case 232: - return 178; /* rsr.exccause */ - case 233: - return 219; /* rsr.debugcause */ - case 234: - return 233; /* rsr.ccount */ - case 235: - return 187; /* rsr.prid */ - case 236: - return 222; /* rsr.icount */ - case 237: - return 225; /* rsr.icountlevel */ - case 238: - return 172; /* rsr.excvaddr */ - case 240: - return 236; /* rsr.ccompare0 */ - case 241: - return 239; /* rsr.ccompare1 */ - case 242: - return 242; /* rsr.ccompare2 */ - case 244: - return 181; /* rsr.misc0 */ - case 245: - return 184; /* rsr.misc1 */ - } - break; - case 1: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return 126; /* wsr.lbeg */ - case 1: - return 120; /* wsr.lend */ - case 2: - return 123; /* wsr.lcount */ - case 3: - return 129; /* wsr.sar */ - case 5: - return 132; /* wsr.litbase */ - case 72: - return 21; /* wsr.windowbase */ - case 73: - return 24; /* wsr.windowstart */ - case 83: - return 264; /* wsr.ptevaddr */ - case 90: - return 268; /* wsr.rasid */ - case 91: - return 271; /* wsr.itlbcfg */ - case 92: - return 274; /* wsr.dtlbcfg */ - case 96: - return 217; /* wsr.ibreakenable */ - case 104: - return 229; /* wsr.ddr */ - case 128: - return 211; /* wsr.ibreaka0 */ - case 129: - return 214; /* wsr.ibreaka1 */ - case 144: - return 199; /* wsr.dbreaka0 */ - case 145: - return 205; /* wsr.dbreaka1 */ - case 160: - return 202; /* wsr.dbreakc0 */ - case 161: - return 208; /* wsr.dbreakc1 */ - case 177: - return 140; /* wsr.epc1 */ - case 178: - return 146; /* wsr.epc2 */ - case 179: - return 152; /* wsr.epc3 */ - case 180: - return 158; /* wsr.epc4 */ - case 192: - return 176; /* wsr.depc */ - case 194: - return 164; /* wsr.eps2 */ - case 195: - return 167; /* wsr.eps3 */ - case 196: - return 170; /* wsr.eps4 */ - case 209: - return 143; /* wsr.excsave1 */ - case 210: - return 149; /* wsr.excsave2 */ - case 211: - return 155; /* wsr.excsave3 */ - case 212: - return 161; /* wsr.excsave4 */ - case 226: - return 191; /* wsr.intset */ - case 227: - return 192; /* wsr.intclear */ - case 228: - return 194; /* wsr.intenable */ - case 230: - return 137; /* wsr.ps */ - case 232: - return 179; /* wsr.exccause */ - case 233: - return 220; /* wsr.debugcause */ - case 234: - return 234; /* wsr.ccount */ - case 236: - return 223; /* wsr.icount */ - case 237: - return 226; /* wsr.icountlevel */ - case 238: - return 173; /* wsr.excvaddr */ - case 240: - return 237; /* wsr.ccompare0 */ - case 241: - return 240; /* wsr.ccompare1 */ - case 242: - return 243; /* wsr.ccompare2 */ - case 244: - return 182; /* wsr.misc0 */ - case 245: - return 185; /* wsr.misc1 */ - } - break; - case 8: - return 89; /* moveqz */ - case 9: - return 90; /* movnez */ - case 10: - return 91; /* movltz */ - case 11: - return 92; /* movgez */ - } - break; - case 4: - case 5: - return 76; /* extui */ - case 9: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return 18; /* l32e */ - case 4: - return 19; /* s32e */ - } - break; - } - break; - case 1: - return 83; /* l32r */ - case 2: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 84; /* l8ui */ - case 1: - return 80; /* l16ui */ - case 2: - return 82; /* l32i */ - case 4: - return 99; /* s8i */ - case 5: - return 97; /* s16i */ - case 6: - return 98; /* s32i */ - case 7: - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return 258; /* dpfr */ - case 1: - return 259; /* dpfw */ - case 2: - return 260; /* dpfro */ - case 3: - return 261; /* dpfwo */ - case 4: - return 252; /* dhwb */ - case 5: - return 253; /* dhwbi */ - case 6: - return 256; /* dhi */ - case 7: - return 257; /* dii */ - case 8: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - return 254; /* diwb */ - case 5: - return 255; /* diwbi */ - } - break; - case 12: - return 245; /* ipf */ - case 14: - return 246; /* ihi */ - case 15: - return 247; /* iii */ - } - break; - case 9: - return 81; /* l16si */ - case 10: - return 88; /* movi */ - case 12: - return 37; /* addi */ - case 13: - return 38; /* addmi */ - } - break; - case 5: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 74; /* call0 */ - case 1: - return 7; /* call4 */ - case 2: - return 6; /* call8 */ - case 3: - return 5; /* call12 */ - } - break; - case 6: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return 78; /* j */ - case 1: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 70; /* beqz */ - case 1: - return 71; /* bnez */ - case 2: - return 73; /* bltz */ - case 3: - return 72; /* bgez */ - } - break; - case 2: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 50; /* beqi */ - case 1: - return 51; /* bnei */ - case 2: - return 53; /* blti */ - case 3: - return 52; /* bgei */ - } - break; - case 3: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return 11; /* entry */ - case 1: - switch (Field_r_Slot_inst_get (insn)) - { - case 8: - return 85; /* loop */ - case 9: - return 86; /* loopnez */ - case 10: - return 87; /* loopgtz */ - } - break; - case 2: - return 57; /* bltui */ - case 3: - return 56; /* bgeui */ - } - break; - } - break; - case 7: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return 65; /* bnone */ - case 1: - return 58; /* beq */ - case 2: - return 61; /* blt */ - case 3: - return 63; /* bltu */ - case 4: - return 66; /* ball */ - case 5: - return 68; /* bbc */ - case 6: - case 7: - return 54; /* bbci */ - case 8: - return 64; /* bany */ - case 9: - return 59; /* bne */ - case 10: - return 60; /* bge */ - case 11: - return 62; /* bgeu */ - case 12: - return 67; /* bnall */ - case 13: - return 69; /* bbs */ - case 14: - case 15: - return 55; /* bbsi */ - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16b_get (insn)) - { - case 12: - switch (Field_i_Slot_inst16b_get (insn)) - { - case 0: - return 33; /* movi.n */ - case 1: - switch (Field_z_Slot_inst16b_get (insn)) - { - case 0: - return 28; /* beqz.n */ - case 1: - return 29; /* bnez.n */ - } - break; - } - break; - case 13: - switch (Field_r_Slot_inst16b_get (insn)) - { - case 0: - return 32; /* mov.n */ - case 15: - switch (Field_t_Slot_inst16b_get (insn)) - { - case 0: - return 35; /* ret.n */ - case 1: - return 15; /* retw.n */ - case 2: - return 197; /* break.n */ - case 3: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 34; /* nop.n */ - break; - case 6: - if (Field_s_Slot_inst16b_get (insn) == 0) - return 30; /* ill.n */ - break; - } - break; - } - break; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - switch (Field_op0_Slot_inst16a_get (insn)) - { - case 8: - return 31; /* l32i.n */ - case 9: - return 36; /* s32i.n */ - case 10: - return 26; /* add.n */ - case 11: - return 27; /* addi.n */ - } - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = ((insn[0] & 0xffff00) >> 8); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = ((insn[0] & 0xffff00) >> 8); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x800000; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc00000; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x800000) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc00000) == 0x800000) - return 1; /* x16a */ - if ((insn[0] & 0xe00000) == 0xc00000) - return 2; /* x16b */ - return -1; -} - -static int length_table[16] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int op0 = (insn[0] >> 4) & 0xf; - return length_table[op0]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 1 /* big-endian */, - 3 /* insn_size */, 0, - 3, formats, format_decoder, length_decoder, - 3, slots, - 39 /* num_fields */, - 70, operands, - 235, iclasses, - 291, opcodes, 0, - 1, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 0, interfaces, 0, - 0, funcUnits, 0 -}; diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c index a1d220bb9a..fd5de5576b 100644 --- a/target/xtensa/core-sample_controller.c +++ b/target/xtensa/core-sample_controller.c @@ -34,13 +34,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_sample_controller -#include "core-sample_controller/xtensa-modules.inc.c" +#include "core-sample_controller/xtensa-modules.c.inc" static XtensaConfig sample_controller __attribute__((unused)) = { .name = "sample_controller", .gdb_regmap = { .reg = { -#include "core-sample_controller/gdb-config.inc.c" +#include "core-sample_controller/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-sample_controller/gdb-config.c.inc b/target/xtensa/core-sample_controller/gdb-config.c.inc new file mode 100644 index 0000000000..99e172d819 --- /dev/null +++ b/target/xtensa/core-sample_controller/gdb-config.c.inc @@ -0,0 +1,141 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) + XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask0,0,0,0) + XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask1,0,0,0) + XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask2,0,0,0) + XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask3,0,0,0) + XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask4,0,0,0) + XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask5,0,0,0) + XTREG_END diff --git a/target/xtensa/core-sample_controller/gdb-config.inc.c b/target/xtensa/core-sample_controller/gdb-config.inc.c deleted file mode 100644 index 99e172d819..0000000000 --- a/target/xtensa/core-sample_controller/gdb-config.inc.c +++ /dev/null @@ -1,141 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2016 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) - XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) - XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) - XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) - XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) - XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) - XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) - XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) - XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) - XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) - XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) - XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) - XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) - XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) - XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) - XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) - XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) - XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) - XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) - XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) - XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) - XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) - XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) - XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) - XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) - XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) - XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask0,0,0,0) - XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask1,0,0,0) - XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask2,0,0,0) - XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask3,0,0,0) - XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask4,0,0,0) - XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask5,0,0,0) - XTREG_END diff --git a/target/xtensa/core-sample_controller/xtensa-modules.c.inc b/target/xtensa/core-sample_controller/xtensa-modules.c.inc new file mode 100644 index 0000000000..7e87d216bd --- /dev/null +++ b/target/xtensa/core-sample_controller/xtensa-modules.c.inc @@ -0,0 +1,11366 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "qemu/osdep.h" +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 55 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 230 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EPS6", 13, 0 }, + { "EPS7", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "SAR", 6, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 59 + +enum xtensa_state_id { + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_SAR, + STATE_MISC0, + STATE_MISC1, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12 +}; + + +/* Functional units. */ + +#define funcUnits 0 + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + return (*valp >= 32); +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = uimmrx4_in_0 << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_immt, + OPERAND_imms, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wer_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_salt, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + + + + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_XSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_XSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_XSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_RSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_RSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_RSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_WSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_WSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_WSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 43 /* num_fields */, + 77, operands, + 263, iclasses, + 317, opcodes, 0, + 1, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 0, funcUnits, 0 +}; diff --git a/target/xtensa/core-sample_controller/xtensa-modules.inc.c b/target/xtensa/core-sample_controller/xtensa-modules.inc.c deleted file mode 100644 index 7e87d216bd..0000000000 --- a/target/xtensa/core-sample_controller/xtensa-modules.inc.c +++ /dev/null @@ -1,11366 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2016 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "qemu/osdep.h" -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "EXPSTATE", 230, 1 } -}; - -#define NUM_SYSREGS 55 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 230 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, - { "EPS5", 13, 0 }, - { "EPS6", 13, 0 }, - { "EPS7", 13, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "SAR", 6, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } -}; - -#define NUM_STATES 59 - -enum xtensa_state_id { - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_SAR, - STATE_MISC0, - STATE_MISC1, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_EXPSTATE -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12 -}; - - -/* Functional units. */ - -#define funcUnits 0 - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "IMPWIRE", 32, 0, 0, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - return (*valp >= 32); -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) -{ - unsigned uimmrx4_out_0; - unsigned uimmrx4_in_0; - uimmrx4_in_0 = *valp & 0xf; - uimmrx4_out_0 = uimmrx4_in_0 << 2; - *valp = uimmrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) -{ - unsigned uimmrx4_in_0; - unsigned uimmrx4_out_0; - uimmrx4_out_0 = *valp; - uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); - *valp = uimmrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) -{ - unsigned xt_wbr18_label_out_0; - unsigned xt_wbr18_label_in_0; - xt_wbr18_label_in_0 = *valp & 0x3ffff; - xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); - *valp = xt_wbr18_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) -{ - unsigned xt_wbr18_label_in_0; - unsigned xt_wbr18_label_out_0; - xt_wbr18_label_out_0 = *valp; - xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bitindex_decode (uint32 *valp) -{ - unsigned bitindex_out_0; - unsigned bitindex_in_0; - bitindex_in_0 = *valp & 0x1f; - bitindex_out_0 = (0 << 5) | bitindex_in_0; - *valp = bitindex_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bitindex_encode (uint32 *valp) -{ - unsigned bitindex_in_0; - unsigned bitindex_out_0; - bitindex_out_0 = *valp; - bitindex_in_0 = (bitindex_out_0 & 0x1f); - *valp = bitindex_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "bitindex", FIELD_bitindex, -1, 0, - 0, - OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_immt, - OPERAND_imms, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_bitindex, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimmrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32nb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_salt_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_lddr32_p_args, - 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sddr32_p_args, - 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eraccess_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eraccess_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eraccess_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wer_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_expstate_args, - 1, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 1, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s32nb, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_memctl, - ICLASS_xt_iclass_wsr_memctl, - ICLASS_xt_iclass_xsr_memctl, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_iclass_salt, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_lddr32_p, - ICLASS_xt_iclass_sddr32_p, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rsr_eraccess, - ICLASS_xt_iclass_wsr_eraccess, - ICLASS_xt_iclass_xsr_eraccess, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x590000; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36100; -} - -static void -Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136100; -} - -static void -Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616100; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b300; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b300; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b300; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d300; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d300; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d300; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b400; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b400; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b400; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d400; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d400; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d400; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b500; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b500; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b500; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d500; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d500; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d500; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b600; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b600; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b600; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d600; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d600; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d600; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b700; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b700; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b700; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d700; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d700; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d700; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c300; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c300; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c300; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c400; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c400; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c400; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c500; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c500; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c500; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c600; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c600; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c600; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c700; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c700; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c700; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x720000; -} - -static void -Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x620000; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39000; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139000; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619000; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a000; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a000; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a000; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39100; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x139100; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x619100; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a100; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13a100; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61a100; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38000; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138000; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618000; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38100; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x138100; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x618100; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36000; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136000; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616000; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e0; -} - -static void -Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f0; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135900; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f200; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f200; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f200; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20000; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20000; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20000; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf20000; -} - -static void -Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35f00; -} - -static void -Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135f00; -} - -static void -Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615f00; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e60; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e600; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0000; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1000; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1200; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe2000; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { - Opcode_s32nb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { - Opcode_rsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { - Opcode_wsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { - Opcode_xsr_memctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { - Opcode_salt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { - Opcode_saltu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { - Opcode_lddr32_p_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { - Opcode_sddr32_p_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { - Opcode_rsr_eraccess_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { - Opcode_wsr_eraccess_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { - Opcode_xsr_eraccess_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 -}; - - - - - -/* Opcode table. */ - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s32nb", ICLASS_xt_iclass_s32nb, - 0, - Opcode_s32nb_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, - 0, - Opcode_rsr_memctl_encode_fns, 0, 0 }, - { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, - 0, - Opcode_wsr_memctl_encode_fns, 0, 0 }, - { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, - 0, - Opcode_xsr_memctl_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "salt", ICLASS_xt_iclass_salt, - 0, - Opcode_salt_encode_fns, 0, 0 }, - { "saltu", ICLASS_xt_iclass_salt, - 0, - Opcode_saltu_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "lddr32.p", ICLASS_xt_iclass_lddr32_p, - 0, - Opcode_lddr32_p_encode_fns, 0, 0 }, - { "sddr32.p", ICLASS_xt_iclass_sddr32_p, - 0, - Opcode_sddr32_p_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, - 0, - Opcode_rsr_eraccess_encode_fns, 0, 0 }, - { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, - 0, - Opcode_wsr_eraccess_encode_fns, 0, 0 }, - { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, - 0, - Opcode_xsr_eraccess_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S32NB, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_MEMCTL, - OPCODE_WSR_MEMCTL, - OPCODE_XSR_MEMCTL, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_SALT, - OPCODE_SALTU, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_LDDR32_P, - OPCODE_SDDR32_P, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RSR_ERACCESS, - OPCODE_WSR_ERACCESS, - OPCODE_XSR_ERACCESS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_LDDR32_P; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_SDDR32_P; - } - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 95) - return OPCODE_XSR_ERACCESS; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_XSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_SALTU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_SALT; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_QUOU; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_QUOS; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_REMU; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_REMS; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 95) - return OPCODE_RSR_ERACCESS; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_RSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 89) - return OPCODE_WSR_MMID; - if (Field_sr_Slot_inst_get (insn) == 95) - return OPCODE_WSR_ERACCESS; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_WSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 230) - return OPCODE_RUR_EXPSTATE; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WUR_EXPSTATE; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_S32NB; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc) - return 2; /* x16b */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 3 /* insn_size */, 0, - 3, formats, format_decoder, length_decoder, - 3, slots, - 43 /* num_fields */, - 77, operands, - 263, iclasses, - 317, opcodes, 0, - 1, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 1, interfaces, 0, - 0, funcUnits, 0 -}; diff --git a/target/xtensa/core-test_kc705_be.c b/target/xtensa/core-test_kc705_be.c index ab73c3885f..294c16f2f4 100644 --- a/target/xtensa/core-test_kc705_be.c +++ b/target/xtensa/core-test_kc705_be.c @@ -34,13 +34,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_test_kc705_be -#include "core-test_kc705_be/xtensa-modules.inc.c" +#include "core-test_kc705_be/xtensa-modules.c.inc" static XtensaConfig test_kc705_be __attribute__((unused)) = { .name = "test_kc705_be", .gdb_regmap = { .reg = { -#include "core-test_kc705_be/gdb-config.inc.c" +#include "core-test_kc705_be/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-test_kc705_be/gdb-config.c.inc b/target/xtensa/core-test_kc705_be/gdb-config.c.inc new file mode 100644 index 0000000000..eb3e03cd52 --- /dev/null +++ b/target/xtensa/core-test_kc705_be/gdb-config.c.inc @@ -0,0 +1,259 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) + XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, + "03:40:48:2b","03:40:48:7a",0,0,0,0) + XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, + "03:40:49:2b","03:40:49:7a",0,0,0,0) + XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, + "03:40:4a:2b","03:40:4a:7a",0,0,0,0) + XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, + "03:40:4b:2b","03:40:4b:7a",0,0,0,0) + XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, + "03:40:4c:2b","03:40:4c:7a",0,0,0,0) + XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, + "03:40:4d:2b","03:40:4d:7a",0,0,0,0) + XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, + "03:40:4e:2b","03:40:4e:7a",0,0,0,0) + XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, + "03:40:4f:2b","03:40:4f:7a",0,0,0,0) + XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, + "03:40:40:3c","03:40:40:1c",0,0,0,0) + XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, + "03:40:41:3c","03:40:44:1c",0,0,0,0) + XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, + "03:40:42:3c","03:40:48:1c",0,0,0,0) + XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, + "03:40:43:3c","03:40:4c:1c",0,0,0,0) + XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) + XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) + XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) + XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) + XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) + XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) + XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) + XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) + XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) + XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) + XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask19,0,0,0) + XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask20,0,0,0) + XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask21,0,0,0) + XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask22,0,0,0) + XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask23,0,0,0) + XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask24,0,0,0) + XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3, + 0,0,&xtensa_mask25,0,0,0) + XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2, + 0,0,&xtensa_mask26,0,0,0) + XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1, + 0,0,&xtensa_mask27,0,0,0) + XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6, + 0,0,&xtensa_mask28,0,0,0) + XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5, + 0,0,&xtensa_mask29,0,0,0) + XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4, + 0,0,&xtensa_mask30,0,0,0) + XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6, + 0,0,&xtensa_mask31,0,0,0) + XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5, + 0,0,&xtensa_mask32,0,0,0) + XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4, + 0,0,&xtensa_mask33,0,0,0) + XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase, + 0,0,&xtensa_mask34,0,0,0) + XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow, + 0,0,&xtensa_mask35,0,0,0) + XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar, + 0,0,&xtensa_mask36,0,0,0) + XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr, + 0,0,&xtensa_mask37,0,0,0) + XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused, + 0,0,&xtensa_mask38,0,0,0) + XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize, + 0,0,&xtensa_mask39,0,0,0) + XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts, + 0,0,&xtensa_mask40,0,0,0) + XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset, + 0,0,&xtensa_mask41,0,0,0) + XTREG_END diff --git a/target/xtensa/core-test_kc705_be/gdb-config.inc.c b/target/xtensa/core-test_kc705_be/gdb-config.inc.c deleted file mode 100644 index eb3e03cd52..0000000000 --- a/target/xtensa/core-test_kc705_be/gdb-config.inc.c +++ /dev/null @@ -1,259 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) - XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) - XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) - XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) - XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) - XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) - XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) - XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) - XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) - XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) - XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) - XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) - XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, - "03:40:48:2b","03:40:48:7a",0,0,0,0) - XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, - "03:40:49:2b","03:40:49:7a",0,0,0,0) - XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, - "03:40:4a:2b","03:40:4a:7a",0,0,0,0) - XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, - "03:40:4b:2b","03:40:4b:7a",0,0,0,0) - XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, - "03:40:4c:2b","03:40:4c:7a",0,0,0,0) - XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, - "03:40:4d:2b","03:40:4d:7a",0,0,0,0) - XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, - "03:40:4e:2b","03:40:4e:7a",0,0,0,0) - XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, - "03:40:4f:2b","03:40:4f:7a",0,0,0,0) - XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, - "03:40:40:3c","03:40:40:1c",0,0,0,0) - XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, - "03:40:41:3c","03:40:44:1c",0,0,0,0) - XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, - "03:40:42:3c","03:40:48:1c",0,0,0,0) - XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, - "03:40:43:3c","03:40:4c:1c",0,0,0,0) - XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) - XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) - XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) - XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) - XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) - XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) - XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) - XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) - XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) - XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) - XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) - XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) - XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) - XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) - XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) - XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) - XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) - XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) - XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) - XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) - XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) - XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) - XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) - XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) - XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) - XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) - XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) - XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) - XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) - XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) - XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) - XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) - XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) - XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) - XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) - XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) - XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) - XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, - 0,0,&xtensa_mask0,0,0,0) - XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, - 0,0,&xtensa_mask1,0,0,0) - XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, - 0,0,&xtensa_mask2,0,0,0) - XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, - 0,0,&xtensa_mask3,0,0,0) - XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, - 0,0,&xtensa_mask4,0,0,0) - XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, - 0,0,&xtensa_mask5,0,0,0) - XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, - 0,0,&xtensa_mask6,0,0,0) - XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, - 0,0,&xtensa_mask7,0,0,0) - XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, - 0,0,&xtensa_mask8,0,0,0) - XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, - 0,0,&xtensa_mask9,0,0,0) - XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, - 0,0,&xtensa_mask10,0,0,0) - XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, - 0,0,&xtensa_mask11,0,0,0) - XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, - 0,0,&xtensa_mask12,0,0,0) - XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, - 0,0,&xtensa_mask13,0,0,0) - XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, - 0,0,&xtensa_mask14,0,0,0) - XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, - 0,0,&xtensa_mask15,0,0,0) - XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask16,0,0,0) - XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask17,0,0,0) - XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask18,0,0,0) - XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, - 0,0,&xtensa_mask19,0,0,0) - XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask20,0,0,0) - XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask21,0,0,0) - XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask22,0,0,0) - XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc, - 0,0,&xtensa_mask23,0,0,0) - XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum, - 0,0,&xtensa_mask24,0,0,0) - XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3, - 0,0,&xtensa_mask25,0,0,0) - XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2, - 0,0,&xtensa_mask26,0,0,0) - XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1, - 0,0,&xtensa_mask27,0,0,0) - XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6, - 0,0,&xtensa_mask28,0,0,0) - XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5, - 0,0,&xtensa_mask29,0,0,0) - XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4, - 0,0,&xtensa_mask30,0,0,0) - XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6, - 0,0,&xtensa_mask31,0,0,0) - XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5, - 0,0,&xtensa_mask32,0,0,0) - XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4, - 0,0,&xtensa_mask33,0,0,0) - XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase, - 0,0,&xtensa_mask34,0,0,0) - XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow, - 0,0,&xtensa_mask35,0,0,0) - XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar, - 0,0,&xtensa_mask36,0,0,0) - XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr, - 0,0,&xtensa_mask37,0,0,0) - XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused, - 0,0,&xtensa_mask38,0,0,0) - XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize, - 0,0,&xtensa_mask39,0,0,0) - XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts, - 0,0,&xtensa_mask40,0,0,0) - XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset, - 0,0,&xtensa_mask41,0,0,0) - XTREG_END diff --git a/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc b/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc new file mode 100644 index 0000000000..bc7cf44828 --- /dev/null +++ b/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc @@ -0,0 +1,45117 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 78 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 247 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "PREFCTL", 9, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID6", 1, 0 }, + { "INSTPGSZID5", 1, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID6", 1, 0 }, + { "DATAPGSZID5", 1, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_SAR", 6, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 89 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_PREFCTL, + STATE_ASID3, + STATE_ASID2, + STATE_ASID1, + STATE_INSTPGSZID6, + STATE_INSTPGSZID5, + STATE_INSTPGSZID4, + STATE_DATAPGSZID6, + STATE_DATAPGSZID5, + STATE_DATAPGSZID4, + STATE_PTBASE, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_AE_OVERFLOW, + STATE_AE_SAR, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_ftsf333ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf333ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_ftsf359ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf359ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_ftsf355ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_ftsf355ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf354ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_ftsf354ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_ftsf357ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_ftsf357ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf347ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf347ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_ftsf345ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_ftsf345ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf358ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_ftsf358ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 20) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf93ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf93ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf55_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ftsf55_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_ftsf121ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf121ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_ftsf91_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_ftsf91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_ftsf351_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_ftsf351_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 21) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 20) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf20ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf20ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_ftsf356ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_ftsf356ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ftsf62ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf62ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf352ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_ftsf352ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf123ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf123ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); + tie_t = (val << 23) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf117ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf117ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf68ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf68ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); +} + +static unsigned +Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + return tie_t; +} + +static void +Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf61_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_ftsf61_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf83ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf83ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf70ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf70ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf74ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf74ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf85ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf85ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf102ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ftsf102ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_ftsf335_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_ftsf335_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf208ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf208ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf340ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf340ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld69_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld68_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld19_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld74_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld66_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld90_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld88_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld65_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld79_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); +} + +static unsigned +Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf280_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_ftsf280_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_ftsf288_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); + return tie_t; +} + +static void +Field_ftsf288_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +} + +static unsigned +Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + return tie_t; +} + +static void +Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); +} + +static unsigned +Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_ftsf211ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf211ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 21) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); + tie_t = (val << 17) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 21) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); + tie_t = (val << 17) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf287ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf287ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +} + +static unsigned +Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21); +} + +static unsigned +Field_ftsf285ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf285ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21); +} + +static unsigned +Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); + tie_t = (val << 20) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 11) >> 18); + return tie_t; +} + +static void +Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf309_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + return tie_t; +} + +static void +Field_ftsf309_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_ftsf327ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf327ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_ftsf363ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); + return tie_t; +} + +static void +Field_ftsf363ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf373ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ftsf373ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_ftsf376ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_ftsf376ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 21) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_ftsf370ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_ftsf370ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf378ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_ftsf378ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf217ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf217ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf305ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf305ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf307ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf307ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_ftsf379ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf379ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf315_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + return tie_t; +} + +static void +Field_ftsf315_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld52_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_combined1e9fefee_fld96_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_combined1e9fefee_fld96_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_combined1e9fefee_fld98_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_combined1e9fefee_fld98_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld49_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld50_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld40_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_ftsf362_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf362_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_op0_s4_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_op0_s4_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld47_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf289ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf289ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); + tie_t = (val << 19) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_ftsf386ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf386ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 21) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf382ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf382ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf291ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf291ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +} + +static unsigned +Field_ftsf383ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf383ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf293ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_ftsf293ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_ftsf384ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf384ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); + return tie_t; +} + +static void +Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_ftsf387ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ftsf387ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf319ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); + return tie_t; +} + +static void +Field_ftsf319ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf388ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_ftsf388ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); + return tie_t; +} + +static void +Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf389ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_ftsf389ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +} + +static unsigned +Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); + tie_t = (val << 19) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); +} + +static unsigned +Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld123_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld121_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); +} + +static unsigned +Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld28_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld127_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); +} + +static unsigned +Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld46_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 5) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x7f80000) | (tie_t << 19); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 9) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff800) | (tie_t << 11); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ftsf11_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_ftsf11_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_ftsf11_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_ftsf11_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_ftsf11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_combined2c0b5f72_fld37_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld37_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 14) >> 21); + return tie_t; +} + +static void +Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff80) | (tie_t << 7); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_r3, + FIELD_ae_s_non_samt, + FIELD_ae_s3, + FIELD_ae_r32, + FIELD_ae_samt_s_t, + FIELD_ae_r20, + FIELD_ae_r10, + FIELD_ae_s20, + FIELD_ae_fld_ohba, + FIELD_ae_fld_ohba2, + FIELD_op0_s3, + FIELD_ftsf11, + FIELD_ftsf12, + FIELD_ftsf13, + FIELD_ftsf20ae_slot1, + FIELD_ftsf21ae_slot1, + FIELD_ftsf22ae_slot1, + FIELD_ftsf23ae_slot1, + FIELD_ftsf24ae_slot1, + FIELD_ftsf25ae_slot1, + FIELD_ftsf26ae_slot1, + FIELD_ftsf27ae_slot1, + FIELD_ftsf28ae_slot1, + FIELD_ftsf29ae_slot1, + FIELD_ftsf30ae_slot1, + FIELD_ftsf31ae_slot1, + FIELD_ftsf32ae_slot1, + FIELD_ftsf33ae_slot1, + FIELD_ftsf34ae_slot1, + FIELD_ftsf35ae_slot1, + FIELD_ftsf36ae_slot1, + FIELD_ftsf37ae_slot1, + FIELD_ftsf38ae_slot1, + FIELD_ftsf40ae_slot1, + FIELD_ftsf41ae_slot1, + FIELD_ftsf42ae_slot1, + FIELD_ftsf43ae_slot1, + FIELD_ftsf45ae_slot1, + FIELD_ftsf47ae_slot1, + FIELD_ftsf48ae_slot1, + FIELD_ftsf49ae_slot1, + FIELD_ftsf50ae_slot1, + FIELD_ftsf51ae_slot1, + FIELD_ftsf52ae_slot1, + FIELD_ftsf53ae_slot1, + FIELD_ftsf54ae_slot1, + FIELD_ftsf55, + FIELD_ftsf56ae_slot1, + FIELD_ftsf57ae_slot1, + FIELD_ftsf58ae_slot1, + FIELD_ftsf60ae_slot1, + FIELD_ftsf61, + FIELD_ftsf62ae_slot1, + FIELD_ftsf63ae_slot1, + FIELD_ftsf64ae_slot1, + FIELD_ftsf66ae_slot1, + FIELD_ftsf68ae_slot1, + FIELD_ftsf69ae_slot1, + FIELD_ftsf70ae_slot1, + FIELD_ftsf71ae_slot1, + FIELD_ftsf72ae_slot1, + FIELD_ftsf73ae_slot1, + FIELD_ftsf74ae_slot1, + FIELD_ftsf75ae_slot1, + FIELD_ftsf76ae_slot1, + FIELD_ftsf77ae_slot1, + FIELD_ftsf78ae_slot1, + FIELD_ftsf79ae_slot1, + FIELD_ftsf80ae_slot1, + FIELD_ftsf81ae_slot1, + FIELD_ftsf82ae_slot1, + FIELD_ftsf83ae_slot1, + FIELD_ftsf84ae_slot1, + FIELD_ftsf85ae_slot1, + FIELD_ftsf86ae_slot1, + FIELD_ftsf87ae_slot1, + FIELD_ftsf88ae_slot1, + FIELD_ftsf89ae_slot1, + FIELD_ftsf90ae_slot1, + FIELD_ftsf91, + FIELD_ftsf92ae_slot1, + FIELD_ftsf93ae_slot1, + FIELD_ftsf94ae_slot1, + FIELD_ftsf96ae_slot1, + FIELD_ftsf97ae_slot1, + FIELD_ftsf99ae_slot1, + FIELD_ftsf101ae_slot1, + FIELD_ftsf102ae_slot1, + FIELD_ftsf103ae_slot1, + FIELD_ftsf106ae_slot1, + FIELD_ftsf107ae_slot1, + FIELD_ftsf108ae_slot1, + FIELD_ftsf109ae_slot1, + FIELD_ftsf110ae_slot1, + FIELD_ftsf111ae_slot1, + FIELD_ftsf112ae_slot1, + FIELD_ftsf113ae_slot1, + FIELD_ftsf114ae_slot1, + FIELD_ftsf115ae_slot1, + FIELD_ftsf116ae_slot1, + FIELD_ftsf117ae_slot1, + FIELD_ftsf118ae_slot1, + FIELD_ftsf120ae_slot1, + FIELD_ftsf121ae_slot1, + FIELD_ftsf123ae_slot1, + FIELD_ftsf124ae_slot1, + FIELD_ftsf125ae_slot1, + FIELD_ftsf126ae_slot1, + FIELD_ftsf127ae_slot1, + FIELD_ftsf128ae_slot1, + FIELD_ftsf129ae_slot1, + FIELD_ftsf130ae_slot1, + FIELD_ftsf131ae_slot1, + FIELD_ftsf132ae_slot1, + FIELD_ftsf133ae_slot1, + FIELD_ftsf134ae_slot1, + FIELD_ftsf135ae_slot1, + FIELD_ftsf136ae_slot1, + FIELD_ftsf137ae_slot1, + FIELD_ftsf138ae_slot1, + FIELD_ftsf139ae_slot1, + FIELD_ftsf140ae_slot1, + FIELD_ftsf141ae_slot1, + FIELD_ftsf142ae_slot1, + FIELD_ftsf143ae_slot1, + FIELD_ftsf144ae_slot1, + FIELD_ftsf145ae_slot1, + FIELD_ftsf146ae_slot1, + FIELD_ftsf147ae_slot1, + FIELD_ftsf148ae_slot1, + FIELD_ftsf149ae_slot1, + FIELD_ftsf150ae_slot1, + FIELD_ftsf151ae_slot1, + FIELD_ftsf152ae_slot1, + FIELD_ftsf153ae_slot1, + FIELD_ftsf154ae_slot1, + FIELD_ftsf155ae_slot1, + FIELD_ftsf156ae_slot1, + FIELD_ftsf157ae_slot1, + FIELD_ftsf158ae_slot1, + FIELD_ftsf159ae_slot1, + FIELD_ftsf160ae_slot1, + FIELD_ftsf161ae_slot1, + FIELD_ftsf162ae_slot1, + FIELD_ftsf163ae_slot1, + FIELD_ftsf164ae_slot1, + FIELD_ftsf165ae_slot1, + FIELD_ftsf166ae_slot1, + FIELD_ftsf167ae_slot1, + FIELD_ftsf168ae_slot1, + FIELD_ftsf169ae_slot1, + FIELD_ftsf170ae_slot1, + FIELD_ftsf171ae_slot1, + FIELD_ftsf172ae_slot1, + FIELD_ftsf173ae_slot1, + FIELD_ftsf174ae_slot1, + FIELD_ftsf175ae_slot1, + FIELD_ftsf176ae_slot1, + FIELD_ftsf177ae_slot1, + FIELD_ftsf178ae_slot1, + FIELD_ftsf179ae_slot1, + FIELD_ftsf180ae_slot1, + FIELD_ftsf181ae_slot1, + FIELD_ftsf182ae_slot1, + FIELD_ftsf183ae_slot1, + FIELD_ftsf184ae_slot1, + FIELD_ftsf185ae_slot1, + FIELD_ftsf186ae_slot1, + FIELD_ftsf187ae_slot1, + FIELD_ftsf188ae_slot1, + FIELD_ftsf189ae_slot1, + FIELD_ftsf190ae_slot1, + FIELD_ftsf191ae_slot1, + FIELD_ftsf192ae_slot1, + FIELD_ftsf193ae_slot1, + FIELD_ftsf194ae_slot1, + FIELD_ftsf195ae_slot1, + FIELD_ftsf196ae_slot1, + FIELD_ftsf197ae_slot1, + FIELD_ftsf198ae_slot1, + FIELD_ftsf199ae_slot1, + FIELD_ftsf200ae_slot1, + FIELD_ftsf201ae_slot1, + FIELD_ftsf202ae_slot1, + FIELD_ftsf203ae_slot1, + FIELD_ftsf204ae_slot1, + FIELD_ftsf205ae_slot1, + FIELD_ftsf206ae_slot1, + FIELD_ftsf207ae_slot1, + FIELD_ftsf208ae_slot1, + FIELD_ftsf210ae_slot1, + FIELD_ftsf333ae_slot1, + FIELD_ftsf334ae_slot1, + FIELD_ftsf335, + FIELD_ftsf336ae_slot1, + FIELD_ftsf337ae_slot1, + FIELD_ftsf339ae_slot1, + FIELD_ftsf340ae_slot1, + FIELD_ftsf341ae_slot1, + FIELD_ftsf342ae_slot1, + FIELD_ftsf343ae_slot1, + FIELD_ftsf344ae_slot1, + FIELD_ftsf345ae_slot1, + FIELD_ftsf347ae_slot1, + FIELD_ftsf348ae_slot1, + FIELD_ftsf349ae_slot1, + FIELD_ftsf350ae_slot1, + FIELD_ftsf351, + FIELD_ftsf352ae_slot1, + FIELD_ftsf354ae_slot1, + FIELD_ftsf355ae_slot1, + FIELD_ftsf356ae_slot1, + FIELD_ftsf357ae_slot1, + FIELD_ftsf358ae_slot1, + FIELD_ftsf359ae_slot1, + FIELD_op0_s4, + FIELD_ftsf211ae_slot0, + FIELD_ftsf212ae_slot0, + FIELD_ftsf213ae_slot0, + FIELD_ftsf214ae_slot0, + FIELD_ftsf215ae_slot0, + FIELD_ftsf217ae_slot0, + FIELD_ftsf218ae_slot0, + FIELD_ftsf219ae_slot0, + FIELD_ftsf220ae_slot0, + FIELD_ftsf221ae_slot0, + FIELD_ftsf222ae_slot0, + FIELD_ftsf223ae_slot0, + FIELD_ftsf224ae_slot0, + FIELD_ftsf225ae_slot0, + FIELD_ftsf226ae_slot0, + FIELD_ftsf227ae_slot0, + FIELD_ftsf228ae_slot0, + FIELD_ftsf229ae_slot0, + FIELD_ftsf230ae_slot0, + FIELD_ftsf231ae_slot0, + FIELD_ftsf232ae_slot0, + FIELD_ftsf233ae_slot0, + FIELD_ftsf234ae_slot0, + FIELD_ftsf235ae_slot0, + FIELD_ftsf236ae_slot0, + FIELD_ftsf237ae_slot0, + FIELD_ftsf238ae_slot0, + FIELD_ftsf239ae_slot0, + FIELD_ftsf240ae_slot0, + FIELD_ftsf241ae_slot0, + FIELD_ftsf242ae_slot0, + FIELD_ftsf243ae_slot0, + FIELD_ftsf244ae_slot0, + FIELD_ftsf245ae_slot0, + FIELD_ftsf246ae_slot0, + FIELD_ftsf247ae_slot0, + FIELD_ftsf248ae_slot0, + FIELD_ftsf249ae_slot0, + FIELD_ftsf250ae_slot0, + FIELD_ftsf251ae_slot0, + FIELD_ftsf252ae_slot0, + FIELD_ftsf253ae_slot0, + FIELD_ftsf254ae_slot0, + FIELD_ftsf255ae_slot0, + FIELD_ftsf256ae_slot0, + FIELD_ftsf257ae_slot0, + FIELD_ftsf258ae_slot0, + FIELD_ftsf259ae_slot0, + FIELD_ftsf260ae_slot0, + FIELD_ftsf261ae_slot0, + FIELD_ftsf262ae_slot0, + FIELD_ftsf263ae_slot0, + FIELD_ftsf264ae_slot0, + FIELD_ftsf265ae_slot0, + FIELD_ftsf266ae_slot0, + FIELD_ftsf267ae_slot0, + FIELD_ftsf268ae_slot0, + FIELD_ftsf269ae_slot0, + FIELD_ftsf270ae_slot0, + FIELD_ftsf271ae_slot0, + FIELD_ftsf272ae_slot0, + FIELD_ftsf273ae_slot0, + FIELD_ftsf274ae_slot0, + FIELD_ftsf275ae_slot0, + FIELD_ftsf276ae_slot0, + FIELD_ftsf277ae_slot0, + FIELD_ftsf278ae_slot0, + FIELD_ftsf279ae_slot0, + FIELD_ftsf280, + FIELD_ftsf281ae_slot0, + FIELD_ftsf282ae_slot0, + FIELD_ftsf284ae_slot0, + FIELD_ftsf285ae_slot0, + FIELD_ftsf287ae_slot0, + FIELD_ftsf288, + FIELD_ftsf289ae_slot0, + FIELD_ftsf290ae_slot0, + FIELD_ftsf291ae_slot0, + FIELD_ftsf292ae_slot0, + FIELD_ftsf293ae_slot0, + FIELD_ftsf294ae_slot0, + FIELD_ftsf295ae_slot0, + FIELD_ftsf296ae_slot0, + FIELD_ftsf297ae_slot0, + FIELD_ftsf298ae_slot0, + FIELD_ftsf300ae_slot0, + FIELD_ftsf302ae_slot0, + FIELD_ftsf304ae_slot0, + FIELD_ftsf305ae_slot0, + FIELD_ftsf306ae_slot0, + FIELD_ftsf307ae_slot0, + FIELD_ftsf308ae_slot0, + FIELD_ftsf309, + FIELD_ftsf310ae_slot0, + FIELD_ftsf311ae_slot0, + FIELD_ftsf312ae_slot0, + FIELD_ftsf313ae_slot0, + FIELD_ftsf314ae_slot0, + FIELD_ftsf315, + FIELD_ftsf316ae_slot0, + FIELD_ftsf317ae_slot0, + FIELD_ftsf319ae_slot0, + FIELD_ftsf320ae_slot0, + FIELD_ftsf322ae_slot0, + FIELD_ftsf323ae_slot0, + FIELD_ftsf324ae_slot0, + FIELD_ftsf325ae_slot0, + FIELD_ftsf326ae_slot0, + FIELD_ftsf327ae_slot0, + FIELD_ftsf328ae_slot0, + FIELD_ftsf329ae_slot0, + FIELD_ftsf360ae_slot0, + FIELD_ftsf361ae_slot0, + FIELD_ftsf362, + FIELD_ftsf363ae_slot0, + FIELD_ftsf364ae_slot0, + FIELD_ftsf366ae_slot0, + FIELD_ftsf368ae_slot0, + FIELD_ftsf370ae_slot0, + FIELD_ftsf373ae_slot0, + FIELD_ftsf376ae_slot0, + FIELD_ftsf378ae_slot0, + FIELD_ftsf379ae_slot0, + FIELD_ftsf382ae_slot0, + FIELD_ftsf383ae_slot0, + FIELD_ftsf384ae_slot0, + FIELD_ftsf386ae_slot0, + FIELD_ftsf387ae_slot0, + FIELD_ftsf388ae_slot0, + FIELD_ftsf389ae_slot0, + FIELD_ae_mul32x24fld, + FIELD_op0_s4_s4, + FIELD_combined2c0b5f72_fld28, + FIELD_combined2c0b5f72_fld37, + FIELD_combined2c0b5f72_fld39, + FIELD_combined2c0b5f72_fld40, + FIELD_combined2c0b5f72_fld46, + FIELD_combined2c0b5f72_fld47, + FIELD_combined2c0b5f72_fld49, + FIELD_combined2c0b5f72_fld50, + FIELD_combined2c0b5f72_fld52, + FIELD_combined2c0b5f72_fld121, + FIELD_combined2c0b5f72_fld123, + FIELD_combined2c0b5f72_fld127, + FIELD_combined2c0b5f72_fld133ae_slot0, + FIELD_combined2c0b5f72_fld134ae_slot0, + FIELD_combined2c0b5f72_fld135ae_slot0, + FIELD_combined2c0b5f72_fld136ae_slot0, + FIELD_combined2c0b5f72_fld137ae_slot0, + FIELD_combined2c0b5f72_fld138ae_slot0, + FIELD_combined2c0b5f72_fld139ae_slot0, + FIELD_combined2c0b5f72_fld140ae_slot0, + FIELD_combined2c0b5f72_fld141ae_slot0, + FIELD_combined2c0b5f72_fld142ae_slot0, + FIELD_combined2c0b5f72_fld143ae_slot0, + FIELD_combined2c0b5f72_fld144ae_slot0, + FIELD_combined2c0b5f72_fld145ae_slot0, + FIELD_combined2c0b5f72_fld146ae_slot0, + FIELD_combined2c0b5f72_fld148ae_slot0, + FIELD_combined2c0b5f72_fld149ae_slot0, + FIELD_op0_s4_s4_s4, + FIELD_combined1e9fefee_fld96, + FIELD_combined1e9fefee_fld98, + FIELD_combined1e9fefee_fld106ae_slot0, + FIELD_combined1e9fefee_fld107ae_slot0, + FIELD_combined1e9fefee_fld108ae_slot0, + FIELD_combined1e9fefee_fld109ae_slot0, + FIELD_op0_s3_s3, + FIELD_combined2c0b5f72_fld19, + FIELD_combined2c0b5f72_fld22, + FIELD_combined2c0b5f72_fld24, + FIELD_combined2c0b5f72_fld65, + FIELD_combined2c0b5f72_fld66, + FIELD_combined2c0b5f72_fld68, + FIELD_combined2c0b5f72_fld69, + FIELD_combined2c0b5f72_fld74, + FIELD_combined2c0b5f72_fld79, + FIELD_combined2c0b5f72_fld88, + FIELD_combined2c0b5f72_fld90, + FIELD_combined2c0b5f72_fld91, + FIELD_combined2c0b5f72_fld131ae_slot1, + FIELD_combined2c0b5f72_fld132ae_slot1, + FIELD_combined2c0b5f72_fld147ae_slot1, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + { "ae_add32", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_subshift", 1 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_ae_add32, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_subshift +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR, + REGFILE_BR, + REGFILE_AE_PR, + REGFILE_AE_QR, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, + { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) +{ + unsigned ae_samt32_out_0; + unsigned ae_samt32_in_0; + ae_samt32_in_0 = *valp & 0x1f; + ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; + *valp = ae_samt32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) +{ + unsigned ae_samt32_in_0; + unsigned ae_samt32_out_0; + ae_samt32_out_0 = *valp; + ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); + *valp = ae_samt32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 8); + return error; +} + +static int +OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) +{ + unsigned ae_lsimm16_out_0; + unsigned ae_lsimm16_in_0; + ae_lsimm16_in_0 = *valp & 0xf; + ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; + *valp = ae_lsimm16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) +{ + unsigned ae_lsimm16_in_0; + unsigned ae_lsimm16_out_0; + ae_lsimm16_out_0 = *valp; + ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); + *valp = ae_lsimm16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) +{ + unsigned ae_lsimm32_out_0; + unsigned ae_lsimm32_in_0; + ae_lsimm32_in_0 = *valp & 0xf; + ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; + *valp = ae_lsimm32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) +{ + unsigned ae_lsimm32_in_0; + unsigned ae_lsimm32_out_0; + ae_lsimm32_out_0 = *valp; + ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); + *valp = ae_lsimm32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) +{ + unsigned ae_lsimm64_out_0; + unsigned ae_lsimm64_in_0; + ae_lsimm64_in_0 = *valp & 0xf; + ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; + *valp = ae_lsimm64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) +{ + unsigned ae_lsimm64_in_0; + unsigned ae_lsimm64_out_0; + ae_lsimm64_out_0 = *valp; + ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); + *valp = ae_lsimm64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) +{ + unsigned ae_samt64_out_0; + unsigned ae_samt64_in_0; + ae_samt64_in_0 = *valp & 0x3f; + ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; + *valp = ae_samt64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) +{ + unsigned ae_samt64_in_0; + unsigned ae_samt64_out_0; + ae_samt64_out_0 = *valp; + ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); + *valp = ae_samt64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) +{ + unsigned ae_ohba_out_0; + unsigned ae_ohba_in_0; + ae_ohba_in_0 = *valp & 0xf; + ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); + *valp = ae_ohba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) +{ + unsigned ae_ohba_in_0; + unsigned ae_ohba_out_0; + ae_ohba_out_0 = *valp; + ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); + *valp = ae_ohba_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "ae_samt32", FIELD_ftsf13, -1, 0, + 0, + OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, + 0, 0 }, + { "pr0", FIELD_ftsf11, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "ae_lsimm16", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, + 0, 0 }, + { "ae_lsimm32", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, + 0, 0 }, + { "ae_lsimm64", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, + 0, 0 }, + { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, + 0, 0 }, + { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0 }, + { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0 }, + { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf11", FIELD_ftsf11, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf20ae_slot1", FIELD_ftsf20ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf55", FIELD_ftsf55, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf61", FIELD_ftsf61, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf62ae_slot1", FIELD_ftsf62ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf68ae_slot1", FIELD_ftsf68ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf70ae_slot1", FIELD_ftsf70ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf74ae_slot1", FIELD_ftsf74ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf83ae_slot1", FIELD_ftsf83ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf85ae_slot1", FIELD_ftsf85ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf91", FIELD_ftsf91, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf93ae_slot1", FIELD_ftsf93ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf102ae_slot1", FIELD_ftsf102ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf117ae_slot1", FIELD_ftsf117ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf121ae_slot1", FIELD_ftsf121ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf123ae_slot1", FIELD_ftsf123ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf208ae_slot1", FIELD_ftsf208ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf333ae_slot1", FIELD_ftsf333ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf335", FIELD_ftsf335, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf340ae_slot1", FIELD_ftsf340ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf345ae_slot1", FIELD_ftsf345ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf347ae_slot1", FIELD_ftsf347ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf351", FIELD_ftsf351, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf352ae_slot1", FIELD_ftsf352ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf354ae_slot1", FIELD_ftsf354ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf355ae_slot1", FIELD_ftsf355ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf356ae_slot1", FIELD_ftsf356ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf357ae_slot1", FIELD_ftsf357ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf358ae_slot1", FIELD_ftsf358ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf359ae_slot1", FIELD_ftsf359ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf211ae_slot0", FIELD_ftsf211ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf217ae_slot0", FIELD_ftsf217ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf280", FIELD_ftsf280, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf285ae_slot0", FIELD_ftsf285ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf287ae_slot0", FIELD_ftsf287ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf288", FIELD_ftsf288, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf289ae_slot0", FIELD_ftsf289ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf291ae_slot0", FIELD_ftsf291ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf293ae_slot0", FIELD_ftsf293ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf305ae_slot0", FIELD_ftsf305ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf307ae_slot0", FIELD_ftsf307ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf309", FIELD_ftsf309, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf315", FIELD_ftsf315, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf319ae_slot0", FIELD_ftsf319ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf327ae_slot0", FIELD_ftsf327ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf362", FIELD_ftsf362, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf363ae_slot0", FIELD_ftsf363ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf370ae_slot0", FIELD_ftsf370ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf373ae_slot0", FIELD_ftsf373ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf376ae_slot0", FIELD_ftsf376ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf378ae_slot0", FIELD_ftsf378ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf379ae_slot0", FIELD_ftsf379ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf382ae_slot0", FIELD_ftsf382ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf383ae_slot0", FIELD_ftsf383ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf384ae_slot0", FIELD_ftsf384ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf386ae_slot0", FIELD_ftsf386ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf387ae_slot0", FIELD_ftsf387ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf388ae_slot0", FIELD_ftsf388ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf389ae_slot0", FIELD_ftsf389ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld28", FIELD_combined2c0b5f72_fld28, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld37", FIELD_combined2c0b5f72_fld37, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld39", FIELD_combined2c0b5f72_fld39, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld40", FIELD_combined2c0b5f72_fld40, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld46", FIELD_combined2c0b5f72_fld46, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld47", FIELD_combined2c0b5f72_fld47, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld49", FIELD_combined2c0b5f72_fld49, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld50", FIELD_combined2c0b5f72_fld50, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld52", FIELD_combined2c0b5f72_fld52, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld121", FIELD_combined2c0b5f72_fld121, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld123", FIELD_combined2c0b5f72_fld123, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld127", FIELD_combined2c0b5f72_fld127, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld133ae_slot0", FIELD_combined2c0b5f72_fld133ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld134ae_slot0", FIELD_combined2c0b5f72_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld135ae_slot0", FIELD_combined2c0b5f72_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld136ae_slot0", FIELD_combined2c0b5f72_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld137ae_slot0", FIELD_combined2c0b5f72_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld138ae_slot0", FIELD_combined2c0b5f72_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld139ae_slot0", FIELD_combined2c0b5f72_fld139ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld140ae_slot0", FIELD_combined2c0b5f72_fld140ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld141ae_slot0", FIELD_combined2c0b5f72_fld141ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld142ae_slot0", FIELD_combined2c0b5f72_fld142ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld143ae_slot0", FIELD_combined2c0b5f72_fld143ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld144ae_slot0", FIELD_combined2c0b5f72_fld144ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld145ae_slot0", FIELD_combined2c0b5f72_fld145ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld146ae_slot0", FIELD_combined2c0b5f72_fld146ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld148ae_slot0", FIELD_combined2c0b5f72_fld148ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld149ae_slot0", FIELD_combined2c0b5f72_fld149ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s4_s4_s4", FIELD_op0_s4_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld96", FIELD_combined1e9fefee_fld96, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld98", FIELD_combined1e9fefee_fld98, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld106ae_slot0", FIELD_combined1e9fefee_fld106ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld107ae_slot0", FIELD_combined1e9fefee_fld107ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld108ae_slot0", FIELD_combined1e9fefee_fld108ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "combined1e9fefee_fld109ae_slot0", FIELD_combined1e9fefee_fld109ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld19", FIELD_combined2c0b5f72_fld19, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld22", FIELD_combined2c0b5f72_fld22, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld24", FIELD_combined2c0b5f72_fld24, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld65", FIELD_combined2c0b5f72_fld65, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld66", FIELD_combined2c0b5f72_fld66, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld68", FIELD_combined2c0b5f72_fld68, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld69", FIELD_combined2c0b5f72_fld69, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld74", FIELD_combined2c0b5f72_fld74, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld79", FIELD_combined2c0b5f72_fld79, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld88", FIELD_combined2c0b5f72_fld88, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld90", FIELD_combined2c0b5f72_fld90, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld91", FIELD_combined2c0b5f72_fld91, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld131ae_slot1", FIELD_combined2c0b5f72_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld132ae_slot1", FIELD_combined2c0b5f72_fld132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "combined2c0b5f72_fld147ae_slot1", FIELD_combined2c0b5f72_fld147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_samt32, + OPERAND_pr0, + OPERAND_qr0, + OPERAND_mac_qr0, + OPERAND_ae_lsimm16, + OPERAND_ae_lsimm32, + OPERAND_ae_lsimm64, + OPERAND_ae_samt64, + OPERAND_ae_ohba, + OPERAND_ae_ohba2, + OPERAND_pr, + OPERAND_cvt_pr, + OPERAND_qr0_rw, + OPERAND_mac_qr0_rw, + OPERAND_qr1_w, + OPERAND_mac_qr1_w, + OPERAND_ps, + OPERAND_alupppb_ps, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_r3, + OPERAND_ae_s_non_samt, + OPERAND_ae_s3, + OPERAND_ae_r32, + OPERAND_ae_samt_s_t, + OPERAND_ae_r20, + OPERAND_ae_r10, + OPERAND_ae_s20, + OPERAND_ae_fld_ohba, + OPERAND_ae_fld_ohba2, + OPERAND_op0_s3, + OPERAND_ftsf11, + OPERAND_ftsf12, + OPERAND_ftsf13, + OPERAND_ftsf20ae_slot1, + OPERAND_ftsf21ae_slot1, + OPERAND_ftsf22ae_slot1, + OPERAND_ftsf23ae_slot1, + OPERAND_ftsf24ae_slot1, + OPERAND_ftsf25ae_slot1, + OPERAND_ftsf26ae_slot1, + OPERAND_ftsf27ae_slot1, + OPERAND_ftsf28ae_slot1, + OPERAND_ftsf29ae_slot1, + OPERAND_ftsf30ae_slot1, + OPERAND_ftsf31ae_slot1, + OPERAND_ftsf32ae_slot1, + OPERAND_ftsf33ae_slot1, + OPERAND_ftsf34ae_slot1, + OPERAND_ftsf35ae_slot1, + OPERAND_ftsf36ae_slot1, + OPERAND_ftsf37ae_slot1, + OPERAND_ftsf38ae_slot1, + OPERAND_ftsf40ae_slot1, + OPERAND_ftsf41ae_slot1, + OPERAND_ftsf42ae_slot1, + OPERAND_ftsf43ae_slot1, + OPERAND_ftsf45ae_slot1, + OPERAND_ftsf47ae_slot1, + OPERAND_ftsf48ae_slot1, + OPERAND_ftsf49ae_slot1, + OPERAND_ftsf50ae_slot1, + OPERAND_ftsf51ae_slot1, + OPERAND_ftsf52ae_slot1, + OPERAND_ftsf53ae_slot1, + OPERAND_ftsf54ae_slot1, + OPERAND_ftsf55, + OPERAND_ftsf56ae_slot1, + OPERAND_ftsf57ae_slot1, + OPERAND_ftsf58ae_slot1, + OPERAND_ftsf60ae_slot1, + OPERAND_ftsf61, + OPERAND_ftsf62ae_slot1, + OPERAND_ftsf63ae_slot1, + OPERAND_ftsf64ae_slot1, + OPERAND_ftsf66ae_slot1, + OPERAND_ftsf68ae_slot1, + OPERAND_ftsf69ae_slot1, + OPERAND_ftsf70ae_slot1, + OPERAND_ftsf71ae_slot1, + OPERAND_ftsf72ae_slot1, + OPERAND_ftsf73ae_slot1, + OPERAND_ftsf74ae_slot1, + OPERAND_ftsf75ae_slot1, + OPERAND_ftsf76ae_slot1, + OPERAND_ftsf77ae_slot1, + OPERAND_ftsf78ae_slot1, + OPERAND_ftsf79ae_slot1, + OPERAND_ftsf80ae_slot1, + OPERAND_ftsf81ae_slot1, + OPERAND_ftsf82ae_slot1, + OPERAND_ftsf83ae_slot1, + OPERAND_ftsf84ae_slot1, + OPERAND_ftsf85ae_slot1, + OPERAND_ftsf86ae_slot1, + OPERAND_ftsf87ae_slot1, + OPERAND_ftsf88ae_slot1, + OPERAND_ftsf89ae_slot1, + OPERAND_ftsf90ae_slot1, + OPERAND_ftsf91, + OPERAND_ftsf92ae_slot1, + OPERAND_ftsf93ae_slot1, + OPERAND_ftsf94ae_slot1, + OPERAND_ftsf96ae_slot1, + OPERAND_ftsf97ae_slot1, + OPERAND_ftsf99ae_slot1, + OPERAND_ftsf101ae_slot1, + OPERAND_ftsf102ae_slot1, + OPERAND_ftsf103ae_slot1, + OPERAND_ftsf106ae_slot1, + OPERAND_ftsf107ae_slot1, + OPERAND_ftsf108ae_slot1, + OPERAND_ftsf109ae_slot1, + OPERAND_ftsf110ae_slot1, + OPERAND_ftsf111ae_slot1, + OPERAND_ftsf112ae_slot1, + OPERAND_ftsf113ae_slot1, + OPERAND_ftsf114ae_slot1, + OPERAND_ftsf115ae_slot1, + OPERAND_ftsf116ae_slot1, + OPERAND_ftsf117ae_slot1, + OPERAND_ftsf118ae_slot1, + OPERAND_ftsf120ae_slot1, + OPERAND_ftsf121ae_slot1, + OPERAND_ftsf123ae_slot1, + OPERAND_ftsf124ae_slot1, + OPERAND_ftsf125ae_slot1, + OPERAND_ftsf126ae_slot1, + OPERAND_ftsf127ae_slot1, + OPERAND_ftsf128ae_slot1, + OPERAND_ftsf129ae_slot1, + OPERAND_ftsf130ae_slot1, + OPERAND_ftsf131ae_slot1, + OPERAND_ftsf132ae_slot1, + OPERAND_ftsf133ae_slot1, + OPERAND_ftsf134ae_slot1, + OPERAND_ftsf135ae_slot1, + OPERAND_ftsf136ae_slot1, + OPERAND_ftsf137ae_slot1, + OPERAND_ftsf138ae_slot1, + OPERAND_ftsf139ae_slot1, + OPERAND_ftsf140ae_slot1, + OPERAND_ftsf141ae_slot1, + OPERAND_ftsf142ae_slot1, + OPERAND_ftsf143ae_slot1, + OPERAND_ftsf144ae_slot1, + OPERAND_ftsf145ae_slot1, + OPERAND_ftsf146ae_slot1, + OPERAND_ftsf147ae_slot1, + OPERAND_ftsf148ae_slot1, + OPERAND_ftsf149ae_slot1, + OPERAND_ftsf150ae_slot1, + OPERAND_ftsf151ae_slot1, + OPERAND_ftsf152ae_slot1, + OPERAND_ftsf153ae_slot1, + OPERAND_ftsf154ae_slot1, + OPERAND_ftsf155ae_slot1, + OPERAND_ftsf156ae_slot1, + OPERAND_ftsf157ae_slot1, + OPERAND_ftsf158ae_slot1, + OPERAND_ftsf159ae_slot1, + OPERAND_ftsf160ae_slot1, + OPERAND_ftsf161ae_slot1, + OPERAND_ftsf162ae_slot1, + OPERAND_ftsf163ae_slot1, + OPERAND_ftsf164ae_slot1, + OPERAND_ftsf165ae_slot1, + OPERAND_ftsf166ae_slot1, + OPERAND_ftsf167ae_slot1, + OPERAND_ftsf168ae_slot1, + OPERAND_ftsf169ae_slot1, + OPERAND_ftsf170ae_slot1, + OPERAND_ftsf171ae_slot1, + OPERAND_ftsf172ae_slot1, + OPERAND_ftsf173ae_slot1, + OPERAND_ftsf174ae_slot1, + OPERAND_ftsf175ae_slot1, + OPERAND_ftsf176ae_slot1, + OPERAND_ftsf177ae_slot1, + OPERAND_ftsf178ae_slot1, + OPERAND_ftsf179ae_slot1, + OPERAND_ftsf180ae_slot1, + OPERAND_ftsf181ae_slot1, + OPERAND_ftsf182ae_slot1, + OPERAND_ftsf183ae_slot1, + OPERAND_ftsf184ae_slot1, + OPERAND_ftsf185ae_slot1, + OPERAND_ftsf186ae_slot1, + OPERAND_ftsf187ae_slot1, + OPERAND_ftsf188ae_slot1, + OPERAND_ftsf189ae_slot1, + OPERAND_ftsf190ae_slot1, + OPERAND_ftsf191ae_slot1, + OPERAND_ftsf192ae_slot1, + OPERAND_ftsf193ae_slot1, + OPERAND_ftsf194ae_slot1, + OPERAND_ftsf195ae_slot1, + OPERAND_ftsf196ae_slot1, + OPERAND_ftsf197ae_slot1, + OPERAND_ftsf198ae_slot1, + OPERAND_ftsf199ae_slot1, + OPERAND_ftsf200ae_slot1, + OPERAND_ftsf201ae_slot1, + OPERAND_ftsf202ae_slot1, + OPERAND_ftsf203ae_slot1, + OPERAND_ftsf204ae_slot1, + OPERAND_ftsf205ae_slot1, + OPERAND_ftsf206ae_slot1, + OPERAND_ftsf207ae_slot1, + OPERAND_ftsf208ae_slot1, + OPERAND_ftsf210ae_slot1, + OPERAND_ftsf333ae_slot1, + OPERAND_ftsf334ae_slot1, + OPERAND_ftsf335, + OPERAND_ftsf336ae_slot1, + OPERAND_ftsf337ae_slot1, + OPERAND_ftsf339ae_slot1, + OPERAND_ftsf340ae_slot1, + OPERAND_ftsf341ae_slot1, + OPERAND_ftsf342ae_slot1, + OPERAND_ftsf343ae_slot1, + OPERAND_ftsf344ae_slot1, + OPERAND_ftsf345ae_slot1, + OPERAND_ftsf347ae_slot1, + OPERAND_ftsf348ae_slot1, + OPERAND_ftsf349ae_slot1, + OPERAND_ftsf350ae_slot1, + OPERAND_ftsf351, + OPERAND_ftsf352ae_slot1, + OPERAND_ftsf354ae_slot1, + OPERAND_ftsf355ae_slot1, + OPERAND_ftsf356ae_slot1, + OPERAND_ftsf357ae_slot1, + OPERAND_ftsf358ae_slot1, + OPERAND_ftsf359ae_slot1, + OPERAND_op0_s4, + OPERAND_ftsf211ae_slot0, + OPERAND_ftsf212ae_slot0, + OPERAND_ftsf213ae_slot0, + OPERAND_ftsf214ae_slot0, + OPERAND_ftsf215ae_slot0, + OPERAND_ftsf217ae_slot0, + OPERAND_ftsf218ae_slot0, + OPERAND_ftsf219ae_slot0, + OPERAND_ftsf220ae_slot0, + OPERAND_ftsf221ae_slot0, + OPERAND_ftsf222ae_slot0, + OPERAND_ftsf223ae_slot0, + OPERAND_ftsf224ae_slot0, + OPERAND_ftsf225ae_slot0, + OPERAND_ftsf226ae_slot0, + OPERAND_ftsf227ae_slot0, + OPERAND_ftsf228ae_slot0, + OPERAND_ftsf229ae_slot0, + OPERAND_ftsf230ae_slot0, + OPERAND_ftsf231ae_slot0, + OPERAND_ftsf232ae_slot0, + OPERAND_ftsf233ae_slot0, + OPERAND_ftsf234ae_slot0, + OPERAND_ftsf235ae_slot0, + OPERAND_ftsf236ae_slot0, + OPERAND_ftsf237ae_slot0, + OPERAND_ftsf238ae_slot0, + OPERAND_ftsf239ae_slot0, + OPERAND_ftsf240ae_slot0, + OPERAND_ftsf241ae_slot0, + OPERAND_ftsf242ae_slot0, + OPERAND_ftsf243ae_slot0, + OPERAND_ftsf244ae_slot0, + OPERAND_ftsf245ae_slot0, + OPERAND_ftsf246ae_slot0, + OPERAND_ftsf247ae_slot0, + OPERAND_ftsf248ae_slot0, + OPERAND_ftsf249ae_slot0, + OPERAND_ftsf250ae_slot0, + OPERAND_ftsf251ae_slot0, + OPERAND_ftsf252ae_slot0, + OPERAND_ftsf253ae_slot0, + OPERAND_ftsf254ae_slot0, + OPERAND_ftsf255ae_slot0, + OPERAND_ftsf256ae_slot0, + OPERAND_ftsf257ae_slot0, + OPERAND_ftsf258ae_slot0, + OPERAND_ftsf259ae_slot0, + OPERAND_ftsf260ae_slot0, + OPERAND_ftsf261ae_slot0, + OPERAND_ftsf262ae_slot0, + OPERAND_ftsf263ae_slot0, + OPERAND_ftsf264ae_slot0, + OPERAND_ftsf265ae_slot0, + OPERAND_ftsf266ae_slot0, + OPERAND_ftsf267ae_slot0, + OPERAND_ftsf268ae_slot0, + OPERAND_ftsf269ae_slot0, + OPERAND_ftsf270ae_slot0, + OPERAND_ftsf271ae_slot0, + OPERAND_ftsf272ae_slot0, + OPERAND_ftsf273ae_slot0, + OPERAND_ftsf274ae_slot0, + OPERAND_ftsf275ae_slot0, + OPERAND_ftsf276ae_slot0, + OPERAND_ftsf277ae_slot0, + OPERAND_ftsf278ae_slot0, + OPERAND_ftsf279ae_slot0, + OPERAND_ftsf280, + OPERAND_ftsf281ae_slot0, + OPERAND_ftsf282ae_slot0, + OPERAND_ftsf284ae_slot0, + OPERAND_ftsf285ae_slot0, + OPERAND_ftsf287ae_slot0, + OPERAND_ftsf288, + OPERAND_ftsf289ae_slot0, + OPERAND_ftsf290ae_slot0, + OPERAND_ftsf291ae_slot0, + OPERAND_ftsf292ae_slot0, + OPERAND_ftsf293ae_slot0, + OPERAND_ftsf294ae_slot0, + OPERAND_ftsf295ae_slot0, + OPERAND_ftsf296ae_slot0, + OPERAND_ftsf297ae_slot0, + OPERAND_ftsf298ae_slot0, + OPERAND_ftsf300ae_slot0, + OPERAND_ftsf302ae_slot0, + OPERAND_ftsf304ae_slot0, + OPERAND_ftsf305ae_slot0, + OPERAND_ftsf306ae_slot0, + OPERAND_ftsf307ae_slot0, + OPERAND_ftsf308ae_slot0, + OPERAND_ftsf309, + OPERAND_ftsf310ae_slot0, + OPERAND_ftsf311ae_slot0, + OPERAND_ftsf312ae_slot0, + OPERAND_ftsf313ae_slot0, + OPERAND_ftsf314ae_slot0, + OPERAND_ftsf315, + OPERAND_ftsf316ae_slot0, + OPERAND_ftsf317ae_slot0, + OPERAND_ftsf319ae_slot0, + OPERAND_ftsf320ae_slot0, + OPERAND_ftsf322ae_slot0, + OPERAND_ftsf323ae_slot0, + OPERAND_ftsf324ae_slot0, + OPERAND_ftsf325ae_slot0, + OPERAND_ftsf326ae_slot0, + OPERAND_ftsf327ae_slot0, + OPERAND_ftsf328ae_slot0, + OPERAND_ftsf329ae_slot0, + OPERAND_ftsf360ae_slot0, + OPERAND_ftsf361ae_slot0, + OPERAND_ftsf362, + OPERAND_ftsf363ae_slot0, + OPERAND_ftsf364ae_slot0, + OPERAND_ftsf366ae_slot0, + OPERAND_ftsf368ae_slot0, + OPERAND_ftsf370ae_slot0, + OPERAND_ftsf373ae_slot0, + OPERAND_ftsf376ae_slot0, + OPERAND_ftsf378ae_slot0, + OPERAND_ftsf379ae_slot0, + OPERAND_ftsf382ae_slot0, + OPERAND_ftsf383ae_slot0, + OPERAND_ftsf384ae_slot0, + OPERAND_ftsf386ae_slot0, + OPERAND_ftsf387ae_slot0, + OPERAND_ftsf388ae_slot0, + OPERAND_ftsf389ae_slot0, + OPERAND_ae_mul32x24fld, + OPERAND_op0_s4_s4, + OPERAND_combined2c0b5f72_fld28, + OPERAND_combined2c0b5f72_fld37, + OPERAND_combined2c0b5f72_fld39, + OPERAND_combined2c0b5f72_fld40, + OPERAND_combined2c0b5f72_fld46, + OPERAND_combined2c0b5f72_fld47, + OPERAND_combined2c0b5f72_fld49, + OPERAND_combined2c0b5f72_fld50, + OPERAND_combined2c0b5f72_fld52, + OPERAND_combined2c0b5f72_fld121, + OPERAND_combined2c0b5f72_fld123, + OPERAND_combined2c0b5f72_fld127, + OPERAND_combined2c0b5f72_fld133ae_slot0, + OPERAND_combined2c0b5f72_fld134ae_slot0, + OPERAND_combined2c0b5f72_fld135ae_slot0, + OPERAND_combined2c0b5f72_fld136ae_slot0, + OPERAND_combined2c0b5f72_fld137ae_slot0, + OPERAND_combined2c0b5f72_fld138ae_slot0, + OPERAND_combined2c0b5f72_fld139ae_slot0, + OPERAND_combined2c0b5f72_fld140ae_slot0, + OPERAND_combined2c0b5f72_fld141ae_slot0, + OPERAND_combined2c0b5f72_fld142ae_slot0, + OPERAND_combined2c0b5f72_fld143ae_slot0, + OPERAND_combined2c0b5f72_fld144ae_slot0, + OPERAND_combined2c0b5f72_fld145ae_slot0, + OPERAND_combined2c0b5f72_fld146ae_slot0, + OPERAND_combined2c0b5f72_fld148ae_slot0, + OPERAND_combined2c0b5f72_fld149ae_slot0, + OPERAND_op0_s4_s4_s4, + OPERAND_combined1e9fefee_fld96, + OPERAND_combined1e9fefee_fld98, + OPERAND_combined1e9fefee_fld106ae_slot0, + OPERAND_combined1e9fefee_fld107ae_slot0, + OPERAND_combined1e9fefee_fld108ae_slot0, + OPERAND_combined1e9fefee_fld109ae_slot0, + OPERAND_op0_s3_s3, + OPERAND_combined2c0b5f72_fld19, + OPERAND_combined2c0b5f72_fld22, + OPERAND_combined2c0b5f72_fld24, + OPERAND_combined2c0b5f72_fld65, + OPERAND_combined2c0b5f72_fld66, + OPERAND_combined2c0b5f72_fld68, + OPERAND_combined2c0b5f72_fld69, + OPERAND_combined2c0b5f72_fld74, + OPERAND_combined2c0b5f72_fld79, + OPERAND_combined2c0b5f72_fld88, + OPERAND_combined2c0b5f72_fld90, + OPERAND_combined2c0b5f72_fld91, + OPERAND_combined2c0b5f72_fld131ae_slot1, + OPERAND_combined2c0b5f72_fld132ae_slot1, + OPERAND_combined2c0b5f72_fld147ae_slot1, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_243_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'i' }, + { { STATE_INSTPGSZID5 }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'o' }, + { { STATE_INSTPGSZID5 }, 'o' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'm' }, + { { STATE_INSTPGSZID5 }, 'm' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'i' }, + { { STATE_DATAPGSZID5 }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'o' }, + { { STATE_DATAPGSZID5 }, 'o' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'm' }, + { { STATE_DATAPGSZID5 }, 'm' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { + { { OPERAND_ps }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { + { { OPERAND_qr1_w }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { + { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { + { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_cvt_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_cvt_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { + { { OPERAND_alupppb_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { + { { OPERAND_alupppb_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bt }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bt }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_243_args, + 2, Iclass_xt_iclass_rsr_243_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 3, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 3, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_sd_no_args, + 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_sd_no_args, + 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_overflow_args, + 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_overflow_args, + 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_sar_args, + 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_sar_args, + 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_bitptr_args, + 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_bitptr_args, + 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_bitsused_args, + 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_bitsused_args, + 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_tablesize_args, + 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_tablesize_args, + 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_first_ts_args, + 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_first_ts_args, + 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, + 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, + 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_searchdone_args, + 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_searchdone_args, + 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_i_args, + 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_iu_args, + 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_x_args, + 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_xu_args, + 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_i_args, + 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_iu_args, + 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_x_args, + 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_xu_args, + 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_i_args, + 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_iu_args, + 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_x_args, + 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_xu_args, + 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_i_args, + 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_iu_args, + 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_x_args, + 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_xu_args, + 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_i_args, + 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_iu_args, + 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_x_args, + 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_xu_args, + 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_i_args, + 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_iu_args, + 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_x_args, + 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_xu_args, + 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_i_args, + 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_iu_args, + 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_x_args, + 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_xu_args, + 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2s_i_args, + 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2s_iu_args, + 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2s_x_args, + 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2s_xu_args, + 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2f_i_args, + 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2f_iu_args, + 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2f_x_args, + 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24x2f_xu_args, + 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16f_l_i_args, + 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16f_l_iu_args, + 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16f_l_x_args, + 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16f_l_xu_args, + 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24s_l_i_args, + 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24s_l_iu_args, + 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24s_l_x_args, + 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24s_l_xu_args, + 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24f_l_i_args, + 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24f_l_iu_args, + 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24f_l_x_args, + 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp24f_l_xu_args, + 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq56_i_args, + 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq56_iu_args, + 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq56_x_args, + 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq56_xu_args, + 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq32f_i_args, + 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq32f_iu_args, + 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq32f_x_args, + 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lq32f_xu_args, + 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq56s_i_args, + 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq56s_iu_args, + 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq56s_x_args, + 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq56s_xu_args, + 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq32f_i_args, + 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq32f_iu_args, + 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq32f_x_args, + 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sq32f_xu_args, + 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_zerop48_args, + 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_movp48_args, + 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_selp24_ll_args, + 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_selp24_lh_args, + 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_selp24_hl_args, + 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_selp24_hh_args, + 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_movtp24x2_args, + 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_movfp24x2_args, + 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_movtp48_args, + 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_movfp48_args, + 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_movpa24x2_args, + 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_truncp24a32x2_args, + 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_cvta32p24_l_args, + 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_cvta32p24_h_args, + 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, + 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, + 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, + 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, + 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_truncp24q48x2_args, + 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_truncp16_args, + 1, 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Iclass_ae_iclass_mulsq32sp16s_l_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsq32sp16s_h_args, + 1, Iclass_ae_iclass_mulsq32sp16s_h_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsq32sp16u_l_args, + 1, Iclass_ae_iclass_mulsq32sp16u_l_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsq32sp16u_h_args, + 1, Iclass_ae_iclass_mulsq32sp16u_h_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaaq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, + 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, + 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, + 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, + 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, + 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, + { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, + 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_sha32_args, + 0, 0, 0, 0 }, + { 3, Iclass_ae_iclass_vldl32t_args, + 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vldl16t_args, + 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vldl16c_args, + 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vldsht_args, + 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_lb_args, + 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_lbi_args, + 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lbk_args, + 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lbki_args, + 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_db_args, + 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_dbi_args, + 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vlel32t_args, + 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vlel16t_args, + 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_sb_args, + 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sbi_args, + 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vles16c_args, + 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_sbf_args, + 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SLAASQ56S_args, + 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_icls_AE_MINABSSP24S_args, + 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_MAXABSSP24S_args, + 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_MINABSSQ56S_args, + 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_MAXABSSQ56S_args, + 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP24X2_C_args, + 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP24X2S_C_args, + 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP24X2F_C_args, + 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP24X2F_C_args, + 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP16X2F_C_args, + 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP16X2F_C_args, + 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP24_C_args, + 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP24S_L_C_args, + 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP24F_C_args, + 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP24F_L_C_args, + 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LP16F_C_args, + 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SP16F_L_C_args, + 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LQ56_C_args, + 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SQ56S_C_args, + 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_LQ32F_C_args, + 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, + { 3, Iclass_icls_AE_SQ32F_C_args, + 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_243, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_wsr_ptevaddr, + ICLASS_xt_iclass_rsr_ptevaddr, + ICLASS_xt_iclass_xsr_ptevaddr, + ICLASS_xt_iclass_rsr_rasid, + ICLASS_xt_iclass_wsr_rasid, + ICLASS_xt_iclass_xsr_rasid, + ICLASS_xt_iclass_rsr_itlbcfg, + ICLASS_xt_iclass_wsr_itlbcfg, + ICLASS_xt_iclass_xsr_itlbcfg, + ICLASS_xt_iclass_rsr_dtlbcfg, + ICLASS_xt_iclass_wsr_dtlbcfg, + ICLASS_xt_iclass_xsr_dtlbcfg, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_ldpte, + ICLASS_xt_iclass_hwwitlba, + ICLASS_xt_iclass_hwwdtlba, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_sd_no, + ICLASS_wur_ae_sd_no, + ICLASS_ae_iclass_rur_ae_overflow, + ICLASS_ae_iclass_wur_ae_overflow, + ICLASS_ae_iclass_rur_ae_sar, + ICLASS_ae_iclass_wur_ae_sar, + ICLASS_ae_iclass_rur_ae_bitptr, + ICLASS_ae_iclass_wur_ae_bitptr, + ICLASS_ae_iclass_rur_ae_bitsused, + ICLASS_ae_iclass_wur_ae_bitsused, + ICLASS_ae_iclass_rur_ae_tablesize, + ICLASS_ae_iclass_wur_ae_tablesize, + ICLASS_ae_iclass_rur_ae_first_ts, + ICLASS_ae_iclass_wur_ae_first_ts, + ICLASS_ae_iclass_rur_ae_nextoffset, + ICLASS_ae_iclass_wur_ae_nextoffset, + ICLASS_ae_iclass_rur_ae_searchdone, + ICLASS_ae_iclass_wur_ae_searchdone, + ICLASS_ae_iclass_lp16f_i, + ICLASS_ae_iclass_lp16f_iu, + ICLASS_ae_iclass_lp16f_x, + ICLASS_ae_iclass_lp16f_xu, + ICLASS_ae_iclass_lp24_i, + ICLASS_ae_iclass_lp24_iu, + ICLASS_ae_iclass_lp24_x, + ICLASS_ae_iclass_lp24_xu, + ICLASS_ae_iclass_lp24f_i, + ICLASS_ae_iclass_lp24f_iu, + ICLASS_ae_iclass_lp24f_x, + ICLASS_ae_iclass_lp24f_xu, + ICLASS_ae_iclass_lp16x2f_i, + ICLASS_ae_iclass_lp16x2f_iu, + ICLASS_ae_iclass_lp16x2f_x, + ICLASS_ae_iclass_lp16x2f_xu, + ICLASS_ae_iclass_lp24x2f_i, + ICLASS_ae_iclass_lp24x2f_iu, + ICLASS_ae_iclass_lp24x2f_x, + ICLASS_ae_iclass_lp24x2f_xu, + ICLASS_ae_iclass_lp24x2_i, + ICLASS_ae_iclass_lp24x2_iu, + ICLASS_ae_iclass_lp24x2_x, + ICLASS_ae_iclass_lp24x2_xu, + ICLASS_ae_iclass_sp16x2f_i, + ICLASS_ae_iclass_sp16x2f_iu, + ICLASS_ae_iclass_sp16x2f_x, + ICLASS_ae_iclass_sp16x2f_xu, + ICLASS_ae_iclass_sp24x2s_i, + ICLASS_ae_iclass_sp24x2s_iu, + ICLASS_ae_iclass_sp24x2s_x, + ICLASS_ae_iclass_sp24x2s_xu, + ICLASS_ae_iclass_sp24x2f_i, + ICLASS_ae_iclass_sp24x2f_iu, + ICLASS_ae_iclass_sp24x2f_x, + ICLASS_ae_iclass_sp24x2f_xu, + ICLASS_ae_iclass_sp16f_l_i, + ICLASS_ae_iclass_sp16f_l_iu, + ICLASS_ae_iclass_sp16f_l_x, + ICLASS_ae_iclass_sp16f_l_xu, + ICLASS_ae_iclass_sp24s_l_i, + ICLASS_ae_iclass_sp24s_l_iu, + ICLASS_ae_iclass_sp24s_l_x, + ICLASS_ae_iclass_sp24s_l_xu, + ICLASS_ae_iclass_sp24f_l_i, + ICLASS_ae_iclass_sp24f_l_iu, + ICLASS_ae_iclass_sp24f_l_x, + ICLASS_ae_iclass_sp24f_l_xu, + ICLASS_ae_iclass_lq56_i, + ICLASS_ae_iclass_lq56_iu, + ICLASS_ae_iclass_lq56_x, + ICLASS_ae_iclass_lq56_xu, + ICLASS_ae_iclass_lq32f_i, + ICLASS_ae_iclass_lq32f_iu, + ICLASS_ae_iclass_lq32f_x, + ICLASS_ae_iclass_lq32f_xu, + ICLASS_ae_iclass_sq56s_i, + ICLASS_ae_iclass_sq56s_iu, + ICLASS_ae_iclass_sq56s_x, + ICLASS_ae_iclass_sq56s_xu, + ICLASS_ae_iclass_sq32f_i, + ICLASS_ae_iclass_sq32f_iu, + ICLASS_ae_iclass_sq32f_x, + ICLASS_ae_iclass_sq32f_xu, + ICLASS_ae_iclass_zerop48, + ICLASS_ae_iclass_movp48, + ICLASS_ae_iclass_selp24_ll, + ICLASS_ae_iclass_selp24_lh, + ICLASS_ae_iclass_selp24_hl, + ICLASS_ae_iclass_selp24_hh, + ICLASS_ae_iclass_movtp24x2, + ICLASS_ae_iclass_movfp24x2, + ICLASS_ae_iclass_movtp48, + ICLASS_ae_iclass_movfp48, + ICLASS_ae_iclass_movpa24x2, + ICLASS_ae_iclass_truncp24a32x2, + ICLASS_ae_iclass_cvta32p24_l, + ICLASS_ae_iclass_cvta32p24_h, + ICLASS_ae_iclass_cvtp24a16x2_ll, + ICLASS_ae_iclass_cvtp24a16x2_lh, + ICLASS_ae_iclass_cvtp24a16x2_hl, + ICLASS_ae_iclass_cvtp24a16x2_hh, + ICLASS_ae_iclass_truncp24q48x2, + ICLASS_ae_iclass_truncp16, + ICLASS_ae_iclass_roundsp24q48sym, + ICLASS_ae_iclass_roundsp24q48asym, + ICLASS_ae_iclass_roundsp16q48sym, + ICLASS_ae_iclass_roundsp16q48asym, + ICLASS_ae_iclass_roundsp16sym, + ICLASS_ae_iclass_roundsp16asym, + ICLASS_ae_iclass_zeroq56, + ICLASS_ae_iclass_movq56, + ICLASS_ae_iclass_movtq56, + ICLASS_ae_iclass_movfq56, + ICLASS_ae_iclass_cvtq48a32s, + ICLASS_ae_iclass_cvtq48p24s_l, + ICLASS_ae_iclass_cvtq48p24s_h, + ICLASS_ae_iclass_satq48s, + ICLASS_ae_iclass_truncq32, + ICLASS_ae_iclass_roundsq32sym, + ICLASS_ae_iclass_roundsq32asym, + ICLASS_ae_iclass_trunca32q48, + ICLASS_ae_iclass_movap24s_l, + ICLASS_ae_iclass_movap24s_h, + ICLASS_ae_iclass_trunca16p24s_l, + ICLASS_ae_iclass_trunca16p24s_h, + ICLASS_ae_iclass_addp24, + ICLASS_ae_iclass_subp24, + ICLASS_ae_iclass_negp24, + ICLASS_ae_iclass_absp24, + ICLASS_ae_iclass_maxp24s, + ICLASS_ae_iclass_minp24s, + ICLASS_ae_iclass_maxbp24s, + ICLASS_ae_iclass_minbp24s, + ICLASS_ae_iclass_addsp24s, + ICLASS_ae_iclass_subsp24s, + ICLASS_ae_iclass_negsp24s, + ICLASS_ae_iclass_abssp24s, + ICLASS_ae_iclass_andp48, + ICLASS_ae_iclass_nandp48, + ICLASS_ae_iclass_orp48, + ICLASS_ae_iclass_xorp48, + ICLASS_ae_iclass_ltp24s, + ICLASS_ae_iclass_lep24s, + ICLASS_ae_iclass_eqp24, + ICLASS_ae_iclass_addq56, + ICLASS_ae_iclass_subq56, + ICLASS_ae_iclass_negq56, + ICLASS_ae_iclass_absq56, + ICLASS_ae_iclass_maxq56s, + ICLASS_ae_iclass_minq56s, + ICLASS_ae_iclass_maxbq56s, + ICLASS_ae_iclass_minbq56s, + ICLASS_ae_iclass_addsq56s, + ICLASS_ae_iclass_subsq56s, + ICLASS_ae_iclass_negsq56s, + ICLASS_ae_iclass_abssq56s, + ICLASS_ae_iclass_andq56, + ICLASS_ae_iclass_nandq56, + ICLASS_ae_iclass_orq56, + ICLASS_ae_iclass_xorq56, + ICLASS_ae_iclass_sllip24, + ICLASS_ae_iclass_srlip24, + ICLASS_ae_iclass_sraip24, + ICLASS_ae_iclass_sllsp24, + ICLASS_ae_iclass_srlsp24, + ICLASS_ae_iclass_srasp24, + ICLASS_ae_iclass_sllisp24s, + ICLASS_ae_iclass_sllssp24s, + ICLASS_ae_iclass_slliq56, + ICLASS_ae_iclass_srliq56, + ICLASS_ae_iclass_sraiq56, + ICLASS_ae_iclass_sllsq56, + ICLASS_ae_iclass_srlsq56, + ICLASS_ae_iclass_srasq56, + ICLASS_ae_iclass_sllaq56, + ICLASS_ae_iclass_srlaq56, + ICLASS_ae_iclass_sraaq56, + ICLASS_ae_iclass_sllisq56s, + ICLASS_ae_iclass_sllssq56s, + ICLASS_ae_iclass_sllasq56s, + ICLASS_ae_iclass_ltq56s, + ICLASS_ae_iclass_leq56s, + ICLASS_ae_iclass_eqq56, + ICLASS_ae_iclass_nsaq56s, + ICLASS_ae_iclass_mulsrfq32sp24s_h, + ICLASS_ae_iclass_mulsrfq32sp24s_l, + ICLASS_ae_iclass_mularfq32sp24s_h, + ICLASS_ae_iclass_mularfq32sp24s_l, + ICLASS_ae_iclass_mulrfq32sp24s_h, + ICLASS_ae_iclass_mulrfq32sp24s_l, + ICLASS_ae_iclass_mulsfq32sp24s_h, + ICLASS_ae_iclass_mulsfq32sp24s_l, + ICLASS_ae_iclass_mulafq32sp24s_h, + ICLASS_ae_iclass_mulafq32sp24s_l, + ICLASS_ae_iclass_mulfq32sp24s_h, + ICLASS_ae_iclass_mulfq32sp24s_l, + ICLASS_ae_iclass_mulfs32p16s_ll, + ICLASS_ae_iclass_mulfp24s_ll, + ICLASS_ae_iclass_mulp24s_ll, + ICLASS_ae_iclass_mulfs32p16s_lh, + ICLASS_ae_iclass_mulfp24s_lh, + ICLASS_ae_iclass_mulp24s_lh, + ICLASS_ae_iclass_mulfs32p16s_hl, + ICLASS_ae_iclass_mulfp24s_hl, + ICLASS_ae_iclass_mulp24s_hl, + ICLASS_ae_iclass_mulfs32p16s_hh, + ICLASS_ae_iclass_mulfp24s_hh, + ICLASS_ae_iclass_mulp24s_hh, + ICLASS_ae_iclass_mulafs32p16s_ll, + ICLASS_ae_iclass_mulafp24s_ll, + ICLASS_ae_iclass_mulap24s_ll, + ICLASS_ae_iclass_mulafs32p16s_lh, + ICLASS_ae_iclass_mulafp24s_lh, + ICLASS_ae_iclass_mulap24s_lh, + ICLASS_ae_iclass_mulafs32p16s_hl, + ICLASS_ae_iclass_mulafp24s_hl, + ICLASS_ae_iclass_mulap24s_hl, + ICLASS_ae_iclass_mulafs32p16s_hh, + ICLASS_ae_iclass_mulafp24s_hh, + ICLASS_ae_iclass_mulap24s_hh, + ICLASS_ae_iclass_mulsfs32p16s_ll, + ICLASS_ae_iclass_mulsfp24s_ll, + ICLASS_ae_iclass_mulsp24s_ll, + ICLASS_ae_iclass_mulsfs32p16s_lh, + ICLASS_ae_iclass_mulsfp24s_lh, + ICLASS_ae_iclass_mulsp24s_lh, + ICLASS_ae_iclass_mulsfs32p16s_hl, + ICLASS_ae_iclass_mulsfp24s_hl, + ICLASS_ae_iclass_mulsp24s_hl, + ICLASS_ae_iclass_mulsfs32p16s_hh, + ICLASS_ae_iclass_mulsfp24s_hh, + ICLASS_ae_iclass_mulsp24s_hh, + ICLASS_ae_iclass_mulafs56p24s_ll, + ICLASS_ae_iclass_mulas56p24s_ll, + ICLASS_ae_iclass_mulafs56p24s_lh, + ICLASS_ae_iclass_mulas56p24s_lh, + ICLASS_ae_iclass_mulafs56p24s_hl, + ICLASS_ae_iclass_mulas56p24s_hl, + ICLASS_ae_iclass_mulafs56p24s_hh, + ICLASS_ae_iclass_mulas56p24s_hh, + ICLASS_ae_iclass_mulsfs56p24s_ll, + ICLASS_ae_iclass_mulss56p24s_ll, + ICLASS_ae_iclass_mulsfs56p24s_lh, + ICLASS_ae_iclass_mulss56p24s_lh, + ICLASS_ae_iclass_mulsfs56p24s_hl, + ICLASS_ae_iclass_mulss56p24s_hl, + ICLASS_ae_iclass_mulsfs56p24s_hh, + ICLASS_ae_iclass_mulss56p24s_hh, + ICLASS_ae_iclass_mulfq32sp16s_l, + ICLASS_ae_iclass_mulfq32sp16s_h, + ICLASS_ae_iclass_mulfq32sp16u_l, + ICLASS_ae_iclass_mulfq32sp16u_h, + ICLASS_ae_iclass_mulq32sp16s_l, + ICLASS_ae_iclass_mulq32sp16s_h, + ICLASS_ae_iclass_mulq32sp16u_l, + ICLASS_ae_iclass_mulq32sp16u_h, + ICLASS_ae_iclass_mulafq32sp16s_l, + ICLASS_ae_iclass_mulafq32sp16s_h, + ICLASS_ae_iclass_mulafq32sp16u_l, + ICLASS_ae_iclass_mulafq32sp16u_h, + ICLASS_ae_iclass_mulaq32sp16s_l, + ICLASS_ae_iclass_mulaq32sp16s_h, + ICLASS_ae_iclass_mulaq32sp16u_l, + ICLASS_ae_iclass_mulaq32sp16u_h, + ICLASS_ae_iclass_mulsfq32sp16s_l, + ICLASS_ae_iclass_mulsfq32sp16s_h, + ICLASS_ae_iclass_mulsfq32sp16u_l, + ICLASS_ae_iclass_mulsfq32sp16u_h, + ICLASS_ae_iclass_mulsq32sp16s_l, + ICLASS_ae_iclass_mulsq32sp16s_h, + ICLASS_ae_iclass_mulsq32sp16u_l, + ICLASS_ae_iclass_mulsq32sp16u_h, + ICLASS_ae_iclass_mulzaaq32sp16s_ll, + ICLASS_ae_iclass_mulzaafq32sp16s_ll, + ICLASS_ae_iclass_mulzaaq32sp16u_ll, + ICLASS_ae_iclass_mulzaafq32sp16u_ll, + ICLASS_ae_iclass_mulzaaq32sp16s_hh, + ICLASS_ae_iclass_mulzaafq32sp16s_hh, + ICLASS_ae_iclass_mulzaaq32sp16u_hh, + ICLASS_ae_iclass_mulzaafq32sp16u_hh, + ICLASS_ae_iclass_mulzaaq32sp16s_lh, + ICLASS_ae_iclass_mulzaafq32sp16s_lh, + ICLASS_ae_iclass_mulzaaq32sp16u_lh, + ICLASS_ae_iclass_mulzaafq32sp16u_lh, + ICLASS_ae_iclass_mulzasq32sp16s_ll, + ICLASS_ae_iclass_mulzasfq32sp16s_ll, + ICLASS_ae_iclass_mulzasq32sp16u_ll, + ICLASS_ae_iclass_mulzasfq32sp16u_ll, + ICLASS_ae_iclass_mulzasq32sp16s_hh, + ICLASS_ae_iclass_mulzasfq32sp16s_hh, + ICLASS_ae_iclass_mulzasq32sp16u_hh, + ICLASS_ae_iclass_mulzasfq32sp16u_hh, + ICLASS_ae_iclass_mulzasq32sp16s_lh, + ICLASS_ae_iclass_mulzasfq32sp16s_lh, + ICLASS_ae_iclass_mulzasq32sp16u_lh, + ICLASS_ae_iclass_mulzasfq32sp16u_lh, + ICLASS_ae_iclass_mulzsaq32sp16s_ll, + ICLASS_ae_iclass_mulzsafq32sp16s_ll, + ICLASS_ae_iclass_mulzsaq32sp16u_ll, + ICLASS_ae_iclass_mulzsafq32sp16u_ll, + ICLASS_ae_iclass_mulzsaq32sp16s_hh, + ICLASS_ae_iclass_mulzsafq32sp16s_hh, + ICLASS_ae_iclass_mulzsaq32sp16u_hh, + ICLASS_ae_iclass_mulzsafq32sp16u_hh, + ICLASS_ae_iclass_mulzsaq32sp16s_lh, + ICLASS_ae_iclass_mulzsafq32sp16s_lh, + ICLASS_ae_iclass_mulzsaq32sp16u_lh, + ICLASS_ae_iclass_mulzsafq32sp16u_lh, + ICLASS_ae_iclass_mulzssq32sp16s_ll, + ICLASS_ae_iclass_mulzssfq32sp16s_ll, + ICLASS_ae_iclass_mulzssq32sp16u_ll, + ICLASS_ae_iclass_mulzssfq32sp16u_ll, + ICLASS_ae_iclass_mulzssq32sp16s_hh, + ICLASS_ae_iclass_mulzssfq32sp16s_hh, + ICLASS_ae_iclass_mulzssq32sp16u_hh, + ICLASS_ae_iclass_mulzssfq32sp16u_hh, + ICLASS_ae_iclass_mulzssq32sp16s_lh, + ICLASS_ae_iclass_mulzssfq32sp16s_lh, + ICLASS_ae_iclass_mulzssq32sp16u_lh, + ICLASS_ae_iclass_mulzssfq32sp16u_lh, + ICLASS_ae_iclass_mulzaafp24s_hh_ll, + ICLASS_ae_iclass_mulzaap24s_hh_ll, + ICLASS_ae_iclass_mulzaafp24s_hl_lh, + ICLASS_ae_iclass_mulzaap24s_hl_lh, + ICLASS_ae_iclass_mulzasfp24s_hh_ll, + ICLASS_ae_iclass_mulzasp24s_hh_ll, + ICLASS_ae_iclass_mulzasfp24s_hl_lh, + ICLASS_ae_iclass_mulzasp24s_hl_lh, + ICLASS_ae_iclass_mulzsafp24s_hh_ll, + ICLASS_ae_iclass_mulzsap24s_hh_ll, + ICLASS_ae_iclass_mulzsafp24s_hl_lh, + ICLASS_ae_iclass_mulzsap24s_hl_lh, + ICLASS_ae_iclass_mulzssfp24s_hh_ll, + ICLASS_ae_iclass_mulzssp24s_hh_ll, + ICLASS_ae_iclass_mulzssfp24s_hl_lh, + ICLASS_ae_iclass_mulzssp24s_hl_lh, + ICLASS_ae_iclass_mulaafp24s_hh_ll, + ICLASS_ae_iclass_mulaap24s_hh_ll, + ICLASS_ae_iclass_mulaafp24s_hl_lh, + ICLASS_ae_iclass_mulaap24s_hl_lh, + ICLASS_ae_iclass_mulasfp24s_hh_ll, + ICLASS_ae_iclass_mulasp24s_hh_ll, + ICLASS_ae_iclass_mulasfp24s_hl_lh, + ICLASS_ae_iclass_mulasp24s_hl_lh, + ICLASS_ae_iclass_mulsafp24s_hh_ll, + ICLASS_ae_iclass_mulsap24s_hh_ll, + ICLASS_ae_iclass_mulsafp24s_hl_lh, + ICLASS_ae_iclass_mulsap24s_hl_lh, + ICLASS_ae_iclass_mulssfp24s_hh_ll, + ICLASS_ae_iclass_mulssp24s_hh_ll, + ICLASS_ae_iclass_mulssfp24s_hl_lh, + ICLASS_ae_iclass_mulssp24s_hl_lh, + ICLASS_ae_iclass_sha32, + ICLASS_ae_iclass_vldl32t, + ICLASS_ae_iclass_vldl16t, + ICLASS_ae_iclass_vldl16c, + ICLASS_ae_iclass_vldsht, + ICLASS_ae_iclass_lb, + ICLASS_ae_iclass_lbi, + ICLASS_ae_iclass_lbk, + ICLASS_ae_iclass_lbki, + ICLASS_ae_iclass_db, + ICLASS_ae_iclass_dbi, + ICLASS_ae_iclass_vlel32t, + ICLASS_ae_iclass_vlel16t, + ICLASS_ae_iclass_sb, + ICLASS_ae_iclass_sbi, + ICLASS_ae_iclass_vles16c, + ICLASS_ae_iclass_sbf, + ICLASS_icls_AE_SLAASQ56S, + ICLASS_icls_AE_ADDBRBA32, + ICLASS_icls_AE_MINABSSP24S, + ICLASS_icls_AE_MAXABSSP24S, + ICLASS_icls_AE_MINABSSQ56S, + ICLASS_icls_AE_MAXABSSQ56S, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_icls_AE_LP24X2_C, + ICLASS_icls_AE_SP24X2S_C, + ICLASS_icls_AE_LP24X2F_C, + ICLASS_icls_AE_SP24X2F_C, + ICLASS_icls_AE_LP16X2F_C, + ICLASS_icls_AE_SP16X2F_C, + ICLASS_icls_AE_LP24_C, + ICLASS_icls_AE_SP24S_L_C, + ICLASS_icls_AE_LP24F_C, + ICLASS_icls_AE_SP24F_L_C, + ICLASS_icls_AE_LP16F_C, + ICLASS_icls_AE_SP16F_L_C, + ICLASS_icls_AE_LQ56_C, + ICLASS_icls_AE_SQ56S_C, + ICLASS_icls_AE_LQ32F_C, + ICLASS_icls_AE_SQ32F_C, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80200; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10f; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4830; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4831; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4816; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4930; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4931; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4916; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc00; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60f; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30f; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00f; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e03e; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe73f; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200c00; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d00; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb81; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1381; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2381; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b81; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d01; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf81; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d81; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b81; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2501; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f01; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690000; +} + +static void +Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800003; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800003; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000003; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700600; +} + +static void +Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700e00; +} + +static void +Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000003; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000003; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700100; +} + +static void +Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300002; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700900; +} + +static void +Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700a00; +} + +static void +Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600002; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700200; +} + +static void +Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680002; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700b00; +} + +static void +Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380002; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700300; +} + +static void +Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700002; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700800; +} + +static void +Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500002; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700400; +} + +static void +Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180002; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700c00; +} + +static void +Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780002; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700500; +} + +static void +Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580002; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700d00; +} + +static void +Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280002; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650000; +} + +static void +Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670000; +} + +static void +Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x281; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660000; +} + +static void +Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983d01; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200100; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200004; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200900; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100004; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200200; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0800; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0900; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0a00; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200a00; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x301; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7381; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd01; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x701; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x581; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed81; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1006; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed81; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36001; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb83d01; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200500; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200600; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300004; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200400; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983d81; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4183d01; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2183d01; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x304; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1183d01; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e501; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2806f81; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4781; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7ed81; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ed81; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x381; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd81; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20200; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x331; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x316; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6130; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6131; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6116; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x531; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x516; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb030; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb031; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd030; +} + +static void +Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf330; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe630; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe631; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe616; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb130; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb131; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb116; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd130; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd131; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd116; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb230; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb231; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb216; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd230; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd231; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd216; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb330; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb331; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb316; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd330; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd331; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd316; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb430; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb431; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb416; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd430; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd431; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd416; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb530; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb531; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb516; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd530; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd531; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd516; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb630; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb631; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb616; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd630; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd631; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd616; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb730; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb731; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb716; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd730; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd731; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd716; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc230; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc231; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc216; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc330; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc331; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc316; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc430; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc431; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc416; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc530; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc531; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc516; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc630; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc631; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc616; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc730; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc731; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc716; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee30; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee31; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee16; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc030; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc031; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc016; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe830; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe831; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe816; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf430; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf431; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf416; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf530; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf531; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf516; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb30; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe730; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe731; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe716; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400047; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400057; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400067; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400077; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400007; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400017; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400027; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400037; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400043; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400053; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400063; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400073; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400046; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400056; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400066; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400076; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400042; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400052; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400062; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400072; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400087; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400097; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a7; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b7; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c7; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d7; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000e7; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000f7; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400083; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400093; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a3; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b3; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c3; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d3; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000e3; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000f3; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400086; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400096; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a6; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b6; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c6; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d6; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000e6; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000f6; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400082; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400092; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a2; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b2; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c2; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d2; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000e2; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000f2; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400085; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400084; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400095; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400094; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a5; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a4; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b5; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b4; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400081; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400080; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400091; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400090; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a1; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a0; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b1; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b0; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400009; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400008; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2031; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2016; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2130; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2131; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2116; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2230; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2231; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2216; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2330; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2331; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2316; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1030; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1016; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1131; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1116; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe230; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe231; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe331; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe430; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe431; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe416; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20f; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9030; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9031; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9016; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa031; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa016; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9130; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9131; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9116; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa130; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa131; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa116; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8031; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8016; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8131; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8116; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6030; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6031; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6016; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe930; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe931; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe916; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec30; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec31; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec16; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed30; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed31; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed16; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6830; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6831; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0700; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0700; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1f; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e1f; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5931; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5381; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b81; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4581; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x781; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f81; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96501; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e501; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6501; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6501; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800003; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0100; +} + +static void +Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000003; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b81; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1501; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x431; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x416; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea30; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea31; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea16; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf030; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf031; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf016; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf130; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf131; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf116; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf230; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf231; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf216; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0700; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0700; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0700; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0720; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0730; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0700; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31f; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240700; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250700; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2807f0; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280740; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280750; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260700; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270700; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200700; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210700; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220700; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230700; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280700; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280720; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280730; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91f; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2830; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2831; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2816; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5331; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5330; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5316; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a30; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a31; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a16; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b30; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b31; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b16; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c30; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c31; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c16; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc05; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd05; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb05; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf05; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe05; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x405; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x305; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x705; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x605; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe030; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe031; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe016; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b81; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b81; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3381; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b81; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6381; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe04; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf04; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4701; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200b00; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200f00; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200e00; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc31; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc16; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6330; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6331; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6316; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x604; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x704; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03e; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03f; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f03e; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13f; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f03e; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf23f; +} + +static void +Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f03e; +} + +static void +Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33f; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40809c; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000ac; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40909c; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001ac; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a09c; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002ac; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b09c; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003ac; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c09c; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4004ac; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40d09c; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4005ac; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e09c; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4006ac; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f09c; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007ac; +} + +static void +Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81581; +} + +static void +Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005a; +} + +static void +Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1781; +} + +static void +Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009a; +} + +static void +Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81701; +} + +static void +Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000ca; +} + +static void +Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81781; +} + +static void +Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000fa; +} + +static void +Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d81; +} + +static void +Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40085a; +} + +static void +Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f01; +} + +static void +Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40089a; +} + +static void +Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81f81; +} + +static void +Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008ca; +} + +static void +Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5581; +} + +static void +Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008fa; +} + +static void +Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5701; +} + +static void +Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006a; +} + +static void +Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d01; +} + +static void +Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000aa; +} + +static void +Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85501; +} + +static void +Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000da; +} + +static void +Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5781; +} + +static void +Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000b; +} + +static void +Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81; +} + +static void +Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40086a; +} + +static void +Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f01; +} + +static void +Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008aa; +} + +static void +Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d01; +} + +static void +Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008da; +} + +static void +Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f81; +} + +static void +Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080b; +} + +static void +Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85701; +} + +static void +Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007a; +} + +static void +Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85d01; +} + +static void +Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000ba; +} + +static void +Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85781; +} + +static void +Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000ea; +} + +static void +Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85d81; +} + +static void +Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001b; +} + +static void +Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d81; +} + +static void +Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40087a; +} + +static void +Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f01; +} + +static void +Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008ba; +} + +static void +Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f81; +} + +static void +Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008ea; +} + +static void +Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85581; +} + +static void +Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40081b; +} + +static void +Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3501; +} + +static void +Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002b; +} + +static void +Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6501; +} + +static void +Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005b; +} + +static void +Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82581; +} + +static void +Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008b; +} + +static void +Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781; +} + +static void +Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000bb; +} + +static void +Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83501; +} + +static void +Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40082b; +} + +static void +Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3781; +} + +static void +Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40085b; +} + +static void +Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d81; +} + +static void +Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088b; +} + +static void +Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f01; +} + +static void +Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008bb; +} + +static void +Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82f81; +} + +static void +Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40003b; +} + +static void +Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3581; +} + +static void +Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006b; +} + +static void +Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3701; +} + +static void +Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009b; +} + +static void +Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d01; +} + +static void +Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000cb; +} + +static void +Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85f81; +} + +static void +Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40083b; +} + +static void +Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2581; +} + +static void +Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40086b; +} + +static void +Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2701; +} + +static void +Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40089b; +} + +static void +Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d01; +} + +static void +Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008cb; +} + +static void +Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82d01; +} + +static void +Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004b; +} + +static void +Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f81; +} + +static void +Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007b; +} + +static void +Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82d81; +} + +static void +Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000ab; +} + +static void +Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82f01; +} + +static void +Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000db; +} + +static void +Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82701; +} + +static void +Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40084b; +} + +static void +Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82781; +} + +static void +Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40087b; +} + +static void +Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d81; +} + +static void +Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008ab; +} + +static void +Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f01; +} + +static void +Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008db; +} + +static void +Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206581; +} + +static void +Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001c; +} + +static void +Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406581; +} + +static void +Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40021c; +} + +static void +Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x606581; +} + +static void +Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002c; +} + +static void +Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6781; +} + +static void +Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40022c; +} + +static void +Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6581; +} + +static void +Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40011c; +} + +static void +Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6701; +} + +static void +Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40031c; +} + +static void +Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d01; +} + +static void +Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40012c; +} + +static void +Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7501; +} + +static void +Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40032c; +} + +static void +Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83781; +} + +static void +Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40003c; +} + +static void +Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183701; +} + +static void +Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40083c; +} + +static void +Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183781; +} + +static void +Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004c; +} + +static void +Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d81; +} + +static void +Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40084c; +} + +static void +Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83581; +} + +static void +Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40043c; +} + +static void +Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83701; +} + +static void +Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c3c; +} + +static void +Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83d01; +} + +static void +Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40044c; +} + +static void +Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183581; +} + +static void +Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c4c; +} + +static void +Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46001; +} + +static void +Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86001; +} + +static void +Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86501; +} + +static void +Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009c; +} + +static void +Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd081; +} + +static void +Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89001; +} + +static void +Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001; +} + +static void +Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9081; +} + +static void +Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402081; +} + +static void +Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202081; +} + +static void +Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2001; +} + +static void +Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1001; +} + +static void +Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85f01; +} + +static void +Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000c; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f81; +} + +static void +Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080c; +} + +static void +Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f81; +} + +static void +Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000bc; +} + +static void +Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83f01; +} + +static void +Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008bc; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5501; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000eb; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d01; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008eb; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1701; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000fb; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1581; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008fb; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20005; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86e01; +} + +static void +Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3881; +} + +static void +Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3481; +} + +static void +Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3281; +} + +static void +Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3081; +} + +static void +Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86401; +} + +static void +Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86201; +} + +static void +Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x284581; +} + +static void +Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380581; +} + +static void +Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef01; +} + +static void +Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41409c; +} + +static void +Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x806f81; +} + +static void +Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41005e; +} + +static void +Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f81; +} + +static void +Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41006e; +} + +static void +Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206701; +} + +static void +Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43027e; +} + +static void +Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300581; +} + +static void +Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280581; +} + +static void +Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488605; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0581; +} + +static void +Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0581; +} + +static void +Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390581; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183d81; +} + +static void +Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41007e; +} + +static void +Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1083f01; +} + +static void +Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007c; +} + +static void +Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x883f01; +} + +static void +Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40087c; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4083f01; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008c; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2083f01; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088c; +} + +static void +Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1081; +} + +static void +Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89081; +} + +static void +Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001; +} + +static void +Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6001; +} + +static void +Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81081; +} + +static void +Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5081; +} + +static void +Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81; +} + +static void +Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5001; +} + +static void +Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d001; +} + +static void +Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26001; +} + +static void +Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa001; +} + +static void +Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9001; +} + +static void +Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85001; +} + +static void +Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85081; +} + +static void +Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d081; +} + +static void +Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102081; +} + +static void +Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001; +} + +static void +Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2081; +} + +static void +Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005; +} + +static void +Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280605; +} + +static void +Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600605; +} + +static void +Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480605; +} + +static void +Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100605; +} + +static void +Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200605; +} + +static void +Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x205; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x605; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300605; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x484605; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500605; +} + +static void +Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80605; +} + +static void +Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400605; +} + +static void +Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180605; +} + +static void +Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380605; +} + +static void +Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101; +} + +static void +Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501; +} + +static void +Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x301; +} + +static void +Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86801; +} + +static void +Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86c01; +} + +static void +Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86a01; +} + +static void +Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181; +} + +static void +Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86601; +} + +static void +Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d81; +} + +static void +Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005c; +} + +static void +Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d81; +} + +static void +Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40105c; +} + +static void +Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed81; +} + +static void +Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40205c; +} + +static void +Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f01; +} + +static void +Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41009c; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80ef01; +} + +static void +Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41109c; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4ef01; +} + +static void +Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41209c; +} + +static void +Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1006f81; +} + +static void +Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41001e; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1806f81; +} + +static void +Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41002e; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4006f81; +} + +static void +Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41003e; +} + +static void +Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f01; +} + +static void +Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40305c; +} + +static void +Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ef01; +} + +static void +Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41309c; +} + +static void +Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2006f81; +} + +static void +Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41004e; +} + +static void +Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10005; +} + +static void +Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x805; +} + +static void +Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x405; +} + +static void +Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183d01; +} + +static void +Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41047e; +} + +static void +Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500901; +} + +static void +Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300901; +} + +static void +Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600901; +} + +static void +Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100901; +} + +static void +Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400901; +} + +static void +Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200901; +} + +static void +Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680901; +} + +static void +Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180901; +} + +static void +Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480901; +} + +static void +Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280901; +} + +static void +Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700901; +} + +static void +Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80901; +} + +static void +Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100086; +} + +static void +Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88186; +} + +static void +Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180006; +} + +static void +Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c186; +} + +static void +Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c006; +} + +static void +Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108006; +} + +static void +Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c106; +} + +static void +Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88106; +} + +static void +Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104006; +} + +static void +Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c086; +} + +static void +Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88086; +} + +static void +Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100106; +} + +static void +Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4106; +} + +static void +Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200006; +} + +static void +Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc186; +} + +static void +Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4086; +} + +static void +Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100006; +} + +static void +Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc106; +} + +static void +Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186; +} + +static void +Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006; +} + +static void +Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc086; +} + +static void +Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400006; +} + +static void +Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8006; +} + +static void +Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8186; +} + +static void +Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180086; +} + +static void +Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108186; +} + +static void +Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188086; +} + +static void +Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c186; +} + +static void +Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c006; +} + +static void +Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184186; +} + +static void +Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c106; +} + +static void +Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108106; +} + +static void +Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184106; +} + +static void +Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c086; +} + +static void +Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108086; +} + +static void +Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184086; +} + +static void +Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc006; +} + +static void +Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88006; +} + +static void +Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8106; +} + +static void +Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84006; +} + +static void +Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8086; +} + +static void +Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80106; +} + +static void +Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4186; +} + +static void +Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80086; +} + +static void +Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180186; +} + +static void +Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c086; +} + +static void +Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188006; +} + +static void +Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188186; +} + +static void +Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184006; +} + +static void +Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c006; +} + +static void +Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180106; +} + +static void +Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188106; +} + +static void +Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380381; +} + +static void +Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300381; +} + +static void +Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500381; +} + +static void +Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480381; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580381; +} + +static void +Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600381; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700381; +} + +static void +Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680381; +} + +static void +Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x381; +} + +static void +Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x901; +} + +static void +Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100381; +} + +static void +Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80381; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400381; +} + +static void +Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200381; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280381; +} + +static void +Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180381; +} + +static void +Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x581; +} + +static void +Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780381; +} + +static void +Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80581; +} + +static void +Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x701; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200581; +} + +static void +Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100581; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180581; +} + +static void +Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400581; +} + +static void +Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380002; +} + +static void +Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100002; +} + +static void +Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600002; +} + +static void +Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180002; +} + +static void +Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280002; +} + +static void +Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480002; +} + +static void +Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200002; +} + +static void +Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300002; +} + +static void +Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002; +} + +static void +Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500002; +} + +static void +Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400002; +} + +static void +Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400003; +} + +static void +Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700002; +} + +static void +Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300003; +} + +static void +Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003; +} + +static void +Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100003; +} + +static void +Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580002; +} + +static void +Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180003; +} + +static void +Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780002; +} + +static void +Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200003; +} + +static void +Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680002; +} + +static void +Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280003; +} + +static void +Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500003; +} + +static void +Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200004; +} + +static void +Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680003; +} + +static void +Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700003; +} + +static void +Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380003; +} + +static void +Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600003; +} + +static void +Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780003; +} + +static void +Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480003; +} + +static void +Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100004; +} + +static void +Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580003; +} + +static void +Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500004; +} + +static void +Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300004; +} + +static void +Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600004; +} + +static void +Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204006; +} + +static void +Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280006; +} + +static void +Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208006; +} + +static void +Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300006; +} + +static void +Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200186; +} + +static void +Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204106; +} + +static void +Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204086; +} + +static void +Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204186; +} + +static void +Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208086; +} + +static void +Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c006; +} + +static void +Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208106; +} + +static void +Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208186; +} + +static void +Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c086; +} + +static void +Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c186; +} + +static void +Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c106; +} + +static void +Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280086; +} + +static void +Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106; +} + +static void +Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86; +} + +static void +Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4006; +} + +static void +Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80186; +} + +static void +Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84106; +} + +static void +Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84086; +} + +static void +Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84186; +} + +static void +Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100186; +} + +static void +Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104106; +} + +static void +Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104086; +} + +static void +Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104186; +} + +static void +Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c106; +} + +static void +Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200086; +} + +static void +Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c186; +} + +static void +Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200106; +} + +static void +Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000e; +} + +static void +Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a; +} + +static void +Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001a; +} + +static void +Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410e7e; +} + +static void +Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4008ac; +} + +static void +Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006c; +} + +static void +Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000e; +} + +static void +Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002a; +} + +static void +Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000e; +} + +static void +Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010f; +} + +static void +Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40020f; +} + +static void +Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40003a; +} + +static void +Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004a; +} + +static void +Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40011f; +} + +static void +Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000f; +} + +static void +Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410c7e; +} + +static void +Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410d7e; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6006f81; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e001; +} + +static void +Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001; +} + +static void +Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240005; +} + +static void +Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440005; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f03e; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf63f; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f03e; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf73f; +} + +static void +Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f01; +} + +static void +Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87781; +} + +static void +Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87f01; +} + +static void +Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7781; +} + +static void +Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87d01; +} + +static void +Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87581; +} + +static void +Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7701; +} + +static void +Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87d81; +} + +static void +Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87701; +} + +static void +Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d81; +} + +static void +Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d01; +} + +static void +Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7581; +} + +static void +Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x207501; +} + +static void +Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87f81; +} + +static void +Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407501; +} + +static void +Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f81; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e03e; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe63f; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e0; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { + Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { + Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { + Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { + Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { + Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { + Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { + Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { + Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { + Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { + Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { + Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { + Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { + Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { + Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { + Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { + Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { + Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { + Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { + Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { + Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { + Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { + Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { + Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { + Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { + Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { + Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { + Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { + Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { + Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { + Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { + Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { + Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { + Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { + Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { + Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { + Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { + Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { + Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { + Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { + Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { + Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { + Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { + Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { + Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { + Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { + Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { + Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { + Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { + Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { + Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { + Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { + Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { + Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { + Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { + Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { + Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { + Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { + Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { + Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { + Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { + Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { + Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { + Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { + Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { + Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { + Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { + Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { + 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { + Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { + Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { + Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { + Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { + Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { + Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { + Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { + Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { + 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { + Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { + Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { + Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { + Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { + Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { + Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { + Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { + Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { + Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { + Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { + Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0 +}; + + + + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_shift32x5, 3 }, + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_shift32x5, 3 }, + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.243", ICLASS_xt_iclass_rsr_243, + 0, + Opcode_rsr_243_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 0, 0 }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 0, 0 }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 0, 0 }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", ICLASS_xt_iclass_ldpte, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", ICLASS_xt_iclass_hwwitlba, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, + 0, + Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, + { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, + 0, + Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, + 0, + Opcode_ae_lp16f_i_encode_fns, 0, 0 }, + { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, + 0, + Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, + { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, + 0, + Opcode_ae_lp16f_x_encode_fns, 0, 0 }, + { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, + 0, + Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, + { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, + 0, + Opcode_ae_lp24_i_encode_fns, 0, 0 }, + { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, + 0, + Opcode_ae_lp24_iu_encode_fns, 0, 0 }, + { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, + 0, + Opcode_ae_lp24_x_encode_fns, 0, 0 }, + { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, + 0, + Opcode_ae_lp24_xu_encode_fns, 0, 0 }, + { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, + 0, + Opcode_ae_lp24f_i_encode_fns, 0, 0 }, + { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, + 0, + Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, + { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, + 0, + Opcode_ae_lp24f_x_encode_fns, 0, 0 }, + { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, + 0, + Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, + { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, + 0, + Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, + { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, + 0, + Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, + { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, + 0, + Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, + { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, + 0, + Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, + { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, + 0, + Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, + { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, + 0, + Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, + { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, + 0, + Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, + { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, + 0, + Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, + { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, + 0, + Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, + { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, + 0, + Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, + { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, + 0, + Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, + { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, + 0, + Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, + { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, + 0, + Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, + { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, + 0, + Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, + { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, + 0, + Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, + { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, + 0, + Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, + { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, + 0, + Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, + { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, + 0, + Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, + { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, + 0, + Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, + { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, + 0, + Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, + { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, + 0, + Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, + { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, + 0, + Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, + { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, + 0, + Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, + { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, + 0, + Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, + { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, + 0, + Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, + { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, + 0, + Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, + { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, + 0, + Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, + { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, + 0, + Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, + { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, + 0, + Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, + { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, + 0, + Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, + { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, + 0, + Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, + { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, + 0, + Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, + { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, + 0, + Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, + { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, + 0, + Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, + { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, + 0, + Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, + { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, + 0, + Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, + { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, + 0, + Opcode_ae_lq56_i_encode_fns, 0, 0 }, + { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, + 0, + Opcode_ae_lq56_iu_encode_fns, 0, 0 }, + { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, + 0, + Opcode_ae_lq56_x_encode_fns, 0, 0 }, + { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, + 0, + Opcode_ae_lq56_xu_encode_fns, 0, 0 }, + { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, + 0, + Opcode_ae_lq32f_i_encode_fns, 0, 0 }, + { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, + 0, + Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, + { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, + 0, + Opcode_ae_lq32f_x_encode_fns, 0, 0 }, + { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, + 0, + Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, + { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, + 0, + Opcode_ae_sq56s_i_encode_fns, 0, 0 }, + { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, + 0, + Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, + { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, + 0, + Opcode_ae_sq56s_x_encode_fns, 0, 0 }, + { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, + 0, + Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, + { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, + 0, + Opcode_ae_sq32f_i_encode_fns, 0, 0 }, + { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, + 0, + Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, + { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, + 0, + Opcode_ae_sq32f_x_encode_fns, 0, 0 }, + { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, + 0, + Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, + { "ae_zerop48", ICLASS_ae_iclass_zerop48, + 0, + Opcode_ae_zerop48_encode_fns, 0, 0 }, + { "ae_movp48", ICLASS_ae_iclass_movp48, + 0, + Opcode_ae_movp48_encode_fns, 0, 0 }, + { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll, + 0, + Opcode_ae_selp24_ll_encode_fns, 0, 0 }, + { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh, + 0, + Opcode_ae_selp24_lh_encode_fns, 0, 0 }, + { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl, + 0, + Opcode_ae_selp24_hl_encode_fns, 0, 0 }, + { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh, + 0, + Opcode_ae_selp24_hh_encode_fns, 0, 0 }, + { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2, + 0, + Opcode_ae_movtp24x2_encode_fns, 0, 0 }, + { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2, + 0, + Opcode_ae_movfp24x2_encode_fns, 0, 0 }, + { "ae_movtp48", ICLASS_ae_iclass_movtp48, + 0, + Opcode_ae_movtp48_encode_fns, 0, 0 }, + { "ae_movfp48", ICLASS_ae_iclass_movfp48, + 0, + Opcode_ae_movfp48_encode_fns, 0, 0 }, + { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2, + 0, + Opcode_ae_movpa24x2_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l, + 0, + Opcode_ae_cvta32p24_l_encode_fns, 0, 0 }, + { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h, + 0, + Opcode_ae_cvta32p24_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_ae_iclass_truncp16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym, + 0, + Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 }, + { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym, + 0, + Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 }, + { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym, + 0, + Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym, + 0, + Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 }, + { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym, + 0, + Opcode_ae_roundsp16sym_encode_fns, 0, 0 }, + { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym, + 0, + Opcode_ae_roundsp16asym_encode_fns, 0, 0 }, + { "ae_zeroq56", ICLASS_ae_iclass_zeroq56, + 0, + Opcode_ae_zeroq56_encode_fns, 0, 0 }, + { "ae_movq56", ICLASS_ae_iclass_movq56, + 0, + Opcode_ae_movq56_encode_fns, 0, 0 }, + { "ae_movtq56", ICLASS_ae_iclass_movtq56, + 0, + Opcode_ae_movtq56_encode_fns, 0, 0 }, + { "ae_movfq56", ICLASS_ae_iclass_movfq56, + 0, + Opcode_ae_movfq56_encode_fns, 0, 0 }, + { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s, + 0, + Opcode_ae_cvtq48a32s_encode_fns, 0, 0 }, + { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l, + 0, + Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 }, + { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h, + 0, + Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 }, + { "ae_satq48s", ICLASS_ae_iclass_satq48s, + 0, + Opcode_ae_satq48s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_ae_iclass_truncq32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym, + 0, + Opcode_ae_roundsq32sym_encode_fns, 0, 0 }, + { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym, + 0, + Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, + 0, + Opcode_ae_movap24s_l_encode_fns, 0, 0 }, + { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, + 0, + Opcode_ae_movap24s_h_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_addp24", ICLASS_ae_iclass_addp24, + 0, + Opcode_ae_addp24_encode_fns, 0, 0 }, + { "ae_subp24", ICLASS_ae_iclass_subp24, + 0, + Opcode_ae_subp24_encode_fns, 0, 0 }, + { "ae_negp24", ICLASS_ae_iclass_negp24, + 0, + Opcode_ae_negp24_encode_fns, 0, 0 }, + { "ae_absp24", ICLASS_ae_iclass_absp24, + 0, + Opcode_ae_absp24_encode_fns, 0, 0 }, + { "ae_maxp24s", ICLASS_ae_iclass_maxp24s, + 0, + Opcode_ae_maxp24s_encode_fns, 0, 0 }, + { "ae_minp24s", ICLASS_ae_iclass_minp24s, + 0, + Opcode_ae_minp24s_encode_fns, 0, 0 }, + { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s, + 0, + Opcode_ae_maxbp24s_encode_fns, 0, 0 }, + { "ae_minbp24s", ICLASS_ae_iclass_minbp24s, + 0, + Opcode_ae_minbp24s_encode_fns, 0, 0 }, + { "ae_addsp24s", ICLASS_ae_iclass_addsp24s, + 0, + Opcode_ae_addsp24s_encode_fns, 0, 0 }, + { "ae_subsp24s", ICLASS_ae_iclass_subsp24s, + 0, + Opcode_ae_subsp24s_encode_fns, 0, 0 }, + { "ae_negsp24s", ICLASS_ae_iclass_negsp24s, + 0, + Opcode_ae_negsp24s_encode_fns, 0, 0 }, + { "ae_abssp24s", ICLASS_ae_iclass_abssp24s, + 0, + Opcode_ae_abssp24s_encode_fns, 0, 0 }, + { "ae_andp48", ICLASS_ae_iclass_andp48, + 0, + Opcode_ae_andp48_encode_fns, 0, 0 }, + { "ae_nandp48", ICLASS_ae_iclass_nandp48, + 0, + Opcode_ae_nandp48_encode_fns, 0, 0 }, + { "ae_orp48", ICLASS_ae_iclass_orp48, + 0, + Opcode_ae_orp48_encode_fns, 0, 0 }, + { "ae_xorp48", ICLASS_ae_iclass_xorp48, + 0, + Opcode_ae_xorp48_encode_fns, 0, 0 }, + { "ae_ltp24s", ICLASS_ae_iclass_ltp24s, + 0, + Opcode_ae_ltp24s_encode_fns, 0, 0 }, + { "ae_lep24s", ICLASS_ae_iclass_lep24s, + 0, + Opcode_ae_lep24s_encode_fns, 0, 0 }, + { "ae_eqp24", ICLASS_ae_iclass_eqp24, + 0, + Opcode_ae_eqp24_encode_fns, 0, 0 }, + { "ae_addq56", ICLASS_ae_iclass_addq56, + 0, + Opcode_ae_addq56_encode_fns, 0, 0 }, + { "ae_subq56", ICLASS_ae_iclass_subq56, + 0, + Opcode_ae_subq56_encode_fns, 0, 0 }, + { "ae_negq56", ICLASS_ae_iclass_negq56, + 0, + Opcode_ae_negq56_encode_fns, 0, 0 }, + { "ae_absq56", ICLASS_ae_iclass_absq56, + 0, + Opcode_ae_absq56_encode_fns, 0, 0 }, + { "ae_maxq56s", ICLASS_ae_iclass_maxq56s, + 0, + Opcode_ae_maxq56s_encode_fns, 0, 0 }, + { "ae_minq56s", ICLASS_ae_iclass_minq56s, + 0, + Opcode_ae_minq56s_encode_fns, 0, 0 }, + { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s, + 0, + Opcode_ae_maxbq56s_encode_fns, 0, 0 }, + { "ae_minbq56s", ICLASS_ae_iclass_minbq56s, + 0, + Opcode_ae_minbq56s_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_ae_iclass_addsq56s, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_ae_iclass_subsq56s, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_ae_iclass_negsq56s, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_ae_iclass_abssq56s, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_andq56", ICLASS_ae_iclass_andq56, + 0, + Opcode_ae_andq56_encode_fns, 0, 0 }, + { "ae_nandq56", ICLASS_ae_iclass_nandq56, + 0, + Opcode_ae_nandq56_encode_fns, 0, 0 }, + { "ae_orq56", ICLASS_ae_iclass_orq56, + 0, + Opcode_ae_orq56_encode_fns, 0, 0 }, + { "ae_xorq56", ICLASS_ae_iclass_xorq56, + 0, + Opcode_ae_xorq56_encode_fns, 0, 0 }, + { "ae_sllip24", ICLASS_ae_iclass_sllip24, + 0, + Opcode_ae_sllip24_encode_fns, 0, 0 }, + { "ae_srlip24", ICLASS_ae_iclass_srlip24, + 0, + Opcode_ae_srlip24_encode_fns, 0, 0 }, + { "ae_sraip24", ICLASS_ae_iclass_sraip24, + 0, + Opcode_ae_sraip24_encode_fns, 0, 0 }, + { "ae_sllsp24", ICLASS_ae_iclass_sllsp24, + 0, + Opcode_ae_sllsp24_encode_fns, 0, 0 }, + { "ae_srlsp24", ICLASS_ae_iclass_srlsp24, + 0, + Opcode_ae_srlsp24_encode_fns, 0, 0 }, + { "ae_srasp24", ICLASS_ae_iclass_srasp24, + 0, + Opcode_ae_srasp24_encode_fns, 0, 0 }, + { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s, + 0, + Opcode_ae_sllisp24s_encode_fns, 0, 0 }, + { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s, + 0, + Opcode_ae_sllssp24s_encode_fns, 0, 0 }, + { "ae_slliq56", ICLASS_ae_iclass_slliq56, + 0, + Opcode_ae_slliq56_encode_fns, 0, 0 }, + { "ae_srliq56", ICLASS_ae_iclass_srliq56, + 0, + Opcode_ae_srliq56_encode_fns, 0, 0 }, + { "ae_sraiq56", ICLASS_ae_iclass_sraiq56, + 0, + Opcode_ae_sraiq56_encode_fns, 0, 0 }, + { "ae_sllsq56", ICLASS_ae_iclass_sllsq56, + 0, + Opcode_ae_sllsq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_ae_iclass_srlsq56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_ae_iclass_srasq56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_sllaq56", ICLASS_ae_iclass_sllaq56, + 0, + Opcode_ae_sllaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_ae_iclass_srlaq56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_ae_iclass_sraaq56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s, + 0, + Opcode_ae_sllisq56s_encode_fns, 0, 0 }, + { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s, + 0, + Opcode_ae_sllssq56s_encode_fns, 0, 0 }, + { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s, + 0, + Opcode_ae_sllasq56s_encode_fns, 0, 0 }, + { "ae_ltq56s", ICLASS_ae_iclass_ltq56s, + 0, + Opcode_ae_ltq56s_encode_fns, 0, 0 }, + { "ae_leq56s", ICLASS_ae_iclass_leq56s, + 0, + Opcode_ae_leq56s_encode_fns, 0, 0 }, + { "ae_eqq56", ICLASS_ae_iclass_eqq56, + 0, + Opcode_ae_eqq56_encode_fns, 0, 0 }, + { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s, + 0, + Opcode_ae_nsaq56s_encode_fns, 0, 0 }, + { "ae_mulsrfq32sp24s.h", ICLASS_ae_iclass_mulsrfq32sp24s_h, + 0, + Opcode_ae_mulsrfq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mulsrfq32sp24s.l", ICLASS_ae_iclass_mulsrfq32sp24s_l, + 0, + Opcode_ae_mulsrfq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mularfq32sp24s.h", ICLASS_ae_iclass_mularfq32sp24s_h, + 0, + Opcode_ae_mularfq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mularfq32sp24s.l", ICLASS_ae_iclass_mularfq32sp24s_l, + 0, + Opcode_ae_mularfq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mulrfq32sp24s.h", ICLASS_ae_iclass_mulrfq32sp24s_h, + 0, + Opcode_ae_mulrfq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mulrfq32sp24s.l", ICLASS_ae_iclass_mulrfq32sp24s_l, + 0, + Opcode_ae_mulrfq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mulsfq32sp24s.h", ICLASS_ae_iclass_mulsfq32sp24s_h, + 0, + Opcode_ae_mulsfq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mulsfq32sp24s.l", ICLASS_ae_iclass_mulsfq32sp24s_l, + 0, + Opcode_ae_mulsfq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mulafq32sp24s.h", ICLASS_ae_iclass_mulafq32sp24s_h, + 0, + Opcode_ae_mulafq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mulafq32sp24s.l", ICLASS_ae_iclass_mulafq32sp24s_l, + 0, + Opcode_ae_mulafq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mulfq32sp24s.h", ICLASS_ae_iclass_mulfq32sp24s_h, + 0, + Opcode_ae_mulfq32sp24s_h_encode_fns, 0, 0 }, + { "ae_mulfq32sp24s.l", ICLASS_ae_iclass_mulfq32sp24s_l, + 0, + Opcode_ae_mulfq32sp24s_l_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll, + 0, + Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll, + 0, + Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 }, + { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll, + 0, + Opcode_ae_mulp24s_ll_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh, + 0, + Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh, + 0, + Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 }, + { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh, + 0, + Opcode_ae_mulp24s_lh_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl, + 0, + Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl, + 0, + Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 }, + { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl, + 0, + Opcode_ae_mulp24s_hl_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh, + 0, + Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh, + 0, + Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 }, + { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh, + 0, + Opcode_ae_mulp24s_hh_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll, + 0, + Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll, + 0, + Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 }, + { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll, + 0, + Opcode_ae_mulap24s_ll_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh, + 0, + Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh, + 0, + Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 }, + { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh, + 0, + Opcode_ae_mulap24s_lh_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl, + 0, + Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl, + 0, + Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 }, + { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl, + 0, + Opcode_ae_mulap24s_hl_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh, + 0, + Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh, + 0, + Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 }, + { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh, + 0, + Opcode_ae_mulap24s_hh_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll, + 0, + Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll, + 0, + Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 }, + { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll, + 0, + Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh, + 0, + Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh, + 0, + Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 }, + { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh, + 0, + Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl, + 0, + Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl, + 0, + Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 }, + { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl, + 0, + Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh, + 0, + Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh, + 0, + Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 }, + { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh, + 0, + Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll, + 0, + Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll, + 0, + Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh, + 0, + Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh, + 0, + Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl, + 0, + Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl, + 0, + Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh, + 0, + Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh, + 0, + Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll, + 0, + Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll, + 0, + Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh, + 0, + Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh, + 0, + Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl, + 0, + Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl, + 0, + Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh, + 0, + Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh, + 0, + Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l, + 0, + Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h, + 0, + Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l, + 0, + Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h, + 0, + Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h, + 0, + Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h, + 0, + Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l, + 0, + Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h, + 0, + Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l, + 0, + Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h, + 0, + Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h, + 0, + Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h, + 0, + Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l, + 0, + Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h, + 0, + Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l, + 0, + Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h, + 0, + Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h, + 0, + Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h, + 0, + Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll, + 0, + Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll, + 0, + Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll, + 0, + Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll, + 0, + Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh, + 0, + Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh, + 0, + Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh, + 0, + Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh, + 0, + Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh, + 0, + Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh, + 0, + Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh, + 0, + Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh, + 0, + Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll, + 0, + Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll, + 0, + Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll, + 0, + Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll, + 0, + Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh, + 0, + Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh, + 0, + Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh, + 0, + Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh, + 0, + Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh, + 0, + Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh, + 0, + Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh, + 0, + Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh, + 0, + Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll, + 0, + Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll, + 0, + Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll, + 0, + Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll, + 0, + Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh, + 0, + Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh, + 0, + Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh, + 0, + Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh, + 0, + Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh, + 0, + Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh, + 0, + Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, + 0, + Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, + 0, + Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, + 0, + Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, + 0, + Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, + 0, + Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, + 0, + Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, + 0, + Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, + 0, + Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, + 0, + Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, + 0, + Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, + 0, + Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, + 0, + Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, + 0, + Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, + 0, + Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, + 0, + Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, + 0, + Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, + 0, + Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, + 0, + Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, + 0, + Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, + 0, + Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, + 0, + Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, + 0, + Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, + 0, + Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, + 0, + Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, + 0, + Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, + 0, + Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, + 0, + Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, + 0, + Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, + 0, + Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, + 0, + Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, + 0, + Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, + 0, + Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, + 0, + Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, + 0, + Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, + 0, + Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, + 0, + Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, + 0, + Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, + 0, + Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, + 0, + Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, + 0, + Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, + 0, + Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, + 0, + Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, + 0, + Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, + 0, + Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, + 0, + Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, + 0, + Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_ae_iclass_sha32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, + 0, + Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, + 0, + Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, + 0, + Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldsht", ICLASS_ae_iclass_vldsht, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_ae_iclass_lb, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_ae_iclass_lbi, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_ae_iclass_lbk, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_ae_iclass_lbki, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_db", ICLASS_ae_iclass_db, + 0, + Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_ae_iclass_dbi, + 0, + Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, + { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, + 0, + Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, + 0, + Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_ae_iclass_sb, + 0, + Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_ae_iclass_sbi, + 0, + Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_ae_iclass_vles16c, + 0, + Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_ae_iclass_sbf, + 0, + Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, + { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, + 0, + Opcode_ae_minabssp24s_encode_fns, 0, 0 }, + { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, + 0, + Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, + { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, + 0, + Opcode_ae_minabssq56s_encode_fns, 0, 0 }, + { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, + 0, + Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, + 0, + Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, + { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, + 0, + Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, + { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, + 0, + Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, + { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, + 0, + Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, + { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, + 0, + Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, + { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, + 0, + Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, + { "ae_lp24.c", ICLASS_icls_AE_LP24_C, + 0, + Opcode_ae_lp24_c_encode_fns, 0, 0 }, + { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, + 0, + Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, + { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, + 0, + Opcode_ae_lp24f_c_encode_fns, 0, 0 }, + { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, + 0, + Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, + { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, + 0, + Opcode_ae_lp16f_c_encode_fns, 0, 0 }, + { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, + 0, + Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, + { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, + 0, + Opcode_ae_lq56_c_encode_fns, 0, 0 }, + { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, + 0, + Opcode_ae_sq56s_c_encode_fns, 0, 0 }, + { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, + 0, + Opcode_ae_lq32f_c_encode_fns, 0, 0 }, + { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, + 0, + Opcode_ae_sq32f_c_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_243, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_MULUH, + OPCODE_MULSH, + OPCODE_MUL_AA_LL, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_HH, + OPCODE_UMUL_AA_LL, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_HH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_HH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DD_LL, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_HH, + OPCODE_MULA_AA_LL, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_HH, + OPCODE_MULS_AA_LL, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_HH, + OPCODE_MULA_AD_LL, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_HH, + OPCODE_MULS_AD_LL, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_HH, + OPCODE_MULA_DA_LL, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_HH, + OPCODE_MULS_DA_LL, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_HH, + OPCODE_MULA_DD_LL, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_HH, + OPCODE_MULS_DD_LL, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_HH, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_DPFL, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_WSR_PTEVADDR, + OPCODE_RSR_PTEVADDR, + OPCODE_XSR_PTEVADDR, + OPCODE_RSR_RASID, + OPCODE_WSR_RASID, + OPCODE_XSR_RASID, + OPCODE_RSR_ITLBCFG, + OPCODE_WSR_ITLBCFG, + OPCODE_XSR_ITLBCFG, + OPCODE_RSR_DTLBCFG, + OPCODE_WSR_DTLBCFG, + OPCODE_XSR_DTLBCFG, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_LDPTE, + OPCODE_HWWITLBA, + OPCODE_HWWDTLBA, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOU, + OPCODE_QUOS, + OPCODE_REMU, + OPCODE_REMS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_SD_NO, + OPCODE_WUR_AE_SD_NO, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_AE_LP16F_I, + OPCODE_AE_LP16F_IU, + OPCODE_AE_LP16F_X, + OPCODE_AE_LP16F_XU, + OPCODE_AE_LP24_I, + OPCODE_AE_LP24_IU, + OPCODE_AE_LP24_X, + OPCODE_AE_LP24_XU, + OPCODE_AE_LP24F_I, + OPCODE_AE_LP24F_IU, + OPCODE_AE_LP24F_X, + OPCODE_AE_LP24F_XU, + OPCODE_AE_LP16X2F_I, + OPCODE_AE_LP16X2F_IU, + OPCODE_AE_LP16X2F_X, + OPCODE_AE_LP16X2F_XU, + OPCODE_AE_LP24X2F_I, + OPCODE_AE_LP24X2F_IU, + OPCODE_AE_LP24X2F_X, + OPCODE_AE_LP24X2F_XU, + OPCODE_AE_LP24X2_I, + OPCODE_AE_LP24X2_IU, + OPCODE_AE_LP24X2_X, + OPCODE_AE_LP24X2_XU, + OPCODE_AE_SP16X2F_I, + OPCODE_AE_SP16X2F_IU, + OPCODE_AE_SP16X2F_X, + OPCODE_AE_SP16X2F_XU, + OPCODE_AE_SP24X2S_I, + OPCODE_AE_SP24X2S_IU, + OPCODE_AE_SP24X2S_X, + OPCODE_AE_SP24X2S_XU, + OPCODE_AE_SP24X2F_I, + OPCODE_AE_SP24X2F_IU, + OPCODE_AE_SP24X2F_X, + OPCODE_AE_SP24X2F_XU, + OPCODE_AE_SP16F_L_I, + OPCODE_AE_SP16F_L_IU, + OPCODE_AE_SP16F_L_X, + OPCODE_AE_SP16F_L_XU, + OPCODE_AE_SP24S_L_I, + OPCODE_AE_SP24S_L_IU, + OPCODE_AE_SP24S_L_X, + OPCODE_AE_SP24S_L_XU, + OPCODE_AE_SP24F_L_I, + OPCODE_AE_SP24F_L_IU, + OPCODE_AE_SP24F_L_X, + OPCODE_AE_SP24F_L_XU, + OPCODE_AE_LQ56_I, + OPCODE_AE_LQ56_IU, + OPCODE_AE_LQ56_X, + OPCODE_AE_LQ56_XU, + OPCODE_AE_LQ32F_I, + OPCODE_AE_LQ32F_IU, + OPCODE_AE_LQ32F_X, + OPCODE_AE_LQ32F_XU, + OPCODE_AE_SQ56S_I, + OPCODE_AE_SQ56S_IU, + OPCODE_AE_SQ56S_X, + OPCODE_AE_SQ56S_XU, + OPCODE_AE_SQ32F_I, + OPCODE_AE_SQ32F_IU, + OPCODE_AE_SQ32F_X, + OPCODE_AE_SQ32F_XU, + OPCODE_AE_ZEROP48, + OPCODE_AE_MOVP48, + OPCODE_AE_SELP24_LL, + OPCODE_AE_SELP24_LH, + OPCODE_AE_SELP24_HL, + OPCODE_AE_SELP24_HH, + OPCODE_AE_MOVTP24X2, + OPCODE_AE_MOVFP24X2, + OPCODE_AE_MOVTP48, + OPCODE_AE_MOVFP48, + OPCODE_AE_MOVPA24X2, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_CVTA32P24_L, + OPCODE_AE_CVTA32P24_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUNDSP24Q48SYM, + OPCODE_AE_ROUNDSP24Q48ASYM, + OPCODE_AE_ROUNDSP16Q48SYM, + OPCODE_AE_ROUNDSP16Q48ASYM, + OPCODE_AE_ROUNDSP16SYM, + OPCODE_AE_ROUNDSP16ASYM, + OPCODE_AE_ZEROQ56, + OPCODE_AE_MOVQ56, + OPCODE_AE_MOVTQ56, + OPCODE_AE_MOVFQ56, + OPCODE_AE_CVTQ48A32S, + OPCODE_AE_CVTQ48P24S_L, + OPCODE_AE_CVTQ48P24S_H, + OPCODE_AE_SATQ48S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_ROUNDSQ32SYM, + OPCODE_AE_ROUNDSQ32ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAP24S_L, + OPCODE_AE_MOVAP24S_H, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADDP24, + OPCODE_AE_SUBP24, + OPCODE_AE_NEGP24, + OPCODE_AE_ABSP24, + OPCODE_AE_MAXP24S, + OPCODE_AE_MINP24S, + OPCODE_AE_MAXBP24S, + OPCODE_AE_MINBP24S, + OPCODE_AE_ADDSP24S, + OPCODE_AE_SUBSP24S, + OPCODE_AE_NEGSP24S, + OPCODE_AE_ABSSP24S, + OPCODE_AE_ANDP48, + OPCODE_AE_NANDP48, + OPCODE_AE_ORP48, + OPCODE_AE_XORP48, + OPCODE_AE_LTP24S, + OPCODE_AE_LEP24S, + OPCODE_AE_EQP24, + OPCODE_AE_ADDQ56, + OPCODE_AE_SUBQ56, + OPCODE_AE_NEGQ56, + OPCODE_AE_ABSQ56, + OPCODE_AE_MAXQ56S, + OPCODE_AE_MINQ56S, + OPCODE_AE_MAXBQ56S, + OPCODE_AE_MINBQ56S, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_ANDQ56, + OPCODE_AE_NANDQ56, + OPCODE_AE_ORQ56, + OPCODE_AE_XORQ56, + OPCODE_AE_SLLIP24, + OPCODE_AE_SRLIP24, + OPCODE_AE_SRAIP24, + OPCODE_AE_SLLSP24, + OPCODE_AE_SRLSP24, + OPCODE_AE_SRASP24, + OPCODE_AE_SLLISP24S, + OPCODE_AE_SLLSSP24S, + OPCODE_AE_SLLIQ56, + OPCODE_AE_SRLIQ56, + OPCODE_AE_SRAIQ56, + OPCODE_AE_SLLSQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLLAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLLISQ56S, + OPCODE_AE_SLLSSQ56S, + OPCODE_AE_SLLASQ56S, + OPCODE_AE_LTQ56S, + OPCODE_AE_LEQ56S, + OPCODE_AE_EQQ56, + OPCODE_AE_NSAQ56S, + OPCODE_AE_MULSRFQ32SP24S_H, + OPCODE_AE_MULSRFQ32SP24S_L, + OPCODE_AE_MULARFQ32SP24S_H, + OPCODE_AE_MULARFQ32SP24S_L, + OPCODE_AE_MULRFQ32SP24S_H, + OPCODE_AE_MULRFQ32SP24S_L, + OPCODE_AE_MULSFQ32SP24S_H, + OPCODE_AE_MULSFQ32SP24S_L, + OPCODE_AE_MULAFQ32SP24S_H, + OPCODE_AE_MULAFQ32SP24S_L, + OPCODE_AE_MULFQ32SP24S_H, + OPCODE_AE_MULFQ32SP24S_L, + OPCODE_AE_MULFS32P16S_LL, + OPCODE_AE_MULFP24S_LL, + OPCODE_AE_MULP24S_LL, + OPCODE_AE_MULFS32P16S_LH, + OPCODE_AE_MULFP24S_LH, + OPCODE_AE_MULP24S_LH, + OPCODE_AE_MULFS32P16S_HL, + OPCODE_AE_MULFP24S_HL, + OPCODE_AE_MULP24S_HL, + OPCODE_AE_MULFS32P16S_HH, + OPCODE_AE_MULFP24S_HH, + OPCODE_AE_MULP24S_HH, + OPCODE_AE_MULAFS32P16S_LL, + OPCODE_AE_MULAFP24S_LL, + OPCODE_AE_MULAP24S_LL, + OPCODE_AE_MULAFS32P16S_LH, + OPCODE_AE_MULAFP24S_LH, + OPCODE_AE_MULAP24S_LH, + OPCODE_AE_MULAFS32P16S_HL, + OPCODE_AE_MULAFP24S_HL, + OPCODE_AE_MULAP24S_HL, + OPCODE_AE_MULAFS32P16S_HH, + OPCODE_AE_MULAFP24S_HH, + OPCODE_AE_MULAP24S_HH, + OPCODE_AE_MULSFS32P16S_LL, + OPCODE_AE_MULSFP24S_LL, + OPCODE_AE_MULSP24S_LL, + OPCODE_AE_MULSFS32P16S_LH, + OPCODE_AE_MULSFP24S_LH, + OPCODE_AE_MULSP24S_LH, + OPCODE_AE_MULSFS32P16S_HL, + OPCODE_AE_MULSFP24S_HL, + OPCODE_AE_MULSP24S_HL, + OPCODE_AE_MULSFS32P16S_HH, + OPCODE_AE_MULSFP24S_HH, + OPCODE_AE_MULSP24S_HH, + OPCODE_AE_MULAFS56P24S_LL, + OPCODE_AE_MULAS56P24S_LL, + OPCODE_AE_MULAFS56P24S_LH, + OPCODE_AE_MULAS56P24S_LH, + OPCODE_AE_MULAFS56P24S_HL, + OPCODE_AE_MULAS56P24S_HL, + OPCODE_AE_MULAFS56P24S_HH, + OPCODE_AE_MULAS56P24S_HH, + OPCODE_AE_MULSFS56P24S_LL, + OPCODE_AE_MULSS56P24S_LL, + OPCODE_AE_MULSFS56P24S_LH, + OPCODE_AE_MULSS56P24S_LH, + OPCODE_AE_MULSFS56P24S_HL, + OPCODE_AE_MULSS56P24S_HL, + OPCODE_AE_MULSFS56P24S_HH, + OPCODE_AE_MULSS56P24S_HH, + OPCODE_AE_MULFQ32SP16S_L, + OPCODE_AE_MULFQ32SP16S_H, + OPCODE_AE_MULFQ32SP16U_L, + OPCODE_AE_MULFQ32SP16U_H, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16S_H, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULQ32SP16U_H, + OPCODE_AE_MULAFQ32SP16S_L, + OPCODE_AE_MULAFQ32SP16S_H, + OPCODE_AE_MULAFQ32SP16U_L, + OPCODE_AE_MULAFQ32SP16U_H, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16S_H, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULAQ32SP16U_H, + OPCODE_AE_MULSFQ32SP16S_L, + OPCODE_AE_MULSFQ32SP16S_H, + OPCODE_AE_MULSFQ32SP16U_L, + OPCODE_AE_MULSFQ32SP16U_H, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16S_H, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULSQ32SP16U_H, + OPCODE_AE_MULZAAQ32SP16S_LL, + OPCODE_AE_MULZAAFQ32SP16S_LL, + OPCODE_AE_MULZAAQ32SP16U_LL, + OPCODE_AE_MULZAAFQ32SP16U_LL, + OPCODE_AE_MULZAAQ32SP16S_HH, + OPCODE_AE_MULZAAFQ32SP16S_HH, + OPCODE_AE_MULZAAQ32SP16U_HH, + OPCODE_AE_MULZAAFQ32SP16U_HH, + OPCODE_AE_MULZAAQ32SP16S_LH, + OPCODE_AE_MULZAAFQ32SP16S_LH, + OPCODE_AE_MULZAAQ32SP16U_LH, + OPCODE_AE_MULZAAFQ32SP16U_LH, + OPCODE_AE_MULZASQ32SP16S_LL, + OPCODE_AE_MULZASFQ32SP16S_LL, + OPCODE_AE_MULZASQ32SP16U_LL, + OPCODE_AE_MULZASFQ32SP16U_LL, + OPCODE_AE_MULZASQ32SP16S_HH, + OPCODE_AE_MULZASFQ32SP16S_HH, + OPCODE_AE_MULZASQ32SP16U_HH, + OPCODE_AE_MULZASFQ32SP16U_HH, + OPCODE_AE_MULZASQ32SP16S_LH, + OPCODE_AE_MULZASFQ32SP16S_LH, + OPCODE_AE_MULZASQ32SP16U_LH, + OPCODE_AE_MULZASFQ32SP16U_LH, + OPCODE_AE_MULZSAQ32SP16S_LL, + OPCODE_AE_MULZSAFQ32SP16S_LL, + OPCODE_AE_MULZSAQ32SP16U_LL, + OPCODE_AE_MULZSAFQ32SP16U_LL, + OPCODE_AE_MULZSAQ32SP16S_HH, + OPCODE_AE_MULZSAFQ32SP16S_HH, + OPCODE_AE_MULZSAQ32SP16U_HH, + OPCODE_AE_MULZSAFQ32SP16U_HH, + OPCODE_AE_MULZSAQ32SP16S_LH, + OPCODE_AE_MULZSAFQ32SP16S_LH, + OPCODE_AE_MULZSAQ32SP16U_LH, + OPCODE_AE_MULZSAFQ32SP16U_LH, + OPCODE_AE_MULZSSQ32SP16S_LL, + OPCODE_AE_MULZSSFQ32SP16S_LL, + OPCODE_AE_MULZSSQ32SP16U_LL, + OPCODE_AE_MULZSSFQ32SP16U_LL, + OPCODE_AE_MULZSSQ32SP16S_HH, + OPCODE_AE_MULZSSFQ32SP16S_HH, + OPCODE_AE_MULZSSQ32SP16U_HH, + OPCODE_AE_MULZSSFQ32SP16U_HH, + OPCODE_AE_MULZSSQ32SP16S_LH, + OPCODE_AE_MULZSSFQ32SP16S_LH, + OPCODE_AE_MULZSSQ32SP16U_LH, + OPCODE_AE_MULZSSFQ32SP16U_LH, + OPCODE_AE_MULZAAFP24S_HH_LL, + OPCODE_AE_MULZAAP24S_HH_LL, + OPCODE_AE_MULZAAFP24S_HL_LH, + OPCODE_AE_MULZAAP24S_HL_LH, + OPCODE_AE_MULZASFP24S_HH_LL, + OPCODE_AE_MULZASP24S_HH_LL, + OPCODE_AE_MULZASFP24S_HL_LH, + OPCODE_AE_MULZASP24S_HL_LH, + OPCODE_AE_MULZSAFP24S_HH_LL, + OPCODE_AE_MULZSAP24S_HH_LL, + OPCODE_AE_MULZSAFP24S_HL_LH, + OPCODE_AE_MULZSAP24S_HL_LH, + OPCODE_AE_MULZSSFP24S_HH_LL, + OPCODE_AE_MULZSSP24S_HH_LL, + OPCODE_AE_MULZSSFP24S_HL_LH, + OPCODE_AE_MULZSSP24S_HL_LH, + OPCODE_AE_MULAAFP24S_HH_LL, + OPCODE_AE_MULAAP24S_HH_LL, + OPCODE_AE_MULAAFP24S_HL_LH, + OPCODE_AE_MULAAP24S_HL_LH, + OPCODE_AE_MULASFP24S_HH_LL, + OPCODE_AE_MULASP24S_HH_LL, + OPCODE_AE_MULASFP24S_HL_LH, + OPCODE_AE_MULASP24S_HL_LH, + OPCODE_AE_MULSAFP24S_HH_LL, + OPCODE_AE_MULSAP24S_HH_LL, + OPCODE_AE_MULSAFP24S_HL_LH, + OPCODE_AE_MULSAP24S_HL_LH, + OPCODE_AE_MULSSFP24S_HH_LL, + OPCODE_AE_MULSSP24S_HH_LL, + OPCODE_AE_MULSSFP24S_HL_LH, + OPCODE_AE_MULSSP24S_HL_LH, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_MINABSSP24S, + OPCODE_AE_MAXABSSP24S, + OPCODE_AE_MINABSSQ56S, + OPCODE_AE_MAXABSSQ56S, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_AE_LP24X2_C, + OPCODE_AE_SP24X2S_C, + OPCODE_AE_LP24X2F_C, + OPCODE_AE_SP24X2F_C, + OPCODE_AE_LP16X2F_C, + OPCODE_AE_SP16X2F_C, + OPCODE_AE_LP24_C, + OPCODE_AE_SP24S_L_C, + OPCODE_AE_LP24F_C, + OPCODE_AE_SP24F_L_C, + OPCODE_AE_LP16F_C, + OPCODE_AE_SP16F_L_C, + OPCODE_AE_LQ56_C, + OPCODE_AE_SQ56S_C, + OPCODE_AE_LQ32F_C, + OPCODE_AE_SQ32F_C, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_HWWITLBA; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_HWWDTLBA; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_XSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_XSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_XSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_XSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_XSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_XSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_LDPTE; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_RSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_RSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_RSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_RSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_RSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_RSR_243; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_WSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_WSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_WSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_WSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_WSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_I; + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_X; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_I; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_X; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_XU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_CVTQ48A32S; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_ae_s3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVP48; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVPA24X2; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_I; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_X; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_TRUNCA32Q48; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_I; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_X; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_NSAQ56S; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_XU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_XU; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRAIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLISQ56S; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SHA32; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL32T; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLAQ56; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL16T; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LBK; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRAAQ56; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL32T; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLASQ56S; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL16T; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVTQ56; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVFQ56; + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SBI; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SAR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DB; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SB; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITPTR; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITSUSED; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_r_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_r_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_VLDSHT; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLES16C; + if (Field_r_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SBF; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLDL16C; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSQ56; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LB; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLSQ56; + if (Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRASQ56; + if (Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSSQ56S; + if (Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVQ56; + if (Field_s_Slot_inst_get (insn) == 8 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_s_Slot_inst_get (insn) == 9 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_s_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITPTR; + if (Field_s_Slot_inst_get (insn) == 11 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITSUSED; + if (Field_s_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_s_Slot_inst_get (insn) == 13 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_s_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_s_Slot_inst_get (insn) == 15 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBKI; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DBI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBI; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_ae_s20_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_ftsf378ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BT; + if (Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SELP24_HH; + if (Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SELP24_HL; + if (Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SELP24_LH; + if (Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_ftsf315_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 2 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAASQ56S; + if (Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_C; + if (Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_C; + if (Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_C; + if (Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_C; + if (Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_C; + if (Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_C; + if (Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_C; + if (Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_C; + if (Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_C; + if (Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_C; + if (Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_C; + if (Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_C; + if (Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SQ32F_C; + if (Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SQ56S_C; + if (Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && + Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && + Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SELP24_LL; + if (Field_ftsf211ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_J; + if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_EXTUI; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BEQZ; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BGEZ; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVI; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 13 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BLTZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 43 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_ftsf217ae_slot0_Slot_ae_slot0_get (insn) == 299 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_I; + if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 46 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 47 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_IU; + if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 302 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_X; + if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 303 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_XU; + if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 58 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 59 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_I; + if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 62 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_IU; + if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 63 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_XU; + if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 314 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_X; + if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 315 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_I; + if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 318 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_IU; + if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 319 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_X; + if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 170 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 171 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_XU; + if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 174 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_I; + if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 175 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_XU; + if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 186 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_IU; + if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 187 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_I; + if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 190 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_IU; + if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 191 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_X; + if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 426 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_X; + if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 427 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_XU; + if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 430 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_I; + if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 431 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_X; + if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 442 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_IU; + if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 443 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_XU; + if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 446 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVPA24X2; + if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_I; + if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 75 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_IU; + if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 331 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_X; + if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 78 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_X; + if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 79 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_XU; + if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 334 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_I; + if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 335 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_IU; + if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 90 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_XU; + if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 91 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_X; + if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 94 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_XU; + if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 95 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_IU; + if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 346 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_I; + if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 347 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_X; + if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 350 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_XU; + if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 351 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_I; + if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 106 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_I; + if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 107 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_IU; + if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 110 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_X; + if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 111 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_IU; + if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 122 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_XU; + if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 123 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_X; + if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 126 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_XU; + if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 127 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 362 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_I; + if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 363 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_I; + if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 875 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_XU; + if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 366 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_IU; + if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 367 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_I; + if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 878 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_IU; + if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 879 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_X; + if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 378 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_X; + if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 379 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_XU; + if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 890 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAQ56S; + if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 891 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 2938 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_JX; + if (Field_ftsf280_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBCI; + if (Field_ftsf280_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBSI; + if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 2939 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 1981 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 957 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_ftsf285ae_slot0_Slot_ae_slot0_get (insn) == 957 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_ftsf287ae_slot0_Slot_ae_slot0_get (insn) == 957 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSL; + if (Field_ftsf288_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BLTUI; + if (Field_ftsf289ae_slot0_Slot_ae_slot0_get (insn) == 382 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32P24_H; + if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 383 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32P24_L; + if (Field_ftsf291ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAP24S_H; + if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf382ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAP24S_L; + if (Field_ftsf293ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf384ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf383ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 202 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_IU; + if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 4298 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf315_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVP48; + if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 4554 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 12746 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf309_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSAI; + if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 2506 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf373ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANY4; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 1482 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf370ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 970 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf376ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANY8; + if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 203 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_I; + if (Field_ftsf305ae_slot0_Slot_ae_slot0_get (insn) == 459 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_I; + if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 715 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_IU; + if (Field_ftsf307ae_slot0_Slot_ae_slot0_get (insn) == 971 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_X; + if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 206 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ32F_IU; + if (Field_ftsf309_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ56_C; + if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 207 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ56_XU; + if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 231 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf386ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTQ48A32S; + if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 219 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLIQ56; + if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 222 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLISQ56S; + if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 475 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAIQ56; + if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 731 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLIQ56; + if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 987 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 2011 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 3035 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 4059 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 478 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVQ56; + if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 1502 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLLSSQ56S; + if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 1502 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf389ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRASQ56; + if (Field_ftsf319ae_slot0_Slot_ae_slot0_get (insn) == 1502 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf388ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLSQ56; + if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 478 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf387ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLLSQ56; + if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 223 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVFQ56; + if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 479 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVTQ56; + if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 735 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLAQ56; + if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 991 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLAQ56; + if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 735 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLLASQ56S; + if (Field_ftsf327ae_slot0_Slot_ae_slot0_get (insn) == 991 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 479 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAAQ56; + if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf379ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ32F_XU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 11 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVGEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 14 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 15 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 23 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_imm8_Slot_ae_slot0_get (insn) == 26 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVNEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 27 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRLI; + if (Field_imm8_Slot_ae_slot0_get (insn) == 30 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 31 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 39 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 42 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 55 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_imm8_Slot_ae_slot0_get (insn) == 71 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 74 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 87 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_CLAMPS; + if (Field_imm8_Slot_ae_slot0_get (insn) == 103 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_imm8_Slot_ae_slot0_get (insn) == 119 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_imm8_Slot_ae_slot0_get (insn) == 139 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 142 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SEXT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 143 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 151 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 154 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 155 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 158 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XOR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 159 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 167 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 215 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MINU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 218 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_r10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ32F_X; + if (Field_imm8_Slot_ae_slot0_get (insn) == 231 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVEQZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 247 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF; + if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_L32R; + if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDBRBA32; + if (Field_r_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNE; + if (Field_r_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNONE; + if (Field_r_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_r_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16SI; + if (Field_r_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BALL; + if (Field_r_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L8UI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDMI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16UI; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBS; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S16I; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BEQ; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S32I; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGEU; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BANY; + if (Field_r_Slot_ae_slot0_get (insn) == 11 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBC; + if (Field_r_Slot_ae_slot0_get (insn) == 12 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGE; + if (Field_r_Slot_ae_slot0_get (insn) == 13 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_ae_slot0_get (insn) == 14 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLTU; + if (Field_r_Slot_ae_slot0_get (insn) == 15 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BNALL; + if (Field_s8_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && + Field_ftsf280_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_s8_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf309_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_C; + if (Field_t_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BEQI; + if (Field_t_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEI; + if (Field_t_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEUI; + if (Field_t_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BNEI; + if (Field_t_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BLTI; + if (Field_t_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_r_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BF; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 50 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 82 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULARFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 114 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 146 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULRFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 178 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 210 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSRFQ32SP24S_L; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 274 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULRFQ32SP24S_H; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 306 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP24S_H; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 338 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSRFQ32SP24S_H; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 402 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULARFQ32SP24S_H; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 434 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP24S_H; + if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 466 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP24S_H; + if (Field_ae_r20_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LTQ56S; + if (Field_ae_s20_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf340ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZAAP24S_HL_LH; + if (Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && + Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MAXABSSP24S; + if (Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && + Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MINABSSP24S; + if (Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && + Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && + Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MINABSSQ56S; + if (Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 0 && + Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && + Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && + Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MAXABSSQ56S; + if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 43 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf335_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULSQ32SP16U_H; + if (Field_ftsf102ae_slot1_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULSFQ32SP16U_H; + if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULAFQ32SP16S_H; + if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MAXBQ56S; + if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MINBQ56S; + if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ae_r32_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_EQQ56; + if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ADDSQ56S; + if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 67 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ANDQ56; + if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 131 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MAXQ56S; + if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 195 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ORQ56; + if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 259 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MINQ56S; + if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 323 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_SUBQ56; + if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 387 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_SUBSQ56S; + if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 451 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_XORQ56; + if (Field_ftsf117ae_slot1_Slot_ae_slot1_get (insn) == 515 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_NANDQ56; + if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 2307 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ABSQ56; + if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 2315 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_NEGSQ56S; + if (Field_ftsf121ae_slot1_Slot_ae_slot1_get (insn) == 1163 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf91_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_SATQ48S; + if (Field_ftsf123ae_slot1_Slot_ae_slot1_get (insn) == 323 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 195 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf352ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_NEGQ56; + if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LEQ56S; + if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf357ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDQ56; + if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAFP24S_HH_LL; + if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAFP24S_HL_LH; + if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAP24S_HH_LL; + if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_HL; + if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAP24S_HL_LH; + if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_LH; + if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_LL; + if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_HH; + if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_HH; + if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_HL; + if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_LH; + if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_HH; + if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_LL; + if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_HL; + if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_LH; + if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_LL; + if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 16 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_HL; + if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 17 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_HH; + if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 18 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_HL; + if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 19 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASFP24S_HH_LL; + if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 20 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_LH; + if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 21 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASFP24S_HL_LH; + if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 22 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASP24S_HH_LL; + if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 23 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASP24S_HL_LH; + if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 24 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_LL; + if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_HH; + if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 26 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_HL; + if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 27 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_LL; + if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 28 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_LH; + if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_HH; + if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 30 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_HL; + if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 31 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_LH; + if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 32 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_LH; + if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 33 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_LL; + if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 34 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_HH; + if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 35 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAFP24S_HH_LL; + if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 36 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_HL; + if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 37 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAFP24S_HL_LH; + if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 38 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAP24S_HH_LL; + if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 39 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAP24S_HL_LH; + if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 40 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_LH; + if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 41 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_HH; + if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 42 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_HL; + if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 43 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_LL; + if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 44 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_LH; + if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 45 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_HH; + if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 46 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_HL; + if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 47 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_LH; + if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 48 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_LL; + if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 49 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_LL; + if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 50 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_HH; + if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 51 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_LL; + if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 52 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_HL; + if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 53 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_HH; + if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 54 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_HL; + if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 55 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_LH; + if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 56 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_LH; + if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 57 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_LL; + if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 58 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_HH; + if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 59 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_LH; + if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 60 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_HL; + if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 61 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_LL; + if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 62 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSFP24S_HH_LL; + if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 63 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSFP24S_HL_LH; + if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 64 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_LL; + if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 65 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSP24S_HH_LL; + if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 66 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSP24S_HL_LH; + if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 67 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASFP24S_HH_LL; + if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 68 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZAAFP24S_HH_LL; + if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 69 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASFP24S_HL_LH; + if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 70 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASP24S_HH_LL; + if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 71 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASP24S_HL_LH; + if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 72 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZAAFP24S_HL_LH; + if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 73 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAFP24S_HH_LL; + if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 74 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAFP24S_HL_LH; + if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 75 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAP24S_HL_LH; + if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 76 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAP24S_HH_LL; + if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 77 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSFP24S_HH_LL; + if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 78 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSFP24S_HL_LH; + if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 79 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSP24S_HH_LL; + if (Field_ftsf208ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZAAP24S_HH_LL; + if (Field_ftsf20ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MAXBP24S; + if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZSSP24S_HL_LH; + if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MINBP24S; + if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVFP48; + if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ADDP24; + if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 69 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MAXP24S; + if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ADDSP24S; + if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MINP24S; + if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 84 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_NANDP48; + if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 85 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ORP48; + if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 36 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ANDP48; + if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 37 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_HH; + if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 52 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_HL; + if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 53 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_LL; + if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 100 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_LH; + if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 101 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SUBP24; + if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 116 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SUBSP24S; + if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 117 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_XORP48; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVTP48; + if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 24 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ABSP24; + if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 88 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_NEGP24; + if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 152 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_NEGSP24S; + if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 216 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf333ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 88 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf359ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ZEROP48; + if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 704 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVP48; + if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 708 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16ASYM; + if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 712 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16SYM; + if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 716 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLSSP24S; + if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 720 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLSP24; + if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 724 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRASP24; + if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 728 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRLSP24; + if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 732 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP16; + if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 24 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf356ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ABSSP24S; + if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_EQP24; + if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LTP24S; + if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MOVFP24X2; + if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf355ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MOVTP24X2; + if (Field_ftsf61_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULAFS32P16S_HH; + if (Field_ftsf62ae_slot1_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LEP24S; + if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 97 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP16Q48ASYM; + if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 101 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP16Q48SYM; + if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 53 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf345ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP24Q48ASYM; + if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf347ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP24Q48SYM; + if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLIP24; + if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLISP24S; + if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRAIP24; + if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRLIP24; + if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16S_L; + if (Field_ftsf70ae_slot1_Slot_ae_slot1_get (insn) == 39 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16U_H; + if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 71 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16U_L; + if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 103 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_H; + if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 135 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_H; + if (Field_ftsf74ae_slot1_Slot_ae_slot1_get (insn) == 167 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 199 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16S_H; + if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 231 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16S_L; + if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 263 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 295 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16U_H; + if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 327 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16U_L; + if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 359 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 391 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_H; + if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 423 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16U_H; + if (Field_ftsf83ae_slot1_Slot_ae_slot1_get (insn) == 455 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 487 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16S_H; + if (Field_ftsf85ae_slot1_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16S_L; + if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 43 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16U_L; + if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 75 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSQ32SP16S_H; + if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 107 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 139 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 331 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf55_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_CVTQ48P24S_H; + if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 363 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf358ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ZEROQ56; + if (Field_ftsf93ae_slot1_Slot_ae_slot1_get (insn) == 203 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r10_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_CVTQ48P24S_L; + if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 1803 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVQ56; + if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 1835 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSQ32ASYM; + if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 939 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSQ32SYM; + if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 491 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf351_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCQ32; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LL; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0xffffff00) >> 8); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xffffff00) | ((slotbuf[0] & 0xffffff) << 8); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); +} + +static void +Slot_ae_format_Format_ae_slot1_10_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xfffffc00) >> 10); + slotbuf[0] = (slotbuf[0] & ~0x400000) | ((insn[1] & 0x1) << 22); +} + +static void +Slot_ae_format_Format_ae_slot1_10_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfffffc00) | ((slotbuf[0] & 0x3fffff) << 10); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x400000) >> 22); +} + +static void +Slot_ae_format_Format_ae_slot0_33_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0xffffffe) >> 1); +} + +static void +Slot_ae_format_Format_ae_slot0_33_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xffffffe) | ((slotbuf[0] & 0x7ffffff) << 1); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_ae_r3_Slot_inst_get, + Field_ae_s_non_samt_Slot_inst_get, + Field_ae_s3_Slot_inst_get, + Field_ae_r32_Slot_inst_get, + Field_ae_samt_s_t_Slot_inst_get, + Field_ae_r20_Slot_inst_get, + Field_ae_r10_Slot_inst_get, + Field_ae_s20_Slot_inst_get, + Field_ae_fld_ohba_Slot_inst_get, + Field_ae_fld_ohba2_Slot_inst_get, + 0, + Field_ftsf11_Slot_inst_get, + Field_ftsf12_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_ae_r3_Slot_inst_set, + Field_ae_s_non_samt_Slot_inst_set, + Field_ae_s3_Slot_inst_set, + Field_ae_r32_Slot_inst_set, + Field_ae_samt_s_t_Slot_inst_set, + Field_ae_r20_Slot_inst_set, + Field_ae_r10_Slot_inst_set, + Field_ae_s20_Slot_inst_set, + Field_ae_fld_ohba_Slot_inst_set, + Field_ae_fld_ohba2_Slot_inst_set, + 0, + Field_ftsf11_Slot_inst_set, + Field_ftsf12_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_get, + Field_s3to1_Slot_inst16a_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16a_set, + Field_s3to1_Slot_inst16a_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_get, + Field_s3to1_Slot_inst16b_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_inst16b_set, + Field_s3to1_Slot_inst16b_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot1_get, + 0, + Field_ae_r20_Slot_ae_slot1_get, + Field_ae_r10_Slot_ae_slot1_get, + Field_ae_s20_Slot_ae_slot1_get, + 0, + 0, + Field_op0_s3_Slot_ae_slot1_get, + Field_ftsf11_Slot_ae_slot1_get, + Field_ftsf12_Slot_ae_slot1_get, + Field_ftsf13_Slot_ae_slot1_get, + Field_ftsf20ae_slot1_Slot_ae_slot1_get, + Field_ftsf21ae_slot1_Slot_ae_slot1_get, + Field_ftsf22ae_slot1_Slot_ae_slot1_get, + Field_ftsf23ae_slot1_Slot_ae_slot1_get, + Field_ftsf24ae_slot1_Slot_ae_slot1_get, + Field_ftsf25ae_slot1_Slot_ae_slot1_get, + Field_ftsf26ae_slot1_Slot_ae_slot1_get, + Field_ftsf27ae_slot1_Slot_ae_slot1_get, + Field_ftsf28ae_slot1_Slot_ae_slot1_get, + Field_ftsf29ae_slot1_Slot_ae_slot1_get, + Field_ftsf30ae_slot1_Slot_ae_slot1_get, + Field_ftsf31ae_slot1_Slot_ae_slot1_get, + Field_ftsf32ae_slot1_Slot_ae_slot1_get, + Field_ftsf33ae_slot1_Slot_ae_slot1_get, + Field_ftsf34ae_slot1_Slot_ae_slot1_get, + Field_ftsf35ae_slot1_Slot_ae_slot1_get, + Field_ftsf36ae_slot1_Slot_ae_slot1_get, + Field_ftsf37ae_slot1_Slot_ae_slot1_get, + Field_ftsf38ae_slot1_Slot_ae_slot1_get, + Field_ftsf40ae_slot1_Slot_ae_slot1_get, + Field_ftsf41ae_slot1_Slot_ae_slot1_get, + Field_ftsf42ae_slot1_Slot_ae_slot1_get, + Field_ftsf43ae_slot1_Slot_ae_slot1_get, + Field_ftsf45ae_slot1_Slot_ae_slot1_get, + Field_ftsf47ae_slot1_Slot_ae_slot1_get, + Field_ftsf48ae_slot1_Slot_ae_slot1_get, + Field_ftsf49ae_slot1_Slot_ae_slot1_get, + Field_ftsf50ae_slot1_Slot_ae_slot1_get, + Field_ftsf51ae_slot1_Slot_ae_slot1_get, + Field_ftsf52ae_slot1_Slot_ae_slot1_get, + Field_ftsf53ae_slot1_Slot_ae_slot1_get, + Field_ftsf54ae_slot1_Slot_ae_slot1_get, + Field_ftsf55_Slot_ae_slot1_get, + Field_ftsf56ae_slot1_Slot_ae_slot1_get, + Field_ftsf57ae_slot1_Slot_ae_slot1_get, + Field_ftsf58ae_slot1_Slot_ae_slot1_get, + Field_ftsf60ae_slot1_Slot_ae_slot1_get, + Field_ftsf61_Slot_ae_slot1_get, + Field_ftsf62ae_slot1_Slot_ae_slot1_get, + Field_ftsf63ae_slot1_Slot_ae_slot1_get, + Field_ftsf64ae_slot1_Slot_ae_slot1_get, + Field_ftsf66ae_slot1_Slot_ae_slot1_get, + Field_ftsf68ae_slot1_Slot_ae_slot1_get, + Field_ftsf69ae_slot1_Slot_ae_slot1_get, + Field_ftsf70ae_slot1_Slot_ae_slot1_get, + Field_ftsf71ae_slot1_Slot_ae_slot1_get, + Field_ftsf72ae_slot1_Slot_ae_slot1_get, + Field_ftsf73ae_slot1_Slot_ae_slot1_get, + Field_ftsf74ae_slot1_Slot_ae_slot1_get, + Field_ftsf75ae_slot1_Slot_ae_slot1_get, + Field_ftsf76ae_slot1_Slot_ae_slot1_get, + Field_ftsf77ae_slot1_Slot_ae_slot1_get, + Field_ftsf78ae_slot1_Slot_ae_slot1_get, + Field_ftsf79ae_slot1_Slot_ae_slot1_get, + Field_ftsf80ae_slot1_Slot_ae_slot1_get, + Field_ftsf81ae_slot1_Slot_ae_slot1_get, + Field_ftsf82ae_slot1_Slot_ae_slot1_get, + Field_ftsf83ae_slot1_Slot_ae_slot1_get, + Field_ftsf84ae_slot1_Slot_ae_slot1_get, + Field_ftsf85ae_slot1_Slot_ae_slot1_get, + Field_ftsf86ae_slot1_Slot_ae_slot1_get, + Field_ftsf87ae_slot1_Slot_ae_slot1_get, + Field_ftsf88ae_slot1_Slot_ae_slot1_get, + Field_ftsf89ae_slot1_Slot_ae_slot1_get, + Field_ftsf90ae_slot1_Slot_ae_slot1_get, + Field_ftsf91_Slot_ae_slot1_get, + Field_ftsf92ae_slot1_Slot_ae_slot1_get, + Field_ftsf93ae_slot1_Slot_ae_slot1_get, + Field_ftsf94ae_slot1_Slot_ae_slot1_get, + Field_ftsf96ae_slot1_Slot_ae_slot1_get, + Field_ftsf97ae_slot1_Slot_ae_slot1_get, + Field_ftsf99ae_slot1_Slot_ae_slot1_get, + Field_ftsf101ae_slot1_Slot_ae_slot1_get, + Field_ftsf102ae_slot1_Slot_ae_slot1_get, + Field_ftsf103ae_slot1_Slot_ae_slot1_get, + Field_ftsf106ae_slot1_Slot_ae_slot1_get, + Field_ftsf107ae_slot1_Slot_ae_slot1_get, + Field_ftsf108ae_slot1_Slot_ae_slot1_get, + Field_ftsf109ae_slot1_Slot_ae_slot1_get, + Field_ftsf110ae_slot1_Slot_ae_slot1_get, + Field_ftsf111ae_slot1_Slot_ae_slot1_get, + Field_ftsf112ae_slot1_Slot_ae_slot1_get, + Field_ftsf113ae_slot1_Slot_ae_slot1_get, + Field_ftsf114ae_slot1_Slot_ae_slot1_get, + Field_ftsf115ae_slot1_Slot_ae_slot1_get, + Field_ftsf116ae_slot1_Slot_ae_slot1_get, + Field_ftsf117ae_slot1_Slot_ae_slot1_get, + Field_ftsf118ae_slot1_Slot_ae_slot1_get, + Field_ftsf120ae_slot1_Slot_ae_slot1_get, + Field_ftsf121ae_slot1_Slot_ae_slot1_get, + Field_ftsf123ae_slot1_Slot_ae_slot1_get, + Field_ftsf124ae_slot1_Slot_ae_slot1_get, + Field_ftsf125ae_slot1_Slot_ae_slot1_get, + Field_ftsf126ae_slot1_Slot_ae_slot1_get, + Field_ftsf127ae_slot1_Slot_ae_slot1_get, + Field_ftsf128ae_slot1_Slot_ae_slot1_get, + Field_ftsf129ae_slot1_Slot_ae_slot1_get, + Field_ftsf130ae_slot1_Slot_ae_slot1_get, + Field_ftsf131ae_slot1_Slot_ae_slot1_get, + Field_ftsf132ae_slot1_Slot_ae_slot1_get, + Field_ftsf133ae_slot1_Slot_ae_slot1_get, + Field_ftsf134ae_slot1_Slot_ae_slot1_get, + Field_ftsf135ae_slot1_Slot_ae_slot1_get, + Field_ftsf136ae_slot1_Slot_ae_slot1_get, + Field_ftsf137ae_slot1_Slot_ae_slot1_get, + Field_ftsf138ae_slot1_Slot_ae_slot1_get, + Field_ftsf139ae_slot1_Slot_ae_slot1_get, + Field_ftsf140ae_slot1_Slot_ae_slot1_get, + Field_ftsf141ae_slot1_Slot_ae_slot1_get, + Field_ftsf142ae_slot1_Slot_ae_slot1_get, + Field_ftsf143ae_slot1_Slot_ae_slot1_get, + Field_ftsf144ae_slot1_Slot_ae_slot1_get, + Field_ftsf145ae_slot1_Slot_ae_slot1_get, + Field_ftsf146ae_slot1_Slot_ae_slot1_get, + Field_ftsf147ae_slot1_Slot_ae_slot1_get, + Field_ftsf148ae_slot1_Slot_ae_slot1_get, + Field_ftsf149ae_slot1_Slot_ae_slot1_get, + Field_ftsf150ae_slot1_Slot_ae_slot1_get, + Field_ftsf151ae_slot1_Slot_ae_slot1_get, + Field_ftsf152ae_slot1_Slot_ae_slot1_get, + Field_ftsf153ae_slot1_Slot_ae_slot1_get, + Field_ftsf154ae_slot1_Slot_ae_slot1_get, + Field_ftsf155ae_slot1_Slot_ae_slot1_get, + Field_ftsf156ae_slot1_Slot_ae_slot1_get, + Field_ftsf157ae_slot1_Slot_ae_slot1_get, + Field_ftsf158ae_slot1_Slot_ae_slot1_get, + Field_ftsf159ae_slot1_Slot_ae_slot1_get, + Field_ftsf160ae_slot1_Slot_ae_slot1_get, + Field_ftsf161ae_slot1_Slot_ae_slot1_get, + Field_ftsf162ae_slot1_Slot_ae_slot1_get, + Field_ftsf163ae_slot1_Slot_ae_slot1_get, + Field_ftsf164ae_slot1_Slot_ae_slot1_get, + Field_ftsf165ae_slot1_Slot_ae_slot1_get, + Field_ftsf166ae_slot1_Slot_ae_slot1_get, + Field_ftsf167ae_slot1_Slot_ae_slot1_get, + Field_ftsf168ae_slot1_Slot_ae_slot1_get, + Field_ftsf169ae_slot1_Slot_ae_slot1_get, + Field_ftsf170ae_slot1_Slot_ae_slot1_get, + Field_ftsf171ae_slot1_Slot_ae_slot1_get, + Field_ftsf172ae_slot1_Slot_ae_slot1_get, + Field_ftsf173ae_slot1_Slot_ae_slot1_get, + Field_ftsf174ae_slot1_Slot_ae_slot1_get, + Field_ftsf175ae_slot1_Slot_ae_slot1_get, + Field_ftsf176ae_slot1_Slot_ae_slot1_get, + Field_ftsf177ae_slot1_Slot_ae_slot1_get, + Field_ftsf178ae_slot1_Slot_ae_slot1_get, + Field_ftsf179ae_slot1_Slot_ae_slot1_get, + Field_ftsf180ae_slot1_Slot_ae_slot1_get, + Field_ftsf181ae_slot1_Slot_ae_slot1_get, + Field_ftsf182ae_slot1_Slot_ae_slot1_get, + Field_ftsf183ae_slot1_Slot_ae_slot1_get, + Field_ftsf184ae_slot1_Slot_ae_slot1_get, + Field_ftsf185ae_slot1_Slot_ae_slot1_get, + Field_ftsf186ae_slot1_Slot_ae_slot1_get, + Field_ftsf187ae_slot1_Slot_ae_slot1_get, + Field_ftsf188ae_slot1_Slot_ae_slot1_get, + Field_ftsf189ae_slot1_Slot_ae_slot1_get, + Field_ftsf190ae_slot1_Slot_ae_slot1_get, + Field_ftsf191ae_slot1_Slot_ae_slot1_get, + Field_ftsf192ae_slot1_Slot_ae_slot1_get, + Field_ftsf193ae_slot1_Slot_ae_slot1_get, + Field_ftsf194ae_slot1_Slot_ae_slot1_get, + Field_ftsf195ae_slot1_Slot_ae_slot1_get, + Field_ftsf196ae_slot1_Slot_ae_slot1_get, + Field_ftsf197ae_slot1_Slot_ae_slot1_get, + Field_ftsf198ae_slot1_Slot_ae_slot1_get, + Field_ftsf199ae_slot1_Slot_ae_slot1_get, + Field_ftsf200ae_slot1_Slot_ae_slot1_get, + Field_ftsf201ae_slot1_Slot_ae_slot1_get, + Field_ftsf202ae_slot1_Slot_ae_slot1_get, + Field_ftsf203ae_slot1_Slot_ae_slot1_get, + Field_ftsf204ae_slot1_Slot_ae_slot1_get, + Field_ftsf205ae_slot1_Slot_ae_slot1_get, + Field_ftsf206ae_slot1_Slot_ae_slot1_get, + Field_ftsf207ae_slot1_Slot_ae_slot1_get, + Field_ftsf208ae_slot1_Slot_ae_slot1_get, + Field_ftsf210ae_slot1_Slot_ae_slot1_get, + Field_ftsf333ae_slot1_Slot_ae_slot1_get, + Field_ftsf334ae_slot1_Slot_ae_slot1_get, + Field_ftsf335_Slot_ae_slot1_get, + Field_ftsf336ae_slot1_Slot_ae_slot1_get, + Field_ftsf337ae_slot1_Slot_ae_slot1_get, + Field_ftsf339ae_slot1_Slot_ae_slot1_get, + Field_ftsf340ae_slot1_Slot_ae_slot1_get, + Field_ftsf341ae_slot1_Slot_ae_slot1_get, + Field_ftsf342ae_slot1_Slot_ae_slot1_get, + Field_ftsf343ae_slot1_Slot_ae_slot1_get, + Field_ftsf344ae_slot1_Slot_ae_slot1_get, + Field_ftsf345ae_slot1_Slot_ae_slot1_get, + Field_ftsf347ae_slot1_Slot_ae_slot1_get, + Field_ftsf348ae_slot1_Slot_ae_slot1_get, + Field_ftsf349ae_slot1_Slot_ae_slot1_get, + Field_ftsf350ae_slot1_Slot_ae_slot1_get, + Field_ftsf351_Slot_ae_slot1_get, + Field_ftsf352ae_slot1_Slot_ae_slot1_get, + Field_ftsf354ae_slot1_Slot_ae_slot1_get, + Field_ftsf355ae_slot1_Slot_ae_slot1_get, + Field_ftsf356ae_slot1_Slot_ae_slot1_get, + Field_ftsf357ae_slot1_Slot_ae_slot1_get, + Field_ftsf358ae_slot1_Slot_ae_slot1_get, + Field_ftsf359ae_slot1_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_mul32x24fld_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s3_s3_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld19_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld22_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld24_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld65_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld66_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld68_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld69_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld74_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld79_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld88_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld90_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld91_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get, + Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot1_set, + 0, + Field_ae_r20_Slot_ae_slot1_set, + Field_ae_r10_Slot_ae_slot1_set, + Field_ae_s20_Slot_ae_slot1_set, + 0, + 0, + Field_op0_s3_Slot_ae_slot1_set, + Field_ftsf11_Slot_ae_slot1_set, + Field_ftsf12_Slot_ae_slot1_set, + Field_ftsf13_Slot_ae_slot1_set, + Field_ftsf20ae_slot1_Slot_ae_slot1_set, + Field_ftsf21ae_slot1_Slot_ae_slot1_set, + Field_ftsf22ae_slot1_Slot_ae_slot1_set, + Field_ftsf23ae_slot1_Slot_ae_slot1_set, + Field_ftsf24ae_slot1_Slot_ae_slot1_set, + Field_ftsf25ae_slot1_Slot_ae_slot1_set, + Field_ftsf26ae_slot1_Slot_ae_slot1_set, + Field_ftsf27ae_slot1_Slot_ae_slot1_set, + Field_ftsf28ae_slot1_Slot_ae_slot1_set, + Field_ftsf29ae_slot1_Slot_ae_slot1_set, + Field_ftsf30ae_slot1_Slot_ae_slot1_set, + Field_ftsf31ae_slot1_Slot_ae_slot1_set, + Field_ftsf32ae_slot1_Slot_ae_slot1_set, + Field_ftsf33ae_slot1_Slot_ae_slot1_set, + Field_ftsf34ae_slot1_Slot_ae_slot1_set, + Field_ftsf35ae_slot1_Slot_ae_slot1_set, + Field_ftsf36ae_slot1_Slot_ae_slot1_set, + Field_ftsf37ae_slot1_Slot_ae_slot1_set, + Field_ftsf38ae_slot1_Slot_ae_slot1_set, + Field_ftsf40ae_slot1_Slot_ae_slot1_set, + Field_ftsf41ae_slot1_Slot_ae_slot1_set, + Field_ftsf42ae_slot1_Slot_ae_slot1_set, + Field_ftsf43ae_slot1_Slot_ae_slot1_set, + Field_ftsf45ae_slot1_Slot_ae_slot1_set, + Field_ftsf47ae_slot1_Slot_ae_slot1_set, + Field_ftsf48ae_slot1_Slot_ae_slot1_set, + Field_ftsf49ae_slot1_Slot_ae_slot1_set, + Field_ftsf50ae_slot1_Slot_ae_slot1_set, + Field_ftsf51ae_slot1_Slot_ae_slot1_set, + Field_ftsf52ae_slot1_Slot_ae_slot1_set, + Field_ftsf53ae_slot1_Slot_ae_slot1_set, + Field_ftsf54ae_slot1_Slot_ae_slot1_set, + Field_ftsf55_Slot_ae_slot1_set, + Field_ftsf56ae_slot1_Slot_ae_slot1_set, + Field_ftsf57ae_slot1_Slot_ae_slot1_set, + Field_ftsf58ae_slot1_Slot_ae_slot1_set, + Field_ftsf60ae_slot1_Slot_ae_slot1_set, + Field_ftsf61_Slot_ae_slot1_set, + Field_ftsf62ae_slot1_Slot_ae_slot1_set, + Field_ftsf63ae_slot1_Slot_ae_slot1_set, + Field_ftsf64ae_slot1_Slot_ae_slot1_set, + Field_ftsf66ae_slot1_Slot_ae_slot1_set, + Field_ftsf68ae_slot1_Slot_ae_slot1_set, + Field_ftsf69ae_slot1_Slot_ae_slot1_set, + Field_ftsf70ae_slot1_Slot_ae_slot1_set, + Field_ftsf71ae_slot1_Slot_ae_slot1_set, + Field_ftsf72ae_slot1_Slot_ae_slot1_set, + Field_ftsf73ae_slot1_Slot_ae_slot1_set, + Field_ftsf74ae_slot1_Slot_ae_slot1_set, + Field_ftsf75ae_slot1_Slot_ae_slot1_set, + Field_ftsf76ae_slot1_Slot_ae_slot1_set, + Field_ftsf77ae_slot1_Slot_ae_slot1_set, + Field_ftsf78ae_slot1_Slot_ae_slot1_set, + Field_ftsf79ae_slot1_Slot_ae_slot1_set, + Field_ftsf80ae_slot1_Slot_ae_slot1_set, + Field_ftsf81ae_slot1_Slot_ae_slot1_set, + Field_ftsf82ae_slot1_Slot_ae_slot1_set, + Field_ftsf83ae_slot1_Slot_ae_slot1_set, + Field_ftsf84ae_slot1_Slot_ae_slot1_set, + Field_ftsf85ae_slot1_Slot_ae_slot1_set, + Field_ftsf86ae_slot1_Slot_ae_slot1_set, + Field_ftsf87ae_slot1_Slot_ae_slot1_set, + Field_ftsf88ae_slot1_Slot_ae_slot1_set, + Field_ftsf89ae_slot1_Slot_ae_slot1_set, + Field_ftsf90ae_slot1_Slot_ae_slot1_set, + Field_ftsf91_Slot_ae_slot1_set, + Field_ftsf92ae_slot1_Slot_ae_slot1_set, + Field_ftsf93ae_slot1_Slot_ae_slot1_set, + Field_ftsf94ae_slot1_Slot_ae_slot1_set, + Field_ftsf96ae_slot1_Slot_ae_slot1_set, + Field_ftsf97ae_slot1_Slot_ae_slot1_set, + Field_ftsf99ae_slot1_Slot_ae_slot1_set, + Field_ftsf101ae_slot1_Slot_ae_slot1_set, + Field_ftsf102ae_slot1_Slot_ae_slot1_set, + Field_ftsf103ae_slot1_Slot_ae_slot1_set, + Field_ftsf106ae_slot1_Slot_ae_slot1_set, + Field_ftsf107ae_slot1_Slot_ae_slot1_set, + Field_ftsf108ae_slot1_Slot_ae_slot1_set, + Field_ftsf109ae_slot1_Slot_ae_slot1_set, + Field_ftsf110ae_slot1_Slot_ae_slot1_set, + Field_ftsf111ae_slot1_Slot_ae_slot1_set, + Field_ftsf112ae_slot1_Slot_ae_slot1_set, + Field_ftsf113ae_slot1_Slot_ae_slot1_set, + Field_ftsf114ae_slot1_Slot_ae_slot1_set, + Field_ftsf115ae_slot1_Slot_ae_slot1_set, + Field_ftsf116ae_slot1_Slot_ae_slot1_set, + Field_ftsf117ae_slot1_Slot_ae_slot1_set, + Field_ftsf118ae_slot1_Slot_ae_slot1_set, + Field_ftsf120ae_slot1_Slot_ae_slot1_set, + Field_ftsf121ae_slot1_Slot_ae_slot1_set, + Field_ftsf123ae_slot1_Slot_ae_slot1_set, + Field_ftsf124ae_slot1_Slot_ae_slot1_set, + Field_ftsf125ae_slot1_Slot_ae_slot1_set, + Field_ftsf126ae_slot1_Slot_ae_slot1_set, + Field_ftsf127ae_slot1_Slot_ae_slot1_set, + Field_ftsf128ae_slot1_Slot_ae_slot1_set, + Field_ftsf129ae_slot1_Slot_ae_slot1_set, + Field_ftsf130ae_slot1_Slot_ae_slot1_set, + Field_ftsf131ae_slot1_Slot_ae_slot1_set, + Field_ftsf132ae_slot1_Slot_ae_slot1_set, + Field_ftsf133ae_slot1_Slot_ae_slot1_set, + Field_ftsf134ae_slot1_Slot_ae_slot1_set, + Field_ftsf135ae_slot1_Slot_ae_slot1_set, + Field_ftsf136ae_slot1_Slot_ae_slot1_set, + Field_ftsf137ae_slot1_Slot_ae_slot1_set, + Field_ftsf138ae_slot1_Slot_ae_slot1_set, + Field_ftsf139ae_slot1_Slot_ae_slot1_set, + Field_ftsf140ae_slot1_Slot_ae_slot1_set, + Field_ftsf141ae_slot1_Slot_ae_slot1_set, + Field_ftsf142ae_slot1_Slot_ae_slot1_set, + Field_ftsf143ae_slot1_Slot_ae_slot1_set, + Field_ftsf144ae_slot1_Slot_ae_slot1_set, + Field_ftsf145ae_slot1_Slot_ae_slot1_set, + Field_ftsf146ae_slot1_Slot_ae_slot1_set, + Field_ftsf147ae_slot1_Slot_ae_slot1_set, + Field_ftsf148ae_slot1_Slot_ae_slot1_set, + Field_ftsf149ae_slot1_Slot_ae_slot1_set, + Field_ftsf150ae_slot1_Slot_ae_slot1_set, + Field_ftsf151ae_slot1_Slot_ae_slot1_set, + Field_ftsf152ae_slot1_Slot_ae_slot1_set, + Field_ftsf153ae_slot1_Slot_ae_slot1_set, + Field_ftsf154ae_slot1_Slot_ae_slot1_set, + Field_ftsf155ae_slot1_Slot_ae_slot1_set, + Field_ftsf156ae_slot1_Slot_ae_slot1_set, + Field_ftsf157ae_slot1_Slot_ae_slot1_set, + Field_ftsf158ae_slot1_Slot_ae_slot1_set, + Field_ftsf159ae_slot1_Slot_ae_slot1_set, + Field_ftsf160ae_slot1_Slot_ae_slot1_set, + Field_ftsf161ae_slot1_Slot_ae_slot1_set, + Field_ftsf162ae_slot1_Slot_ae_slot1_set, + Field_ftsf163ae_slot1_Slot_ae_slot1_set, + Field_ftsf164ae_slot1_Slot_ae_slot1_set, + Field_ftsf165ae_slot1_Slot_ae_slot1_set, + Field_ftsf166ae_slot1_Slot_ae_slot1_set, + Field_ftsf167ae_slot1_Slot_ae_slot1_set, + Field_ftsf168ae_slot1_Slot_ae_slot1_set, + Field_ftsf169ae_slot1_Slot_ae_slot1_set, + Field_ftsf170ae_slot1_Slot_ae_slot1_set, + Field_ftsf171ae_slot1_Slot_ae_slot1_set, + Field_ftsf172ae_slot1_Slot_ae_slot1_set, + Field_ftsf173ae_slot1_Slot_ae_slot1_set, + Field_ftsf174ae_slot1_Slot_ae_slot1_set, + Field_ftsf175ae_slot1_Slot_ae_slot1_set, + Field_ftsf176ae_slot1_Slot_ae_slot1_set, + Field_ftsf177ae_slot1_Slot_ae_slot1_set, + Field_ftsf178ae_slot1_Slot_ae_slot1_set, + Field_ftsf179ae_slot1_Slot_ae_slot1_set, + Field_ftsf180ae_slot1_Slot_ae_slot1_set, + Field_ftsf181ae_slot1_Slot_ae_slot1_set, + Field_ftsf182ae_slot1_Slot_ae_slot1_set, + Field_ftsf183ae_slot1_Slot_ae_slot1_set, + Field_ftsf184ae_slot1_Slot_ae_slot1_set, + Field_ftsf185ae_slot1_Slot_ae_slot1_set, + Field_ftsf186ae_slot1_Slot_ae_slot1_set, + Field_ftsf187ae_slot1_Slot_ae_slot1_set, + Field_ftsf188ae_slot1_Slot_ae_slot1_set, + Field_ftsf189ae_slot1_Slot_ae_slot1_set, + Field_ftsf190ae_slot1_Slot_ae_slot1_set, + Field_ftsf191ae_slot1_Slot_ae_slot1_set, + Field_ftsf192ae_slot1_Slot_ae_slot1_set, + Field_ftsf193ae_slot1_Slot_ae_slot1_set, + Field_ftsf194ae_slot1_Slot_ae_slot1_set, + Field_ftsf195ae_slot1_Slot_ae_slot1_set, + Field_ftsf196ae_slot1_Slot_ae_slot1_set, + Field_ftsf197ae_slot1_Slot_ae_slot1_set, + Field_ftsf198ae_slot1_Slot_ae_slot1_set, + Field_ftsf199ae_slot1_Slot_ae_slot1_set, + Field_ftsf200ae_slot1_Slot_ae_slot1_set, + Field_ftsf201ae_slot1_Slot_ae_slot1_set, + Field_ftsf202ae_slot1_Slot_ae_slot1_set, + Field_ftsf203ae_slot1_Slot_ae_slot1_set, + Field_ftsf204ae_slot1_Slot_ae_slot1_set, + Field_ftsf205ae_slot1_Slot_ae_slot1_set, + Field_ftsf206ae_slot1_Slot_ae_slot1_set, + Field_ftsf207ae_slot1_Slot_ae_slot1_set, + Field_ftsf208ae_slot1_Slot_ae_slot1_set, + Field_ftsf210ae_slot1_Slot_ae_slot1_set, + Field_ftsf333ae_slot1_Slot_ae_slot1_set, + Field_ftsf334ae_slot1_Slot_ae_slot1_set, + Field_ftsf335_Slot_ae_slot1_set, + Field_ftsf336ae_slot1_Slot_ae_slot1_set, + Field_ftsf337ae_slot1_Slot_ae_slot1_set, + Field_ftsf339ae_slot1_Slot_ae_slot1_set, + Field_ftsf340ae_slot1_Slot_ae_slot1_set, + Field_ftsf341ae_slot1_Slot_ae_slot1_set, + Field_ftsf342ae_slot1_Slot_ae_slot1_set, + Field_ftsf343ae_slot1_Slot_ae_slot1_set, + Field_ftsf344ae_slot1_Slot_ae_slot1_set, + Field_ftsf345ae_slot1_Slot_ae_slot1_set, + Field_ftsf347ae_slot1_Slot_ae_slot1_set, + Field_ftsf348ae_slot1_Slot_ae_slot1_set, + Field_ftsf349ae_slot1_Slot_ae_slot1_set, + Field_ftsf350ae_slot1_Slot_ae_slot1_set, + Field_ftsf351_Slot_ae_slot1_set, + Field_ftsf352ae_slot1_Slot_ae_slot1_set, + Field_ftsf354ae_slot1_Slot_ae_slot1_set, + Field_ftsf355ae_slot1_Slot_ae_slot1_set, + Field_ftsf356ae_slot1_Slot_ae_slot1_set, + Field_ftsf357ae_slot1_Slot_ae_slot1_set, + Field_ftsf358ae_slot1_Slot_ae_slot1_set, + Field_ftsf359ae_slot1_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_mul32x24fld_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s3_s3_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld19_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld22_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld24_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld65_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld66_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld68_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld69_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld74_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld79_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld88_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld90_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld91_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set, + Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + Field_bbi_Slot_ae_slot0_get, + Field_imm12_Slot_ae_slot0_get, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae_slot0_get, + 0, + 0, + Field_s8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot0_get, + Field_ae_samt_s_t_Slot_ae_slot0_get, + Field_ae_r20_Slot_ae_slot0_get, + Field_ae_r10_Slot_ae_slot0_get, + Field_ae_s20_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_ftsf11_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_ae_slot0_get, + Field_ftsf211ae_slot0_Slot_ae_slot0_get, + Field_ftsf212ae_slot0_Slot_ae_slot0_get, + Field_ftsf213ae_slot0_Slot_ae_slot0_get, + Field_ftsf214ae_slot0_Slot_ae_slot0_get, + Field_ftsf215ae_slot0_Slot_ae_slot0_get, + Field_ftsf217ae_slot0_Slot_ae_slot0_get, + Field_ftsf218ae_slot0_Slot_ae_slot0_get, + Field_ftsf219ae_slot0_Slot_ae_slot0_get, + Field_ftsf220ae_slot0_Slot_ae_slot0_get, + Field_ftsf221ae_slot0_Slot_ae_slot0_get, + Field_ftsf222ae_slot0_Slot_ae_slot0_get, + Field_ftsf223ae_slot0_Slot_ae_slot0_get, + Field_ftsf224ae_slot0_Slot_ae_slot0_get, + Field_ftsf225ae_slot0_Slot_ae_slot0_get, + Field_ftsf226ae_slot0_Slot_ae_slot0_get, + Field_ftsf227ae_slot0_Slot_ae_slot0_get, + Field_ftsf228ae_slot0_Slot_ae_slot0_get, + Field_ftsf229ae_slot0_Slot_ae_slot0_get, + Field_ftsf230ae_slot0_Slot_ae_slot0_get, + Field_ftsf231ae_slot0_Slot_ae_slot0_get, + Field_ftsf232ae_slot0_Slot_ae_slot0_get, + Field_ftsf233ae_slot0_Slot_ae_slot0_get, + Field_ftsf234ae_slot0_Slot_ae_slot0_get, + Field_ftsf235ae_slot0_Slot_ae_slot0_get, + Field_ftsf236ae_slot0_Slot_ae_slot0_get, + Field_ftsf237ae_slot0_Slot_ae_slot0_get, + Field_ftsf238ae_slot0_Slot_ae_slot0_get, + Field_ftsf239ae_slot0_Slot_ae_slot0_get, + Field_ftsf240ae_slot0_Slot_ae_slot0_get, + Field_ftsf241ae_slot0_Slot_ae_slot0_get, + Field_ftsf242ae_slot0_Slot_ae_slot0_get, + Field_ftsf243ae_slot0_Slot_ae_slot0_get, + Field_ftsf244ae_slot0_Slot_ae_slot0_get, + Field_ftsf245ae_slot0_Slot_ae_slot0_get, + Field_ftsf246ae_slot0_Slot_ae_slot0_get, + Field_ftsf247ae_slot0_Slot_ae_slot0_get, + Field_ftsf248ae_slot0_Slot_ae_slot0_get, + Field_ftsf249ae_slot0_Slot_ae_slot0_get, + Field_ftsf250ae_slot0_Slot_ae_slot0_get, + Field_ftsf251ae_slot0_Slot_ae_slot0_get, + Field_ftsf252ae_slot0_Slot_ae_slot0_get, + Field_ftsf253ae_slot0_Slot_ae_slot0_get, + Field_ftsf254ae_slot0_Slot_ae_slot0_get, + Field_ftsf255ae_slot0_Slot_ae_slot0_get, + Field_ftsf256ae_slot0_Slot_ae_slot0_get, + Field_ftsf257ae_slot0_Slot_ae_slot0_get, + Field_ftsf258ae_slot0_Slot_ae_slot0_get, + Field_ftsf259ae_slot0_Slot_ae_slot0_get, + Field_ftsf260ae_slot0_Slot_ae_slot0_get, + Field_ftsf261ae_slot0_Slot_ae_slot0_get, + Field_ftsf262ae_slot0_Slot_ae_slot0_get, + Field_ftsf263ae_slot0_Slot_ae_slot0_get, + Field_ftsf264ae_slot0_Slot_ae_slot0_get, + Field_ftsf265ae_slot0_Slot_ae_slot0_get, + Field_ftsf266ae_slot0_Slot_ae_slot0_get, + Field_ftsf267ae_slot0_Slot_ae_slot0_get, + Field_ftsf268ae_slot0_Slot_ae_slot0_get, + Field_ftsf269ae_slot0_Slot_ae_slot0_get, + Field_ftsf270ae_slot0_Slot_ae_slot0_get, + Field_ftsf271ae_slot0_Slot_ae_slot0_get, + Field_ftsf272ae_slot0_Slot_ae_slot0_get, + Field_ftsf273ae_slot0_Slot_ae_slot0_get, + Field_ftsf274ae_slot0_Slot_ae_slot0_get, + Field_ftsf275ae_slot0_Slot_ae_slot0_get, + Field_ftsf276ae_slot0_Slot_ae_slot0_get, + Field_ftsf277ae_slot0_Slot_ae_slot0_get, + Field_ftsf278ae_slot0_Slot_ae_slot0_get, + Field_ftsf279ae_slot0_Slot_ae_slot0_get, + Field_ftsf280_Slot_ae_slot0_get, + Field_ftsf281ae_slot0_Slot_ae_slot0_get, + Field_ftsf282ae_slot0_Slot_ae_slot0_get, + Field_ftsf284ae_slot0_Slot_ae_slot0_get, + Field_ftsf285ae_slot0_Slot_ae_slot0_get, + Field_ftsf287ae_slot0_Slot_ae_slot0_get, + Field_ftsf288_Slot_ae_slot0_get, + Field_ftsf289ae_slot0_Slot_ae_slot0_get, + Field_ftsf290ae_slot0_Slot_ae_slot0_get, + Field_ftsf291ae_slot0_Slot_ae_slot0_get, + Field_ftsf292ae_slot0_Slot_ae_slot0_get, + Field_ftsf293ae_slot0_Slot_ae_slot0_get, + Field_ftsf294ae_slot0_Slot_ae_slot0_get, + Field_ftsf295ae_slot0_Slot_ae_slot0_get, + Field_ftsf296ae_slot0_Slot_ae_slot0_get, + Field_ftsf297ae_slot0_Slot_ae_slot0_get, + Field_ftsf298ae_slot0_Slot_ae_slot0_get, + Field_ftsf300ae_slot0_Slot_ae_slot0_get, + Field_ftsf302ae_slot0_Slot_ae_slot0_get, + Field_ftsf304ae_slot0_Slot_ae_slot0_get, + Field_ftsf305ae_slot0_Slot_ae_slot0_get, + Field_ftsf306ae_slot0_Slot_ae_slot0_get, + Field_ftsf307ae_slot0_Slot_ae_slot0_get, + Field_ftsf308ae_slot0_Slot_ae_slot0_get, + Field_ftsf309_Slot_ae_slot0_get, + Field_ftsf310ae_slot0_Slot_ae_slot0_get, + Field_ftsf311ae_slot0_Slot_ae_slot0_get, + Field_ftsf312ae_slot0_Slot_ae_slot0_get, + Field_ftsf313ae_slot0_Slot_ae_slot0_get, + Field_ftsf314ae_slot0_Slot_ae_slot0_get, + Field_ftsf315_Slot_ae_slot0_get, + Field_ftsf316ae_slot0_Slot_ae_slot0_get, + Field_ftsf317ae_slot0_Slot_ae_slot0_get, + Field_ftsf319ae_slot0_Slot_ae_slot0_get, + Field_ftsf320ae_slot0_Slot_ae_slot0_get, + Field_ftsf322ae_slot0_Slot_ae_slot0_get, + Field_ftsf323ae_slot0_Slot_ae_slot0_get, + Field_ftsf324ae_slot0_Slot_ae_slot0_get, + Field_ftsf325ae_slot0_Slot_ae_slot0_get, + Field_ftsf326ae_slot0_Slot_ae_slot0_get, + Field_ftsf327ae_slot0_Slot_ae_slot0_get, + Field_ftsf328ae_slot0_Slot_ae_slot0_get, + Field_ftsf329ae_slot0_Slot_ae_slot0_get, + Field_ftsf360ae_slot0_Slot_ae_slot0_get, + Field_ftsf361ae_slot0_Slot_ae_slot0_get, + Field_ftsf362_Slot_ae_slot0_get, + Field_ftsf363ae_slot0_Slot_ae_slot0_get, + Field_ftsf364ae_slot0_Slot_ae_slot0_get, + Field_ftsf366ae_slot0_Slot_ae_slot0_get, + Field_ftsf368ae_slot0_Slot_ae_slot0_get, + Field_ftsf370ae_slot0_Slot_ae_slot0_get, + Field_ftsf373ae_slot0_Slot_ae_slot0_get, + Field_ftsf376ae_slot0_Slot_ae_slot0_get, + Field_ftsf378ae_slot0_Slot_ae_slot0_get, + Field_ftsf379ae_slot0_Slot_ae_slot0_get, + Field_ftsf382ae_slot0_Slot_ae_slot0_get, + Field_ftsf383ae_slot0_Slot_ae_slot0_get, + Field_ftsf384ae_slot0_Slot_ae_slot0_get, + Field_ftsf386ae_slot0_Slot_ae_slot0_get, + Field_ftsf387ae_slot0_Slot_ae_slot0_get, + Field_ftsf388ae_slot0_Slot_ae_slot0_get, + Field_ftsf389ae_slot0_Slot_ae_slot0_get, + 0, + Field_op0_s4_s4_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld28_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld37_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld39_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld40_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld46_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld47_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld49_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld50_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld52_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld121_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld123_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld127_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get, + Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get, + Field_op0_s4_s4_s4_Slot_ae_slot0_get, + Field_combined1e9fefee_fld96_Slot_ae_slot0_get, + Field_combined1e9fefee_fld98_Slot_ae_slot0_get, + Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get, + Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get, + Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get, + Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_ae_slot0_get, + Field_s3to1_Slot_ae_slot0_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + Field_bbi_Slot_ae_slot0_set, + Field_imm12_Slot_ae_slot0_set, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae_slot0_set, + 0, + 0, + Field_s8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot0_set, + Field_ae_samt_s_t_Slot_ae_slot0_set, + Field_ae_r20_Slot_ae_slot0_set, + Field_ae_r10_Slot_ae_slot0_set, + Field_ae_s20_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_ftsf11_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_ae_slot0_set, + Field_ftsf211ae_slot0_Slot_ae_slot0_set, + Field_ftsf212ae_slot0_Slot_ae_slot0_set, + Field_ftsf213ae_slot0_Slot_ae_slot0_set, + Field_ftsf214ae_slot0_Slot_ae_slot0_set, + Field_ftsf215ae_slot0_Slot_ae_slot0_set, + Field_ftsf217ae_slot0_Slot_ae_slot0_set, + Field_ftsf218ae_slot0_Slot_ae_slot0_set, + Field_ftsf219ae_slot0_Slot_ae_slot0_set, + Field_ftsf220ae_slot0_Slot_ae_slot0_set, + Field_ftsf221ae_slot0_Slot_ae_slot0_set, + Field_ftsf222ae_slot0_Slot_ae_slot0_set, + Field_ftsf223ae_slot0_Slot_ae_slot0_set, + Field_ftsf224ae_slot0_Slot_ae_slot0_set, + Field_ftsf225ae_slot0_Slot_ae_slot0_set, + Field_ftsf226ae_slot0_Slot_ae_slot0_set, + Field_ftsf227ae_slot0_Slot_ae_slot0_set, + Field_ftsf228ae_slot0_Slot_ae_slot0_set, + Field_ftsf229ae_slot0_Slot_ae_slot0_set, + Field_ftsf230ae_slot0_Slot_ae_slot0_set, + Field_ftsf231ae_slot0_Slot_ae_slot0_set, + Field_ftsf232ae_slot0_Slot_ae_slot0_set, + Field_ftsf233ae_slot0_Slot_ae_slot0_set, + Field_ftsf234ae_slot0_Slot_ae_slot0_set, + Field_ftsf235ae_slot0_Slot_ae_slot0_set, + Field_ftsf236ae_slot0_Slot_ae_slot0_set, + Field_ftsf237ae_slot0_Slot_ae_slot0_set, + Field_ftsf238ae_slot0_Slot_ae_slot0_set, + Field_ftsf239ae_slot0_Slot_ae_slot0_set, + Field_ftsf240ae_slot0_Slot_ae_slot0_set, + Field_ftsf241ae_slot0_Slot_ae_slot0_set, + Field_ftsf242ae_slot0_Slot_ae_slot0_set, + Field_ftsf243ae_slot0_Slot_ae_slot0_set, + Field_ftsf244ae_slot0_Slot_ae_slot0_set, + Field_ftsf245ae_slot0_Slot_ae_slot0_set, + Field_ftsf246ae_slot0_Slot_ae_slot0_set, + Field_ftsf247ae_slot0_Slot_ae_slot0_set, + Field_ftsf248ae_slot0_Slot_ae_slot0_set, + Field_ftsf249ae_slot0_Slot_ae_slot0_set, + Field_ftsf250ae_slot0_Slot_ae_slot0_set, + Field_ftsf251ae_slot0_Slot_ae_slot0_set, + Field_ftsf252ae_slot0_Slot_ae_slot0_set, + Field_ftsf253ae_slot0_Slot_ae_slot0_set, + Field_ftsf254ae_slot0_Slot_ae_slot0_set, + Field_ftsf255ae_slot0_Slot_ae_slot0_set, + Field_ftsf256ae_slot0_Slot_ae_slot0_set, + Field_ftsf257ae_slot0_Slot_ae_slot0_set, + Field_ftsf258ae_slot0_Slot_ae_slot0_set, + Field_ftsf259ae_slot0_Slot_ae_slot0_set, + Field_ftsf260ae_slot0_Slot_ae_slot0_set, + Field_ftsf261ae_slot0_Slot_ae_slot0_set, + Field_ftsf262ae_slot0_Slot_ae_slot0_set, + Field_ftsf263ae_slot0_Slot_ae_slot0_set, + Field_ftsf264ae_slot0_Slot_ae_slot0_set, + Field_ftsf265ae_slot0_Slot_ae_slot0_set, + Field_ftsf266ae_slot0_Slot_ae_slot0_set, + Field_ftsf267ae_slot0_Slot_ae_slot0_set, + Field_ftsf268ae_slot0_Slot_ae_slot0_set, + Field_ftsf269ae_slot0_Slot_ae_slot0_set, + Field_ftsf270ae_slot0_Slot_ae_slot0_set, + Field_ftsf271ae_slot0_Slot_ae_slot0_set, + Field_ftsf272ae_slot0_Slot_ae_slot0_set, + Field_ftsf273ae_slot0_Slot_ae_slot0_set, + Field_ftsf274ae_slot0_Slot_ae_slot0_set, + Field_ftsf275ae_slot0_Slot_ae_slot0_set, + Field_ftsf276ae_slot0_Slot_ae_slot0_set, + Field_ftsf277ae_slot0_Slot_ae_slot0_set, + Field_ftsf278ae_slot0_Slot_ae_slot0_set, + Field_ftsf279ae_slot0_Slot_ae_slot0_set, + Field_ftsf280_Slot_ae_slot0_set, + Field_ftsf281ae_slot0_Slot_ae_slot0_set, + Field_ftsf282ae_slot0_Slot_ae_slot0_set, + Field_ftsf284ae_slot0_Slot_ae_slot0_set, + Field_ftsf285ae_slot0_Slot_ae_slot0_set, + Field_ftsf287ae_slot0_Slot_ae_slot0_set, + Field_ftsf288_Slot_ae_slot0_set, + Field_ftsf289ae_slot0_Slot_ae_slot0_set, + Field_ftsf290ae_slot0_Slot_ae_slot0_set, + Field_ftsf291ae_slot0_Slot_ae_slot0_set, + Field_ftsf292ae_slot0_Slot_ae_slot0_set, + Field_ftsf293ae_slot0_Slot_ae_slot0_set, + Field_ftsf294ae_slot0_Slot_ae_slot0_set, + Field_ftsf295ae_slot0_Slot_ae_slot0_set, + Field_ftsf296ae_slot0_Slot_ae_slot0_set, + Field_ftsf297ae_slot0_Slot_ae_slot0_set, + Field_ftsf298ae_slot0_Slot_ae_slot0_set, + Field_ftsf300ae_slot0_Slot_ae_slot0_set, + Field_ftsf302ae_slot0_Slot_ae_slot0_set, + Field_ftsf304ae_slot0_Slot_ae_slot0_set, + Field_ftsf305ae_slot0_Slot_ae_slot0_set, + Field_ftsf306ae_slot0_Slot_ae_slot0_set, + Field_ftsf307ae_slot0_Slot_ae_slot0_set, + Field_ftsf308ae_slot0_Slot_ae_slot0_set, + Field_ftsf309_Slot_ae_slot0_set, + Field_ftsf310ae_slot0_Slot_ae_slot0_set, + Field_ftsf311ae_slot0_Slot_ae_slot0_set, + Field_ftsf312ae_slot0_Slot_ae_slot0_set, + Field_ftsf313ae_slot0_Slot_ae_slot0_set, + Field_ftsf314ae_slot0_Slot_ae_slot0_set, + Field_ftsf315_Slot_ae_slot0_set, + Field_ftsf316ae_slot0_Slot_ae_slot0_set, + Field_ftsf317ae_slot0_Slot_ae_slot0_set, + Field_ftsf319ae_slot0_Slot_ae_slot0_set, + Field_ftsf320ae_slot0_Slot_ae_slot0_set, + Field_ftsf322ae_slot0_Slot_ae_slot0_set, + Field_ftsf323ae_slot0_Slot_ae_slot0_set, + Field_ftsf324ae_slot0_Slot_ae_slot0_set, + Field_ftsf325ae_slot0_Slot_ae_slot0_set, + Field_ftsf326ae_slot0_Slot_ae_slot0_set, + Field_ftsf327ae_slot0_Slot_ae_slot0_set, + Field_ftsf328ae_slot0_Slot_ae_slot0_set, + Field_ftsf329ae_slot0_Slot_ae_slot0_set, + Field_ftsf360ae_slot0_Slot_ae_slot0_set, + Field_ftsf361ae_slot0_Slot_ae_slot0_set, + Field_ftsf362_Slot_ae_slot0_set, + Field_ftsf363ae_slot0_Slot_ae_slot0_set, + Field_ftsf364ae_slot0_Slot_ae_slot0_set, + Field_ftsf366ae_slot0_Slot_ae_slot0_set, + Field_ftsf368ae_slot0_Slot_ae_slot0_set, + Field_ftsf370ae_slot0_Slot_ae_slot0_set, + Field_ftsf373ae_slot0_Slot_ae_slot0_set, + Field_ftsf376ae_slot0_Slot_ae_slot0_set, + Field_ftsf378ae_slot0_Slot_ae_slot0_set, + Field_ftsf379ae_slot0_Slot_ae_slot0_set, + Field_ftsf382ae_slot0_Slot_ae_slot0_set, + Field_ftsf383ae_slot0_Slot_ae_slot0_set, + Field_ftsf384ae_slot0_Slot_ae_slot0_set, + Field_ftsf386ae_slot0_Slot_ae_slot0_set, + Field_ftsf387ae_slot0_Slot_ae_slot0_set, + Field_ftsf388ae_slot0_Slot_ae_slot0_set, + Field_ftsf389ae_slot0_Slot_ae_slot0_set, + 0, + Field_op0_s4_s4_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld28_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld37_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld39_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld40_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld46_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld47_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld49_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld50_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld52_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld121_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld123_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld127_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set, + Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set, + Field_op0_s4_s4_s4_Slot_ae_slot0_set, + Field_combined1e9fefee_fld96_Slot_ae_slot0_set, + Field_combined1e9fefee_fld98_Slot_ae_slot0_set, + Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set, + Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set, + Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set, + Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_bitindex_Slot_ae_slot0_set, + Field_s3to1_Slot_ae_slot0_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_10_get, Slot_ae_format_Format_ae_slot1_10_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_33_get, Slot_ae_format_Format_ae_slot0_33_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0x80000000; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0xc0000000; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0xf0000000; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 3, 4 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0) == 0 && (insn[1] & 0x80000000) == 0) + return 0; /* x24 */ + if ((insn[0] & 0) == 0 && (insn[1] & 0xc0000000) == 0x80000000) + return 1; /* x16a */ + if ((insn[0] & 0) == 0 && (insn[1] & 0xe0000000) == 0xc0000000) + return 2; /* x16b */ + if ((insn[0] & 0x3ff) == 0 && (insn[1] & 0xf0000000) == 0xf0000000) + return 3; /* ae_format */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8, + 8 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 1 /* big-endian */, + 8 /* insn_size */, 0, + 4, formats, format_decoder, length_decoder, + 5, slots, + 468 /* num_fields */, + 536, operands, + 746, iclasses, + 881, opcodes, 0, + 9, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 4, funcUnits, 0 +}; diff --git a/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c b/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c deleted file mode 100644 index bc7cf44828..0000000000 --- a/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c +++ /dev/null @@ -1,45117 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "ACCLO", 16, 0 }, - { "ACCHI", 17, 0 }, - { "M0", 32, 0 }, - { "M1", 33, 0 }, - { "M2", 34, 0 }, - { "M3", 35, 0 }, - { "PTEVADDR", 83, 0 }, - { "MMID", 89, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "CCOMPARE2", 242, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EPC3", 179, 0 }, - { "EPC4", 180, 0 }, - { "EPC5", 181, 0 }, - { "EPC6", 182, 0 }, - { "EPC7", 183, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EXCSAVE3", 211, 0 }, - { "EXCSAVE4", 212, 0 }, - { "EXCSAVE5", 213, 0 }, - { "EXCSAVE6", 214, 0 }, - { "EXCSAVE7", 215, 0 }, - { "EPS2", 194, 0 }, - { "EPS3", 195, 0 }, - { "EPS4", 196, 0 }, - { "EPS5", 197, 0 }, - { "EPS6", 198, 0 }, - { "EPS7", 199, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "DBREAKA0", 144, 0 }, - { "DBREAKC0", 160, 0 }, - { "DBREAKA1", 145, 0 }, - { "DBREAKC1", 161, 0 }, - { "IBREAKA0", 128, 0 }, - { "IBREAKA1", 129, 0 }, - { "IBREAKENABLE", 96, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "PREFCTL", 40, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "THREADPTR", 231, 1 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 }, - { "AE_CBEGIN0", 246, 1 }, - { "AE_CEND0", 247, 1 }, - { "EXPSTATE", 230, 1 } -}; - -#define NUM_SYSREGS 78 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 247 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 22, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EPC3", 32, 0 }, - { "EPC4", 32, 0 }, - { "EPC5", 32, 0 }, - { "EPC6", 32, 0 }, - { "EPC7", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EXCSAVE3", 32, 0 }, - { "EXCSAVE4", 32, 0 }, - { "EXCSAVE5", 32, 0 }, - { "EXCSAVE6", 32, 0 }, - { "EXCSAVE7", 32, 0 }, - { "EPS2", 15, 0 }, - { "EPS3", 15, 0 }, - { "EPS4", 15, 0 }, - { "EPS5", 15, 0 }, - { "EPS6", 15, 0 }, - { "EPS7", 15, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "ACC", 40, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 22, 0 }, - { "DBREAKA0", 32, 0 }, - { "DBREAKC0", 8, 0 }, - { "DBREAKA1", 32, 0 }, - { "DBREAKC1", 8, 0 }, - { "IBREAKA0", 32, 0 }, - { "IBREAKA1", 32, 0 }, - { "IBREAKENABLE", 2, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 }, - { "PREFCTL", 9, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID6", 1, 0 }, - { "INSTPGSZID5", 1, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID6", 1, 0 }, - { "DATAPGSZID5", 1, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 }, - { "CPENABLE", 8, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "ERI_RAW_INTERLOCK", 1, 0 }, - { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 }, - { "AE_CBEGIN0", 32, 0 }, - { "AE_CEND0", 32, 0 }, - { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } -}; - -#define NUM_STATES 89 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EPC3, - STATE_EPC4, - STATE_EPC5, - STATE_EPC6, - STATE_EPC7, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EXCSAVE3, - STATE_EXCSAVE4, - STATE_EXCSAVE5, - STATE_EXCSAVE6, - STATE_EXCSAVE7, - STATE_EPS2, - STATE_EPS3, - STATE_EPS4, - STATE_EPS5, - STATE_EPS6, - STATE_EPS7, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSRING, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_THREADPTR, - STATE_MISC0, - STATE_MISC1, - STATE_ACC, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_DBREAKA0, - STATE_DBREAKC0, - STATE_DBREAKA1, - STATE_DBREAKC1, - STATE_IBREAKA0, - STATE_IBREAKA1, - STATE_IBREAKENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_CCOMPARE2, - STATE_PREFCTL, - STATE_ASID3, - STATE_ASID2, - STATE_ASID1, - STATE_INSTPGSZID6, - STATE_INSTPGSZID5, - STATE_INSTPGSZID4, - STATE_DATAPGSZID6, - STATE_DATAPGSZID5, - STATE_DATAPGSZID4, - STATE_PTBASE, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_ERI_RAW_INTERLOCK, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE, - STATE_AE_CBEGIN0, - STATE_AE_CEND0, - STATE_EXPSTATE -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_t3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_w_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); -} - -static unsigned -Field_ftsf333ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf333ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf359ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_ftsf355ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); - return tie_t; -} - -static void -Field_ftsf355ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf354ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); -} - -static unsigned -Field_ftsf357ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); - return tie_t; -} - -static void -Field_ftsf357ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf347ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf347ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); -} - -static unsigned -Field_ftsf345ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_ftsf345ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); - tie_t = (val << 22) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf358ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); - return tie_t; -} - -static void -Field_ftsf358ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 20) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf93ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf93ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); - tie_t = (val << 22) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf55_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf55_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf121ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf121ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf91_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_ftsf91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf351_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_ftsf351_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 21) >> 26; - insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 20) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf20ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf20ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf356ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_ftsf356ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ftsf62ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf62ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf352ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf352ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 20) >> 23; - insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 20) >> 23; - insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf123ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf123ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf117ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf117ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf68ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf68ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf61_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - return tie_t; -} - -static void -Field_ftsf61_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf83ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf83ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf70ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf70ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf74ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf74ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf85ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf85ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf102ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_ftsf102ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 23) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_ftsf335_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - return tie_t; -} - -static void -Field_ftsf335_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf208ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf208ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf340ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf340ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld69_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld68_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld19_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); -} - -static unsigned -Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld74_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); -} - -static unsigned -Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld66_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld90_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld88_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld65_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld79_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf280_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - return tie_t; -} - -static void -Field_ftsf280_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); -} - -static unsigned -Field_ftsf288_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} - -static void -Field_ftsf288_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x380) | (tie_t << 7); -} - -static unsigned -Field_ftsf211ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf211ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); - tie_t = (val << 17) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); - tie_t = (val << 18) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); - tie_t = (val << 26) >> 31; - insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); - tie_t = (val << 17) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf287ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf287ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); - tie_t = (val << 22) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21); -} - -static unsigned -Field_ftsf285ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf285ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); - tie_t = (val << 21) >> 30; - insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 14) | ((insn[0] << 11) >> 18); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 18) >> 18; - insn[0] = (insn[0] & ~0x1fff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf309_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); - return tie_t; -} - -static void -Field_ftsf309_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); -} - -static unsigned -Field_ftsf327ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf327ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); - tie_t = (val << 21) >> 30; - insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); -} - -static unsigned -Field_ftsf363ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); - return tie_t; -} - -static void -Field_ftsf363ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf373ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf373ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf376ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); - return tie_t; -} - -static void -Field_ftsf376ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf370ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); - return tie_t; -} - -static void -Field_ftsf370ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf378ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); - return tie_t; -} - -static void -Field_ftsf378ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf217ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf217ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf305ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf305ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf307ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf307ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ftsf379ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf379ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf315_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - return tie_t; -} - -static void -Field_ftsf315_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld52_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); -} - -static unsigned -Field_combined1e9fefee_fld96_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined1e9fefee_fld96_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_combined1e9fefee_fld98_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_combined1e9fefee_fld98_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld49_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld50_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x200) | (tie_t << 9); -} - -static unsigned -Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld40_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf362_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf362_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_op0_s4_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); -} - -static unsigned -Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); - return tie_t; -} - -static void -Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); -} - -static unsigned -Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); -} - -static unsigned -Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld47_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); - return tie_t; -} - -static void -Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); -} - -static unsigned -Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); - return tie_t; -} - -static void -Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 19) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf289ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf289ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 19) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); - tie_t = (val << 19) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); -} - -static unsigned -Field_ftsf386ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf386ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); - tie_t = (val << 18) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf382ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf382ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf291ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf291ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -} - -static unsigned -Field_ftsf383ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf383ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf293ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); - return tie_t; -} - -static void -Field_ftsf293ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); -} - -static unsigned -Field_ftsf384ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf384ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_ftsf387ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf387ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); - tie_t = (val << 25) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf319ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); - return tie_t; -} - -static void -Field_ftsf319ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); - tie_t = (val << 21) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf388ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); - return tie_t; -} - -static void -Field_ftsf388ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); - tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); - tie_t = (val << 21) >> 31; - insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); - tie_t = (val << 20) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf389ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); - return tie_t; -} - -static void -Field_ftsf389ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); - tie_t = (val << 19) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 23) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); - tie_t = (val << 21) >> 30; - insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); - tie_t = (val << 22) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); - tie_t = (val << 18) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld123_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); -} - -static unsigned -Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld121_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); -} - -static unsigned -Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld28_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld127_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); -} - -static unsigned -Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); -} - -static unsigned -Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld46_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 5) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0x7f80000) | (tie_t << 19); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 9) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0x7ff800) | (tie_t << 11); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); - return tie_t; -} - -static void -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); -} - -static unsigned -Field_y_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); - return tie_t; -} - -static void -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); -} - -static unsigned -Field_x_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); - return tie_t; -} - -static void -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x400) | (tie_t << 10); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); - tie_t = (val << 26) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf11_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf11_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf11_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_ftsf11_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf11_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); -} - -static unsigned -Field_combined2c0b5f72_fld37_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld37_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 14) >> 21); - return tie_t; -} - -static void -Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0x3ff80) | (tie_t << 7); -} - -static unsigned -Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); - return tie_t; -} - -static void -Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); - return tie_t; -} - -static void -Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 3; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_r3, - FIELD_rbit2, - FIELD_rhi, - FIELD_t3, - FIELD_tbit2, - FIELD_tlo, - FIELD_w, - FIELD_y, - FIELD_x, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf11, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf20ae_slot1, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61, - FIELD_ftsf62ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf68ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf70ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf74ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf83ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf85ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91, - FIELD_ftsf92ae_slot1, - FIELD_ftsf93ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf102ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf117ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf121ae_slot1, - FIELD_ftsf123ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf333ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf335, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340ae_slot1, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf345ae_slot1, - FIELD_ftsf347ae_slot1, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_ftsf351, - FIELD_ftsf352ae_slot1, - FIELD_ftsf354ae_slot1, - FIELD_ftsf355ae_slot1, - FIELD_ftsf356ae_slot1, - FIELD_ftsf357ae_slot1, - FIELD_ftsf358ae_slot1, - FIELD_ftsf359ae_slot1, - FIELD_op0_s4, - FIELD_ftsf211ae_slot0, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf217ae_slot0, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf280, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf285ae_slot0, - FIELD_ftsf287ae_slot0, - FIELD_ftsf288, - FIELD_ftsf289ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf291ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293ae_slot0, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf305ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf307ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf319ae_slot0, - FIELD_ftsf320ae_slot0, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf327ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362, - FIELD_ftsf363ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf370ae_slot0, - FIELD_ftsf373ae_slot0, - FIELD_ftsf376ae_slot0, - FIELD_ftsf378ae_slot0, - FIELD_ftsf379ae_slot0, - FIELD_ftsf382ae_slot0, - FIELD_ftsf383ae_slot0, - FIELD_ftsf384ae_slot0, - FIELD_ftsf386ae_slot0, - FIELD_ftsf387ae_slot0, - FIELD_ftsf388ae_slot0, - FIELD_ftsf389ae_slot0, - FIELD_ae_mul32x24fld, - FIELD_op0_s4_s4, - FIELD_combined2c0b5f72_fld28, - FIELD_combined2c0b5f72_fld37, - FIELD_combined2c0b5f72_fld39, - FIELD_combined2c0b5f72_fld40, - FIELD_combined2c0b5f72_fld46, - FIELD_combined2c0b5f72_fld47, - FIELD_combined2c0b5f72_fld49, - FIELD_combined2c0b5f72_fld50, - FIELD_combined2c0b5f72_fld52, - FIELD_combined2c0b5f72_fld121, - FIELD_combined2c0b5f72_fld123, - FIELD_combined2c0b5f72_fld127, - FIELD_combined2c0b5f72_fld133ae_slot0, - FIELD_combined2c0b5f72_fld134ae_slot0, - FIELD_combined2c0b5f72_fld135ae_slot0, - FIELD_combined2c0b5f72_fld136ae_slot0, - FIELD_combined2c0b5f72_fld137ae_slot0, - FIELD_combined2c0b5f72_fld138ae_slot0, - FIELD_combined2c0b5f72_fld139ae_slot0, - FIELD_combined2c0b5f72_fld140ae_slot0, - FIELD_combined2c0b5f72_fld141ae_slot0, - FIELD_combined2c0b5f72_fld142ae_slot0, - FIELD_combined2c0b5f72_fld143ae_slot0, - FIELD_combined2c0b5f72_fld144ae_slot0, - FIELD_combined2c0b5f72_fld145ae_slot0, - FIELD_combined2c0b5f72_fld146ae_slot0, - FIELD_combined2c0b5f72_fld148ae_slot0, - FIELD_combined2c0b5f72_fld149ae_slot0, - FIELD_op0_s4_s4_s4, - FIELD_combined1e9fefee_fld96, - FIELD_combined1e9fefee_fld98, - FIELD_combined1e9fefee_fld106ae_slot0, - FIELD_combined1e9fefee_fld107ae_slot0, - FIELD_combined1e9fefee_fld108ae_slot0, - FIELD_combined1e9fefee_fld109ae_slot0, - FIELD_op0_s3_s3, - FIELD_combined2c0b5f72_fld19, - FIELD_combined2c0b5f72_fld22, - FIELD_combined2c0b5f72_fld24, - FIELD_combined2c0b5f72_fld65, - FIELD_combined2c0b5f72_fld66, - FIELD_combined2c0b5f72_fld68, - FIELD_combined2c0b5f72_fld69, - FIELD_combined2c0b5f72_fld74, - FIELD_combined2c0b5f72_fld79, - FIELD_combined2c0b5f72_fld88, - FIELD_combined2c0b5f72_fld90, - FIELD_combined2c0b5f72_fld91, - FIELD_combined2c0b5f72_fld131ae_slot1, - FIELD_combined2c0b5f72_fld132ae_slot1, - FIELD_combined2c0b5f72_fld147ae_slot1, - FIELD_bitindex, - FIELD_s3to1, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__mr0, - FIELD__mr1, - FIELD__mr2, - FIELD__mr3, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_MR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "MR", "m", REGFILE_MR, 32, 4 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "ERI_RD_Out", 14, 0, 0, 'o' }, - { "ERI_RD_In", 32, 0, 1, 'i' }, - { "ERI_RD_Rdy", 1, 0, 0, 'i' }, - { "ERI_WR_Out", 46, 0, 2, 'o' }, - { "ERI_WR_In", 1, 0, 3, 'i' }, - { "IMPWIRE", 32, 0, 4, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_ERI_RD_Out, - INTERFACE_ERI_RD_In, - INTERFACE_ERI_RD_Rdy, - INTERFACE_ERI_WR_Out, - INTERFACE_ERI_WR_In, - INTERFACE_IMPWIRE -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_MR_0_decode (uint32 *valp) -{ - *valp += 2; - return 0; -} - -static int -OperandSem_opnd_sem_MR_0_encode (uint32 *valp) -{ - int error; - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); - *valp = *valp & 1; - return error; -} - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_out_0; - unsigned ulabel8_in_0; - ulabel8_in_0 = *valp & 0xff; - ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); - *valp = ulabel8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) -{ - unsigned ulabel8_in_0; - unsigned ulabel8_out_0; - ulabel8_out_0 = *valp; - ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; - *valp = ulabel8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_1_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_3_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_MR_5_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_BR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16); - return error; -} - -static int -OperandSem_opnd_sem_BR2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -OperandSem_opnd_sem_BR2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 1) != 0); - *valp = *valp >> 1; - return error; -} - -static int -OperandSem_opnd_sem_BR4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -OperandSem_opnd_sem_BR4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 3) != 0); - *valp = *valp >> 2; - return error; -} - -static int -OperandSem_opnd_sem_BR8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -OperandSem_opnd_sem_BR8_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 7) != 0); - *valp = *valp >> 3; - return error; -} - -static int -OperandSem_opnd_sem_BR16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -OperandSem_opnd_sem_BR16_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 15) != 0); - *valp = *valp >> 4; - return error; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_out_0; - unsigned ae_samt32_in_0; - ae_samt32_in_0 = *valp & 0x1f; - ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; - *valp = ae_samt32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) -{ - unsigned ae_samt32_in_0; - unsigned ae_samt32_out_0; - ae_samt32_out_0 = *valp; - ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); - *valp = ae_samt32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 8); - return error; -} - -static int -OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_out_0; - unsigned ae_lsimm16_in_0; - ae_lsimm16_in_0 = *valp & 0xf; - ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) -{ - unsigned ae_lsimm16_in_0; - unsigned ae_lsimm16_out_0; - ae_lsimm16_out_0 = *valp; - ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); - *valp = ae_lsimm16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_out_0; - unsigned ae_lsimm32_in_0; - ae_lsimm32_in_0 = *valp & 0xf; - ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) -{ - unsigned ae_lsimm32_in_0; - unsigned ae_lsimm32_out_0; - ae_lsimm32_out_0 = *valp; - ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); - *valp = ae_lsimm32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_out_0; - unsigned ae_lsimm64_in_0; - ae_lsimm64_in_0 = *valp & 0xf; - ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) -{ - unsigned ae_lsimm64_in_0; - unsigned ae_lsimm64_out_0; - ae_lsimm64_out_0 = *valp; - ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); - *valp = ae_lsimm64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_out_0; - unsigned ae_samt64_in_0; - ae_samt64_in_0 = *valp & 0x3f; - ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; - *valp = ae_samt64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt64_in_0; - unsigned ae_samt64_out_0; - ae_samt64_out_0 = *valp; - ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); - *valp = ae_samt64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_out_0; - unsigned ae_ohba_in_0; - ae_ohba_in_0 = *valp & 0xf; - ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); - *valp = ae_ohba_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_ohba_in_0; - unsigned ae_ohba_out_0; - ae_ohba_out_0 = *valp; - ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); - *valp = ae_ohba_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "mx", FIELD_x, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, - 0, 0 }, - { "my", FIELD_y, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, - OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, - 0, 0 }, - { "mw", FIELD_w, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, - 0, 0 }, - { "mr0", FIELD__mr0, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, - 0, 0 }, - { "mr1", FIELD__mr1, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, - 0, 0 }, - { "mr2", FIELD__mr2, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, - 0, 0 }, - { "mr3", FIELD__mr3, REGFILE_MR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf13, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf11, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "bitindex", FIELD_bitindex, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, - { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, - { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, - { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, - { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, - { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, - { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf11", FIELD_ftsf11, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf20ae_slot1", FIELD_ftsf20ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55", FIELD_ftsf55, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61", FIELD_ftsf61, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf62ae_slot1", FIELD_ftsf62ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf68ae_slot1", FIELD_ftsf68ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf70ae_slot1", FIELD_ftsf70ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf74ae_slot1", FIELD_ftsf74ae_slot1, -1, 0, 0, 0, 0, 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FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf217ae_slot0", FIELD_ftsf217ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf280", FIELD_ftsf280, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf285ae_slot0", FIELD_ftsf285ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf287ae_slot0", FIELD_ftsf287ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf288", FIELD_ftsf288, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf289ae_slot0", FIELD_ftsf289ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf291ae_slot0", FIELD_ftsf291ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf293ae_slot0", FIELD_ftsf293ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf305ae_slot0", FIELD_ftsf305ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf307ae_slot0", FIELD_ftsf307ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf309", FIELD_ftsf309, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf315", FIELD_ftsf315, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf319ae_slot0", FIELD_ftsf319ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf327ae_slot0", FIELD_ftsf327ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362", FIELD_ftsf362, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf363ae_slot0", FIELD_ftsf363ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf370ae_slot0", FIELD_ftsf370ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf373ae_slot0", FIELD_ftsf373ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf376ae_slot0", FIELD_ftsf376ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf378ae_slot0", FIELD_ftsf378ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf379ae_slot0", FIELD_ftsf379ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf382ae_slot0", FIELD_ftsf382ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf383ae_slot0", FIELD_ftsf383ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf384ae_slot0", FIELD_ftsf384ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf386ae_slot0", FIELD_ftsf386ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf387ae_slot0", FIELD_ftsf387ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf388ae_slot0", FIELD_ftsf388ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf389ae_slot0", FIELD_ftsf389ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld28", FIELD_combined2c0b5f72_fld28, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld37", FIELD_combined2c0b5f72_fld37, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld39", FIELD_combined2c0b5f72_fld39, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld40", FIELD_combined2c0b5f72_fld40, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld46", FIELD_combined2c0b5f72_fld46, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld47", FIELD_combined2c0b5f72_fld47, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld49", FIELD_combined2c0b5f72_fld49, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld50", FIELD_combined2c0b5f72_fld50, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld52", FIELD_combined2c0b5f72_fld52, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld121", FIELD_combined2c0b5f72_fld121, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld123", FIELD_combined2c0b5f72_fld123, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld127", FIELD_combined2c0b5f72_fld127, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld133ae_slot0", FIELD_combined2c0b5f72_fld133ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld134ae_slot0", FIELD_combined2c0b5f72_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld135ae_slot0", FIELD_combined2c0b5f72_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld136ae_slot0", FIELD_combined2c0b5f72_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld137ae_slot0", FIELD_combined2c0b5f72_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld138ae_slot0", FIELD_combined2c0b5f72_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld139ae_slot0", FIELD_combined2c0b5f72_fld139ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld140ae_slot0", FIELD_combined2c0b5f72_fld140ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld141ae_slot0", FIELD_combined2c0b5f72_fld141ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld142ae_slot0", FIELD_combined2c0b5f72_fld142ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld143ae_slot0", FIELD_combined2c0b5f72_fld143ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld144ae_slot0", FIELD_combined2c0b5f72_fld144ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld145ae_slot0", FIELD_combined2c0b5f72_fld145ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld146ae_slot0", FIELD_combined2c0b5f72_fld146ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld148ae_slot0", FIELD_combined2c0b5f72_fld148ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld149ae_slot0", FIELD_combined2c0b5f72_fld149ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s4_s4_s4", FIELD_op0_s4_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld96", FIELD_combined1e9fefee_fld96, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld98", FIELD_combined1e9fefee_fld98, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld106ae_slot0", FIELD_combined1e9fefee_fld106ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld107ae_slot0", FIELD_combined1e9fefee_fld107ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld108ae_slot0", FIELD_combined1e9fefee_fld108ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "combined1e9fefee_fld109ae_slot0", FIELD_combined1e9fefee_fld109ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld19", FIELD_combined2c0b5f72_fld19, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld22", FIELD_combined2c0b5f72_fld22, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld24", FIELD_combined2c0b5f72_fld24, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld65", FIELD_combined2c0b5f72_fld65, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld66", FIELD_combined2c0b5f72_fld66, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld68", FIELD_combined2c0b5f72_fld68, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld69", FIELD_combined2c0b5f72_fld69, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld74", FIELD_combined2c0b5f72_fld74, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld79", FIELD_combined2c0b5f72_fld79, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld88", FIELD_combined2c0b5f72_fld88, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld90", FIELD_combined2c0b5f72_fld90, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld91", FIELD_combined2c0b5f72_fld91, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld131ae_slot1", FIELD_combined2c0b5f72_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld132ae_slot1", FIELD_combined2c0b5f72_fld132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "combined2c0b5f72_fld147ae_slot1", FIELD_combined2c0b5f72_fld147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_mx, - OPERAND_my, - OPERAND_mw, - OPERAND_mr0, - OPERAND_mr1, - OPERAND_mr2, - OPERAND_mr3, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_bitindex, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_r3, - OPERAND_rbit2, - OPERAND_rhi, - OPERAND_t3, - OPERAND_tbit2, - OPERAND_tlo, - OPERAND_w, - OPERAND_y, - OPERAND_x, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf11, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf20ae_slot1, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61, - OPERAND_ftsf62ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf68ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf70ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf74ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf83ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf85ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf93ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf102ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf117ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf121ae_slot1, - OPERAND_ftsf123ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf333ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf335, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340ae_slot1, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf345ae_slot1, - OPERAND_ftsf347ae_slot1, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_ftsf351, - OPERAND_ftsf352ae_slot1, - OPERAND_ftsf354ae_slot1, - OPERAND_ftsf355ae_slot1, - OPERAND_ftsf356ae_slot1, - OPERAND_ftsf357ae_slot1, - OPERAND_ftsf358ae_slot1, - OPERAND_ftsf359ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf211ae_slot0, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf217ae_slot0, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf280, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf285ae_slot0, - OPERAND_ftsf287ae_slot0, - OPERAND_ftsf288, - OPERAND_ftsf289ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf291ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293ae_slot0, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf305ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf307ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf319ae_slot0, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf327ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362, - OPERAND_ftsf363ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf370ae_slot0, - OPERAND_ftsf373ae_slot0, - OPERAND_ftsf376ae_slot0, - OPERAND_ftsf378ae_slot0, - OPERAND_ftsf379ae_slot0, - OPERAND_ftsf382ae_slot0, - OPERAND_ftsf383ae_slot0, - OPERAND_ftsf384ae_slot0, - OPERAND_ftsf386ae_slot0, - OPERAND_ftsf387ae_slot0, - OPERAND_ftsf388ae_slot0, - OPERAND_ftsf389ae_slot0, - OPERAND_ae_mul32x24fld, - OPERAND_op0_s4_s4, - OPERAND_combined2c0b5f72_fld28, - OPERAND_combined2c0b5f72_fld37, - OPERAND_combined2c0b5f72_fld39, - OPERAND_combined2c0b5f72_fld40, - OPERAND_combined2c0b5f72_fld46, - OPERAND_combined2c0b5f72_fld47, - OPERAND_combined2c0b5f72_fld49, - OPERAND_combined2c0b5f72_fld50, - OPERAND_combined2c0b5f72_fld52, - OPERAND_combined2c0b5f72_fld121, - OPERAND_combined2c0b5f72_fld123, - OPERAND_combined2c0b5f72_fld127, - OPERAND_combined2c0b5f72_fld133ae_slot0, - OPERAND_combined2c0b5f72_fld134ae_slot0, - OPERAND_combined2c0b5f72_fld135ae_slot0, - OPERAND_combined2c0b5f72_fld136ae_slot0, - OPERAND_combined2c0b5f72_fld137ae_slot0, - OPERAND_combined2c0b5f72_fld138ae_slot0, - OPERAND_combined2c0b5f72_fld139ae_slot0, - OPERAND_combined2c0b5f72_fld140ae_slot0, - OPERAND_combined2c0b5f72_fld141ae_slot0, - OPERAND_combined2c0b5f72_fld142ae_slot0, - OPERAND_combined2c0b5f72_fld143ae_slot0, - OPERAND_combined2c0b5f72_fld144ae_slot0, - OPERAND_combined2c0b5f72_fld145ae_slot0, - OPERAND_combined2c0b5f72_fld146ae_slot0, - OPERAND_combined2c0b5f72_fld148ae_slot0, - OPERAND_combined2c0b5f72_fld149ae_slot0, - OPERAND_op0_s4_s4_s4, - OPERAND_combined1e9fefee_fld96, - OPERAND_combined1e9fefee_fld98, - OPERAND_combined1e9fefee_fld106ae_slot0, - OPERAND_combined1e9fefee_fld107ae_slot0, - OPERAND_combined1e9fefee_fld108ae_slot0, - OPERAND_combined1e9fefee_fld109ae_slot0, - OPERAND_op0_s3_s3, - OPERAND_combined2c0b5f72_fld19, - OPERAND_combined2c0b5f72_fld22, - OPERAND_combined2c0b5f72_fld24, - OPERAND_combined2c0b5f72_fld65, - OPERAND_combined2c0b5f72_fld66, - OPERAND_combined2c0b5f72_fld68, - OPERAND_combined2c0b5f72_fld69, - OPERAND_combined2c0b5f72_fld74, - OPERAND_combined2c0b5f72_fld79, - OPERAND_combined2c0b5f72_fld88, - OPERAND_combined2c0b5f72_fld90, - OPERAND_combined2c0b5f72_fld91, - OPERAND_combined2c0b5f72_fld131ae_slot1, - OPERAND_combined2c0b5f72_fld132ae_slot1, - OPERAND_combined2c0b5f72_fld147ae_slot1, - OPERAND_s3to1 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimmrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_243_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS5 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS6 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS7 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32h_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { - { { STATE_ACC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_mx }, 'i' }, - { { OPERAND_my }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { - { { OPERAND_mw }, 'o' }, - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_mr3 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_mr3 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_mr3 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { - { { STATE_ACC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPC3 }, 'i' }, - { { STATE_EPC4 }, 'i' }, - { { STATE_EPC5 }, 'i' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_EPC7 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_EPS3 }, 'i' }, - { { STATE_EPS4 }, 'i' }, - { { STATE_EPS5 }, 'i' }, - { { STATE_EPS6 }, 'i' }, - { { STATE_EPS7 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC0 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKA1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DBREAKC1 }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKA1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_IBREAKENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_InOCDMode }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC6 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE2 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { - { { STATE_PREFCTL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'i' }, - { { STATE_INSTPGSZID5 }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'o' }, - { { STATE_INSTPGSZID5 }, 'o' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID6 }, 'm' }, - { { STATE_INSTPGSZID5 }, 'm' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'i' }, - { { STATE_DATAPGSZID5 }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'o' }, - { { STATE_DATAPGSZID5 }, 'o' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID6 }, 'm' }, - { { STATE_DATAPGSZID5 }, 'm' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_ERI_RAW_INTERLOCK }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { - INTERFACE_ERI_RD_In, - INTERFACE_ERI_RD_Out -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_ERI_RAW_INTERLOCK }, 'o' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { - INTERFACE_ERI_WR_In, - INTERFACE_ERI_WR_Out -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { - { { STATE_AE_CEND0 }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { - { { STATE_AE_CBEGIN0 }, 'i' }, - { { STATE_AE_CEND0 }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { - { { STATE_EXPSTATE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { - INTERFACE_IMPWIRE -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { - { { OPERAND_bitindex }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { - { { STATE_EXPSTATE }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32nb_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_memctl_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_243_args, - 2, Iclass_xt_iclass_rsr_243_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc3_args, - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc3_args, - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc3_args, - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave3_args, - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave3_args, - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave3_args, - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc4_args, - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc4_args, - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc4_args, - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave4_args, - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave4_args, - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave4_args, - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc5_args, - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc5_args, - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc5_args, - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave5_args, - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave5_args, - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave5_args, - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc6_args, - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc6_args, - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc6_args, - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave6_args, - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave6_args, - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave6_args, - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc7_args, - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc7_args, - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc7_args, - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave7_args, - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave7_args, - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave7_args, - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps3_args, - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps3_args, - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps3_args, - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps4_args, - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps4_args, - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps4_args, - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps5_args, - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps5_args, - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps5_args, - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps6_args, - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps6_args, - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps6_args, - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps7_args, - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps7_args, - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps7_args, - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32h_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_aa_args, - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_ad_args, - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_da_args, - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_dd_args, - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_aa_args, - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_ad_args, - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_da_args, - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16a_dd_args, - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_da_args, - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, - { 4, Iclass_xt_iclass_mac16al_dd_args, - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_mac16_l_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m2_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_wsr_m3_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_xsr_m3_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acclo_args, - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acclo_args, - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acclo_args, - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_acchi_args, - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_acchi_args, - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_acchi_args, - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_lddr32_p_args, - 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sddr32_p_args, - 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_mmid_args, - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_lock_args, - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_dcache_dyn_args, - 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_lock_args, - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prefctl_args, - 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_prefctl_args, - 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_prefctl_args, - 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_div_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 3, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, - { 2, Iclass_xt_iclass_wer_args, - 3, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_lh_args, - 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hl_args, - 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hh_args, - 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp24x2_args, - 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp24x2_args, - 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp48_args, - 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp48_args, - 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movpa24x2_args, - 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24a32x2_args, - 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_l_args, - 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_h_args, - 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, - 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24q48x2_args, - 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncp16_args, - 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48sym_args, - 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48asym_args, - 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48sym_args, - 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48asym_args, - 2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16sym_args, - 2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16asym_args, - 2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zeroq56_args, - 1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movq56_args, - 1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtq56_args, - 1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfq56_args, - 1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48a32s_args, - 1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_l_args, - 1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_h_args, - 1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_satq48s_args, - 2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncq32_args, - 1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32sym_args, - 2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32asym_args, - 2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca32q48_args, - 1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_l_args, - 1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_h_args, - 1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_l_args, - 1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_h_args, - 1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addp24_args, - 1, Iclass_ae_iclass_addp24_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_subp24_args, - 1, Iclass_ae_iclass_subp24_stateArgs, 0, 0 }, - { 2, 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Iclass_ae_iclass_mulzasq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sha32_args, - 0, 0, 0, 0 }, - { 3, Iclass_ae_iclass_vldl32t_args, - 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vldl16t_args, - 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldl16c_args, - 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldsht_args, - 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lb_args, - 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lbi_args, - 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbk_args, - 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbki_args, - 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_db_args, - 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_dbi_args, - 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel32t_args, - 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel16t_args, - 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sb_args, - 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sbi_args, - 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vles16c_args, - 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_sbf_args, - 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SLAASQ56S_args, - 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_ADDBRBA32_args, - 0, 0, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSP24S_args, - 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSP24S_args, - 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MINABSSQ56S_args, - 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_MAXABSSQ56S_args, - 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cbegin0_args, - 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cbegin0_args, - 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_cend0_args, - 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_cend0_args, - 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2_C_args, - 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2S_C_args, - 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24X2F_C_args, - 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24X2F_C_args, - 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16X2F_C_args, - 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16X2F_C_args, - 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24_C_args, - 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24S_L_C_args, - 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP24F_C_args, - 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP24F_L_C_args, - 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LP16F_C_args, - 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SP16F_L_C_args, - 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ56_C_args, - 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ56S_C_args, - 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_LQ32F_C_args, - 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, - { 3, Iclass_icls_AE_SQ32F_C_args, - 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 }, - { 1, Iclass_rur_expstate_args, - 2, Iclass_rur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_wur_expstate_args, - 2, Iclass_wur_expstate_stateArgs, 0, 0 }, - { 1, Iclass_iclass_READ_IMPWIRE_args, - 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, - { 1, Iclass_iclass_SETB_EXPSTATE_args, - 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, - { 1, Iclass_iclass_CLRB_EXPSTATE_args, - 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, - { 2, Iclass_iclass_WRMSK_EXPSTATE_args, - 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_rur_threadptr, - ICLASS_wur_threadptr, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s32nb, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_memctl, - ICLASS_xt_iclass_wsr_memctl, - ICLASS_xt_iclass_xsr_memctl, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_243, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_epc3, - ICLASS_xt_iclass_wsr_epc3, - ICLASS_xt_iclass_xsr_epc3, - ICLASS_xt_iclass_rsr_excsave3, - ICLASS_xt_iclass_wsr_excsave3, - ICLASS_xt_iclass_xsr_excsave3, - ICLASS_xt_iclass_rsr_epc4, - ICLASS_xt_iclass_wsr_epc4, - ICLASS_xt_iclass_xsr_epc4, - ICLASS_xt_iclass_rsr_excsave4, - ICLASS_xt_iclass_wsr_excsave4, - ICLASS_xt_iclass_xsr_excsave4, - ICLASS_xt_iclass_rsr_epc5, - ICLASS_xt_iclass_wsr_epc5, - ICLASS_xt_iclass_xsr_epc5, - ICLASS_xt_iclass_rsr_excsave5, - ICLASS_xt_iclass_wsr_excsave5, - ICLASS_xt_iclass_xsr_excsave5, - ICLASS_xt_iclass_rsr_epc6, - ICLASS_xt_iclass_wsr_epc6, - ICLASS_xt_iclass_xsr_epc6, - ICLASS_xt_iclass_rsr_excsave6, - ICLASS_xt_iclass_wsr_excsave6, - ICLASS_xt_iclass_xsr_excsave6, - ICLASS_xt_iclass_rsr_epc7, - ICLASS_xt_iclass_wsr_epc7, - ICLASS_xt_iclass_xsr_epc7, - ICLASS_xt_iclass_rsr_excsave7, - ICLASS_xt_iclass_wsr_excsave7, - ICLASS_xt_iclass_xsr_excsave7, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_eps3, - ICLASS_xt_iclass_wsr_eps3, - ICLASS_xt_iclass_xsr_eps3, - ICLASS_xt_iclass_rsr_eps4, - ICLASS_xt_iclass_wsr_eps4, - ICLASS_xt_iclass_xsr_eps4, - ICLASS_xt_iclass_rsr_eps5, - ICLASS_xt_iclass_wsr_eps5, - ICLASS_xt_iclass_xsr_eps5, - ICLASS_xt_iclass_rsr_eps6, - ICLASS_xt_iclass_wsr_eps6, - ICLASS_xt_iclass_xsr_eps6, - ICLASS_xt_iclass_rsr_eps7, - ICLASS_xt_iclass_wsr_eps7, - ICLASS_xt_iclass_xsr_eps7, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_mul32h, - ICLASS_xt_iclass_mac16_aa, - ICLASS_xt_iclass_mac16_ad, - ICLASS_xt_iclass_mac16_da, - ICLASS_xt_iclass_mac16_dd, - ICLASS_xt_iclass_mac16a_aa, - ICLASS_xt_iclass_mac16a_ad, - ICLASS_xt_iclass_mac16a_da, - ICLASS_xt_iclass_mac16a_dd, - ICLASS_xt_iclass_mac16al_da, - ICLASS_xt_iclass_mac16al_dd, - ICLASS_xt_iclass_mac16_l, - ICLASS_xt_iclass_rsr_m0, - ICLASS_xt_iclass_wsr_m0, - ICLASS_xt_iclass_xsr_m0, - ICLASS_xt_iclass_rsr_m1, - ICLASS_xt_iclass_wsr_m1, - ICLASS_xt_iclass_xsr_m1, - ICLASS_xt_iclass_rsr_m2, - ICLASS_xt_iclass_wsr_m2, - ICLASS_xt_iclass_xsr_m2, - ICLASS_xt_iclass_rsr_m3, - ICLASS_xt_iclass_wsr_m3, - ICLASS_xt_iclass_xsr_m3, - ICLASS_xt_iclass_rsr_acclo, - ICLASS_xt_iclass_wsr_acclo, - ICLASS_xt_iclass_xsr_acclo, - ICLASS_xt_iclass_rsr_acchi, - ICLASS_xt_iclass_wsr_acchi, - ICLASS_xt_iclass_xsr_acchi, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_dbreaka0, - ICLASS_xt_iclass_wsr_dbreaka0, - ICLASS_xt_iclass_xsr_dbreaka0, - ICLASS_xt_iclass_rsr_dbreakc0, - ICLASS_xt_iclass_wsr_dbreakc0, - ICLASS_xt_iclass_xsr_dbreakc0, - ICLASS_xt_iclass_rsr_dbreaka1, - ICLASS_xt_iclass_wsr_dbreaka1, - ICLASS_xt_iclass_xsr_dbreaka1, - ICLASS_xt_iclass_rsr_dbreakc1, - ICLASS_xt_iclass_wsr_dbreakc1, - ICLASS_xt_iclass_xsr_dbreakc1, - ICLASS_xt_iclass_rsr_ibreaka0, - ICLASS_xt_iclass_wsr_ibreaka0, - ICLASS_xt_iclass_xsr_ibreaka0, - ICLASS_xt_iclass_rsr_ibreaka1, - ICLASS_xt_iclass_wsr_ibreaka1, - ICLASS_xt_iclass_xsr_ibreaka1, - ICLASS_xt_iclass_rsr_ibreakenable, - ICLASS_xt_iclass_wsr_ibreakenable, - ICLASS_xt_iclass_xsr_ibreakenable, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_lddr32_p, - ICLASS_xt_iclass_sddr32_p, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_wsr_mmid, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_rsr_ccompare2, - ICLASS_xt_iclass_wsr_ccompare2, - ICLASS_xt_iclass_xsr_ccompare2, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_lock, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_dyn, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_dcache_lock, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_rsr_prefctl, - ICLASS_xt_iclass_wsr_prefctl, - ICLASS_xt_iclass_xsr_prefctl, - ICLASS_xt_iclass_wsr_ptevaddr, - ICLASS_xt_iclass_rsr_ptevaddr, - ICLASS_xt_iclass_xsr_ptevaddr, - ICLASS_xt_iclass_rsr_rasid, - ICLASS_xt_iclass_wsr_rasid, - ICLASS_xt_iclass_xsr_rasid, - ICLASS_xt_iclass_rsr_itlbcfg, - ICLASS_xt_iclass_wsr_itlbcfg, - ICLASS_xt_iclass_xsr_itlbcfg, - ICLASS_xt_iclass_rsr_dtlbcfg, - ICLASS_xt_iclass_wsr_dtlbcfg, - ICLASS_xt_iclass_xsr_dtlbcfg, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_ldpte, - ICLASS_xt_iclass_hwwitlba, - ICLASS_xt_iclass_hwwdtlba, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_div, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - ICLASS_ae_iclass_wur_ae_bitsused, - ICLASS_ae_iclass_rur_ae_tablesize, - ICLASS_ae_iclass_wur_ae_tablesize, - ICLASS_ae_iclass_rur_ae_first_ts, - ICLASS_ae_iclass_wur_ae_first_ts, - ICLASS_ae_iclass_rur_ae_nextoffset, - ICLASS_ae_iclass_wur_ae_nextoffset, - ICLASS_ae_iclass_rur_ae_searchdone, - ICLASS_ae_iclass_wur_ae_searchdone, - ICLASS_ae_iclass_lp16f_i, - ICLASS_ae_iclass_lp16f_iu, - ICLASS_ae_iclass_lp16f_x, - ICLASS_ae_iclass_lp16f_xu, - ICLASS_ae_iclass_lp24_i, - ICLASS_ae_iclass_lp24_iu, - ICLASS_ae_iclass_lp24_x, - ICLASS_ae_iclass_lp24_xu, - ICLASS_ae_iclass_lp24f_i, - ICLASS_ae_iclass_lp24f_iu, - ICLASS_ae_iclass_lp24f_x, - ICLASS_ae_iclass_lp24f_xu, - ICLASS_ae_iclass_lp16x2f_i, - ICLASS_ae_iclass_lp16x2f_iu, - ICLASS_ae_iclass_lp16x2f_x, - ICLASS_ae_iclass_lp16x2f_xu, - ICLASS_ae_iclass_lp24x2f_i, - ICLASS_ae_iclass_lp24x2f_iu, - ICLASS_ae_iclass_lp24x2f_x, - ICLASS_ae_iclass_lp24x2f_xu, - ICLASS_ae_iclass_lp24x2_i, - ICLASS_ae_iclass_lp24x2_iu, - ICLASS_ae_iclass_lp24x2_x, - ICLASS_ae_iclass_lp24x2_xu, - ICLASS_ae_iclass_sp16x2f_i, - ICLASS_ae_iclass_sp16x2f_iu, - ICLASS_ae_iclass_sp16x2f_x, - ICLASS_ae_iclass_sp16x2f_xu, - ICLASS_ae_iclass_sp24x2s_i, - ICLASS_ae_iclass_sp24x2s_iu, - ICLASS_ae_iclass_sp24x2s_x, - ICLASS_ae_iclass_sp24x2s_xu, - ICLASS_ae_iclass_sp24x2f_i, - ICLASS_ae_iclass_sp24x2f_iu, - ICLASS_ae_iclass_sp24x2f_x, - ICLASS_ae_iclass_sp24x2f_xu, - ICLASS_ae_iclass_sp16f_l_i, - ICLASS_ae_iclass_sp16f_l_iu, - ICLASS_ae_iclass_sp16f_l_x, - ICLASS_ae_iclass_sp16f_l_xu, - ICLASS_ae_iclass_sp24s_l_i, - ICLASS_ae_iclass_sp24s_l_iu, - ICLASS_ae_iclass_sp24s_l_x, - ICLASS_ae_iclass_sp24s_l_xu, - ICLASS_ae_iclass_sp24f_l_i, - ICLASS_ae_iclass_sp24f_l_iu, - ICLASS_ae_iclass_sp24f_l_x, - ICLASS_ae_iclass_sp24f_l_xu, - ICLASS_ae_iclass_lq56_i, - ICLASS_ae_iclass_lq56_iu, - ICLASS_ae_iclass_lq56_x, - ICLASS_ae_iclass_lq56_xu, - ICLASS_ae_iclass_lq32f_i, - ICLASS_ae_iclass_lq32f_iu, - ICLASS_ae_iclass_lq32f_x, - ICLASS_ae_iclass_lq32f_xu, - ICLASS_ae_iclass_sq56s_i, - ICLASS_ae_iclass_sq56s_iu, - ICLASS_ae_iclass_sq56s_x, - ICLASS_ae_iclass_sq56s_xu, - ICLASS_ae_iclass_sq32f_i, - ICLASS_ae_iclass_sq32f_iu, - ICLASS_ae_iclass_sq32f_x, - ICLASS_ae_iclass_sq32f_xu, - ICLASS_ae_iclass_zerop48, - ICLASS_ae_iclass_movp48, - ICLASS_ae_iclass_selp24_ll, - ICLASS_ae_iclass_selp24_lh, - ICLASS_ae_iclass_selp24_hl, - ICLASS_ae_iclass_selp24_hh, - ICLASS_ae_iclass_movtp24x2, - ICLASS_ae_iclass_movfp24x2, - ICLASS_ae_iclass_movtp48, - ICLASS_ae_iclass_movfp48, - ICLASS_ae_iclass_movpa24x2, - ICLASS_ae_iclass_truncp24a32x2, - ICLASS_ae_iclass_cvta32p24_l, - ICLASS_ae_iclass_cvta32p24_h, - ICLASS_ae_iclass_cvtp24a16x2_ll, - ICLASS_ae_iclass_cvtp24a16x2_lh, - ICLASS_ae_iclass_cvtp24a16x2_hl, - ICLASS_ae_iclass_cvtp24a16x2_hh, - ICLASS_ae_iclass_truncp24q48x2, - ICLASS_ae_iclass_truncp16, - ICLASS_ae_iclass_roundsp24q48sym, - ICLASS_ae_iclass_roundsp24q48asym, - ICLASS_ae_iclass_roundsp16q48sym, - ICLASS_ae_iclass_roundsp16q48asym, - ICLASS_ae_iclass_roundsp16sym, - ICLASS_ae_iclass_roundsp16asym, - ICLASS_ae_iclass_zeroq56, - ICLASS_ae_iclass_movq56, - ICLASS_ae_iclass_movtq56, - ICLASS_ae_iclass_movfq56, - ICLASS_ae_iclass_cvtq48a32s, - ICLASS_ae_iclass_cvtq48p24s_l, - ICLASS_ae_iclass_cvtq48p24s_h, - ICLASS_ae_iclass_satq48s, - ICLASS_ae_iclass_truncq32, - ICLASS_ae_iclass_roundsq32sym, - ICLASS_ae_iclass_roundsq32asym, - ICLASS_ae_iclass_trunca32q48, - ICLASS_ae_iclass_movap24s_l, - ICLASS_ae_iclass_movap24s_h, - ICLASS_ae_iclass_trunca16p24s_l, - ICLASS_ae_iclass_trunca16p24s_h, - ICLASS_ae_iclass_addp24, - ICLASS_ae_iclass_subp24, - ICLASS_ae_iclass_negp24, - ICLASS_ae_iclass_absp24, - ICLASS_ae_iclass_maxp24s, - ICLASS_ae_iclass_minp24s, - ICLASS_ae_iclass_maxbp24s, - ICLASS_ae_iclass_minbp24s, - ICLASS_ae_iclass_addsp24s, - ICLASS_ae_iclass_subsp24s, - ICLASS_ae_iclass_negsp24s, - ICLASS_ae_iclass_abssp24s, - ICLASS_ae_iclass_andp48, - ICLASS_ae_iclass_nandp48, - ICLASS_ae_iclass_orp48, - ICLASS_ae_iclass_xorp48, - ICLASS_ae_iclass_ltp24s, - ICLASS_ae_iclass_lep24s, - ICLASS_ae_iclass_eqp24, - ICLASS_ae_iclass_addq56, - ICLASS_ae_iclass_subq56, - ICLASS_ae_iclass_negq56, - ICLASS_ae_iclass_absq56, - ICLASS_ae_iclass_maxq56s, - ICLASS_ae_iclass_minq56s, - ICLASS_ae_iclass_maxbq56s, - ICLASS_ae_iclass_minbq56s, - ICLASS_ae_iclass_addsq56s, - ICLASS_ae_iclass_subsq56s, - ICLASS_ae_iclass_negsq56s, - ICLASS_ae_iclass_abssq56s, - ICLASS_ae_iclass_andq56, - ICLASS_ae_iclass_nandq56, - ICLASS_ae_iclass_orq56, - ICLASS_ae_iclass_xorq56, - ICLASS_ae_iclass_sllip24, - ICLASS_ae_iclass_srlip24, - ICLASS_ae_iclass_sraip24, - ICLASS_ae_iclass_sllsp24, - ICLASS_ae_iclass_srlsp24, - ICLASS_ae_iclass_srasp24, - ICLASS_ae_iclass_sllisp24s, - ICLASS_ae_iclass_sllssp24s, - ICLASS_ae_iclass_slliq56, - ICLASS_ae_iclass_srliq56, - ICLASS_ae_iclass_sraiq56, - ICLASS_ae_iclass_sllsq56, - ICLASS_ae_iclass_srlsq56, - ICLASS_ae_iclass_srasq56, - ICLASS_ae_iclass_sllaq56, - ICLASS_ae_iclass_srlaq56, - ICLASS_ae_iclass_sraaq56, - ICLASS_ae_iclass_sllisq56s, - ICLASS_ae_iclass_sllssq56s, - ICLASS_ae_iclass_sllasq56s, - ICLASS_ae_iclass_ltq56s, - ICLASS_ae_iclass_leq56s, - ICLASS_ae_iclass_eqq56, - ICLASS_ae_iclass_nsaq56s, - ICLASS_ae_iclass_mulsrfq32sp24s_h, - ICLASS_ae_iclass_mulsrfq32sp24s_l, - ICLASS_ae_iclass_mularfq32sp24s_h, - ICLASS_ae_iclass_mularfq32sp24s_l, - ICLASS_ae_iclass_mulrfq32sp24s_h, - ICLASS_ae_iclass_mulrfq32sp24s_l, - ICLASS_ae_iclass_mulsfq32sp24s_h, - ICLASS_ae_iclass_mulsfq32sp24s_l, - ICLASS_ae_iclass_mulafq32sp24s_h, - ICLASS_ae_iclass_mulafq32sp24s_l, - ICLASS_ae_iclass_mulfq32sp24s_h, - ICLASS_ae_iclass_mulfq32sp24s_l, - ICLASS_ae_iclass_mulfs32p16s_ll, - ICLASS_ae_iclass_mulfp24s_ll, - ICLASS_ae_iclass_mulp24s_ll, - ICLASS_ae_iclass_mulfs32p16s_lh, - ICLASS_ae_iclass_mulfp24s_lh, - ICLASS_ae_iclass_mulp24s_lh, - ICLASS_ae_iclass_mulfs32p16s_hl, - ICLASS_ae_iclass_mulfp24s_hl, - ICLASS_ae_iclass_mulp24s_hl, - ICLASS_ae_iclass_mulfs32p16s_hh, - ICLASS_ae_iclass_mulfp24s_hh, - ICLASS_ae_iclass_mulp24s_hh, - ICLASS_ae_iclass_mulafs32p16s_ll, - ICLASS_ae_iclass_mulafp24s_ll, - ICLASS_ae_iclass_mulap24s_ll, - ICLASS_ae_iclass_mulafs32p16s_lh, - ICLASS_ae_iclass_mulafp24s_lh, - ICLASS_ae_iclass_mulap24s_lh, - ICLASS_ae_iclass_mulafs32p16s_hl, - ICLASS_ae_iclass_mulafp24s_hl, - ICLASS_ae_iclass_mulap24s_hl, - ICLASS_ae_iclass_mulafs32p16s_hh, - ICLASS_ae_iclass_mulafp24s_hh, - ICLASS_ae_iclass_mulap24s_hh, - ICLASS_ae_iclass_mulsfs32p16s_ll, - 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ICLASS_ae_iclass_lb, - ICLASS_ae_iclass_lbi, - ICLASS_ae_iclass_lbk, - ICLASS_ae_iclass_lbki, - ICLASS_ae_iclass_db, - ICLASS_ae_iclass_dbi, - ICLASS_ae_iclass_vlel32t, - ICLASS_ae_iclass_vlel16t, - ICLASS_ae_iclass_sb, - ICLASS_ae_iclass_sbi, - ICLASS_ae_iclass_vles16c, - ICLASS_ae_iclass_sbf, - ICLASS_icls_AE_SLAASQ56S, - ICLASS_icls_AE_ADDBRBA32, - ICLASS_icls_AE_MINABSSP24S, - ICLASS_icls_AE_MAXABSSP24S, - ICLASS_icls_AE_MINABSSQ56S, - ICLASS_icls_AE_MAXABSSQ56S, - ICLASS_rur_ae_cbegin0, - ICLASS_wur_ae_cbegin0, - ICLASS_rur_ae_cend0, - ICLASS_wur_ae_cend0, - ICLASS_icls_AE_LP24X2_C, - ICLASS_icls_AE_SP24X2S_C, - ICLASS_icls_AE_LP24X2F_C, - ICLASS_icls_AE_SP24X2F_C, - ICLASS_icls_AE_LP16X2F_C, - ICLASS_icls_AE_SP16X2F_C, - ICLASS_icls_AE_LP24_C, - ICLASS_icls_AE_SP24S_L_C, - ICLASS_icls_AE_LP24F_C, - ICLASS_icls_AE_SP24F_L_C, - ICLASS_icls_AE_LP16F_C, - ICLASS_icls_AE_SP16F_L_C, - ICLASS_icls_AE_LQ56_C, - ICLASS_icls_AE_SQ56S_C, - ICLASS_icls_AE_LQ32F_C, - ICLASS_icls_AE_SQ32F_C, - ICLASS_rur_expstate, - ICLASS_wur_expstate, - ICLASS_iclass_READ_IMPWIRE, - ICLASS_iclass_SETB_EXPSTATE, - ICLASS_iclass_CLRB_EXPSTATE, - ICLASS_iclass_WRMSK_EXPSTATE -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80200; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2300; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c0000; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580000; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x540000; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0000; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb0000; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70000; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6c0000; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x804; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10f; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4300; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5300; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x94; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4830; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4831; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4816; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4930; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4931; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4916; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc800; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc00; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd60f; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd000; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc000; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30f; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00f; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7e03e; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe73f; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200c00; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100002; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200d00; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200002; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb81; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1381; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2381; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4b81; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4d01; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf81; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4d81; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b81; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2501; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4f01; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680000; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x690000; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1800003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b0000; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800003; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6a0000; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000003; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700600; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700e00; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80002; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f0000; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000003; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e0000; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000003; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700100; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700900; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700a00; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600002; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700200; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680002; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700b00; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380002; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700300; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700002; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700800; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500002; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700000; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700400; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180002; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700c00; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780002; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700500; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580002; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700d00; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280002; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x640000; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x101; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x650000; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x181; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x670000; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x281; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x660000; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x681; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0000; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x983d01; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200100; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200004; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200900; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100004; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200200; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400004; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0800; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0900; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0a00; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200a00; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x301; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x38; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7381; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x39; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd01; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x701; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x581; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed81; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1006; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed81; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0200; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36001; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb83d01; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1500; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200500; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200600; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x95; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200400; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x983d81; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4183d01; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2183d01; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x304; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1183d01; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18e501; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2806f81; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4781; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x19; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7ed81; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5ed81; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x12; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x381; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd81; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0200; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0200; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20200; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x131; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x116; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x231; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x216; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x331; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x316; -} - -static void -Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6130; -} - -static void -Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6131; -} - -static void -Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6116; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x531; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x516; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb030; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb031; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd030; -} - -static void -Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf330; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe630; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe631; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe616; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb130; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb131; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb116; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd130; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd131; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd116; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb230; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb231; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb216; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd230; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd231; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd216; -} - -static void -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb330; -} - -static void -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb331; -} - -static void -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb316; -} - -static void -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd330; -} - -static void -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd331; -} - -static void -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd316; -} - -static void -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb430; -} - -static void -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb431; -} - -static void -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb416; -} - -static void -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd430; -} - -static void -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd431; -} - -static void -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd416; -} - -static void -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb530; -} - -static void -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb531; -} - -static void -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb516; -} - -static void -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd530; -} - -static void -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd531; -} - -static void -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd516; -} - -static void -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb630; -} - -static void -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb631; -} - -static void -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb616; -} - -static void -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd630; -} - -static void -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd631; -} - -static void -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd616; -} - -static void -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb730; -} - -static void -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb731; -} - -static void -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb716; -} - -static void -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd730; -} - -static void -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd731; -} - -static void -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd716; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc230; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc231; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc216; -} - -static void -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc330; -} - -static void -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc331; -} - -static void -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc316; -} - -static void -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc430; -} - -static void -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc431; -} - -static void -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc416; -} - -static void -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc530; -} - -static void -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc531; -} - -static void -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc516; -} - -static void -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc630; -} - -static void -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc631; -} - -static void -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc616; -} - -static void -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc730; -} - -static void -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc731; -} - -static void -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc716; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee30; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee31; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xee16; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc030; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc031; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc016; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe830; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe831; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe816; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf430; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf431; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf416; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf530; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf531; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf516; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xeb30; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe730; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe731; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe716; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x28; -} - -static void -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2a; -} - -static void -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b; -} - -static void -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400047; -} - -static void -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400057; -} - -static void -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400067; -} - -static void -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400077; -} - -static void -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400007; -} - -static void -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400017; -} - -static void -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400027; -} - -static void -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400037; -} - -static void -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400043; -} - -static void -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400053; -} - -static void -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400063; -} - -static void -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400073; -} - -static void -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400046; -} - -static void -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400056; -} - -static void -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400066; -} - -static void -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400076; -} - -static void -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400042; -} - -static void -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400052; -} - -static void -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400062; -} - -static void -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400072; -} - -static void -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400087; -} - -static void -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400097; -} - -static void -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a7; -} - -static void -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b7; -} - -static void -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c7; -} - -static void -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d7; -} - -static void -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e7; -} - -static void -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f7; -} - -static void -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400083; -} - -static void -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400093; -} - -static void -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a3; -} - -static void -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b3; -} - -static void -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c3; -} - -static void -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d3; -} - -static void -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e3; -} - -static void -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f3; -} - -static void -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400086; -} - -static void -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400096; -} - -static void -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a6; -} - -static void -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b6; -} - -static void -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c6; -} - -static void -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d6; -} - -static void -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e6; -} - -static void -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f6; -} - -static void -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400082; -} - -static void -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400092; -} - -static void -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a2; -} - -static void -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b2; -} - -static void -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c2; -} - -static void -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d2; -} - -static void -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e2; -} - -static void -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f2; -} - -static void -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400085; -} - -static void -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400084; -} - -static void -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400095; -} - -static void -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400094; -} - -static void -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a5; -} - -static void -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a4; -} - -static void -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b5; -} - -static void -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b4; -} - -static void -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400081; -} - -static void -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400091; -} - -static void -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400090; -} - -static void -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a1; -} - -static void -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a0; -} - -static void -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b1; -} - -static void -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b0; -} - -static void -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400009; -} - -static void -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400008; -} - -static void -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2031; -} - -static void -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2016; -} - -static void -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2130; -} - -static void -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2131; -} - -static void -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2116; -} - -static void -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2230; -} - -static void -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2231; -} - -static void -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2216; -} - -static void -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2330; -} - -static void -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2331; -} - -static void -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2316; -} - -static void -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1030; -} - -static void -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1031; -} - -static void -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1016; -} - -static void -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1130; -} - -static void -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1131; -} - -static void -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1116; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10300; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe230; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe231; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe331; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe430; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe431; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe416; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd20f; -} - -static void -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9030; -} - -static void -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9031; -} - -static void -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9016; -} - -static void -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa030; -} - -static void -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa031; -} - -static void -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa016; -} - -static void -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9130; -} - -static void -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9131; -} - -static void -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9116; -} - -static void -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa130; -} - -static void -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa131; -} - -static void -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa116; -} - -static void -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8030; -} - -static void -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8031; -} - -static void -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8016; -} - -static void -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8130; -} - -static void -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8131; -} - -static void -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8116; -} - -static void -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6030; -} - -static void -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6031; -} - -static void -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6016; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe930; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe931; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe916; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec30; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec31; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xec16; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed30; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed31; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed16; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6830; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6831; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6816; -} - -static void -Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0700; -} - -static void -Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0700; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe1f; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10e1f; -} - -static void -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5931; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5381; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x21; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b81; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x22; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4581; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x23; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x781; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x24; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4f81; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96501; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8e501; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc6501; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6501; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0000; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2800003; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d0100; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000003; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7b81; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1501; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x431; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x416; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea30; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea31; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xea16; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf030; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf031; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf016; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf130; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf131; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf116; -} - -static void -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf230; -} - -static void -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf231; -} - -static void -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf216; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c0700; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0700; -} - -static void -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0700; -} - -static void -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0720; -} - -static void -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d0730; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f0700; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x21f; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x11f; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x31f; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240700; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x250700; -} - -static void -Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2807f0; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280740; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280750; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x260700; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x270700; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200700; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210700; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220700; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230700; -} - -static void -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280700; -} - -static void -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280720; -} - -static void -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280730; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x91f; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81f; -} - -static void -Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2830; -} - -static void -Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2831; -} - -static void -Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2816; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5331; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5330; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5316; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a30; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a31; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5a16; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b30; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b31; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5b16; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c30; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c31; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5c16; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc05; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd05; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb05; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf05; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe05; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x405; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x305; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x705; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x605; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x105; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x905; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe030; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe031; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe016; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x33; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2b81; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b81; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3381; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6b81; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x37; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6381; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe04; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf04; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x32; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4701; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200b00; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200f00; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200e00; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc31; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc16; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6330; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6331; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6316; -} - -static void -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2c; -} - -static void -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d; -} - -static void -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e; -} - -static void -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x604; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x704; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03e; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03f; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f03e; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13f; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f03e; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf23f; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f03e; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf33f; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40809c; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000ac; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40909c; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4001ac; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40a09c; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002ac; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40b09c; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4003ac; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40c09c; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4004ac; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40d09c; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4005ac; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e09c; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4006ac; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f09c; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007ac; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81581; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005a; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1781; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009a; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81701; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000ca; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81781; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000fa; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81d81; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40085a; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81f01; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40089a; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81f81; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008ca; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5581; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008fa; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5701; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006a; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5d01; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000aa; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85501; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000da; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5781; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000b; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d81; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40086a; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f01; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008aa; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81d01; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008da; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f81; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40080b; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85701; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007a; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85d01; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000ba; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85781; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000ea; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85d81; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001b; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5d81; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40087a; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5f01; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008ba; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5f81; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008ea; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85581; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40081b; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3501; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002b; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6501; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005b; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82581; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008b; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2781; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000bb; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83501; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40082b; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3781; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40085b; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d81; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40088b; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f01; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008bb; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82f81; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003b; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3581; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006b; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3701; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009b; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d01; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000cb; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85f81; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40083b; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2581; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40086b; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2701; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40089b; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d01; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008cb; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82d01; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004b; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f81; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007b; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82d81; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000ab; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82f01; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000db; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82701; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40084b; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x82781; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40087b; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2d81; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008ab; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2f01; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008db; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x206581; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001c; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406581; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40021c; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x606581; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002c; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6781; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40022c; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6581; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40011c; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6701; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40031c; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d01; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40012c; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7501; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40032c; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83781; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003c; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x183701; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40083c; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x183781; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004c; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83d81; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40084c; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83581; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40043c; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83701; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400c3c; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83d01; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40044c; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x183581; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400c4c; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x46001; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86001; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86501; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009c; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd081; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x24000; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x89001; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd001; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc000; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9081; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402081; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x202081; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2001; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1001; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85f01; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000c; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f81; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40080c; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83f81; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000bc; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x83f01; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008bc; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5501; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000eb; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d01; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008eb; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1701; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000fb; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1581; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008fb; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86e01; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3881; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3481; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3281; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3081; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86401; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86201; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x284581; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380581; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xef01; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41409c; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x806f81; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41005e; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f81; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41006e; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x206701; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x43027e; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300581; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280581; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x488605; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c0581; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3a0581; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x390581; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x183d81; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41007e; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1083f01; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007c; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x883f01; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40087c; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4083f01; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008c; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2083f01; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40088c; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1081; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x89081; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6001; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81081; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5081; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x81; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5001; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8d001; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26001; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa001; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9001; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85001; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x85081; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8d081; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x102081; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2081; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280605; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600605; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480605; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100605; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200605; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x205; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x605; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300605; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x484605; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500605; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80605; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400605; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180605; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380605; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x101; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x301; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86801; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86c01; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86a01; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x181; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86601; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6d81; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005c; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16d81; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40105c; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xed81; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40205c; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16f01; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41009c; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80ef01; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41109c; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4ef01; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41209c; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1006f81; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41001e; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1806f81; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41002e; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4006f81; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41003e; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f01; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40305c; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2ef01; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41309c; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2006f81; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41004e; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10005; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x805; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x405; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x183d01; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41047e; -} - -static void -Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500901; -} - -static void -Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300901; -} - -static void -Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600901; -} - -static void -Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100901; -} - -static void -Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400901; -} - -static void -Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200901; -} - -static void -Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680901; -} - -static void -Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180901; -} - -static void -Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480901; -} - -static void -Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280901; -} - -static void -Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700901; -} - -static void -Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80901; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100086; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x88186; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180006; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c186; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c006; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x108006; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c106; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x88106; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104006; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c086; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x88086; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100106; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4106; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200006; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc186; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4086; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100006; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc106; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x186; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80006; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc086; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400006; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8006; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8186; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180086; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x108186; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x188086; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10c186; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10c006; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x184186; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10c106; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x108106; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x184106; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10c086; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x108086; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x184086; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc006; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x88006; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8106; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x84006; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8086; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80106; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4186; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80086; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180186; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18c086; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x188006; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x188186; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x184006; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18c006; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180106; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x188106; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380381; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300381; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500381; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480381; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580381; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600381; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700381; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680381; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x381; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x901; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100381; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80381; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400381; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200381; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280381; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180381; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x581; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780381; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80581; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x701; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200581; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100581; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180581; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400581; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380002; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600002; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180002; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280002; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480002; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200002; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80002; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500002; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400002; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400003; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700002; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80003; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100003; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580002; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780002; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200003; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680002; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280003; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500003; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680003; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700003; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380003; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80004; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600003; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780003; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480003; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100004; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580003; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x580004; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280004; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x780004; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x480004; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500004; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400004; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x680004; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600004; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180004; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x700004; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x380004; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204006; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280006; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x208006; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200186; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204106; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204086; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x204186; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x208086; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c006; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x208106; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x208186; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c086; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c186; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c106; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x280086; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x106; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x86; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4006; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80186; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x84106; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x84086; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x84186; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100186; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104086; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x104186; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18c106; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200086; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18c186; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200106; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x41000e; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000a; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001a; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410e7e; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4008ac; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006c; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x42000e; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002a; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000e; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40010f; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40020f; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003a; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004a; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40011f; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000f; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410c7e; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410d7e; -} - -static void -Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6006f81; -} - -static void -Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8e001; -} - -static void -Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe001; -} - -static void -Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x240005; -} - -static void -Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x440005; -} - -static void -Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6f03e; -} - -static void -Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf63f; -} - -static void -Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f03e; -} - -static void -Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf73f; -} - -static void -Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f01; -} - -static void -Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87781; -} - -static void -Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87f01; -} - -static void -Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7781; -} - -static void -Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87d01; -} - -static void -Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87581; -} - -static void -Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7701; -} - -static void -Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87d81; -} - -static void -Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87701; -} - -static void -Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d81; -} - -static void -Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7d01; -} - -static void -Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7581; -} - -static void -Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x207501; -} - -static void -Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x87f81; -} - -static void -Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407501; -} - -static void -Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7f81; -} - -static void -Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6e03e; -} - -static void -Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe63f; -} - -static void -Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0; -} - -static void -Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x21e0; -} - -static void -Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2e0; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { - Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { - Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { - Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { - Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { - Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { - Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { - Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { - Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { - Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { - Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { - Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { - Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { - Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { - Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { - Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { - 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { - Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { - Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { - Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { - Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { - Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { - Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0 -}; - - - - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s32nb", ICLASS_xt_iclass_s32nb, - 0, - Opcode_s32nb_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, - 0, - Opcode_rsr_memctl_encode_fns, 0, 0 }, - { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, - 0, - Opcode_wsr_memctl_encode_fns, 0, 0 }, - { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, - 0, - Opcode_xsr_memctl_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.243", ICLASS_xt_iclass_rsr_243, - 0, - Opcode_rsr_243_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, - 0, - Opcode_rsr_epc3_encode_fns, 0, 0 }, - { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, - 0, - Opcode_wsr_epc3_encode_fns, 0, 0 }, - { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, - 0, - Opcode_xsr_epc3_encode_fns, 0, 0 }, - { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, - 0, - Opcode_rsr_excsave3_encode_fns, 0, 0 }, - { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, - 0, - Opcode_wsr_excsave3_encode_fns, 0, 0 }, - { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, - 0, - Opcode_xsr_excsave3_encode_fns, 0, 0 }, - { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, - 0, - Opcode_rsr_epc4_encode_fns, 0, 0 }, - { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, - 0, - Opcode_wsr_epc4_encode_fns, 0, 0 }, - { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, - 0, - Opcode_xsr_epc4_encode_fns, 0, 0 }, - { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, - 0, - Opcode_rsr_excsave4_encode_fns, 0, 0 }, - { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, - 0, - Opcode_wsr_excsave4_encode_fns, 0, 0 }, - { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, - 0, - Opcode_xsr_excsave4_encode_fns, 0, 0 }, - { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, - 0, - Opcode_rsr_epc5_encode_fns, 0, 0 }, - { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, - 0, - Opcode_wsr_epc5_encode_fns, 0, 0 }, - { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, - 0, - Opcode_xsr_epc5_encode_fns, 0, 0 }, - { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, - 0, - Opcode_rsr_excsave5_encode_fns, 0, 0 }, - { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, - 0, - Opcode_wsr_excsave5_encode_fns, 0, 0 }, - { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, - 0, - Opcode_xsr_excsave5_encode_fns, 0, 0 }, - { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, - 0, - Opcode_rsr_epc6_encode_fns, 0, 0 }, - { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, - 0, - Opcode_wsr_epc6_encode_fns, 0, 0 }, - { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, - 0, - Opcode_xsr_epc6_encode_fns, 0, 0 }, - { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, - 0, - Opcode_rsr_excsave6_encode_fns, 0, 0 }, - { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, - 0, - Opcode_wsr_excsave6_encode_fns, 0, 0 }, - { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, - 0, - Opcode_xsr_excsave6_encode_fns, 0, 0 }, - { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, - 0, - Opcode_rsr_epc7_encode_fns, 0, 0 }, - { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, - 0, - Opcode_wsr_epc7_encode_fns, 0, 0 }, - { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, - 0, - Opcode_xsr_epc7_encode_fns, 0, 0 }, - { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, - 0, - Opcode_rsr_excsave7_encode_fns, 0, 0 }, - { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, - 0, - Opcode_wsr_excsave7_encode_fns, 0, 0 }, - { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, - 0, - Opcode_xsr_excsave7_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, - 0, - Opcode_rsr_eps3_encode_fns, 0, 0 }, - { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, - 0, - Opcode_wsr_eps3_encode_fns, 0, 0 }, - { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, - 0, - Opcode_xsr_eps3_encode_fns, 0, 0 }, - { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, - 0, - Opcode_rsr_eps4_encode_fns, 0, 0 }, - { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, - 0, - Opcode_wsr_eps4_encode_fns, 0, 0 }, - { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, - 0, - Opcode_xsr_eps4_encode_fns, 0, 0 }, - { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, - 0, - Opcode_rsr_eps5_encode_fns, 0, 0 }, - { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, - 0, - Opcode_wsr_eps5_encode_fns, 0, 0 }, - { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, - 0, - Opcode_xsr_eps5_encode_fns, 0, 0 }, - { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, - 0, - Opcode_rsr_eps6_encode_fns, 0, 0 }, - { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, - 0, - Opcode_wsr_eps6_encode_fns, 0, 0 }, - { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, - 0, - Opcode_xsr_eps6_encode_fns, 0, 0 }, - { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, - 0, - Opcode_rsr_eps7_encode_fns, 0, 0 }, - { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, - 0, - Opcode_wsr_eps7_encode_fns, 0, 0 }, - { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, - 0, - Opcode_xsr_eps7_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "muluh", ICLASS_xt_mul32h, - 0, - Opcode_muluh_encode_fns, 0, 0 }, - { "mulsh", ICLASS_xt_mul32h, - 0, - Opcode_mulsh_encode_fns, 0, 0 }, - { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_ll_encode_fns, 0, 0 }, - { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hl_encode_fns, 0, 0 }, - { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_lh_encode_fns, 0, 0 }, - { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_mul_aa_hh_encode_fns, 0, 0 }, - { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_ll_encode_fns, 0, 0 }, - { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hl_encode_fns, 0, 0 }, - { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_lh_encode_fns, 0, 0 }, - { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, - 0, - Opcode_umul_aa_hh_encode_fns, 0, 0 }, - { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_ll_encode_fns, 0, 0 }, - { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hl_encode_fns, 0, 0 }, - { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_lh_encode_fns, 0, 0 }, - { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, - 0, - Opcode_mul_ad_hh_encode_fns, 0, 0 }, - { "mul.da.ll", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_ll_encode_fns, 0, 0 }, - { "mul.da.hl", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hl_encode_fns, 0, 0 }, - { "mul.da.lh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_lh_encode_fns, 0, 0 }, - { "mul.da.hh", ICLASS_xt_iclass_mac16_da, - 0, - Opcode_mul_da_hh_encode_fns, 0, 0 }, - { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_ll_encode_fns, 0, 0 }, - { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hl_encode_fns, 0, 0 }, - { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_lh_encode_fns, 0, 0 }, - { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, - 0, - Opcode_mul_dd_hh_encode_fns, 0, 0 }, - { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_ll_encode_fns, 0, 0 }, - { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hl_encode_fns, 0, 0 }, - { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_lh_encode_fns, 0, 0 }, - { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_mula_aa_hh_encode_fns, 0, 0 }, - { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_ll_encode_fns, 0, 0 }, - { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hl_encode_fns, 0, 0 }, - { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_lh_encode_fns, 0, 0 }, - { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, - 0, - Opcode_muls_aa_hh_encode_fns, 0, 0 }, - { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_ll_encode_fns, 0, 0 }, - { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hl_encode_fns, 0, 0 }, - { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_lh_encode_fns, 0, 0 }, - { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_mula_ad_hh_encode_fns, 0, 0 }, - { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_ll_encode_fns, 0, 0 }, - { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hl_encode_fns, 0, 0 }, - { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_lh_encode_fns, 0, 0 }, - { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, - 0, - Opcode_muls_ad_hh_encode_fns, 0, 0 }, - { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_ll_encode_fns, 0, 0 }, - { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hl_encode_fns, 0, 0 }, - { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_lh_encode_fns, 0, 0 }, - { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_mula_da_hh_encode_fns, 0, 0 }, - { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_ll_encode_fns, 0, 0 }, - { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hl_encode_fns, 0, 0 }, - { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_lh_encode_fns, 0, 0 }, - { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, - 0, - Opcode_muls_da_hh_encode_fns, 0, 0 }, - { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_ll_encode_fns, 0, 0 }, - { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hl_encode_fns, 0, 0 }, - { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_lh_encode_fns, 0, 0 }, - { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_mula_dd_hh_encode_fns, 0, 0 }, - { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_ll_encode_fns, 0, 0 }, - { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hl_encode_fns, 0, 0 }, - { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_lh_encode_fns, 0, 0 }, - { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, - 0, - Opcode_muls_dd_hh_encode_fns, 0, 0 }, - { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, - { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, - { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, - { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, - { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, - { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, - { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, - { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, - 0, - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, - { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, - { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, - { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, - { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, - { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, - { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, - 0, - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, - { "lddec", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_lddec_encode_fns, 0, 0 }, - { "ldinc", ICLASS_xt_iclass_mac16_l, - 0, - Opcode_ldinc_encode_fns, 0, 0 }, - { "rsr.m0", ICLASS_xt_iclass_rsr_m0, - 0, - Opcode_rsr_m0_encode_fns, 0, 0 }, - { "wsr.m0", ICLASS_xt_iclass_wsr_m0, - 0, - Opcode_wsr_m0_encode_fns, 0, 0 }, - { "xsr.m0", ICLASS_xt_iclass_xsr_m0, - 0, - Opcode_xsr_m0_encode_fns, 0, 0 }, - { "rsr.m1", ICLASS_xt_iclass_rsr_m1, - 0, - Opcode_rsr_m1_encode_fns, 0, 0 }, - { "wsr.m1", ICLASS_xt_iclass_wsr_m1, - 0, - Opcode_wsr_m1_encode_fns, 0, 0 }, - { "xsr.m1", ICLASS_xt_iclass_xsr_m1, - 0, - Opcode_xsr_m1_encode_fns, 0, 0 }, - { "rsr.m2", ICLASS_xt_iclass_rsr_m2, - 0, - Opcode_rsr_m2_encode_fns, 0, 0 }, - { "wsr.m2", ICLASS_xt_iclass_wsr_m2, - 0, - Opcode_wsr_m2_encode_fns, 0, 0 }, - { "xsr.m2", ICLASS_xt_iclass_xsr_m2, - 0, - Opcode_xsr_m2_encode_fns, 0, 0 }, - { "rsr.m3", ICLASS_xt_iclass_rsr_m3, - 0, - Opcode_rsr_m3_encode_fns, 0, 0 }, - { "wsr.m3", ICLASS_xt_iclass_wsr_m3, - 0, - Opcode_wsr_m3_encode_fns, 0, 0 }, - { "xsr.m3", ICLASS_xt_iclass_xsr_m3, - 0, - Opcode_xsr_m3_encode_fns, 0, 0 }, - { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, - 0, - Opcode_rsr_acclo_encode_fns, 0, 0 }, - { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, - 0, - Opcode_wsr_acclo_encode_fns, 0, 0 }, - { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, - 0, - Opcode_xsr_acclo_encode_fns, 0, 0 }, - { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, - 0, - Opcode_rsr_acchi_encode_fns, 0, 0 }, - { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, - 0, - Opcode_wsr_acchi_encode_fns, 0, 0 }, - { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, - 0, - Opcode_xsr_acchi_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, - 0, - Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, - { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, - 0, - Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, - { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, - 0, - Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, - { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, - 0, - Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, - { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, - 0, - Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, - { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, - 0, - Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, - { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, - 0, - Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, - { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, - 0, - Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, - { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, - 0, - Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, - { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, - 0, - Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, - { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, - 0, - Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, - { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, - 0, - Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, - { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, - 0, - Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, - { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, - 0, - Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, - { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, - 0, - Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, - { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, - 0, - Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, - { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, - 0, - Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, - { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, - 0, - Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, - { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, - 0, - Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, - { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, - 0, - Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, - { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, - 0, - Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "lddr32.p", ICLASS_xt_iclass_lddr32_p, - 0, - Opcode_lddr32_p_encode_fns, 0, 0 }, - { "sddr32.p", ICLASS_xt_iclass_sddr32_p, - 0, - Opcode_sddr32_p_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, - 0, - Opcode_wsr_mmid_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, - 0, - Opcode_rsr_ccompare2_encode_fns, 0, 0 }, - { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, - 0, - Opcode_wsr_ccompare2_encode_fns, 0, 0 }, - { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, - 0, - Opcode_xsr_ccompare2_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "ipfl", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ipfl_encode_fns, 0, 0 }, - { "ihu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_ihu_encode_fns, 0, 0 }, - { "iiu", ICLASS_xt_iclass_icache_lock, - 0, - Opcode_iiu_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, - 0, - Opcode_diwbui_p_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "dpfl", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dpfl_encode_fns, 0, 0 }, - { "dhu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_dhu_encode_fns, 0, 0 }, - { "diu", ICLASS_xt_iclass_dcache_lock, - 0, - Opcode_diu_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, - 0, - Opcode_rsr_prefctl_encode_fns, 0, 0 }, - { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, - 0, - Opcode_wsr_prefctl_encode_fns, 0, 0 }, - { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, - 0, - Opcode_xsr_prefctl_encode_fns, 0, 0 }, - { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", ICLASS_xt_iclass_ldpte, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", ICLASS_xt_iclass_hwwitlba, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "quou", ICLASS_xt_iclass_div, - 0, - Opcode_quou_encode_fns, 0, 0 }, - { "quos", ICLASS_xt_iclass_div, - 0, - Opcode_quos_encode_fns, 0, 0 }, - { "remu", ICLASS_xt_iclass_div, - 0, - Opcode_remu_encode_fns, 0, 0 }, - { "rems", ICLASS_xt_iclass_div, - 0, - Opcode_rems_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, - 0, - Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, - { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, - 0, - Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, - { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, - 0, - Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, - { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, - 0, - Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, - { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, - 0, - Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, - { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, - 0, - Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, - { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, - 0, - Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, - { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, - 0, - Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, - { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, - 0, - Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, - { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, - 0, - Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, - { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, - 0, - Opcode_ae_lp16f_i_encode_fns, 0, 0 }, - { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, - 0, - Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, - { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, - 0, - Opcode_ae_lp16f_x_encode_fns, 0, 0 }, - { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, - 0, - Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, - { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, - 0, - Opcode_ae_lp24_i_encode_fns, 0, 0 }, - { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, - 0, - Opcode_ae_lp24_iu_encode_fns, 0, 0 }, - { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, - 0, - Opcode_ae_lp24_x_encode_fns, 0, 0 }, - { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, - 0, - Opcode_ae_lp24_xu_encode_fns, 0, 0 }, - { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, - 0, - Opcode_ae_lp24f_i_encode_fns, 0, 0 }, - { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, - 0, - Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, - { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, - 0, - Opcode_ae_lp24f_x_encode_fns, 0, 0 }, - { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, - 0, - Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, - { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, - 0, - Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, - { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, - 0, - Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, - { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, - 0, - Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, - { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, - 0, - Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, - 0, - Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, - { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, - 0, - Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, - { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, - 0, - Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, - { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, - 0, - Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, - 0, - Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, - { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, - 0, - Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, - { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, - 0, - Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, - { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, - 0, - Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, - { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, - 0, - Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, - { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, - 0, - Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, - { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, - 0, - Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, - { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, - 0, - Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, - { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, - 0, - Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, - { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, - 0, - Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, - { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, - 0, - Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, - { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, - 0, - Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, - { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, - 0, - Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, - { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, - 0, - Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, - { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, - 0, - Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, - { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, - 0, - Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, - { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, - 0, - Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, - { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, - 0, - Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, - { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, - 0, - Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, - { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, - 0, - Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, - { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, - 0, - Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, - { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, - 0, - Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, - { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, - 0, - Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, - { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, - 0, - Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, - { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, - 0, - Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, - { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, - 0, - Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, - { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, - 0, - Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, - { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, - 0, - Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, - { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, - 0, - Opcode_ae_lq56_i_encode_fns, 0, 0 }, - { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, - 0, - Opcode_ae_lq56_iu_encode_fns, 0, 0 }, - { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, - 0, - Opcode_ae_lq56_x_encode_fns, 0, 0 }, - { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, - 0, - Opcode_ae_lq56_xu_encode_fns, 0, 0 }, - { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, - 0, - Opcode_ae_lq32f_i_encode_fns, 0, 0 }, - { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, - 0, - Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, - { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, - 0, - Opcode_ae_lq32f_x_encode_fns, 0, 0 }, - { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, - 0, - Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, - { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, - 0, - Opcode_ae_sq56s_i_encode_fns, 0, 0 }, - { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, - 0, - Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, - { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, - 0, - Opcode_ae_sq56s_x_encode_fns, 0, 0 }, - { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, - 0, - Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, - { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, - 0, - Opcode_ae_sq32f_i_encode_fns, 0, 0 }, - { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, - 0, - Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, - { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, - 0, - Opcode_ae_sq32f_x_encode_fns, 0, 0 }, - { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, - 0, - Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, - { "ae_zerop48", ICLASS_ae_iclass_zerop48, - 0, - Opcode_ae_zerop48_encode_fns, 0, 0 }, - { "ae_movp48", ICLASS_ae_iclass_movp48, - 0, - Opcode_ae_movp48_encode_fns, 0, 0 }, - { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll, - 0, - Opcode_ae_selp24_ll_encode_fns, 0, 0 }, - { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh, - 0, - Opcode_ae_selp24_lh_encode_fns, 0, 0 }, - { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl, - 0, - Opcode_ae_selp24_hl_encode_fns, 0, 0 }, - { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh, - 0, - Opcode_ae_selp24_hh_encode_fns, 0, 0 }, - { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2, - 0, - Opcode_ae_movtp24x2_encode_fns, 0, 0 }, - { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2, - 0, - Opcode_ae_movfp24x2_encode_fns, 0, 0 }, - { "ae_movtp48", ICLASS_ae_iclass_movtp48, - 0, - Opcode_ae_movtp48_encode_fns, 0, 0 }, - { "ae_movfp48", ICLASS_ae_iclass_movfp48, - 0, - Opcode_ae_movfp48_encode_fns, 0, 0 }, - { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2, - 0, - Opcode_ae_movpa24x2_encode_fns, 0, 0 }, - { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2, - 0, - Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, - { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l, - 0, - Opcode_ae_cvta32p24_l_encode_fns, 0, 0 }, - { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h, - 0, - Opcode_ae_cvta32p24_h_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll, - 0, - Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh, - 0, - Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl, - 0, - Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh, - 0, - Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, - { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2, - 0, - Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, - { "ae_truncp16", ICLASS_ae_iclass_truncp16, - 0, - Opcode_ae_truncp16_encode_fns, 0, 0 }, - { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym, - 0, - Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 }, - { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym, - 0, - Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 }, - { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym, - 0, - Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 }, - { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym, - 0, - Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 }, - { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym, - 0, - Opcode_ae_roundsp16sym_encode_fns, 0, 0 }, - { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym, - 0, - Opcode_ae_roundsp16asym_encode_fns, 0, 0 }, - { "ae_zeroq56", ICLASS_ae_iclass_zeroq56, - 0, - Opcode_ae_zeroq56_encode_fns, 0, 0 }, - { "ae_movq56", ICLASS_ae_iclass_movq56, - 0, - Opcode_ae_movq56_encode_fns, 0, 0 }, - { "ae_movtq56", ICLASS_ae_iclass_movtq56, - 0, - Opcode_ae_movtq56_encode_fns, 0, 0 }, - { "ae_movfq56", ICLASS_ae_iclass_movfq56, - 0, - Opcode_ae_movfq56_encode_fns, 0, 0 }, - { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s, - 0, - Opcode_ae_cvtq48a32s_encode_fns, 0, 0 }, - { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l, - 0, - Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 }, - { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h, - 0, - Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 }, - { "ae_satq48s", ICLASS_ae_iclass_satq48s, - 0, - Opcode_ae_satq48s_encode_fns, 0, 0 }, - { "ae_truncq32", ICLASS_ae_iclass_truncq32, - 0, - Opcode_ae_truncq32_encode_fns, 0, 0 }, - { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym, - 0, - Opcode_ae_roundsq32sym_encode_fns, 0, 0 }, - { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym, - 0, - Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, - { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, - 0, - Opcode_ae_trunca32q48_encode_fns, 0, 0 }, - { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, - 0, - Opcode_ae_movap24s_l_encode_fns, 0, 0 }, - { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, - 0, - Opcode_ae_movap24s_h_encode_fns, 0, 0 }, - { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, - 0, - Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, - { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, - 0, - Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, - { "ae_addp24", ICLASS_ae_iclass_addp24, - 0, - Opcode_ae_addp24_encode_fns, 0, 0 }, - { "ae_subp24", ICLASS_ae_iclass_subp24, - 0, - Opcode_ae_subp24_encode_fns, 0, 0 }, - { "ae_negp24", ICLASS_ae_iclass_negp24, - 0, - Opcode_ae_negp24_encode_fns, 0, 0 }, - { "ae_absp24", ICLASS_ae_iclass_absp24, - 0, - Opcode_ae_absp24_encode_fns, 0, 0 }, - { "ae_maxp24s", ICLASS_ae_iclass_maxp24s, - 0, - Opcode_ae_maxp24s_encode_fns, 0, 0 }, - { "ae_minp24s", ICLASS_ae_iclass_minp24s, - 0, - Opcode_ae_minp24s_encode_fns, 0, 0 }, - { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s, - 0, - Opcode_ae_maxbp24s_encode_fns, 0, 0 }, - { "ae_minbp24s", ICLASS_ae_iclass_minbp24s, - 0, - Opcode_ae_minbp24s_encode_fns, 0, 0 }, - { "ae_addsp24s", ICLASS_ae_iclass_addsp24s, - 0, - Opcode_ae_addsp24s_encode_fns, 0, 0 }, - { "ae_subsp24s", ICLASS_ae_iclass_subsp24s, - 0, - Opcode_ae_subsp24s_encode_fns, 0, 0 }, - { "ae_negsp24s", ICLASS_ae_iclass_negsp24s, - 0, - Opcode_ae_negsp24s_encode_fns, 0, 0 }, - { "ae_abssp24s", ICLASS_ae_iclass_abssp24s, - 0, - Opcode_ae_abssp24s_encode_fns, 0, 0 }, - { "ae_andp48", ICLASS_ae_iclass_andp48, - 0, - Opcode_ae_andp48_encode_fns, 0, 0 }, - { "ae_nandp48", ICLASS_ae_iclass_nandp48, - 0, - Opcode_ae_nandp48_encode_fns, 0, 0 }, - { "ae_orp48", ICLASS_ae_iclass_orp48, - 0, - Opcode_ae_orp48_encode_fns, 0, 0 }, - { "ae_xorp48", ICLASS_ae_iclass_xorp48, - 0, - Opcode_ae_xorp48_encode_fns, 0, 0 }, - { "ae_ltp24s", ICLASS_ae_iclass_ltp24s, - 0, - Opcode_ae_ltp24s_encode_fns, 0, 0 }, - { "ae_lep24s", ICLASS_ae_iclass_lep24s, - 0, - Opcode_ae_lep24s_encode_fns, 0, 0 }, - { "ae_eqp24", ICLASS_ae_iclass_eqp24, - 0, - Opcode_ae_eqp24_encode_fns, 0, 0 }, - { "ae_addq56", ICLASS_ae_iclass_addq56, - 0, - Opcode_ae_addq56_encode_fns, 0, 0 }, - { "ae_subq56", ICLASS_ae_iclass_subq56, - 0, - Opcode_ae_subq56_encode_fns, 0, 0 }, - { "ae_negq56", ICLASS_ae_iclass_negq56, - 0, - Opcode_ae_negq56_encode_fns, 0, 0 }, - { "ae_absq56", ICLASS_ae_iclass_absq56, - 0, - Opcode_ae_absq56_encode_fns, 0, 0 }, - { "ae_maxq56s", ICLASS_ae_iclass_maxq56s, - 0, - Opcode_ae_maxq56s_encode_fns, 0, 0 }, - { "ae_minq56s", ICLASS_ae_iclass_minq56s, - 0, - Opcode_ae_minq56s_encode_fns, 0, 0 }, - { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s, - 0, - Opcode_ae_maxbq56s_encode_fns, 0, 0 }, - { "ae_minbq56s", ICLASS_ae_iclass_minbq56s, - 0, - Opcode_ae_minbq56s_encode_fns, 0, 0 }, - { "ae_addsq56s", ICLASS_ae_iclass_addsq56s, - 0, - Opcode_ae_addsq56s_encode_fns, 0, 0 }, - { "ae_subsq56s", ICLASS_ae_iclass_subsq56s, - 0, - Opcode_ae_subsq56s_encode_fns, 0, 0 }, - { "ae_negsq56s", ICLASS_ae_iclass_negsq56s, - 0, - Opcode_ae_negsq56s_encode_fns, 0, 0 }, - { "ae_abssq56s", ICLASS_ae_iclass_abssq56s, - 0, - Opcode_ae_abssq56s_encode_fns, 0, 0 }, - { "ae_andq56", ICLASS_ae_iclass_andq56, - 0, - Opcode_ae_andq56_encode_fns, 0, 0 }, - { "ae_nandq56", ICLASS_ae_iclass_nandq56, - 0, - Opcode_ae_nandq56_encode_fns, 0, 0 }, - { "ae_orq56", ICLASS_ae_iclass_orq56, - 0, - Opcode_ae_orq56_encode_fns, 0, 0 }, - { "ae_xorq56", ICLASS_ae_iclass_xorq56, - 0, - Opcode_ae_xorq56_encode_fns, 0, 0 }, - { "ae_sllip24", ICLASS_ae_iclass_sllip24, - 0, - Opcode_ae_sllip24_encode_fns, 0, 0 }, - { "ae_srlip24", ICLASS_ae_iclass_srlip24, - 0, - Opcode_ae_srlip24_encode_fns, 0, 0 }, - { "ae_sraip24", ICLASS_ae_iclass_sraip24, - 0, - Opcode_ae_sraip24_encode_fns, 0, 0 }, - { "ae_sllsp24", ICLASS_ae_iclass_sllsp24, - 0, - Opcode_ae_sllsp24_encode_fns, 0, 0 }, - { "ae_srlsp24", ICLASS_ae_iclass_srlsp24, - 0, - Opcode_ae_srlsp24_encode_fns, 0, 0 }, - { "ae_srasp24", ICLASS_ae_iclass_srasp24, - 0, - Opcode_ae_srasp24_encode_fns, 0, 0 }, - { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s, - 0, - Opcode_ae_sllisp24s_encode_fns, 0, 0 }, - { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s, - 0, - Opcode_ae_sllssp24s_encode_fns, 0, 0 }, - { "ae_slliq56", ICLASS_ae_iclass_slliq56, - 0, - Opcode_ae_slliq56_encode_fns, 0, 0 }, - { "ae_srliq56", ICLASS_ae_iclass_srliq56, - 0, - Opcode_ae_srliq56_encode_fns, 0, 0 }, - { "ae_sraiq56", ICLASS_ae_iclass_sraiq56, - 0, - Opcode_ae_sraiq56_encode_fns, 0, 0 }, - { "ae_sllsq56", ICLASS_ae_iclass_sllsq56, - 0, - Opcode_ae_sllsq56_encode_fns, 0, 0 }, - { "ae_srlsq56", ICLASS_ae_iclass_srlsq56, - 0, - Opcode_ae_srlsq56_encode_fns, 0, 0 }, - { "ae_srasq56", ICLASS_ae_iclass_srasq56, - 0, - Opcode_ae_srasq56_encode_fns, 0, 0 }, - { "ae_sllaq56", ICLASS_ae_iclass_sllaq56, - 0, - Opcode_ae_sllaq56_encode_fns, 0, 0 }, - { "ae_srlaq56", ICLASS_ae_iclass_srlaq56, - 0, - Opcode_ae_srlaq56_encode_fns, 0, 0 }, - { "ae_sraaq56", ICLASS_ae_iclass_sraaq56, - 0, - Opcode_ae_sraaq56_encode_fns, 0, 0 }, - { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s, - 0, - Opcode_ae_sllisq56s_encode_fns, 0, 0 }, - { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s, - 0, - Opcode_ae_sllssq56s_encode_fns, 0, 0 }, - { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s, - 0, - Opcode_ae_sllasq56s_encode_fns, 0, 0 }, - { "ae_ltq56s", ICLASS_ae_iclass_ltq56s, - 0, - Opcode_ae_ltq56s_encode_fns, 0, 0 }, - { "ae_leq56s", ICLASS_ae_iclass_leq56s, - 0, - Opcode_ae_leq56s_encode_fns, 0, 0 }, - { "ae_eqq56", ICLASS_ae_iclass_eqq56, - 0, - Opcode_ae_eqq56_encode_fns, 0, 0 }, - { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s, - 0, - Opcode_ae_nsaq56s_encode_fns, 0, 0 }, - { "ae_mulsrfq32sp24s.h", ICLASS_ae_iclass_mulsrfq32sp24s_h, - 0, - Opcode_ae_mulsrfq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mulsrfq32sp24s.l", ICLASS_ae_iclass_mulsrfq32sp24s_l, - 0, - Opcode_ae_mulsrfq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mularfq32sp24s.h", ICLASS_ae_iclass_mularfq32sp24s_h, - 0, - Opcode_ae_mularfq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mularfq32sp24s.l", ICLASS_ae_iclass_mularfq32sp24s_l, - 0, - Opcode_ae_mularfq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mulrfq32sp24s.h", ICLASS_ae_iclass_mulrfq32sp24s_h, - 0, - Opcode_ae_mulrfq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mulrfq32sp24s.l", ICLASS_ae_iclass_mulrfq32sp24s_l, - 0, - Opcode_ae_mulrfq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mulsfq32sp24s.h", ICLASS_ae_iclass_mulsfq32sp24s_h, - 0, - Opcode_ae_mulsfq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mulsfq32sp24s.l", ICLASS_ae_iclass_mulsfq32sp24s_l, - 0, - Opcode_ae_mulsfq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mulafq32sp24s.h", ICLASS_ae_iclass_mulafq32sp24s_h, - 0, - Opcode_ae_mulafq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mulafq32sp24s.l", ICLASS_ae_iclass_mulafq32sp24s_l, - 0, - Opcode_ae_mulafq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mulfq32sp24s.h", ICLASS_ae_iclass_mulfq32sp24s_h, - 0, - Opcode_ae_mulfq32sp24s_h_encode_fns, 0, 0 }, - { "ae_mulfq32sp24s.l", ICLASS_ae_iclass_mulfq32sp24s_l, - 0, - Opcode_ae_mulfq32sp24s_l_encode_fns, 0, 0 }, - { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll, - 0, - Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 }, - { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll, - 0, - Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 }, - { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll, - 0, - Opcode_ae_mulp24s_ll_encode_fns, 0, 0 }, - { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh, - 0, - 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Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, - 0, - Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, - 0, - Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, - 0, - Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, - 0, - Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, - 0, - Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, - 0, - Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, - 0, - Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, - 0, - Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, - 0, - Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, - 0, - Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, - 0, - Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, - 0, - Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, - { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, - 0, - Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, - 0, - Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, - 0, - Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, - 0, - Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, - 0, - Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, - 0, - Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, - 0, - Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, - 0, - Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, - 0, - Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, - 0, - Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, - 0, - Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, - 0, - Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, - 0, - Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, - 0, - Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, - 0, - Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, - 0, - Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, - 0, - Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, - 0, - Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, - 0, - Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, - 0, - Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, - 0, - Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, - 0, - Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, - 0, - Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, - 0, - Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, - 0, - Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, - 0, - Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, - 0, - Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, - 0, - Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, - 0, - Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, - 0, - Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, - 0, - Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, - 0, - Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, - 0, - Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, - 0, - Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_sha32", ICLASS_ae_iclass_sha32, - 0, - Opcode_ae_sha32_encode_fns, 0, 0 }, - { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, - 0, - Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, - { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, - 0, - Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, - { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, - 0, - Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, - { "ae_vldsht", ICLASS_ae_iclass_vldsht, - 0, - Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, - { "ae_lb", ICLASS_ae_iclass_lb, - 0, - Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, - { "ae_lbi", ICLASS_ae_iclass_lbi, - 0, - Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, - { "ae_lbk", ICLASS_ae_iclass_lbk, - 0, - Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, - { "ae_lbki", ICLASS_ae_iclass_lbki, - 0, - Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, - { "ae_db", ICLASS_ae_iclass_db, - 0, - Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, - { "ae_dbi", ICLASS_ae_iclass_dbi, - 0, - Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, - { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, - 0, - Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, - { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, - 0, - Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, - { "ae_sb", ICLASS_ae_iclass_sb, - 0, - Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, - { "ae_sbi", ICLASS_ae_iclass_sbi, - 0, - Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, - { "ae_vles16c", ICLASS_ae_iclass_vles16c, - 0, - Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, - { "ae_sbf", ICLASS_ae_iclass_sbf, - 0, - Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, - { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, - 0, - Opcode_ae_slaasq56s_encode_fns, 0, 0 }, - { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, - 0, - Opcode_ae_addbrba32_encode_fns, 0, 0 }, - { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, - 0, - Opcode_ae_minabssp24s_encode_fns, 0, 0 }, - { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, - 0, - Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, - { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, - 0, - Opcode_ae_minabssq56s_encode_fns, 0, 0 }, - { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, - 0, - Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, - { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, - 0, - Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, - { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, - 0, - Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, - { "rur.ae_cend0", ICLASS_rur_ae_cend0, - 0, - Opcode_rur_ae_cend0_encode_fns, 0, 0 }, - { "wur.ae_cend0", ICLASS_wur_ae_cend0, - 0, - Opcode_wur_ae_cend0_encode_fns, 0, 0 }, - { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, - 0, - Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, - { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, - 0, - Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, - { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, - 0, - Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, - { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, - 0, - Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, - { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, - 0, - Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, - { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, - 0, - Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, - { "ae_lp24.c", ICLASS_icls_AE_LP24_C, - 0, - Opcode_ae_lp24_c_encode_fns, 0, 0 }, - { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, - 0, - Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, - { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, - 0, - Opcode_ae_lp24f_c_encode_fns, 0, 0 }, - { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, - 0, - Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, - { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, - 0, - Opcode_ae_lp16f_c_encode_fns, 0, 0 }, - { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, - 0, - Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, - { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, - 0, - Opcode_ae_lq56_c_encode_fns, 0, 0 }, - { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, - 0, - Opcode_ae_sq56s_c_encode_fns, 0, 0 }, - { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, - 0, - Opcode_ae_lq32f_c_encode_fns, 0, 0 }, - { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, - 0, - Opcode_ae_sq32f_c_encode_fns, 0, 0 }, - { "rur.expstate", ICLASS_rur_expstate, - 0, - Opcode_rur_expstate_encode_fns, 0, 0 }, - { "wur.expstate", ICLASS_wur_expstate, - 0, - Opcode_wur_expstate_encode_fns, 0, 0 }, - { "read_impwire", ICLASS_iclass_READ_IMPWIRE, - 0, - Opcode_read_impwire_encode_fns, 0, 0 }, - { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, - 0, - Opcode_setb_expstate_encode_fns, 0, 0 }, - { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, - 0, - Opcode_clrb_expstate_encode_fns, 0, 0 }, - { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, - 0, - Opcode_wrmsk_expstate_encode_fns, 0, 0 } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S32NB, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_MEMCTL, - OPCODE_WSR_MEMCTL, - OPCODE_XSR_MEMCTL, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_243, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPC3, - OPCODE_WSR_EPC3, - OPCODE_XSR_EPC3, - OPCODE_RSR_EXCSAVE3, - OPCODE_WSR_EXCSAVE3, - OPCODE_XSR_EXCSAVE3, - OPCODE_RSR_EPC4, - OPCODE_WSR_EPC4, - OPCODE_XSR_EPC4, - OPCODE_RSR_EXCSAVE4, - OPCODE_WSR_EXCSAVE4, - OPCODE_XSR_EXCSAVE4, - OPCODE_RSR_EPC5, - OPCODE_WSR_EPC5, - OPCODE_XSR_EPC5, - OPCODE_RSR_EXCSAVE5, - OPCODE_WSR_EXCSAVE5, - OPCODE_XSR_EXCSAVE5, - OPCODE_RSR_EPC6, - OPCODE_WSR_EPC6, - OPCODE_XSR_EPC6, - OPCODE_RSR_EXCSAVE6, - OPCODE_WSR_EXCSAVE6, - OPCODE_XSR_EXCSAVE6, - OPCODE_RSR_EPC7, - OPCODE_WSR_EPC7, - OPCODE_XSR_EPC7, - OPCODE_RSR_EXCSAVE7, - OPCODE_WSR_EXCSAVE7, - OPCODE_XSR_EXCSAVE7, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EPS3, - OPCODE_WSR_EPS3, - OPCODE_XSR_EPS3, - OPCODE_RSR_EPS4, - OPCODE_WSR_EPS4, - OPCODE_XSR_EPS4, - OPCODE_RSR_EPS5, - OPCODE_WSR_EPS5, - OPCODE_XSR_EPS5, - OPCODE_RSR_EPS6, - OPCODE_WSR_EPS6, - OPCODE_XSR_EPS6, - OPCODE_RSR_EPS7, - OPCODE_WSR_EPS7, - OPCODE_XSR_EPS7, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_MULUH, - OPCODE_MULSH, - OPCODE_MUL_AA_LL, - OPCODE_MUL_AA_HL, - OPCODE_MUL_AA_LH, - OPCODE_MUL_AA_HH, - OPCODE_UMUL_AA_LL, - OPCODE_UMUL_AA_HL, - OPCODE_UMUL_AA_LH, - OPCODE_UMUL_AA_HH, - OPCODE_MUL_AD_LL, - OPCODE_MUL_AD_HL, - OPCODE_MUL_AD_LH, - OPCODE_MUL_AD_HH, - OPCODE_MUL_DA_LL, - OPCODE_MUL_DA_HL, - OPCODE_MUL_DA_LH, - OPCODE_MUL_DA_HH, - OPCODE_MUL_DD_LL, - OPCODE_MUL_DD_HL, - OPCODE_MUL_DD_LH, - OPCODE_MUL_DD_HH, - OPCODE_MULA_AA_LL, - OPCODE_MULA_AA_HL, - OPCODE_MULA_AA_LH, - OPCODE_MULA_AA_HH, - OPCODE_MULS_AA_LL, - OPCODE_MULS_AA_HL, - OPCODE_MULS_AA_LH, - OPCODE_MULS_AA_HH, - OPCODE_MULA_AD_LL, - OPCODE_MULA_AD_HL, - OPCODE_MULA_AD_LH, - OPCODE_MULA_AD_HH, - OPCODE_MULS_AD_LL, - OPCODE_MULS_AD_HL, - OPCODE_MULS_AD_LH, - OPCODE_MULS_AD_HH, - OPCODE_MULA_DA_LL, - OPCODE_MULA_DA_HL, - OPCODE_MULA_DA_LH, - OPCODE_MULA_DA_HH, - OPCODE_MULS_DA_LL, - OPCODE_MULS_DA_HL, - OPCODE_MULS_DA_LH, - OPCODE_MULS_DA_HH, - OPCODE_MULA_DD_LL, - OPCODE_MULA_DD_HL, - OPCODE_MULA_DD_LH, - OPCODE_MULA_DD_HH, - OPCODE_MULS_DD_LL, - OPCODE_MULS_DD_HL, - OPCODE_MULS_DD_LH, - OPCODE_MULS_DD_HH, - OPCODE_MULA_DA_LL_LDDEC, - OPCODE_MULA_DA_LL_LDINC, - OPCODE_MULA_DA_HL_LDDEC, - OPCODE_MULA_DA_HL_LDINC, - OPCODE_MULA_DA_LH_LDDEC, - OPCODE_MULA_DA_LH_LDINC, - OPCODE_MULA_DA_HH_LDDEC, - OPCODE_MULA_DA_HH_LDINC, - OPCODE_MULA_DD_LL_LDDEC, - OPCODE_MULA_DD_LL_LDINC, - OPCODE_MULA_DD_HL_LDDEC, - OPCODE_MULA_DD_HL_LDINC, - OPCODE_MULA_DD_LH_LDDEC, - OPCODE_MULA_DD_LH_LDINC, - OPCODE_MULA_DD_HH_LDDEC, - OPCODE_MULA_DD_HH_LDINC, - OPCODE_LDDEC, - OPCODE_LDINC, - OPCODE_RSR_M0, - OPCODE_WSR_M0, - OPCODE_XSR_M0, - OPCODE_RSR_M1, - OPCODE_WSR_M1, - OPCODE_XSR_M1, - OPCODE_RSR_M2, - OPCODE_WSR_M2, - OPCODE_XSR_M2, - OPCODE_RSR_M3, - OPCODE_WSR_M3, - OPCODE_XSR_M3, - OPCODE_RSR_ACCLO, - OPCODE_WSR_ACCLO, - OPCODE_XSR_ACCLO, - OPCODE_RSR_ACCHI, - OPCODE_WSR_ACCHI, - OPCODE_XSR_ACCHI, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DBREAKA0, - OPCODE_WSR_DBREAKA0, - OPCODE_XSR_DBREAKA0, - OPCODE_RSR_DBREAKC0, - OPCODE_WSR_DBREAKC0, - OPCODE_XSR_DBREAKC0, - OPCODE_RSR_DBREAKA1, - OPCODE_WSR_DBREAKA1, - OPCODE_XSR_DBREAKA1, - OPCODE_RSR_DBREAKC1, - OPCODE_WSR_DBREAKC1, - OPCODE_XSR_DBREAKC1, - OPCODE_RSR_IBREAKA0, - OPCODE_WSR_IBREAKA0, - OPCODE_XSR_IBREAKA0, - OPCODE_RSR_IBREAKA1, - OPCODE_WSR_IBREAKA1, - OPCODE_XSR_IBREAKA1, - OPCODE_RSR_IBREAKENABLE, - OPCODE_WSR_IBREAKENABLE, - OPCODE_XSR_IBREAKENABLE, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_LDDR32_P, - OPCODE_SDDR32_P, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_WSR_MMID, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_RSR_CCOMPARE2, - OPCODE_WSR_CCOMPARE2, - OPCODE_XSR_CCOMPARE2, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_IPFL, - OPCODE_IHU, - OPCODE_IIU, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWBUI_P, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_DPFL, - OPCODE_DHU, - OPCODE_DIU, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_RSR_PREFCTL, - OPCODE_WSR_PREFCTL, - OPCODE_XSR_PREFCTL, - OPCODE_WSR_PTEVADDR, - OPCODE_RSR_PTEVADDR, - OPCODE_XSR_PTEVADDR, - OPCODE_RSR_RASID, - OPCODE_WSR_RASID, - OPCODE_XSR_RASID, - OPCODE_RSR_ITLBCFG, - OPCODE_WSR_ITLBCFG, - OPCODE_XSR_ITLBCFG, - OPCODE_RSR_DTLBCFG, - OPCODE_WSR_DTLBCFG, - OPCODE_XSR_DTLBCFG, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_LDPTE, - OPCODE_HWWITLBA, - OPCODE_HWWDTLBA, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_QUOU, - OPCODE_QUOS, - OPCODE_REMU, - OPCODE_REMS, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULSRFQ32SP24S_H, - OPCODE_AE_MULSRFQ32SP24S_L, - OPCODE_AE_MULARFQ32SP24S_H, - OPCODE_AE_MULARFQ32SP24S_L, - OPCODE_AE_MULRFQ32SP24S_H, - OPCODE_AE_MULRFQ32SP24S_L, - OPCODE_AE_MULSFQ32SP24S_H, - OPCODE_AE_MULSFQ32SP24S_L, - OPCODE_AE_MULAFQ32SP24S_H, - OPCODE_AE_MULAFQ32SP24S_L, - OPCODE_AE_MULFQ32SP24S_H, - OPCODE_AE_MULFQ32SP24S_L, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF, - OPCODE_AE_SLAASQ56S, - OPCODE_AE_ADDBRBA32, - OPCODE_AE_MINABSSP24S, - OPCODE_AE_MAXABSSP24S, - OPCODE_AE_MINABSSQ56S, - OPCODE_AE_MAXABSSQ56S, - OPCODE_RUR_AE_CBEGIN0, - OPCODE_WUR_AE_CBEGIN0, - OPCODE_RUR_AE_CEND0, - OPCODE_WUR_AE_CEND0, - OPCODE_AE_LP24X2_C, - OPCODE_AE_SP24X2S_C, - OPCODE_AE_LP24X2F_C, - OPCODE_AE_SP24X2F_C, - OPCODE_AE_LP16X2F_C, - OPCODE_AE_SP16X2F_C, - OPCODE_AE_LP24_C, - OPCODE_AE_SP24S_L_C, - OPCODE_AE_LP24F_C, - OPCODE_AE_SP24F_L_C, - OPCODE_AE_LP16F_C, - OPCODE_AE_SP16F_L_C, - OPCODE_AE_LQ56_C, - OPCODE_AE_SQ56S_C, - OPCODE_AE_LQ32F_C, - OPCODE_AE_SQ32F_C, - OPCODE_RUR_EXPSTATE, - OPCODE_WUR_EXPSTATE, - OPCODE_READ_IMPWIRE, - OPCODE_SETB_EXPSTATE, - OPCODE_CLRB_EXPSTATE, - OPCODE_WRMSK_EXPSTATE -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_LDDR32_P; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_SDDR32_P; - } - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_HWWITLBA; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_HWWDTLBA; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_XSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_XSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_XSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_XSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_XSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_XSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_XSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_XSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_XSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_XSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_XSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_XSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_XSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_XSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_XSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_XSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_XSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_XSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_XSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_XSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_XSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_XSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_XSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_XSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_XSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_XSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_XSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_XSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_XSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_XSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_XSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_XSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_XSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_XSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_XSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_LDPTE; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MULUH; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MULSH; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_QUOU; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_QUOS; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_REMU; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_REMS; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_RSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_RSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_RSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_RSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_RSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_RSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_RSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_RSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_RSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_RSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_RSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_RSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_RSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_RSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_RSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_RSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_RSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_RSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_RSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_RSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_RSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_RSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_RSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_RSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_RSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_RSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_RSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_RSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_RSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_RSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_RSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_RSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_RSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_RSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_RSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_RSR_243; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 16) - return OPCODE_WSR_ACCLO; - if (Field_sr_Slot_inst_get (insn) == 17) - return OPCODE_WSR_ACCHI; - if (Field_sr_Slot_inst_get (insn) == 32) - return OPCODE_WSR_M0; - if (Field_sr_Slot_inst_get (insn) == 33) - return OPCODE_WSR_M1; - if (Field_sr_Slot_inst_get (insn) == 34) - return OPCODE_WSR_M2; - if (Field_sr_Slot_inst_get (insn) == 35) - return OPCODE_WSR_M3; - if (Field_sr_Slot_inst_get (insn) == 40) - return OPCODE_WSR_PREFCTL; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_WSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 89) - return OPCODE_WSR_MMID; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_WSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_WSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_WSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 96) - return OPCODE_WSR_IBREAKENABLE; - if (Field_sr_Slot_inst_get (insn) == 97) - return OPCODE_WSR_MEMCTL; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 128) - return OPCODE_WSR_IBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 129) - return OPCODE_WSR_IBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 144) - return OPCODE_WSR_DBREAKA0; - if (Field_sr_Slot_inst_get (insn) == 145) - return OPCODE_WSR_DBREAKA1; - if (Field_sr_Slot_inst_get (insn) == 160) - return OPCODE_WSR_DBREAKC0; - if (Field_sr_Slot_inst_get (insn) == 161) - return OPCODE_WSR_DBREAKC1; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 179) - return OPCODE_WSR_EPC3; - if (Field_sr_Slot_inst_get (insn) == 180) - return OPCODE_WSR_EPC4; - if (Field_sr_Slot_inst_get (insn) == 181) - return OPCODE_WSR_EPC5; - if (Field_sr_Slot_inst_get (insn) == 182) - return OPCODE_WSR_EPC6; - if (Field_sr_Slot_inst_get (insn) == 183) - return OPCODE_WSR_EPC7; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 195) - return OPCODE_WSR_EPS3; - if (Field_sr_Slot_inst_get (insn) == 196) - return OPCODE_WSR_EPS4; - if (Field_sr_Slot_inst_get (insn) == 197) - return OPCODE_WSR_EPS5; - if (Field_sr_Slot_inst_get (insn) == 198) - return OPCODE_WSR_EPS6; - if (Field_sr_Slot_inst_get (insn) == 199) - return OPCODE_WSR_EPS7; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 211) - return OPCODE_WSR_EXCSAVE3; - if (Field_sr_Slot_inst_get (insn) == 212) - return OPCODE_WSR_EXCSAVE4; - if (Field_sr_Slot_inst_get (insn) == 213) - return OPCODE_WSR_EXCSAVE5; - if (Field_sr_Slot_inst_get (insn) == 214) - return OPCODE_WSR_EXCSAVE6; - if (Field_sr_Slot_inst_get (insn) == 215) - return OPCODE_WSR_EXCSAVE7; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WSR_CCOMPARE2; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 230) - return OPCODE_RUR_EXPSTATE; - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - if (Field_st_Slot_inst_get (insn) == 246) - return OPCODE_RUR_AE_CBEGIN0; - if (Field_st_Slot_inst_get (insn) == 247) - return OPCODE_RUR_AE_CEND0; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WUR_EXPSTATE; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - if (Field_sr_Slot_inst_get (insn) == 246) - return OPCODE_WUR_AE_CBEGIN0; - if (Field_sr_Slot_inst_get (insn) == 247) - return OPCODE_WUR_AE_CEND0; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_S32NB; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_READ_IMPWIRE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_SETB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s3to1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_CLRB_EXPSTATE; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14) - return OPCODE_WRMSK_EXPSTATE; - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_DPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_DHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_DIU; - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_DIWBUI_P; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 13) - { - if (Field_op1_Slot_inst_get (insn) == 0) - return OPCODE_IPFL; - if (Field_op1_Slot_inst_get (insn) == 2) - return OPCODE_IHU; - if (Field_op1_Slot_inst_get (insn) == 3) - return OPCODE_IIU; - } - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 2) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 3) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AD_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0 && - Field_t3_Slot_inst_get (insn) == 0 && - Field_tlo_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AD_HH; - } - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDINC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDINC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH_LDDEC; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH_LDDEC; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MUL_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULA_DA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_s_Slot_inst_get (insn) == 0 && - Field_w_Slot_inst_get (insn) == 0 && - Field_r3_Slot_inst_get (insn) == 0) - return OPCODE_MULS_DA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 7) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_UMUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MUL_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULA_AA_HH; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LL; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HL; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_r_Slot_inst_get (insn) == 0) - return OPCODE_MULS_AA_HH; - } - if (Field_op2_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDINC; - } - if (Field_op2_Slot_inst_get (insn) == 9) - { - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_rhi_Slot_inst_get (insn) == 0) - return OPCODE_LDDEC; - } - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return XTENSA_UNDEFINED; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_s20_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf378ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_HH; - if (Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_HL; - if (Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LH; - if (Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_ftsf315_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 2 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLAASQ56S; - if (Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_C; - if (Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_C; - if (Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_C; - if (Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_C; - if (Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_C; - if (Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_C; - if (Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_C; - if (Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_C; - if (Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_C; - if (Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_C; - if (Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_C; - if (Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_C; - if (Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_C; - if (Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ56S_C; - if (Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && - Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf211ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 43 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217ae_slot0_Slot_ae_slot0_get (insn) == 299 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 46 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 47 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 302 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 303 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 58 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 59 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 62 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 63 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 314 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 315 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 318 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 319 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 170 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 171 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 174 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 175 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 75 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 331 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 78 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 79 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 334 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 335 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 90 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 91 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 94 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 95 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 346 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 347 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 350 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 351 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 106 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 107 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 110 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 111 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 122 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 126 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 127 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 362 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 363 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 875 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_XU; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 366 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 367 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 878 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 879 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 378 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_X; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 379 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 890 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 891 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 2938 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_JX; - if (Field_ftsf280_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf280_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 2939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSR; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 1981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 957 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf285ae_slot0_Slot_ae_slot0_get (insn) == 957 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf287ae_slot0_Slot_ae_slot0_get (insn) == 957 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf288_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf289ae_slot0_Slot_ae_slot0_get (insn) == 382 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 383 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf291ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf382ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf293ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf384ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf383ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 4298 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf315_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 4554 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ALL4; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 12746 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf309_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 2506 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf373ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 1482 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf370ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 970 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf376ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf305ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 715 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf307ae_slot0_Slot_ae_slot0_get (insn) == 971 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf309_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_C; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 231 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf386ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 219 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 222 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 475 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 731 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 987 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 2011 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 3035 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 4059 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 1502 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 1502 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf389ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf319ae_slot0_Slot_ae_slot0_get (insn) == 1502 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf388ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf387ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 223 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 479 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 735 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 991 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 735 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf327ae_slot0_Slot_ae_slot0_get (insn) == 991 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SLL; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 479 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf379ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ32F_XU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 23 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 26 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 27 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 30 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 39 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 42 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 55 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 71 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 74 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 87 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 103 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 119 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 139 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 142 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 143 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 151 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 154 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 155 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 158 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 159 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 167 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 215 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 218 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ32F_X; - if (Field_imm8_Slot_ae_slot0_get (insn) == 231 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 247 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_ADDBRBA32; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_s8_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ftsf280_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_s8_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf309_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_C; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return XTENSA_UNDEFINED; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 82 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 146 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 210 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_L; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 274 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 306 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 338 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSRFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 402 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULARFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 434 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP24S_H; - if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 466 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP24S_H; - if (Field_ae_r20_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ae_s20_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf340ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && - Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXABSSP24S; - if (Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && - Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINABSSP24S; - if (Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && - Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MINABSSQ56S; - if (Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && - Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && - Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXABSSQ56S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf335_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf102ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 131 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 259 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 323 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 387 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 451 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf117ae_slot1_Slot_ae_slot1_get (insn) == 515 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 2307 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 2315 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf121ae_slot1_Slot_ae_slot1_get (insn) == 1163 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf91_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf123ae_slot1_Slot_ae_slot1_get (insn) == 323 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf352ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf357ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf208ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf20ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 84 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 85 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 100 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 101 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 116 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 117 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ABSP24; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 88 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NEGP24; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 152 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 216 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf333ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 88 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf359ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 704 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 708 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 712 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 716 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 720 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 724 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 728 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 732 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf356ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LTP24S; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf355ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf61_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf62ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEP24S; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 101 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf345ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf70ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 103 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 135 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf74ae_slot1_Slot_ae_slot1_get (insn) == 167 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 199 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 231 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 263 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 295 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 327 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 359 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 391 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf83ae_slot1_Slot_ae_slot1_get (insn) == 455 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 487 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf85ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 107 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 139 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 331 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf55_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 363 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf358ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf93ae_slot1_Slot_ae_slot1_get (insn) == 203 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 1803 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 1835 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 939 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 491 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf351_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[1] & 0xffffff00) >> 8); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[1] = (insn[1] & ~0xffffff00) | ((slotbuf[0] & 0xffffff) << 8); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); -} - -static void -Slot_ae_format_Format_ae_slot1_10_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0xfffffc00) >> 10); - slotbuf[0] = (slotbuf[0] & ~0x400000) | ((insn[1] & 0x1) << 22); -} - -static void -Slot_ae_format_Format_ae_slot1_10_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xfffffc00) | ((slotbuf[0] & 0x3fffff) << 10); - insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x400000) >> 22); -} - -static void -Slot_ae_format_Format_ae_slot0_33_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[1] & 0xffffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_33_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[1] = (insn[1] & ~0xffffffe) | ((slotbuf[0] & 0x7ffffff) << 1); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_get, - Field_rbit2_Slot_inst_get, - Field_rhi_Slot_inst_get, - Field_t3_Slot_inst_get, - Field_tbit2_Slot_inst_get, - Field_tlo_Slot_inst_get, - Field_w_Slot_inst_get, - Field_y_Slot_inst_get, - Field_x_Slot_inst_get, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf11_Slot_inst_get, - Field_ftsf12_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_get, - Field_s3to1_Slot_inst_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_r3_Slot_inst_set, - Field_rbit2_Slot_inst_set, - Field_rhi_Slot_inst_set, - Field_t3_Slot_inst_set, - Field_tbit2_Slot_inst_set, - Field_tlo_Slot_inst_set, - Field_w_Slot_inst_set, - Field_y_Slot_inst_set, - Field_x_Slot_inst_set, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf11_Slot_inst_set, - Field_ftsf12_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst_set, - Field_s3to1_Slot_inst_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_get, - Field_s3to1_Slot_inst16a_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16a_set, - Field_s3to1_Slot_inst16a_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_get, - Field_s3to1_Slot_inst16b_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_inst16b_set, - Field_s3to1_Slot_inst16b_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf11_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf20ae_slot1_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61_Slot_ae_slot1_get, - Field_ftsf62ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf68ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf70ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf74ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf83ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf85ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf93ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf102ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf117ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf121ae_slot1_Slot_ae_slot1_get, - Field_ftsf123ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf333ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf335_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340ae_slot1_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf345ae_slot1_Slot_ae_slot1_get, - Field_ftsf347ae_slot1_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - Field_ftsf351_Slot_ae_slot1_get, - Field_ftsf352ae_slot1_Slot_ae_slot1_get, - Field_ftsf354ae_slot1_Slot_ae_slot1_get, - Field_ftsf355ae_slot1_Slot_ae_slot1_get, - Field_ftsf356ae_slot1_Slot_ae_slot1_get, - Field_ftsf357ae_slot1_Slot_ae_slot1_get, - Field_ftsf358ae_slot1_Slot_ae_slot1_get, - Field_ftsf359ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s3_s3_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld19_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld22_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld24_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld65_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld66_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld68_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld69_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld74_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld79_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld88_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld90_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld91_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get, - Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf11_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf20ae_slot1_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61_Slot_ae_slot1_set, - Field_ftsf62ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf68ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf70ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf74ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf83ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf85ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf93ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf102ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf117ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf121ae_slot1_Slot_ae_slot1_set, - Field_ftsf123ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf333ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf335_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340ae_slot1_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf345ae_slot1_Slot_ae_slot1_set, - Field_ftsf347ae_slot1_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - Field_ftsf351_Slot_ae_slot1_set, - Field_ftsf352ae_slot1_Slot_ae_slot1_set, - Field_ftsf354ae_slot1_Slot_ae_slot1_set, - Field_ftsf355ae_slot1_Slot_ae_slot1_set, - Field_ftsf356ae_slot1_Slot_ae_slot1_set, - Field_ftsf357ae_slot1_Slot_ae_slot1_set, - Field_ftsf358ae_slot1_Slot_ae_slot1_set, - Field_ftsf359ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_mul32x24fld_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s3_s3_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld19_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld22_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld24_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld65_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld66_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld68_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld69_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld74_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld79_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld88_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld90_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld91_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set, - Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - Field_ftsf11_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf211ae_slot0_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf217ae_slot0_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf280_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf285ae_slot0_Slot_ae_slot0_get, - Field_ftsf287ae_slot0_Slot_ae_slot0_get, - Field_ftsf288_Slot_ae_slot0_get, - Field_ftsf289ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf291ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293ae_slot0_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf305ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf307ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf319ae_slot0_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf327ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362_Slot_ae_slot0_get, - Field_ftsf363ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf370ae_slot0_Slot_ae_slot0_get, - Field_ftsf373ae_slot0_Slot_ae_slot0_get, - Field_ftsf376ae_slot0_Slot_ae_slot0_get, - Field_ftsf378ae_slot0_Slot_ae_slot0_get, - Field_ftsf379ae_slot0_Slot_ae_slot0_get, - Field_ftsf382ae_slot0_Slot_ae_slot0_get, - Field_ftsf383ae_slot0_Slot_ae_slot0_get, - Field_ftsf384ae_slot0_Slot_ae_slot0_get, - Field_ftsf386ae_slot0_Slot_ae_slot0_get, - Field_ftsf387ae_slot0_Slot_ae_slot0_get, - Field_ftsf388ae_slot0_Slot_ae_slot0_get, - Field_ftsf389ae_slot0_Slot_ae_slot0_get, - 0, - Field_op0_s4_s4_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld28_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld37_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld39_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld40_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld46_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld47_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld49_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld50_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld52_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld121_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld123_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld127_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get, - Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get, - Field_op0_s4_s4_s4_Slot_ae_slot0_get, - Field_combined1e9fefee_fld96_Slot_ae_slot0_get, - Field_combined1e9fefee_fld98_Slot_ae_slot0_get, - Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get, - Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get, - Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get, - Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_get, - Field_s3to1_Slot_ae_slot0_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_mr0_get, - Implicit_Field_mr1_get, - Implicit_Field_mr2_get, - Implicit_Field_mr3_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - Field_ftsf11_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf211ae_slot0_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf217ae_slot0_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf280_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf285ae_slot0_Slot_ae_slot0_set, - Field_ftsf287ae_slot0_Slot_ae_slot0_set, - Field_ftsf288_Slot_ae_slot0_set, - Field_ftsf289ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf291ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293ae_slot0_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf305ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf307ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf319ae_slot0_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf327ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362_Slot_ae_slot0_set, - Field_ftsf363ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf370ae_slot0_Slot_ae_slot0_set, - Field_ftsf373ae_slot0_Slot_ae_slot0_set, - Field_ftsf376ae_slot0_Slot_ae_slot0_set, - Field_ftsf378ae_slot0_Slot_ae_slot0_set, - Field_ftsf379ae_slot0_Slot_ae_slot0_set, - Field_ftsf382ae_slot0_Slot_ae_slot0_set, - Field_ftsf383ae_slot0_Slot_ae_slot0_set, - Field_ftsf384ae_slot0_Slot_ae_slot0_set, - Field_ftsf386ae_slot0_Slot_ae_slot0_set, - Field_ftsf387ae_slot0_Slot_ae_slot0_set, - Field_ftsf388ae_slot0_Slot_ae_slot0_set, - Field_ftsf389ae_slot0_Slot_ae_slot0_set, - 0, - Field_op0_s4_s4_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld28_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld37_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld39_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld40_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld46_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld47_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld49_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld50_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld52_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld121_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld123_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld127_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set, - Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set, - Field_op0_s4_s4_s4_Slot_ae_slot0_set, - Field_combined1e9fefee_fld96_Slot_ae_slot0_set, - Field_combined1e9fefee_fld98_Slot_ae_slot0_set, - Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set, - Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set, - Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set, - Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_bitindex_Slot_ae_slot0_set, - Field_s3to1_Slot_ae_slot0_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_10_get, Slot_ae_format_Format_ae_slot1_10_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_33_get, Slot_ae_format_Format_ae_slot0_33_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0x80000000; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0xc0000000; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0xf0000000; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 3, 4 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0) == 0 && (insn[1] & 0x80000000) == 0) - return 0; /* x24 */ - if ((insn[0] & 0) == 0 && (insn[1] & 0xc0000000) == 0x80000000) - return 1; /* x16a */ - if ((insn[0] & 0) == 0 && (insn[1] & 0xe0000000) == 0xc0000000) - return 2; /* x16b */ - if ((insn[0] & 0x3ff) == 0 && (insn[1] & 0xf0000000) == 0xf0000000) - return 3; /* ae_format */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 1 /* big-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 468 /* num_fields */, - 536, operands, - 746, iclasses, - 881, opcodes, 0, - 9, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 6, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c index 089ed7da5d..123c630b0d 100644 --- a/target/xtensa/core-test_mmuhifi_c3.c +++ b/target/xtensa/core-test_mmuhifi_c3.c @@ -35,13 +35,13 @@ #include "overlay_tool.h" #define xtensa_modules xtensa_modules_test_mmuhifi_c3 -#include "core-test_mmuhifi_c3/xtensa-modules.inc.c" +#include "core-test_mmuhifi_c3/xtensa-modules.c.inc" static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = { .name = "test_mmuhifi_c3", .gdb_regmap = { .reg = { -#include "core-test_mmuhifi_c3/gdb-config.inc.c" +#include "core-test_mmuhifi_c3/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc b/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc new file mode 100644 index 0000000000..0bca70b5af --- /dev/null +++ b/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc @@ -0,0 +1,220 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2019 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) + XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, + "03:04:84:b2","03:04:84:a7",0,0,0,0) + XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, + "03:04:94:b2","03:04:94:a7",0,0,0,0) + XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, + "03:04:a4:b2","03:04:a4:a7",0,0,0,0) + XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, + "03:04:b4:b2","03:04:b4:a7",0,0,0,0) + XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, + "03:04:c4:b2","03:04:c4:a7",0,0,0,0) + XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, + "03:04:d4:b2","03:04:d4:a7",0,0,0,0) + XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, + "03:04:e4:b2","03:04:e4:a7",0,0,0,0) + XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, + "03:04:f4:b2","03:04:f4:a7",0,0,0,0) + XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, + "03:04:04:c3","03:04:04:c1",0,0,0,0) + XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, + "03:04:14:c3","03:04:44:c1",0,0,0,0) + XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, + "03:04:24:c3","03:04:84:c1",0,0,0,0) + XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, + "03:04:34:c3","03:04:c4:c1",0,0,0,0) + XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) + XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) + XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) + XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) + XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) + XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask19,0,0,0) + XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask20,0,0,0) + XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask21,0,0,0) + XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask22,0,0,0) + XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr, + 0,0,&xtensa_mask23,0,0,0) + XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben, + 0,0,&xtensa_mask24,0,0,0) + XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask25,0,0,0) + XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3, + 0,0,&xtensa_mask26,0,0,0) + XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2, + 0,0,&xtensa_mask27,0,0,0) + XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1, + 0,0,&xtensa_mask28,0,0,0) + XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4, + 0,0,&xtensa_mask29,0,0,0) + XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4, + 0,0,&xtensa_mask30,0,0,0) + XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase, + 0,0,&xtensa_mask31,0,0,0) + XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow, + 0,0,&xtensa_mask32,0,0,0) + XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar, + 0,0,&xtensa_mask33,0,0,0) + XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr, + 0,0,&xtensa_mask34,0,0,0) + XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused, + 0,0,&xtensa_mask35,0,0,0) + XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize, + 0,0,&xtensa_mask36,0,0,0) + XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts, + 0,0,&xtensa_mask37,0,0,0) + XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset, + 0,0,&xtensa_mask38,0,0,0) + XTREG_END diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c b/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c deleted file mode 100644 index 0bca70b5af..0000000000 --- a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c +++ /dev/null @@ -1,220 +0,0 @@ -/* Configuration for the Xtensa architecture for GDB, the GNU debugger. - - Copyright (c) 2003-2019 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) - XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) - XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) - XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) - XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) - XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) - XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) - XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) - XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) - XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) - XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) - XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) - XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) - XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) - XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) - XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) - XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) - XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) - XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) - XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) - XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) - XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) - XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) - XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) - XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) - XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) - XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) - XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) - XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) - XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) - XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) - XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) - XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) - XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) - XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) - XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) - XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) - XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) - XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) - XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) - XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) - XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) - XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) - XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) - XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0, - "03:04:84:b2","03:04:84:a7",0,0,0,0) - XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1, - "03:04:94:b2","03:04:94:a7",0,0,0,0) - XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2, - "03:04:a4:b2","03:04:a4:a7",0,0,0,0) - XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3, - "03:04:b4:b2","03:04:b4:a7",0,0,0,0) - XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4, - "03:04:c4:b2","03:04:c4:a7",0,0,0,0) - XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5, - "03:04:d4:b2","03:04:d4:a7",0,0,0,0) - XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6, - "03:04:e4:b2","03:04:e4:a7",0,0,0,0) - XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7, - "03:04:f4:b2","03:04:f4:a7",0,0,0,0) - XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0, - "03:04:04:c3","03:04:04:c1",0,0,0,0) - XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1, - "03:04:14:c3","03:04:44:c1",0,0,0,0) - XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2, - "03:04:24:c3","03:04:84:c1",0,0,0,0) - XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3, - "03:04:34:c3","03:04:c4:c1",0,0,0,0) - XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) - XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) - XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) - XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0) - XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) - XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) - XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) - XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) - XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) - XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) - XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) - XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) - XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) - XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) - XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) - XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) - XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) - XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) - XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) - XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) - XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) - XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) - XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) - XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) - XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) - XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) - XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) - XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) - XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) - XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) - XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) - XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) - XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) - XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) - XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) - XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) - XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) - XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) - XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) - XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) - XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) - XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) - XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) - XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) - XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) - XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) - XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) - XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) - XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) - XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, - 0,0,&xtensa_mask0,0,0,0) - XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, - 0,0,&xtensa_mask1,0,0,0) - XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, - 0,0,&xtensa_mask2,0,0,0) - XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, - 0,0,&xtensa_mask3,0,0,0) - XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, - 0,0,&xtensa_mask4,0,0,0) - XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, - 0,0,&xtensa_mask5,0,0,0) - XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, - 0,0,&xtensa_mask6,0,0,0) - XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, - 0,0,&xtensa_mask7,0,0,0) - XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, - 0,0,&xtensa_mask8,0,0,0) - XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, - 0,0,&xtensa_mask9,0,0,0) - XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, - 0,0,&xtensa_mask10,0,0,0) - XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, - 0,0,&xtensa_mask11,0,0,0) - XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, - 0,0,&xtensa_mask12,0,0,0) - XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, - 0,0,&xtensa_mask13,0,0,0) - XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, - 0,0,&xtensa_mask14,0,0,0) - XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, - 0,0,&xtensa_mask15,0,0,0) - XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel, - 0,0,&xtensa_mask16,0,0,0) - XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum, - 0,0,&xtensa_mask17,0,0,0) - XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe, - 0,0,&xtensa_mask18,0,0,0) - XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring, - 0,0,&xtensa_mask19,0,0,0) - XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm, - 0,0,&xtensa_mask20,0,0,0) - XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc, - 0,0,&xtensa_mask21,0,0,0) - XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb, - 0,0,&xtensa_mask22,0,0,0) - XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr, - 0,0,&xtensa_mask23,0,0,0) - XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben, - 0,0,&xtensa_mask24,0,0,0) - XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum, - 0,0,&xtensa_mask25,0,0,0) - XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3, - 0,0,&xtensa_mask26,0,0,0) - XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2, - 0,0,&xtensa_mask27,0,0,0) - XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1, - 0,0,&xtensa_mask28,0,0,0) - XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4, - 0,0,&xtensa_mask29,0,0,0) - XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4, - 0,0,&xtensa_mask30,0,0,0) - XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase, - 0,0,&xtensa_mask31,0,0,0) - XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow, - 0,0,&xtensa_mask32,0,0,0) - XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar, - 0,0,&xtensa_mask33,0,0,0) - XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr, - 0,0,&xtensa_mask34,0,0,0) - XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused, - 0,0,&xtensa_mask35,0,0,0) - XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize, - 0,0,&xtensa_mask36,0,0,0) - XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts, - 0,0,&xtensa_mask37,0,0,0) - XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset, - 0,0,&xtensa_mask38,0,0,0) - XTREG_END diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc new file mode 100644 index 0000000000..28561147fc --- /dev/null +++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc @@ -0,0 +1,36387 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2019 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "PTEVADDR", 83, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EPS2", 194, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_SD_NO", 243, 1 } +}; + +#define NUM_SYSREGS 45 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 243 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 12, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EPS2", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 12, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 2, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "CCON", 1, XTENSA_STATE_IS_EXPORTED }, + { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED }, + { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED }, + { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED }, + { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED }, + { "AE_OVERFLOW", 1, 0 }, + { "AE_SAR", 6, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 } +}; + +#define NUM_STATES 63 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EPS2, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_LITBADDR, + STATE_LITBEN, + STATE_MISC0, + STATE_MISC1, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_ASID3, + STATE_ASID2, + STATE_ASID1, + STATE_INSTPGSZID4, + STATE_DATAPGSZID4, + STATE_PTBASE, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_CCON, + STATE_MPSCORE, + STATE_WMPINT_ADDR, + STATE_WMPINT_DATA, + STATE_WMPINT_TOGGLEEN, + STATE_AE_OVERFLOW, + STATE_AE_SAR, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + return tie_t; +} + +static void +Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + return tie_t; +} + +static void +Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 23) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); + tie_t = (val << 22) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 21) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 21) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 21) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); + tie_t = (val << 21) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); + return tie_t; +} + +static void +Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); +} + +static unsigned +Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); + tie_t = (val << 20) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); + tie_t = (val << 20) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); + return tie_t; +} + +static void +Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); + tie_t = (val << 23) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + return tie_t; +} + +static void +Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); +} + +static unsigned +Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 17) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); + return tie_t; +} + +static void +Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); + return tie_t; +} + +static void +Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); +} + +static unsigned +Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + return tie_t; +} + +static void +Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); + return tie_t; +} + +static void +Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); +} + +static unsigned +Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 17) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); + tie_t = (val << 18) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); + tie_t = (val << 18) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 22) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 17) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_r3, + FIELD_ae_s_non_samt, + FIELD_ae_s3, + FIELD_ae_r32, + FIELD_ae_samt_s_t, + FIELD_ae_r20, + FIELD_ae_r10, + FIELD_ae_s20, + FIELD_ae_fld_ohba, + FIELD_ae_fld_ohba2, + FIELD_op0_s3, + FIELD_ftsf12, + FIELD_ftsf13, + FIELD_ftsf14, + FIELD_ftsf21ae_slot1, + FIELD_ftsf22ae_slot1, + FIELD_ftsf23ae_slot1, + FIELD_ftsf24ae_slot1, + FIELD_ftsf25ae_slot1, + FIELD_ftsf26ae_slot1, + FIELD_ftsf27ae_slot1, + FIELD_ftsf28ae_slot1, + FIELD_ftsf29ae_slot1, + FIELD_ftsf30ae_slot1, + FIELD_ftsf31ae_slot1, + FIELD_ftsf32ae_slot1, + FIELD_ftsf33ae_slot1, + FIELD_ftsf34ae_slot1, + FIELD_ftsf35ae_slot1, + FIELD_ftsf36ae_slot1, + FIELD_ftsf37ae_slot1, + FIELD_ftsf38ae_slot1, + FIELD_ftsf39ae_slot1, + FIELD_ftsf40ae_slot1, + FIELD_ftsf41ae_slot1, + FIELD_ftsf42ae_slot1, + FIELD_ftsf43ae_slot1, + FIELD_ftsf44ae_slot1, + FIELD_ftsf45ae_slot1, + FIELD_ftsf46ae_slot1, + FIELD_ftsf47ae_slot1, + FIELD_ftsf48ae_slot1, + FIELD_ftsf49ae_slot1, + FIELD_ftsf50ae_slot1, + FIELD_ftsf51ae_slot1, + FIELD_ftsf52ae_slot1, + FIELD_ftsf53ae_slot1, + FIELD_ftsf54ae_slot1, + FIELD_ftsf55ae_slot1, + FIELD_ftsf56ae_slot1, + FIELD_ftsf57ae_slot1, + FIELD_ftsf58ae_slot1, + FIELD_ftsf59ae_slot1, + FIELD_ftsf60ae_slot1, + FIELD_ftsf61ae_slot1, + FIELD_ftsf63ae_slot1, + FIELD_ftsf64ae_slot1, + FIELD_ftsf66ae_slot1, + FIELD_ftsf67ae_slot1, + FIELD_ftsf69ae_slot1, + FIELD_ftsf71ae_slot1, + FIELD_ftsf72ae_slot1, + FIELD_ftsf73ae_slot1, + FIELD_ftsf75ae_slot1, + FIELD_ftsf76ae_slot1, + FIELD_ftsf77ae_slot1, + FIELD_ftsf78ae_slot1, + FIELD_ftsf79ae_slot1, + FIELD_ftsf80ae_slot1, + FIELD_ftsf81ae_slot1, + FIELD_ftsf82ae_slot1, + FIELD_ftsf84ae_slot1, + FIELD_ftsf86ae_slot1, + FIELD_ftsf87ae_slot1, + FIELD_ftsf88ae_slot1, + FIELD_ftsf89ae_slot1, + FIELD_ftsf90ae_slot1, + FIELD_ftsf91ae_slot1, + FIELD_ftsf92ae_slot1, + FIELD_ftsf94ae_slot1, + FIELD_ftsf96ae_slot1, + FIELD_ftsf97ae_slot1, + FIELD_ftsf98ae_slot1, + FIELD_ftsf99ae_slot1, + FIELD_ftsf100ae_slot1, + FIELD_ftsf101ae_slot1, + FIELD_ftsf103ae_slot1, + FIELD_ftsf104ae_slot1, + FIELD_ftsf105ae_slot1, + FIELD_ftsf106ae_slot1, + FIELD_ftsf107ae_slot1, + FIELD_ftsf108ae_slot1, + FIELD_ftsf109ae_slot1, + FIELD_ftsf110ae_slot1, + FIELD_ftsf111ae_slot1, + FIELD_ftsf112ae_slot1, + FIELD_ftsf113ae_slot1, + FIELD_ftsf114ae_slot1, + FIELD_ftsf115ae_slot1, + FIELD_ftsf116ae_slot1, + FIELD_ftsf118ae_slot1, + FIELD_ftsf119ae_slot1, + FIELD_ftsf120ae_slot1, + FIELD_ftsf122ae_slot1, + FIELD_ftsf124ae_slot1, + FIELD_ftsf125ae_slot1, + FIELD_ftsf126ae_slot1, + FIELD_ftsf127ae_slot1, + FIELD_ftsf128ae_slot1, + FIELD_ftsf129ae_slot1, + FIELD_ftsf130ae_slot1, + FIELD_ftsf131ae_slot1, + FIELD_ftsf132ae_slot1, + FIELD_ftsf133ae_slot1, + FIELD_ftsf134ae_slot1, + FIELD_ftsf135ae_slot1, + FIELD_ftsf136ae_slot1, + FIELD_ftsf137ae_slot1, + FIELD_ftsf138ae_slot1, + FIELD_ftsf139ae_slot1, + FIELD_ftsf140ae_slot1, + FIELD_ftsf141ae_slot1, + FIELD_ftsf142ae_slot1, + FIELD_ftsf143ae_slot1, + FIELD_ftsf144ae_slot1, + FIELD_ftsf145ae_slot1, + FIELD_ftsf146ae_slot1, + FIELD_ftsf147ae_slot1, + FIELD_ftsf148ae_slot1, + FIELD_ftsf149ae_slot1, + FIELD_ftsf150ae_slot1, + FIELD_ftsf151ae_slot1, + FIELD_ftsf152ae_slot1, + FIELD_ftsf153ae_slot1, + FIELD_ftsf154ae_slot1, + FIELD_ftsf155ae_slot1, + FIELD_ftsf156ae_slot1, + FIELD_ftsf157ae_slot1, + FIELD_ftsf158ae_slot1, + FIELD_ftsf159ae_slot1, + FIELD_ftsf160ae_slot1, + FIELD_ftsf161ae_slot1, + FIELD_ftsf162ae_slot1, + FIELD_ftsf163ae_slot1, + FIELD_ftsf164ae_slot1, + FIELD_ftsf165ae_slot1, + FIELD_ftsf166ae_slot1, + FIELD_ftsf167ae_slot1, + FIELD_ftsf168ae_slot1, + FIELD_ftsf169ae_slot1, + FIELD_ftsf170ae_slot1, + FIELD_ftsf171ae_slot1, + FIELD_ftsf172ae_slot1, + FIELD_ftsf173ae_slot1, + FIELD_ftsf174ae_slot1, + FIELD_ftsf175ae_slot1, + FIELD_ftsf176ae_slot1, + FIELD_ftsf177ae_slot1, + FIELD_ftsf178ae_slot1, + FIELD_ftsf179ae_slot1, + FIELD_ftsf180ae_slot1, + FIELD_ftsf181ae_slot1, + FIELD_ftsf182ae_slot1, + FIELD_ftsf183ae_slot1, + FIELD_ftsf184ae_slot1, + FIELD_ftsf185ae_slot1, + FIELD_ftsf186ae_slot1, + FIELD_ftsf187ae_slot1, + FIELD_ftsf188ae_slot1, + FIELD_ftsf189ae_slot1, + FIELD_ftsf190ae_slot1, + FIELD_ftsf191ae_slot1, + FIELD_ftsf192ae_slot1, + FIELD_ftsf193ae_slot1, + FIELD_ftsf194ae_slot1, + FIELD_ftsf195ae_slot1, + FIELD_ftsf196ae_slot1, + FIELD_ftsf197ae_slot1, + FIELD_ftsf198ae_slot1, + FIELD_ftsf199ae_slot1, + FIELD_ftsf200ae_slot1, + FIELD_ftsf201ae_slot1, + FIELD_ftsf202ae_slot1, + FIELD_ftsf203ae_slot1, + FIELD_ftsf204ae_slot1, + FIELD_ftsf205ae_slot1, + FIELD_ftsf206ae_slot1, + FIELD_ftsf207ae_slot1, + FIELD_ftsf208, + FIELD_ftsf209ae_slot1, + FIELD_ftsf210ae_slot1, + FIELD_ftsf211ae_slot1, + FIELD_ftsf330ae_slot1, + FIELD_ftsf332ae_slot1, + FIELD_ftsf334ae_slot1, + FIELD_ftsf336ae_slot1, + FIELD_ftsf337ae_slot1, + FIELD_ftsf338, + FIELD_ftsf339ae_slot1, + FIELD_ftsf340, + FIELD_ftsf341ae_slot1, + FIELD_ftsf342ae_slot1, + FIELD_ftsf343ae_slot1, + FIELD_ftsf344ae_slot1, + FIELD_ftsf346ae_slot1, + FIELD_ftsf347, + FIELD_ftsf348ae_slot1, + FIELD_ftsf349ae_slot1, + FIELD_ftsf350ae_slot1, + FIELD_op0_s4, + FIELD_ftsf212ae_slot0, + FIELD_ftsf213ae_slot0, + FIELD_ftsf214ae_slot0, + FIELD_ftsf215ae_slot0, + FIELD_ftsf216ae_slot0, + FIELD_ftsf217, + FIELD_ftsf218ae_slot0, + FIELD_ftsf219ae_slot0, + FIELD_ftsf220ae_slot0, + FIELD_ftsf221ae_slot0, + FIELD_ftsf222ae_slot0, + FIELD_ftsf223ae_slot0, + FIELD_ftsf224ae_slot0, + FIELD_ftsf225ae_slot0, + FIELD_ftsf226ae_slot0, + FIELD_ftsf227ae_slot0, + FIELD_ftsf228ae_slot0, + FIELD_ftsf229ae_slot0, + FIELD_ftsf230ae_slot0, + FIELD_ftsf231ae_slot0, + FIELD_ftsf232ae_slot0, + FIELD_ftsf233ae_slot0, + FIELD_ftsf234ae_slot0, + FIELD_ftsf235ae_slot0, + FIELD_ftsf236ae_slot0, + FIELD_ftsf237ae_slot0, + FIELD_ftsf238ae_slot0, + FIELD_ftsf239ae_slot0, + FIELD_ftsf240ae_slot0, + FIELD_ftsf241ae_slot0, + FIELD_ftsf242ae_slot0, + FIELD_ftsf243ae_slot0, + FIELD_ftsf244ae_slot0, + FIELD_ftsf245ae_slot0, + FIELD_ftsf246ae_slot0, + FIELD_ftsf247ae_slot0, + FIELD_ftsf248ae_slot0, + FIELD_ftsf249ae_slot0, + FIELD_ftsf250ae_slot0, + FIELD_ftsf251ae_slot0, + FIELD_ftsf252ae_slot0, + FIELD_ftsf253ae_slot0, + FIELD_ftsf254ae_slot0, + FIELD_ftsf255ae_slot0, + FIELD_ftsf256ae_slot0, + FIELD_ftsf257ae_slot0, + FIELD_ftsf258ae_slot0, + FIELD_ftsf259ae_slot0, + FIELD_ftsf260ae_slot0, + FIELD_ftsf261ae_slot0, + FIELD_ftsf262ae_slot0, + FIELD_ftsf263ae_slot0, + FIELD_ftsf264ae_slot0, + FIELD_ftsf265ae_slot0, + FIELD_ftsf266ae_slot0, + FIELD_ftsf267ae_slot0, + FIELD_ftsf268ae_slot0, + FIELD_ftsf269ae_slot0, + FIELD_ftsf270ae_slot0, + FIELD_ftsf271ae_slot0, + FIELD_ftsf272ae_slot0, + FIELD_ftsf273ae_slot0, + FIELD_ftsf274ae_slot0, + FIELD_ftsf275ae_slot0, + FIELD_ftsf276ae_slot0, + FIELD_ftsf277ae_slot0, + FIELD_ftsf278ae_slot0, + FIELD_ftsf279ae_slot0, + FIELD_ftsf281ae_slot0, + FIELD_ftsf282ae_slot0, + FIELD_ftsf283ae_slot0, + FIELD_ftsf284ae_slot0, + FIELD_ftsf286ae_slot0, + FIELD_ftsf288ae_slot0, + FIELD_ftsf290ae_slot0, + FIELD_ftsf292ae_slot0, + FIELD_ftsf293, + FIELD_ftsf294ae_slot0, + FIELD_ftsf295ae_slot0, + FIELD_ftsf296ae_slot0, + FIELD_ftsf297ae_slot0, + FIELD_ftsf298ae_slot0, + FIELD_ftsf299ae_slot0, + FIELD_ftsf300ae_slot0, + FIELD_ftsf301ae_slot0, + FIELD_ftsf302ae_slot0, + FIELD_ftsf303ae_slot0, + FIELD_ftsf304ae_slot0, + FIELD_ftsf306ae_slot0, + FIELD_ftsf308ae_slot0, + FIELD_ftsf309ae_slot0, + FIELD_ftsf310ae_slot0, + FIELD_ftsf311ae_slot0, + FIELD_ftsf312ae_slot0, + FIELD_ftsf313ae_slot0, + FIELD_ftsf314ae_slot0, + FIELD_ftsf315ae_slot0, + FIELD_ftsf316ae_slot0, + FIELD_ftsf317ae_slot0, + FIELD_ftsf318ae_slot0, + FIELD_ftsf319, + FIELD_ftsf320ae_slot0, + FIELD_ftsf321, + FIELD_ftsf322ae_slot0, + FIELD_ftsf323ae_slot0, + FIELD_ftsf324ae_slot0, + FIELD_ftsf325ae_slot0, + FIELD_ftsf326ae_slot0, + FIELD_ftsf328ae_slot0, + FIELD_ftsf329ae_slot0, + FIELD_ftsf352ae_slot0, + FIELD_ftsf353, + FIELD_ftsf354ae_slot0, + FIELD_ftsf356ae_slot0, + FIELD_ftsf357, + FIELD_ftsf358ae_slot0, + FIELD_ftsf359ae_slot0, + FIELD_ftsf360ae_slot0, + FIELD_ftsf361ae_slot0, + FIELD_ftsf362ae_slot0, + FIELD_ftsf364ae_slot0, + FIELD_ftsf365ae_slot0, + FIELD_ftsf366ae_slot0, + FIELD_ftsf368ae_slot0, + FIELD_ftsf369ae_slot0, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + { "ae_add32", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_subshift", 1 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_ae_add32, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_subshift +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_AE_PR, + REGFILE_AE_QR, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, + { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "RMPINT_Out", 12, 0, 0, 'o' }, + { "RMPINT_In", 32, 0, 1, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_RMPINT_Out, + INTERFACE_RMPINT_In +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) +{ + unsigned ae_samt32_out_0; + unsigned ae_samt32_in_0; + ae_samt32_in_0 = *valp & 0x1f; + ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; + *valp = ae_samt32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) +{ + unsigned ae_samt32_in_0; + unsigned ae_samt32_out_0; + ae_samt32_out_0 = *valp; + ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); + *valp = ae_samt32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 8); + return error; +} + +static int +OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) +{ + unsigned ae_lsimm16_out_0; + unsigned ae_lsimm16_in_0; + ae_lsimm16_in_0 = *valp & 0xf; + ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; + *valp = ae_lsimm16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) +{ + unsigned ae_lsimm16_in_0; + unsigned ae_lsimm16_out_0; + ae_lsimm16_out_0 = *valp; + ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); + *valp = ae_lsimm16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) +{ + unsigned ae_lsimm32_out_0; + unsigned ae_lsimm32_in_0; + ae_lsimm32_in_0 = *valp & 0xf; + ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; + *valp = ae_lsimm32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) +{ + unsigned ae_lsimm32_in_0; + unsigned ae_lsimm32_out_0; + ae_lsimm32_out_0 = *valp; + ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); + *valp = ae_lsimm32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) +{ + unsigned ae_lsimm64_out_0; + unsigned ae_lsimm64_in_0; + ae_lsimm64_in_0 = *valp & 0xf; + ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; + *valp = ae_lsimm64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) +{ + unsigned ae_lsimm64_in_0; + unsigned ae_lsimm64_out_0; + ae_lsimm64_out_0 = *valp; + ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); + *valp = ae_lsimm64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) +{ + unsigned ae_samt64_out_0; + unsigned ae_samt64_in_0; + ae_samt64_in_0 = *valp & 0x3f; + ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; + *valp = ae_samt64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) +{ + unsigned ae_samt64_in_0; + unsigned ae_samt64_out_0; + ae_samt64_out_0 = *valp; + ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); + *valp = ae_samt64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) +{ + unsigned ae_ohba_out_0; + unsigned ae_ohba_in_0; + ae_ohba_in_0 = *valp & 0xf; + ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); + *valp = ae_ohba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) +{ + unsigned ae_ohba_in_0; + unsigned ae_ohba_out_0; + ae_ohba_out_0 = *valp; + ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); + *valp = ae_ohba_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "ae_samt32", FIELD_ftsf14, -1, 0, + 0, + OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, + 0, 0 }, + { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "ae_lsimm16", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, + 0, 0 }, + { "ae_lsimm32", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, + 0, 0 }, + { "ae_lsimm64", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, + 0, 0 }, + { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, + 0, + OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, + 0, 0 }, + { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0 }, + { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0 }, + { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf119ae_slot1", FIELD_ftsf119ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf122ae_slot1", FIELD_ftsf122ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf208", FIELD_ftsf208, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf209ae_slot1", FIELD_ftsf209ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf211ae_slot1", FIELD_ftsf211ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf330ae_slot1", FIELD_ftsf330ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf332ae_slot1", FIELD_ftsf332ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf338", FIELD_ftsf338, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf340", FIELD_ftsf340, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf346ae_slot1", FIELD_ftsf346ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf347", FIELD_ftsf347, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf216ae_slot0", FIELD_ftsf216ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf217", FIELD_ftsf217, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_samt32, + OPERAND_pr0, + OPERAND_qr0, + OPERAND_mac_qr0, + OPERAND_ae_lsimm16, + OPERAND_ae_lsimm32, + OPERAND_ae_lsimm64, + OPERAND_ae_samt64, + OPERAND_ae_ohba, + OPERAND_ae_ohba2, + OPERAND_pr, + OPERAND_cvt_pr, + OPERAND_qr0_rw, + OPERAND_mac_qr0_rw, + OPERAND_qr1_w, + OPERAND_mac_qr1_w, + OPERAND_ps, + OPERAND_alupppb_ps, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_r3, + OPERAND_ae_s_non_samt, + OPERAND_ae_s3, + OPERAND_ae_r32, + OPERAND_ae_samt_s_t, + OPERAND_ae_r20, + OPERAND_ae_r10, + OPERAND_ae_s20, + OPERAND_ae_fld_ohba, + OPERAND_ae_fld_ohba2, + OPERAND_op0_s3, + OPERAND_ftsf12, + OPERAND_ftsf13, + OPERAND_ftsf14, + OPERAND_ftsf21ae_slot1, + OPERAND_ftsf22ae_slot1, + OPERAND_ftsf23ae_slot1, + OPERAND_ftsf24ae_slot1, + OPERAND_ftsf25ae_slot1, + OPERAND_ftsf26ae_slot1, + OPERAND_ftsf27ae_slot1, + OPERAND_ftsf28ae_slot1, + OPERAND_ftsf29ae_slot1, + OPERAND_ftsf30ae_slot1, + OPERAND_ftsf31ae_slot1, + OPERAND_ftsf32ae_slot1, + OPERAND_ftsf33ae_slot1, + OPERAND_ftsf34ae_slot1, + OPERAND_ftsf35ae_slot1, + OPERAND_ftsf36ae_slot1, + OPERAND_ftsf37ae_slot1, + OPERAND_ftsf38ae_slot1, + OPERAND_ftsf39ae_slot1, + OPERAND_ftsf40ae_slot1, + OPERAND_ftsf41ae_slot1, + OPERAND_ftsf42ae_slot1, + OPERAND_ftsf43ae_slot1, + OPERAND_ftsf44ae_slot1, + OPERAND_ftsf45ae_slot1, + OPERAND_ftsf46ae_slot1, + OPERAND_ftsf47ae_slot1, + OPERAND_ftsf48ae_slot1, + OPERAND_ftsf49ae_slot1, + OPERAND_ftsf50ae_slot1, + OPERAND_ftsf51ae_slot1, + OPERAND_ftsf52ae_slot1, + OPERAND_ftsf53ae_slot1, + OPERAND_ftsf54ae_slot1, + OPERAND_ftsf55ae_slot1, + OPERAND_ftsf56ae_slot1, + OPERAND_ftsf57ae_slot1, + OPERAND_ftsf58ae_slot1, + OPERAND_ftsf59ae_slot1, + OPERAND_ftsf60ae_slot1, + OPERAND_ftsf61ae_slot1, + OPERAND_ftsf63ae_slot1, + OPERAND_ftsf64ae_slot1, + OPERAND_ftsf66ae_slot1, + OPERAND_ftsf67ae_slot1, + OPERAND_ftsf69ae_slot1, + OPERAND_ftsf71ae_slot1, + OPERAND_ftsf72ae_slot1, + OPERAND_ftsf73ae_slot1, + OPERAND_ftsf75ae_slot1, + OPERAND_ftsf76ae_slot1, + OPERAND_ftsf77ae_slot1, + OPERAND_ftsf78ae_slot1, + OPERAND_ftsf79ae_slot1, + OPERAND_ftsf80ae_slot1, + OPERAND_ftsf81ae_slot1, + OPERAND_ftsf82ae_slot1, + OPERAND_ftsf84ae_slot1, + OPERAND_ftsf86ae_slot1, + OPERAND_ftsf87ae_slot1, + OPERAND_ftsf88ae_slot1, + OPERAND_ftsf89ae_slot1, + OPERAND_ftsf90ae_slot1, + OPERAND_ftsf91ae_slot1, + OPERAND_ftsf92ae_slot1, + OPERAND_ftsf94ae_slot1, + OPERAND_ftsf96ae_slot1, + OPERAND_ftsf97ae_slot1, + OPERAND_ftsf98ae_slot1, + OPERAND_ftsf99ae_slot1, + OPERAND_ftsf100ae_slot1, + OPERAND_ftsf101ae_slot1, + OPERAND_ftsf103ae_slot1, + OPERAND_ftsf104ae_slot1, + OPERAND_ftsf105ae_slot1, + OPERAND_ftsf106ae_slot1, + OPERAND_ftsf107ae_slot1, + OPERAND_ftsf108ae_slot1, + OPERAND_ftsf109ae_slot1, + OPERAND_ftsf110ae_slot1, + OPERAND_ftsf111ae_slot1, + OPERAND_ftsf112ae_slot1, + OPERAND_ftsf113ae_slot1, + OPERAND_ftsf114ae_slot1, + OPERAND_ftsf115ae_slot1, + OPERAND_ftsf116ae_slot1, + OPERAND_ftsf118ae_slot1, + OPERAND_ftsf119ae_slot1, + OPERAND_ftsf120ae_slot1, + OPERAND_ftsf122ae_slot1, + OPERAND_ftsf124ae_slot1, + OPERAND_ftsf125ae_slot1, + OPERAND_ftsf126ae_slot1, + OPERAND_ftsf127ae_slot1, + OPERAND_ftsf128ae_slot1, + OPERAND_ftsf129ae_slot1, + OPERAND_ftsf130ae_slot1, + OPERAND_ftsf131ae_slot1, + OPERAND_ftsf132ae_slot1, + OPERAND_ftsf133ae_slot1, + OPERAND_ftsf134ae_slot1, + OPERAND_ftsf135ae_slot1, + OPERAND_ftsf136ae_slot1, + OPERAND_ftsf137ae_slot1, + OPERAND_ftsf138ae_slot1, + OPERAND_ftsf139ae_slot1, + OPERAND_ftsf140ae_slot1, + OPERAND_ftsf141ae_slot1, + OPERAND_ftsf142ae_slot1, + OPERAND_ftsf143ae_slot1, + OPERAND_ftsf144ae_slot1, + OPERAND_ftsf145ae_slot1, + OPERAND_ftsf146ae_slot1, + OPERAND_ftsf147ae_slot1, + OPERAND_ftsf148ae_slot1, + OPERAND_ftsf149ae_slot1, + OPERAND_ftsf150ae_slot1, + OPERAND_ftsf151ae_slot1, + OPERAND_ftsf152ae_slot1, + OPERAND_ftsf153ae_slot1, + OPERAND_ftsf154ae_slot1, + OPERAND_ftsf155ae_slot1, + OPERAND_ftsf156ae_slot1, + OPERAND_ftsf157ae_slot1, + OPERAND_ftsf158ae_slot1, + OPERAND_ftsf159ae_slot1, + OPERAND_ftsf160ae_slot1, + OPERAND_ftsf161ae_slot1, + OPERAND_ftsf162ae_slot1, + OPERAND_ftsf163ae_slot1, + OPERAND_ftsf164ae_slot1, + OPERAND_ftsf165ae_slot1, + OPERAND_ftsf166ae_slot1, + OPERAND_ftsf167ae_slot1, + OPERAND_ftsf168ae_slot1, + OPERAND_ftsf169ae_slot1, + OPERAND_ftsf170ae_slot1, + OPERAND_ftsf171ae_slot1, + OPERAND_ftsf172ae_slot1, + OPERAND_ftsf173ae_slot1, + OPERAND_ftsf174ae_slot1, + OPERAND_ftsf175ae_slot1, + OPERAND_ftsf176ae_slot1, + OPERAND_ftsf177ae_slot1, + OPERAND_ftsf178ae_slot1, + OPERAND_ftsf179ae_slot1, + OPERAND_ftsf180ae_slot1, + OPERAND_ftsf181ae_slot1, + OPERAND_ftsf182ae_slot1, + OPERAND_ftsf183ae_slot1, + OPERAND_ftsf184ae_slot1, + OPERAND_ftsf185ae_slot1, + OPERAND_ftsf186ae_slot1, + OPERAND_ftsf187ae_slot1, + OPERAND_ftsf188ae_slot1, + OPERAND_ftsf189ae_slot1, + OPERAND_ftsf190ae_slot1, + OPERAND_ftsf191ae_slot1, + OPERAND_ftsf192ae_slot1, + OPERAND_ftsf193ae_slot1, + OPERAND_ftsf194ae_slot1, + OPERAND_ftsf195ae_slot1, + OPERAND_ftsf196ae_slot1, + OPERAND_ftsf197ae_slot1, + OPERAND_ftsf198ae_slot1, + OPERAND_ftsf199ae_slot1, + OPERAND_ftsf200ae_slot1, + OPERAND_ftsf201ae_slot1, + OPERAND_ftsf202ae_slot1, + OPERAND_ftsf203ae_slot1, + OPERAND_ftsf204ae_slot1, + OPERAND_ftsf205ae_slot1, + OPERAND_ftsf206ae_slot1, + OPERAND_ftsf207ae_slot1, + OPERAND_ftsf208, + OPERAND_ftsf209ae_slot1, + OPERAND_ftsf210ae_slot1, + OPERAND_ftsf211ae_slot1, + OPERAND_ftsf330ae_slot1, + OPERAND_ftsf332ae_slot1, + OPERAND_ftsf334ae_slot1, + OPERAND_ftsf336ae_slot1, + OPERAND_ftsf337ae_slot1, + OPERAND_ftsf338, + OPERAND_ftsf339ae_slot1, + OPERAND_ftsf340, + OPERAND_ftsf341ae_slot1, + OPERAND_ftsf342ae_slot1, + OPERAND_ftsf343ae_slot1, + OPERAND_ftsf344ae_slot1, + OPERAND_ftsf346ae_slot1, + OPERAND_ftsf347, + OPERAND_ftsf348ae_slot1, + OPERAND_ftsf349ae_slot1, + OPERAND_ftsf350ae_slot1, + OPERAND_op0_s4, + OPERAND_ftsf212ae_slot0, + OPERAND_ftsf213ae_slot0, + OPERAND_ftsf214ae_slot0, + OPERAND_ftsf215ae_slot0, + OPERAND_ftsf216ae_slot0, + OPERAND_ftsf217, + OPERAND_ftsf218ae_slot0, + OPERAND_ftsf219ae_slot0, + OPERAND_ftsf220ae_slot0, + OPERAND_ftsf221ae_slot0, + OPERAND_ftsf222ae_slot0, + OPERAND_ftsf223ae_slot0, + OPERAND_ftsf224ae_slot0, + OPERAND_ftsf225ae_slot0, + OPERAND_ftsf226ae_slot0, + OPERAND_ftsf227ae_slot0, + OPERAND_ftsf228ae_slot0, + OPERAND_ftsf229ae_slot0, + OPERAND_ftsf230ae_slot0, + OPERAND_ftsf231ae_slot0, + OPERAND_ftsf232ae_slot0, + OPERAND_ftsf233ae_slot0, + OPERAND_ftsf234ae_slot0, + OPERAND_ftsf235ae_slot0, + OPERAND_ftsf236ae_slot0, + OPERAND_ftsf237ae_slot0, + OPERAND_ftsf238ae_slot0, + OPERAND_ftsf239ae_slot0, + OPERAND_ftsf240ae_slot0, + OPERAND_ftsf241ae_slot0, + OPERAND_ftsf242ae_slot0, + OPERAND_ftsf243ae_slot0, + OPERAND_ftsf244ae_slot0, + OPERAND_ftsf245ae_slot0, + OPERAND_ftsf246ae_slot0, + OPERAND_ftsf247ae_slot0, + OPERAND_ftsf248ae_slot0, + OPERAND_ftsf249ae_slot0, + OPERAND_ftsf250ae_slot0, + OPERAND_ftsf251ae_slot0, + OPERAND_ftsf252ae_slot0, + OPERAND_ftsf253ae_slot0, + OPERAND_ftsf254ae_slot0, + OPERAND_ftsf255ae_slot0, + OPERAND_ftsf256ae_slot0, + OPERAND_ftsf257ae_slot0, + OPERAND_ftsf258ae_slot0, + OPERAND_ftsf259ae_slot0, + OPERAND_ftsf260ae_slot0, + OPERAND_ftsf261ae_slot0, + OPERAND_ftsf262ae_slot0, + OPERAND_ftsf263ae_slot0, + OPERAND_ftsf264ae_slot0, + OPERAND_ftsf265ae_slot0, + OPERAND_ftsf266ae_slot0, + OPERAND_ftsf267ae_slot0, + OPERAND_ftsf268ae_slot0, + OPERAND_ftsf269ae_slot0, + OPERAND_ftsf270ae_slot0, + OPERAND_ftsf271ae_slot0, + OPERAND_ftsf272ae_slot0, + OPERAND_ftsf273ae_slot0, + OPERAND_ftsf274ae_slot0, + OPERAND_ftsf275ae_slot0, + OPERAND_ftsf276ae_slot0, + OPERAND_ftsf277ae_slot0, + OPERAND_ftsf278ae_slot0, + OPERAND_ftsf279ae_slot0, + OPERAND_ftsf281ae_slot0, + OPERAND_ftsf282ae_slot0, + OPERAND_ftsf283ae_slot0, + OPERAND_ftsf284ae_slot0, + OPERAND_ftsf286ae_slot0, + OPERAND_ftsf288ae_slot0, + OPERAND_ftsf290ae_slot0, + OPERAND_ftsf292ae_slot0, + OPERAND_ftsf293, + OPERAND_ftsf294ae_slot0, + OPERAND_ftsf295ae_slot0, + OPERAND_ftsf296ae_slot0, + OPERAND_ftsf297ae_slot0, + OPERAND_ftsf298ae_slot0, + OPERAND_ftsf299ae_slot0, + OPERAND_ftsf300ae_slot0, + OPERAND_ftsf301ae_slot0, + OPERAND_ftsf302ae_slot0, + OPERAND_ftsf303ae_slot0, + OPERAND_ftsf304ae_slot0, + OPERAND_ftsf306ae_slot0, + OPERAND_ftsf308ae_slot0, + OPERAND_ftsf309ae_slot0, + OPERAND_ftsf310ae_slot0, + OPERAND_ftsf311ae_slot0, + OPERAND_ftsf312ae_slot0, + OPERAND_ftsf313ae_slot0, + OPERAND_ftsf314ae_slot0, + OPERAND_ftsf315ae_slot0, + OPERAND_ftsf316ae_slot0, + OPERAND_ftsf317ae_slot0, + OPERAND_ftsf318ae_slot0, + OPERAND_ftsf319, + OPERAND_ftsf320ae_slot0, + OPERAND_ftsf321, + OPERAND_ftsf322ae_slot0, + OPERAND_ftsf323ae_slot0, + OPERAND_ftsf324ae_slot0, + OPERAND_ftsf325ae_slot0, + OPERAND_ftsf326ae_slot0, + OPERAND_ftsf328ae_slot0, + OPERAND_ftsf329ae_slot0, + OPERAND_ftsf352ae_slot0, + OPERAND_ftsf353, + OPERAND_ftsf354ae_slot0, + OPERAND_ftsf356ae_slot0, + OPERAND_ftsf357, + OPERAND_ftsf358ae_slot0, + OPERAND_ftsf359ae_slot0, + OPERAND_ftsf360ae_slot0, + OPERAND_ftsf361ae_slot0, + OPERAND_ftsf362ae_slot0, + OPERAND_ftsf364ae_slot0, + OPERAND_ftsf365ae_slot0, + OPERAND_ftsf366ae_slot0, + OPERAND_ftsf368ae_slot0, + OPERAND_ftsf369ae_slot0 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_CCON }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPSCORE }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_RMPINT_Out, + INTERFACE_RMPINT_In +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_CCON }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WMPINT_DATA }, 'o' }, + { { STATE_WMPINT_ADDR }, 'o' }, + { { STATE_MPSCORE }, 'm' }, + { { STATE_WMPINT_TOGGLEEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { + { { OPERAND_pr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_lsimm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { + { { OPERAND_ps }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { + { { OPERAND_pr }, 'm' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { + { { OPERAND_pr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { + { { OPERAND_qr1_w }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { + { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { + { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_cvt_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_cvt_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { + { { OPERAND_alupppb_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { + { { OPERAND_alupppb_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' }, + { { OPERAND_bt2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { + { { OPERAND_bt2 }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bt }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_bt }, 'o' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_ae_samt32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { + { { OPERAND_ps }, 'o' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ae_samt64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { + { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_qr0 }, 'i' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_qr0_rw }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_pr }, 'i' }, + { { OPERAND_pr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 7, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_sd_no_args, + 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_sd_no_args, + 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_overflow_args, + 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_overflow_args, + 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_sar_args, + 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_sar_args, + 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_bitptr_args, + 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_bitptr_args, + 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_bitsused_args, + 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_bitsused_args, + 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_tablesize_args, + 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_tablesize_args, + 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_first_ts_args, + 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_first_ts_args, + 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, + 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, + 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_rur_ae_searchdone_args, + 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_wur_ae_searchdone_args, + 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_i_args, + 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_iu_args, + 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_x_args, + 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16f_xu_args, + 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_i_args, + 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_iu_args, + 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_x_args, + 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24_xu_args, + 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_i_args, + 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_iu_args, + 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_x_args, + 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24f_xu_args, + 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_i_args, + 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_iu_args, + 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_x_args, + 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp16x2f_xu_args, + 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_i_args, + 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_iu_args, + 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_x_args, + 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2f_xu_args, + 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_i_args, + 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_iu_args, + 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_x_args, + 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lp24x2_xu_args, + 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_i_args, + 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sp16x2f_iu_args, + 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, + 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Iclass_ae_iclass_mulzaafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, + 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, + 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, + 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, + 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_sha32_args, + 0, 0, 0, 0 }, + { 3, Iclass_ae_iclass_vldl32t_args, + 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vldl16t_args, + 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vldl16c_args, + 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vldsht_args, + 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_lb_args, + 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_lbi_args, + 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lbk_args, + 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_lbki_args, + 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_db_args, + 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_dbi_args, + 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vlel32t_args, + 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_vlel16t_args, + 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, + { 2, Iclass_ae_iclass_sb_args, + 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, + { 3, Iclass_ae_iclass_sbi_args, + 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_vles16c_args, + 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, + { 1, Iclass_ae_iclass_sbf_args, + 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_wsr_ptevaddr, + ICLASS_xt_iclass_rsr_ptevaddr, + ICLASS_xt_iclass_xsr_ptevaddr, + ICLASS_xt_iclass_rsr_rasid, + ICLASS_xt_iclass_wsr_rasid, + ICLASS_xt_iclass_xsr_rasid, + ICLASS_xt_iclass_rsr_itlbcfg, + ICLASS_xt_iclass_wsr_itlbcfg, + ICLASS_xt_iclass_xsr_itlbcfg, + ICLASS_xt_iclass_rsr_dtlbcfg, + ICLASS_xt_iclass_wsr_dtlbcfg, + ICLASS_xt_iclass_xsr_dtlbcfg, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_ldpte, + ICLASS_xt_iclass_hwwitlba, + ICLASS_xt_iclass_hwwdtlba, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_sd_no, + ICLASS_wur_ae_sd_no, + ICLASS_ae_iclass_rur_ae_overflow, + ICLASS_ae_iclass_wur_ae_overflow, + ICLASS_ae_iclass_rur_ae_sar, + ICLASS_ae_iclass_wur_ae_sar, + ICLASS_ae_iclass_rur_ae_bitptr, + ICLASS_ae_iclass_wur_ae_bitptr, + ICLASS_ae_iclass_rur_ae_bitsused, + ICLASS_ae_iclass_wur_ae_bitsused, + ICLASS_ae_iclass_rur_ae_tablesize, + ICLASS_ae_iclass_wur_ae_tablesize, + ICLASS_ae_iclass_rur_ae_first_ts, + ICLASS_ae_iclass_wur_ae_first_ts, + ICLASS_ae_iclass_rur_ae_nextoffset, + ICLASS_ae_iclass_wur_ae_nextoffset, + ICLASS_ae_iclass_rur_ae_searchdone, + ICLASS_ae_iclass_wur_ae_searchdone, + ICLASS_ae_iclass_lp16f_i, + ICLASS_ae_iclass_lp16f_iu, + ICLASS_ae_iclass_lp16f_x, + ICLASS_ae_iclass_lp16f_xu, + ICLASS_ae_iclass_lp24_i, + ICLASS_ae_iclass_lp24_iu, + ICLASS_ae_iclass_lp24_x, + ICLASS_ae_iclass_lp24_xu, + ICLASS_ae_iclass_lp24f_i, + ICLASS_ae_iclass_lp24f_iu, + ICLASS_ae_iclass_lp24f_x, + ICLASS_ae_iclass_lp24f_xu, + ICLASS_ae_iclass_lp16x2f_i, + ICLASS_ae_iclass_lp16x2f_iu, + ICLASS_ae_iclass_lp16x2f_x, + ICLASS_ae_iclass_lp16x2f_xu, + ICLASS_ae_iclass_lp24x2f_i, + ICLASS_ae_iclass_lp24x2f_iu, + ICLASS_ae_iclass_lp24x2f_x, + ICLASS_ae_iclass_lp24x2f_xu, + ICLASS_ae_iclass_lp24x2_i, + ICLASS_ae_iclass_lp24x2_iu, + ICLASS_ae_iclass_lp24x2_x, + ICLASS_ae_iclass_lp24x2_xu, + ICLASS_ae_iclass_sp16x2f_i, + ICLASS_ae_iclass_sp16x2f_iu, + ICLASS_ae_iclass_sp16x2f_x, + ICLASS_ae_iclass_sp16x2f_xu, + ICLASS_ae_iclass_sp24x2s_i, + ICLASS_ae_iclass_sp24x2s_iu, + ICLASS_ae_iclass_sp24x2s_x, + ICLASS_ae_iclass_sp24x2s_xu, + ICLASS_ae_iclass_sp24x2f_i, + ICLASS_ae_iclass_sp24x2f_iu, + ICLASS_ae_iclass_sp24x2f_x, + ICLASS_ae_iclass_sp24x2f_xu, + ICLASS_ae_iclass_sp16f_l_i, + ICLASS_ae_iclass_sp16f_l_iu, + ICLASS_ae_iclass_sp16f_l_x, + ICLASS_ae_iclass_sp16f_l_xu, + ICLASS_ae_iclass_sp24s_l_i, + ICLASS_ae_iclass_sp24s_l_iu, + ICLASS_ae_iclass_sp24s_l_x, + ICLASS_ae_iclass_sp24s_l_xu, + ICLASS_ae_iclass_sp24f_l_i, + ICLASS_ae_iclass_sp24f_l_iu, + ICLASS_ae_iclass_sp24f_l_x, + ICLASS_ae_iclass_sp24f_l_xu, + ICLASS_ae_iclass_lq56_i, + ICLASS_ae_iclass_lq56_iu, + ICLASS_ae_iclass_lq56_x, + ICLASS_ae_iclass_lq56_xu, + ICLASS_ae_iclass_lq32f_i, + ICLASS_ae_iclass_lq32f_iu, + ICLASS_ae_iclass_lq32f_x, + ICLASS_ae_iclass_lq32f_xu, + ICLASS_ae_iclass_sq56s_i, + ICLASS_ae_iclass_sq56s_iu, + ICLASS_ae_iclass_sq56s_x, + ICLASS_ae_iclass_sq56s_xu, + ICLASS_ae_iclass_sq32f_i, + ICLASS_ae_iclass_sq32f_iu, + ICLASS_ae_iclass_sq32f_x, + ICLASS_ae_iclass_sq32f_xu, + ICLASS_ae_iclass_zerop48, + ICLASS_ae_iclass_movp48, + ICLASS_ae_iclass_selp24_ll, + ICLASS_ae_iclass_selp24_lh, + ICLASS_ae_iclass_selp24_hl, + ICLASS_ae_iclass_selp24_hh, + ICLASS_ae_iclass_movtp24x2, + ICLASS_ae_iclass_movfp24x2, + ICLASS_ae_iclass_movtp48, + ICLASS_ae_iclass_movfp48, + ICLASS_ae_iclass_movpa24x2, + ICLASS_ae_iclass_truncp24a32x2, + ICLASS_ae_iclass_cvta32p24_l, + ICLASS_ae_iclass_cvta32p24_h, + ICLASS_ae_iclass_cvtp24a16x2_ll, + ICLASS_ae_iclass_cvtp24a16x2_lh, + ICLASS_ae_iclass_cvtp24a16x2_hl, + ICLASS_ae_iclass_cvtp24a16x2_hh, + ICLASS_ae_iclass_truncp24q48x2, + ICLASS_ae_iclass_truncp16, + ICLASS_ae_iclass_roundsp24q48sym, + ICLASS_ae_iclass_roundsp24q48asym, + ICLASS_ae_iclass_roundsp16q48sym, + ICLASS_ae_iclass_roundsp16q48asym, + ICLASS_ae_iclass_roundsp16sym, + ICLASS_ae_iclass_roundsp16asym, + ICLASS_ae_iclass_zeroq56, + ICLASS_ae_iclass_movq56, + ICLASS_ae_iclass_movtq56, + ICLASS_ae_iclass_movfq56, + ICLASS_ae_iclass_cvtq48a32s, + ICLASS_ae_iclass_cvtq48p24s_l, + ICLASS_ae_iclass_cvtq48p24s_h, + ICLASS_ae_iclass_satq48s, + ICLASS_ae_iclass_truncq32, + ICLASS_ae_iclass_roundsq32sym, + ICLASS_ae_iclass_roundsq32asym, + ICLASS_ae_iclass_trunca32q48, + ICLASS_ae_iclass_movap24s_l, + ICLASS_ae_iclass_movap24s_h, + ICLASS_ae_iclass_trunca16p24s_l, + ICLASS_ae_iclass_trunca16p24s_h, + ICLASS_ae_iclass_addp24, + ICLASS_ae_iclass_subp24, + ICLASS_ae_iclass_negp24, + ICLASS_ae_iclass_absp24, + ICLASS_ae_iclass_maxp24s, + ICLASS_ae_iclass_minp24s, + ICLASS_ae_iclass_maxbp24s, + ICLASS_ae_iclass_minbp24s, + ICLASS_ae_iclass_addsp24s, + ICLASS_ae_iclass_subsp24s, + ICLASS_ae_iclass_negsp24s, + ICLASS_ae_iclass_abssp24s, + ICLASS_ae_iclass_andp48, + ICLASS_ae_iclass_nandp48, + ICLASS_ae_iclass_orp48, + ICLASS_ae_iclass_xorp48, + ICLASS_ae_iclass_ltp24s, + ICLASS_ae_iclass_lep24s, + ICLASS_ae_iclass_eqp24, + ICLASS_ae_iclass_addq56, + ICLASS_ae_iclass_subq56, + ICLASS_ae_iclass_negq56, + ICLASS_ae_iclass_absq56, + ICLASS_ae_iclass_maxq56s, + ICLASS_ae_iclass_minq56s, + ICLASS_ae_iclass_maxbq56s, + ICLASS_ae_iclass_minbq56s, + ICLASS_ae_iclass_addsq56s, + ICLASS_ae_iclass_subsq56s, + ICLASS_ae_iclass_negsq56s, + ICLASS_ae_iclass_abssq56s, + ICLASS_ae_iclass_andq56, + ICLASS_ae_iclass_nandq56, + ICLASS_ae_iclass_orq56, + ICLASS_ae_iclass_xorq56, + ICLASS_ae_iclass_sllip24, + ICLASS_ae_iclass_srlip24, + ICLASS_ae_iclass_sraip24, + ICLASS_ae_iclass_sllsp24, + ICLASS_ae_iclass_srlsp24, + ICLASS_ae_iclass_srasp24, + ICLASS_ae_iclass_sllisp24s, + ICLASS_ae_iclass_sllssp24s, + ICLASS_ae_iclass_slliq56, + ICLASS_ae_iclass_srliq56, + ICLASS_ae_iclass_sraiq56, + ICLASS_ae_iclass_sllsq56, + ICLASS_ae_iclass_srlsq56, + ICLASS_ae_iclass_srasq56, + ICLASS_ae_iclass_sllaq56, + ICLASS_ae_iclass_srlaq56, + ICLASS_ae_iclass_sraaq56, + ICLASS_ae_iclass_sllisq56s, + ICLASS_ae_iclass_sllssq56s, + ICLASS_ae_iclass_sllasq56s, + ICLASS_ae_iclass_ltq56s, + ICLASS_ae_iclass_leq56s, + ICLASS_ae_iclass_eqq56, + ICLASS_ae_iclass_nsaq56s, + ICLASS_ae_iclass_mulfs32p16s_ll, + ICLASS_ae_iclass_mulfp24s_ll, + ICLASS_ae_iclass_mulp24s_ll, + ICLASS_ae_iclass_mulfs32p16s_lh, + ICLASS_ae_iclass_mulfp24s_lh, + ICLASS_ae_iclass_mulp24s_lh, + ICLASS_ae_iclass_mulfs32p16s_hl, + ICLASS_ae_iclass_mulfp24s_hl, + ICLASS_ae_iclass_mulp24s_hl, + ICLASS_ae_iclass_mulfs32p16s_hh, + ICLASS_ae_iclass_mulfp24s_hh, + ICLASS_ae_iclass_mulp24s_hh, + ICLASS_ae_iclass_mulafs32p16s_ll, + ICLASS_ae_iclass_mulafp24s_ll, + ICLASS_ae_iclass_mulap24s_ll, + ICLASS_ae_iclass_mulafs32p16s_lh, + ICLASS_ae_iclass_mulafp24s_lh, + ICLASS_ae_iclass_mulap24s_lh, + ICLASS_ae_iclass_mulafs32p16s_hl, + ICLASS_ae_iclass_mulafp24s_hl, + ICLASS_ae_iclass_mulap24s_hl, + ICLASS_ae_iclass_mulafs32p16s_hh, + ICLASS_ae_iclass_mulafp24s_hh, + ICLASS_ae_iclass_mulap24s_hh, + ICLASS_ae_iclass_mulsfs32p16s_ll, + ICLASS_ae_iclass_mulsfp24s_ll, + ICLASS_ae_iclass_mulsp24s_ll, + ICLASS_ae_iclass_mulsfs32p16s_lh, + ICLASS_ae_iclass_mulsfp24s_lh, + ICLASS_ae_iclass_mulsp24s_lh, + ICLASS_ae_iclass_mulsfs32p16s_hl, + ICLASS_ae_iclass_mulsfp24s_hl, + ICLASS_ae_iclass_mulsp24s_hl, + ICLASS_ae_iclass_mulsfs32p16s_hh, + ICLASS_ae_iclass_mulsfp24s_hh, + ICLASS_ae_iclass_mulsp24s_hh, + ICLASS_ae_iclass_mulafs56p24s_ll, + ICLASS_ae_iclass_mulas56p24s_ll, + ICLASS_ae_iclass_mulafs56p24s_lh, + ICLASS_ae_iclass_mulas56p24s_lh, + ICLASS_ae_iclass_mulafs56p24s_hl, + ICLASS_ae_iclass_mulas56p24s_hl, + ICLASS_ae_iclass_mulafs56p24s_hh, + ICLASS_ae_iclass_mulas56p24s_hh, + ICLASS_ae_iclass_mulsfs56p24s_ll, + ICLASS_ae_iclass_mulss56p24s_ll, + ICLASS_ae_iclass_mulsfs56p24s_lh, + ICLASS_ae_iclass_mulss56p24s_lh, + ICLASS_ae_iclass_mulsfs56p24s_hl, + ICLASS_ae_iclass_mulss56p24s_hl, + ICLASS_ae_iclass_mulsfs56p24s_hh, + ICLASS_ae_iclass_mulss56p24s_hh, + ICLASS_ae_iclass_mulfq32sp16s_l, + ICLASS_ae_iclass_mulfq32sp16s_h, + ICLASS_ae_iclass_mulfq32sp16u_l, + ICLASS_ae_iclass_mulfq32sp16u_h, + ICLASS_ae_iclass_mulq32sp16s_l, + ICLASS_ae_iclass_mulq32sp16s_h, + ICLASS_ae_iclass_mulq32sp16u_l, + ICLASS_ae_iclass_mulq32sp16u_h, + ICLASS_ae_iclass_mulafq32sp16s_l, + ICLASS_ae_iclass_mulafq32sp16s_h, + ICLASS_ae_iclass_mulafq32sp16u_l, + ICLASS_ae_iclass_mulafq32sp16u_h, + ICLASS_ae_iclass_mulaq32sp16s_l, + ICLASS_ae_iclass_mulaq32sp16s_h, + ICLASS_ae_iclass_mulaq32sp16u_l, + ICLASS_ae_iclass_mulaq32sp16u_h, + ICLASS_ae_iclass_mulsfq32sp16s_l, + ICLASS_ae_iclass_mulsfq32sp16s_h, + ICLASS_ae_iclass_mulsfq32sp16u_l, + ICLASS_ae_iclass_mulsfq32sp16u_h, + ICLASS_ae_iclass_mulsq32sp16s_l, + ICLASS_ae_iclass_mulsq32sp16s_h, + ICLASS_ae_iclass_mulsq32sp16u_l, + ICLASS_ae_iclass_mulsq32sp16u_h, + ICLASS_ae_iclass_mulzaaq32sp16s_ll, + ICLASS_ae_iclass_mulzaafq32sp16s_ll, + ICLASS_ae_iclass_mulzaaq32sp16u_ll, + ICLASS_ae_iclass_mulzaafq32sp16u_ll, + ICLASS_ae_iclass_mulzaaq32sp16s_hh, + ICLASS_ae_iclass_mulzaafq32sp16s_hh, + ICLASS_ae_iclass_mulzaaq32sp16u_hh, + ICLASS_ae_iclass_mulzaafq32sp16u_hh, + ICLASS_ae_iclass_mulzaaq32sp16s_lh, + ICLASS_ae_iclass_mulzaafq32sp16s_lh, + ICLASS_ae_iclass_mulzaaq32sp16u_lh, + ICLASS_ae_iclass_mulzaafq32sp16u_lh, + ICLASS_ae_iclass_mulzasq32sp16s_ll, + ICLASS_ae_iclass_mulzasfq32sp16s_ll, + ICLASS_ae_iclass_mulzasq32sp16u_ll, + ICLASS_ae_iclass_mulzasfq32sp16u_ll, + ICLASS_ae_iclass_mulzasq32sp16s_hh, + ICLASS_ae_iclass_mulzasfq32sp16s_hh, + ICLASS_ae_iclass_mulzasq32sp16u_hh, + ICLASS_ae_iclass_mulzasfq32sp16u_hh, + ICLASS_ae_iclass_mulzasq32sp16s_lh, + ICLASS_ae_iclass_mulzasfq32sp16s_lh, + ICLASS_ae_iclass_mulzasq32sp16u_lh, + ICLASS_ae_iclass_mulzasfq32sp16u_lh, + ICLASS_ae_iclass_mulzsaq32sp16s_ll, + ICLASS_ae_iclass_mulzsafq32sp16s_ll, + ICLASS_ae_iclass_mulzsaq32sp16u_ll, + ICLASS_ae_iclass_mulzsafq32sp16u_ll, + ICLASS_ae_iclass_mulzsaq32sp16s_hh, + ICLASS_ae_iclass_mulzsafq32sp16s_hh, + ICLASS_ae_iclass_mulzsaq32sp16u_hh, + ICLASS_ae_iclass_mulzsafq32sp16u_hh, + ICLASS_ae_iclass_mulzsaq32sp16s_lh, + ICLASS_ae_iclass_mulzsafq32sp16s_lh, + ICLASS_ae_iclass_mulzsaq32sp16u_lh, + ICLASS_ae_iclass_mulzsafq32sp16u_lh, + ICLASS_ae_iclass_mulzssq32sp16s_ll, + ICLASS_ae_iclass_mulzssfq32sp16s_ll, + ICLASS_ae_iclass_mulzssq32sp16u_ll, + ICLASS_ae_iclass_mulzssfq32sp16u_ll, + ICLASS_ae_iclass_mulzssq32sp16s_hh, + ICLASS_ae_iclass_mulzssfq32sp16s_hh, + ICLASS_ae_iclass_mulzssq32sp16u_hh, + ICLASS_ae_iclass_mulzssfq32sp16u_hh, + ICLASS_ae_iclass_mulzssq32sp16s_lh, + ICLASS_ae_iclass_mulzssfq32sp16s_lh, + ICLASS_ae_iclass_mulzssq32sp16u_lh, + ICLASS_ae_iclass_mulzssfq32sp16u_lh, + ICLASS_ae_iclass_mulzaafp24s_hh_ll, + ICLASS_ae_iclass_mulzaap24s_hh_ll, + ICLASS_ae_iclass_mulzaafp24s_hl_lh, + ICLASS_ae_iclass_mulzaap24s_hl_lh, + ICLASS_ae_iclass_mulzasfp24s_hh_ll, + ICLASS_ae_iclass_mulzasp24s_hh_ll, + ICLASS_ae_iclass_mulzasfp24s_hl_lh, + ICLASS_ae_iclass_mulzasp24s_hl_lh, + ICLASS_ae_iclass_mulzsafp24s_hh_ll, + ICLASS_ae_iclass_mulzsap24s_hh_ll, + ICLASS_ae_iclass_mulzsafp24s_hl_lh, + ICLASS_ae_iclass_mulzsap24s_hl_lh, + ICLASS_ae_iclass_mulzssfp24s_hh_ll, + ICLASS_ae_iclass_mulzssp24s_hh_ll, + ICLASS_ae_iclass_mulzssfp24s_hl_lh, + ICLASS_ae_iclass_mulzssp24s_hl_lh, + ICLASS_ae_iclass_mulaafp24s_hh_ll, + ICLASS_ae_iclass_mulaap24s_hh_ll, + ICLASS_ae_iclass_mulaafp24s_hl_lh, + ICLASS_ae_iclass_mulaap24s_hl_lh, + ICLASS_ae_iclass_mulasfp24s_hh_ll, + ICLASS_ae_iclass_mulasp24s_hh_ll, + ICLASS_ae_iclass_mulasfp24s_hl_lh, + ICLASS_ae_iclass_mulasp24s_hl_lh, + ICLASS_ae_iclass_mulsafp24s_hh_ll, + ICLASS_ae_iclass_mulsap24s_hh_ll, + ICLASS_ae_iclass_mulsafp24s_hl_lh, + ICLASS_ae_iclass_mulsap24s_hl_lh, + ICLASS_ae_iclass_mulssfp24s_hh_ll, + ICLASS_ae_iclass_mulssp24s_hh_ll, + ICLASS_ae_iclass_mulssfp24s_hl_lh, + ICLASS_ae_iclass_mulssp24s_hl_lh, + ICLASS_ae_iclass_sha32, + ICLASS_ae_iclass_vldl32t, + ICLASS_ae_iclass_vldl16t, + ICLASS_ae_iclass_vldl16c, + ICLASS_ae_iclass_vldsht, + ICLASS_ae_iclass_lb, + ICLASS_ae_iclass_lbi, + ICLASS_ae_iclass_lbk, + ICLASS_ae_iclass_lbki, + ICLASS_ae_iclass_db, + ICLASS_ae_iclass_dbi, + ICLASS_ae_iclass_vlel32t, + ICLASS_ae_iclass_vlel16t, + ICLASS_ae_iclass_sb, + ICLASS_ae_iclass_sbi, + ICLASS_ae_iclass_vles16c, + ICLASS_ae_iclass_sbf +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200040; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200080; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300003; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300001; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300004; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200020; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300002; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300008; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000a0; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000c0; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000d0; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000b0; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000e0; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200060; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400010; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200050; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000f0; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200070; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200090; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee031; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400040; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400020; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400080; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400030; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1d00; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1c00; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16105; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee0b1; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400050; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400060; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400070; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee071; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee038; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee034; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee032; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef0a0; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5003; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1f00; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1e00; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2480; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2800; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef060; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef020; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300005; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300006; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90804; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0004; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90904; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca1004; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90a04; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca2004; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90b04; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca3004; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90c04; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca4004; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90d04; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca5004; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90e04; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca6004; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90f04; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca7004; +} + +static void +Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1080; +} + +static void +Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50004; +} + +static void +Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2080; +} + +static void +Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa90004; +} + +static void +Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0004; +} + +static void +Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3080; +} + +static void +Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0004; +} + +static void +Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6080; +} + +static void +Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa58004; +} + +static void +Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7000; +} + +static void +Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa98004; +} + +static void +Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7080; +} + +static void +Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac8004; +} + +static void +Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8080; +} + +static void +Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf8004; +} + +static void +Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60004; +} + +static void +Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0004; +} + +static void +Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0004; +} + +static void +Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9080; +} + +static void +Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00004; +} + +static void +Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4080; +} + +static void +Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa68004; +} + +static void +Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5000; +} + +static void +Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa8004; +} + +static void +Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad8004; +} + +static void +Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5080; +} + +static void +Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb08004; +} + +static void +Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd000; +} + +static void +Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa70004; +} + +static void +Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0004; +} + +static void +Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd080; +} + +static void +Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0004; +} + +static void +Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de080; +} + +static void +Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10004; +} + +static void +Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da080; +} + +static void +Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa78004; +} + +static void +Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8004; +} + +static void +Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db080; +} + +static void +Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae8004; +} + +static void +Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc080; +} + +static void +Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb18004; +} + +static void +Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20004; +} + +static void +Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50004; +} + +static void +Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1080; +} + +static void +Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80004; +} + +static void +Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2080; +} + +static void +Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0004; +} + +static void +Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb28004; +} + +static void +Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9080; +} + +static void +Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb58004; +} + +static void +Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea080; +} + +static void +Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb88004; +} + +static void +Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb000; +} + +static void +Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8004; +} + +static void +Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7080; +} + +static void +Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30004; +} + +static void +Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8080; +} + +static void +Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60004; +} + +static void +Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90004; +} + +static void +Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0004; +} + +static void +Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df080; +} + +static void +Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb38004; +} + +static void +Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb68004; +} + +static void +Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98004; +} + +static void +Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4000; +} + +static void +Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc8004; +} + +static void +Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40004; +} + +static void +Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5080; +} + +static void +Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70004; +} + +static void +Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6080; +} + +static void +Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0004; +} + +static void +Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7000; +} + +static void +Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0004; +} + +static void +Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb48004; +} + +static void +Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3080; +} + +static void +Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb78004; +} + +static void +Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4080; +} + +static void +Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba8004; +} + +static void +Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5000; +} + +static void +Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd8004; +} + +static void +Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed030; +} + +static void +Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10004; +} + +static void +Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee010; +} + +static void +Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12004; +} + +static void +Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee020; +} + +static void +Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20004; +} + +static void +Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef000; +} + +static void +Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc22004; +} + +static void +Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed000; +} + +static void +Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc11004; +} + +static void +Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc13004; +} + +static void +Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed010; +} + +static void +Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21004; +} + +static void +Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed020; +} + +static void +Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc23004; +} + +static void +Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0080; +} + +static void +Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30004; +} + +static void +Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c0; +} + +static void +Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc38004; +} + +static void +Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40004; +} + +static void +Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3040; +} + +static void +Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48004; +} + +static void +Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec080; +} + +static void +Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc34004; +} + +static void +Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0c0; +} + +static void +Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3c004; +} + +static void +Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4000; +} + +static void +Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc44004; +} + +static void +Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c004; +} + +static void +Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b88; +} + +static void +Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16808; +} + +static void +Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2400; +} + +static void +Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90004; +} + +static void +Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780; +} + +static void +Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708; +} + +static void +Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10688; +} + +static void +Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700; +} + +static void +Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200; +} + +static void +Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c004; +} + +static void +Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480; +} + +static void +Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400; +} + +static void +Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df000; +} + +static void +Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00004; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb080; +} + +static void +Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08004; +} + +static void +Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3081; +} + +static void +Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0004; +} + +static void +Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3080; +} + +static void +Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb8004; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0004; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe8004; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0004; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf8004; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b08; +} + +static void +Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e48; +} + +static void +Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e28; +} + +static void +Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e18; +} + +static void +Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e08; +} + +static void +Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16908; +} + +static void +Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16888; +} + +static void +Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16085; +} + +static void +Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16007; +} + +static void +Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2500; +} + +static void +Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90414; +} + +static void +Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50014; +} + +static void +Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5000; +} + +static void +Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60014; +} + +static void +Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee030; +} + +static void +Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe72034; +} + +static void +Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16006; +} + +static void +Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16005; +} + +static void +Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50139; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16047; +} + +static void +Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16027; +} + +static void +Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16017; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3086; +} + +static void +Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70014; +} + +static void +Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3084; +} + +static void +Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70004; +} + +static void +Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3082; +} + +static void +Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc78004; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3083; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80004; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3088; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88004; +} + +static void +Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500; +} + +static void +Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10788; +} + +static void +Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600; +} + +static void +Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c480; +} + +static void +Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580; +} + +static void +Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588; +} + +static void +Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600; +} + +static void +Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400; +} + +static void +Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c488; +} + +static void +Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500; +} + +static void +Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508; +} + +static void +Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608; +} + +static void +Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680; +} + +static void +Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c408; +} + +static void +Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c002; +} + +static void +Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c001; +} + +static void +Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50035; +} + +static void +Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5003c; +} + +static void +Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50039; +} + +static void +Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50032; +} + +static void +Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50034; +} + +static void +Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50010; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50030; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50036; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500b9; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5003a; +} + +static void +Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50031; +} + +static void +Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50038; +} + +static void +Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50033; +} + +static void +Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50037; +} + +static void +Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000; +} + +static void +Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14800; +} + +static void +Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a08; +} + +static void +Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a88; +} + +static void +Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16988; +} + +static void +Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c08; +} + +static void +Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50004; +} + +static void +Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1800; +} + +static void +Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50404; +} + +static void +Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1400; +} + +static void +Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50804; +} + +static void +Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2600; +} + +static void +Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90014; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2504; +} + +static void +Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90114; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2502; +} + +static void +Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90214; +} + +static void +Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5001; +} + +static void +Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe10014; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5008; +} + +static void +Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20014; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5004; +} + +static void +Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30014; +} + +static void +Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50c04; +} + +static void +Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2501; +} + +static void +Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90314; +} + +static void +Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5002; +} + +static void +Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40014; +} + +static void +Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50800; +} + +static void +Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50040; +} + +static void +Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50020; +} + +static void +Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3085; +} + +static void +Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe74014; +} + +static void +Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60101; +} + +static void +Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008b; +} + +static void +Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60180; +} + +static void +Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008f; +} + +static void +Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008c; +} + +static void +Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60108; +} + +static void +Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008e; +} + +static void +Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008a; +} + +static void +Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60104; +} + +static void +Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6008d; +} + +static void +Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60089; +} + +static void +Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60102; +} + +static void +Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60006; +} + +static void +Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000f; +} + +static void +Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60005; +} + +static void +Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60100; +} + +static void +Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000e; +} + +static void +Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003; +} + +static void +Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60080; +} + +static void +Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000d; +} + +static void +Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60008; +} + +static void +Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000b; +} + +static void +Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60181; +} + +static void +Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010b; +} + +static void +Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60189; +} + +static void +Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010f; +} + +static void +Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010c; +} + +static void +Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60187; +} + +static void +Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010e; +} + +static void +Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010a; +} + +static void +Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60186; +} + +static void +Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6010d; +} + +static void +Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60109; +} + +static void +Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60185; +} + +static void +Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c; +} + +static void +Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60088; +} + +static void +Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000a; +} + +static void +Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60084; +} + +static void +Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60009; +} + +static void +Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60082; +} + +static void +Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60007; +} + +static void +Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60081; +} + +static void +Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60183; +} + +static void +Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018d; +} + +static void +Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60188; +} + +static void +Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018b; +} + +static void +Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60184; +} + +static void +Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018c; +} + +static void +Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60182; +} + +static void +Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018a; +} + +static void +Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15807; +} + +static void +Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15806; +} + +static void +Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580a; +} + +static void +Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15809; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580b; +} + +static void +Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580c; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580e; +} + +static void +Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580d; +} + +static void +Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15800; +} + +static void +Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000; +} + +static void +Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15802; +} + +static void +Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15801; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15808; +} + +static void +Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15804; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15805; +} + +static void +Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15803; +} + +static void +Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001; +} + +static void +Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580f; +} + +static void +Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16004; +} + +static void +Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800; +} + +static void +Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16008; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003; +} + +static void +Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000; +} + +static void +Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20007; +} + +static void +Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20002; +} + +static void +Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000c; +} + +static void +Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20003; +} + +static void +Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20005; +} + +static void +Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20009; +} + +static void +Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20004; +} + +static void +Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20006; +} + +static void +Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000a; +} + +static void +Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20008; +} + +static void +Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30008; +} + +static void +Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000e; +} + +static void +Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30006; +} + +static void +Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001; +} + +static void +Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30002; +} + +static void +Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000b; +} + +static void +Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30003; +} + +static void +Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000f; +} + +static void +Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30004; +} + +static void +Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000d; +} + +static void +Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30005; +} + +static void +Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000a; +} + +static void +Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004; +} + +static void +Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000d; +} + +static void +Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000e; +} + +static void +Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30007; +} + +static void +Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000c; +} + +static void +Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000f; +} + +static void +Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30009; +} + +static void +Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000b; +} + +static void +Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000b; +} + +static void +Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005; +} + +static void +Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000f; +} + +static void +Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009; +} + +static void +Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a; +} + +static void +Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008; +} + +static void +Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d; +} + +static void +Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006; +} + +static void +Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c; +} + +static void +Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40003; +} + +static void +Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000e; +} + +static void +Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007; +} + +static void +Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64004; +} + +static void +Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64080; +} + +static void +Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64008; +} + +static void +Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64100; +} + +static void +Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003; +} + +static void +Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64006; +} + +static void +Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64005; +} + +static void +Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64007; +} + +static void +Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64009; +} + +static void +Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c; +} + +static void +Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400a; +} + +static void +Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400b; +} + +static void +Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400d; +} + +static void +Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400f; +} + +static void +Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400e; +} + +static void +Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64081; +} + +static void +Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002; +} + +static void +Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001; +} + +static void +Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60004; +} + +static void +Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60083; +} + +static void +Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60086; +} + +static void +Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60085; +} + +static void +Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60087; +} + +static void +Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60103; +} + +static void +Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60106; +} + +static void +Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60105; +} + +static void +Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60107; +} + +static void +Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018e; +} + +static void +Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001; +} + +static void +Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6018f; +} + +static void +Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002; +} + +static void +Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00014; +} + +static void +Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00004; +} + +static void +Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10004; +} + +static void +Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7e014; +} + +static void +Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca8004; +} + +static void +Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60004; +} + +static void +Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00024; +} + +static void +Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20004; +} + +static void +Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00004; +} + +static void +Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01004; +} + +static void +Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02004; +} + +static void +Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30004; +} + +static void +Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40004; +} + +static void +Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11004; +} + +static void +Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00004; +} + +static void +Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7c014; +} + +static void +Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7d014; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { + Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { + Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { + Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { + Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { + Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { + Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { + Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { + Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { + Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { + Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { + Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { + Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { + Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { + Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { + Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { + Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { + Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { + Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { + Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { + Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { + Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { + Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { + Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { + Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { + Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { + Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { + Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { + Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { + Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { + Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { + Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { + Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { + Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { + Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { + Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { + Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { + Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { + Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { + Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { + Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { + Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { + Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { + Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { + Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { + Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { + Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { + Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { + Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { + Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { + Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { + Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { + Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { + Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { + Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { + Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { + Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { + Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { + Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { + Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { + Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { + Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { + Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { + Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { + Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { + Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { + Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { + 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { + Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { + Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { + Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { + Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { + Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { + Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { + Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { + Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { + 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { + Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { + Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { + 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { + Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { + Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { + Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { + Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { + Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { + Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { + Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { + Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { + Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_shift32x5, 3 }, + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_shift32x5, 3 }, + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 2 }, + { FUNCUNIT_ae_subshift, 2 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", ICLASS_xt_iclass_ldpte, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", ICLASS_xt_iclass_hwwitlba, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, + 0, + Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, + { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, + 0, + Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, + 0, + Opcode_ae_lp16f_i_encode_fns, 0, 0 }, + { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, + 0, + Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, + { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, + 0, + Opcode_ae_lp16f_x_encode_fns, 0, 0 }, + { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, + 0, + Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, + { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, + 0, + Opcode_ae_lp24_i_encode_fns, 0, 0 }, + { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, + 0, + Opcode_ae_lp24_iu_encode_fns, 0, 0 }, + { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, + 0, + Opcode_ae_lp24_x_encode_fns, 0, 0 }, + { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, + 0, + Opcode_ae_lp24_xu_encode_fns, 0, 0 }, + { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, + 0, + Opcode_ae_lp24f_i_encode_fns, 0, 0 }, + { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, + 0, + Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, + { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, + 0, + Opcode_ae_lp24f_x_encode_fns, 0, 0 }, + { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, + 0, + Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, + { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, + 0, + Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, + { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, + 0, + Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, + { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, + 0, + Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, + { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, + 0, + Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, + { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, + 0, + Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, + { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, + 0, + Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, + { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, + 0, + Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, + { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, + 0, + Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, + { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, + 0, + Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, + { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, + 0, + Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, + { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, + 0, + Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, + { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, + 0, + Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, + { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, + 0, + Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, + { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, + 0, + Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, + { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, + 0, + Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, + { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, + 0, + Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, + { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, + 0, + Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, + { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, + 0, + Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, + { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, + 0, + Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, + { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, + 0, + Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, + { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, + 0, + Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, + { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, + 0, + Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, + { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, + 0, + Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, + { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, + 0, + Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, + { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, + 0, + Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, + { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, + 0, + Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, + { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, + 0, + Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, + { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, + 0, + Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, + { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, + 0, + Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, + { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, + 0, + Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, + { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, + 0, + Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, + { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, + 0, + Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, + { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, + 0, + Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, + { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, + 0, + Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, + { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, + 0, + Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, + { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, + 0, + Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, + { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, + 0, + Opcode_ae_lq56_i_encode_fns, 0, 0 }, + { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, + 0, + Opcode_ae_lq56_iu_encode_fns, 0, 0 }, + { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, + 0, + Opcode_ae_lq56_x_encode_fns, 0, 0 }, + { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, + 0, + Opcode_ae_lq56_xu_encode_fns, 0, 0 }, + { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, + 0, + Opcode_ae_lq32f_i_encode_fns, 0, 0 }, + { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, + 0, + Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, + { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, + 0, + Opcode_ae_lq32f_x_encode_fns, 0, 0 }, + { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, + 0, + Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, + { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, + 0, + Opcode_ae_sq56s_i_encode_fns, 0, 0 }, + { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, + 0, + Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, + { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, + 0, + Opcode_ae_sq56s_x_encode_fns, 0, 0 }, + { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, + 0, + Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, + { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, + 0, + Opcode_ae_sq32f_i_encode_fns, 0, 0 }, + { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, + 0, + Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, + { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, + 0, + Opcode_ae_sq32f_x_encode_fns, 0, 0 }, + { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, + 0, + Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, + { "ae_zerop48", ICLASS_ae_iclass_zerop48, + 0, + Opcode_ae_zerop48_encode_fns, 0, 0 }, + { "ae_movp48", ICLASS_ae_iclass_movp48, + 0, + Opcode_ae_movp48_encode_fns, 0, 0 }, + { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll, + 0, + Opcode_ae_selp24_ll_encode_fns, 0, 0 }, + { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh, + 0, + Opcode_ae_selp24_lh_encode_fns, 0, 0 }, + { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl, + 0, + Opcode_ae_selp24_hl_encode_fns, 0, 0 }, + { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh, + 0, + Opcode_ae_selp24_hh_encode_fns, 0, 0 }, + { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2, + 0, + Opcode_ae_movtp24x2_encode_fns, 0, 0 }, + { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2, + 0, + Opcode_ae_movfp24x2_encode_fns, 0, 0 }, + { "ae_movtp48", ICLASS_ae_iclass_movtp48, + 0, + Opcode_ae_movtp48_encode_fns, 0, 0 }, + { "ae_movfp48", ICLASS_ae_iclass_movfp48, + 0, + Opcode_ae_movfp48_encode_fns, 0, 0 }, + { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2, + 0, + Opcode_ae_movpa24x2_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l, + 0, + Opcode_ae_cvta32p24_l_encode_fns, 0, 0 }, + { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h, + 0, + Opcode_ae_cvta32p24_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_ae_iclass_truncp16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym, + 0, + Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 }, + { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym, + 0, + Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 }, + { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym, + 0, + Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym, + 0, + Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 }, + { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym, + 0, + Opcode_ae_roundsp16sym_encode_fns, 0, 0 }, + { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym, + 0, + Opcode_ae_roundsp16asym_encode_fns, 0, 0 }, + { "ae_zeroq56", ICLASS_ae_iclass_zeroq56, + 0, + Opcode_ae_zeroq56_encode_fns, 0, 0 }, + { "ae_movq56", ICLASS_ae_iclass_movq56, + 0, + Opcode_ae_movq56_encode_fns, 0, 0 }, + { "ae_movtq56", ICLASS_ae_iclass_movtq56, + 0, + Opcode_ae_movtq56_encode_fns, 0, 0 }, + { "ae_movfq56", ICLASS_ae_iclass_movfq56, + 0, + Opcode_ae_movfq56_encode_fns, 0, 0 }, + { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s, + 0, + Opcode_ae_cvtq48a32s_encode_fns, 0, 0 }, + { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l, + 0, + Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 }, + { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h, + 0, + Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 }, + { "ae_satq48s", ICLASS_ae_iclass_satq48s, + 0, + Opcode_ae_satq48s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_ae_iclass_truncq32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym, + 0, + Opcode_ae_roundsq32sym_encode_fns, 0, 0 }, + { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym, + 0, + Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, + 0, + Opcode_ae_movap24s_l_encode_fns, 0, 0 }, + { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, + 0, + Opcode_ae_movap24s_h_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_addp24", ICLASS_ae_iclass_addp24, + 0, + Opcode_ae_addp24_encode_fns, 0, 0 }, + { "ae_subp24", ICLASS_ae_iclass_subp24, + 0, + Opcode_ae_subp24_encode_fns, 0, 0 }, + { "ae_negp24", ICLASS_ae_iclass_negp24, + 0, + Opcode_ae_negp24_encode_fns, 0, 0 }, + { "ae_absp24", ICLASS_ae_iclass_absp24, + 0, + Opcode_ae_absp24_encode_fns, 0, 0 }, + { "ae_maxp24s", ICLASS_ae_iclass_maxp24s, + 0, + Opcode_ae_maxp24s_encode_fns, 0, 0 }, + { "ae_minp24s", ICLASS_ae_iclass_minp24s, + 0, + Opcode_ae_minp24s_encode_fns, 0, 0 }, + { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s, + 0, + Opcode_ae_maxbp24s_encode_fns, 0, 0 }, + { "ae_minbp24s", ICLASS_ae_iclass_minbp24s, + 0, + Opcode_ae_minbp24s_encode_fns, 0, 0 }, + { "ae_addsp24s", ICLASS_ae_iclass_addsp24s, + 0, + Opcode_ae_addsp24s_encode_fns, 0, 0 }, + { "ae_subsp24s", ICLASS_ae_iclass_subsp24s, + 0, + Opcode_ae_subsp24s_encode_fns, 0, 0 }, + { "ae_negsp24s", ICLASS_ae_iclass_negsp24s, + 0, + Opcode_ae_negsp24s_encode_fns, 0, 0 }, + { "ae_abssp24s", ICLASS_ae_iclass_abssp24s, + 0, + Opcode_ae_abssp24s_encode_fns, 0, 0 }, + { "ae_andp48", ICLASS_ae_iclass_andp48, + 0, + Opcode_ae_andp48_encode_fns, 0, 0 }, + { "ae_nandp48", ICLASS_ae_iclass_nandp48, + 0, + Opcode_ae_nandp48_encode_fns, 0, 0 }, + { "ae_orp48", ICLASS_ae_iclass_orp48, + 0, + Opcode_ae_orp48_encode_fns, 0, 0 }, + { "ae_xorp48", ICLASS_ae_iclass_xorp48, + 0, + Opcode_ae_xorp48_encode_fns, 0, 0 }, + { "ae_ltp24s", ICLASS_ae_iclass_ltp24s, + 0, + Opcode_ae_ltp24s_encode_fns, 0, 0 }, + { "ae_lep24s", ICLASS_ae_iclass_lep24s, + 0, + Opcode_ae_lep24s_encode_fns, 0, 0 }, + { "ae_eqp24", ICLASS_ae_iclass_eqp24, + 0, + Opcode_ae_eqp24_encode_fns, 0, 0 }, + { "ae_addq56", ICLASS_ae_iclass_addq56, + 0, + Opcode_ae_addq56_encode_fns, 0, 0 }, + { "ae_subq56", ICLASS_ae_iclass_subq56, + 0, + Opcode_ae_subq56_encode_fns, 0, 0 }, + { "ae_negq56", ICLASS_ae_iclass_negq56, + 0, + Opcode_ae_negq56_encode_fns, 0, 0 }, + { "ae_absq56", ICLASS_ae_iclass_absq56, + 0, + Opcode_ae_absq56_encode_fns, 0, 0 }, + { "ae_maxq56s", ICLASS_ae_iclass_maxq56s, + 0, + Opcode_ae_maxq56s_encode_fns, 0, 0 }, + { "ae_minq56s", ICLASS_ae_iclass_minq56s, + 0, + Opcode_ae_minq56s_encode_fns, 0, 0 }, + { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s, + 0, + Opcode_ae_maxbq56s_encode_fns, 0, 0 }, + { "ae_minbq56s", ICLASS_ae_iclass_minbq56s, + 0, + Opcode_ae_minbq56s_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_ae_iclass_addsq56s, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_ae_iclass_subsq56s, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_ae_iclass_negsq56s, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_ae_iclass_abssq56s, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_andq56", ICLASS_ae_iclass_andq56, + 0, + Opcode_ae_andq56_encode_fns, 0, 0 }, + { "ae_nandq56", ICLASS_ae_iclass_nandq56, + 0, + Opcode_ae_nandq56_encode_fns, 0, 0 }, + { "ae_orq56", ICLASS_ae_iclass_orq56, + 0, + Opcode_ae_orq56_encode_fns, 0, 0 }, + { "ae_xorq56", ICLASS_ae_iclass_xorq56, + 0, + Opcode_ae_xorq56_encode_fns, 0, 0 }, + { "ae_sllip24", ICLASS_ae_iclass_sllip24, + 0, + Opcode_ae_sllip24_encode_fns, 0, 0 }, + { "ae_srlip24", ICLASS_ae_iclass_srlip24, + 0, + Opcode_ae_srlip24_encode_fns, 0, 0 }, + { "ae_sraip24", ICLASS_ae_iclass_sraip24, + 0, + Opcode_ae_sraip24_encode_fns, 0, 0 }, + { "ae_sllsp24", ICLASS_ae_iclass_sllsp24, + 0, + Opcode_ae_sllsp24_encode_fns, 0, 0 }, + { "ae_srlsp24", ICLASS_ae_iclass_srlsp24, + 0, + Opcode_ae_srlsp24_encode_fns, 0, 0 }, + { "ae_srasp24", ICLASS_ae_iclass_srasp24, + 0, + Opcode_ae_srasp24_encode_fns, 0, 0 }, + { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s, + 0, + Opcode_ae_sllisp24s_encode_fns, 0, 0 }, + { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s, + 0, + Opcode_ae_sllssp24s_encode_fns, 0, 0 }, + { "ae_slliq56", ICLASS_ae_iclass_slliq56, + 0, + Opcode_ae_slliq56_encode_fns, 0, 0 }, + { "ae_srliq56", ICLASS_ae_iclass_srliq56, + 0, + Opcode_ae_srliq56_encode_fns, 0, 0 }, + { "ae_sraiq56", ICLASS_ae_iclass_sraiq56, + 0, + Opcode_ae_sraiq56_encode_fns, 0, 0 }, + { "ae_sllsq56", ICLASS_ae_iclass_sllsq56, + 0, + Opcode_ae_sllsq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_ae_iclass_srlsq56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_ae_iclass_srasq56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_sllaq56", ICLASS_ae_iclass_sllaq56, + 0, + Opcode_ae_sllaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_ae_iclass_srlaq56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_ae_iclass_sraaq56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s, + 0, + Opcode_ae_sllisq56s_encode_fns, 0, 0 }, + { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s, + 0, + Opcode_ae_sllssq56s_encode_fns, 0, 0 }, + { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s, + 0, + Opcode_ae_sllasq56s_encode_fns, 0, 0 }, + { "ae_ltq56s", ICLASS_ae_iclass_ltq56s, + 0, + Opcode_ae_ltq56s_encode_fns, 0, 0 }, + { "ae_leq56s", ICLASS_ae_iclass_leq56s, + 0, + Opcode_ae_leq56s_encode_fns, 0, 0 }, + { "ae_eqq56", ICLASS_ae_iclass_eqq56, + 0, + Opcode_ae_eqq56_encode_fns, 0, 0 }, + { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s, + 0, + Opcode_ae_nsaq56s_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll, + 0, + Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll, + 0, + Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 }, + { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll, + 0, + Opcode_ae_mulp24s_ll_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh, + 0, + Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh, + 0, + Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 }, + { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh, + 0, + Opcode_ae_mulp24s_lh_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl, + 0, + Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl, + 0, + Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 }, + { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl, + 0, + Opcode_ae_mulp24s_hl_encode_fns, 0, 0 }, + { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh, + 0, + Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh, + 0, + Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 }, + { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh, + 0, + Opcode_ae_mulp24s_hh_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll, + 0, + Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll, + 0, + Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 }, + { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll, + 0, + Opcode_ae_mulap24s_ll_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh, + 0, + Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh, + 0, + Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 }, + { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh, + 0, + Opcode_ae_mulap24s_lh_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl, + 0, + Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl, + 0, + Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 }, + { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl, + 0, + Opcode_ae_mulap24s_hl_encode_fns, 0, 0 }, + { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh, + 0, + Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh, + 0, + Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 }, + { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh, + 0, + Opcode_ae_mulap24s_hh_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll, + 0, + Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll, + 0, + Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 }, + { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll, + 0, + Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh, + 0, + Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh, + 0, + Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 }, + { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh, + 0, + Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl, + 0, + Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 }, + { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl, + 0, + Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 }, + { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl, + 0, + Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 }, + { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh, + 0, + Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh, + 0, + Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 }, + { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh, + 0, + Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll, + 0, + Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll, + 0, + Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh, + 0, + Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh, + 0, + Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl, + 0, + Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl, + 0, + Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh, + 0, + Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh, + 0, + Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll, + 0, + Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll, + 0, + Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh, + 0, + Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh, + 0, + Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl, + 0, + Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl, + 0, + Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 }, + { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh, + 0, + Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh, + 0, + Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 }, + { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l, + 0, + Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h, + 0, + Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l, + 0, + Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h, + 0, + Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h, + 0, + Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h, + 0, + Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l, + 0, + Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h, + 0, + Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l, + 0, + Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h, + 0, + Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h, + 0, + Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h, + 0, + Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l, + 0, + Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h, + 0, + Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l, + 0, + Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h, + 0, + Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h, + 0, + Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h, + 0, + Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll, + 0, + Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll, + 0, + Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll, + 0, + Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll, + 0, + Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh, + 0, + Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh, + 0, + Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh, + 0, + Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh, + 0, + Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh, + 0, + Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh, + 0, + Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh, + 0, + Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh, + 0, + Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll, + 0, + Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll, + 0, + Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll, + 0, + Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll, + 0, + Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh, + 0, + Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh, + 0, + Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh, + 0, + Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh, + 0, + Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh, + 0, + Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh, + 0, + Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh, + 0, + Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh, + 0, + Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll, + 0, + Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll, + 0, + Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll, + 0, + Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll, + 0, + Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh, + 0, + Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh, + 0, + Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh, + 0, + Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh, + 0, + Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh, + 0, + Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh, + 0, + Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, + 0, + Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, + 0, + Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, + 0, + Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, + 0, + Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, + 0, + Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, + 0, + Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, + 0, + Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, + 0, + Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, + 0, + Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, + 0, + Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, + 0, + Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, + 0, + Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, + { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, + 0, + Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, + 0, + Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, + { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, + 0, + Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, + 0, + Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, + 0, + Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, + 0, + Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, + 0, + Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, + 0, + Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, + 0, + Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, + 0, + Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, + 0, + Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, + 0, + Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, + 0, + Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, + 0, + Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, + 0, + Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, + 0, + Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, + 0, + Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, + 0, + Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, + 0, + Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, + 0, + Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, + 0, + Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, + 0, + Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, + 0, + Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, + 0, + Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, + 0, + Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, + 0, + Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, + 0, + Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, + 0, + Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, + 0, + Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, + 0, + Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, + 0, + Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, + 0, + Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, + 0, + Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, + 0, + Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_ae_iclass_sha32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, + 0, + Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, + 0, + Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, + 0, + Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldsht", ICLASS_ae_iclass_vldsht, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_ae_iclass_lb, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_ae_iclass_lbi, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_ae_iclass_lbk, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_ae_iclass_lbki, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_db", ICLASS_ae_iclass_db, + 0, + Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_ae_iclass_dbi, + 0, + Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, + { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, + 0, + Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, + 0, + Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_ae_iclass_sb, + 0, + Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_ae_iclass_sbi, + 0, + Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_ae_iclass_vles16c, + 0, + Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_ae_iclass_sbf, + 0, + Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_WSR_PTEVADDR, + OPCODE_RSR_PTEVADDR, + OPCODE_XSR_PTEVADDR, + OPCODE_RSR_RASID, + OPCODE_WSR_RASID, + OPCODE_XSR_RASID, + OPCODE_RSR_ITLBCFG, + OPCODE_WSR_ITLBCFG, + OPCODE_XSR_ITLBCFG, + OPCODE_RSR_DTLBCFG, + OPCODE_WSR_DTLBCFG, + OPCODE_XSR_DTLBCFG, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_LDPTE, + OPCODE_HWWITLBA, + OPCODE_HWWDTLBA, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_SD_NO, + OPCODE_WUR_AE_SD_NO, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_AE_LP16F_I, + OPCODE_AE_LP16F_IU, + OPCODE_AE_LP16F_X, + OPCODE_AE_LP16F_XU, + OPCODE_AE_LP24_I, + OPCODE_AE_LP24_IU, + OPCODE_AE_LP24_X, + OPCODE_AE_LP24_XU, + OPCODE_AE_LP24F_I, + OPCODE_AE_LP24F_IU, + OPCODE_AE_LP24F_X, + OPCODE_AE_LP24F_XU, + OPCODE_AE_LP16X2F_I, + OPCODE_AE_LP16X2F_IU, + OPCODE_AE_LP16X2F_X, + OPCODE_AE_LP16X2F_XU, + OPCODE_AE_LP24X2F_I, + OPCODE_AE_LP24X2F_IU, + OPCODE_AE_LP24X2F_X, + OPCODE_AE_LP24X2F_XU, + OPCODE_AE_LP24X2_I, + OPCODE_AE_LP24X2_IU, + OPCODE_AE_LP24X2_X, + OPCODE_AE_LP24X2_XU, + OPCODE_AE_SP16X2F_I, + OPCODE_AE_SP16X2F_IU, + OPCODE_AE_SP16X2F_X, + OPCODE_AE_SP16X2F_XU, + OPCODE_AE_SP24X2S_I, + OPCODE_AE_SP24X2S_IU, + OPCODE_AE_SP24X2S_X, + OPCODE_AE_SP24X2S_XU, + OPCODE_AE_SP24X2F_I, + OPCODE_AE_SP24X2F_IU, + OPCODE_AE_SP24X2F_X, + OPCODE_AE_SP24X2F_XU, + OPCODE_AE_SP16F_L_I, + OPCODE_AE_SP16F_L_IU, + OPCODE_AE_SP16F_L_X, + OPCODE_AE_SP16F_L_XU, + OPCODE_AE_SP24S_L_I, + OPCODE_AE_SP24S_L_IU, + OPCODE_AE_SP24S_L_X, + OPCODE_AE_SP24S_L_XU, + OPCODE_AE_SP24F_L_I, + OPCODE_AE_SP24F_L_IU, + OPCODE_AE_SP24F_L_X, + OPCODE_AE_SP24F_L_XU, + OPCODE_AE_LQ56_I, + OPCODE_AE_LQ56_IU, + OPCODE_AE_LQ56_X, + OPCODE_AE_LQ56_XU, + OPCODE_AE_LQ32F_I, + OPCODE_AE_LQ32F_IU, + OPCODE_AE_LQ32F_X, + OPCODE_AE_LQ32F_XU, + OPCODE_AE_SQ56S_I, + OPCODE_AE_SQ56S_IU, + OPCODE_AE_SQ56S_X, + OPCODE_AE_SQ56S_XU, + OPCODE_AE_SQ32F_I, + OPCODE_AE_SQ32F_IU, + OPCODE_AE_SQ32F_X, + OPCODE_AE_SQ32F_XU, + OPCODE_AE_ZEROP48, + OPCODE_AE_MOVP48, + OPCODE_AE_SELP24_LL, + OPCODE_AE_SELP24_LH, + OPCODE_AE_SELP24_HL, + OPCODE_AE_SELP24_HH, + OPCODE_AE_MOVTP24X2, + OPCODE_AE_MOVFP24X2, + OPCODE_AE_MOVTP48, + OPCODE_AE_MOVFP48, + OPCODE_AE_MOVPA24X2, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_CVTA32P24_L, + OPCODE_AE_CVTA32P24_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUNDSP24Q48SYM, + OPCODE_AE_ROUNDSP24Q48ASYM, + OPCODE_AE_ROUNDSP16Q48SYM, + OPCODE_AE_ROUNDSP16Q48ASYM, + OPCODE_AE_ROUNDSP16SYM, + OPCODE_AE_ROUNDSP16ASYM, + OPCODE_AE_ZEROQ56, + OPCODE_AE_MOVQ56, + OPCODE_AE_MOVTQ56, + OPCODE_AE_MOVFQ56, + OPCODE_AE_CVTQ48A32S, + OPCODE_AE_CVTQ48P24S_L, + OPCODE_AE_CVTQ48P24S_H, + OPCODE_AE_SATQ48S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_ROUNDSQ32SYM, + OPCODE_AE_ROUNDSQ32ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAP24S_L, + OPCODE_AE_MOVAP24S_H, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADDP24, + OPCODE_AE_SUBP24, + OPCODE_AE_NEGP24, + OPCODE_AE_ABSP24, + OPCODE_AE_MAXP24S, + OPCODE_AE_MINP24S, + OPCODE_AE_MAXBP24S, + OPCODE_AE_MINBP24S, + OPCODE_AE_ADDSP24S, + OPCODE_AE_SUBSP24S, + OPCODE_AE_NEGSP24S, + OPCODE_AE_ABSSP24S, + OPCODE_AE_ANDP48, + OPCODE_AE_NANDP48, + OPCODE_AE_ORP48, + OPCODE_AE_XORP48, + OPCODE_AE_LTP24S, + OPCODE_AE_LEP24S, + OPCODE_AE_EQP24, + OPCODE_AE_ADDQ56, + OPCODE_AE_SUBQ56, + OPCODE_AE_NEGQ56, + OPCODE_AE_ABSQ56, + OPCODE_AE_MAXQ56S, + OPCODE_AE_MINQ56S, + OPCODE_AE_MAXBQ56S, + OPCODE_AE_MINBQ56S, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_ANDQ56, + OPCODE_AE_NANDQ56, + OPCODE_AE_ORQ56, + OPCODE_AE_XORQ56, + OPCODE_AE_SLLIP24, + OPCODE_AE_SRLIP24, + OPCODE_AE_SRAIP24, + OPCODE_AE_SLLSP24, + OPCODE_AE_SRLSP24, + OPCODE_AE_SRASP24, + OPCODE_AE_SLLISP24S, + OPCODE_AE_SLLSSP24S, + OPCODE_AE_SLLIQ56, + OPCODE_AE_SRLIQ56, + OPCODE_AE_SRAIQ56, + OPCODE_AE_SLLSQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLLAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLLISQ56S, + OPCODE_AE_SLLSSQ56S, + OPCODE_AE_SLLASQ56S, + OPCODE_AE_LTQ56S, + OPCODE_AE_LEQ56S, + OPCODE_AE_EQQ56, + OPCODE_AE_NSAQ56S, + OPCODE_AE_MULFS32P16S_LL, + OPCODE_AE_MULFP24S_LL, + OPCODE_AE_MULP24S_LL, + OPCODE_AE_MULFS32P16S_LH, + OPCODE_AE_MULFP24S_LH, + OPCODE_AE_MULP24S_LH, + OPCODE_AE_MULFS32P16S_HL, + OPCODE_AE_MULFP24S_HL, + OPCODE_AE_MULP24S_HL, + OPCODE_AE_MULFS32P16S_HH, + OPCODE_AE_MULFP24S_HH, + OPCODE_AE_MULP24S_HH, + OPCODE_AE_MULAFS32P16S_LL, + OPCODE_AE_MULAFP24S_LL, + OPCODE_AE_MULAP24S_LL, + OPCODE_AE_MULAFS32P16S_LH, + OPCODE_AE_MULAFP24S_LH, + OPCODE_AE_MULAP24S_LH, + OPCODE_AE_MULAFS32P16S_HL, + OPCODE_AE_MULAFP24S_HL, + OPCODE_AE_MULAP24S_HL, + OPCODE_AE_MULAFS32P16S_HH, + OPCODE_AE_MULAFP24S_HH, + OPCODE_AE_MULAP24S_HH, + OPCODE_AE_MULSFS32P16S_LL, + OPCODE_AE_MULSFP24S_LL, + OPCODE_AE_MULSP24S_LL, + OPCODE_AE_MULSFS32P16S_LH, + OPCODE_AE_MULSFP24S_LH, + OPCODE_AE_MULSP24S_LH, + OPCODE_AE_MULSFS32P16S_HL, + OPCODE_AE_MULSFP24S_HL, + OPCODE_AE_MULSP24S_HL, + OPCODE_AE_MULSFS32P16S_HH, + OPCODE_AE_MULSFP24S_HH, + OPCODE_AE_MULSP24S_HH, + OPCODE_AE_MULAFS56P24S_LL, + OPCODE_AE_MULAS56P24S_LL, + OPCODE_AE_MULAFS56P24S_LH, + OPCODE_AE_MULAS56P24S_LH, + OPCODE_AE_MULAFS56P24S_HL, + OPCODE_AE_MULAS56P24S_HL, + OPCODE_AE_MULAFS56P24S_HH, + OPCODE_AE_MULAS56P24S_HH, + OPCODE_AE_MULSFS56P24S_LL, + OPCODE_AE_MULSS56P24S_LL, + OPCODE_AE_MULSFS56P24S_LH, + OPCODE_AE_MULSS56P24S_LH, + OPCODE_AE_MULSFS56P24S_HL, + OPCODE_AE_MULSS56P24S_HL, + OPCODE_AE_MULSFS56P24S_HH, + OPCODE_AE_MULSS56P24S_HH, + OPCODE_AE_MULFQ32SP16S_L, + OPCODE_AE_MULFQ32SP16S_H, + OPCODE_AE_MULFQ32SP16U_L, + OPCODE_AE_MULFQ32SP16U_H, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16S_H, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULQ32SP16U_H, + OPCODE_AE_MULAFQ32SP16S_L, + OPCODE_AE_MULAFQ32SP16S_H, + OPCODE_AE_MULAFQ32SP16U_L, + OPCODE_AE_MULAFQ32SP16U_H, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16S_H, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULAQ32SP16U_H, + OPCODE_AE_MULSFQ32SP16S_L, + OPCODE_AE_MULSFQ32SP16S_H, + OPCODE_AE_MULSFQ32SP16U_L, + OPCODE_AE_MULSFQ32SP16U_H, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16S_H, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULSQ32SP16U_H, + OPCODE_AE_MULZAAQ32SP16S_LL, + OPCODE_AE_MULZAAFQ32SP16S_LL, + OPCODE_AE_MULZAAQ32SP16U_LL, + OPCODE_AE_MULZAAFQ32SP16U_LL, + OPCODE_AE_MULZAAQ32SP16S_HH, + OPCODE_AE_MULZAAFQ32SP16S_HH, + OPCODE_AE_MULZAAQ32SP16U_HH, + OPCODE_AE_MULZAAFQ32SP16U_HH, + OPCODE_AE_MULZAAQ32SP16S_LH, + OPCODE_AE_MULZAAFQ32SP16S_LH, + OPCODE_AE_MULZAAQ32SP16U_LH, + OPCODE_AE_MULZAAFQ32SP16U_LH, + OPCODE_AE_MULZASQ32SP16S_LL, + OPCODE_AE_MULZASFQ32SP16S_LL, + OPCODE_AE_MULZASQ32SP16U_LL, + OPCODE_AE_MULZASFQ32SP16U_LL, + OPCODE_AE_MULZASQ32SP16S_HH, + OPCODE_AE_MULZASFQ32SP16S_HH, + OPCODE_AE_MULZASQ32SP16U_HH, + OPCODE_AE_MULZASFQ32SP16U_HH, + OPCODE_AE_MULZASQ32SP16S_LH, + OPCODE_AE_MULZASFQ32SP16S_LH, + OPCODE_AE_MULZASQ32SP16U_LH, + OPCODE_AE_MULZASFQ32SP16U_LH, + OPCODE_AE_MULZSAQ32SP16S_LL, + OPCODE_AE_MULZSAFQ32SP16S_LL, + OPCODE_AE_MULZSAQ32SP16U_LL, + OPCODE_AE_MULZSAFQ32SP16U_LL, + OPCODE_AE_MULZSAQ32SP16S_HH, + OPCODE_AE_MULZSAFQ32SP16S_HH, + OPCODE_AE_MULZSAQ32SP16U_HH, + OPCODE_AE_MULZSAFQ32SP16U_HH, + OPCODE_AE_MULZSAQ32SP16S_LH, + OPCODE_AE_MULZSAFQ32SP16S_LH, + OPCODE_AE_MULZSAQ32SP16U_LH, + OPCODE_AE_MULZSAFQ32SP16U_LH, + OPCODE_AE_MULZSSQ32SP16S_LL, + OPCODE_AE_MULZSSFQ32SP16S_LL, + OPCODE_AE_MULZSSQ32SP16U_LL, + OPCODE_AE_MULZSSFQ32SP16U_LL, + OPCODE_AE_MULZSSQ32SP16S_HH, + OPCODE_AE_MULZSSFQ32SP16S_HH, + OPCODE_AE_MULZSSQ32SP16U_HH, + OPCODE_AE_MULZSSFQ32SP16U_HH, + OPCODE_AE_MULZSSQ32SP16S_LH, + OPCODE_AE_MULZSSFQ32SP16S_LH, + OPCODE_AE_MULZSSQ32SP16U_LH, + OPCODE_AE_MULZSSFQ32SP16U_LH, + OPCODE_AE_MULZAAFP24S_HH_LL, + OPCODE_AE_MULZAAP24S_HH_LL, + OPCODE_AE_MULZAAFP24S_HL_LH, + OPCODE_AE_MULZAAP24S_HL_LH, + OPCODE_AE_MULZASFP24S_HH_LL, + OPCODE_AE_MULZASP24S_HH_LL, + OPCODE_AE_MULZASFP24S_HL_LH, + OPCODE_AE_MULZASP24S_HL_LH, + OPCODE_AE_MULZSAFP24S_HH_LL, + OPCODE_AE_MULZSAP24S_HH_LL, + OPCODE_AE_MULZSAFP24S_HL_LH, + OPCODE_AE_MULZSAP24S_HL_LH, + OPCODE_AE_MULZSSFP24S_HH_LL, + OPCODE_AE_MULZSSP24S_HH_LL, + OPCODE_AE_MULZSSFP24S_HL_LH, + OPCODE_AE_MULZSSP24S_HL_LH, + OPCODE_AE_MULAAFP24S_HH_LL, + OPCODE_AE_MULAAP24S_HH_LL, + OPCODE_AE_MULAAFP24S_HL_LH, + OPCODE_AE_MULAAP24S_HL_LH, + OPCODE_AE_MULASFP24S_HH_LL, + OPCODE_AE_MULASP24S_HH_LL, + OPCODE_AE_MULASFP24S_HL_LH, + OPCODE_AE_MULASP24S_HL_LH, + OPCODE_AE_MULSAFP24S_HH_LL, + OPCODE_AE_MULSAP24S_HH_LL, + OPCODE_AE_MULSAFP24S_HL_LH, + OPCODE_AE_MULSAP24S_HL_LH, + OPCODE_AE_MULSSFP24S_HH_LL, + OPCODE_AE_MULSSP24S_HH_LL, + OPCODE_AE_MULSSFP24S_HL_LH, + OPCODE_AE_MULSSP24S_HL_LH, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_HWWITLBA; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_HWWDTLBA; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_XSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_XSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_XSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_LDPTE; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_RSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_RSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_WSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_WSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_SD_NO; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_SD_NO; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_I; + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_X; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_I; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_X; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_XU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_CVTQ48A32S; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_ae_s3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVP48; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVPA24X2; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_I; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_X; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_TRUNCA32Q48; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_I; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_X; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_NSAQ56S; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_XU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_XU; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRAIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLISQ56S; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SHA32; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL32T; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLAQ56; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL16T; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LBK; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRAAQ56; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL32T; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLASQ56S; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL16T; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVTQ56; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVFQ56; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SBI; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SAR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DB; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SB; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITPTR; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITSUSED; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_r_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_r_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_VLDSHT; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLES16C; + if (Field_r_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SBF; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLDL16C; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSQ56; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LB; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLSQ56; + if (Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRASQ56; + if (Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSSQ56S; + if (Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVQ56; + if (Field_s_Slot_inst_get (insn) == 8 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_s_Slot_inst_get (insn) == 9 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_s_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITPTR; + if (Field_s_Slot_inst_get (insn) == 11 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITSUSED; + if (Field_s_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_s_Slot_inst_get (insn) == 13 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_s_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_s_Slot_inst_get (insn) == 15 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBKI; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DBI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBI; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_J; + if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_EXTUI; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BGEZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BLTZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BEQZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVTQ56; + if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && + Field_ae_r20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_I; + if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_IU; + if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_X; + if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16F_XU; + if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_I; + if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_IU; + if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_XU; + if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP16X2F_X; + if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_I; + if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_IU; + if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_X; + if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24_XU; + if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_I; + if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_XU; + if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_IU; + if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_I; + if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_IU; + if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_X; + if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24F_X; + if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2_XU; + if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_I; + if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_X; + if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_IU; + if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LP24X2F_XU; + if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVPA24X2; + if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_I; + if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_IU; + if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_X; + if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_X; + if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_XU; + if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_I; + if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_IU; + if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16F_L_XU; + if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_X; + if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24F_L_XU; + if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_IU; + if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_I; + if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_X; + if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24S_L_XU; + if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_I; + if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_I; + if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_IU; + if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_X; + if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_IU; + if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2F_XU; + if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_X; + if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_XU; + if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP24X2S_I; + if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_I; + if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ32F_IU; + if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_I; + if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_X; + if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_XU; + if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_I; + if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ32F_IU; + if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_IU; + if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LQ56_X; + if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ48A32S; + if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSL; + if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LQ56_XU; + if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBCI; + if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBSI; + if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_s_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANY8; + if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SSAI; + if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SP16X2F_IU; + if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_I; + if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_IU; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLISQ56S; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf321_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVP48; + if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf353_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANY4; + if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf321_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVQ56; + if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf321_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLLSSQ56S; + if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRASQ56; + if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLSQ56; + if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLLSQ56; + if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_X; + if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SQ56S_XU; + if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32P24_H; + if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32P24_L; + if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVAP24S_H; + if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVAP24S_L; + if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf353_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NSAQ56S; + if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32Q48; + if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BT; + if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_ae_s20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BLTUI; + if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVFQ56; + if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLAQ56; + if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLASQ56S; + if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SLL; + if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf357_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAAQ56; + if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLAQ56; + if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SQ32F_XU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_CLAMPS; + if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MINU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVEQZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF; + if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVGEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SEXT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVNEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRLI; + if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XOR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_r32_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SQ32F_X; + if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_L32R; + if (Field_r_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNE; + if (Field_r_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNONE; + if (Field_r_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16SI; + if (Field_r_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L8UI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16UI; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BALL; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S16I; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BANY; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S32I; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBC; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_ae_slot0_get (insn) == 8 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDMI; + if (Field_r_Slot_ae_slot0_get (insn) == 9 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBS; + if (Field_r_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BEQ; + if (Field_r_Slot_ae_slot0_get (insn) == 11 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGEU; + if (Field_r_Slot_ae_slot0_get (insn) == 12 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGE; + if (Field_r_Slot_ae_slot0_get (insn) == 13 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_ae_slot0_get (insn) == 14 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLTU; + if (Field_r_Slot_ae_slot0_get (insn) == 15 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BNALL; + if (Field_t_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BEQI; + if (Field_t_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEI; + if (Field_t_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEUI; + if (Field_t_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BNEI; + if (Field_t_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BLTI; + if (Field_t_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_r_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BF; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_NEGSP24S; + if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ABSSP24S; + if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_NEGP24; + if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MAXBQ56S; + if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MINBQ56S; + if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ae_r32_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_EQQ56; + if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ADDSQ56S; + if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ANDQ56; + if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MAXQ56S; + if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ORQ56; + if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_MINQ56S; + if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_SUBQ56; + if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_SUBSQ56S; + if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_XORQ56; + if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_NANDQ56; + if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ABSQ56; + if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_NEGSQ56S; + if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf338_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_SATQ48S; + if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LTQ56S; + if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_NEGQ56; + if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LEQ56S; + if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && + Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDQ56; + if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAFP24S_HH_LL; + if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAFP24S_HL_LH; + if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAP24S_HH_LL; + if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf12_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_SLLISP24S; + if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_HL; + if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAAP24S_HL_LH; + if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_LH; + if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS32P16S_LL; + if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_HH; + if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_HH; + if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_HL; + if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_LH; + if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_HH; + if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFS56P24S_LL; + if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_HL; + if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_LH; + if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAP24S_LL; + if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_HL; + if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_HH; + if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_HL; + if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASFP24S_HH_LL; + if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_LH; + if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASFP24S_HL_LH; + if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASP24S_HH_LL; + if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULASP24S_HL_LH; + if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAS56P24S_LL; + if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_HH; + if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_HL; + if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_LL; + if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFP24S_LH; + if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_HH; + if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_HL; + if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_LH; + if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_LH; + if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULFS32P16S_LL; + if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_HH; + if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAFP24S_HH_LL; + if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_HL; + if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAFP24S_HL_LH; + if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAP24S_HH_LL; + if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSAP24S_HL_LH; + if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_LH; + if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_HH; + if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_HL; + if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_LL; + if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFP24S_LH; + if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_HH; + if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_HL; + if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_LH; + if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULP24S_LL; + if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS32P16S_LL; + if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_HH; + if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_LL; + if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_HL; + if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_HH; + if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_HL; + if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_LH; + if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSFS56P24S_LH; + if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSP24S_LL; + if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_HH; + if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_LH; + if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_HL; + if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSS56P24S_LL; + if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSFP24S_HH_LL; + if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSFP24S_HL_LH; + if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULAFP24S_LL; + if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSP24S_HH_LL; + if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULSSP24S_HL_LH; + if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASFP24S_HH_LL; + if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZAAFP24S_HH_LL; + if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASFP24S_HL_LH; + if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASP24S_HH_LL; + if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZASP24S_HL_LH; + if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZAAFP24S_HL_LH; + if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAFP24S_HH_LL; + if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAFP24S_HL_LH; + if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAP24S_HL_LH; + if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSAP24S_HH_LL; + if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSFP24S_HH_LL; + if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSFP24S_HL_LH; + if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_MULZSSP24S_HH_LL; + if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZAAP24S_HH_LL; + if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZSSP24S_HL_LH; + if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULZAAP24S_HL_LH; + if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && + Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULAFS32P16S_HH; + if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MAXBP24S; + if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MINBP24S; + if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVFP48; + if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVTP48; + if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ADDP24; + if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ANDP48; + if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MAXP24S; + if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MINP24S; + if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ADDSP24S; + if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_NANDP48; + if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ORP48; + if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_HL; + if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_HH; + if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_LH; + if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SELP24_LL; + if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SUBP24; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLIP24; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRAIP24; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRLIP24; + if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16S_L; + if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16U_H; + if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16U_L; + if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_H; + if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_H; + if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16S_H; + if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16S_L; + if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16U_H; + if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULFQ32SP16U_L; + if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_H; + if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16U_H; + if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16S_H; + if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULAFQ32SP16S_H; + if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16S_L; + if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16U_H; + if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MULSFQ32SP16U_L; + if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_CVTQ48P24S_H; + if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ZEROQ56; + if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r10_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_CVTQ48P24S_L; + if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVQ56; + if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSQ32ASYM; + if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSQ32SYM; + if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf340_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCQ32; + if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULSQ32SP16S_H; + if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVP48; + if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16ASYM; + if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16SYM; + if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRASP24; + if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLSP24; + if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRLSP24; + if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP16; + if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ZEROP48; + if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r10_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_SLLSSP24S; + if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16Q48ASYM; + if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_ROUNDSP16Q48SYM; + if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP24Q48ASYM; + if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf340_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ROUNDSP24Q48SYM; + if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MULSQ32SP16U_H; + if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_EQP24; + if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LEP24S; + if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf208_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LTP24S; + if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ftsf347_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MOVFP24X2; + if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_s20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_MOVTP24X2; + if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SUBSP24S; + if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_XORP48; + if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && + Field_ae_r20_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ABSP24; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LL; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x80000000) >> 31); + slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); +} + +static void +Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); + insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); +} + +static void +Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); +} + +static void +Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_ae_r3_Slot_inst_get, + Field_ae_s_non_samt_Slot_inst_get, + Field_ae_s3_Slot_inst_get, + Field_ae_r32_Slot_inst_get, + Field_ae_samt_s_t_Slot_inst_get, + Field_ae_r20_Slot_inst_get, + Field_ae_r10_Slot_inst_get, + Field_ae_s20_Slot_inst_get, + Field_ae_fld_ohba_Slot_inst_get, + Field_ae_fld_ohba2_Slot_inst_get, + 0, + Field_ftsf12_Slot_inst_get, + Field_ftsf13_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_ae_r3_Slot_inst_set, + Field_ae_s_non_samt_Slot_inst_set, + Field_ae_s3_Slot_inst_set, + Field_ae_r32_Slot_inst_set, + Field_ae_samt_s_t_Slot_inst_set, + Field_ae_r20_Slot_inst_set, + Field_ae_r10_Slot_inst_set, + Field_ae_s20_Slot_inst_set, + Field_ae_fld_ohba_Slot_inst_set, + Field_ae_fld_ohba2_Slot_inst_set, + 0, + Field_ftsf12_Slot_inst_set, + Field_ftsf13_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot1_get, + 0, + Field_ae_r20_Slot_ae_slot1_get, + Field_ae_r10_Slot_ae_slot1_get, + Field_ae_s20_Slot_ae_slot1_get, + 0, + 0, + Field_op0_s3_Slot_ae_slot1_get, + Field_ftsf12_Slot_ae_slot1_get, + Field_ftsf13_Slot_ae_slot1_get, + Field_ftsf14_Slot_ae_slot1_get, + Field_ftsf21ae_slot1_Slot_ae_slot1_get, + Field_ftsf22ae_slot1_Slot_ae_slot1_get, + Field_ftsf23ae_slot1_Slot_ae_slot1_get, + Field_ftsf24ae_slot1_Slot_ae_slot1_get, + Field_ftsf25ae_slot1_Slot_ae_slot1_get, + Field_ftsf26ae_slot1_Slot_ae_slot1_get, + Field_ftsf27ae_slot1_Slot_ae_slot1_get, + Field_ftsf28ae_slot1_Slot_ae_slot1_get, + Field_ftsf29ae_slot1_Slot_ae_slot1_get, + Field_ftsf30ae_slot1_Slot_ae_slot1_get, + Field_ftsf31ae_slot1_Slot_ae_slot1_get, + Field_ftsf32ae_slot1_Slot_ae_slot1_get, + Field_ftsf33ae_slot1_Slot_ae_slot1_get, + Field_ftsf34ae_slot1_Slot_ae_slot1_get, + Field_ftsf35ae_slot1_Slot_ae_slot1_get, + Field_ftsf36ae_slot1_Slot_ae_slot1_get, + Field_ftsf37ae_slot1_Slot_ae_slot1_get, + Field_ftsf38ae_slot1_Slot_ae_slot1_get, + Field_ftsf39ae_slot1_Slot_ae_slot1_get, + Field_ftsf40ae_slot1_Slot_ae_slot1_get, + Field_ftsf41ae_slot1_Slot_ae_slot1_get, + Field_ftsf42ae_slot1_Slot_ae_slot1_get, + Field_ftsf43ae_slot1_Slot_ae_slot1_get, + Field_ftsf44ae_slot1_Slot_ae_slot1_get, + Field_ftsf45ae_slot1_Slot_ae_slot1_get, + Field_ftsf46ae_slot1_Slot_ae_slot1_get, + Field_ftsf47ae_slot1_Slot_ae_slot1_get, + Field_ftsf48ae_slot1_Slot_ae_slot1_get, + Field_ftsf49ae_slot1_Slot_ae_slot1_get, + Field_ftsf50ae_slot1_Slot_ae_slot1_get, + Field_ftsf51ae_slot1_Slot_ae_slot1_get, + Field_ftsf52ae_slot1_Slot_ae_slot1_get, + Field_ftsf53ae_slot1_Slot_ae_slot1_get, + Field_ftsf54ae_slot1_Slot_ae_slot1_get, + Field_ftsf55ae_slot1_Slot_ae_slot1_get, + Field_ftsf56ae_slot1_Slot_ae_slot1_get, + Field_ftsf57ae_slot1_Slot_ae_slot1_get, + Field_ftsf58ae_slot1_Slot_ae_slot1_get, + Field_ftsf59ae_slot1_Slot_ae_slot1_get, + Field_ftsf60ae_slot1_Slot_ae_slot1_get, + Field_ftsf61ae_slot1_Slot_ae_slot1_get, + Field_ftsf63ae_slot1_Slot_ae_slot1_get, + Field_ftsf64ae_slot1_Slot_ae_slot1_get, + Field_ftsf66ae_slot1_Slot_ae_slot1_get, + Field_ftsf67ae_slot1_Slot_ae_slot1_get, + Field_ftsf69ae_slot1_Slot_ae_slot1_get, + Field_ftsf71ae_slot1_Slot_ae_slot1_get, + Field_ftsf72ae_slot1_Slot_ae_slot1_get, + Field_ftsf73ae_slot1_Slot_ae_slot1_get, + Field_ftsf75ae_slot1_Slot_ae_slot1_get, + Field_ftsf76ae_slot1_Slot_ae_slot1_get, + Field_ftsf77ae_slot1_Slot_ae_slot1_get, + Field_ftsf78ae_slot1_Slot_ae_slot1_get, + Field_ftsf79ae_slot1_Slot_ae_slot1_get, + Field_ftsf80ae_slot1_Slot_ae_slot1_get, + Field_ftsf81ae_slot1_Slot_ae_slot1_get, + Field_ftsf82ae_slot1_Slot_ae_slot1_get, + Field_ftsf84ae_slot1_Slot_ae_slot1_get, + Field_ftsf86ae_slot1_Slot_ae_slot1_get, + Field_ftsf87ae_slot1_Slot_ae_slot1_get, + Field_ftsf88ae_slot1_Slot_ae_slot1_get, + Field_ftsf89ae_slot1_Slot_ae_slot1_get, + Field_ftsf90ae_slot1_Slot_ae_slot1_get, + Field_ftsf91ae_slot1_Slot_ae_slot1_get, + Field_ftsf92ae_slot1_Slot_ae_slot1_get, + Field_ftsf94ae_slot1_Slot_ae_slot1_get, + Field_ftsf96ae_slot1_Slot_ae_slot1_get, + Field_ftsf97ae_slot1_Slot_ae_slot1_get, + Field_ftsf98ae_slot1_Slot_ae_slot1_get, + Field_ftsf99ae_slot1_Slot_ae_slot1_get, + Field_ftsf100ae_slot1_Slot_ae_slot1_get, + Field_ftsf101ae_slot1_Slot_ae_slot1_get, + Field_ftsf103ae_slot1_Slot_ae_slot1_get, + Field_ftsf104ae_slot1_Slot_ae_slot1_get, + Field_ftsf105ae_slot1_Slot_ae_slot1_get, + Field_ftsf106ae_slot1_Slot_ae_slot1_get, + Field_ftsf107ae_slot1_Slot_ae_slot1_get, + Field_ftsf108ae_slot1_Slot_ae_slot1_get, + Field_ftsf109ae_slot1_Slot_ae_slot1_get, + Field_ftsf110ae_slot1_Slot_ae_slot1_get, + Field_ftsf111ae_slot1_Slot_ae_slot1_get, + Field_ftsf112ae_slot1_Slot_ae_slot1_get, + Field_ftsf113ae_slot1_Slot_ae_slot1_get, + Field_ftsf114ae_slot1_Slot_ae_slot1_get, + Field_ftsf115ae_slot1_Slot_ae_slot1_get, + Field_ftsf116ae_slot1_Slot_ae_slot1_get, + Field_ftsf118ae_slot1_Slot_ae_slot1_get, + Field_ftsf119ae_slot1_Slot_ae_slot1_get, + Field_ftsf120ae_slot1_Slot_ae_slot1_get, + Field_ftsf122ae_slot1_Slot_ae_slot1_get, + Field_ftsf124ae_slot1_Slot_ae_slot1_get, + Field_ftsf125ae_slot1_Slot_ae_slot1_get, + Field_ftsf126ae_slot1_Slot_ae_slot1_get, + Field_ftsf127ae_slot1_Slot_ae_slot1_get, + Field_ftsf128ae_slot1_Slot_ae_slot1_get, + Field_ftsf129ae_slot1_Slot_ae_slot1_get, + Field_ftsf130ae_slot1_Slot_ae_slot1_get, + Field_ftsf131ae_slot1_Slot_ae_slot1_get, + Field_ftsf132ae_slot1_Slot_ae_slot1_get, + Field_ftsf133ae_slot1_Slot_ae_slot1_get, + Field_ftsf134ae_slot1_Slot_ae_slot1_get, + Field_ftsf135ae_slot1_Slot_ae_slot1_get, + Field_ftsf136ae_slot1_Slot_ae_slot1_get, + Field_ftsf137ae_slot1_Slot_ae_slot1_get, + Field_ftsf138ae_slot1_Slot_ae_slot1_get, + Field_ftsf139ae_slot1_Slot_ae_slot1_get, + Field_ftsf140ae_slot1_Slot_ae_slot1_get, + Field_ftsf141ae_slot1_Slot_ae_slot1_get, + Field_ftsf142ae_slot1_Slot_ae_slot1_get, + Field_ftsf143ae_slot1_Slot_ae_slot1_get, + Field_ftsf144ae_slot1_Slot_ae_slot1_get, + Field_ftsf145ae_slot1_Slot_ae_slot1_get, + Field_ftsf146ae_slot1_Slot_ae_slot1_get, + Field_ftsf147ae_slot1_Slot_ae_slot1_get, + Field_ftsf148ae_slot1_Slot_ae_slot1_get, + Field_ftsf149ae_slot1_Slot_ae_slot1_get, + Field_ftsf150ae_slot1_Slot_ae_slot1_get, + Field_ftsf151ae_slot1_Slot_ae_slot1_get, + Field_ftsf152ae_slot1_Slot_ae_slot1_get, + Field_ftsf153ae_slot1_Slot_ae_slot1_get, + Field_ftsf154ae_slot1_Slot_ae_slot1_get, + Field_ftsf155ae_slot1_Slot_ae_slot1_get, + Field_ftsf156ae_slot1_Slot_ae_slot1_get, + Field_ftsf157ae_slot1_Slot_ae_slot1_get, + Field_ftsf158ae_slot1_Slot_ae_slot1_get, + Field_ftsf159ae_slot1_Slot_ae_slot1_get, + Field_ftsf160ae_slot1_Slot_ae_slot1_get, + Field_ftsf161ae_slot1_Slot_ae_slot1_get, + Field_ftsf162ae_slot1_Slot_ae_slot1_get, + Field_ftsf163ae_slot1_Slot_ae_slot1_get, + Field_ftsf164ae_slot1_Slot_ae_slot1_get, + Field_ftsf165ae_slot1_Slot_ae_slot1_get, + Field_ftsf166ae_slot1_Slot_ae_slot1_get, + Field_ftsf167ae_slot1_Slot_ae_slot1_get, + Field_ftsf168ae_slot1_Slot_ae_slot1_get, + Field_ftsf169ae_slot1_Slot_ae_slot1_get, + Field_ftsf170ae_slot1_Slot_ae_slot1_get, + Field_ftsf171ae_slot1_Slot_ae_slot1_get, + Field_ftsf172ae_slot1_Slot_ae_slot1_get, + Field_ftsf173ae_slot1_Slot_ae_slot1_get, + Field_ftsf174ae_slot1_Slot_ae_slot1_get, + Field_ftsf175ae_slot1_Slot_ae_slot1_get, + Field_ftsf176ae_slot1_Slot_ae_slot1_get, + Field_ftsf177ae_slot1_Slot_ae_slot1_get, + Field_ftsf178ae_slot1_Slot_ae_slot1_get, + Field_ftsf179ae_slot1_Slot_ae_slot1_get, + Field_ftsf180ae_slot1_Slot_ae_slot1_get, + Field_ftsf181ae_slot1_Slot_ae_slot1_get, + Field_ftsf182ae_slot1_Slot_ae_slot1_get, + Field_ftsf183ae_slot1_Slot_ae_slot1_get, + Field_ftsf184ae_slot1_Slot_ae_slot1_get, + Field_ftsf185ae_slot1_Slot_ae_slot1_get, + Field_ftsf186ae_slot1_Slot_ae_slot1_get, + Field_ftsf187ae_slot1_Slot_ae_slot1_get, + Field_ftsf188ae_slot1_Slot_ae_slot1_get, + Field_ftsf189ae_slot1_Slot_ae_slot1_get, + Field_ftsf190ae_slot1_Slot_ae_slot1_get, + Field_ftsf191ae_slot1_Slot_ae_slot1_get, + Field_ftsf192ae_slot1_Slot_ae_slot1_get, + Field_ftsf193ae_slot1_Slot_ae_slot1_get, + Field_ftsf194ae_slot1_Slot_ae_slot1_get, + Field_ftsf195ae_slot1_Slot_ae_slot1_get, + Field_ftsf196ae_slot1_Slot_ae_slot1_get, + Field_ftsf197ae_slot1_Slot_ae_slot1_get, + Field_ftsf198ae_slot1_Slot_ae_slot1_get, + Field_ftsf199ae_slot1_Slot_ae_slot1_get, + Field_ftsf200ae_slot1_Slot_ae_slot1_get, + Field_ftsf201ae_slot1_Slot_ae_slot1_get, + Field_ftsf202ae_slot1_Slot_ae_slot1_get, + Field_ftsf203ae_slot1_Slot_ae_slot1_get, + Field_ftsf204ae_slot1_Slot_ae_slot1_get, + Field_ftsf205ae_slot1_Slot_ae_slot1_get, + Field_ftsf206ae_slot1_Slot_ae_slot1_get, + Field_ftsf207ae_slot1_Slot_ae_slot1_get, + Field_ftsf208_Slot_ae_slot1_get, + Field_ftsf209ae_slot1_Slot_ae_slot1_get, + Field_ftsf210ae_slot1_Slot_ae_slot1_get, + Field_ftsf211ae_slot1_Slot_ae_slot1_get, + Field_ftsf330ae_slot1_Slot_ae_slot1_get, + Field_ftsf332ae_slot1_Slot_ae_slot1_get, + Field_ftsf334ae_slot1_Slot_ae_slot1_get, + Field_ftsf336ae_slot1_Slot_ae_slot1_get, + Field_ftsf337ae_slot1_Slot_ae_slot1_get, + Field_ftsf338_Slot_ae_slot1_get, + Field_ftsf339ae_slot1_Slot_ae_slot1_get, + Field_ftsf340_Slot_ae_slot1_get, + Field_ftsf341ae_slot1_Slot_ae_slot1_get, + Field_ftsf342ae_slot1_Slot_ae_slot1_get, + Field_ftsf343ae_slot1_Slot_ae_slot1_get, + Field_ftsf344ae_slot1_Slot_ae_slot1_get, + Field_ftsf346ae_slot1_Slot_ae_slot1_get, + Field_ftsf347_Slot_ae_slot1_get, + Field_ftsf348ae_slot1_Slot_ae_slot1_get, + Field_ftsf349ae_slot1_Slot_ae_slot1_get, + Field_ftsf350ae_slot1_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot1_set, + 0, + Field_ae_r20_Slot_ae_slot1_set, + Field_ae_r10_Slot_ae_slot1_set, + Field_ae_s20_Slot_ae_slot1_set, + 0, + 0, + Field_op0_s3_Slot_ae_slot1_set, + Field_ftsf12_Slot_ae_slot1_set, + Field_ftsf13_Slot_ae_slot1_set, + Field_ftsf14_Slot_ae_slot1_set, + Field_ftsf21ae_slot1_Slot_ae_slot1_set, + Field_ftsf22ae_slot1_Slot_ae_slot1_set, + Field_ftsf23ae_slot1_Slot_ae_slot1_set, + Field_ftsf24ae_slot1_Slot_ae_slot1_set, + Field_ftsf25ae_slot1_Slot_ae_slot1_set, + Field_ftsf26ae_slot1_Slot_ae_slot1_set, + Field_ftsf27ae_slot1_Slot_ae_slot1_set, + Field_ftsf28ae_slot1_Slot_ae_slot1_set, + Field_ftsf29ae_slot1_Slot_ae_slot1_set, + Field_ftsf30ae_slot1_Slot_ae_slot1_set, + Field_ftsf31ae_slot1_Slot_ae_slot1_set, + Field_ftsf32ae_slot1_Slot_ae_slot1_set, + Field_ftsf33ae_slot1_Slot_ae_slot1_set, + Field_ftsf34ae_slot1_Slot_ae_slot1_set, + Field_ftsf35ae_slot1_Slot_ae_slot1_set, + Field_ftsf36ae_slot1_Slot_ae_slot1_set, + Field_ftsf37ae_slot1_Slot_ae_slot1_set, + Field_ftsf38ae_slot1_Slot_ae_slot1_set, + Field_ftsf39ae_slot1_Slot_ae_slot1_set, + Field_ftsf40ae_slot1_Slot_ae_slot1_set, + Field_ftsf41ae_slot1_Slot_ae_slot1_set, + Field_ftsf42ae_slot1_Slot_ae_slot1_set, + Field_ftsf43ae_slot1_Slot_ae_slot1_set, + Field_ftsf44ae_slot1_Slot_ae_slot1_set, + Field_ftsf45ae_slot1_Slot_ae_slot1_set, + Field_ftsf46ae_slot1_Slot_ae_slot1_set, + Field_ftsf47ae_slot1_Slot_ae_slot1_set, + Field_ftsf48ae_slot1_Slot_ae_slot1_set, + Field_ftsf49ae_slot1_Slot_ae_slot1_set, + Field_ftsf50ae_slot1_Slot_ae_slot1_set, + Field_ftsf51ae_slot1_Slot_ae_slot1_set, + Field_ftsf52ae_slot1_Slot_ae_slot1_set, + Field_ftsf53ae_slot1_Slot_ae_slot1_set, + Field_ftsf54ae_slot1_Slot_ae_slot1_set, + Field_ftsf55ae_slot1_Slot_ae_slot1_set, + Field_ftsf56ae_slot1_Slot_ae_slot1_set, + Field_ftsf57ae_slot1_Slot_ae_slot1_set, + Field_ftsf58ae_slot1_Slot_ae_slot1_set, + Field_ftsf59ae_slot1_Slot_ae_slot1_set, + Field_ftsf60ae_slot1_Slot_ae_slot1_set, + Field_ftsf61ae_slot1_Slot_ae_slot1_set, + Field_ftsf63ae_slot1_Slot_ae_slot1_set, + Field_ftsf64ae_slot1_Slot_ae_slot1_set, + Field_ftsf66ae_slot1_Slot_ae_slot1_set, + Field_ftsf67ae_slot1_Slot_ae_slot1_set, + Field_ftsf69ae_slot1_Slot_ae_slot1_set, + Field_ftsf71ae_slot1_Slot_ae_slot1_set, + Field_ftsf72ae_slot1_Slot_ae_slot1_set, + Field_ftsf73ae_slot1_Slot_ae_slot1_set, + Field_ftsf75ae_slot1_Slot_ae_slot1_set, + Field_ftsf76ae_slot1_Slot_ae_slot1_set, + Field_ftsf77ae_slot1_Slot_ae_slot1_set, + Field_ftsf78ae_slot1_Slot_ae_slot1_set, + Field_ftsf79ae_slot1_Slot_ae_slot1_set, + Field_ftsf80ae_slot1_Slot_ae_slot1_set, + Field_ftsf81ae_slot1_Slot_ae_slot1_set, + Field_ftsf82ae_slot1_Slot_ae_slot1_set, + Field_ftsf84ae_slot1_Slot_ae_slot1_set, + Field_ftsf86ae_slot1_Slot_ae_slot1_set, + Field_ftsf87ae_slot1_Slot_ae_slot1_set, + Field_ftsf88ae_slot1_Slot_ae_slot1_set, + Field_ftsf89ae_slot1_Slot_ae_slot1_set, + Field_ftsf90ae_slot1_Slot_ae_slot1_set, + Field_ftsf91ae_slot1_Slot_ae_slot1_set, + Field_ftsf92ae_slot1_Slot_ae_slot1_set, + Field_ftsf94ae_slot1_Slot_ae_slot1_set, + Field_ftsf96ae_slot1_Slot_ae_slot1_set, + Field_ftsf97ae_slot1_Slot_ae_slot1_set, + Field_ftsf98ae_slot1_Slot_ae_slot1_set, + Field_ftsf99ae_slot1_Slot_ae_slot1_set, + Field_ftsf100ae_slot1_Slot_ae_slot1_set, + Field_ftsf101ae_slot1_Slot_ae_slot1_set, + Field_ftsf103ae_slot1_Slot_ae_slot1_set, + Field_ftsf104ae_slot1_Slot_ae_slot1_set, + Field_ftsf105ae_slot1_Slot_ae_slot1_set, + Field_ftsf106ae_slot1_Slot_ae_slot1_set, + Field_ftsf107ae_slot1_Slot_ae_slot1_set, + Field_ftsf108ae_slot1_Slot_ae_slot1_set, + Field_ftsf109ae_slot1_Slot_ae_slot1_set, + Field_ftsf110ae_slot1_Slot_ae_slot1_set, + Field_ftsf111ae_slot1_Slot_ae_slot1_set, + Field_ftsf112ae_slot1_Slot_ae_slot1_set, + Field_ftsf113ae_slot1_Slot_ae_slot1_set, + Field_ftsf114ae_slot1_Slot_ae_slot1_set, + Field_ftsf115ae_slot1_Slot_ae_slot1_set, + Field_ftsf116ae_slot1_Slot_ae_slot1_set, + Field_ftsf118ae_slot1_Slot_ae_slot1_set, + Field_ftsf119ae_slot1_Slot_ae_slot1_set, + Field_ftsf120ae_slot1_Slot_ae_slot1_set, + Field_ftsf122ae_slot1_Slot_ae_slot1_set, + Field_ftsf124ae_slot1_Slot_ae_slot1_set, + Field_ftsf125ae_slot1_Slot_ae_slot1_set, + Field_ftsf126ae_slot1_Slot_ae_slot1_set, + Field_ftsf127ae_slot1_Slot_ae_slot1_set, + Field_ftsf128ae_slot1_Slot_ae_slot1_set, + Field_ftsf129ae_slot1_Slot_ae_slot1_set, + Field_ftsf130ae_slot1_Slot_ae_slot1_set, + Field_ftsf131ae_slot1_Slot_ae_slot1_set, + Field_ftsf132ae_slot1_Slot_ae_slot1_set, + Field_ftsf133ae_slot1_Slot_ae_slot1_set, + Field_ftsf134ae_slot1_Slot_ae_slot1_set, + Field_ftsf135ae_slot1_Slot_ae_slot1_set, + Field_ftsf136ae_slot1_Slot_ae_slot1_set, + Field_ftsf137ae_slot1_Slot_ae_slot1_set, + Field_ftsf138ae_slot1_Slot_ae_slot1_set, + Field_ftsf139ae_slot1_Slot_ae_slot1_set, + Field_ftsf140ae_slot1_Slot_ae_slot1_set, + Field_ftsf141ae_slot1_Slot_ae_slot1_set, + Field_ftsf142ae_slot1_Slot_ae_slot1_set, + Field_ftsf143ae_slot1_Slot_ae_slot1_set, + Field_ftsf144ae_slot1_Slot_ae_slot1_set, + Field_ftsf145ae_slot1_Slot_ae_slot1_set, + Field_ftsf146ae_slot1_Slot_ae_slot1_set, + Field_ftsf147ae_slot1_Slot_ae_slot1_set, + Field_ftsf148ae_slot1_Slot_ae_slot1_set, + Field_ftsf149ae_slot1_Slot_ae_slot1_set, + Field_ftsf150ae_slot1_Slot_ae_slot1_set, + Field_ftsf151ae_slot1_Slot_ae_slot1_set, + Field_ftsf152ae_slot1_Slot_ae_slot1_set, + Field_ftsf153ae_slot1_Slot_ae_slot1_set, + Field_ftsf154ae_slot1_Slot_ae_slot1_set, + Field_ftsf155ae_slot1_Slot_ae_slot1_set, + Field_ftsf156ae_slot1_Slot_ae_slot1_set, + Field_ftsf157ae_slot1_Slot_ae_slot1_set, + Field_ftsf158ae_slot1_Slot_ae_slot1_set, + Field_ftsf159ae_slot1_Slot_ae_slot1_set, + Field_ftsf160ae_slot1_Slot_ae_slot1_set, + Field_ftsf161ae_slot1_Slot_ae_slot1_set, + Field_ftsf162ae_slot1_Slot_ae_slot1_set, + Field_ftsf163ae_slot1_Slot_ae_slot1_set, + Field_ftsf164ae_slot1_Slot_ae_slot1_set, + Field_ftsf165ae_slot1_Slot_ae_slot1_set, + Field_ftsf166ae_slot1_Slot_ae_slot1_set, + Field_ftsf167ae_slot1_Slot_ae_slot1_set, + Field_ftsf168ae_slot1_Slot_ae_slot1_set, + Field_ftsf169ae_slot1_Slot_ae_slot1_set, + Field_ftsf170ae_slot1_Slot_ae_slot1_set, + Field_ftsf171ae_slot1_Slot_ae_slot1_set, + Field_ftsf172ae_slot1_Slot_ae_slot1_set, + Field_ftsf173ae_slot1_Slot_ae_slot1_set, + Field_ftsf174ae_slot1_Slot_ae_slot1_set, + Field_ftsf175ae_slot1_Slot_ae_slot1_set, + Field_ftsf176ae_slot1_Slot_ae_slot1_set, + Field_ftsf177ae_slot1_Slot_ae_slot1_set, + Field_ftsf178ae_slot1_Slot_ae_slot1_set, + Field_ftsf179ae_slot1_Slot_ae_slot1_set, + Field_ftsf180ae_slot1_Slot_ae_slot1_set, + Field_ftsf181ae_slot1_Slot_ae_slot1_set, + Field_ftsf182ae_slot1_Slot_ae_slot1_set, + Field_ftsf183ae_slot1_Slot_ae_slot1_set, + Field_ftsf184ae_slot1_Slot_ae_slot1_set, + Field_ftsf185ae_slot1_Slot_ae_slot1_set, + Field_ftsf186ae_slot1_Slot_ae_slot1_set, + Field_ftsf187ae_slot1_Slot_ae_slot1_set, + Field_ftsf188ae_slot1_Slot_ae_slot1_set, + Field_ftsf189ae_slot1_Slot_ae_slot1_set, + Field_ftsf190ae_slot1_Slot_ae_slot1_set, + Field_ftsf191ae_slot1_Slot_ae_slot1_set, + Field_ftsf192ae_slot1_Slot_ae_slot1_set, + Field_ftsf193ae_slot1_Slot_ae_slot1_set, + Field_ftsf194ae_slot1_Slot_ae_slot1_set, + Field_ftsf195ae_slot1_Slot_ae_slot1_set, + Field_ftsf196ae_slot1_Slot_ae_slot1_set, + Field_ftsf197ae_slot1_Slot_ae_slot1_set, + Field_ftsf198ae_slot1_Slot_ae_slot1_set, + Field_ftsf199ae_slot1_Slot_ae_slot1_set, + Field_ftsf200ae_slot1_Slot_ae_slot1_set, + Field_ftsf201ae_slot1_Slot_ae_slot1_set, + Field_ftsf202ae_slot1_Slot_ae_slot1_set, + Field_ftsf203ae_slot1_Slot_ae_slot1_set, + Field_ftsf204ae_slot1_Slot_ae_slot1_set, + Field_ftsf205ae_slot1_Slot_ae_slot1_set, + Field_ftsf206ae_slot1_Slot_ae_slot1_set, + Field_ftsf207ae_slot1_Slot_ae_slot1_set, + Field_ftsf208_Slot_ae_slot1_set, + Field_ftsf209ae_slot1_Slot_ae_slot1_set, + Field_ftsf210ae_slot1_Slot_ae_slot1_set, + Field_ftsf211ae_slot1_Slot_ae_slot1_set, + Field_ftsf330ae_slot1_Slot_ae_slot1_set, + Field_ftsf332ae_slot1_Slot_ae_slot1_set, + Field_ftsf334ae_slot1_Slot_ae_slot1_set, + Field_ftsf336ae_slot1_Slot_ae_slot1_set, + Field_ftsf337ae_slot1_Slot_ae_slot1_set, + Field_ftsf338_Slot_ae_slot1_set, + Field_ftsf339ae_slot1_Slot_ae_slot1_set, + Field_ftsf340_Slot_ae_slot1_set, + Field_ftsf341ae_slot1_Slot_ae_slot1_set, + Field_ftsf342ae_slot1_Slot_ae_slot1_set, + Field_ftsf343ae_slot1_Slot_ae_slot1_set, + Field_ftsf344ae_slot1_Slot_ae_slot1_set, + Field_ftsf346ae_slot1_Slot_ae_slot1_set, + Field_ftsf347_Slot_ae_slot1_set, + Field_ftsf348ae_slot1_Slot_ae_slot1_set, + Field_ftsf349ae_slot1_Slot_ae_slot1_set, + Field_ftsf350ae_slot1_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + Field_bbi_Slot_ae_slot0_get, + Field_imm12_Slot_ae_slot0_get, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae_slot0_get, + 0, + 0, + Field_s8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot0_get, + Field_ae_samt_s_t_Slot_ae_slot0_get, + Field_ae_r20_Slot_ae_slot0_get, + Field_ae_r10_Slot_ae_slot0_get, + Field_ae_s20_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_ae_slot0_get, + Field_ftsf212ae_slot0_Slot_ae_slot0_get, + Field_ftsf213ae_slot0_Slot_ae_slot0_get, + Field_ftsf214ae_slot0_Slot_ae_slot0_get, + Field_ftsf215ae_slot0_Slot_ae_slot0_get, + Field_ftsf216ae_slot0_Slot_ae_slot0_get, + Field_ftsf217_Slot_ae_slot0_get, + Field_ftsf218ae_slot0_Slot_ae_slot0_get, + Field_ftsf219ae_slot0_Slot_ae_slot0_get, + Field_ftsf220ae_slot0_Slot_ae_slot0_get, + Field_ftsf221ae_slot0_Slot_ae_slot0_get, + Field_ftsf222ae_slot0_Slot_ae_slot0_get, + Field_ftsf223ae_slot0_Slot_ae_slot0_get, + Field_ftsf224ae_slot0_Slot_ae_slot0_get, + Field_ftsf225ae_slot0_Slot_ae_slot0_get, + Field_ftsf226ae_slot0_Slot_ae_slot0_get, + Field_ftsf227ae_slot0_Slot_ae_slot0_get, + Field_ftsf228ae_slot0_Slot_ae_slot0_get, + Field_ftsf229ae_slot0_Slot_ae_slot0_get, + Field_ftsf230ae_slot0_Slot_ae_slot0_get, + Field_ftsf231ae_slot0_Slot_ae_slot0_get, + Field_ftsf232ae_slot0_Slot_ae_slot0_get, + Field_ftsf233ae_slot0_Slot_ae_slot0_get, + Field_ftsf234ae_slot0_Slot_ae_slot0_get, + Field_ftsf235ae_slot0_Slot_ae_slot0_get, + Field_ftsf236ae_slot0_Slot_ae_slot0_get, + Field_ftsf237ae_slot0_Slot_ae_slot0_get, + Field_ftsf238ae_slot0_Slot_ae_slot0_get, + Field_ftsf239ae_slot0_Slot_ae_slot0_get, + Field_ftsf240ae_slot0_Slot_ae_slot0_get, + Field_ftsf241ae_slot0_Slot_ae_slot0_get, + Field_ftsf242ae_slot0_Slot_ae_slot0_get, + Field_ftsf243ae_slot0_Slot_ae_slot0_get, + Field_ftsf244ae_slot0_Slot_ae_slot0_get, + Field_ftsf245ae_slot0_Slot_ae_slot0_get, + Field_ftsf246ae_slot0_Slot_ae_slot0_get, + Field_ftsf247ae_slot0_Slot_ae_slot0_get, + Field_ftsf248ae_slot0_Slot_ae_slot0_get, + Field_ftsf249ae_slot0_Slot_ae_slot0_get, + Field_ftsf250ae_slot0_Slot_ae_slot0_get, + Field_ftsf251ae_slot0_Slot_ae_slot0_get, + Field_ftsf252ae_slot0_Slot_ae_slot0_get, + Field_ftsf253ae_slot0_Slot_ae_slot0_get, + Field_ftsf254ae_slot0_Slot_ae_slot0_get, + Field_ftsf255ae_slot0_Slot_ae_slot0_get, + Field_ftsf256ae_slot0_Slot_ae_slot0_get, + Field_ftsf257ae_slot0_Slot_ae_slot0_get, + Field_ftsf258ae_slot0_Slot_ae_slot0_get, + Field_ftsf259ae_slot0_Slot_ae_slot0_get, + Field_ftsf260ae_slot0_Slot_ae_slot0_get, + Field_ftsf261ae_slot0_Slot_ae_slot0_get, + Field_ftsf262ae_slot0_Slot_ae_slot0_get, + Field_ftsf263ae_slot0_Slot_ae_slot0_get, + Field_ftsf264ae_slot0_Slot_ae_slot0_get, + Field_ftsf265ae_slot0_Slot_ae_slot0_get, + Field_ftsf266ae_slot0_Slot_ae_slot0_get, + Field_ftsf267ae_slot0_Slot_ae_slot0_get, + Field_ftsf268ae_slot0_Slot_ae_slot0_get, + Field_ftsf269ae_slot0_Slot_ae_slot0_get, + Field_ftsf270ae_slot0_Slot_ae_slot0_get, + Field_ftsf271ae_slot0_Slot_ae_slot0_get, + Field_ftsf272ae_slot0_Slot_ae_slot0_get, + Field_ftsf273ae_slot0_Slot_ae_slot0_get, + Field_ftsf274ae_slot0_Slot_ae_slot0_get, + Field_ftsf275ae_slot0_Slot_ae_slot0_get, + Field_ftsf276ae_slot0_Slot_ae_slot0_get, + Field_ftsf277ae_slot0_Slot_ae_slot0_get, + Field_ftsf278ae_slot0_Slot_ae_slot0_get, + Field_ftsf279ae_slot0_Slot_ae_slot0_get, + Field_ftsf281ae_slot0_Slot_ae_slot0_get, + Field_ftsf282ae_slot0_Slot_ae_slot0_get, + Field_ftsf283ae_slot0_Slot_ae_slot0_get, + Field_ftsf284ae_slot0_Slot_ae_slot0_get, + Field_ftsf286ae_slot0_Slot_ae_slot0_get, + Field_ftsf288ae_slot0_Slot_ae_slot0_get, + Field_ftsf290ae_slot0_Slot_ae_slot0_get, + Field_ftsf292ae_slot0_Slot_ae_slot0_get, + Field_ftsf293_Slot_ae_slot0_get, + Field_ftsf294ae_slot0_Slot_ae_slot0_get, + Field_ftsf295ae_slot0_Slot_ae_slot0_get, + Field_ftsf296ae_slot0_Slot_ae_slot0_get, + Field_ftsf297ae_slot0_Slot_ae_slot0_get, + Field_ftsf298ae_slot0_Slot_ae_slot0_get, + Field_ftsf299ae_slot0_Slot_ae_slot0_get, + Field_ftsf300ae_slot0_Slot_ae_slot0_get, + Field_ftsf301ae_slot0_Slot_ae_slot0_get, + Field_ftsf302ae_slot0_Slot_ae_slot0_get, + Field_ftsf303ae_slot0_Slot_ae_slot0_get, + Field_ftsf304ae_slot0_Slot_ae_slot0_get, + Field_ftsf306ae_slot0_Slot_ae_slot0_get, + Field_ftsf308ae_slot0_Slot_ae_slot0_get, + Field_ftsf309ae_slot0_Slot_ae_slot0_get, + Field_ftsf310ae_slot0_Slot_ae_slot0_get, + Field_ftsf311ae_slot0_Slot_ae_slot0_get, + Field_ftsf312ae_slot0_Slot_ae_slot0_get, + Field_ftsf313ae_slot0_Slot_ae_slot0_get, + Field_ftsf314ae_slot0_Slot_ae_slot0_get, + Field_ftsf315ae_slot0_Slot_ae_slot0_get, + Field_ftsf316ae_slot0_Slot_ae_slot0_get, + Field_ftsf317ae_slot0_Slot_ae_slot0_get, + Field_ftsf318ae_slot0_Slot_ae_slot0_get, + Field_ftsf319_Slot_ae_slot0_get, + Field_ftsf320ae_slot0_Slot_ae_slot0_get, + Field_ftsf321_Slot_ae_slot0_get, + Field_ftsf322ae_slot0_Slot_ae_slot0_get, + Field_ftsf323ae_slot0_Slot_ae_slot0_get, + Field_ftsf324ae_slot0_Slot_ae_slot0_get, + Field_ftsf325ae_slot0_Slot_ae_slot0_get, + Field_ftsf326ae_slot0_Slot_ae_slot0_get, + Field_ftsf328ae_slot0_Slot_ae_slot0_get, + Field_ftsf329ae_slot0_Slot_ae_slot0_get, + Field_ftsf352ae_slot0_Slot_ae_slot0_get, + Field_ftsf353_Slot_ae_slot0_get, + Field_ftsf354ae_slot0_Slot_ae_slot0_get, + Field_ftsf356ae_slot0_Slot_ae_slot0_get, + Field_ftsf357_Slot_ae_slot0_get, + Field_ftsf358ae_slot0_Slot_ae_slot0_get, + Field_ftsf359ae_slot0_Slot_ae_slot0_get, + Field_ftsf360ae_slot0_Slot_ae_slot0_get, + Field_ftsf361ae_slot0_Slot_ae_slot0_get, + Field_ftsf362ae_slot0_Slot_ae_slot0_get, + Field_ftsf364ae_slot0_Slot_ae_slot0_get, + Field_ftsf365ae_slot0_Slot_ae_slot0_get, + Field_ftsf366ae_slot0_Slot_ae_slot0_get, + Field_ftsf368ae_slot0_Slot_ae_slot0_get, + Field_ftsf369ae_slot0_Slot_ae_slot0_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + Field_bbi_Slot_ae_slot0_set, + Field_imm12_Slot_ae_slot0_set, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae_slot0_set, + 0, + 0, + Field_s8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_r32_Slot_ae_slot0_set, + Field_ae_samt_s_t_Slot_ae_slot0_set, + Field_ae_r20_Slot_ae_slot0_set, + Field_ae_r10_Slot_ae_slot0_set, + Field_ae_s20_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_ae_slot0_set, + Field_ftsf212ae_slot0_Slot_ae_slot0_set, + Field_ftsf213ae_slot0_Slot_ae_slot0_set, + Field_ftsf214ae_slot0_Slot_ae_slot0_set, + Field_ftsf215ae_slot0_Slot_ae_slot0_set, + Field_ftsf216ae_slot0_Slot_ae_slot0_set, + Field_ftsf217_Slot_ae_slot0_set, + Field_ftsf218ae_slot0_Slot_ae_slot0_set, + Field_ftsf219ae_slot0_Slot_ae_slot0_set, + Field_ftsf220ae_slot0_Slot_ae_slot0_set, + Field_ftsf221ae_slot0_Slot_ae_slot0_set, + Field_ftsf222ae_slot0_Slot_ae_slot0_set, + Field_ftsf223ae_slot0_Slot_ae_slot0_set, + Field_ftsf224ae_slot0_Slot_ae_slot0_set, + Field_ftsf225ae_slot0_Slot_ae_slot0_set, + Field_ftsf226ae_slot0_Slot_ae_slot0_set, + Field_ftsf227ae_slot0_Slot_ae_slot0_set, + Field_ftsf228ae_slot0_Slot_ae_slot0_set, + Field_ftsf229ae_slot0_Slot_ae_slot0_set, + Field_ftsf230ae_slot0_Slot_ae_slot0_set, + Field_ftsf231ae_slot0_Slot_ae_slot0_set, + Field_ftsf232ae_slot0_Slot_ae_slot0_set, + Field_ftsf233ae_slot0_Slot_ae_slot0_set, + Field_ftsf234ae_slot0_Slot_ae_slot0_set, + Field_ftsf235ae_slot0_Slot_ae_slot0_set, + Field_ftsf236ae_slot0_Slot_ae_slot0_set, + Field_ftsf237ae_slot0_Slot_ae_slot0_set, + Field_ftsf238ae_slot0_Slot_ae_slot0_set, + Field_ftsf239ae_slot0_Slot_ae_slot0_set, + Field_ftsf240ae_slot0_Slot_ae_slot0_set, + Field_ftsf241ae_slot0_Slot_ae_slot0_set, + Field_ftsf242ae_slot0_Slot_ae_slot0_set, + Field_ftsf243ae_slot0_Slot_ae_slot0_set, + Field_ftsf244ae_slot0_Slot_ae_slot0_set, + Field_ftsf245ae_slot0_Slot_ae_slot0_set, + Field_ftsf246ae_slot0_Slot_ae_slot0_set, + Field_ftsf247ae_slot0_Slot_ae_slot0_set, + Field_ftsf248ae_slot0_Slot_ae_slot0_set, + Field_ftsf249ae_slot0_Slot_ae_slot0_set, + Field_ftsf250ae_slot0_Slot_ae_slot0_set, + Field_ftsf251ae_slot0_Slot_ae_slot0_set, + Field_ftsf252ae_slot0_Slot_ae_slot0_set, + Field_ftsf253ae_slot0_Slot_ae_slot0_set, + Field_ftsf254ae_slot0_Slot_ae_slot0_set, + Field_ftsf255ae_slot0_Slot_ae_slot0_set, + Field_ftsf256ae_slot0_Slot_ae_slot0_set, + Field_ftsf257ae_slot0_Slot_ae_slot0_set, + Field_ftsf258ae_slot0_Slot_ae_slot0_set, + Field_ftsf259ae_slot0_Slot_ae_slot0_set, + Field_ftsf260ae_slot0_Slot_ae_slot0_set, + Field_ftsf261ae_slot0_Slot_ae_slot0_set, + Field_ftsf262ae_slot0_Slot_ae_slot0_set, + Field_ftsf263ae_slot0_Slot_ae_slot0_set, + Field_ftsf264ae_slot0_Slot_ae_slot0_set, + Field_ftsf265ae_slot0_Slot_ae_slot0_set, + Field_ftsf266ae_slot0_Slot_ae_slot0_set, + Field_ftsf267ae_slot0_Slot_ae_slot0_set, + Field_ftsf268ae_slot0_Slot_ae_slot0_set, + Field_ftsf269ae_slot0_Slot_ae_slot0_set, + Field_ftsf270ae_slot0_Slot_ae_slot0_set, + Field_ftsf271ae_slot0_Slot_ae_slot0_set, + Field_ftsf272ae_slot0_Slot_ae_slot0_set, + Field_ftsf273ae_slot0_Slot_ae_slot0_set, + Field_ftsf274ae_slot0_Slot_ae_slot0_set, + Field_ftsf275ae_slot0_Slot_ae_slot0_set, + Field_ftsf276ae_slot0_Slot_ae_slot0_set, + Field_ftsf277ae_slot0_Slot_ae_slot0_set, + Field_ftsf278ae_slot0_Slot_ae_slot0_set, + Field_ftsf279ae_slot0_Slot_ae_slot0_set, + Field_ftsf281ae_slot0_Slot_ae_slot0_set, + Field_ftsf282ae_slot0_Slot_ae_slot0_set, + Field_ftsf283ae_slot0_Slot_ae_slot0_set, + Field_ftsf284ae_slot0_Slot_ae_slot0_set, + Field_ftsf286ae_slot0_Slot_ae_slot0_set, + Field_ftsf288ae_slot0_Slot_ae_slot0_set, + Field_ftsf290ae_slot0_Slot_ae_slot0_set, + Field_ftsf292ae_slot0_Slot_ae_slot0_set, + Field_ftsf293_Slot_ae_slot0_set, + Field_ftsf294ae_slot0_Slot_ae_slot0_set, + Field_ftsf295ae_slot0_Slot_ae_slot0_set, + Field_ftsf296ae_slot0_Slot_ae_slot0_set, + Field_ftsf297ae_slot0_Slot_ae_slot0_set, + Field_ftsf298ae_slot0_Slot_ae_slot0_set, + Field_ftsf299ae_slot0_Slot_ae_slot0_set, + Field_ftsf300ae_slot0_Slot_ae_slot0_set, + Field_ftsf301ae_slot0_Slot_ae_slot0_set, + Field_ftsf302ae_slot0_Slot_ae_slot0_set, + Field_ftsf303ae_slot0_Slot_ae_slot0_set, + Field_ftsf304ae_slot0_Slot_ae_slot0_set, + Field_ftsf306ae_slot0_Slot_ae_slot0_set, + Field_ftsf308ae_slot0_Slot_ae_slot0_set, + Field_ftsf309ae_slot0_Slot_ae_slot0_set, + Field_ftsf310ae_slot0_Slot_ae_slot0_set, + Field_ftsf311ae_slot0_Slot_ae_slot0_set, + Field_ftsf312ae_slot0_Slot_ae_slot0_set, + Field_ftsf313ae_slot0_Slot_ae_slot0_set, + Field_ftsf314ae_slot0_Slot_ae_slot0_set, + Field_ftsf315ae_slot0_Slot_ae_slot0_set, + Field_ftsf316ae_slot0_Slot_ae_slot0_set, + Field_ftsf317ae_slot0_Slot_ae_slot0_set, + Field_ftsf318ae_slot0_Slot_ae_slot0_set, + Field_ftsf319_Slot_ae_slot0_set, + Field_ftsf320ae_slot0_Slot_ae_slot0_set, + Field_ftsf321_Slot_ae_slot0_set, + Field_ftsf322ae_slot0_Slot_ae_slot0_set, + Field_ftsf323ae_slot0_Slot_ae_slot0_set, + Field_ftsf324ae_slot0_Slot_ae_slot0_set, + Field_ftsf325ae_slot0_Slot_ae_slot0_set, + Field_ftsf326ae_slot0_Slot_ae_slot0_set, + Field_ftsf328ae_slot0_Slot_ae_slot0_set, + Field_ftsf329ae_slot0_Slot_ae_slot0_set, + Field_ftsf352ae_slot0_Slot_ae_slot0_set, + Field_ftsf353_Slot_ae_slot0_set, + Field_ftsf354ae_slot0_Slot_ae_slot0_set, + Field_ftsf356ae_slot0_Slot_ae_slot0_set, + Field_ftsf357_Slot_ae_slot0_set, + Field_ftsf358ae_slot0_Slot_ae_slot0_set, + Field_ftsf359ae_slot0_Slot_ae_slot0_set, + Field_ftsf360ae_slot0_Slot_ae_slot0_set, + Field_ftsf361ae_slot0_Slot_ae_slot0_set, + Field_ftsf362ae_slot0_Slot_ae_slot0_set, + Field_ftsf364ae_slot0_Slot_ae_slot0_set, + Field_ftsf365ae_slot0_Slot_ae_slot0_set, + Field_ftsf366ae_slot0_Slot_ae_slot0_set, + Field_ftsf368ae_slot0_Slot_ae_slot0_set, + Field_ftsf369ae_slot0_Slot_ae_slot0_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 4, 3 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) + return 3; /* ae_format */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 8 /* insn_size */, 0, + 4, formats, format_decoder, length_decoder, + 5, slots, + 389 /* num_fields */, + 454, operands, + 588, iclasses, + 656, opcodes, 0, + 8, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 2, interfaces, 0, + 4, funcUnits, 0 +}; diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c deleted file mode 100644 index 28561147fc..0000000000 --- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c +++ /dev/null @@ -1,36387 +0,0 @@ -/* Xtensa configuration-specific ISA information. - - Copyright (c) 2003-2019 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "xtensa-isa.h" -#include "xtensa-isa-internal.h" - - -/* Sysregs. */ - -static xtensa_sysreg_internal sysregs[] = { - { "LBEG", 0, 0 }, - { "LEND", 1, 0 }, - { "LCOUNT", 2, 0 }, - { "BR", 4, 0 }, - { "PTEVADDR", 83, 0 }, - { "DDR", 104, 0 }, - { "CONFIGID0", 176, 0 }, - { "CONFIGID1", 208, 0 }, - { "INTERRUPT", 226, 0 }, - { "INTCLEAR", 227, 0 }, - { "CCOUNT", 234, 0 }, - { "PRID", 235, 0 }, - { "ICOUNT", 236, 0 }, - { "CCOMPARE0", 240, 0 }, - { "CCOMPARE1", 241, 0 }, - { "VECBASE", 231, 0 }, - { "EPC1", 177, 0 }, - { "EPC2", 178, 0 }, - { "EXCSAVE1", 209, 0 }, - { "EXCSAVE2", 210, 0 }, - { "EPS2", 194, 0 }, - { "EXCCAUSE", 232, 0 }, - { "DEPC", 192, 0 }, - { "EXCVADDR", 238, 0 }, - { "WINDOWBASE", 72, 0 }, - { "WINDOWSTART", 73, 0 }, - { "SAR", 3, 0 }, - { "LITBASE", 5, 0 }, - { "PS", 230, 0 }, - { "MISC0", 244, 0 }, - { "MISC1", 245, 0 }, - { "INTENABLE", 228, 0 }, - { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 }, - { "RASID", 90, 0 }, - { "ITLBCFG", 91, 0 }, - { "DTLBCFG", 92, 0 }, - { "CPENABLE", 224, 0 }, - { "SCOMPARE1", 12, 0 }, - { "ATOMCTL", 99, 0 }, - { "THREADPTR", 231, 1 }, - { "AE_OVF_SAR", 240, 1 }, - { "AE_BITHEAD", 241, 1 }, - { "AE_TS_FTS_BU_BP", 242, 1 }, - { "AE_SD_NO", 243, 1 } -}; - -#define NUM_SYSREGS 45 -#define MAX_SPECIAL_REG 245 -#define MAX_USER_REG 243 - - -/* Processor states. */ - -static xtensa_state_internal states[] = { - { "LCOUNT", 32, 0 }, - { "PC", 32, 0 }, - { "ICOUNT", 32, 0 }, - { "DDR", 32, 0 }, - { "INTERRUPT", 12, 0 }, - { "CCOUNT", 32, 0 }, - { "XTSYNC", 1, 0 }, - { "VECBASE", 22, 0 }, - { "EPC1", 32, 0 }, - { "EPC2", 32, 0 }, - { "EXCSAVE1", 32, 0 }, - { "EXCSAVE2", 32, 0 }, - { "EPS2", 15, 0 }, - { "EXCCAUSE", 6, 0 }, - { "PSINTLEVEL", 4, 0 }, - { "PSUM", 1, 0 }, - { "PSWOE", 1, 0 }, - { "PSRING", 2, 0 }, - { "PSEXCM", 1, 0 }, - { "DEPC", 32, 0 }, - { "EXCVADDR", 32, 0 }, - { "WindowBase", 3, 0 }, - { "WindowStart", 8, 0 }, - { "PSCALLINC", 2, 0 }, - { "PSOWB", 4, 0 }, - { "LBEG", 32, 0 }, - { "LEND", 32, 0 }, - { "SAR", 6, 0 }, - { "THREADPTR", 32, 0 }, - { "LITBADDR", 20, 0 }, - { "LITBEN", 1, 0 }, - { "MISC0", 32, 0 }, - { "MISC1", 32, 0 }, - { "InOCDMode", 1, 0 }, - { "INTENABLE", 12, 0 }, - { "ICOUNTLEVEL", 4, 0 }, - { "DEBUGCAUSE", 6, 0 }, - { "DBNUM", 4, 0 }, - { "CCOMPARE0", 32, 0 }, - { "CCOMPARE1", 32, 0 }, - { "ASID3", 8, 0 }, - { "ASID2", 8, 0 }, - { "ASID1", 8, 0 }, - { "INSTPGSZID4", 2, 0 }, - { "DATAPGSZID4", 2, 0 }, - { "PTBASE", 10, 0 }, - { "CPENABLE", 2, 0 }, - { "SCOMPARE1", 32, 0 }, - { "ATOMCTL", 6, 0 }, - { "CCON", 1, XTENSA_STATE_IS_EXPORTED }, - { "MPSCORE", 16, XTENSA_STATE_IS_EXPORTED }, - { "WMPINT_ADDR", 12, XTENSA_STATE_IS_EXPORTED }, - { "WMPINT_DATA", 32, XTENSA_STATE_IS_EXPORTED }, - { "WMPINT_TOGGLEEN", 1, XTENSA_STATE_IS_EXPORTED }, - { "AE_OVERFLOW", 1, 0 }, - { "AE_SAR", 6, 0 }, - { "AE_BITHEAD", 32, 0 }, - { "AE_BITPTR", 4, 0 }, - { "AE_BITSUSED", 4, 0 }, - { "AE_TABLESIZE", 4, 0 }, - { "AE_FIRST_TS", 4, 0 }, - { "AE_NEXTOFFSET", 27, 0 }, - { "AE_SEARCHDONE", 1, 0 } -}; - -#define NUM_STATES 63 - -enum xtensa_state_id { - STATE_LCOUNT, - STATE_PC, - STATE_ICOUNT, - STATE_DDR, - STATE_INTERRUPT, - STATE_CCOUNT, - STATE_XTSYNC, - STATE_VECBASE, - STATE_EPC1, - STATE_EPC2, - STATE_EXCSAVE1, - STATE_EXCSAVE2, - STATE_EPS2, - STATE_EXCCAUSE, - STATE_PSINTLEVEL, - STATE_PSUM, - STATE_PSWOE, - STATE_PSRING, - STATE_PSEXCM, - STATE_DEPC, - STATE_EXCVADDR, - STATE_WindowBase, - STATE_WindowStart, - STATE_PSCALLINC, - STATE_PSOWB, - STATE_LBEG, - STATE_LEND, - STATE_SAR, - STATE_THREADPTR, - STATE_LITBADDR, - STATE_LITBEN, - STATE_MISC0, - STATE_MISC1, - STATE_InOCDMode, - STATE_INTENABLE, - STATE_ICOUNTLEVEL, - STATE_DEBUGCAUSE, - STATE_DBNUM, - STATE_CCOMPARE0, - STATE_CCOMPARE1, - STATE_ASID3, - STATE_ASID2, - STATE_ASID1, - STATE_INSTPGSZID4, - STATE_DATAPGSZID4, - STATE_PTBASE, - STATE_CPENABLE, - STATE_SCOMPARE1, - STATE_ATOMCTL, - STATE_CCON, - STATE_MPSCORE, - STATE_WMPINT_ADDR, - STATE_WMPINT_DATA, - STATE_WMPINT_TOGGLEEN, - STATE_AE_OVERFLOW, - STATE_AE_SAR, - STATE_AE_BITHEAD, - STATE_AE_BITPTR, - STATE_AE_BITSUSED, - STATE_AE_TABLESIZE, - STATE_AE_FIRST_TS, - STATE_AE_NEXTOFFSET, - STATE_AE_SEARCHDONE -}; - - -/* Field definitions. */ - -static unsigned -Field_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_s_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); -} - -static unsigned -Field_op1_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_op0_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_n_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_m_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_sr_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf61ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf61ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); - return tie_t; -} - -static void -Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf330ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_ftsf330ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf347_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf347_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - return tie_t; -} - -static void -Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); - return tie_t; -} - -static void -Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); -} - -static unsigned -Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 23) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf340_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf340_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 22) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); - return tie_t; -} - -static void -Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x78) | (tie_t << 3); - tie_t = (val << 21) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf59ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf59ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf119ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf119ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 24) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 21) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf338_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf338_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 22) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf67ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf67ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x60) | (tie_t << 5); - tie_t = (val << 21) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 20) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 23) >> 26); - return tie_t; -} - -static void -Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x1f8) | (tie_t << 3); -} - -static unsigned -Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf100ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf100ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); - return tie_t; -} - -static void -Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); -} - -static unsigned -Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf98ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf98ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf208_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf208_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); -} - -static unsigned -Field_ftsf91ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf91ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); - tie_t = (val << 25) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); - return tie_t; -} - -static void -Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); -} - -static unsigned -Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 23) >> 30; - insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); -} - -static unsigned -Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf122ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); - return tie_t; -} - -static void -Field_ftsf122ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); - tie_t = (val << 24) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf346ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf346ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf104ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf104ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf105ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf105ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); - return tie_t; -} - -static void -Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); - tie_t = (val << 20) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 6) | ((insn[0] << 25) >> 26); - return tie_t; -} - -static void -Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x7e) | (tie_t << 1); - tie_t = (val << 23) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); - return tie_t; -} - -static void -Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); - tie_t = (val << 22) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - return tie_t; -} - -static void -Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 22) >> 23; - insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 24) >> 25; - insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 28) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); - tie_t = (val << 26) >> 29; - insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); -} - -static unsigned -Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x600) | (tie_t << 9); -} - -static unsigned -Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf211ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_ftsf211ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf332ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf332ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); -} - -static unsigned -Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf44ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf44ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf39ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf39ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf46ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf46ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf55ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf55ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 26) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 23) >> 27; - insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); -} - -static unsigned -Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - return tie_t; -} - -static void -Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf209ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf209ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); - tie_t = (val << 24) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); - return tie_t; -} - -static void -Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); -} - -static unsigned -Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); -} - -static unsigned -Field_ftsf293_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf293_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_ftsf321_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf321_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); -} - -static unsigned -Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); - return tie_t; -} - -static void -Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); -} - -static unsigned -Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); - return tie_t; -} - -static void -Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); -} - -static unsigned -Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf217_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf217_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - return tie_t; -} - -static void -Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf283ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf283ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 25) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 17) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf352ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf352ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 16) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf288ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); - return tie_t; -} - -static void -Field_ftsf288ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x38) | (tie_t << 3); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf359ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf359ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 27) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf286ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); - return tie_t; -} - -static void -Field_ftsf286ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf356ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf356ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 5) | ((insn[0] << 26) >> 27); - return tie_t; -} - -static void -Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x3e) | (tie_t << 1); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf354ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf354ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf358ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf358ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); - return tie_t; -} - -static void -Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 25) >> 25; - insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); -} - -static unsigned -Field_ftsf301ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); - return tie_t; -} - -static void -Field_ftsf301ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 19) >> 19; - insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); -} - -static unsigned -Field_ftsf353_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_ftsf353_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf309ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); - return tie_t; -} - -static void -Field_ftsf309ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 23) >> 23; - insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); -} - -static unsigned -Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); - return tie_t; -} - -static void -Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); -} - -static unsigned -Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); - tie_t = (val << 21) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf319_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf319_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); -} - -static unsigned -Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); - return tie_t; -} - -static void -Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x20) | (tie_t << 5); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); - return tie_t; -} - -static void -Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); -} - -static unsigned -Field_ftsf362ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_ftsf362ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); - tie_t = (val << 27) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf216ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_ftsf216ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); - return tie_t; -} - -static void -Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); - tie_t = (val << 18) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf318ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); - return tie_t; -} - -static void -Field_ftsf318ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe) | (tie_t << 1); - tie_t = (val << 28) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf365ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf365ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf315ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf315ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf299ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); - return tie_t; -} - -static void -Field_ftsf299ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 22) >> 22; - insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); -} - -static unsigned -Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); - return tie_t; -} - -static void -Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 21) >> 21; - insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); -} - -static unsigned -Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100) | (tie_t << 8); -} - -static unsigned -Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); - return tie_t; -} - -static void -Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x4) | (tie_t << 2); - tie_t = (val << 19) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); - tie_t = (val << 29) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); - return tie_t; -} - -static void -Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x6) | (tie_t << 1); - tie_t = (val << 18) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf369ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); - return tie_t; -} - -static void -Field_ftsf369ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1) | (tie_t << 0); - tie_t = (val << 30) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); -} - -static unsigned -Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 23) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); - return tie_t; -} - -static void -Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc) | (tie_t << 2); - tie_t = (val << 22) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf357_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); - return tie_t; -} - -static void -Field_ftsf357_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x3) | (tie_t << 0); -} - -static unsigned -Field_ftsf303ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); - tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); - return tie_t; -} - -static void -Field_ftsf303ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7) | (tie_t << 0); - tie_t = (val << 17) >> 20; - insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); -} - -static unsigned -Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 20) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); - tie_t = (val << 19) >> 24; - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); -} - -static unsigned -Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); -} - -static unsigned -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - return tie_t; -} - -static void -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); - return tie_t; -} - -static void -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); -} - -static unsigned -Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); - return tie_t; -} - -static void -Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff) | (tie_t << 0); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); -} - -static unsigned -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); - return tie_t; -} - -static void -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 24) >> 24; - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); - tie_t = (val << 20) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); - return tie_t; -} - -static void -Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 20) >> 20; - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); -} - -static unsigned -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); -} - -static unsigned -Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); - return tie_t; -} - -static void -Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 16) >> 16; - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); -} - -static unsigned -Field_offset_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); - return tie_t; -} - -static void -Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); -} - -static unsigned -Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - return tie_t; -} - -static void -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - return tie_t; -} - -static void -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); -} - -static unsigned -Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27); - return tie_t; -} - -static void -Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12); -} - -static unsigned -Field_sal_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); -} - -static unsigned -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); -} - -static unsigned -Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); - return tie_t; -} - -static void -Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); -} - -static unsigned -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - return tie_t; -} - -static void -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 27) >> 31; - insn[0] = (insn[0] & ~0x10) | (tie_t << 4); -} - -static unsigned -Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); - return tie_t; -} - -static void -Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 27) >> 27; - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); -} - -static unsigned -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - return tie_t; -} - -static void -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); - return tie_t; -} - -static void -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); - tie_t = (val << 24) >> 28; - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); -} - -static unsigned -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_mn_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); - tie_t = (val << 28) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); -} - -static unsigned -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); - return tie_t; -} - -static void -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x40) | (tie_t << 6); -} - -static unsigned -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); - return tie_t; -} - -static void -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); - tie_t = (val << 25) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_t2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); - return tie_t; -} - -static void -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); -} - -static unsigned -Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 29) >> 30; - insn[0] = (insn[0] & ~0x180) | (tie_t << 7); -} - -static unsigned -Field_s2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); - return tie_t; -} - -static void -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); -} - -static unsigned -Field_r2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); - return tie_t; -} - -static void -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); -} - -static unsigned -Field_t4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); - return tie_t; -} - -static void -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); -} - -static unsigned -Field_s4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); -} - -static unsigned -Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_r4_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); - return tie_t; -} - -static void -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); -} - -static unsigned -Field_t8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); - return tie_t; -} - -static void -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x80) | (tie_t << 7); -} - -static unsigned -Field_s8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); - return tie_t; -} - -static void -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x800) | (tie_t << 11); -} - -static unsigned -Field_r8_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); - return tie_t; -} - -static void -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); -} - -static unsigned -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); - return tie_t; -} - -static void -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 17) >> 17; - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); -} - -static unsigned -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); - return tie_t; -} - -static void -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 14) >> 14; - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); -} - -static unsigned -Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 26) >> 26; - insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); -} - -static unsigned -Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); - return tie_t; -} - -static void -Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf) | (tie_t << 0); - tie_t = (val << 26) >> 30; - insn[0] = (insn[0] & ~0x300) | (tie_t << 8); -} - -static unsigned -Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); - return tie_t; -} - -static void -Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); -} - -static unsigned -Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); - return tie_t; -} - -static void -Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x700) | (tie_t << 8); -} - -static unsigned -Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); - return tie_t; -} - -static void -Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 28) >> 28; - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); -} - -static unsigned -Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); - return tie_t; -} - -static void -Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 29) >> 29; - insn[0] = (insn[0] & ~0x70) | (tie_t << 4); -} - -static unsigned -Field_ftsf13_Slot_inst_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); - return tie_t; -} - -static void -Field_ftsf13_Slot_inst_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 30) >> 30; - insn[0] = (insn[0] & ~0x30) | (tie_t << 4); -} - -static unsigned -Field_ftsf14_Slot_ae_slot1_get (const xtensa_insnbuf insn) -{ - unsigned tie_t = 0; - tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); - tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); - return tie_t; -} - -static void -Field_ftsf14_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) -{ - uint32 tie_t; - tie_t = (val << 31) >> 31; - insn[0] = (insn[0] & ~0x8) | (tie_t << 3); - tie_t = (val << 27) >> 28; - insn[0] = (insn[0] & ~0x780) | (tie_t << 7); -} - -static void -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, - uint32 val ATTRIBUTE_UNUSED) -{ - /* Do nothing. */ -} - -static unsigned -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 4; -} - -static unsigned -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 8; -} - -static unsigned -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 12; -} - -static unsigned -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -static unsigned -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) -{ - return 0; -} - -enum xtensa_field_id { - FIELD_t, - FIELD_bbi4, - FIELD_bbi, - FIELD_imm12, - FIELD_imm8, - FIELD_s, - FIELD_imm12b, - FIELD_imm16, - FIELD_m, - FIELD_n, - FIELD_offset, - FIELD_op0, - FIELD_op1, - FIELD_op2, - FIELD_r, - FIELD_sa4, - FIELD_sae4, - FIELD_sae, - FIELD_sal, - FIELD_sargt, - FIELD_sas4, - FIELD_sas, - FIELD_sr, - FIELD_st, - FIELD_thi3, - FIELD_imm4, - FIELD_mn, - FIELD_i, - FIELD_imm6lo, - FIELD_imm6hi, - FIELD_imm7lo, - FIELD_imm7hi, - FIELD_z, - FIELD_imm6, - FIELD_imm7, - FIELD_t2, - FIELD_s2, - FIELD_r2, - FIELD_t4, - FIELD_s4, - FIELD_r4, - FIELD_t8, - FIELD_s8, - FIELD_r8, - FIELD_xt_wbr15_imm, - FIELD_xt_wbr18_imm, - FIELD_ae_r3, - FIELD_ae_s_non_samt, - FIELD_ae_s3, - FIELD_ae_r32, - FIELD_ae_samt_s_t, - FIELD_ae_r20, - FIELD_ae_r10, - FIELD_ae_s20, - FIELD_ae_fld_ohba, - FIELD_ae_fld_ohba2, - FIELD_op0_s3, - FIELD_ftsf12, - FIELD_ftsf13, - FIELD_ftsf14, - FIELD_ftsf21ae_slot1, - FIELD_ftsf22ae_slot1, - FIELD_ftsf23ae_slot1, - FIELD_ftsf24ae_slot1, - FIELD_ftsf25ae_slot1, - FIELD_ftsf26ae_slot1, - FIELD_ftsf27ae_slot1, - FIELD_ftsf28ae_slot1, - FIELD_ftsf29ae_slot1, - FIELD_ftsf30ae_slot1, - FIELD_ftsf31ae_slot1, - FIELD_ftsf32ae_slot1, - FIELD_ftsf33ae_slot1, - FIELD_ftsf34ae_slot1, - FIELD_ftsf35ae_slot1, - FIELD_ftsf36ae_slot1, - FIELD_ftsf37ae_slot1, - FIELD_ftsf38ae_slot1, - FIELD_ftsf39ae_slot1, - FIELD_ftsf40ae_slot1, - FIELD_ftsf41ae_slot1, - FIELD_ftsf42ae_slot1, - FIELD_ftsf43ae_slot1, - FIELD_ftsf44ae_slot1, - FIELD_ftsf45ae_slot1, - FIELD_ftsf46ae_slot1, - FIELD_ftsf47ae_slot1, - FIELD_ftsf48ae_slot1, - FIELD_ftsf49ae_slot1, - FIELD_ftsf50ae_slot1, - FIELD_ftsf51ae_slot1, - FIELD_ftsf52ae_slot1, - FIELD_ftsf53ae_slot1, - FIELD_ftsf54ae_slot1, - FIELD_ftsf55ae_slot1, - FIELD_ftsf56ae_slot1, - FIELD_ftsf57ae_slot1, - FIELD_ftsf58ae_slot1, - FIELD_ftsf59ae_slot1, - FIELD_ftsf60ae_slot1, - FIELD_ftsf61ae_slot1, - FIELD_ftsf63ae_slot1, - FIELD_ftsf64ae_slot1, - FIELD_ftsf66ae_slot1, - FIELD_ftsf67ae_slot1, - FIELD_ftsf69ae_slot1, - FIELD_ftsf71ae_slot1, - FIELD_ftsf72ae_slot1, - FIELD_ftsf73ae_slot1, - FIELD_ftsf75ae_slot1, - FIELD_ftsf76ae_slot1, - FIELD_ftsf77ae_slot1, - FIELD_ftsf78ae_slot1, - FIELD_ftsf79ae_slot1, - FIELD_ftsf80ae_slot1, - FIELD_ftsf81ae_slot1, - FIELD_ftsf82ae_slot1, - FIELD_ftsf84ae_slot1, - FIELD_ftsf86ae_slot1, - FIELD_ftsf87ae_slot1, - FIELD_ftsf88ae_slot1, - FIELD_ftsf89ae_slot1, - FIELD_ftsf90ae_slot1, - FIELD_ftsf91ae_slot1, - FIELD_ftsf92ae_slot1, - FIELD_ftsf94ae_slot1, - FIELD_ftsf96ae_slot1, - FIELD_ftsf97ae_slot1, - FIELD_ftsf98ae_slot1, - FIELD_ftsf99ae_slot1, - FIELD_ftsf100ae_slot1, - FIELD_ftsf101ae_slot1, - FIELD_ftsf103ae_slot1, - FIELD_ftsf104ae_slot1, - FIELD_ftsf105ae_slot1, - FIELD_ftsf106ae_slot1, - FIELD_ftsf107ae_slot1, - FIELD_ftsf108ae_slot1, - FIELD_ftsf109ae_slot1, - FIELD_ftsf110ae_slot1, - FIELD_ftsf111ae_slot1, - FIELD_ftsf112ae_slot1, - FIELD_ftsf113ae_slot1, - FIELD_ftsf114ae_slot1, - FIELD_ftsf115ae_slot1, - FIELD_ftsf116ae_slot1, - FIELD_ftsf118ae_slot1, - FIELD_ftsf119ae_slot1, - FIELD_ftsf120ae_slot1, - FIELD_ftsf122ae_slot1, - FIELD_ftsf124ae_slot1, - FIELD_ftsf125ae_slot1, - FIELD_ftsf126ae_slot1, - FIELD_ftsf127ae_slot1, - FIELD_ftsf128ae_slot1, - FIELD_ftsf129ae_slot1, - FIELD_ftsf130ae_slot1, - FIELD_ftsf131ae_slot1, - FIELD_ftsf132ae_slot1, - FIELD_ftsf133ae_slot1, - FIELD_ftsf134ae_slot1, - FIELD_ftsf135ae_slot1, - FIELD_ftsf136ae_slot1, - FIELD_ftsf137ae_slot1, - FIELD_ftsf138ae_slot1, - FIELD_ftsf139ae_slot1, - FIELD_ftsf140ae_slot1, - FIELD_ftsf141ae_slot1, - FIELD_ftsf142ae_slot1, - FIELD_ftsf143ae_slot1, - FIELD_ftsf144ae_slot1, - FIELD_ftsf145ae_slot1, - FIELD_ftsf146ae_slot1, - FIELD_ftsf147ae_slot1, - FIELD_ftsf148ae_slot1, - FIELD_ftsf149ae_slot1, - FIELD_ftsf150ae_slot1, - FIELD_ftsf151ae_slot1, - FIELD_ftsf152ae_slot1, - FIELD_ftsf153ae_slot1, - FIELD_ftsf154ae_slot1, - FIELD_ftsf155ae_slot1, - FIELD_ftsf156ae_slot1, - FIELD_ftsf157ae_slot1, - FIELD_ftsf158ae_slot1, - FIELD_ftsf159ae_slot1, - FIELD_ftsf160ae_slot1, - FIELD_ftsf161ae_slot1, - FIELD_ftsf162ae_slot1, - FIELD_ftsf163ae_slot1, - FIELD_ftsf164ae_slot1, - FIELD_ftsf165ae_slot1, - FIELD_ftsf166ae_slot1, - FIELD_ftsf167ae_slot1, - FIELD_ftsf168ae_slot1, - FIELD_ftsf169ae_slot1, - FIELD_ftsf170ae_slot1, - FIELD_ftsf171ae_slot1, - FIELD_ftsf172ae_slot1, - FIELD_ftsf173ae_slot1, - FIELD_ftsf174ae_slot1, - FIELD_ftsf175ae_slot1, - FIELD_ftsf176ae_slot1, - FIELD_ftsf177ae_slot1, - FIELD_ftsf178ae_slot1, - FIELD_ftsf179ae_slot1, - FIELD_ftsf180ae_slot1, - FIELD_ftsf181ae_slot1, - FIELD_ftsf182ae_slot1, - FIELD_ftsf183ae_slot1, - FIELD_ftsf184ae_slot1, - FIELD_ftsf185ae_slot1, - FIELD_ftsf186ae_slot1, - FIELD_ftsf187ae_slot1, - FIELD_ftsf188ae_slot1, - FIELD_ftsf189ae_slot1, - FIELD_ftsf190ae_slot1, - FIELD_ftsf191ae_slot1, - FIELD_ftsf192ae_slot1, - FIELD_ftsf193ae_slot1, - FIELD_ftsf194ae_slot1, - FIELD_ftsf195ae_slot1, - FIELD_ftsf196ae_slot1, - FIELD_ftsf197ae_slot1, - FIELD_ftsf198ae_slot1, - FIELD_ftsf199ae_slot1, - FIELD_ftsf200ae_slot1, - FIELD_ftsf201ae_slot1, - FIELD_ftsf202ae_slot1, - FIELD_ftsf203ae_slot1, - FIELD_ftsf204ae_slot1, - FIELD_ftsf205ae_slot1, - FIELD_ftsf206ae_slot1, - FIELD_ftsf207ae_slot1, - FIELD_ftsf208, - FIELD_ftsf209ae_slot1, - FIELD_ftsf210ae_slot1, - FIELD_ftsf211ae_slot1, - FIELD_ftsf330ae_slot1, - FIELD_ftsf332ae_slot1, - FIELD_ftsf334ae_slot1, - FIELD_ftsf336ae_slot1, - FIELD_ftsf337ae_slot1, - FIELD_ftsf338, - FIELD_ftsf339ae_slot1, - FIELD_ftsf340, - FIELD_ftsf341ae_slot1, - FIELD_ftsf342ae_slot1, - FIELD_ftsf343ae_slot1, - FIELD_ftsf344ae_slot1, - FIELD_ftsf346ae_slot1, - FIELD_ftsf347, - FIELD_ftsf348ae_slot1, - FIELD_ftsf349ae_slot1, - FIELD_ftsf350ae_slot1, - FIELD_op0_s4, - FIELD_ftsf212ae_slot0, - FIELD_ftsf213ae_slot0, - FIELD_ftsf214ae_slot0, - FIELD_ftsf215ae_slot0, - FIELD_ftsf216ae_slot0, - FIELD_ftsf217, - FIELD_ftsf218ae_slot0, - FIELD_ftsf219ae_slot0, - FIELD_ftsf220ae_slot0, - FIELD_ftsf221ae_slot0, - FIELD_ftsf222ae_slot0, - FIELD_ftsf223ae_slot0, - FIELD_ftsf224ae_slot0, - FIELD_ftsf225ae_slot0, - FIELD_ftsf226ae_slot0, - FIELD_ftsf227ae_slot0, - FIELD_ftsf228ae_slot0, - FIELD_ftsf229ae_slot0, - FIELD_ftsf230ae_slot0, - FIELD_ftsf231ae_slot0, - FIELD_ftsf232ae_slot0, - FIELD_ftsf233ae_slot0, - FIELD_ftsf234ae_slot0, - FIELD_ftsf235ae_slot0, - FIELD_ftsf236ae_slot0, - FIELD_ftsf237ae_slot0, - FIELD_ftsf238ae_slot0, - FIELD_ftsf239ae_slot0, - FIELD_ftsf240ae_slot0, - FIELD_ftsf241ae_slot0, - FIELD_ftsf242ae_slot0, - FIELD_ftsf243ae_slot0, - FIELD_ftsf244ae_slot0, - FIELD_ftsf245ae_slot0, - FIELD_ftsf246ae_slot0, - FIELD_ftsf247ae_slot0, - FIELD_ftsf248ae_slot0, - FIELD_ftsf249ae_slot0, - FIELD_ftsf250ae_slot0, - FIELD_ftsf251ae_slot0, - FIELD_ftsf252ae_slot0, - FIELD_ftsf253ae_slot0, - FIELD_ftsf254ae_slot0, - FIELD_ftsf255ae_slot0, - FIELD_ftsf256ae_slot0, - FIELD_ftsf257ae_slot0, - FIELD_ftsf258ae_slot0, - FIELD_ftsf259ae_slot0, - FIELD_ftsf260ae_slot0, - FIELD_ftsf261ae_slot0, - FIELD_ftsf262ae_slot0, - FIELD_ftsf263ae_slot0, - FIELD_ftsf264ae_slot0, - FIELD_ftsf265ae_slot0, - FIELD_ftsf266ae_slot0, - FIELD_ftsf267ae_slot0, - FIELD_ftsf268ae_slot0, - FIELD_ftsf269ae_slot0, - FIELD_ftsf270ae_slot0, - FIELD_ftsf271ae_slot0, - FIELD_ftsf272ae_slot0, - FIELD_ftsf273ae_slot0, - FIELD_ftsf274ae_slot0, - FIELD_ftsf275ae_slot0, - FIELD_ftsf276ae_slot0, - FIELD_ftsf277ae_slot0, - FIELD_ftsf278ae_slot0, - FIELD_ftsf279ae_slot0, - FIELD_ftsf281ae_slot0, - FIELD_ftsf282ae_slot0, - FIELD_ftsf283ae_slot0, - FIELD_ftsf284ae_slot0, - FIELD_ftsf286ae_slot0, - FIELD_ftsf288ae_slot0, - FIELD_ftsf290ae_slot0, - FIELD_ftsf292ae_slot0, - FIELD_ftsf293, - FIELD_ftsf294ae_slot0, - FIELD_ftsf295ae_slot0, - FIELD_ftsf296ae_slot0, - FIELD_ftsf297ae_slot0, - FIELD_ftsf298ae_slot0, - FIELD_ftsf299ae_slot0, - FIELD_ftsf300ae_slot0, - FIELD_ftsf301ae_slot0, - FIELD_ftsf302ae_slot0, - FIELD_ftsf303ae_slot0, - FIELD_ftsf304ae_slot0, - FIELD_ftsf306ae_slot0, - FIELD_ftsf308ae_slot0, - FIELD_ftsf309ae_slot0, - FIELD_ftsf310ae_slot0, - FIELD_ftsf311ae_slot0, - FIELD_ftsf312ae_slot0, - FIELD_ftsf313ae_slot0, - FIELD_ftsf314ae_slot0, - FIELD_ftsf315ae_slot0, - FIELD_ftsf316ae_slot0, - FIELD_ftsf317ae_slot0, - FIELD_ftsf318ae_slot0, - FIELD_ftsf319, - FIELD_ftsf320ae_slot0, - FIELD_ftsf321, - FIELD_ftsf322ae_slot0, - FIELD_ftsf323ae_slot0, - FIELD_ftsf324ae_slot0, - FIELD_ftsf325ae_slot0, - FIELD_ftsf326ae_slot0, - FIELD_ftsf328ae_slot0, - FIELD_ftsf329ae_slot0, - FIELD_ftsf352ae_slot0, - FIELD_ftsf353, - FIELD_ftsf354ae_slot0, - FIELD_ftsf356ae_slot0, - FIELD_ftsf357, - FIELD_ftsf358ae_slot0, - FIELD_ftsf359ae_slot0, - FIELD_ftsf360ae_slot0, - FIELD_ftsf361ae_slot0, - FIELD_ftsf362ae_slot0, - FIELD_ftsf364ae_slot0, - FIELD_ftsf365ae_slot0, - FIELD_ftsf366ae_slot0, - FIELD_ftsf368ae_slot0, - FIELD_ftsf369ae_slot0, - FIELD__ar0, - FIELD__ar4, - FIELD__ar8, - FIELD__ar12, - FIELD__bt16, - FIELD__bs16, - FIELD__br16, - FIELD__brall -}; - - -/* Functional units. */ - -static xtensa_funcUnit_internal funcUnits[] = { - { "ae_add32", 1 }, - { "ae_shift32x4", 1 }, - { "ae_shift32x5", 1 }, - { "ae_subshift", 1 } -}; - -enum xtensa_funcUnit_id { - FUNCUNIT_ae_add32, - FUNCUNIT_ae_shift32x4, - FUNCUNIT_ae_shift32x5, - FUNCUNIT_ae_subshift -}; - - -/* Register files. */ - -enum xtensa_regfile_id { - REGFILE_AR, - REGFILE_BR, - REGFILE_AE_PR, - REGFILE_AE_QR, - REGFILE_BR2, - REGFILE_BR4, - REGFILE_BR8, - REGFILE_BR16 -}; - -static xtensa_regfile_internal regfiles[] = { - { "AR", "a", REGFILE_AR, 32, 32 }, - { "BR", "b", REGFILE_BR, 1, 16 }, - { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, - { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, - { "BR2", "b", REGFILE_BR, 2, 8 }, - { "BR4", "b", REGFILE_BR, 4, 4 }, - { "BR8", "b", REGFILE_BR, 8, 2 }, - { "BR16", "b", REGFILE_BR, 16, 1 } -}; - - -/* Interfaces. */ - -static xtensa_interface_internal interfaces[] = { - { "RMPINT_Out", 12, 0, 0, 'o' }, - { "RMPINT_In", 32, 0, 1, 'i' } -}; - -enum xtensa_interface_id { - INTERFACE_RMPINT_Out, - INTERFACE_RMPINT_In -}; - - -/* Constant tables. */ - -/* constant table ai4c */ -static const unsigned CONST_TBL_ai4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0x9, - 0xa, - 0xb, - 0xc, - 0xd, - 0xe, - 0xf, - 0 -}; - -/* constant table b4c */ -static const unsigned CONST_TBL_b4c_0[] = { - 0xffffffff, - 0x1, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - -/* constant table b4cu */ -static const unsigned CONST_TBL_b4cu_0[] = { - 0x8000, - 0x10000, - 0x2, - 0x3, - 0x4, - 0x5, - 0x6, - 0x7, - 0x8, - 0xa, - 0xc, - 0x10, - 0x20, - 0x40, - 0x80, - 0x100, - 0 -}; - - -/* Instruction operands. */ - -static int -OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_out_0; - unsigned soffsetx4_in_0; - soffsetx4_in_0 = *valp & 0x3ffff; - soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); - *valp = soffsetx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) -{ - unsigned soffsetx4_in_0; - unsigned soffsetx4_out_0; - soffsetx4_out_0 = *valp; - soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; - *valp = soffsetx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) -{ - unsigned uimm12x8_out_0; - unsigned uimm12x8_in_0; - uimm12x8_in_0 = *valp & 0xfff; - uimm12x8_out_0 = uimm12x8_in_0 << 3; - *valp = uimm12x8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) -{ - unsigned uimm12x8_in_0; - unsigned uimm12x8_out_0; - uimm12x8_out_0 = *valp; - uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); - *valp = uimm12x8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_decode (uint32 *valp) -{ - unsigned simm4_out_0; - unsigned simm4_in_0; - simm4_in_0 = *valp & 0xf; - simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; - *valp = simm4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm4_encode (uint32 *valp) -{ - unsigned simm4_in_0; - unsigned simm4_out_0; - simm4_out_0 = *valp; - simm4_in_0 = (simm4_out_0 & 0xf); - *valp = simm4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_0_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_1_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_3_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AR_4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 32); - return error; -} - -static int -OperandSem_opnd_sem_immrx4_decode (uint32 *valp) -{ - unsigned immrx4_out_0; - unsigned immrx4_in_0; - immrx4_in_0 = *valp & 0xf; - immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; - *valp = immrx4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immrx4_encode (uint32 *valp) -{ - unsigned immrx4_in_0; - unsigned immrx4_out_0; - immrx4_out_0 = *valp; - immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); - *valp = immrx4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) -{ - unsigned lsi4x4_out_0; - unsigned lsi4x4_in_0; - lsi4x4_in_0 = *valp & 0xf; - lsi4x4_out_0 = lsi4x4_in_0 << 2; - *valp = lsi4x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) -{ - unsigned lsi4x4_in_0; - unsigned lsi4x4_out_0; - lsi4x4_out_0 = *valp; - lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); - *valp = lsi4x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_decode (uint32 *valp) -{ - unsigned simm7_out_0; - unsigned simm7_in_0; - simm7_in_0 = *valp & 0x7f; - simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; - *valp = simm7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm7_encode (uint32 *valp) -{ - unsigned simm7_in_0; - unsigned simm7_out_0; - simm7_out_0 = *valp; - simm7_in_0 = (simm7_out_0 & 0x7f); - *valp = simm7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_decode (uint32 *valp) -{ - unsigned uimm6_out_0; - unsigned uimm6_in_0; - uimm6_in_0 = *valp & 0x3f; - uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); - *valp = uimm6_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm6_encode (uint32 *valp) -{ - unsigned uimm6_in_0; - unsigned uimm6_out_0; - uimm6_out_0 = *valp; - uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; - *valp = uimm6_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_out_0; - unsigned ai4const_in_0; - ai4const_in_0 = *valp & 0xf; - ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; - *valp = ai4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ai4const_encode (uint32 *valp) -{ - unsigned ai4const_in_0; - unsigned ai4const_out_0; - ai4const_out_0 = *valp; - switch (ai4const_out_0) - { - case 0xffffffff: ai4const_in_0 = 0; break; - case 0x1: ai4const_in_0 = 0x1; break; - case 0x2: ai4const_in_0 = 0x2; break; - case 0x3: ai4const_in_0 = 0x3; break; - case 0x4: ai4const_in_0 = 0x4; break; - case 0x5: ai4const_in_0 = 0x5; break; - case 0x6: ai4const_in_0 = 0x6; break; - case 0x7: ai4const_in_0 = 0x7; break; - case 0x8: ai4const_in_0 = 0x8; break; - case 0x9: ai4const_in_0 = 0x9; break; - case 0xa: ai4const_in_0 = 0xa; break; - case 0xb: ai4const_in_0 = 0xb; break; - case 0xc: ai4const_in_0 = 0xc; break; - case 0xd: ai4const_in_0 = 0xd; break; - case 0xe: ai4const_in_0 = 0xe; break; - default: ai4const_in_0 = 0xf; break; - } - *valp = ai4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_decode (uint32 *valp) -{ - unsigned b4const_out_0; - unsigned b4const_in_0; - b4const_in_0 = *valp & 0xf; - b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; - *valp = b4const_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4const_encode (uint32 *valp) -{ - unsigned b4const_in_0; - unsigned b4const_out_0; - b4const_out_0 = *valp; - switch (b4const_out_0) - { - case 0xffffffff: b4const_in_0 = 0; break; - case 0x1: b4const_in_0 = 0x1; break; - case 0x2: b4const_in_0 = 0x2; break; - case 0x3: b4const_in_0 = 0x3; break; - case 0x4: b4const_in_0 = 0x4; break; - case 0x5: b4const_in_0 = 0x5; break; - case 0x6: b4const_in_0 = 0x6; break; - case 0x7: b4const_in_0 = 0x7; break; - case 0x8: b4const_in_0 = 0x8; break; - case 0xa: b4const_in_0 = 0x9; break; - case 0xc: b4const_in_0 = 0xa; break; - case 0x10: b4const_in_0 = 0xb; break; - case 0x20: b4const_in_0 = 0xc; break; - case 0x40: b4const_in_0 = 0xd; break; - case 0x80: b4const_in_0 = 0xe; break; - default: b4const_in_0 = 0xf; break; - } - *valp = b4const_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_decode (uint32 *valp) -{ - unsigned b4constu_out_0; - unsigned b4constu_in_0; - b4constu_in_0 = *valp & 0xf; - b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; - *valp = b4constu_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_b4constu_encode (uint32 *valp) -{ - unsigned b4constu_in_0; - unsigned b4constu_out_0; - b4constu_out_0 = *valp; - switch (b4constu_out_0) - { - case 0x8000: b4constu_in_0 = 0; break; - case 0x10000: b4constu_in_0 = 0x1; break; - case 0x2: b4constu_in_0 = 0x2; break; - case 0x3: b4constu_in_0 = 0x3; break; - case 0x4: b4constu_in_0 = 0x4; break; - case 0x5: b4constu_in_0 = 0x5; break; - case 0x6: b4constu_in_0 = 0x6; break; - case 0x7: b4constu_in_0 = 0x7; break; - case 0x8: b4constu_in_0 = 0x8; break; - case 0xa: b4constu_in_0 = 0x9; break; - case 0xc: b4constu_in_0 = 0xa; break; - case 0x10: b4constu_in_0 = 0xb; break; - case 0x20: b4constu_in_0 = 0xc; break; - case 0x40: b4constu_in_0 = 0xd; break; - case 0x80: b4constu_in_0 = 0xe; break; - default: b4constu_in_0 = 0xf; break; - } - *valp = b4constu_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_out_0; - unsigned uimm8_in_0; - uimm8_in_0 = *valp & 0xff; - uimm8_out_0 = uimm8_in_0; - *valp = uimm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8_encode (uint32 *valp) -{ - unsigned uimm8_in_0; - unsigned uimm8_out_0; - uimm8_out_0 = *valp; - uimm8_in_0 = (uimm8_out_0 & 0xff); - *valp = uimm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) -{ - unsigned uimm8x2_out_0; - unsigned uimm8x2_in_0; - uimm8x2_in_0 = *valp & 0xff; - uimm8x2_out_0 = uimm8x2_in_0 << 1; - *valp = uimm8x2_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) -{ - unsigned uimm8x2_in_0; - unsigned uimm8x2_out_0; - uimm8x2_out_0 = *valp; - uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); - *valp = uimm8x2_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) -{ - unsigned uimm8x4_out_0; - unsigned uimm8x4_in_0; - uimm8x4_in_0 = *valp & 0xff; - uimm8x4_out_0 = uimm8x4_in_0 << 2; - *valp = uimm8x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) -{ - unsigned uimm8x4_in_0; - unsigned uimm8x4_out_0; - uimm8x4_out_0 = *valp; - uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); - *valp = uimm8x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) -{ - unsigned uimm4x16_out_0; - unsigned uimm4x16_in_0; - uimm4x16_in_0 = *valp & 0xf; - uimm4x16_out_0 = uimm4x16_in_0 << 4; - *valp = uimm4x16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) -{ - unsigned uimm4x16_in_0; - unsigned uimm4x16_out_0; - uimm4x16_out_0 = *valp; - uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); - *valp = uimm4x16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_decode (uint32 *valp) -{ - unsigned simm8_out_0; - unsigned simm8_in_0; - simm8_in_0 = *valp & 0xff; - simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; - *valp = simm8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8_encode (uint32 *valp) -{ - unsigned simm8_in_0; - unsigned simm8_out_0; - simm8_out_0 = *valp; - simm8_in_0 = (simm8_out_0 & 0xff); - *valp = simm8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) -{ - unsigned simm8x256_out_0; - unsigned simm8x256_in_0; - simm8x256_in_0 = *valp & 0xff; - simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; - *valp = simm8x256_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) -{ - unsigned simm8x256_in_0; - unsigned simm8x256_out_0; - simm8x256_out_0 = *valp; - simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); - *valp = simm8x256_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_out_0; - unsigned simm12b_in_0; - simm12b_in_0 = *valp & 0xfff; - simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; - *valp = simm12b_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_simm12b_encode (uint32 *valp) -{ - unsigned simm12b_in_0; - unsigned simm12b_out_0; - simm12b_out_0 = *valp; - simm12b_in_0 = (simm12b_out_0 & 0xfff); - *valp = simm12b_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_out_0; - unsigned msalp32_in_0; - msalp32_in_0 = *valp & 0x1f; - msalp32_out_0 = 0x20 - msalp32_in_0; - *valp = msalp32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_msalp32_encode (uint32 *valp) -{ - unsigned msalp32_in_0; - unsigned msalp32_out_0; - msalp32_out_0 = *valp; - msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; - *valp = msalp32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_out_0; - unsigned op2p1_in_0; - op2p1_in_0 = *valp & 0xf; - op2p1_out_0 = op2p1_in_0 + 0x1; - *valp = op2p1_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_op2p1_encode (uint32 *valp) -{ - unsigned op2p1_in_0; - unsigned op2p1_out_0; - op2p1_out_0 = *valp; - op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; - *valp = op2p1_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_decode (uint32 *valp) -{ - unsigned label8_out_0; - unsigned label8_in_0; - label8_in_0 = *valp & 0xff; - label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); - *valp = label8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label8_encode (uint32 *valp) -{ - unsigned label8_in_0; - unsigned label8_out_0; - label8_out_0 = *valp; - label8_in_0 = (label8_out_0 - 0x4) & 0xff; - *valp = label8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) -{ - unsigned ulabel8_out_0; - unsigned ulabel8_in_0; - ulabel8_in_0 = *valp & 0xff; - ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); - *valp = ulabel8_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) -{ - unsigned ulabel8_in_0; - unsigned ulabel8_out_0; - ulabel8_out_0 = *valp; - ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; - *valp = ulabel8_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_decode (uint32 *valp) -{ - unsigned label12_out_0; - unsigned label12_in_0; - label12_in_0 = *valp & 0xfff; - label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); - *valp = label12_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_label12_encode (uint32 *valp) -{ - unsigned label12_in_0; - unsigned label12_out_0; - label12_out_0 = *valp; - label12_in_0 = (label12_out_0 - 0x4) & 0xfff; - *valp = label12_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_decode (uint32 *valp) -{ - unsigned soffset_out_0; - unsigned soffset_in_0; - soffset_in_0 = *valp & 0x3ffff; - soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); - *valp = soffset_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_soffset_encode (uint32 *valp) -{ - unsigned soffset_in_0; - unsigned soffset_out_0; - soffset_out_0 = *valp; - soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; - *valp = soffset_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) -{ - unsigned uimm16x4_out_0; - unsigned uimm16x4_in_0; - uimm16x4_in_0 = *valp & 0xffff; - uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; - *valp = uimm16x4_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) -{ - unsigned uimm16x4_in_0; - unsigned uimm16x4_out_0; - uimm16x4_out_0 = *valp; - uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; - *valp = uimm16x4_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_decode (uint32 *valp) -{ - unsigned bbi_out_0; - unsigned bbi_in_0; - bbi_in_0 = *valp & 0x1f; - bbi_out_0 = (0 << 5) | bbi_in_0; - *valp = bbi_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_bbi_encode (uint32 *valp) -{ - unsigned bbi_in_0; - unsigned bbi_out_0; - bbi_out_0 = *valp; - bbi_in_0 = (bbi_out_0 & 0x1f); - *valp = bbi_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_decode (uint32 *valp) -{ - unsigned s_out_0; - unsigned s_in_0; - s_in_0 = *valp & 0xf; - s_out_0 = (0 << 4) | s_in_0; - *valp = s_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_s_encode (uint32 *valp) -{ - unsigned s_in_0; - unsigned s_out_0; - s_out_0 = *valp; - s_in_0 = (s_out_0 & 0xf); - *valp = s_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_decode (uint32 *valp) -{ - unsigned immt_out_0; - unsigned immt_in_0; - immt_in_0 = *valp & 0xf; - immt_out_0 = immt_in_0; - *valp = immt_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_immt_encode (uint32 *valp) -{ - unsigned immt_in_0; - unsigned immt_out_0; - immt_out_0 = *valp; - immt_in_0 = immt_out_0 & 0xf; - *valp = immt_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_BR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16); - return error; -} - -static int -OperandSem_opnd_sem_BR2_decode (uint32 *valp) -{ - *valp = *valp << 1; - return 0; -} - -static int -OperandSem_opnd_sem_BR2_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 1) != 0); - *valp = *valp >> 1; - return error; -} - -static int -OperandSem_opnd_sem_BR4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -OperandSem_opnd_sem_BR4_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 3) != 0); - *valp = *valp >> 2; - return error; -} - -static int -OperandSem_opnd_sem_BR8_decode (uint32 *valp) -{ - *valp = *valp << 3; - return 0; -} - -static int -OperandSem_opnd_sem_BR8_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 7) != 0); - *valp = *valp >> 3; - return error; -} - -static int -OperandSem_opnd_sem_BR16_decode (uint32 *valp) -{ - *valp = *valp << 4; - return 0; -} - -static int -OperandSem_opnd_sem_BR16_encode (uint32 *valp) -{ - int error; - error = (*valp >= 16) || ((*valp & 15) != 0); - *valp = *valp >> 4; - return error; -} - -static int -OperandSem_opnd_sem_tp7_decode (uint32 *valp) -{ - unsigned tp7_out_0; - unsigned tp7_in_0; - tp7_in_0 = *valp & 0xf; - tp7_out_0 = tp7_in_0 + 0x7; - *valp = tp7_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_tp7_encode (uint32 *valp) -{ - unsigned tp7_in_0; - unsigned tp7_out_0; - tp7_out_0 = *valp; - tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; - *valp = tp7_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) -{ - unsigned xt_wbr15_label_out_0; - unsigned xt_wbr15_label_in_0; - xt_wbr15_label_in_0 = *valp & 0x7fff; - xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); - *valp = xt_wbr15_label_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) -{ - unsigned xt_wbr15_label_in_0; - unsigned xt_wbr15_label_out_0; - xt_wbr15_label_out_0 = *valp; - xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_label_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) -{ - unsigned ae_samt32_out_0; - unsigned ae_samt32_in_0; - ae_samt32_in_0 = *valp & 0x1f; - ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; - *valp = ae_samt32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) -{ - unsigned ae_samt32_in_0; - unsigned ae_samt32_out_0; - ae_samt32_out_0 = *valp; - ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); - *valp = ae_samt32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 8); - return error; -} - -static int -OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) -{ - return 0; -} - -static int -OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) -{ - int error; - error = (*valp >= 4); - return error; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) -{ - unsigned ae_lsimm16_out_0; - unsigned ae_lsimm16_in_0; - ae_lsimm16_in_0 = *valp & 0xf; - ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) -{ - unsigned ae_lsimm16_in_0; - unsigned ae_lsimm16_out_0; - ae_lsimm16_out_0 = *valp; - ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); - *valp = ae_lsimm16_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) -{ - unsigned ae_lsimm32_out_0; - unsigned ae_lsimm32_in_0; - ae_lsimm32_in_0 = *valp & 0xf; - ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) -{ - unsigned ae_lsimm32_in_0; - unsigned ae_lsimm32_out_0; - ae_lsimm32_out_0 = *valp; - ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); - *valp = ae_lsimm32_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) -{ - unsigned ae_lsimm64_out_0; - unsigned ae_lsimm64_in_0; - ae_lsimm64_in_0 = *valp & 0xf; - ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) -{ - unsigned ae_lsimm64_in_0; - unsigned ae_lsimm64_out_0; - ae_lsimm64_out_0 = *valp; - ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); - *valp = ae_lsimm64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) -{ - unsigned ae_samt64_out_0; - unsigned ae_samt64_in_0; - ae_samt64_in_0 = *valp & 0x3f; - ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; - *valp = ae_samt64_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) -{ - unsigned ae_samt64_in_0; - unsigned ae_samt64_out_0; - ae_samt64_out_0 = *valp; - ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); - *valp = ae_samt64_in_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) -{ - unsigned ae_ohba_out_0; - unsigned ae_ohba_in_0; - ae_ohba_in_0 = *valp & 0xf; - ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); - *valp = ae_ohba_out_0; - return 0; -} - -static int -OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) -{ - unsigned ae_ohba_in_0; - unsigned ae_ohba_out_0; - ae_ohba_out_0 = *valp; - ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); - *valp = ae_ohba_in_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_label12_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_soffset_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) -{ - *valp -= ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += ((pc + 3) & ~0x3); - return 0; -} - -static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) -{ - *valp += pc; - return 0; -} - -static xtensa_operand_internal operands[] = { - { "soffsetx4", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, - { "uimm12x8", FIELD_imm12, -1, 0, - 0, - OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, - 0, 0 }, - { "simm4", FIELD_mn, -1, 0, - 0, - OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, - 0, 0 }, - { "arr", FIELD_r, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ars", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "*ars_invisible", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "art", FIELD_t, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, - 0, 0 }, - { "ar0", FIELD__ar0, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, - 0, 0 }, - { "ar4", FIELD__ar4, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, - 0, 0 }, - { "ar8", FIELD__ar8, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, - 0, 0 }, - { "ar12", FIELD__ar12, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, - 0, 0 }, - { "ars_entry", FIELD_s, REGFILE_AR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, - 0, 0 }, - { "immrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, - 0, 0 }, - { "lsi4x4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm7", FIELD_imm7, -1, 0, - 0, - OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, - 0, 0 }, - { "uimm6", FIELD_imm6, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, - Operand_uimm6_ator, Operand_uimm6_rtoa }, - { "ai4const", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, - 0, 0 }, - { "b4const", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, - 0, 0 }, - { "b4constu", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, - 0, 0 }, - { "uimm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, - 0, 0 }, - { "uimm8x2", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, - 0, 0 }, - { "uimm8x4", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, - 0, 0 }, - { "uimm4x16", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, - 0, 0 }, - { "uimmrx4", FIELD_r, -1, 0, - 0, - OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, - 0, 0 }, - { "simm8", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, - 0, 0 }, - { "simm8x256", FIELD_imm8, -1, 0, - 0, - OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, - 0, 0 }, - { "simm12b", FIELD_imm12b, -1, 0, - 0, - OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, - 0, 0 }, - { "msalp32", FIELD_sal, -1, 0, - 0, - OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, - 0, 0 }, - { "op2p1", FIELD_op2, -1, 0, - 0, - OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, - 0, 0 }, - { "label8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, - Operand_label8_ator, Operand_label8_rtoa }, - { "ulabel8", FIELD_imm8, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, - Operand_ulabel8_ator, Operand_ulabel8_rtoa }, - { "label12", FIELD_imm12, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, - Operand_label12_ator, Operand_label12_rtoa }, - { "soffset", FIELD_offset, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_soffset_ator, Operand_soffset_rtoa }, - { "uimm16x4", FIELD_imm16, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, - { "bbi", FIELD_bbi, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sae", FIELD_sae, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sas", FIELD_sas, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, - 0, - OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, - 0, 0 }, - { "s", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, - 0, 0 }, - { "immt", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "imms", FIELD_s, -1, 0, - 0, - OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, - 0, 0 }, - { "bt", FIELD_t, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bs", FIELD_s, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "br", FIELD_r, REGFILE_BR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, - 0, 0 }, - { "bt2", FIELD_t2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bs2", FIELD_s2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "br2", FIELD_r2, REGFILE_BR, 2, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, - 0, 0 }, - { "bt4", FIELD_t4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bs4", FIELD_s4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "br4", FIELD_r4, REGFILE_BR, 4, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, - 0, 0 }, - { "bt8", FIELD_t8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bs8", FIELD_s8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "br8", FIELD_r8, REGFILE_BR, 8, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, - 0, 0 }, - { "bt16", FIELD__bt16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "bs16", FIELD__bs16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "br16", FIELD__br16, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "brall", FIELD__brall, REGFILE_BR, 16, - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, - 0, 0 }, - { "tp7", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, - 0, 0 }, - { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, - { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, - XTENSA_OPERAND_IS_PCRELATIVE, - OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, - { "ae_samt32", FIELD_ftsf14, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, - 0, 0 }, - { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ae_lsimm16", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, - 0, 0 }, - { "ae_lsimm32", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, - 0, 0 }, - { "ae_lsimm64", FIELD_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, - 0, 0 }, - { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, - 0, - OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, - 0, 0 }, - { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, - 0, - OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, - 0, 0 }, - { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, - 0, 0 }, - { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, - XTENSA_OPERAND_IS_REGISTER, - OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, - 0, 0 }, - { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, - { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, - { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, - { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, - { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, - { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, - { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, - { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, - { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, - { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, - { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, - { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, - { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, - { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, - { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, - { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, - { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, - { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, - { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, - { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, - { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, - { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, - { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, - { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, - { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, - { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, - { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, - { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, - { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, - { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf14", FIELD_ftsf14, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf39ae_slot1", FIELD_ftsf39ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf44ae_slot1", FIELD_ftsf44ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf46ae_slot1", FIELD_ftsf46ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf55ae_slot1", FIELD_ftsf55ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf59ae_slot1", FIELD_ftsf59ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf61ae_slot1", FIELD_ftsf61ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf67ae_slot1", FIELD_ftsf67ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf91ae_slot1", FIELD_ftsf91ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf98ae_slot1", FIELD_ftsf98ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf100ae_slot1", FIELD_ftsf100ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf104ae_slot1", FIELD_ftsf104ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf105ae_slot1", FIELD_ftsf105ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf118ae_slot1", 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FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf283ae_slot0", FIELD_ftsf283ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf286ae_slot0", FIELD_ftsf286ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf288ae_slot0", FIELD_ftsf288ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf293", FIELD_ftsf293, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf299ae_slot0", FIELD_ftsf299ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf301ae_slot0", FIELD_ftsf301ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf303ae_slot0", FIELD_ftsf303ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf309ae_slot0", FIELD_ftsf309ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf315ae_slot0", FIELD_ftsf315ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf318ae_slot0", FIELD_ftsf318ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf319", FIELD_ftsf319, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf321", FIELD_ftsf321, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf352ae_slot0", FIELD_ftsf352ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf353", FIELD_ftsf353, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf354ae_slot0", FIELD_ftsf354ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf356ae_slot0", FIELD_ftsf356ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf357", FIELD_ftsf357, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf358ae_slot0", FIELD_ftsf358ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf359ae_slot0", FIELD_ftsf359ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf362ae_slot0", FIELD_ftsf362ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf365ae_slot0", FIELD_ftsf365ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, - { "ftsf369ae_slot0", FIELD_ftsf369ae_slot0, -1, 0, 0, 0, 0, 0, 0 } -}; - -enum xtensa_operand_id { - OPERAND_soffsetx4, - OPERAND_uimm12x8, - OPERAND_simm4, - OPERAND_arr, - OPERAND_ars, - OPERAND__ars_invisible, - OPERAND_art, - OPERAND_ar0, - OPERAND_ar4, - OPERAND_ar8, - OPERAND_ar12, - OPERAND_ars_entry, - OPERAND_immrx4, - OPERAND_lsi4x4, - OPERAND_simm7, - OPERAND_uimm6, - OPERAND_ai4const, - OPERAND_b4const, - OPERAND_b4constu, - OPERAND_uimm8, - OPERAND_uimm8x2, - OPERAND_uimm8x4, - OPERAND_uimm4x16, - OPERAND_uimmrx4, - OPERAND_simm8, - OPERAND_simm8x256, - OPERAND_simm12b, - OPERAND_msalp32, - OPERAND_op2p1, - OPERAND_label8, - OPERAND_ulabel8, - OPERAND_label12, - OPERAND_soffset, - OPERAND_uimm16x4, - OPERAND_bbi, - OPERAND_sae, - OPERAND_sas, - OPERAND_sargt, - OPERAND_s, - OPERAND_immt, - OPERAND_imms, - OPERAND_bt, - OPERAND_bs, - OPERAND_br, - OPERAND_bt2, - OPERAND_bs2, - OPERAND_br2, - OPERAND_bt4, - OPERAND_bs4, - OPERAND_br4, - OPERAND_bt8, - OPERAND_bs8, - OPERAND_br8, - OPERAND_bt16, - OPERAND_bs16, - OPERAND_br16, - OPERAND_brall, - OPERAND_tp7, - OPERAND_xt_wbr15_label, - OPERAND_xt_wbr18_label, - OPERAND_ae_samt32, - OPERAND_pr0, - OPERAND_qr0, - OPERAND_mac_qr0, - OPERAND_ae_lsimm16, - OPERAND_ae_lsimm32, - OPERAND_ae_lsimm64, - OPERAND_ae_samt64, - OPERAND_ae_ohba, - OPERAND_ae_ohba2, - OPERAND_pr, - OPERAND_cvt_pr, - OPERAND_qr0_rw, - OPERAND_mac_qr0_rw, - OPERAND_qr1_w, - OPERAND_mac_qr1_w, - OPERAND_ps, - OPERAND_alupppb_ps, - OPERAND_t, - OPERAND_bbi4, - OPERAND_imm12, - OPERAND_imm8, - OPERAND_imm12b, - OPERAND_imm16, - OPERAND_m, - OPERAND_n, - OPERAND_offset, - OPERAND_op0, - OPERAND_op1, - OPERAND_op2, - OPERAND_r, - OPERAND_sa4, - OPERAND_sae4, - OPERAND_sal, - OPERAND_sas4, - OPERAND_sr, - OPERAND_st, - OPERAND_thi3, - OPERAND_imm4, - OPERAND_mn, - OPERAND_i, - OPERAND_imm6lo, - OPERAND_imm6hi, - OPERAND_imm7lo, - OPERAND_imm7hi, - OPERAND_z, - OPERAND_imm6, - OPERAND_imm7, - OPERAND_t2, - OPERAND_s2, - OPERAND_r2, - OPERAND_t4, - OPERAND_s4, - OPERAND_r4, - OPERAND_t8, - OPERAND_s8, - OPERAND_r8, - OPERAND_xt_wbr15_imm, - OPERAND_xt_wbr18_imm, - OPERAND_ae_r3, - OPERAND_ae_s_non_samt, - OPERAND_ae_s3, - OPERAND_ae_r32, - OPERAND_ae_samt_s_t, - OPERAND_ae_r20, - OPERAND_ae_r10, - OPERAND_ae_s20, - OPERAND_ae_fld_ohba, - OPERAND_ae_fld_ohba2, - OPERAND_op0_s3, - OPERAND_ftsf12, - OPERAND_ftsf13, - OPERAND_ftsf14, - OPERAND_ftsf21ae_slot1, - OPERAND_ftsf22ae_slot1, - OPERAND_ftsf23ae_slot1, - OPERAND_ftsf24ae_slot1, - OPERAND_ftsf25ae_slot1, - OPERAND_ftsf26ae_slot1, - OPERAND_ftsf27ae_slot1, - OPERAND_ftsf28ae_slot1, - OPERAND_ftsf29ae_slot1, - OPERAND_ftsf30ae_slot1, - OPERAND_ftsf31ae_slot1, - OPERAND_ftsf32ae_slot1, - OPERAND_ftsf33ae_slot1, - OPERAND_ftsf34ae_slot1, - OPERAND_ftsf35ae_slot1, - OPERAND_ftsf36ae_slot1, - OPERAND_ftsf37ae_slot1, - OPERAND_ftsf38ae_slot1, - OPERAND_ftsf39ae_slot1, - OPERAND_ftsf40ae_slot1, - OPERAND_ftsf41ae_slot1, - OPERAND_ftsf42ae_slot1, - OPERAND_ftsf43ae_slot1, - OPERAND_ftsf44ae_slot1, - OPERAND_ftsf45ae_slot1, - OPERAND_ftsf46ae_slot1, - OPERAND_ftsf47ae_slot1, - OPERAND_ftsf48ae_slot1, - OPERAND_ftsf49ae_slot1, - OPERAND_ftsf50ae_slot1, - OPERAND_ftsf51ae_slot1, - OPERAND_ftsf52ae_slot1, - OPERAND_ftsf53ae_slot1, - OPERAND_ftsf54ae_slot1, - OPERAND_ftsf55ae_slot1, - OPERAND_ftsf56ae_slot1, - OPERAND_ftsf57ae_slot1, - OPERAND_ftsf58ae_slot1, - OPERAND_ftsf59ae_slot1, - OPERAND_ftsf60ae_slot1, - OPERAND_ftsf61ae_slot1, - OPERAND_ftsf63ae_slot1, - OPERAND_ftsf64ae_slot1, - OPERAND_ftsf66ae_slot1, - OPERAND_ftsf67ae_slot1, - OPERAND_ftsf69ae_slot1, - OPERAND_ftsf71ae_slot1, - OPERAND_ftsf72ae_slot1, - OPERAND_ftsf73ae_slot1, - OPERAND_ftsf75ae_slot1, - OPERAND_ftsf76ae_slot1, - OPERAND_ftsf77ae_slot1, - OPERAND_ftsf78ae_slot1, - OPERAND_ftsf79ae_slot1, - OPERAND_ftsf80ae_slot1, - OPERAND_ftsf81ae_slot1, - OPERAND_ftsf82ae_slot1, - OPERAND_ftsf84ae_slot1, - OPERAND_ftsf86ae_slot1, - OPERAND_ftsf87ae_slot1, - OPERAND_ftsf88ae_slot1, - OPERAND_ftsf89ae_slot1, - OPERAND_ftsf90ae_slot1, - OPERAND_ftsf91ae_slot1, - OPERAND_ftsf92ae_slot1, - OPERAND_ftsf94ae_slot1, - OPERAND_ftsf96ae_slot1, - OPERAND_ftsf97ae_slot1, - OPERAND_ftsf98ae_slot1, - OPERAND_ftsf99ae_slot1, - OPERAND_ftsf100ae_slot1, - OPERAND_ftsf101ae_slot1, - OPERAND_ftsf103ae_slot1, - OPERAND_ftsf104ae_slot1, - OPERAND_ftsf105ae_slot1, - OPERAND_ftsf106ae_slot1, - OPERAND_ftsf107ae_slot1, - OPERAND_ftsf108ae_slot1, - OPERAND_ftsf109ae_slot1, - OPERAND_ftsf110ae_slot1, - OPERAND_ftsf111ae_slot1, - OPERAND_ftsf112ae_slot1, - OPERAND_ftsf113ae_slot1, - OPERAND_ftsf114ae_slot1, - OPERAND_ftsf115ae_slot1, - OPERAND_ftsf116ae_slot1, - OPERAND_ftsf118ae_slot1, - OPERAND_ftsf119ae_slot1, - OPERAND_ftsf120ae_slot1, - OPERAND_ftsf122ae_slot1, - OPERAND_ftsf124ae_slot1, - OPERAND_ftsf125ae_slot1, - OPERAND_ftsf126ae_slot1, - OPERAND_ftsf127ae_slot1, - OPERAND_ftsf128ae_slot1, - OPERAND_ftsf129ae_slot1, - OPERAND_ftsf130ae_slot1, - OPERAND_ftsf131ae_slot1, - OPERAND_ftsf132ae_slot1, - OPERAND_ftsf133ae_slot1, - OPERAND_ftsf134ae_slot1, - OPERAND_ftsf135ae_slot1, - OPERAND_ftsf136ae_slot1, - OPERAND_ftsf137ae_slot1, - OPERAND_ftsf138ae_slot1, - OPERAND_ftsf139ae_slot1, - OPERAND_ftsf140ae_slot1, - OPERAND_ftsf141ae_slot1, - OPERAND_ftsf142ae_slot1, - OPERAND_ftsf143ae_slot1, - OPERAND_ftsf144ae_slot1, - OPERAND_ftsf145ae_slot1, - OPERAND_ftsf146ae_slot1, - OPERAND_ftsf147ae_slot1, - OPERAND_ftsf148ae_slot1, - OPERAND_ftsf149ae_slot1, - OPERAND_ftsf150ae_slot1, - OPERAND_ftsf151ae_slot1, - OPERAND_ftsf152ae_slot1, - OPERAND_ftsf153ae_slot1, - OPERAND_ftsf154ae_slot1, - OPERAND_ftsf155ae_slot1, - OPERAND_ftsf156ae_slot1, - OPERAND_ftsf157ae_slot1, - OPERAND_ftsf158ae_slot1, - OPERAND_ftsf159ae_slot1, - OPERAND_ftsf160ae_slot1, - OPERAND_ftsf161ae_slot1, - OPERAND_ftsf162ae_slot1, - OPERAND_ftsf163ae_slot1, - OPERAND_ftsf164ae_slot1, - OPERAND_ftsf165ae_slot1, - OPERAND_ftsf166ae_slot1, - OPERAND_ftsf167ae_slot1, - OPERAND_ftsf168ae_slot1, - OPERAND_ftsf169ae_slot1, - OPERAND_ftsf170ae_slot1, - OPERAND_ftsf171ae_slot1, - OPERAND_ftsf172ae_slot1, - OPERAND_ftsf173ae_slot1, - OPERAND_ftsf174ae_slot1, - OPERAND_ftsf175ae_slot1, - OPERAND_ftsf176ae_slot1, - OPERAND_ftsf177ae_slot1, - OPERAND_ftsf178ae_slot1, - OPERAND_ftsf179ae_slot1, - OPERAND_ftsf180ae_slot1, - OPERAND_ftsf181ae_slot1, - OPERAND_ftsf182ae_slot1, - OPERAND_ftsf183ae_slot1, - OPERAND_ftsf184ae_slot1, - OPERAND_ftsf185ae_slot1, - OPERAND_ftsf186ae_slot1, - OPERAND_ftsf187ae_slot1, - OPERAND_ftsf188ae_slot1, - OPERAND_ftsf189ae_slot1, - OPERAND_ftsf190ae_slot1, - OPERAND_ftsf191ae_slot1, - OPERAND_ftsf192ae_slot1, - OPERAND_ftsf193ae_slot1, - OPERAND_ftsf194ae_slot1, - OPERAND_ftsf195ae_slot1, - OPERAND_ftsf196ae_slot1, - OPERAND_ftsf197ae_slot1, - OPERAND_ftsf198ae_slot1, - OPERAND_ftsf199ae_slot1, - OPERAND_ftsf200ae_slot1, - OPERAND_ftsf201ae_slot1, - OPERAND_ftsf202ae_slot1, - OPERAND_ftsf203ae_slot1, - OPERAND_ftsf204ae_slot1, - OPERAND_ftsf205ae_slot1, - OPERAND_ftsf206ae_slot1, - OPERAND_ftsf207ae_slot1, - OPERAND_ftsf208, - OPERAND_ftsf209ae_slot1, - OPERAND_ftsf210ae_slot1, - OPERAND_ftsf211ae_slot1, - OPERAND_ftsf330ae_slot1, - OPERAND_ftsf332ae_slot1, - OPERAND_ftsf334ae_slot1, - OPERAND_ftsf336ae_slot1, - OPERAND_ftsf337ae_slot1, - OPERAND_ftsf338, - OPERAND_ftsf339ae_slot1, - OPERAND_ftsf340, - OPERAND_ftsf341ae_slot1, - OPERAND_ftsf342ae_slot1, - OPERAND_ftsf343ae_slot1, - OPERAND_ftsf344ae_slot1, - OPERAND_ftsf346ae_slot1, - OPERAND_ftsf347, - OPERAND_ftsf348ae_slot1, - OPERAND_ftsf349ae_slot1, - OPERAND_ftsf350ae_slot1, - OPERAND_op0_s4, - OPERAND_ftsf212ae_slot0, - OPERAND_ftsf213ae_slot0, - OPERAND_ftsf214ae_slot0, - OPERAND_ftsf215ae_slot0, - OPERAND_ftsf216ae_slot0, - OPERAND_ftsf217, - OPERAND_ftsf218ae_slot0, - OPERAND_ftsf219ae_slot0, - OPERAND_ftsf220ae_slot0, - OPERAND_ftsf221ae_slot0, - OPERAND_ftsf222ae_slot0, - OPERAND_ftsf223ae_slot0, - OPERAND_ftsf224ae_slot0, - OPERAND_ftsf225ae_slot0, - OPERAND_ftsf226ae_slot0, - OPERAND_ftsf227ae_slot0, - OPERAND_ftsf228ae_slot0, - OPERAND_ftsf229ae_slot0, - OPERAND_ftsf230ae_slot0, - OPERAND_ftsf231ae_slot0, - OPERAND_ftsf232ae_slot0, - OPERAND_ftsf233ae_slot0, - OPERAND_ftsf234ae_slot0, - OPERAND_ftsf235ae_slot0, - OPERAND_ftsf236ae_slot0, - OPERAND_ftsf237ae_slot0, - OPERAND_ftsf238ae_slot0, - OPERAND_ftsf239ae_slot0, - OPERAND_ftsf240ae_slot0, - OPERAND_ftsf241ae_slot0, - OPERAND_ftsf242ae_slot0, - OPERAND_ftsf243ae_slot0, - OPERAND_ftsf244ae_slot0, - OPERAND_ftsf245ae_slot0, - OPERAND_ftsf246ae_slot0, - OPERAND_ftsf247ae_slot0, - OPERAND_ftsf248ae_slot0, - OPERAND_ftsf249ae_slot0, - OPERAND_ftsf250ae_slot0, - OPERAND_ftsf251ae_slot0, - OPERAND_ftsf252ae_slot0, - OPERAND_ftsf253ae_slot0, - OPERAND_ftsf254ae_slot0, - OPERAND_ftsf255ae_slot0, - OPERAND_ftsf256ae_slot0, - OPERAND_ftsf257ae_slot0, - OPERAND_ftsf258ae_slot0, - OPERAND_ftsf259ae_slot0, - OPERAND_ftsf260ae_slot0, - OPERAND_ftsf261ae_slot0, - OPERAND_ftsf262ae_slot0, - OPERAND_ftsf263ae_slot0, - OPERAND_ftsf264ae_slot0, - OPERAND_ftsf265ae_slot0, - OPERAND_ftsf266ae_slot0, - OPERAND_ftsf267ae_slot0, - OPERAND_ftsf268ae_slot0, - OPERAND_ftsf269ae_slot0, - OPERAND_ftsf270ae_slot0, - OPERAND_ftsf271ae_slot0, - OPERAND_ftsf272ae_slot0, - OPERAND_ftsf273ae_slot0, - OPERAND_ftsf274ae_slot0, - OPERAND_ftsf275ae_slot0, - OPERAND_ftsf276ae_slot0, - OPERAND_ftsf277ae_slot0, - OPERAND_ftsf278ae_slot0, - OPERAND_ftsf279ae_slot0, - OPERAND_ftsf281ae_slot0, - OPERAND_ftsf282ae_slot0, - OPERAND_ftsf283ae_slot0, - OPERAND_ftsf284ae_slot0, - OPERAND_ftsf286ae_slot0, - OPERAND_ftsf288ae_slot0, - OPERAND_ftsf290ae_slot0, - OPERAND_ftsf292ae_slot0, - OPERAND_ftsf293, - OPERAND_ftsf294ae_slot0, - OPERAND_ftsf295ae_slot0, - OPERAND_ftsf296ae_slot0, - OPERAND_ftsf297ae_slot0, - OPERAND_ftsf298ae_slot0, - OPERAND_ftsf299ae_slot0, - OPERAND_ftsf300ae_slot0, - OPERAND_ftsf301ae_slot0, - OPERAND_ftsf302ae_slot0, - OPERAND_ftsf303ae_slot0, - OPERAND_ftsf304ae_slot0, - OPERAND_ftsf306ae_slot0, - OPERAND_ftsf308ae_slot0, - OPERAND_ftsf309ae_slot0, - OPERAND_ftsf310ae_slot0, - OPERAND_ftsf311ae_slot0, - OPERAND_ftsf312ae_slot0, - OPERAND_ftsf313ae_slot0, - OPERAND_ftsf314ae_slot0, - OPERAND_ftsf315ae_slot0, - OPERAND_ftsf316ae_slot0, - OPERAND_ftsf317ae_slot0, - OPERAND_ftsf318ae_slot0, - OPERAND_ftsf319, - OPERAND_ftsf320ae_slot0, - OPERAND_ftsf321, - OPERAND_ftsf322ae_slot0, - OPERAND_ftsf323ae_slot0, - OPERAND_ftsf324ae_slot0, - OPERAND_ftsf325ae_slot0, - OPERAND_ftsf326ae_slot0, - OPERAND_ftsf328ae_slot0, - OPERAND_ftsf329ae_slot0, - OPERAND_ftsf352ae_slot0, - OPERAND_ftsf353, - OPERAND_ftsf354ae_slot0, - OPERAND_ftsf356ae_slot0, - OPERAND_ftsf357, - OPERAND_ftsf358ae_slot0, - OPERAND_ftsf359ae_slot0, - OPERAND_ftsf360ae_slot0, - OPERAND_ftsf361ae_slot0, - OPERAND_ftsf362ae_slot0, - OPERAND_ftsf364ae_slot0, - OPERAND_ftsf365ae_slot0, - OPERAND_ftsf366ae_slot0, - OPERAND_ftsf368ae_slot0, - OPERAND_ftsf369ae_slot0 -}; - - -/* Iclass table. */ - -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSRING }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar12 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar8 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { - { { STATE_PSCALLINC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { - { { OPERAND_ars_entry }, 's' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm12x8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { - { { STATE_WindowBase }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { - { { OPERAND_simm4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSWOE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { - { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' }, - { { STATE_WindowStart }, 'm' }, - { { STATE_PSOWB }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_immrx4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowBase }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WindowStart }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ai4const }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm6 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_simm7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_lsi4x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { - { { STATE_THREADPTR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_simm8x256 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4const }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_bbi }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_b4constu }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_label12 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { - { { OPERAND_soffsetx4 }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ar0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sae }, 'i' }, - { { OPERAND_op2p1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { - { { OPERAND_soffset }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_uimm16x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_ulabel8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { - { { STATE_LBEG }, 'o' }, - { { STATE_LEND }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_simm12b }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { - { { OPERAND__ars_invisible }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { - { { OPERAND_sas }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { - { { STATE_SAR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_msalp32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_sargt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { - { { STATE_LEND }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { - { { STATE_LEND }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { - { { STATE_LEND }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { - { { STATE_LCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_LCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { - { { STATE_LBEG }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { - { { STATE_SAR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { - { { STATE_SAR }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { - { { STATE_SAR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'i' }, - { { STATE_LITBEN }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'o' }, - { { STATE_LITBEN }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { - { { STATE_LITBADDR }, 'm' }, - { { STATE_LITBEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'i' }, - { { STATE_PSCALLINC }, 'i' }, - { { STATE_PSOWB }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSUM }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { - { { STATE_PSWOE }, 'm' }, - { { STATE_PSCALLINC }, 'm' }, - { { STATE_PSOWB }, 'm' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'm' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPC2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCSAVE2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EPS2 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCVADDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEPC }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'i' }, - { { STATE_XTSYNC }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_EXCCAUSE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC0 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MISC1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_VECBASE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_mul16_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_mul32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'm' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'm' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPC1 }, 'i' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_EPS2 }, 'i' }, - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { - { { OPERAND_s }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PSINTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTERRUPT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INTENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { - { { OPERAND_imms }, 'i' }, - { { OPERAND_immt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSINTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'i' }, - { { STATE_DBNUM }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'o' }, - { { STATE_DBNUM }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DEBUGCAUSE }, 'm' }, - { { STATE_DBNUM }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_ICOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ICOUNTLEVEL }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_DDR }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { - { { OPERAND_imms }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { - { { STATE_InOCDMode }, 'm' }, - { { STATE_EPC2 }, 'i' }, - { { STATE_PSWOE }, 'o' }, - { { STATE_PSCALLINC }, 'o' }, - { { STATE_PSOWB }, 'o' }, - { { STATE_PSRING }, 'o' }, - { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, - { { STATE_PSINTLEVEL }, 'o' }, - { { STATE_EPS2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { - { { STATE_InOCDMode }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_bs }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_bs8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { - { { OPERAND_bs }, 'i' }, - { { OPERAND_label8 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { - { { OPERAND_arr }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_brall }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_brall }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_brall }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOUNT }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' }, - { { STATE_CCOUNT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE0 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'o' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CCOMPARE1 }, 'm' }, - { { STATE_INTERRUPT }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm4x16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_PTBASE }, 'm' }, - { { STATE_EXCVADDR }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'i' }, - { { STATE_ASID2 }, 'i' }, - { { STATE_ASID1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'o' }, - { { STATE_ASID2 }, 'o' }, - { { STATE_ASID1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ASID3 }, 'm' }, - { { STATE_ASID2 }, 'm' }, - { { STATE_ASID1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_INSTPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { - { { STATE_XTSYNC }, 'o' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_DATAPGSZID4 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { - { { STATE_PTBASE }, 'i' }, - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { - { { STATE_EXCVADDR }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_CPENABLE }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_tp7 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_uimm8x4 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' }, - { { STATE_XTSYNC }, 'i' }, - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { - { { STATE_SCOMPARE1 }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { - { { OPERAND_art }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'o' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { - { { OPERAND_art }, 'm' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_ATOMCTL }, 'm' }, - { { STATE_XTSYNC }, 'o' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { - { { STATE_CCON }, 'i' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_MPSCORE }, 'i' } -}; - -static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { - INTERFACE_RMPINT_Out, - INTERFACE_RMPINT_In -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { - { { OPERAND_art }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { - { { STATE_CCON }, 'm' }, - { { STATE_PSEXCM }, 'i' }, - { { STATE_PSRING }, 'i' }, - { { STATE_WMPINT_DATA }, 'o' }, - { { STATE_WMPINT_ADDR }, 'o' }, - { { STATE_MPSCORE }, 'm' }, - { { STATE_WMPINT_TOGGLEEN }, 'm' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { - { { STATE_AE_BITHEAD }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { - { { STATE_AE_SAR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { - { { STATE_AE_BITPTR }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { - { { OPERAND_arr }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm16 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { - { { OPERAND_pr }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_lsimm32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { - { { OPERAND_ps }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { - { { OPERAND_pr }, 'm' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { - { { OPERAND_pr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { - { { OPERAND_qr1_w }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bs }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_cvt_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_alupppb_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' }, - { { OPERAND_bt2 }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { - { { OPERAND_bt2 }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_bt }, 'o' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_ae_samt32 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { - { { OPERAND_ps }, 'o' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ae_samt64 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_AE_SAR }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { - { { OPERAND_bt }, 'o' }, - { { OPERAND_qr0 }, 'i' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { - { { OPERAND_ars }, 'o' }, - { { OPERAND_qr0_rw }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { - { { STATE_AE_OVERFLOW }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_mac_qr0_rw }, 'i' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_mac_qr0 }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_mac_qr1_w }, 'm' }, - { { OPERAND_pr }, 'i' }, - { { OPERAND_pr0 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'o' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_SEARCHDONE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { - { { STATE_AE_NEXTOFFSET }, 'm' }, - { { STATE_AE_TABLESIZE }, 'm' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_FIRST_TS }, 'i' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_SEARCHDONE }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_AE_FIRST_TS }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_AE_TABLESIZE }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { - { { OPERAND_arr }, 'o' }, - { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba2 }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { - { { OPERAND_br }, 'o' }, - { { OPERAND_art }, 'm' }, - { { OPERAND_ars }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'o' }, - { { STATE_AE_NEXTOFFSET }, 'o' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { - { { OPERAND_ars }, 'm' }, - { { OPERAND_art }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { - { { STATE_AE_BITPTR }, 'm' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_AE_BITSUSED }, 'i' }, - { { STATE_AE_NEXTOFFSET }, 'i' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { - { { OPERAND_ars }, 'm' } -}; - -static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { - { { STATE_AE_BITPTR }, 'i' }, - { { STATE_AE_BITHEAD }, 'm' }, - { { STATE_CPENABLE }, 'i' } -}; - -static xtensa_iclass_internal iclasses[] = { - { 0, 0 /* xt_iclass_excw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_rfe */, - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfde */, - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_syscall */, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call12_args, - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call8_args, - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_call4_args, - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx12_args, - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx8_args, - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_callx4_args, - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_entry_args, - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movsp_args, - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rotw_args, - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_retw_args, - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfwou */, - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l32e_args, - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_s32e_args, - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowbase_args, - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowbase_args, - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowbase_args, - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_windowstart_args, - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_windowstart_args, - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_windowstart_args, - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_add_n_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addi_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bz6_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill_n */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_loadi4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_mov_n_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_movi_n_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nopn */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_retn_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_storei4_args, - 0, 0, 0, 0 }, - { 1, Iclass_rur_threadptr_args, - 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, - { 1, Iclass_wur_threadptr_args, - 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_addi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addmi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_addsub_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bit_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8b_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bsi8u_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bst8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bsz12_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_call0_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_callx0_args, - 0, 0, 0, 0 }, - { 4, Iclass_xt_iclass_exti_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_ill */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jump_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_jumpx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16ui_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l16si_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_l32r_args, - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_l8i_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_loop_args, - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_loopz_args, - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_movi_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_movz_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_neg_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_nop */, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_return_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s16i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32i_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s8i_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_sar_args, - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_sari_args, - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shifts_args, - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_shiftst_args, - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_shiftt_args, - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_slli_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_srli_args, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_memw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_extw */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_isync */, - 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_sync */, - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rsil_args, - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lend_args, - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lend_args, - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lend_args, - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lcount_args, - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lcount_args, - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lcount_args, - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_lbeg_args, - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_lbeg_args, - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_lbeg_args, - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_sar_args, - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_sar_args, - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_sar_args, - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_litbase_args, - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_litbase_args, - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_litbase_args, - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid0_args, - 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_configid0_args, - 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_configid1_args, - 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ps_args, - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ps_args, - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ps_args, - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc1_args, - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc1_args, - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc1_args, - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave1_args, - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave1_args, - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave1_args, - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_epc2_args, - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_epc2_args, - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_epc2_args, - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excsave2_args, - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excsave2_args, - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excsave2_args, - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_eps2_args, - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_eps2_args, - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_eps2_args, - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_depc_args, - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_depc_args, - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_depc_args, - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_exccause_args, - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_exccause_args, - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_exccause_args, - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc0_args, - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc0_args, - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc0_args, - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_misc1_args, - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_misc1_args, - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_misc1_args, - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_prid_args, - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_vecbase_args, - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_vecbase_args, - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_vecbase_args, - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, - { 3, Iclass_xt_mul16_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_mul32_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rfi_args, - 11, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wait_args, - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_interrupt_args, - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intset_args, - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intclear_args, - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_intenable_args, - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_intenable_args, - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_intenable_args, - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_break_args, - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_break_n_args, - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_debugcause_args, - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_debugcause_args, - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_debugcause_args, - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icount_args, - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icount_args, - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icount_args, - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ddr_args, - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ddr_args, - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ddr_args, - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rfdo_args, - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_rfdd */, - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_bbool1_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool4_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbool8_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_bbranch_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_bmove_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_RSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_WSR_BR_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_XSR_BR_args, - 0, 0, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccount_args, - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccount_args, - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccount_args, - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_icache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_icache_inv_args, - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_licx_args, - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_sicx_args, - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_ind_args, - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dcache_inv_args, - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_dpf_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_sdct_args, - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ldct_args, - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_ptevaddr_args, - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_ptevaddr_args, - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_ptevaddr_args, - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_rasid_args, - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_rasid_args, - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_rasid_args, - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_itlbcfg_args, - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_itlbcfg_args, - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_itlbcfg_args, - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_idtlb_args, - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rdtlb_args, - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_wdtlb_args, - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_iitlb_args, - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_ritlb_args, - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_witlb_args, - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_ldpte */, - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwitlba */, - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, - { 0, 0 /* xt_iclass_hwwdtlba */, - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_cpenable_args, - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_cpenable_args, - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_cpenable_args, - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, - { 3, Iclass_xt_iclass_clamp_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_minmax_args, - 0, 0, 0, 0 }, - { 2, Iclass_xt_iclass_nsa_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_sx_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_l32ai_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32ri_args, - 0, 0, 0, 0 }, - { 3, Iclass_xt_iclass_s32c1i_args, - 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_scompare1_args, - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_scompare1_args, - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_scompare1_args, - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_atomctl_args, - 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_atomctl_args, - 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_xsr_atomctl_args, - 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, - { 2, Iclass_xt_iclass_rer_args, - 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, - { 2, Iclass_xt_iclass_wer_args, - 7, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ovf_sar_args, - 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ovf_sar_args, - 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_bithead_args, - 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_bithead_args, - 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_ts_fts_bu_bp_args, - 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_ts_fts_bu_bp_args, - 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, - { 1, Iclass_rur_ae_sd_no_args, - 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_wur_ae_sd_no_args, - 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_overflow_args, - 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_overflow_args, - 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_sar_args, - 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_sar_args, - 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitptr_args, - 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitptr_args, - 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_bitsused_args, - 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_bitsused_args, - 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_tablesize_args, - 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_tablesize_args, - 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_first_ts_args, - 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_first_ts_args, - 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, - 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, - 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_rur_ae_searchdone_args, - 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_wur_ae_searchdone_args, - 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_i_args, - 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_iu_args, - 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_x_args, - 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16f_xu_args, - 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_i_args, - 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_iu_args, - 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_x_args, - 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24_xu_args, - 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_i_args, - 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_iu_args, - 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_x_args, - 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24f_xu_args, - 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_i_args, - 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_iu_args, - 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_x_args, - 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp16x2f_xu_args, - 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_i_args, - 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_iu_args, - 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_x_args, - 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2f_xu_args, - 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_i_args, - 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_iu_args, - 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_x_args, - 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lp24x2_xu_args, - 1, Iclass_ae_iclass_lp24x2_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_i_args, - 1, Iclass_ae_iclass_sp16x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_iu_args, - 1, Iclass_ae_iclass_sp16x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_x_args, - 1, Iclass_ae_iclass_sp16x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16x2f_xu_args, - 1, Iclass_ae_iclass_sp16x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_i_args, - 1, Iclass_ae_iclass_sp24x2s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_iu_args, - 1, Iclass_ae_iclass_sp24x2s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_x_args, - 1, Iclass_ae_iclass_sp24x2s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2s_xu_args, - 1, Iclass_ae_iclass_sp24x2s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_i_args, - 1, Iclass_ae_iclass_sp24x2f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_iu_args, - 1, Iclass_ae_iclass_sp24x2f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_x_args, - 1, Iclass_ae_iclass_sp24x2f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24x2f_xu_args, - 1, Iclass_ae_iclass_sp24x2f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_i_args, - 1, Iclass_ae_iclass_sp16f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_iu_args, - 1, Iclass_ae_iclass_sp16f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_x_args, - 1, Iclass_ae_iclass_sp16f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp16f_l_xu_args, - 1, Iclass_ae_iclass_sp16f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_i_args, - 1, Iclass_ae_iclass_sp24s_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_iu_args, - 1, Iclass_ae_iclass_sp24s_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_x_args, - 1, Iclass_ae_iclass_sp24s_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24s_l_xu_args, - 1, Iclass_ae_iclass_sp24s_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_i_args, - 1, Iclass_ae_iclass_sp24f_l_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_iu_args, - 1, Iclass_ae_iclass_sp24f_l_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_x_args, - 1, Iclass_ae_iclass_sp24f_l_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sp24f_l_xu_args, - 1, Iclass_ae_iclass_sp24f_l_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_i_args, - 1, Iclass_ae_iclass_lq56_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_iu_args, - 1, Iclass_ae_iclass_lq56_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_x_args, - 1, Iclass_ae_iclass_lq56_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq56_xu_args, - 1, Iclass_ae_iclass_lq56_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_i_args, - 1, Iclass_ae_iclass_lq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_iu_args, - 1, Iclass_ae_iclass_lq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_x_args, - 1, Iclass_ae_iclass_lq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lq32f_xu_args, - 1, Iclass_ae_iclass_lq32f_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_i_args, - 1, Iclass_ae_iclass_sq56s_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_iu_args, - 1, Iclass_ae_iclass_sq56s_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_x_args, - 1, Iclass_ae_iclass_sq56s_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq56s_xu_args, - 1, Iclass_ae_iclass_sq56s_xu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_i_args, - 1, Iclass_ae_iclass_sq32f_i_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_iu_args, - 1, Iclass_ae_iclass_sq32f_iu_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_x_args, - 1, Iclass_ae_iclass_sq32f_x_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sq32f_xu_args, - 1, Iclass_ae_iclass_sq32f_xu_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zerop48_args, - 1, Iclass_ae_iclass_zerop48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movp48_args, - 1, Iclass_ae_iclass_movp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_ll_args, - 1, Iclass_ae_iclass_selp24_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_lh_args, - 1, Iclass_ae_iclass_selp24_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hl_args, - 1, Iclass_ae_iclass_selp24_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_selp24_hh_args, - 1, Iclass_ae_iclass_selp24_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp24x2_args, - 1, Iclass_ae_iclass_movtp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp24x2_args, - 1, Iclass_ae_iclass_movfp24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtp48_args, - 1, Iclass_ae_iclass_movtp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfp48_args, - 1, Iclass_ae_iclass_movfp48_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movpa24x2_args, - 1, Iclass_ae_iclass_movpa24x2_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24a32x2_args, - 1, Iclass_ae_iclass_truncp24a32x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_l_args, - 1, Iclass_ae_iclass_cvta32p24_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvta32p24_h_args, - 1, Iclass_ae_iclass_cvta32p24_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_ll_args, - 1, Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_lh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hl_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_cvtp24a16x2_hh_args, - 1, Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_truncp24q48x2_args, - 1, Iclass_ae_iclass_truncp24q48x2_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncp16_args, - 1, Iclass_ae_iclass_truncp16_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48sym_args, - 2, Iclass_ae_iclass_roundsp24q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp24q48asym_args, - 2, Iclass_ae_iclass_roundsp24q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48sym_args, - 2, Iclass_ae_iclass_roundsp16q48sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16q48asym_args, - 2, Iclass_ae_iclass_roundsp16q48asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16sym_args, - 2, Iclass_ae_iclass_roundsp16sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsp16asym_args, - 2, Iclass_ae_iclass_roundsp16asym_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_zeroq56_args, - 1, Iclass_ae_iclass_zeroq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movq56_args, - 1, Iclass_ae_iclass_movq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movtq56_args, - 1, Iclass_ae_iclass_movtq56_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_movfq56_args, - 1, Iclass_ae_iclass_movfq56_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48a32s_args, - 1, Iclass_ae_iclass_cvtq48a32s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_l_args, - 1, Iclass_ae_iclass_cvtq48p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_cvtq48p24s_h_args, - 1, Iclass_ae_iclass_cvtq48p24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_satq48s_args, - 2, Iclass_ae_iclass_satq48s_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_truncq32_args, - 1, Iclass_ae_iclass_truncq32_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32sym_args, - 2, Iclass_ae_iclass_roundsq32sym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_roundsq32asym_args, - 2, Iclass_ae_iclass_roundsq32asym_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca32q48_args, - 1, Iclass_ae_iclass_trunca32q48_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_l_args, - 1, Iclass_ae_iclass_movap24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_movap24s_h_args, - 1, Iclass_ae_iclass_movap24s_h_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_l_args, - 1, Iclass_ae_iclass_trunca16p24s_l_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_trunca16p24s_h_args, - 1, Iclass_ae_iclass_trunca16p24s_h_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_addp24_args, - 1, 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Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzaafq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzasfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, - { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, - 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, - 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, - 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, - 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, - 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sha32_args, - 0, 0, 0, 0 }, - { 3, Iclass_ae_iclass_vldl32t_args, - 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vldl16t_args, - 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldl16c_args, - 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vldsht_args, - 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lb_args, - 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_lbi_args, - 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbk_args, - 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_lbki_args, - 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_db_args, - 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_dbi_args, - 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel32t_args, - 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_vlel16t_args, - 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, - { 2, Iclass_ae_iclass_sb_args, - 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, - { 3, Iclass_ae_iclass_sbi_args, - 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_vles16c_args, - 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, - { 1, Iclass_ae_iclass_sbf_args, - 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 } -}; - -enum xtensa_iclass_id { - ICLASS_xt_iclass_excw, - ICLASS_xt_iclass_rfe, - ICLASS_xt_iclass_rfde, - ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_call12, - ICLASS_xt_iclass_call8, - ICLASS_xt_iclass_call4, - ICLASS_xt_iclass_callx12, - ICLASS_xt_iclass_callx8, - ICLASS_xt_iclass_callx4, - ICLASS_xt_iclass_entry, - ICLASS_xt_iclass_movsp, - ICLASS_xt_iclass_rotw, - ICLASS_xt_iclass_retw, - ICLASS_xt_iclass_rfwou, - ICLASS_xt_iclass_l32e, - ICLASS_xt_iclass_s32e, - ICLASS_xt_iclass_rsr_windowbase, - ICLASS_xt_iclass_wsr_windowbase, - ICLASS_xt_iclass_xsr_windowbase, - ICLASS_xt_iclass_rsr_windowstart, - ICLASS_xt_iclass_wsr_windowstart, - ICLASS_xt_iclass_xsr_windowstart, - ICLASS_xt_iclass_add_n, - ICLASS_xt_iclass_addi_n, - ICLASS_xt_iclass_bz6, - ICLASS_xt_iclass_ill_n, - ICLASS_xt_iclass_loadi4, - ICLASS_xt_iclass_mov_n, - ICLASS_xt_iclass_movi_n, - ICLASS_xt_iclass_nopn, - ICLASS_xt_iclass_retn, - ICLASS_xt_iclass_storei4, - ICLASS_rur_threadptr, - ICLASS_wur_threadptr, - ICLASS_xt_iclass_addi, - ICLASS_xt_iclass_addmi, - ICLASS_xt_iclass_addsub, - ICLASS_xt_iclass_bit, - ICLASS_xt_iclass_bsi8, - ICLASS_xt_iclass_bsi8b, - ICLASS_xt_iclass_bsi8u, - ICLASS_xt_iclass_bst8, - ICLASS_xt_iclass_bsz12, - ICLASS_xt_iclass_call0, - ICLASS_xt_iclass_callx0, - ICLASS_xt_iclass_exti, - ICLASS_xt_iclass_ill, - ICLASS_xt_iclass_jump, - ICLASS_xt_iclass_jumpx, - ICLASS_xt_iclass_l16ui, - ICLASS_xt_iclass_l16si, - ICLASS_xt_iclass_l32i, - ICLASS_xt_iclass_l32r, - ICLASS_xt_iclass_l8i, - ICLASS_xt_iclass_loop, - ICLASS_xt_iclass_loopz, - ICLASS_xt_iclass_movi, - ICLASS_xt_iclass_movz, - ICLASS_xt_iclass_neg, - ICLASS_xt_iclass_nop, - ICLASS_xt_iclass_return, - ICLASS_xt_iclass_simcall, - ICLASS_xt_iclass_s16i, - ICLASS_xt_iclass_s32i, - ICLASS_xt_iclass_s8i, - ICLASS_xt_iclass_sar, - ICLASS_xt_iclass_sari, - ICLASS_xt_iclass_shifts, - ICLASS_xt_iclass_shiftst, - ICLASS_xt_iclass_shiftt, - ICLASS_xt_iclass_slli, - ICLASS_xt_iclass_srai, - ICLASS_xt_iclass_srli, - ICLASS_xt_iclass_memw, - ICLASS_xt_iclass_extw, - ICLASS_xt_iclass_isync, - ICLASS_xt_iclass_sync, - ICLASS_xt_iclass_rsil, - ICLASS_xt_iclass_rsr_lend, - ICLASS_xt_iclass_wsr_lend, - ICLASS_xt_iclass_xsr_lend, - ICLASS_xt_iclass_rsr_lcount, - ICLASS_xt_iclass_wsr_lcount, - ICLASS_xt_iclass_xsr_lcount, - ICLASS_xt_iclass_rsr_lbeg, - ICLASS_xt_iclass_wsr_lbeg, - ICLASS_xt_iclass_xsr_lbeg, - ICLASS_xt_iclass_rsr_sar, - ICLASS_xt_iclass_wsr_sar, - ICLASS_xt_iclass_xsr_sar, - ICLASS_xt_iclass_rsr_litbase, - ICLASS_xt_iclass_wsr_litbase, - ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_configid0, - ICLASS_xt_iclass_wsr_configid0, - ICLASS_xt_iclass_rsr_configid1, - ICLASS_xt_iclass_rsr_ps, - ICLASS_xt_iclass_wsr_ps, - ICLASS_xt_iclass_xsr_ps, - ICLASS_xt_iclass_rsr_epc1, - ICLASS_xt_iclass_wsr_epc1, - ICLASS_xt_iclass_xsr_epc1, - ICLASS_xt_iclass_rsr_excsave1, - ICLASS_xt_iclass_wsr_excsave1, - ICLASS_xt_iclass_xsr_excsave1, - ICLASS_xt_iclass_rsr_epc2, - ICLASS_xt_iclass_wsr_epc2, - ICLASS_xt_iclass_xsr_epc2, - ICLASS_xt_iclass_rsr_excsave2, - ICLASS_xt_iclass_wsr_excsave2, - ICLASS_xt_iclass_xsr_excsave2, - ICLASS_xt_iclass_rsr_eps2, - ICLASS_xt_iclass_wsr_eps2, - ICLASS_xt_iclass_xsr_eps2, - ICLASS_xt_iclass_rsr_excvaddr, - ICLASS_xt_iclass_wsr_excvaddr, - ICLASS_xt_iclass_xsr_excvaddr, - ICLASS_xt_iclass_rsr_depc, - ICLASS_xt_iclass_wsr_depc, - ICLASS_xt_iclass_xsr_depc, - ICLASS_xt_iclass_rsr_exccause, - ICLASS_xt_iclass_wsr_exccause, - ICLASS_xt_iclass_xsr_exccause, - ICLASS_xt_iclass_rsr_misc0, - ICLASS_xt_iclass_wsr_misc0, - ICLASS_xt_iclass_xsr_misc0, - ICLASS_xt_iclass_rsr_misc1, - ICLASS_xt_iclass_wsr_misc1, - ICLASS_xt_iclass_xsr_misc1, - ICLASS_xt_iclass_rsr_prid, - ICLASS_xt_iclass_rsr_vecbase, - ICLASS_xt_iclass_wsr_vecbase, - ICLASS_xt_iclass_xsr_vecbase, - ICLASS_xt_mul16, - ICLASS_xt_mul32, - ICLASS_xt_iclass_rfi, - ICLASS_xt_iclass_wait, - ICLASS_xt_iclass_rsr_interrupt, - ICLASS_xt_iclass_wsr_intset, - ICLASS_xt_iclass_wsr_intclear, - ICLASS_xt_iclass_rsr_intenable, - ICLASS_xt_iclass_wsr_intenable, - ICLASS_xt_iclass_xsr_intenable, - ICLASS_xt_iclass_break, - ICLASS_xt_iclass_break_n, - ICLASS_xt_iclass_rsr_debugcause, - ICLASS_xt_iclass_wsr_debugcause, - ICLASS_xt_iclass_xsr_debugcause, - ICLASS_xt_iclass_rsr_icount, - ICLASS_xt_iclass_wsr_icount, - ICLASS_xt_iclass_xsr_icount, - ICLASS_xt_iclass_rsr_icountlevel, - ICLASS_xt_iclass_wsr_icountlevel, - ICLASS_xt_iclass_xsr_icountlevel, - ICLASS_xt_iclass_rsr_ddr, - ICLASS_xt_iclass_wsr_ddr, - ICLASS_xt_iclass_xsr_ddr, - ICLASS_xt_iclass_rfdo, - ICLASS_xt_iclass_rfdd, - ICLASS_xt_iclass_bbool1, - ICLASS_xt_iclass_bbool4, - ICLASS_xt_iclass_bbool8, - ICLASS_xt_iclass_bbranch, - ICLASS_xt_iclass_bmove, - ICLASS_xt_iclass_RSR_BR, - ICLASS_xt_iclass_WSR_BR, - ICLASS_xt_iclass_XSR_BR, - ICLASS_xt_iclass_rsr_ccount, - ICLASS_xt_iclass_wsr_ccount, - ICLASS_xt_iclass_xsr_ccount, - ICLASS_xt_iclass_rsr_ccompare0, - ICLASS_xt_iclass_wsr_ccompare0, - ICLASS_xt_iclass_xsr_ccompare0, - ICLASS_xt_iclass_rsr_ccompare1, - ICLASS_xt_iclass_wsr_ccompare1, - ICLASS_xt_iclass_xsr_ccompare1, - ICLASS_xt_iclass_icache, - ICLASS_xt_iclass_icache_inv, - ICLASS_xt_iclass_licx, - ICLASS_xt_iclass_sicx, - ICLASS_xt_iclass_dcache, - ICLASS_xt_iclass_dcache_ind, - ICLASS_xt_iclass_dcache_inv, - ICLASS_xt_iclass_dpf, - ICLASS_xt_iclass_sdct, - ICLASS_xt_iclass_ldct, - ICLASS_xt_iclass_wsr_ptevaddr, - ICLASS_xt_iclass_rsr_ptevaddr, - ICLASS_xt_iclass_xsr_ptevaddr, - ICLASS_xt_iclass_rsr_rasid, - ICLASS_xt_iclass_wsr_rasid, - ICLASS_xt_iclass_xsr_rasid, - ICLASS_xt_iclass_rsr_itlbcfg, - ICLASS_xt_iclass_wsr_itlbcfg, - ICLASS_xt_iclass_xsr_itlbcfg, - ICLASS_xt_iclass_rsr_dtlbcfg, - ICLASS_xt_iclass_wsr_dtlbcfg, - ICLASS_xt_iclass_xsr_dtlbcfg, - ICLASS_xt_iclass_idtlb, - ICLASS_xt_iclass_rdtlb, - ICLASS_xt_iclass_wdtlb, - ICLASS_xt_iclass_iitlb, - ICLASS_xt_iclass_ritlb, - ICLASS_xt_iclass_witlb, - ICLASS_xt_iclass_ldpte, - ICLASS_xt_iclass_hwwitlba, - ICLASS_xt_iclass_hwwdtlba, - ICLASS_xt_iclass_rsr_cpenable, - ICLASS_xt_iclass_wsr_cpenable, - ICLASS_xt_iclass_xsr_cpenable, - ICLASS_xt_iclass_clamp, - ICLASS_xt_iclass_minmax, - ICLASS_xt_iclass_nsa, - ICLASS_xt_iclass_sx, - ICLASS_xt_iclass_l32ai, - ICLASS_xt_iclass_s32ri, - ICLASS_xt_iclass_s32c1i, - ICLASS_xt_iclass_rsr_scompare1, - ICLASS_xt_iclass_wsr_scompare1, - ICLASS_xt_iclass_xsr_scompare1, - ICLASS_xt_iclass_rsr_atomctl, - ICLASS_xt_iclass_wsr_atomctl, - ICLASS_xt_iclass_xsr_atomctl, - ICLASS_xt_iclass_rer, - ICLASS_xt_iclass_wer, - ICLASS_rur_ae_ovf_sar, - ICLASS_wur_ae_ovf_sar, - ICLASS_rur_ae_bithead, - ICLASS_wur_ae_bithead, - ICLASS_rur_ae_ts_fts_bu_bp, - ICLASS_wur_ae_ts_fts_bu_bp, - ICLASS_rur_ae_sd_no, - ICLASS_wur_ae_sd_no, - ICLASS_ae_iclass_rur_ae_overflow, - ICLASS_ae_iclass_wur_ae_overflow, - ICLASS_ae_iclass_rur_ae_sar, - ICLASS_ae_iclass_wur_ae_sar, - ICLASS_ae_iclass_rur_ae_bitptr, - ICLASS_ae_iclass_wur_ae_bitptr, - ICLASS_ae_iclass_rur_ae_bitsused, - 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ICLASS_ae_iclass_mulafp24s_hh, - ICLASS_ae_iclass_mulap24s_hh, - ICLASS_ae_iclass_mulsfs32p16s_ll, - ICLASS_ae_iclass_mulsfp24s_ll, - ICLASS_ae_iclass_mulsp24s_ll, - ICLASS_ae_iclass_mulsfs32p16s_lh, - ICLASS_ae_iclass_mulsfp24s_lh, - ICLASS_ae_iclass_mulsp24s_lh, - ICLASS_ae_iclass_mulsfs32p16s_hl, - ICLASS_ae_iclass_mulsfp24s_hl, - ICLASS_ae_iclass_mulsp24s_hl, - ICLASS_ae_iclass_mulsfs32p16s_hh, - ICLASS_ae_iclass_mulsfp24s_hh, - ICLASS_ae_iclass_mulsp24s_hh, - ICLASS_ae_iclass_mulafs56p24s_ll, - ICLASS_ae_iclass_mulas56p24s_ll, - ICLASS_ae_iclass_mulafs56p24s_lh, - ICLASS_ae_iclass_mulas56p24s_lh, - ICLASS_ae_iclass_mulafs56p24s_hl, - ICLASS_ae_iclass_mulas56p24s_hl, - ICLASS_ae_iclass_mulafs56p24s_hh, - ICLASS_ae_iclass_mulas56p24s_hh, - ICLASS_ae_iclass_mulsfs56p24s_ll, - ICLASS_ae_iclass_mulss56p24s_ll, - ICLASS_ae_iclass_mulsfs56p24s_lh, - ICLASS_ae_iclass_mulss56p24s_lh, - ICLASS_ae_iclass_mulsfs56p24s_hl, - ICLASS_ae_iclass_mulss56p24s_hl, - ICLASS_ae_iclass_mulsfs56p24s_hh, - ICLASS_ae_iclass_mulss56p24s_hh, - ICLASS_ae_iclass_mulfq32sp16s_l, - ICLASS_ae_iclass_mulfq32sp16s_h, - ICLASS_ae_iclass_mulfq32sp16u_l, - ICLASS_ae_iclass_mulfq32sp16u_h, - ICLASS_ae_iclass_mulq32sp16s_l, - ICLASS_ae_iclass_mulq32sp16s_h, - ICLASS_ae_iclass_mulq32sp16u_l, - ICLASS_ae_iclass_mulq32sp16u_h, - ICLASS_ae_iclass_mulafq32sp16s_l, - ICLASS_ae_iclass_mulafq32sp16s_h, - ICLASS_ae_iclass_mulafq32sp16u_l, - ICLASS_ae_iclass_mulafq32sp16u_h, - ICLASS_ae_iclass_mulaq32sp16s_l, - ICLASS_ae_iclass_mulaq32sp16s_h, - ICLASS_ae_iclass_mulaq32sp16u_l, - ICLASS_ae_iclass_mulaq32sp16u_h, - ICLASS_ae_iclass_mulsfq32sp16s_l, - ICLASS_ae_iclass_mulsfq32sp16s_h, - ICLASS_ae_iclass_mulsfq32sp16u_l, - ICLASS_ae_iclass_mulsfq32sp16u_h, - ICLASS_ae_iclass_mulsq32sp16s_l, - ICLASS_ae_iclass_mulsq32sp16s_h, - ICLASS_ae_iclass_mulsq32sp16u_l, - ICLASS_ae_iclass_mulsq32sp16u_h, - ICLASS_ae_iclass_mulzaaq32sp16s_ll, - ICLASS_ae_iclass_mulzaafq32sp16s_ll, - ICLASS_ae_iclass_mulzaaq32sp16u_ll, - ICLASS_ae_iclass_mulzaafq32sp16u_ll, - ICLASS_ae_iclass_mulzaaq32sp16s_hh, - ICLASS_ae_iclass_mulzaafq32sp16s_hh, - ICLASS_ae_iclass_mulzaaq32sp16u_hh, - ICLASS_ae_iclass_mulzaafq32sp16u_hh, - ICLASS_ae_iclass_mulzaaq32sp16s_lh, - ICLASS_ae_iclass_mulzaafq32sp16s_lh, - ICLASS_ae_iclass_mulzaaq32sp16u_lh, - ICLASS_ae_iclass_mulzaafq32sp16u_lh, - ICLASS_ae_iclass_mulzasq32sp16s_ll, - ICLASS_ae_iclass_mulzasfq32sp16s_ll, - ICLASS_ae_iclass_mulzasq32sp16u_ll, - ICLASS_ae_iclass_mulzasfq32sp16u_ll, - ICLASS_ae_iclass_mulzasq32sp16s_hh, - ICLASS_ae_iclass_mulzasfq32sp16s_hh, - ICLASS_ae_iclass_mulzasq32sp16u_hh, - ICLASS_ae_iclass_mulzasfq32sp16u_hh, - ICLASS_ae_iclass_mulzasq32sp16s_lh, - ICLASS_ae_iclass_mulzasfq32sp16s_lh, - ICLASS_ae_iclass_mulzasq32sp16u_lh, - ICLASS_ae_iclass_mulzasfq32sp16u_lh, - ICLASS_ae_iclass_mulzsaq32sp16s_ll, - ICLASS_ae_iclass_mulzsafq32sp16s_ll, - ICLASS_ae_iclass_mulzsaq32sp16u_ll, - ICLASS_ae_iclass_mulzsafq32sp16u_ll, - ICLASS_ae_iclass_mulzsaq32sp16s_hh, - ICLASS_ae_iclass_mulzsafq32sp16s_hh, - ICLASS_ae_iclass_mulzsaq32sp16u_hh, - ICLASS_ae_iclass_mulzsafq32sp16u_hh, - ICLASS_ae_iclass_mulzsaq32sp16s_lh, - ICLASS_ae_iclass_mulzsafq32sp16s_lh, - ICLASS_ae_iclass_mulzsaq32sp16u_lh, - ICLASS_ae_iclass_mulzsafq32sp16u_lh, - ICLASS_ae_iclass_mulzssq32sp16s_ll, - ICLASS_ae_iclass_mulzssfq32sp16s_ll, - ICLASS_ae_iclass_mulzssq32sp16u_ll, - ICLASS_ae_iclass_mulzssfq32sp16u_ll, - ICLASS_ae_iclass_mulzssq32sp16s_hh, - ICLASS_ae_iclass_mulzssfq32sp16s_hh, - ICLASS_ae_iclass_mulzssq32sp16u_hh, - ICLASS_ae_iclass_mulzssfq32sp16u_hh, - ICLASS_ae_iclass_mulzssq32sp16s_lh, - ICLASS_ae_iclass_mulzssfq32sp16s_lh, - ICLASS_ae_iclass_mulzssq32sp16u_lh, - ICLASS_ae_iclass_mulzssfq32sp16u_lh, - ICLASS_ae_iclass_mulzaafp24s_hh_ll, - ICLASS_ae_iclass_mulzaap24s_hh_ll, - ICLASS_ae_iclass_mulzaafp24s_hl_lh, - ICLASS_ae_iclass_mulzaap24s_hl_lh, - ICLASS_ae_iclass_mulzasfp24s_hh_ll, - ICLASS_ae_iclass_mulzasp24s_hh_ll, - ICLASS_ae_iclass_mulzasfp24s_hl_lh, - ICLASS_ae_iclass_mulzasp24s_hl_lh, - ICLASS_ae_iclass_mulzsafp24s_hh_ll, - ICLASS_ae_iclass_mulzsap24s_hh_ll, - ICLASS_ae_iclass_mulzsafp24s_hl_lh, - ICLASS_ae_iclass_mulzsap24s_hl_lh, - ICLASS_ae_iclass_mulzssfp24s_hh_ll, - ICLASS_ae_iclass_mulzssp24s_hh_ll, - ICLASS_ae_iclass_mulzssfp24s_hl_lh, - ICLASS_ae_iclass_mulzssp24s_hl_lh, - ICLASS_ae_iclass_mulaafp24s_hh_ll, - ICLASS_ae_iclass_mulaap24s_hh_ll, - ICLASS_ae_iclass_mulaafp24s_hl_lh, - ICLASS_ae_iclass_mulaap24s_hl_lh, - ICLASS_ae_iclass_mulasfp24s_hh_ll, - ICLASS_ae_iclass_mulasp24s_hh_ll, - ICLASS_ae_iclass_mulasfp24s_hl_lh, - ICLASS_ae_iclass_mulasp24s_hl_lh, - ICLASS_ae_iclass_mulsafp24s_hh_ll, - ICLASS_ae_iclass_mulsap24s_hh_ll, - ICLASS_ae_iclass_mulsafp24s_hl_lh, - ICLASS_ae_iclass_mulsap24s_hl_lh, - ICLASS_ae_iclass_mulssfp24s_hh_ll, - ICLASS_ae_iclass_mulssp24s_hh_ll, - ICLASS_ae_iclass_mulssfp24s_hl_lh, - ICLASS_ae_iclass_mulssp24s_hl_lh, - ICLASS_ae_iclass_sha32, - ICLASS_ae_iclass_vldl32t, - ICLASS_ae_iclass_vldl16t, - ICLASS_ae_iclass_vldl16c, - ICLASS_ae_iclass_vldsht, - ICLASS_ae_iclass_lb, - ICLASS_ae_iclass_lbi, - ICLASS_ae_iclass_lbk, - ICLASS_ae_iclass_lbki, - ICLASS_ae_iclass_db, - ICLASS_ae_iclass_dbi, - ICLASS_ae_iclass_vlel32t, - ICLASS_ae_iclass_vlel16t, - ICLASS_ae_iclass_sb, - ICLASS_ae_iclass_sbi, - ICLASS_ae_iclass_vles16c, - ICLASS_ae_iclass_sbf -}; - - -/* Opcode encodings. */ - -static void -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2080; -} - -static void -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000; -} - -static void -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3200; -} - -static void -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5000; -} - -static void -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35; -} - -static void -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x25; -} - -static void -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15; -} - -static void -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf0; -} - -static void -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe0; -} - -static void -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd0; -} - -static void -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36; -} - -static void -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1000; -} - -static void -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x408000; -} - -static void -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90; -} - -static void -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01d; -} - -static void -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3400; -} - -static void -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3500; -} - -static void -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x90000; -} - -static void -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x490000; -} - -static void -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34800; -} - -static void -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134800; -} - -static void -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614800; -} - -static void -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x34900; -} - -static void -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x134900; -} - -static void -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x614900; -} - -static void -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa; -} - -static void -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb; -} - -static void -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8c; -} - -static void -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcc; -} - -static void -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf06d; -} - -static void -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8; -} - -static void -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd; -} - -static void -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc; -} - -static void -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf03d; -} - -static void -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00d; -} - -static void -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9; -} - -static void -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30e70; -} - -static void -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3e700; -} - -static void -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc002; -} - -static void -Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200040; -} - -static void -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd002; -} - -static void -Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200080; -} - -static void -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x800000; -} - -static void -Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b2000; -} - -static void -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00000; -} - -static void -Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ca000; -} - -static void -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x900000; -} - -static void -Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b4000; -} - -static void -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00000; -} - -static void -Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b8000; -} - -static void -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00000; -} - -static void -Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b3000; -} - -static void -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd00000; -} - -static void -Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cc000; -} - -static void -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00000; -} - -static void -Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cb000; -} - -static void -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00000; -} - -static void -Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cd000; -} - -static void -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b5000; -} - -static void -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e0000; -} - -static void -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ce000; -} - -static void -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x26; -} - -static void -Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300000; -} - -static void -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x66; -} - -static void -Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300003; -} - -static void -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe6; -} - -static void -Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300001; -} - -static void -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa6; -} - -static void -Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300004; -} - -static void -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6007; -} - -static void -Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200000; -} - -static void -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe007; -} - -static void -Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200020; -} - -static void -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf6; -} - -static void -Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300002; -} - -static void -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb6; -} - -static void -Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300008; -} - -static void -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1007; -} - -static void -Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a0; -} - -static void -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9007; -} - -static void -Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa007; -} - -static void -Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c0; -} - -static void -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2007; -} - -static void -Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d0; -} - -static void -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb007; -} - -static void -Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b0; -} - -static void -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3007; -} - -static void -Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e0; -} - -static void -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8007; -} - -static void -Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200060; -} - -static void -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7; -} - -static void -Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400010; -} - -static void -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4007; -} - -static void -Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200050; -} - -static void -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc007; -} - -static void -Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f0; -} - -static void -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5007; -} - -static void -Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200070; -} - -static void -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd007; -} - -static void -Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x200090; -} - -static void -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16; -} - -static void -Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x180000; -} - -static void -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x56; -} - -static void -Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x190000; -} - -static void -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd6; -} - -static void -Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x160000; -} - -static void -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x96; -} - -static void -Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x170000; -} - -static void -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5; -} - -static void -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc0; -} - -static void -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x140000; -} - -static void -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0; -} - -static void -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6; -} - -static void -Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x100000; -} - -static void -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa0; -} - -static void -Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee031; -} - -static void -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1002; -} - -static void -Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400040; -} - -static void -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9002; -} - -static void -Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400020; -} - -static void -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2002; -} - -static void -Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400080; -} - -static void -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1; -} - -static void -Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500000; -} - -static void -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2; -} - -static void -Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400030; -} - -static void -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8076; -} - -static void -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9076; -} - -static void -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa076; -} - -static void -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa002; -} - -static void -Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1a0000; -} - -static void -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x830000; -} - -static void -Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1be000; -} - -static void -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x930000; -} - -static void -Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c8000; -} - -static void -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30000; -} - -static void -Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c4000; -} - -static void -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30000; -} - -static void -Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c2000; -} - -static void -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600000; -} - -static void -Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1d00; -} - -static void -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x600100; -} - -static void -Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1c00; -} - -static void -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20f0; -} - -static void -Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16105; -} - -static void -Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee0b1; -} - -static void -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x80; -} - -static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5002; -} - -static void -Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400050; -} - -static void -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6002; -} - -static void -Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400060; -} - -static void -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4002; -} - -static void -Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400070; -} - -static void -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x400000; -} - -static void -Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee071; -} - -static void -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x401000; -} - -static void -Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee038; -} - -static void -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x402000; -} - -static void -Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee034; -} - -static void -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x403000; -} - -static void -Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee032; -} - -static void -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x404000; -} - -static void -Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef0a0; -} - -static void -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10000; -} - -static void -Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5003; -} - -static void -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x810000; -} - -static void -Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c7000; -} - -static void -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x910000; -} - -static void -Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1f00; -} - -static void -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10000; -} - -static void -Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1e00; -} - -static void -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c0000; -} - -static void -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x210000; -} - -static void -Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b0000; -} - -static void -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x410000; -} - -static void -Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c9000; -} - -static void -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20c0; -} - -static void -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20d0; -} - -static void -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000; -} - -static void -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2010; -} - -static void -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2020; -} - -static void -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2030; -} - -static void -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000; -} - -static void -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30100; -} - -static void -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130100; -} - -static void -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610100; -} - -static void -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30200; -} - -static void -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130200; -} - -static void -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610200; -} - -static void -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130000; -} - -static void -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610000; -} - -static void -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30300; -} - -static void -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130300; -} - -static void -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610300; -} - -static void -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30500; -} - -static void -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130500; -} - -static void -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610500; -} - -static void -Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b000; -} - -static void -Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b000; -} - -static void -Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d000; -} - -static void -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e600; -} - -static void -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e600; -} - -static void -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e600; -} - -static void -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b100; -} - -static void -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b100; -} - -static void -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b100; -} - -static void -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d100; -} - -static void -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d100; -} - -static void -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d100; -} - -static void -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3b200; -} - -static void -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13b200; -} - -static void -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61b200; -} - -static void -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3d200; -} - -static void -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13d200; -} - -static void -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61d200; -} - -static void -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c200; -} - -static void -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c200; -} - -static void -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c200; -} - -static void -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ee00; -} - -static void -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ee00; -} - -static void -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ee00; -} - -static void -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3c000; -} - -static void -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13c000; -} - -static void -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61c000; -} - -static void -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e800; -} - -static void -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e800; -} - -static void -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e800; -} - -static void -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f400; -} - -static void -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f400; -} - -static void -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f400; -} - -static void -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f500; -} - -static void -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f500; -} - -static void -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f500; -} - -static void -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3eb00; -} - -static void -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e700; -} - -static void -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e700; -} - -static void -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e700; -} - -static void -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10000; -} - -static void -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd10000; -} - -static void -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x820000; -} - -static void -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3010; -} - -static void -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7000; -} - -static void -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e200; -} - -static void -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e200; -} - -static void -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e300; -} - -static void -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e400; -} - -static void -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e400; -} - -static void -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e400; -} - -static void -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000; -} - -static void -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02d; -} - -static void -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e900; -} - -static void -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e900; -} - -static void -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e900; -} - -static void -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ec00; -} - -static void -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ec00; -} - -static void -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ec00; -} - -static void -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ed00; -} - -static void -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ed00; -} - -static void -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ed00; -} - -static void -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36800; -} - -static void -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136800; -} - -static void -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616800; -} - -static void -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e000; -} - -static void -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1e010; -} - -static void -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b6000; -} - -static void -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x120000; -} - -static void -Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b7000; -} - -static void -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x220000; -} - -static void -Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c3000; -} - -static void -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x320000; -} - -static void -Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c5000; -} - -static void -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x420000; -} - -static void -Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1cf000; -} - -static void -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x8000; -} - -static void -Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2480; -} - -static void -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x9000; -} - -static void -Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2800; -} - -static void -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa000; -} - -static void -Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef060; -} - -static void -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb000; -} - -static void -Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef020; -} - -static void -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x76; -} - -static void -Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300005; -} - -static void -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1076; -} - -static void -Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x300006; -} - -static void -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30000; -} - -static void -Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bf000; -} - -static void -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xd30000; -} - -static void -Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d0000; -} - -static void -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30400; -} - -static void -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130400; -} - -static void -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610400; -} - -static void -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3ea00; -} - -static void -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13ea00; -} - -static void -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61ea00; -} - -static void -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f000; -} - -static void -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f000; -} - -static void -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f000; -} - -static void -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3f100; -} - -static void -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13f100; -} - -static void -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61f100; -} - -static void -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70c2; -} - -static void -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70e2; -} - -static void -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x70f2; -} - -static void -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf10000; -} - -static void -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf12000; -} - -static void -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11000; -} - -static void -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf13000; -} - -static void -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7042; -} - -static void -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7052; -} - -static void -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x47082; -} - -static void -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x57082; -} - -static void -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7062; -} - -static void -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7072; -} - -static void -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7002; -} - -static void -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7012; -} - -static void -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7022; -} - -static void -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x7032; -} - -static void -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf19000; -} - -static void -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf18000; -} - -static void -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135300; -} - -static void -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35300; -} - -static void -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615300; -} - -static void -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35a00; -} - -static void -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135a00; -} - -static void -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615a00; -} - -static void -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35b00; -} - -static void -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135b00; -} - -static void -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615b00; -} - -static void -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x35c00; -} - -static void -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x135c00; -} - -static void -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x615c00; -} - -static void -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50c000; -} - -static void -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50d000; -} - -static void -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50b000; -} - -static void -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50f000; -} - -static void -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50e000; -} - -static void -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x504000; -} - -static void -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x505000; -} - -static void -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x503000; -} - -static void -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x507000; -} - -static void -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x506000; -} - -static void -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf1f000; -} - -static void -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x501000; -} - -static void -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x509000; -} - -static void -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3e000; -} - -static void -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x13e000; -} - -static void -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x61e000; -} - -static void -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x330000; -} - -static void -Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1b9000; -} - -static void -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x430000; -} - -static void -Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bb000; -} - -static void -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x530000; -} - -static void -Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ba000; -} - -static void -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x630000; -} - -static void -Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bd000; -} - -static void -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x730000; -} - -static void -Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1bc000; -} - -static void -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40e000; -} - -static void -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40f000; -} - -static void -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x230000; -} - -static void -Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c6000; -} - -static void -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb002; -} - -static void -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf002; -} - -static void -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe002; -} - -static void -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30c00; -} - -static void -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x130c00; -} - -static void -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x610c00; -} - -static void -Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x36300; -} - -static void -Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x136300; -} - -static void -Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x616300; -} - -static void -Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x406000; -} - -static void -Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x407000; -} - -static void -Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f00; -} - -static void -Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f000; -} - -static void -Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f10; -} - -static void -Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f100; -} - -static void -Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f20; -} - -static void -Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f200; -} - -static void -Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30f30; -} - -static void -Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf3f300; -} - -static void -Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90804; -} - -static void -Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca0004; -} - -static void -Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90904; -} - -static void -Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca1004; -} - -static void -Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90a04; -} - -static void -Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca2004; -} - -static void -Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90b04; -} - -static void -Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca3004; -} - -static void -Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90c04; -} - -static void -Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca4004; -} - -static void -Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90d04; -} - -static void -Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca5004; -} - -static void -Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90e04; -} - -static void -Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca6004; -} - -static void -Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90f04; -} - -static void -Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca7004; -} - -static void -Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1080; -} - -static void -Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa50004; -} - -static void -Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2080; -} - -static void -Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa90004; -} - -static void -Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3000; -} - -static void -Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac0004; -} - -static void -Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d3080; -} - -static void -Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf0004; -} - -static void -Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6080; -} - -static void -Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa58004; -} - -static void -Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7000; -} - -static void -Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa98004; -} - -static void -Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d7080; -} - -static void -Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xac8004; -} - -static void -Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8080; -} - -static void -Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaf8004; -} - -static void -Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9000; -} - -static void -Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa60004; -} - -static void -Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da000; -} - -static void -Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa0004; -} - -static void -Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc000; -} - -static void -Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad0004; -} - -static void -Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d9080; -} - -static void -Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb00004; -} - -static void -Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4080; -} - -static void -Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa68004; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5000; -} - -static void -Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xaa8004; -} - -static void -Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d6000; -} - -static void -Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xad8004; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d5080; -} - -static void -Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb08004; -} - -static void -Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd000; -} - -static void -Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa70004; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de000; -} - -static void -Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab0004; -} - -static void -Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dd080; -} - -static void -Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae0004; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1de080; -} - -static void -Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb10004; -} - -static void -Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1da080; -} - -static void -Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa78004; -} - -static void -Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db000; -} - -static void -Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xab8004; -} - -static void -Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1db080; -} - -static void -Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xae8004; -} - -static void -Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1dc080; -} - -static void -Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb18004; -} - -static void -Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8000; -} - -static void -Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb20004; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0000; -} - -static void -Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb50004; -} - -static void -Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1080; -} - -static void -Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb80004; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2080; -} - -static void -Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb0004; -} - -static void -Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec000; -} - -static void -Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb28004; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9080; -} - -static void -Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb58004; -} - -static void -Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea080; -} - -static void -Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb88004; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb000; -} - -static void -Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbb8004; -} - -static void -Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7080; -} - -static void -Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb30004; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e8080; -} - -static void -Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb60004; -} - -static void -Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e9000; -} - -static void -Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb90004; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ea000; -} - -static void -Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc0004; -} - -static void -Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df080; -} - -static void -Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb38004; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e1000; -} - -static void -Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb68004; -} - -static void -Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e2000; -} - -static void -Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb98004; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4000; -} - -static void -Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbc8004; -} - -static void -Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6000; -} - -static void -Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb40004; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5080; -} - -static void -Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb70004; -} - -static void -Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e6080; -} - -static void -Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba0004; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e7000; -} - -static void -Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd0004; -} - -static void -Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3000; -} - -static void -Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb48004; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e3080; -} - -static void -Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xb78004; -} - -static void -Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e4080; -} - -static void -Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xba8004; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1e5000; -} - -static void -Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbd8004; -} - -static void -Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed030; -} - -static void -Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc10004; -} - -static void -Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee010; -} - -static void -Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc12004; -} - -static void -Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee020; -} - -static void -Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc20004; -} - -static void -Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ef000; -} - -static void -Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc22004; -} - -static void -Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed000; -} - -static void -Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc11004; -} - -static void -Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee000; -} - -static void -Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc13004; -} - -static void -Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed010; -} - -static void -Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc21004; -} - -static void -Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ed020; -} - -static void -Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc23004; -} - -static void -Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f0080; -} - -static void -Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc30004; -} - -static void -Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f00c0; -} - -static void -Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc38004; -} - -static void -Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3000; -} - -static void -Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc40004; -} - -static void -Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3040; -} - -static void -Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc48004; -} - -static void -Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec080; -} - -static void -Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc34004; -} - -static void -Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ec0c0; -} - -static void -Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc3c004; -} - -static void -Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f4000; -} - -static void -Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc44004; -} - -static void -Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f8000; -} - -static void -Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc4c004; -} - -static void -Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b88; -} - -static void -Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16808; -} - -static void -Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2400; -} - -static void -Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90004; -} - -static void -Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10780; -} - -static void -Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10708; -} - -static void -Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10688; -} - -static void -Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10700; -} - -static void -Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c200; -} - -static void -Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c004; -} - -static void -Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10480; -} - -static void -Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10400; -} - -static void -Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1df000; -} - -static void -Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc00004; -} - -static void -Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1eb080; -} - -static void -Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc08004; -} - -static void -Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3081; -} - -static void -Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb0004; -} - -static void -Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3080; -} - -static void -Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xcb8004; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d8000; -} - -static void -Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe0004; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d4000; -} - -static void -Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbe8004; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d2000; -} - -static void -Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf0004; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1d1000; -} - -static void -Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xbf8004; -} - -static void -Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x51000; -} - -static void -Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16b08; -} - -static void -Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e48; -} - -static void -Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e28; -} - -static void -Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e18; -} - -static void -Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16e08; -} - -static void -Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16908; -} - -static void -Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16888; -} - -static void -Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16085; -} - -static void -Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16007; -} - -static void -Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2500; -} - -static void -Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90414; -} - -static void -Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f6000; -} - -static void -Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe50014; -} - -static void -Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5000; -} - -static void -Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe60014; -} - -static void -Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1ee030; -} - -static void -Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe72034; -} - -static void -Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16006; -} - -static void -Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16005; -} - -static void -Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50139; -} - -static void -Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16047; -} - -static void -Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16027; -} - -static void -Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16017; -} - -static void -Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3086; -} - -static void -Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe70014; -} - -static void -Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3084; -} - -static void -Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc70004; -} - -static void -Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3082; -} - -static void -Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc78004; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3083; -} - -static void -Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc80004; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3088; -} - -static void -Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc88004; -} - -static void -Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10500; -} - -static void -Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10788; -} - -static void -Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c600; -} - -static void -Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c480; -} - -static void -Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10580; -} - -static void -Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10588; -} - -static void -Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10000; -} - -static void -Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10200; -} - -static void -Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10600; -} - -static void -Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c400; -} - -static void -Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c488; -} - -static void -Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c500; -} - -static void -Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10508; -} - -static void -Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10608; -} - -static void -Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x10680; -} - -static void -Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c408; -} - -static void -Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c002; -} - -static void -Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c001; -} - -static void -Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1c000; -} - -static void -Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x52000; -} - -static void -Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50035; -} - -static void -Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003c; -} - -static void -Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50039; -} - -static void -Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50032; -} - -static void -Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50034; -} - -static void -Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50000; -} - -static void -Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50010; -} - -static void -Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50030; -} - -static void -Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50036; -} - -static void -Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x500b9; -} - -static void -Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5003a; -} - -static void -Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50031; -} - -static void -Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50038; -} - -static void -Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50033; -} - -static void -Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50037; -} - -static void -Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14000; -} - -static void -Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15000; -} - -static void -Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x14800; -} - -static void -Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a08; -} - -static void -Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16a88; -} - -static void -Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16988; -} - -static void -Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x18000; -} - -static void -Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16c08; -} - -static void -Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1000; -} - -static void -Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50004; -} - -static void -Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1800; -} - -static void -Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50404; -} - -static void -Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f1400; -} - -static void -Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50804; -} - -static void -Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2600; -} - -static void -Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90014; -} - -static void -Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2504; -} - -static void -Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90114; -} - -static void -Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2502; -} - -static void -Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90214; -} - -static void -Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5001; -} - -static void -Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe10014; -} - -static void -Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5008; -} - -static void -Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe20014; -} - -static void -Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5004; -} - -static void -Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe30014; -} - -static void -Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2000; -} - -static void -Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc50c04; -} - -static void -Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f2501; -} - -static void -Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc90314; -} - -static void -Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f5002; -} - -static void -Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe40014; -} - -static void -Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50800; -} - -static void -Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50040; -} - -static void -Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x50020; -} - -static void -Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1f3085; -} - -static void -Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe74014; -} - -static void -Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60101; -} - -static void -Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008b; -} - -static void -Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60180; -} - -static void -Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008f; -} - -static void -Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008c; -} - -static void -Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60108; -} - -static void -Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008e; -} - -static void -Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008a; -} - -static void -Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60104; -} - -static void -Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6008d; -} - -static void -Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60089; -} - -static void -Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60102; -} - -static void -Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60006; -} - -static void -Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64000; -} - -static void -Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000f; -} - -static void -Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60005; -} - -static void -Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60100; -} - -static void -Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000e; -} - -static void -Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60003; -} - -static void -Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60080; -} - -static void -Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000d; -} - -static void -Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x68000; -} - -static void -Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60008; -} - -static void -Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000b; -} - -static void -Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60181; -} - -static void -Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010b; -} - -static void -Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60189; -} - -static void -Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010f; -} - -static void -Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010c; -} - -static void -Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60187; -} - -static void -Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010e; -} - -static void -Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010a; -} - -static void -Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60186; -} - -static void -Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6010d; -} - -static void -Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60109; -} - -static void -Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60185; -} - -static void -Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000c; -} - -static void -Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60088; -} - -static void -Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6000a; -} - -static void -Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60084; -} - -static void -Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60009; -} - -static void -Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60082; -} - -static void -Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60007; -} - -static void -Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60081; -} - -static void -Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60183; -} - -static void -Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018d; -} - -static void -Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60188; -} - -static void -Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018b; -} - -static void -Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60184; -} - -static void -Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018c; -} - -static void -Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60182; -} - -static void -Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018a; -} - -static void -Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15807; -} - -static void -Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15806; -} - -static void -Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580a; -} - -static void -Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15809; -} - -static void -Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580b; -} - -static void -Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580c; -} - -static void -Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580e; -} - -static void -Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580d; -} - -static void -Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15800; -} - -static void -Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16000; -} - -static void -Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15802; -} - -static void -Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15801; -} - -static void -Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15808; -} - -static void -Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15804; -} - -static void -Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15805; -} - -static void -Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x15803; -} - -static void -Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16001; -} - -static void -Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x1580f; -} - -static void -Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16004; -} - -static void -Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16002; -} - -static void -Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16800; -} - -static void -Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16008; -} - -static void -Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x16003; -} - -static void -Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x17000; -} - -static void -Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20007; -} - -static void -Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20002; -} - -static void -Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000c; -} - -static void -Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20003; -} - -static void -Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20005; -} - -static void -Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20000; -} - -static void -Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20009; -} - -static void -Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20004; -} - -static void -Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20006; -} - -static void -Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20001; -} - -static void -Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000a; -} - -static void -Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x20008; -} - -static void -Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30008; -} - -static void -Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000e; -} - -static void -Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30006; -} - -static void -Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30001; -} - -static void -Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30002; -} - -static void -Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000b; -} - -static void -Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30003; -} - -static void -Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000f; -} - -static void -Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30004; -} - -static void -Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x2000d; -} - -static void -Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30005; -} - -static void -Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30000; -} - -static void -Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40000; -} - -static void -Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000a; -} - -static void -Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40004; -} - -static void -Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000d; -} - -static void -Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000e; -} - -static void -Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30007; -} - -static void -Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40001; -} - -static void -Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000c; -} - -static void -Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000f; -} - -static void -Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x30009; -} - -static void -Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40002; -} - -static void -Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x3000b; -} - -static void -Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000b; -} - -static void -Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40005; -} - -static void -Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000f; -} - -static void -Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40009; -} - -static void -Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000a; -} - -static void -Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40008; -} - -static void -Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000d; -} - -static void -Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40006; -} - -static void -Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000c; -} - -static void -Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40003; -} - -static void -Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x4000e; -} - -static void -Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x40007; -} - -static void -Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64004; -} - -static void -Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64080; -} - -static void -Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64008; -} - -static void -Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64100; -} - -static void -Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64003; -} - -static void -Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64006; -} - -static void -Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64005; -} - -static void -Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64007; -} - -static void -Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64009; -} - -static void -Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400c; -} - -static void -Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400a; -} - -static void -Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400b; -} - -static void -Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400d; -} - -static void -Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400f; -} - -static void -Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6400e; -} - -static void -Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64081; -} - -static void -Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60000; -} - -static void -Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60002; -} - -static void -Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60001; -} - -static void -Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60004; -} - -static void -Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60083; -} - -static void -Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60086; -} - -static void -Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60085; -} - -static void -Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60087; -} - -static void -Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60103; -} - -static void -Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60106; -} - -static void -Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60105; -} - -static void -Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x60107; -} - -static void -Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018e; -} - -static void -Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64001; -} - -static void -Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x6018f; -} - -static void -Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x64002; -} - -static void -Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00014; -} - -static void -Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa00004; -} - -static void -Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa10004; -} - -static void -Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7e014; -} - -static void -Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xca8004; -} - -static void -Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xc60004; -} - -static void -Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00024; -} - -static void -Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa20004; -} - -static void -Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe00004; -} - -static void -Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf01004; -} - -static void -Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf02004; -} - -static void -Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa30004; -} - -static void -Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xa40004; -} - -static void -Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf11004; -} - -static void -Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xf00004; -} - -static void -Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7c014; -} - -static void -Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0xe7d014; -} - -static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { - 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { - Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { - Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { - Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { - Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { - Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { - Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { - Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { - Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { - Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { - Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { - Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { - Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { - Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { - Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { - Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { - Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { - Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { - Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { - Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { - Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { - Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { - Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { - Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { - Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { - Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { - Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { - Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { - Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { - Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { - Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { - Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { - Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { - Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { - Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { - Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { - Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { - Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { - Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { - Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { - Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { - Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { - Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { - Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { - Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { - Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { - Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { - Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { - Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { - Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { - Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { - Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { - Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { - Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { - Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { - Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { - Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { - Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { - Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { - Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { - Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { - Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { - Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { - Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { - Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { - Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { - Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { - Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { - Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { - Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { - Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { - Opcode_break_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { - Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { - Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { - Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { - Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { - Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { - Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { - Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { - Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { - Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { - Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { - Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { - Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { - Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { - Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { - Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { - Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { - Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { - Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { - Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { - Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { - Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { - Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { - Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { - Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { - Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { - Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { - Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { - Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { - Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { - Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { - Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { - Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { - Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { - Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { - Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { - Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { - Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { - Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { - Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { - Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { - Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { - Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { - Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { - Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { - Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { - Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { - Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { - Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { - Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { - Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { - Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { - Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { - Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { - Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { - Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { - Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { - Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { - Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { - Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { - Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { - Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { - Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { - Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { - Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { - Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { - Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { - Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { - Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { - Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { - Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { - Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { - Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { - Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { - Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { - Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { - Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { - Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { - Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { - Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { - Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { - Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { - Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { - Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { - Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { - Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { - Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { - Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { - Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { - Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { - Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { - Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { - Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { - Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { - Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { - Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { - Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { - Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { - Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { - Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { - Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { - Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { - Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { - Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { - Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { - Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { - Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { - Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { - Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { - Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { - Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { - Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { - Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { - Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { - 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { - Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { - Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { - Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { - Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { - Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { - Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { - Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { - Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { - Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { - Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { - Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { - 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { - 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { - 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { - Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { - Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { - Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { - Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { - Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { - 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { - 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { - Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { - Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { - Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { - Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { - Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { - Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { - Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { - Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { - Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { - Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { - Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { - Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { - 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { - 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { - Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { - 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { - Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { - Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { - Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { - Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { - Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { - Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { - Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { - Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { - Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { - Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { - Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { - Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { - Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { - Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { - Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { - Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 -}; - -static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { - Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 -}; - - -/* Opcode table. */ - -static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_shift32x5, 3 }, - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { - { FUNCUNIT_ae_add32, 3 } -}; - -static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { - { FUNCUNIT_ae_shift32x4, 2 }, - { FUNCUNIT_ae_subshift, 2 } -}; - -static xtensa_opcode_internal opcodes[] = { - { "excw", ICLASS_xt_iclass_excw, - 0, - Opcode_excw_encode_fns, 0, 0 }, - { "rfe", ICLASS_xt_iclass_rfe, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfe_encode_fns, 0, 0 }, - { "rfde", ICLASS_xt_iclass_rfde, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfde_encode_fns, 0, 0 }, - { "syscall", ICLASS_xt_iclass_syscall, - 0, - Opcode_syscall_encode_fns, 0, 0 }, - { "call12", ICLASS_xt_iclass_call12, - XTENSA_OPCODE_IS_CALL, - Opcode_call12_encode_fns, 0, 0 }, - { "call8", ICLASS_xt_iclass_call8, - XTENSA_OPCODE_IS_CALL, - Opcode_call8_encode_fns, 0, 0 }, - { "call4", ICLASS_xt_iclass_call4, - XTENSA_OPCODE_IS_CALL, - Opcode_call4_encode_fns, 0, 0 }, - { "callx12", ICLASS_xt_iclass_callx12, - XTENSA_OPCODE_IS_CALL, - Opcode_callx12_encode_fns, 0, 0 }, - { "callx8", ICLASS_xt_iclass_callx8, - XTENSA_OPCODE_IS_CALL, - Opcode_callx8_encode_fns, 0, 0 }, - { "callx4", ICLASS_xt_iclass_callx4, - XTENSA_OPCODE_IS_CALL, - Opcode_callx4_encode_fns, 0, 0 }, - { "entry", ICLASS_xt_iclass_entry, - 0, - Opcode_entry_encode_fns, 0, 0 }, - { "movsp", ICLASS_xt_iclass_movsp, - 0, - Opcode_movsp_encode_fns, 0, 0 }, - { "rotw", ICLASS_xt_iclass_rotw, - 0, - Opcode_rotw_encode_fns, 0, 0 }, - { "retw", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_encode_fns, 0, 0 }, - { "retw.n", ICLASS_xt_iclass_retw, - XTENSA_OPCODE_IS_JUMP, - Opcode_retw_n_encode_fns, 0, 0 }, - { "rfwo", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwo_encode_fns, 0, 0 }, - { "rfwu", ICLASS_xt_iclass_rfwou, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfwu_encode_fns, 0, 0 }, - { "l32e", ICLASS_xt_iclass_l32e, - 0, - Opcode_l32e_encode_fns, 0, 0 }, - { "s32e", ICLASS_xt_iclass_s32e, - 0, - Opcode_s32e_encode_fns, 0, 0 }, - { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, - 0, - Opcode_rsr_windowbase_encode_fns, 0, 0 }, - { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, - 0, - Opcode_wsr_windowbase_encode_fns, 0, 0 }, - { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, - 0, - Opcode_xsr_windowbase_encode_fns, 0, 0 }, - { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, - 0, - Opcode_rsr_windowstart_encode_fns, 0, 0 }, - { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, - 0, - Opcode_wsr_windowstart_encode_fns, 0, 0 }, - { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, - 0, - Opcode_xsr_windowstart_encode_fns, 0, 0 }, - { "add.n", ICLASS_xt_iclass_add_n, - 0, - Opcode_add_n_encode_fns, 0, 0 }, - { "addi.n", ICLASS_xt_iclass_addi_n, - 0, - Opcode_addi_n_encode_fns, 0, 0 }, - { "beqz.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_n_encode_fns, 0, 0 }, - { "bnez.n", ICLASS_xt_iclass_bz6, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_n_encode_fns, 0, 0 }, - { "ill.n", ICLASS_xt_iclass_ill_n, - 0, - Opcode_ill_n_encode_fns, 0, 0 }, - { "l32i.n", ICLASS_xt_iclass_loadi4, - 0, - Opcode_l32i_n_encode_fns, 0, 0 }, - { "mov.n", ICLASS_xt_iclass_mov_n, - 0, - Opcode_mov_n_encode_fns, 0, 0 }, - { "movi.n", ICLASS_xt_iclass_movi_n, - 0, - Opcode_movi_n_encode_fns, 0, 0 }, - { "nop.n", ICLASS_xt_iclass_nopn, - 0, - Opcode_nop_n_encode_fns, 0, 0 }, - { "ret.n", ICLASS_xt_iclass_retn, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_n_encode_fns, 0, 0 }, - { "s32i.n", ICLASS_xt_iclass_storei4, - 0, - Opcode_s32i_n_encode_fns, 0, 0 }, - { "rur.threadptr", ICLASS_rur_threadptr, - 0, - Opcode_rur_threadptr_encode_fns, 0, 0 }, - { "wur.threadptr", ICLASS_wur_threadptr, - 0, - Opcode_wur_threadptr_encode_fns, 0, 0 }, - { "addi", ICLASS_xt_iclass_addi, - 0, - Opcode_addi_encode_fns, 0, 0 }, - { "addmi", ICLASS_xt_iclass_addmi, - 0, - Opcode_addmi_encode_fns, 0, 0 }, - { "add", ICLASS_xt_iclass_addsub, - 0, - Opcode_add_encode_fns, 0, 0 }, - { "sub", ICLASS_xt_iclass_addsub, - 0, - Opcode_sub_encode_fns, 0, 0 }, - { "addx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx2_encode_fns, 0, 0 }, - { "addx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx4_encode_fns, 0, 0 }, - { "addx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_addx8_encode_fns, 0, 0 }, - { "subx2", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx2_encode_fns, 0, 0 }, - { "subx4", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx4_encode_fns, 0, 0 }, - { "subx8", ICLASS_xt_iclass_addsub, - 0, - Opcode_subx8_encode_fns, 0, 0 }, - { "and", ICLASS_xt_iclass_bit, - 0, - Opcode_and_encode_fns, 0, 0 }, - { "or", ICLASS_xt_iclass_bit, - 0, - Opcode_or_encode_fns, 0, 0 }, - { "xor", ICLASS_xt_iclass_bit, - 0, - Opcode_xor_encode_fns, 0, 0 }, - { "beqi", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqi_encode_fns, 0, 0 }, - { "bnei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnei_encode_fns, 0, 0 }, - { "bgei", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgei_encode_fns, 0, 0 }, - { "blti", ICLASS_xt_iclass_bsi8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blti_encode_fns, 0, 0 }, - { "bbci", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbci_encode_fns, 0, 0 }, - { "bbsi", ICLASS_xt_iclass_bsi8b, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbsi_encode_fns, 0, 0 }, - { "bgeui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeui_encode_fns, 0, 0 }, - { "bltui", ICLASS_xt_iclass_bsi8u, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltui_encode_fns, 0, 0 }, - { "beq", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beq_encode_fns, 0, 0 }, - { "bne", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bne_encode_fns, 0, 0 }, - { "bge", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bge_encode_fns, 0, 0 }, - { "blt", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_blt_encode_fns, 0, 0 }, - { "bgeu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgeu_encode_fns, 0, 0 }, - { "bltu", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltu_encode_fns, 0, 0 }, - { "bany", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bany_encode_fns, 0, 0 }, - { "bnone", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnone_encode_fns, 0, 0 }, - { "ball", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_ball_encode_fns, 0, 0 }, - { "bnall", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnall_encode_fns, 0, 0 }, - { "bbc", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbc_encode_fns, 0, 0 }, - { "bbs", ICLASS_xt_iclass_bst8, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bbs_encode_fns, 0, 0 }, - { "beqz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_beqz_encode_fns, 0, 0 }, - { "bnez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bnez_encode_fns, 0, 0 }, - { "bgez", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bgez_encode_fns, 0, 0 }, - { "bltz", ICLASS_xt_iclass_bsz12, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bltz_encode_fns, 0, 0 }, - { "call0", ICLASS_xt_iclass_call0, - XTENSA_OPCODE_IS_CALL, - Opcode_call0_encode_fns, 0, 0 }, - { "callx0", ICLASS_xt_iclass_callx0, - XTENSA_OPCODE_IS_CALL, - Opcode_callx0_encode_fns, 0, 0 }, - { "extui", ICLASS_xt_iclass_exti, - 0, - Opcode_extui_encode_fns, 0, 0 }, - { "ill", ICLASS_xt_iclass_ill, - 0, - Opcode_ill_encode_fns, 0, 0 }, - { "j", ICLASS_xt_iclass_jump, - XTENSA_OPCODE_IS_JUMP, - Opcode_j_encode_fns, 0, 0 }, - { "jx", ICLASS_xt_iclass_jumpx, - XTENSA_OPCODE_IS_JUMP, - Opcode_jx_encode_fns, 0, 0 }, - { "l16ui", ICLASS_xt_iclass_l16ui, - 0, - Opcode_l16ui_encode_fns, 0, 0 }, - { "l16si", ICLASS_xt_iclass_l16si, - 0, - Opcode_l16si_encode_fns, 0, 0 }, - { "l32i", ICLASS_xt_iclass_l32i, - 0, - Opcode_l32i_encode_fns, 0, 0 }, - { "l32r", ICLASS_xt_iclass_l32r, - 0, - Opcode_l32r_encode_fns, 0, 0 }, - { "l8ui", ICLASS_xt_iclass_l8i, - 0, - Opcode_l8ui_encode_fns, 0, 0 }, - { "loop", ICLASS_xt_iclass_loop, - XTENSA_OPCODE_IS_LOOP, - Opcode_loop_encode_fns, 0, 0 }, - { "loopnez", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopnez_encode_fns, 0, 0 }, - { "loopgtz", ICLASS_xt_iclass_loopz, - XTENSA_OPCODE_IS_LOOP, - Opcode_loopgtz_encode_fns, 0, 0 }, - { "movi", ICLASS_xt_iclass_movi, - 0, - Opcode_movi_encode_fns, 0, 0 }, - { "moveqz", ICLASS_xt_iclass_movz, - 0, - Opcode_moveqz_encode_fns, 0, 0 }, - { "movnez", ICLASS_xt_iclass_movz, - 0, - Opcode_movnez_encode_fns, 0, 0 }, - { "movltz", ICLASS_xt_iclass_movz, - 0, - Opcode_movltz_encode_fns, 0, 0 }, - { "movgez", ICLASS_xt_iclass_movz, - 0, - Opcode_movgez_encode_fns, 0, 0 }, - { "neg", ICLASS_xt_iclass_neg, - 0, - Opcode_neg_encode_fns, 0, 0 }, - { "abs", ICLASS_xt_iclass_neg, - 0, - Opcode_abs_encode_fns, 0, 0 }, - { "nop", ICLASS_xt_iclass_nop, - 0, - Opcode_nop_encode_fns, 0, 0 }, - { "ret", ICLASS_xt_iclass_return, - XTENSA_OPCODE_IS_JUMP, - Opcode_ret_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, - { "s16i", ICLASS_xt_iclass_s16i, - 0, - Opcode_s16i_encode_fns, 0, 0 }, - { "s32i", ICLASS_xt_iclass_s32i, - 0, - Opcode_s32i_encode_fns, 0, 0 }, - { "s8i", ICLASS_xt_iclass_s8i, - 0, - Opcode_s8i_encode_fns, 0, 0 }, - { "ssr", ICLASS_xt_iclass_sar, - 0, - Opcode_ssr_encode_fns, 0, 0 }, - { "ssl", ICLASS_xt_iclass_sar, - 0, - Opcode_ssl_encode_fns, 0, 0 }, - { "ssa8l", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8l_encode_fns, 0, 0 }, - { "ssa8b", ICLASS_xt_iclass_sar, - 0, - Opcode_ssa8b_encode_fns, 0, 0 }, - { "ssai", ICLASS_xt_iclass_sari, - 0, - Opcode_ssai_encode_fns, 0, 0 }, - { "sll", ICLASS_xt_iclass_shifts, - 0, - Opcode_sll_encode_fns, 0, 0 }, - { "src", ICLASS_xt_iclass_shiftst, - 0, - Opcode_src_encode_fns, 0, 0 }, - { "srl", ICLASS_xt_iclass_shiftt, - 0, - Opcode_srl_encode_fns, 0, 0 }, - { "sra", ICLASS_xt_iclass_shiftt, - 0, - Opcode_sra_encode_fns, 0, 0 }, - { "slli", ICLASS_xt_iclass_slli, - 0, - Opcode_slli_encode_fns, 0, 0 }, - { "srai", ICLASS_xt_iclass_srai, - 0, - Opcode_srai_encode_fns, 0, 0 }, - { "srli", ICLASS_xt_iclass_srli, - 0, - Opcode_srli_encode_fns, 0, 0 }, - { "memw", ICLASS_xt_iclass_memw, - 0, - Opcode_memw_encode_fns, 0, 0 }, - { "extw", ICLASS_xt_iclass_extw, - 0, - Opcode_extw_encode_fns, 0, 0 }, - { "isync", ICLASS_xt_iclass_isync, - 0, - Opcode_isync_encode_fns, 0, 0 }, - { "rsync", ICLASS_xt_iclass_sync, - 0, - Opcode_rsync_encode_fns, 0, 0 }, - { "esync", ICLASS_xt_iclass_sync, - 0, - Opcode_esync_encode_fns, 0, 0 }, - { "dsync", ICLASS_xt_iclass_sync, - 0, - Opcode_dsync_encode_fns, 0, 0 }, - { "rsil", ICLASS_xt_iclass_rsil, - 0, - Opcode_rsil_encode_fns, 0, 0 }, - { "rsr.lend", ICLASS_xt_iclass_rsr_lend, - 0, - Opcode_rsr_lend_encode_fns, 0, 0 }, - { "wsr.lend", ICLASS_xt_iclass_wsr_lend, - 0, - Opcode_wsr_lend_encode_fns, 0, 0 }, - { "xsr.lend", ICLASS_xt_iclass_xsr_lend, - 0, - Opcode_xsr_lend_encode_fns, 0, 0 }, - { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, - 0, - Opcode_rsr_lcount_encode_fns, 0, 0 }, - { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, - 0, - Opcode_wsr_lcount_encode_fns, 0, 0 }, - { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, - 0, - Opcode_xsr_lcount_encode_fns, 0, 0 }, - { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, - 0, - Opcode_rsr_lbeg_encode_fns, 0, 0 }, - { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, - 0, - Opcode_wsr_lbeg_encode_fns, 0, 0 }, - { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, - 0, - Opcode_xsr_lbeg_encode_fns, 0, 0 }, - { "rsr.sar", ICLASS_xt_iclass_rsr_sar, - 0, - Opcode_rsr_sar_encode_fns, 0, 0 }, - { "wsr.sar", ICLASS_xt_iclass_wsr_sar, - 0, - Opcode_wsr_sar_encode_fns, 0, 0 }, - { "xsr.sar", ICLASS_xt_iclass_xsr_sar, - 0, - Opcode_xsr_sar_encode_fns, 0, 0 }, - { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, - 0, - Opcode_rsr_litbase_encode_fns, 0, 0 }, - { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, - 0, - Opcode_wsr_litbase_encode_fns, 0, 0 }, - { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, - 0, - Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, - 0, - Opcode_rsr_configid0_encode_fns, 0, 0 }, - { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, - 0, - Opcode_wsr_configid0_encode_fns, 0, 0 }, - { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, - 0, - Opcode_rsr_configid1_encode_fns, 0, 0 }, - { "rsr.ps", ICLASS_xt_iclass_rsr_ps, - 0, - Opcode_rsr_ps_encode_fns, 0, 0 }, - { "wsr.ps", ICLASS_xt_iclass_wsr_ps, - 0, - Opcode_wsr_ps_encode_fns, 0, 0 }, - { "xsr.ps", ICLASS_xt_iclass_xsr_ps, - 0, - Opcode_xsr_ps_encode_fns, 0, 0 }, - { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, - 0, - Opcode_rsr_epc1_encode_fns, 0, 0 }, - { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, - 0, - Opcode_wsr_epc1_encode_fns, 0, 0 }, - { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, - 0, - Opcode_xsr_epc1_encode_fns, 0, 0 }, - { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, - 0, - Opcode_rsr_excsave1_encode_fns, 0, 0 }, - { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, - 0, - Opcode_wsr_excsave1_encode_fns, 0, 0 }, - { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, - 0, - Opcode_xsr_excsave1_encode_fns, 0, 0 }, - { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, - 0, - Opcode_rsr_epc2_encode_fns, 0, 0 }, - { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, - 0, - Opcode_wsr_epc2_encode_fns, 0, 0 }, - { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, - 0, - Opcode_xsr_epc2_encode_fns, 0, 0 }, - { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, - 0, - Opcode_rsr_excsave2_encode_fns, 0, 0 }, - { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, - 0, - Opcode_wsr_excsave2_encode_fns, 0, 0 }, - { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, - 0, - Opcode_xsr_excsave2_encode_fns, 0, 0 }, - { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, - 0, - Opcode_rsr_eps2_encode_fns, 0, 0 }, - { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, - 0, - Opcode_wsr_eps2_encode_fns, 0, 0 }, - { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, - 0, - Opcode_xsr_eps2_encode_fns, 0, 0 }, - { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, - 0, - Opcode_rsr_excvaddr_encode_fns, 0, 0 }, - { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, - 0, - Opcode_wsr_excvaddr_encode_fns, 0, 0 }, - { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, - 0, - Opcode_xsr_excvaddr_encode_fns, 0, 0 }, - { "rsr.depc", ICLASS_xt_iclass_rsr_depc, - 0, - Opcode_rsr_depc_encode_fns, 0, 0 }, - { "wsr.depc", ICLASS_xt_iclass_wsr_depc, - 0, - Opcode_wsr_depc_encode_fns, 0, 0 }, - { "xsr.depc", ICLASS_xt_iclass_xsr_depc, - 0, - Opcode_xsr_depc_encode_fns, 0, 0 }, - { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, - 0, - Opcode_rsr_exccause_encode_fns, 0, 0 }, - { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, - 0, - Opcode_wsr_exccause_encode_fns, 0, 0 }, - { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, - 0, - Opcode_xsr_exccause_encode_fns, 0, 0 }, - { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, - 0, - Opcode_rsr_misc0_encode_fns, 0, 0 }, - { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, - 0, - Opcode_wsr_misc0_encode_fns, 0, 0 }, - { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, - 0, - Opcode_xsr_misc0_encode_fns, 0, 0 }, - { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, - 0, - Opcode_rsr_misc1_encode_fns, 0, 0 }, - { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, - 0, - Opcode_wsr_misc1_encode_fns, 0, 0 }, - { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, - 0, - Opcode_xsr_misc1_encode_fns, 0, 0 }, - { "rsr.prid", ICLASS_xt_iclass_rsr_prid, - 0, - Opcode_rsr_prid_encode_fns, 0, 0 }, - { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, - 0, - Opcode_rsr_vecbase_encode_fns, 0, 0 }, - { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, - 0, - Opcode_wsr_vecbase_encode_fns, 0, 0 }, - { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, - 0, - Opcode_xsr_vecbase_encode_fns, 0, 0 }, - { "mul16u", ICLASS_xt_mul16, - 0, - Opcode_mul16u_encode_fns, 0, 0 }, - { "mul16s", ICLASS_xt_mul16, - 0, - Opcode_mul16s_encode_fns, 0, 0 }, - { "mull", ICLASS_xt_mul32, - 0, - Opcode_mull_encode_fns, 0, 0 }, - { "rfi", ICLASS_xt_iclass_rfi, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfi_encode_fns, 0, 0 }, - { "waiti", ICLASS_xt_iclass_wait, - 0, - Opcode_waiti_encode_fns, 0, 0 }, - { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, - 0, - Opcode_rsr_interrupt_encode_fns, 0, 0 }, - { "wsr.intset", ICLASS_xt_iclass_wsr_intset, - 0, - Opcode_wsr_intset_encode_fns, 0, 0 }, - { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, - 0, - Opcode_wsr_intclear_encode_fns, 0, 0 }, - { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, - 0, - Opcode_rsr_intenable_encode_fns, 0, 0 }, - { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, - 0, - Opcode_wsr_intenable_encode_fns, 0, 0 }, - { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, - 0, - Opcode_xsr_intenable_encode_fns, 0, 0 }, - { "break", ICLASS_xt_iclass_break, - 0, - Opcode_break_encode_fns, 0, 0 }, - { "break.n", ICLASS_xt_iclass_break_n, - 0, - Opcode_break_n_encode_fns, 0, 0 }, - { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, - 0, - Opcode_rsr_debugcause_encode_fns, 0, 0 }, - { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, - 0, - Opcode_wsr_debugcause_encode_fns, 0, 0 }, - { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, - 0, - Opcode_xsr_debugcause_encode_fns, 0, 0 }, - { "rsr.icount", ICLASS_xt_iclass_rsr_icount, - 0, - Opcode_rsr_icount_encode_fns, 0, 0 }, - { "wsr.icount", ICLASS_xt_iclass_wsr_icount, - 0, - Opcode_wsr_icount_encode_fns, 0, 0 }, - { "xsr.icount", ICLASS_xt_iclass_xsr_icount, - 0, - Opcode_xsr_icount_encode_fns, 0, 0 }, - { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, - 0, - Opcode_rsr_icountlevel_encode_fns, 0, 0 }, - { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, - 0, - Opcode_wsr_icountlevel_encode_fns, 0, 0 }, - { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, - 0, - Opcode_xsr_icountlevel_encode_fns, 0, 0 }, - { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, - 0, - Opcode_rsr_ddr_encode_fns, 0, 0 }, - { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, - 0, - Opcode_wsr_ddr_encode_fns, 0, 0 }, - { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, - 0, - Opcode_xsr_ddr_encode_fns, 0, 0 }, - { "rfdo", ICLASS_xt_iclass_rfdo, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdo_encode_fns, 0, 0 }, - { "rfdd", ICLASS_xt_iclass_rfdd, - XTENSA_OPCODE_IS_JUMP, - Opcode_rfdd_encode_fns, 0, 0 }, - { "andb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andb_encode_fns, 0, 0 }, - { "andbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_andbc_encode_fns, 0, 0 }, - { "orb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orb_encode_fns, 0, 0 }, - { "orbc", ICLASS_xt_iclass_bbool1, - 0, - Opcode_orbc_encode_fns, 0, 0 }, - { "xorb", ICLASS_xt_iclass_bbool1, - 0, - Opcode_xorb_encode_fns, 0, 0 }, - { "any4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_any4_encode_fns, 0, 0 }, - { "all4", ICLASS_xt_iclass_bbool4, - 0, - Opcode_all4_encode_fns, 0, 0 }, - { "any8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_any8_encode_fns, 0, 0 }, - { "all8", ICLASS_xt_iclass_bbool8, - 0, - Opcode_all8_encode_fns, 0, 0 }, - { "bf", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bf_encode_fns, 0, 0 }, - { "bt", ICLASS_xt_iclass_bbranch, - XTENSA_OPCODE_IS_BRANCH, - Opcode_bt_encode_fns, 0, 0 }, - { "movf", ICLASS_xt_iclass_bmove, - 0, - Opcode_movf_encode_fns, 0, 0 }, - { "movt", ICLASS_xt_iclass_bmove, - 0, - Opcode_movt_encode_fns, 0, 0 }, - { "rsr.br", ICLASS_xt_iclass_RSR_BR, - 0, - Opcode_rsr_br_encode_fns, 0, 0 }, - { "wsr.br", ICLASS_xt_iclass_WSR_BR, - 0, - Opcode_wsr_br_encode_fns, 0, 0 }, - { "xsr.br", ICLASS_xt_iclass_XSR_BR, - 0, - Opcode_xsr_br_encode_fns, 0, 0 }, - { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, - 0, - Opcode_rsr_ccount_encode_fns, 0, 0 }, - { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, - 0, - Opcode_wsr_ccount_encode_fns, 0, 0 }, - { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, - 0, - Opcode_xsr_ccount_encode_fns, 0, 0 }, - { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, - 0, - Opcode_rsr_ccompare0_encode_fns, 0, 0 }, - { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, - 0, - Opcode_wsr_ccompare0_encode_fns, 0, 0 }, - { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, - 0, - Opcode_xsr_ccompare0_encode_fns, 0, 0 }, - { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, - 0, - Opcode_rsr_ccompare1_encode_fns, 0, 0 }, - { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, - 0, - Opcode_wsr_ccompare1_encode_fns, 0, 0 }, - { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, - 0, - Opcode_xsr_ccompare1_encode_fns, 0, 0 }, - { "ipf", ICLASS_xt_iclass_icache, - 0, - Opcode_ipf_encode_fns, 0, 0 }, - { "ihi", ICLASS_xt_iclass_icache, - 0, - Opcode_ihi_encode_fns, 0, 0 }, - { "iii", ICLASS_xt_iclass_icache_inv, - 0, - Opcode_iii_encode_fns, 0, 0 }, - { "lict", ICLASS_xt_iclass_licx, - 0, - Opcode_lict_encode_fns, 0, 0 }, - { "licw", ICLASS_xt_iclass_licx, - 0, - Opcode_licw_encode_fns, 0, 0 }, - { "sict", ICLASS_xt_iclass_sicx, - 0, - Opcode_sict_encode_fns, 0, 0 }, - { "sicw", ICLASS_xt_iclass_sicx, - 0, - Opcode_sicw_encode_fns, 0, 0 }, - { "dhwb", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwb_encode_fns, 0, 0 }, - { "dhwbi", ICLASS_xt_iclass_dcache, - 0, - Opcode_dhwbi_encode_fns, 0, 0 }, - { "diwb", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwb_encode_fns, 0, 0 }, - { "diwbi", ICLASS_xt_iclass_dcache_ind, - 0, - Opcode_diwbi_encode_fns, 0, 0 }, - { "dhi", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dhi_encode_fns, 0, 0 }, - { "dii", ICLASS_xt_iclass_dcache_inv, - 0, - Opcode_dii_encode_fns, 0, 0 }, - { "dpfr", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfr_encode_fns, 0, 0 }, - { "dpfw", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfw_encode_fns, 0, 0 }, - { "dpfro", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfro_encode_fns, 0, 0 }, - { "dpfwo", ICLASS_xt_iclass_dpf, - 0, - Opcode_dpfwo_encode_fns, 0, 0 }, - { "sdct", ICLASS_xt_iclass_sdct, - 0, - Opcode_sdct_encode_fns, 0, 0 }, - { "ldct", ICLASS_xt_iclass_ldct, - 0, - Opcode_ldct_encode_fns, 0, 0 }, - { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, - 0, - Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, - 0, - Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, - { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, - 0, - Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, - { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, - 0, - Opcode_rsr_rasid_encode_fns, 0, 0 }, - { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, - 0, - Opcode_wsr_rasid_encode_fns, 0, 0 }, - { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, - 0, - Opcode_xsr_rasid_encode_fns, 0, 0 }, - { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, - 0, - Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, - { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, - 0, - Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, - { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, - 0, - Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, - { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, - 0, - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, - { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, - 0, - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, - { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, - 0, - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, - { "idtlb", ICLASS_xt_iclass_idtlb, - 0, - Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", ICLASS_xt_iclass_rdtlb, - 0, - Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", ICLASS_xt_iclass_wdtlb, - 0, - Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", ICLASS_xt_iclass_iitlb, - 0, - Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", ICLASS_xt_iclass_ritlb, - 0, - Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", ICLASS_xt_iclass_ritlb, - 0, - Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", ICLASS_xt_iclass_witlb, - 0, - Opcode_witlb_encode_fns, 0, 0 }, - { "ldpte", ICLASS_xt_iclass_ldpte, - 0, - Opcode_ldpte_encode_fns, 0, 0 }, - { "hwwitlba", ICLASS_xt_iclass_hwwitlba, - XTENSA_OPCODE_IS_BRANCH, - Opcode_hwwitlba_encode_fns, 0, 0 }, - { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, - 0, - Opcode_hwwdtlba_encode_fns, 0, 0 }, - { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, - 0, - Opcode_rsr_cpenable_encode_fns, 0, 0 }, - { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, - 0, - Opcode_wsr_cpenable_encode_fns, 0, 0 }, - { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, - 0, - Opcode_xsr_cpenable_encode_fns, 0, 0 }, - { "clamps", ICLASS_xt_iclass_clamp, - 0, - Opcode_clamps_encode_fns, 0, 0 }, - { "min", ICLASS_xt_iclass_minmax, - 0, - Opcode_min_encode_fns, 0, 0 }, - { "max", ICLASS_xt_iclass_minmax, - 0, - Opcode_max_encode_fns, 0, 0 }, - { "minu", ICLASS_xt_iclass_minmax, - 0, - Opcode_minu_encode_fns, 0, 0 }, - { "maxu", ICLASS_xt_iclass_minmax, - 0, - Opcode_maxu_encode_fns, 0, 0 }, - { "nsa", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", ICLASS_xt_iclass_nsa, - 0, - Opcode_nsau_encode_fns, 0, 0 }, - { "sext", ICLASS_xt_iclass_sx, - 0, - Opcode_sext_encode_fns, 0, 0 }, - { "l32ai", ICLASS_xt_iclass_l32ai, - 0, - Opcode_l32ai_encode_fns, 0, 0 }, - { "s32ri", ICLASS_xt_iclass_s32ri, - 0, - Opcode_s32ri_encode_fns, 0, 0 }, - { "s32c1i", ICLASS_xt_iclass_s32c1i, - 0, - Opcode_s32c1i_encode_fns, 0, 0 }, - { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, - 0, - Opcode_rsr_scompare1_encode_fns, 0, 0 }, - { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, - 0, - Opcode_wsr_scompare1_encode_fns, 0, 0 }, - { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, - 0, - Opcode_xsr_scompare1_encode_fns, 0, 0 }, - { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, - 0, - Opcode_rsr_atomctl_encode_fns, 0, 0 }, - { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, - 0, - Opcode_wsr_atomctl_encode_fns, 0, 0 }, - { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, - 0, - Opcode_xsr_atomctl_encode_fns, 0, 0 }, - { "rer", ICLASS_xt_iclass_rer, - 0, - Opcode_rer_encode_fns, 0, 0 }, - { "wer", ICLASS_xt_iclass_wer, - 0, - Opcode_wer_encode_fns, 0, 0 }, - { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, - 0, - Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, - { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, - 0, - Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, - { "rur.ae_bithead", ICLASS_rur_ae_bithead, - 0, - Opcode_rur_ae_bithead_encode_fns, 0, 0 }, - { "wur.ae_bithead", ICLASS_wur_ae_bithead, - 0, - Opcode_wur_ae_bithead_encode_fns, 0, 0 }, - { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, - 0, - Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, - 0, - Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, - { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, - 0, - Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, - { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, - 0, - Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, - { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, - 0, - Opcode_rur_ae_overflow_encode_fns, 0, 0 }, - { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, - 0, - Opcode_wur_ae_overflow_encode_fns, 0, 0 }, - { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, - 0, - Opcode_rur_ae_sar_encode_fns, 0, 0 }, - { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, - 0, - Opcode_wur_ae_sar_encode_fns, 0, 0 }, - { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, - 0, - Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, - { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, - 0, - Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, - { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, - 0, - Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, - { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, - 0, - Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, - { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, - 0, - Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, - { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, - 0, - Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, - { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, - 0, - Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, - { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, - 0, - Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, - { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, - 0, - Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, - { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, - 0, - Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, - { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, - 0, - Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, - { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, - 0, - Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, - { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, - 0, - Opcode_ae_lp16f_i_encode_fns, 0, 0 }, - { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, - 0, - Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, - { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, - 0, - Opcode_ae_lp16f_x_encode_fns, 0, 0 }, - { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, - 0, - Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, - { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, - 0, - Opcode_ae_lp24_i_encode_fns, 0, 0 }, - { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, - 0, - Opcode_ae_lp24_iu_encode_fns, 0, 0 }, - { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, - 0, - Opcode_ae_lp24_x_encode_fns, 0, 0 }, - { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, - 0, - Opcode_ae_lp24_xu_encode_fns, 0, 0 }, - { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, - 0, - Opcode_ae_lp24f_i_encode_fns, 0, 0 }, - { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, - 0, - Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, - { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, - 0, - Opcode_ae_lp24f_x_encode_fns, 0, 0 }, - { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, - 0, - Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, - { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, - 0, - Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, - { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, - 0, - Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, - { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, - 0, - Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, - { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, - 0, - Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, - 0, - Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, - { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, - 0, - Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, - { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, - 0, - Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, - { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, - 0, - Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, - { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, - 0, - Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, - { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, - 0, - Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, - { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, - 0, - Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, - { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, - 0, - Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, - { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, - 0, - Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, - { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, - 0, - Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, - { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, - 0, - Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, - { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, - 0, - Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, - { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, - 0, - Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, - { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, - 0, - Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, - { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, - 0, - Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, - { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, - 0, - Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, - { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, - 0, - Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, - { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, - 0, - Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, - { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, - 0, - Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, - { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, - 0, - Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, - { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, - 0, - Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, - { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, - 0, - Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, - { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, - 0, - Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, - { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, - 0, - Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, - { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, - 0, - Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, - { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, - 0, - Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, - { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, - 0, - Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, - { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, - 0, - Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, - { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, - 0, - Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, - { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, - 0, - Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, - { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, - 0, - Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, - { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, - 0, - Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, - { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, - 0, - Opcode_ae_lq56_i_encode_fns, 0, 0 }, - { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, - 0, - Opcode_ae_lq56_iu_encode_fns, 0, 0 }, - { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, - 0, - Opcode_ae_lq56_x_encode_fns, 0, 0 }, - { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, - 0, - Opcode_ae_lq56_xu_encode_fns, 0, 0 }, - { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, - 0, - Opcode_ae_lq32f_i_encode_fns, 0, 0 }, - { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, - 0, - Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, - { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, - 0, - Opcode_ae_lq32f_x_encode_fns, 0, 0 }, - { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, - 0, - Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, - { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, - 0, - Opcode_ae_sq56s_i_encode_fns, 0, 0 }, - { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, - 0, - Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, - { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, - 0, - Opcode_ae_sq56s_x_encode_fns, 0, 0 }, - { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, - 0, - Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, - { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, - 0, - Opcode_ae_sq32f_i_encode_fns, 0, 0 }, - { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, - 0, - Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, - { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, - 0, - Opcode_ae_sq32f_x_encode_fns, 0, 0 }, - { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, - 0, - Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, - { "ae_zerop48", ICLASS_ae_iclass_zerop48, - 0, - Opcode_ae_zerop48_encode_fns, 0, 0 }, - { "ae_movp48", ICLASS_ae_iclass_movp48, - 0, - Opcode_ae_movp48_encode_fns, 0, 0 }, - { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll, - 0, - Opcode_ae_selp24_ll_encode_fns, 0, 0 }, - { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh, - 0, - Opcode_ae_selp24_lh_encode_fns, 0, 0 }, - { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl, - 0, - Opcode_ae_selp24_hl_encode_fns, 0, 0 }, - { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh, - 0, - Opcode_ae_selp24_hh_encode_fns, 0, 0 }, - { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2, - 0, - Opcode_ae_movtp24x2_encode_fns, 0, 0 }, - { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2, - 0, - Opcode_ae_movfp24x2_encode_fns, 0, 0 }, - { "ae_movtp48", ICLASS_ae_iclass_movtp48, - 0, - Opcode_ae_movtp48_encode_fns, 0, 0 }, - { "ae_movfp48", ICLASS_ae_iclass_movfp48, - 0, - Opcode_ae_movfp48_encode_fns, 0, 0 }, - { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2, - 0, - Opcode_ae_movpa24x2_encode_fns, 0, 0 }, - { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2, - 0, - Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, - { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l, - 0, - Opcode_ae_cvta32p24_l_encode_fns, 0, 0 }, - { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h, - 0, - Opcode_ae_cvta32p24_h_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll, - 0, - Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh, - 0, - Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl, - 0, - Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, - { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh, - 0, - Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, - { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2, - 0, - Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, - { "ae_truncp16", ICLASS_ae_iclass_truncp16, - 0, - Opcode_ae_truncp16_encode_fns, 0, 0 }, - { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym, - 0, - Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 }, - { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym, - 0, - Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 }, - { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym, - 0, - Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 }, - { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym, - 0, - Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 }, - { "ae_roundsp16sym", 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Opcode_ae_truncq32_encode_fns, 0, 0 }, - { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym, - 0, - Opcode_ae_roundsq32sym_encode_fns, 0, 0 }, - { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym, - 0, - Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, - { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, - 0, - Opcode_ae_trunca32q48_encode_fns, 0, 0 }, - { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, - 0, - Opcode_ae_movap24s_l_encode_fns, 0, 0 }, - { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, - 0, - Opcode_ae_movap24s_h_encode_fns, 0, 0 }, - { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, - 0, - Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, - { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, - 0, - Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, - { "ae_addp24", ICLASS_ae_iclass_addp24, - 0, - Opcode_ae_addp24_encode_fns, 0, 0 }, - { "ae_subp24", ICLASS_ae_iclass_subp24, - 0, - Opcode_ae_subp24_encode_fns, 0, 0 }, - { "ae_negp24", ICLASS_ae_iclass_negp24, - 0, - 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Opcode_ae_nandp48_encode_fns, 0, 0 }, - { "ae_orp48", ICLASS_ae_iclass_orp48, - 0, - Opcode_ae_orp48_encode_fns, 0, 0 }, - { "ae_xorp48", ICLASS_ae_iclass_xorp48, - 0, - Opcode_ae_xorp48_encode_fns, 0, 0 }, - { "ae_ltp24s", ICLASS_ae_iclass_ltp24s, - 0, - Opcode_ae_ltp24s_encode_fns, 0, 0 }, - { "ae_lep24s", ICLASS_ae_iclass_lep24s, - 0, - Opcode_ae_lep24s_encode_fns, 0, 0 }, - { "ae_eqp24", ICLASS_ae_iclass_eqp24, - 0, - Opcode_ae_eqp24_encode_fns, 0, 0 }, - { "ae_addq56", ICLASS_ae_iclass_addq56, - 0, - Opcode_ae_addq56_encode_fns, 0, 0 }, - { "ae_subq56", ICLASS_ae_iclass_subq56, - 0, - Opcode_ae_subq56_encode_fns, 0, 0 }, - { "ae_negq56", ICLASS_ae_iclass_negq56, - 0, - Opcode_ae_negq56_encode_fns, 0, 0 }, - { "ae_absq56", ICLASS_ae_iclass_absq56, - 0, - Opcode_ae_absq56_encode_fns, 0, 0 }, - { "ae_maxq56s", ICLASS_ae_iclass_maxq56s, - 0, - Opcode_ae_maxq56s_encode_fns, 0, 0 }, - { "ae_minq56s", ICLASS_ae_iclass_minq56s, - 0, - Opcode_ae_minq56s_encode_fns, 0, 0 }, - { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s, - 0, - Opcode_ae_maxbq56s_encode_fns, 0, 0 }, - { "ae_minbq56s", ICLASS_ae_iclass_minbq56s, - 0, - Opcode_ae_minbq56s_encode_fns, 0, 0 }, - { "ae_addsq56s", ICLASS_ae_iclass_addsq56s, - 0, - Opcode_ae_addsq56s_encode_fns, 0, 0 }, - { "ae_subsq56s", ICLASS_ae_iclass_subsq56s, - 0, - Opcode_ae_subsq56s_encode_fns, 0, 0 }, - { "ae_negsq56s", ICLASS_ae_iclass_negsq56s, - 0, - Opcode_ae_negsq56s_encode_fns, 0, 0 }, - { "ae_abssq56s", ICLASS_ae_iclass_abssq56s, - 0, - Opcode_ae_abssq56s_encode_fns, 0, 0 }, - { "ae_andq56", ICLASS_ae_iclass_andq56, - 0, - Opcode_ae_andq56_encode_fns, 0, 0 }, - { "ae_nandq56", ICLASS_ae_iclass_nandq56, - 0, - Opcode_ae_nandq56_encode_fns, 0, 0 }, - { "ae_orq56", ICLASS_ae_iclass_orq56, - 0, - Opcode_ae_orq56_encode_fns, 0, 0 }, - { "ae_xorq56", ICLASS_ae_iclass_xorq56, - 0, - Opcode_ae_xorq56_encode_fns, 0, 0 }, - { "ae_sllip24", ICLASS_ae_iclass_sllip24, - 0, - Opcode_ae_sllip24_encode_fns, 0, 0 }, - { "ae_srlip24", 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ICLASS_ae_iclass_nsaq56s, - 0, - Opcode_ae_nsaq56s_encode_fns, 0, 0 }, - { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll, - 0, - Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 }, - { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll, - 0, - Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 }, - { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll, - 0, - Opcode_ae_mulp24s_ll_encode_fns, 0, 0 }, - { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh, - 0, - Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 }, - { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh, - 0, - Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 }, - { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh, - 0, - Opcode_ae_mulp24s_lh_encode_fns, 0, 0 }, - { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl, - 0, - Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 }, - { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl, - 0, - Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 }, - { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl, - 0, - Opcode_ae_mulp24s_hl_encode_fns, 0, 0 }, - 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"ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, - 0, - Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, - 0, - Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, - 0, - Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, - 0, - Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, - 0, - Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, - 0, - Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, - 0, - Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, - 0, - Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, - 0, - Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, - 0, - Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, - 0, - Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, - 0, - Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, - 0, - Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, - 0, - Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, - 0, - Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, - 0, - Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, - 0, - Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, - 0, - Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, - 0, - Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, - 0, - Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, - 0, - Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, - 0, - Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, - 0, - Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, - 0, - Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, - { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, - 0, - Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, - 0, - Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, - { "ae_sha32", ICLASS_ae_iclass_sha32, - 0, - Opcode_ae_sha32_encode_fns, 0, 0 }, - { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, - 0, - Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, - { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, - 0, - Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, - { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, - 0, - Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, - { "ae_vldsht", ICLASS_ae_iclass_vldsht, - 0, - Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, - { "ae_lb", ICLASS_ae_iclass_lb, - 0, - Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, - { "ae_lbi", ICLASS_ae_iclass_lbi, - 0, - Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, - { "ae_lbk", ICLASS_ae_iclass_lbk, - 0, - Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, - { "ae_lbki", ICLASS_ae_iclass_lbki, - 0, - Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, - { "ae_db", ICLASS_ae_iclass_db, - 0, - Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, - { "ae_dbi", ICLASS_ae_iclass_dbi, - 0, - Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, - { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, - 0, - Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, - { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, - 0, - Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, - { "ae_sb", ICLASS_ae_iclass_sb, - 0, - Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, - { "ae_sbi", ICLASS_ae_iclass_sbi, - 0, - Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, - { "ae_vles16c", ICLASS_ae_iclass_vles16c, - 0, - Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, - { "ae_sbf", ICLASS_ae_iclass_sbf, - 0, - Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses } -}; - -enum xtensa_opcode_id { - OPCODE_EXCW, - OPCODE_RFE, - OPCODE_RFDE, - OPCODE_SYSCALL, - OPCODE_CALL12, - OPCODE_CALL8, - OPCODE_CALL4, - OPCODE_CALLX12, - OPCODE_CALLX8, - OPCODE_CALLX4, - OPCODE_ENTRY, - OPCODE_MOVSP, - OPCODE_ROTW, - OPCODE_RETW, - OPCODE_RETW_N, - OPCODE_RFWO, - OPCODE_RFWU, - OPCODE_L32E, - OPCODE_S32E, - OPCODE_RSR_WINDOWBASE, - OPCODE_WSR_WINDOWBASE, - OPCODE_XSR_WINDOWBASE, - OPCODE_RSR_WINDOWSTART, - OPCODE_WSR_WINDOWSTART, - OPCODE_XSR_WINDOWSTART, - OPCODE_ADD_N, - OPCODE_ADDI_N, - OPCODE_BEQZ_N, - OPCODE_BNEZ_N, - OPCODE_ILL_N, - OPCODE_L32I_N, - OPCODE_MOV_N, - OPCODE_MOVI_N, - OPCODE_NOP_N, - OPCODE_RET_N, - OPCODE_S32I_N, - OPCODE_RUR_THREADPTR, - OPCODE_WUR_THREADPTR, - OPCODE_ADDI, - OPCODE_ADDMI, - OPCODE_ADD, - OPCODE_SUB, - OPCODE_ADDX2, - OPCODE_ADDX4, - OPCODE_ADDX8, - OPCODE_SUBX2, - OPCODE_SUBX4, - OPCODE_SUBX8, - OPCODE_AND, - OPCODE_OR, - OPCODE_XOR, - OPCODE_BEQI, - OPCODE_BNEI, - OPCODE_BGEI, - OPCODE_BLTI, - OPCODE_BBCI, - OPCODE_BBSI, - OPCODE_BGEUI, - OPCODE_BLTUI, - OPCODE_BEQ, - OPCODE_BNE, - OPCODE_BGE, - OPCODE_BLT, - OPCODE_BGEU, - OPCODE_BLTU, - OPCODE_BANY, - OPCODE_BNONE, - OPCODE_BALL, - OPCODE_BNALL, - OPCODE_BBC, - OPCODE_BBS, - OPCODE_BEQZ, - OPCODE_BNEZ, - OPCODE_BGEZ, - OPCODE_BLTZ, - OPCODE_CALL0, - OPCODE_CALLX0, - OPCODE_EXTUI, - OPCODE_ILL, - OPCODE_J, - OPCODE_JX, - OPCODE_L16UI, - OPCODE_L16SI, - OPCODE_L32I, - OPCODE_L32R, - OPCODE_L8UI, - OPCODE_LOOP, - OPCODE_LOOPNEZ, - OPCODE_LOOPGTZ, - OPCODE_MOVI, - OPCODE_MOVEQZ, - OPCODE_MOVNEZ, - OPCODE_MOVLTZ, - OPCODE_MOVGEZ, - OPCODE_NEG, - OPCODE_ABS, - OPCODE_NOP, - OPCODE_RET, - OPCODE_SIMCALL, - OPCODE_S16I, - OPCODE_S32I, - OPCODE_S8I, - OPCODE_SSR, - OPCODE_SSL, - OPCODE_SSA8L, - OPCODE_SSA8B, - OPCODE_SSAI, - OPCODE_SLL, - OPCODE_SRC, - OPCODE_SRL, - OPCODE_SRA, - OPCODE_SLLI, - OPCODE_SRAI, - OPCODE_SRLI, - OPCODE_MEMW, - OPCODE_EXTW, - OPCODE_ISYNC, - OPCODE_RSYNC, - OPCODE_ESYNC, - OPCODE_DSYNC, - OPCODE_RSIL, - OPCODE_RSR_LEND, - OPCODE_WSR_LEND, - OPCODE_XSR_LEND, - OPCODE_RSR_LCOUNT, - OPCODE_WSR_LCOUNT, - OPCODE_XSR_LCOUNT, - OPCODE_RSR_LBEG, - OPCODE_WSR_LBEG, - OPCODE_XSR_LBEG, - OPCODE_RSR_SAR, - OPCODE_WSR_SAR, - OPCODE_XSR_SAR, - OPCODE_RSR_LITBASE, - OPCODE_WSR_LITBASE, - OPCODE_XSR_LITBASE, - OPCODE_RSR_CONFIGID0, - OPCODE_WSR_CONFIGID0, - OPCODE_RSR_CONFIGID1, - OPCODE_RSR_PS, - OPCODE_WSR_PS, - OPCODE_XSR_PS, - OPCODE_RSR_EPC1, - OPCODE_WSR_EPC1, - OPCODE_XSR_EPC1, - OPCODE_RSR_EXCSAVE1, - OPCODE_WSR_EXCSAVE1, - OPCODE_XSR_EXCSAVE1, - OPCODE_RSR_EPC2, - OPCODE_WSR_EPC2, - OPCODE_XSR_EPC2, - OPCODE_RSR_EXCSAVE2, - OPCODE_WSR_EXCSAVE2, - OPCODE_XSR_EXCSAVE2, - OPCODE_RSR_EPS2, - OPCODE_WSR_EPS2, - OPCODE_XSR_EPS2, - OPCODE_RSR_EXCVADDR, - OPCODE_WSR_EXCVADDR, - OPCODE_XSR_EXCVADDR, - OPCODE_RSR_DEPC, - OPCODE_WSR_DEPC, - OPCODE_XSR_DEPC, - OPCODE_RSR_EXCCAUSE, - OPCODE_WSR_EXCCAUSE, - OPCODE_XSR_EXCCAUSE, - OPCODE_RSR_MISC0, - OPCODE_WSR_MISC0, - OPCODE_XSR_MISC0, - OPCODE_RSR_MISC1, - OPCODE_WSR_MISC1, - OPCODE_XSR_MISC1, - OPCODE_RSR_PRID, - OPCODE_RSR_VECBASE, - OPCODE_WSR_VECBASE, - OPCODE_XSR_VECBASE, - OPCODE_MUL16U, - OPCODE_MUL16S, - OPCODE_MULL, - OPCODE_RFI, - OPCODE_WAITI, - OPCODE_RSR_INTERRUPT, - OPCODE_WSR_INTSET, - OPCODE_WSR_INTCLEAR, - OPCODE_RSR_INTENABLE, - OPCODE_WSR_INTENABLE, - OPCODE_XSR_INTENABLE, - OPCODE_BREAK, - OPCODE_BREAK_N, - OPCODE_RSR_DEBUGCAUSE, - OPCODE_WSR_DEBUGCAUSE, - OPCODE_XSR_DEBUGCAUSE, - OPCODE_RSR_ICOUNT, - OPCODE_WSR_ICOUNT, - OPCODE_XSR_ICOUNT, - OPCODE_RSR_ICOUNTLEVEL, - OPCODE_WSR_ICOUNTLEVEL, - OPCODE_XSR_ICOUNTLEVEL, - OPCODE_RSR_DDR, - OPCODE_WSR_DDR, - OPCODE_XSR_DDR, - OPCODE_RFDO, - OPCODE_RFDD, - OPCODE_ANDB, - OPCODE_ANDBC, - OPCODE_ORB, - OPCODE_ORBC, - OPCODE_XORB, - OPCODE_ANY4, - OPCODE_ALL4, - OPCODE_ANY8, - OPCODE_ALL8, - OPCODE_BF, - OPCODE_BT, - OPCODE_MOVF, - OPCODE_MOVT, - OPCODE_RSR_BR, - OPCODE_WSR_BR, - OPCODE_XSR_BR, - OPCODE_RSR_CCOUNT, - OPCODE_WSR_CCOUNT, - OPCODE_XSR_CCOUNT, - OPCODE_RSR_CCOMPARE0, - OPCODE_WSR_CCOMPARE0, - OPCODE_XSR_CCOMPARE0, - OPCODE_RSR_CCOMPARE1, - OPCODE_WSR_CCOMPARE1, - OPCODE_XSR_CCOMPARE1, - OPCODE_IPF, - OPCODE_IHI, - OPCODE_III, - OPCODE_LICT, - OPCODE_LICW, - OPCODE_SICT, - OPCODE_SICW, - OPCODE_DHWB, - OPCODE_DHWBI, - OPCODE_DIWB, - OPCODE_DIWBI, - OPCODE_DHI, - OPCODE_DII, - OPCODE_DPFR, - OPCODE_DPFW, - OPCODE_DPFRO, - OPCODE_DPFWO, - OPCODE_SDCT, - OPCODE_LDCT, - OPCODE_WSR_PTEVADDR, - OPCODE_RSR_PTEVADDR, - OPCODE_XSR_PTEVADDR, - OPCODE_RSR_RASID, - OPCODE_WSR_RASID, - OPCODE_XSR_RASID, - OPCODE_RSR_ITLBCFG, - OPCODE_WSR_ITLBCFG, - OPCODE_XSR_ITLBCFG, - OPCODE_RSR_DTLBCFG, - OPCODE_WSR_DTLBCFG, - OPCODE_XSR_DTLBCFG, - OPCODE_IDTLB, - OPCODE_PDTLB, - OPCODE_RDTLB0, - OPCODE_RDTLB1, - OPCODE_WDTLB, - OPCODE_IITLB, - OPCODE_PITLB, - OPCODE_RITLB0, - OPCODE_RITLB1, - OPCODE_WITLB, - OPCODE_LDPTE, - OPCODE_HWWITLBA, - OPCODE_HWWDTLBA, - OPCODE_RSR_CPENABLE, - OPCODE_WSR_CPENABLE, - OPCODE_XSR_CPENABLE, - OPCODE_CLAMPS, - OPCODE_MIN, - OPCODE_MAX, - OPCODE_MINU, - OPCODE_MAXU, - OPCODE_NSA, - OPCODE_NSAU, - OPCODE_SEXT, - OPCODE_L32AI, - OPCODE_S32RI, - OPCODE_S32C1I, - OPCODE_RSR_SCOMPARE1, - OPCODE_WSR_SCOMPARE1, - OPCODE_XSR_SCOMPARE1, - OPCODE_RSR_ATOMCTL, - OPCODE_WSR_ATOMCTL, - OPCODE_XSR_ATOMCTL, - OPCODE_RER, - OPCODE_WER, - OPCODE_RUR_AE_OVF_SAR, - OPCODE_WUR_AE_OVF_SAR, - OPCODE_RUR_AE_BITHEAD, - OPCODE_WUR_AE_BITHEAD, - OPCODE_RUR_AE_TS_FTS_BU_BP, - OPCODE_WUR_AE_TS_FTS_BU_BP, - OPCODE_RUR_AE_SD_NO, - OPCODE_WUR_AE_SD_NO, - OPCODE_RUR_AE_OVERFLOW, - OPCODE_WUR_AE_OVERFLOW, - OPCODE_RUR_AE_SAR, - OPCODE_WUR_AE_SAR, - OPCODE_RUR_AE_BITPTR, - OPCODE_WUR_AE_BITPTR, - OPCODE_RUR_AE_BITSUSED, - OPCODE_WUR_AE_BITSUSED, - OPCODE_RUR_AE_TABLESIZE, - OPCODE_WUR_AE_TABLESIZE, - OPCODE_RUR_AE_FIRST_TS, - OPCODE_WUR_AE_FIRST_TS, - OPCODE_RUR_AE_NEXTOFFSET, - OPCODE_WUR_AE_NEXTOFFSET, - OPCODE_RUR_AE_SEARCHDONE, - OPCODE_WUR_AE_SEARCHDONE, - OPCODE_AE_LP16F_I, - OPCODE_AE_LP16F_IU, - OPCODE_AE_LP16F_X, - OPCODE_AE_LP16F_XU, - OPCODE_AE_LP24_I, - OPCODE_AE_LP24_IU, - OPCODE_AE_LP24_X, - OPCODE_AE_LP24_XU, - OPCODE_AE_LP24F_I, - OPCODE_AE_LP24F_IU, - OPCODE_AE_LP24F_X, - OPCODE_AE_LP24F_XU, - OPCODE_AE_LP16X2F_I, - OPCODE_AE_LP16X2F_IU, - OPCODE_AE_LP16X2F_X, - OPCODE_AE_LP16X2F_XU, - OPCODE_AE_LP24X2F_I, - OPCODE_AE_LP24X2F_IU, - OPCODE_AE_LP24X2F_X, - OPCODE_AE_LP24X2F_XU, - OPCODE_AE_LP24X2_I, - OPCODE_AE_LP24X2_IU, - OPCODE_AE_LP24X2_X, - OPCODE_AE_LP24X2_XU, - OPCODE_AE_SP16X2F_I, - OPCODE_AE_SP16X2F_IU, - OPCODE_AE_SP16X2F_X, - OPCODE_AE_SP16X2F_XU, - OPCODE_AE_SP24X2S_I, - OPCODE_AE_SP24X2S_IU, - OPCODE_AE_SP24X2S_X, - OPCODE_AE_SP24X2S_XU, - OPCODE_AE_SP24X2F_I, - OPCODE_AE_SP24X2F_IU, - OPCODE_AE_SP24X2F_X, - OPCODE_AE_SP24X2F_XU, - OPCODE_AE_SP16F_L_I, - OPCODE_AE_SP16F_L_IU, - OPCODE_AE_SP16F_L_X, - OPCODE_AE_SP16F_L_XU, - OPCODE_AE_SP24S_L_I, - OPCODE_AE_SP24S_L_IU, - OPCODE_AE_SP24S_L_X, - OPCODE_AE_SP24S_L_XU, - OPCODE_AE_SP24F_L_I, - OPCODE_AE_SP24F_L_IU, - OPCODE_AE_SP24F_L_X, - OPCODE_AE_SP24F_L_XU, - OPCODE_AE_LQ56_I, - OPCODE_AE_LQ56_IU, - OPCODE_AE_LQ56_X, - OPCODE_AE_LQ56_XU, - OPCODE_AE_LQ32F_I, - OPCODE_AE_LQ32F_IU, - OPCODE_AE_LQ32F_X, - OPCODE_AE_LQ32F_XU, - OPCODE_AE_SQ56S_I, - OPCODE_AE_SQ56S_IU, - OPCODE_AE_SQ56S_X, - OPCODE_AE_SQ56S_XU, - OPCODE_AE_SQ32F_I, - OPCODE_AE_SQ32F_IU, - OPCODE_AE_SQ32F_X, - OPCODE_AE_SQ32F_XU, - OPCODE_AE_ZEROP48, - OPCODE_AE_MOVP48, - OPCODE_AE_SELP24_LL, - OPCODE_AE_SELP24_LH, - OPCODE_AE_SELP24_HL, - OPCODE_AE_SELP24_HH, - OPCODE_AE_MOVTP24X2, - OPCODE_AE_MOVFP24X2, - OPCODE_AE_MOVTP48, - OPCODE_AE_MOVFP48, - OPCODE_AE_MOVPA24X2, - OPCODE_AE_TRUNCP24A32X2, - OPCODE_AE_CVTA32P24_L, - OPCODE_AE_CVTA32P24_H, - OPCODE_AE_CVTP24A16X2_LL, - OPCODE_AE_CVTP24A16X2_LH, - OPCODE_AE_CVTP24A16X2_HL, - OPCODE_AE_CVTP24A16X2_HH, - OPCODE_AE_TRUNCP24Q48X2, - OPCODE_AE_TRUNCP16, - OPCODE_AE_ROUNDSP24Q48SYM, - OPCODE_AE_ROUNDSP24Q48ASYM, - OPCODE_AE_ROUNDSP16Q48SYM, - OPCODE_AE_ROUNDSP16Q48ASYM, - OPCODE_AE_ROUNDSP16SYM, - OPCODE_AE_ROUNDSP16ASYM, - OPCODE_AE_ZEROQ56, - OPCODE_AE_MOVQ56, - OPCODE_AE_MOVTQ56, - OPCODE_AE_MOVFQ56, - OPCODE_AE_CVTQ48A32S, - OPCODE_AE_CVTQ48P24S_L, - OPCODE_AE_CVTQ48P24S_H, - OPCODE_AE_SATQ48S, - OPCODE_AE_TRUNCQ32, - OPCODE_AE_ROUNDSQ32SYM, - OPCODE_AE_ROUNDSQ32ASYM, - OPCODE_AE_TRUNCA32Q48, - OPCODE_AE_MOVAP24S_L, - OPCODE_AE_MOVAP24S_H, - OPCODE_AE_TRUNCA16P24S_L, - OPCODE_AE_TRUNCA16P24S_H, - OPCODE_AE_ADDP24, - OPCODE_AE_SUBP24, - OPCODE_AE_NEGP24, - OPCODE_AE_ABSP24, - OPCODE_AE_MAXP24S, - OPCODE_AE_MINP24S, - OPCODE_AE_MAXBP24S, - OPCODE_AE_MINBP24S, - OPCODE_AE_ADDSP24S, - OPCODE_AE_SUBSP24S, - OPCODE_AE_NEGSP24S, - OPCODE_AE_ABSSP24S, - OPCODE_AE_ANDP48, - OPCODE_AE_NANDP48, - OPCODE_AE_ORP48, - OPCODE_AE_XORP48, - OPCODE_AE_LTP24S, - OPCODE_AE_LEP24S, - OPCODE_AE_EQP24, - OPCODE_AE_ADDQ56, - OPCODE_AE_SUBQ56, - OPCODE_AE_NEGQ56, - OPCODE_AE_ABSQ56, - OPCODE_AE_MAXQ56S, - OPCODE_AE_MINQ56S, - OPCODE_AE_MAXBQ56S, - OPCODE_AE_MINBQ56S, - OPCODE_AE_ADDSQ56S, - OPCODE_AE_SUBSQ56S, - OPCODE_AE_NEGSQ56S, - OPCODE_AE_ABSSQ56S, - OPCODE_AE_ANDQ56, - OPCODE_AE_NANDQ56, - OPCODE_AE_ORQ56, - OPCODE_AE_XORQ56, - OPCODE_AE_SLLIP24, - OPCODE_AE_SRLIP24, - OPCODE_AE_SRAIP24, - OPCODE_AE_SLLSP24, - OPCODE_AE_SRLSP24, - OPCODE_AE_SRASP24, - OPCODE_AE_SLLISP24S, - OPCODE_AE_SLLSSP24S, - OPCODE_AE_SLLIQ56, - OPCODE_AE_SRLIQ56, - OPCODE_AE_SRAIQ56, - OPCODE_AE_SLLSQ56, - OPCODE_AE_SRLSQ56, - OPCODE_AE_SRASQ56, - OPCODE_AE_SLLAQ56, - OPCODE_AE_SRLAQ56, - OPCODE_AE_SRAAQ56, - OPCODE_AE_SLLISQ56S, - OPCODE_AE_SLLSSQ56S, - OPCODE_AE_SLLASQ56S, - OPCODE_AE_LTQ56S, - OPCODE_AE_LEQ56S, - OPCODE_AE_EQQ56, - OPCODE_AE_NSAQ56S, - OPCODE_AE_MULFS32P16S_LL, - OPCODE_AE_MULFP24S_LL, - OPCODE_AE_MULP24S_LL, - OPCODE_AE_MULFS32P16S_LH, - OPCODE_AE_MULFP24S_LH, - OPCODE_AE_MULP24S_LH, - OPCODE_AE_MULFS32P16S_HL, - OPCODE_AE_MULFP24S_HL, - OPCODE_AE_MULP24S_HL, - OPCODE_AE_MULFS32P16S_HH, - OPCODE_AE_MULFP24S_HH, - OPCODE_AE_MULP24S_HH, - OPCODE_AE_MULAFS32P16S_LL, - OPCODE_AE_MULAFP24S_LL, - OPCODE_AE_MULAP24S_LL, - OPCODE_AE_MULAFS32P16S_LH, - OPCODE_AE_MULAFP24S_LH, - OPCODE_AE_MULAP24S_LH, - OPCODE_AE_MULAFS32P16S_HL, - OPCODE_AE_MULAFP24S_HL, - OPCODE_AE_MULAP24S_HL, - OPCODE_AE_MULAFS32P16S_HH, - OPCODE_AE_MULAFP24S_HH, - OPCODE_AE_MULAP24S_HH, - OPCODE_AE_MULSFS32P16S_LL, - OPCODE_AE_MULSFP24S_LL, - OPCODE_AE_MULSP24S_LL, - OPCODE_AE_MULSFS32P16S_LH, - OPCODE_AE_MULSFP24S_LH, - OPCODE_AE_MULSP24S_LH, - OPCODE_AE_MULSFS32P16S_HL, - OPCODE_AE_MULSFP24S_HL, - OPCODE_AE_MULSP24S_HL, - OPCODE_AE_MULSFS32P16S_HH, - OPCODE_AE_MULSFP24S_HH, - OPCODE_AE_MULSP24S_HH, - OPCODE_AE_MULAFS56P24S_LL, - OPCODE_AE_MULAS56P24S_LL, - OPCODE_AE_MULAFS56P24S_LH, - OPCODE_AE_MULAS56P24S_LH, - OPCODE_AE_MULAFS56P24S_HL, - OPCODE_AE_MULAS56P24S_HL, - OPCODE_AE_MULAFS56P24S_HH, - OPCODE_AE_MULAS56P24S_HH, - OPCODE_AE_MULSFS56P24S_LL, - OPCODE_AE_MULSS56P24S_LL, - OPCODE_AE_MULSFS56P24S_LH, - OPCODE_AE_MULSS56P24S_LH, - OPCODE_AE_MULSFS56P24S_HL, - OPCODE_AE_MULSS56P24S_HL, - OPCODE_AE_MULSFS56P24S_HH, - OPCODE_AE_MULSS56P24S_HH, - OPCODE_AE_MULFQ32SP16S_L, - OPCODE_AE_MULFQ32SP16S_H, - OPCODE_AE_MULFQ32SP16U_L, - OPCODE_AE_MULFQ32SP16U_H, - OPCODE_AE_MULQ32SP16S_L, - OPCODE_AE_MULQ32SP16S_H, - OPCODE_AE_MULQ32SP16U_L, - OPCODE_AE_MULQ32SP16U_H, - OPCODE_AE_MULAFQ32SP16S_L, - OPCODE_AE_MULAFQ32SP16S_H, - OPCODE_AE_MULAFQ32SP16U_L, - OPCODE_AE_MULAFQ32SP16U_H, - OPCODE_AE_MULAQ32SP16S_L, - OPCODE_AE_MULAQ32SP16S_H, - OPCODE_AE_MULAQ32SP16U_L, - OPCODE_AE_MULAQ32SP16U_H, - OPCODE_AE_MULSFQ32SP16S_L, - OPCODE_AE_MULSFQ32SP16S_H, - OPCODE_AE_MULSFQ32SP16U_L, - OPCODE_AE_MULSFQ32SP16U_H, - OPCODE_AE_MULSQ32SP16S_L, - OPCODE_AE_MULSQ32SP16S_H, - OPCODE_AE_MULSQ32SP16U_L, - OPCODE_AE_MULSQ32SP16U_H, - OPCODE_AE_MULZAAQ32SP16S_LL, - OPCODE_AE_MULZAAFQ32SP16S_LL, - OPCODE_AE_MULZAAQ32SP16U_LL, - OPCODE_AE_MULZAAFQ32SP16U_LL, - OPCODE_AE_MULZAAQ32SP16S_HH, - OPCODE_AE_MULZAAFQ32SP16S_HH, - OPCODE_AE_MULZAAQ32SP16U_HH, - OPCODE_AE_MULZAAFQ32SP16U_HH, - OPCODE_AE_MULZAAQ32SP16S_LH, - OPCODE_AE_MULZAAFQ32SP16S_LH, - OPCODE_AE_MULZAAQ32SP16U_LH, - OPCODE_AE_MULZAAFQ32SP16U_LH, - OPCODE_AE_MULZASQ32SP16S_LL, - OPCODE_AE_MULZASFQ32SP16S_LL, - OPCODE_AE_MULZASQ32SP16U_LL, - OPCODE_AE_MULZASFQ32SP16U_LL, - OPCODE_AE_MULZASQ32SP16S_HH, - OPCODE_AE_MULZASFQ32SP16S_HH, - OPCODE_AE_MULZASQ32SP16U_HH, - OPCODE_AE_MULZASFQ32SP16U_HH, - OPCODE_AE_MULZASQ32SP16S_LH, - OPCODE_AE_MULZASFQ32SP16S_LH, - OPCODE_AE_MULZASQ32SP16U_LH, - OPCODE_AE_MULZASFQ32SP16U_LH, - OPCODE_AE_MULZSAQ32SP16S_LL, - OPCODE_AE_MULZSAFQ32SP16S_LL, - OPCODE_AE_MULZSAQ32SP16U_LL, - OPCODE_AE_MULZSAFQ32SP16U_LL, - OPCODE_AE_MULZSAQ32SP16S_HH, - OPCODE_AE_MULZSAFQ32SP16S_HH, - OPCODE_AE_MULZSAQ32SP16U_HH, - OPCODE_AE_MULZSAFQ32SP16U_HH, - OPCODE_AE_MULZSAQ32SP16S_LH, - OPCODE_AE_MULZSAFQ32SP16S_LH, - OPCODE_AE_MULZSAQ32SP16U_LH, - OPCODE_AE_MULZSAFQ32SP16U_LH, - OPCODE_AE_MULZSSQ32SP16S_LL, - OPCODE_AE_MULZSSFQ32SP16S_LL, - OPCODE_AE_MULZSSQ32SP16U_LL, - OPCODE_AE_MULZSSFQ32SP16U_LL, - OPCODE_AE_MULZSSQ32SP16S_HH, - OPCODE_AE_MULZSSFQ32SP16S_HH, - OPCODE_AE_MULZSSQ32SP16U_HH, - OPCODE_AE_MULZSSFQ32SP16U_HH, - OPCODE_AE_MULZSSQ32SP16S_LH, - OPCODE_AE_MULZSSFQ32SP16S_LH, - OPCODE_AE_MULZSSQ32SP16U_LH, - OPCODE_AE_MULZSSFQ32SP16U_LH, - OPCODE_AE_MULZAAFP24S_HH_LL, - OPCODE_AE_MULZAAP24S_HH_LL, - OPCODE_AE_MULZAAFP24S_HL_LH, - OPCODE_AE_MULZAAP24S_HL_LH, - OPCODE_AE_MULZASFP24S_HH_LL, - OPCODE_AE_MULZASP24S_HH_LL, - OPCODE_AE_MULZASFP24S_HL_LH, - OPCODE_AE_MULZASP24S_HL_LH, - OPCODE_AE_MULZSAFP24S_HH_LL, - OPCODE_AE_MULZSAP24S_HH_LL, - OPCODE_AE_MULZSAFP24S_HL_LH, - OPCODE_AE_MULZSAP24S_HL_LH, - OPCODE_AE_MULZSSFP24S_HH_LL, - OPCODE_AE_MULZSSP24S_HH_LL, - OPCODE_AE_MULZSSFP24S_HL_LH, - OPCODE_AE_MULZSSP24S_HL_LH, - OPCODE_AE_MULAAFP24S_HH_LL, - OPCODE_AE_MULAAP24S_HH_LL, - OPCODE_AE_MULAAFP24S_HL_LH, - OPCODE_AE_MULAAP24S_HL_LH, - OPCODE_AE_MULASFP24S_HH_LL, - OPCODE_AE_MULASP24S_HH_LL, - OPCODE_AE_MULASFP24S_HL_LH, - OPCODE_AE_MULASP24S_HL_LH, - OPCODE_AE_MULSAFP24S_HH_LL, - OPCODE_AE_MULSAP24S_HH_LL, - OPCODE_AE_MULSAFP24S_HL_LH, - OPCODE_AE_MULSAP24S_HL_LH, - OPCODE_AE_MULSSFP24S_HH_LL, - OPCODE_AE_MULSSP24S_HH_LL, - OPCODE_AE_MULSSFP24S_HL_LH, - OPCODE_AE_MULSSP24S_HL_LH, - OPCODE_AE_SHA32, - OPCODE_AE_VLDL32T, - OPCODE_AE_VLDL16T, - OPCODE_AE_VLDL16C, - OPCODE_AE_VLDSHT, - OPCODE_AE_LB, - OPCODE_AE_LBI, - OPCODE_AE_LBK, - OPCODE_AE_LBKI, - OPCODE_AE_DB, - OPCODE_AE_DBI, - OPCODE_AE_VLEL32T, - OPCODE_AE_VLEL16T, - OPCODE_AE_SB, - OPCODE_AE_SBI, - OPCODE_AE_VLES16C, - OPCODE_AE_SBF -}; - - -/* Slot-specific opcode decode functions. */ - -static int -Slot_inst_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst_get (insn) == 0) - { - if (Field_op1_Slot_inst_get (insn) == 0) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_r_Slot_inst_get (insn) == 0) - { - if (Field_m_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - if (Field_m_Slot_inst_get (insn) == 2) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_RET; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_RETW; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_JX; - } - if (Field_m_Slot_inst_get (insn) == 3) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALLX0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALLX4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALLX8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALLX12; - } - } - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_MOVSP; - if (Field_r_Slot_inst_get (insn) == 2) - { - if (Field_s_Slot_inst_get (insn) == 0) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_ISYNC; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RSYNC; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_ESYNC; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DSYNC; - if (Field_t_Slot_inst_get (insn) == 8) - return OPCODE_EXCW; - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_MEMW; - if (Field_t_Slot_inst_get (insn) == 13) - return OPCODE_EXTW; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_NOP; - } - } - if (Field_r_Slot_inst_get (insn) == 3) - { - if (Field_t_Slot_inst_get (insn) == 0) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_RFE; - if (Field_s_Slot_inst_get (insn) == 2) - return OPCODE_RFDE; - if (Field_s_Slot_inst_get (insn) == 4) - return OPCODE_RFWO; - if (Field_s_Slot_inst_get (insn) == 5) - return OPCODE_RFWU; - } - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFI; - } - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BREAK; - if (Field_r_Slot_inst_get (insn) == 5) - { - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - } - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RSIL; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_ANY4; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_ALL4; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_ANY8; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_ALL8; - } - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_AND; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_OR; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_XOR; - if (Field_op2_Slot_inst_get (insn) == 4) - { - if (Field_r_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_RER; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_WER; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_NSA; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_NSAU; - } - if (Field_op2_Slot_inst_get (insn) == 5) - { - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_HWWITLBA; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_RITLB0; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_PITLB; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_WITLB; - if (Field_r_Slot_inst_get (insn) == 7) - return OPCODE_RITLB1; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_HWWDTLBA; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_RDTLB0; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_PDTLB; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_WDTLB; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_RDTLB1; - } - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_NEG; - if (Field_s_Slot_inst_get (insn) == 1) - return OPCODE_ABS; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_ADD; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_ADDX2; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_ADDX4; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_ADDX8; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_SUB; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_SUBX2; - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_SUBX4; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_SUBX8; - } - if (Field_op1_Slot_inst_get (insn) == 1) - { - if ((Field_op2_Slot_inst_get (insn) == 0 || - Field_op2_Slot_inst_get (insn) == 1)) - return OPCODE_SLLI; - if ((Field_op2_Slot_inst_get (insn) == 2 || - Field_op2_Slot_inst_get (insn) == 3)) - return OPCODE_SRAI; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_SRLI; - if (Field_op2_Slot_inst_get (insn) == 6) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_XSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_XSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_XSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_XSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_XSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_XSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_XSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_XSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_XSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_XSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_XSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_XSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_XSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_XSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_XSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_XSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_XSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_XSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_XSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_XSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_XSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_XSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_XSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_XSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_XSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_XSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_XSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_XSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_XSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_XSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_XSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_XSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_XSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_XSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_XSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_SRC; - if (Field_op2_Slot_inst_get (insn) == 9 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - if (Field_op2_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - if (Field_op2_Slot_inst_get (insn) == 11 && - Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MUL16U; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MUL16S; - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_LICT; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_SICT; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_LICW; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_SICW; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LDCT; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_SDCT; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_LDPTE; - } - } - if (Field_op1_Slot_inst_get (insn) == 2) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_ANDB; - if (Field_op2_Slot_inst_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_ORB; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_ORBC; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_XORB; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MULL; - } - if (Field_op1_Slot_inst_get (insn) == 3) - { - if (Field_op2_Slot_inst_get (insn) == 0) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_RSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_RSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_RSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_RSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_RSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_RSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_RSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_RSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_RSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_RSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_RSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_RSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_RSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_RSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_RSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_RSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_RSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_RSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_RSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_RSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 208) - return OPCODE_RSR_CONFIGID1; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_RSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_RSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_RSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_RSR_INTERRUPT; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_RSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_RSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_RSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_RSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_RSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_RSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 235) - return OPCODE_RSR_PRID; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_RSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_RSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_RSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_RSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_RSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_RSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_RSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 1) - { - if (Field_sr_Slot_inst_get (insn) == 0) - return OPCODE_WSR_LBEG; - if (Field_sr_Slot_inst_get (insn) == 1) - return OPCODE_WSR_LEND; - if (Field_sr_Slot_inst_get (insn) == 2) - return OPCODE_WSR_LCOUNT; - if (Field_sr_Slot_inst_get (insn) == 3) - return OPCODE_WSR_SAR; - if (Field_sr_Slot_inst_get (insn) == 4) - return OPCODE_WSR_BR; - if (Field_sr_Slot_inst_get (insn) == 5) - return OPCODE_WSR_LITBASE; - if (Field_sr_Slot_inst_get (insn) == 12) - return OPCODE_WSR_SCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 72) - return OPCODE_WSR_WINDOWBASE; - if (Field_sr_Slot_inst_get (insn) == 73) - return OPCODE_WSR_WINDOWSTART; - if (Field_sr_Slot_inst_get (insn) == 83) - return OPCODE_WSR_PTEVADDR; - if (Field_sr_Slot_inst_get (insn) == 90) - return OPCODE_WSR_RASID; - if (Field_sr_Slot_inst_get (insn) == 91) - return OPCODE_WSR_ITLBCFG; - if (Field_sr_Slot_inst_get (insn) == 92) - return OPCODE_WSR_DTLBCFG; - if (Field_sr_Slot_inst_get (insn) == 99) - return OPCODE_WSR_ATOMCTL; - if (Field_sr_Slot_inst_get (insn) == 104) - return OPCODE_WSR_DDR; - if (Field_sr_Slot_inst_get (insn) == 176) - return OPCODE_WSR_CONFIGID0; - if (Field_sr_Slot_inst_get (insn) == 177) - return OPCODE_WSR_EPC1; - if (Field_sr_Slot_inst_get (insn) == 178) - return OPCODE_WSR_EPC2; - if (Field_sr_Slot_inst_get (insn) == 192) - return OPCODE_WSR_DEPC; - if (Field_sr_Slot_inst_get (insn) == 194) - return OPCODE_WSR_EPS2; - if (Field_sr_Slot_inst_get (insn) == 209) - return OPCODE_WSR_EXCSAVE1; - if (Field_sr_Slot_inst_get (insn) == 210) - return OPCODE_WSR_EXCSAVE2; - if (Field_sr_Slot_inst_get (insn) == 224) - return OPCODE_WSR_CPENABLE; - if (Field_sr_Slot_inst_get (insn) == 226) - return OPCODE_WSR_INTSET; - if (Field_sr_Slot_inst_get (insn) == 227) - return OPCODE_WSR_INTCLEAR; - if (Field_sr_Slot_inst_get (insn) == 228) - return OPCODE_WSR_INTENABLE; - if (Field_sr_Slot_inst_get (insn) == 230) - return OPCODE_WSR_PS; - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WSR_VECBASE; - if (Field_sr_Slot_inst_get (insn) == 232) - return OPCODE_WSR_EXCCAUSE; - if (Field_sr_Slot_inst_get (insn) == 233) - return OPCODE_WSR_DEBUGCAUSE; - if (Field_sr_Slot_inst_get (insn) == 234) - return OPCODE_WSR_CCOUNT; - if (Field_sr_Slot_inst_get (insn) == 236) - return OPCODE_WSR_ICOUNT; - if (Field_sr_Slot_inst_get (insn) == 237) - return OPCODE_WSR_ICOUNTLEVEL; - if (Field_sr_Slot_inst_get (insn) == 238) - return OPCODE_WSR_EXCVADDR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WSR_CCOMPARE0; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WSR_CCOMPARE1; - if (Field_sr_Slot_inst_get (insn) == 244) - return OPCODE_WSR_MISC0; - if (Field_sr_Slot_inst_get (insn) == 245) - return OPCODE_WSR_MISC1; - } - if (Field_op2_Slot_inst_get (insn) == 2) - return OPCODE_SEXT; - if (Field_op2_Slot_inst_get (insn) == 3) - return OPCODE_CLAMPS; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_MIN; - if (Field_op2_Slot_inst_get (insn) == 5) - return OPCODE_MAX; - if (Field_op2_Slot_inst_get (insn) == 6) - return OPCODE_MINU; - if (Field_op2_Slot_inst_get (insn) == 7) - return OPCODE_MAXU; - if (Field_op2_Slot_inst_get (insn) == 8) - return OPCODE_MOVEQZ; - if (Field_op2_Slot_inst_get (insn) == 9) - return OPCODE_MOVNEZ; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_MOVLTZ; - if (Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_MOVGEZ; - if (Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_MOVF; - if (Field_op2_Slot_inst_get (insn) == 13) - return OPCODE_MOVT; - if (Field_op2_Slot_inst_get (insn) == 14) - { - if (Field_st_Slot_inst_get (insn) == 231) - return OPCODE_RUR_THREADPTR; - if (Field_st_Slot_inst_get (insn) == 240) - return OPCODE_RUR_AE_OVF_SAR; - if (Field_st_Slot_inst_get (insn) == 241) - return OPCODE_RUR_AE_BITHEAD; - if (Field_st_Slot_inst_get (insn) == 242) - return OPCODE_RUR_AE_TS_FTS_BU_BP; - if (Field_st_Slot_inst_get (insn) == 243) - return OPCODE_RUR_AE_SD_NO; - } - if (Field_op2_Slot_inst_get (insn) == 15) - { - if (Field_sr_Slot_inst_get (insn) == 231) - return OPCODE_WUR_THREADPTR; - if (Field_sr_Slot_inst_get (insn) == 240) - return OPCODE_WUR_AE_OVF_SAR; - if (Field_sr_Slot_inst_get (insn) == 241) - return OPCODE_WUR_AE_BITHEAD; - if (Field_sr_Slot_inst_get (insn) == 242) - return OPCODE_WUR_AE_TS_FTS_BU_BP; - if (Field_sr_Slot_inst_get (insn) == 243) - return OPCODE_WUR_AE_SD_NO; - } - } - if ((Field_op1_Slot_inst_get (insn) == 4 || - Field_op1_Slot_inst_get (insn) == 5)) - return OPCODE_EXTUI; - if (Field_op1_Slot_inst_get (insn) == 9) - { - if (Field_op2_Slot_inst_get (insn) == 0) - return OPCODE_L32E; - if (Field_op2_Slot_inst_get (insn) == 4) - return OPCODE_S32E; - } - } - if (Field_op0_Slot_inst_get (insn) == 1) - return OPCODE_L32R; - if (Field_op0_Slot_inst_get (insn) == 2) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_L8UI; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_L16UI; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_L32I; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_S16I; - if (Field_r_Slot_inst_get (insn) == 6) - return OPCODE_S32I; - if (Field_r_Slot_inst_get (insn) == 7) - { - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_DPFR; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_DPFW; - if (Field_t_Slot_inst_get (insn) == 2) - return OPCODE_DPFRO; - if (Field_t_Slot_inst_get (insn) == 3) - return OPCODE_DPFWO; - if (Field_t_Slot_inst_get (insn) == 4) - return OPCODE_DHWB; - if (Field_t_Slot_inst_get (insn) == 5) - return OPCODE_DHWBI; - if (Field_t_Slot_inst_get (insn) == 6) - return OPCODE_DHI; - if (Field_t_Slot_inst_get (insn) == 7) - return OPCODE_DII; - if (Field_t_Slot_inst_get (insn) == 8) - { - if (Field_op1_Slot_inst_get (insn) == 4) - return OPCODE_DIWB; - if (Field_op1_Slot_inst_get (insn) == 5) - return OPCODE_DIWBI; - } - if (Field_t_Slot_inst_get (insn) == 12) - return OPCODE_IPF; - if (Field_t_Slot_inst_get (insn) == 14) - return OPCODE_IHI; - if (Field_t_Slot_inst_get (insn) == 15) - return OPCODE_III; - } - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_L16SI; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_MOVI; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_L32AI; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_ADDI; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_ADDMI; - if (Field_r_Slot_inst_get (insn) == 14) - return OPCODE_S32C1I; - if (Field_r_Slot_inst_get (insn) == 15) - return OPCODE_S32RI; - } - if (Field_op0_Slot_inst_get (insn) == 4) - { - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_ae_r10_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_ae_r10_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_ae_r10_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_ae_r10_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_ae_r3_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_ae_r32_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_ae_r32_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_ae_r32_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && - Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_r_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_r_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - if (Field_r_Slot_inst_get (insn) == 3 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - if (Field_r_Slot_inst_get (insn) == 4 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - if (Field_r_Slot_inst_get (insn) == 5 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - if (Field_r_Slot_inst_get (insn) == 6 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - if (Field_r_Slot_inst_get (insn) == 7 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - if (Field_r_Slot_inst_get (insn) == 8 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - if (Field_r_Slot_inst_get (insn) == 12 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - if (Field_r_Slot_inst_get (insn) == 13 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - if (Field_r_Slot_inst_get (insn) == 14 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - if (Field_s_Slot_inst_get (insn) == 1 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - if (Field_s_Slot_inst_get (insn) == 2 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - if (Field_s_Slot_inst_get (insn) == 3 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - if (Field_s_Slot_inst_get (insn) == 4 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - if (Field_s_Slot_inst_get (insn) == 8 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - if (Field_s_Slot_inst_get (insn) == 9 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - if (Field_s_Slot_inst_get (insn) == 10 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - if (Field_s_Slot_inst_get (insn) == 11 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - if (Field_s_Slot_inst_get (insn) == 12 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - if (Field_s_Slot_inst_get (insn) == 13 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - if (Field_s_Slot_inst_get (insn) == 14 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - if (Field_s_Slot_inst_get (insn) == 15 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - if (Field_t_Slot_inst_get (insn) == 2 && - Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - } - if (Field_op0_Slot_inst_get (insn) == 5) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_CALL0; - if (Field_n_Slot_inst_get (insn) == 1) - return OPCODE_CALL4; - if (Field_n_Slot_inst_get (insn) == 2) - return OPCODE_CALL8; - if (Field_n_Slot_inst_get (insn) == 3) - return OPCODE_CALL12; - } - if (Field_op0_Slot_inst_get (insn) == 6) - { - if (Field_n_Slot_inst_get (insn) == 0) - return OPCODE_J; - if (Field_n_Slot_inst_get (insn) == 1) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQZ; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTZ; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEZ; - } - if (Field_n_Slot_inst_get (insn) == 2) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_BEQI; - if (Field_m_Slot_inst_get (insn) == 1) - return OPCODE_BNEI; - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEI; - } - if (Field_n_Slot_inst_get (insn) == 3) - { - if (Field_m_Slot_inst_get (insn) == 0) - return OPCODE_ENTRY; - if (Field_m_Slot_inst_get (insn) == 1) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BF; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BT; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_LOOP; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_LOOPNEZ; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_LOOPGTZ; - } - if (Field_m_Slot_inst_get (insn) == 2) - return OPCODE_BLTUI; - if (Field_m_Slot_inst_get (insn) == 3) - return OPCODE_BGEUI; - } - } - if (Field_op0_Slot_inst_get (insn) == 7) - { - if (Field_r_Slot_inst_get (insn) == 0) - return OPCODE_BNONE; - if (Field_r_Slot_inst_get (insn) == 1) - return OPCODE_BEQ; - if (Field_r_Slot_inst_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_inst_get (insn) == 3) - return OPCODE_BLTU; - if (Field_r_Slot_inst_get (insn) == 4) - return OPCODE_BALL; - if (Field_r_Slot_inst_get (insn) == 5) - return OPCODE_BBC; - if ((Field_r_Slot_inst_get (insn) == 6 || - Field_r_Slot_inst_get (insn) == 7)) - return OPCODE_BBCI; - if (Field_r_Slot_inst_get (insn) == 8) - return OPCODE_BANY; - if (Field_r_Slot_inst_get (insn) == 9) - return OPCODE_BNE; - if (Field_r_Slot_inst_get (insn) == 10) - return OPCODE_BGE; - if (Field_r_Slot_inst_get (insn) == 11) - return OPCODE_BGEU; - if (Field_r_Slot_inst_get (insn) == 12) - return OPCODE_BNALL; - if (Field_r_Slot_inst_get (insn) == 13) - return OPCODE_BBS; - if ((Field_r_Slot_inst_get (insn) == 14 || - Field_r_Slot_inst_get (insn) == 15)) - return OPCODE_BBSI; - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16b_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16b_get (insn) == 12) - { - if (Field_i_Slot_inst16b_get (insn) == 0) - return OPCODE_MOVI_N; - if (Field_i_Slot_inst16b_get (insn) == 1) - { - if (Field_z_Slot_inst16b_get (insn) == 0) - return OPCODE_BEQZ_N; - if (Field_z_Slot_inst16b_get (insn) == 1) - return OPCODE_BNEZ_N; - } - } - if (Field_op0_Slot_inst16b_get (insn) == 13) - { - if (Field_r_Slot_inst16b_get (insn) == 0) - return OPCODE_MOV_N; - if (Field_r_Slot_inst16b_get (insn) == 15) - { - if (Field_t_Slot_inst16b_get (insn) == 0) - return OPCODE_RET_N; - if (Field_t_Slot_inst16b_get (insn) == 1) - return OPCODE_RETW_N; - if (Field_t_Slot_inst16b_get (insn) == 2) - return OPCODE_BREAK_N; - if (Field_t_Slot_inst16b_get (insn) == 3 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - if (Field_t_Slot_inst16b_get (insn) == 6 && - Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - } - } - return XTENSA_UNDEFINED; -} - -static int -Slot_inst16a_decode (const xtensa_insnbuf insn) -{ - if (Field_op0_Slot_inst16a_get (insn) == 8) - return OPCODE_L32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 9) - return OPCODE_S32I_N; - if (Field_op0_Slot_inst16a_get (insn) == 10) - return OPCODE_ADD_N; - if (Field_op0_Slot_inst16a_get (insn) == 11) - return OPCODE_ADDI_N; - return XTENSA_UNDEFINED; -} - -static int -Slot_ae_slot0_decode (const xtensa_insnbuf insn) -{ - if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_J; - if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_EXTUI; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_ftsf217_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && - Field_ae_r20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_L32I; - if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 419 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_I; - if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 420 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 421 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_IU; - if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 422 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_X; - if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 423 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16F_XU; - if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 424 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 425 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_I; - if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 426 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_IU; - if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 427 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_XU; - if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 428 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP16X2F_X; - if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 429 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_I; - if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 430 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_IU; - if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 431 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_X; - if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 432 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 433 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24_XU; - if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 434 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_I; - if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 435 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_XU; - if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 436 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_IU; - if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 437 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_I; - if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 438 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_IU; - if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 439 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_X; - if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 440 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24F_X; - if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 441 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2_XU; - if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 442 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_I; - if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 443 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_X; - if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 444 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_IU; - if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 445 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LP24X2F_XU; - if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 446 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVPA24X2; - if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 447 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_I; - if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 450 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_IU; - if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 451 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_X; - if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 452 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_X; - if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 453 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_XU; - if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 454 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_I; - if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 455 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_IU; - if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 456 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16F_L_XU; - if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 457 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_X; - if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 458 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24F_L_XU; - if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 459 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_IU; - if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 460 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_I; - if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 461 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_X; - if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 462 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24S_L_XU; - if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 463 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_I; - if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 464 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_I; - if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 465 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_IU; - if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 466 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_X; - if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 467 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_IU; - if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 468 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2F_XU; - if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 469 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_X; - if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 470 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_XU; - if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 471 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 472 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP24X2S_I; - if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 946 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_I; - if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 947 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ32F_IU; - if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 948 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_I; - if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 949 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_X; - if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 950 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_XU; - if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 951 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_I; - if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 952 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ32F_IU; - if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 953 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_IU; - if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 954 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_LQ56_X; - if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 15280 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTQ48A32S; - if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 60977 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_JX; - if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 61041 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SSR; - if (Field_ftsf283ae_slot0_Slot_ae_slot0_get (insn) == 30577 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf352ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 7641 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf354ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8B; - if (Field_ftsf286ae_slot0_Slot_ae_slot0_get (insn) == 3821 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf356ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSA8L; - if (Field_ftsf288ae_slot0_Slot_ae_slot0_get (insn) == 1911 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf359ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSL; - if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 478 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s8_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_LQ56_XU; - if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 1913 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL8; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_s_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY8; - if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 959 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf358ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_SSAI; - if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 480 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SP16X2F_IU; - if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 962 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_I; - if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_IU; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVQ56; - if (Field_ftsf303ae_slot0_Slot_ae_slot0_get (insn) == 31017 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSSQ56S; - if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 15509 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf369ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRASQ56; - if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 7755 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLSQ56; - if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 1939 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SLLSQ56; - if (Field_ftsf309ae_slot0_Slot_ae_slot0_get (insn) == 485 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ALL4; - if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 972 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_X; - if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 973 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SQ56S_XU; - if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 7792 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_H; - if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 7793 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_CVTA32P24_L; - if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 7794 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_H; - if (Field_ftsf315ae_slot0_Slot_ae_slot0_get (insn) == 7795 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_TRUNCA16P24S_L; - if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 7796 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVAP24S_L; - if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 7797 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_NSAQ56S; - if (Field_ftsf318ae_slot0_Slot_ae_slot0_get (insn) == 3899 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf365ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA32Q48; - if (Field_ftsf319_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BT; - if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 975 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_TRUNCA16P24S_H; - if (Field_ftsf321_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BLTUI; - if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 3920 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_MOVFQ56; - if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 3921 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLAQ56; - if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 3922 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLASQ56S; - if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 3923 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLL; - if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 981 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf357_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRAAQ56; - if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 491 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SRLAQ56; - if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_XU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) - return OPCODE_L32R; - if (Field_r_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - if (Field_r_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - if (Field_r_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - if (Field_r_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_r_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_r_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_r_Slot_ae_slot0_get (insn) == 6 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_r_Slot_ae_slot0_get (insn) == 7 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - if (Field_r_Slot_ae_slot0_get (insn) == 8 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - if (Field_r_Slot_ae_slot0_get (insn) == 9 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - if (Field_r_Slot_ae_slot0_get (insn) == 10 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - if (Field_r_Slot_ae_slot0_get (insn) == 11 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - if (Field_r_Slot_ae_slot0_get (insn) == 12 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - if (Field_r_Slot_ae_slot0_get (insn) == 13 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - if (Field_r_Slot_ae_slot0_get (insn) == 14 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - if (Field_r_Slot_ae_slot0_get (insn) == 15 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - if (Field_t_Slot_ae_slot0_get (insn) == 0 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - if (Field_t_Slot_ae_slot0_get (insn) == 1 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - if (Field_t_Slot_ae_slot0_get (insn) == 2 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - if (Field_t_Slot_ae_slot0_get (insn) == 3 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - if (Field_t_Slot_ae_slot0_get (insn) == 4 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - if (Field_t_Slot_ae_slot0_get (insn) == 5 && - Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - return XTENSA_UNDEFINED; -} - -static int -Slot_ae_slot1_decode (const xtensa_insnbuf insn) -{ - if (Field_ftsf100ae_slot1_Slot_ae_slot1_get (insn) == 115 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGSP24S; - if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSP24S; - if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGP24; - if (Field_ftsf104ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXBQ56S; - if (Field_ftsf105ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINBQ56S; - if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ae_r32_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_EQQ56; - if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ADDSQ56S; - if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ANDQ56; - if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MAXQ56S; - if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ORQ56; - if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_MINQ56S; - if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBQ56; - if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_SUBSQ56S; - if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_XORQ56; - if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NANDQ56; - if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_ABSQ56; - if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5) - return OPCODE_AE_NEGSQ56S; - if (Field_ftsf119ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf338_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SATQ48S; - if (Field_ftsf12_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTQ56S; - if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSSQ56S; - if (Field_ftsf122ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf346ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_NEGQ56; - if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LEQ56S; - if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCP24Q48X2; - if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && - Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ADDQ56; - if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HH_LL; - if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAFP24S_HL_LH; - if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HH_LL; - if (Field_ftsf13_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf12_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLISP24S; - if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_HL; - if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAAP24S_HL_LH; - if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LH; - if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS32P16S_LL; - if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HH; - if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HH; - if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_HL; - if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LH; - if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HH; - if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFS56P24S_LL; - if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_HL; - if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LH; - if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAP24S_LL; - if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 16 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_HL; - if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 17 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HH; - if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 18 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_HL; - if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 19 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HH_LL; - if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LH; - if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASFP24S_HL_LH; - if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HH_LL; - if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULASP24S_HL_LH; - if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAS56P24S_LL; - if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HH; - if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_HL; - if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LL; - if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFP24S_LH; - if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HH; - if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_HL; - if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LH; - if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 32 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LH; - if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 33 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULFS32P16S_LL; - if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 34 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HH; - if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 35 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HH_LL; - if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 36 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_HL; - if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 37 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAFP24S_HL_LH; - if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 38 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HH_LL; - if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 39 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSAP24S_HL_LH; - if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 40 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LH; - if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 41 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HH; - if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 42 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_HL; - if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 43 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LL; - if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 44 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFP24S_LH; - if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 45 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HH; - if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 46 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_HL; - if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 47 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LH; - if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 48 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULP24S_LL; - if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS32P16S_LL; - if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 50 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HH; - if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 51 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LL; - if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 52 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_HL; - if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 53 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HH; - if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 54 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_HL; - if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 55 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LH; - if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 56 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSFS56P24S_LH; - if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 57 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSP24S_LL; - if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 58 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HH; - if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 59 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LH; - if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 60 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_HL; - if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 61 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSS56P24S_LL; - if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 62 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HH_LL; - if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 63 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSFP24S_HL_LH; - if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 64 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULAFP24S_LL; - if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 65 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HH_LL; - if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 66 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULSSP24S_HL_LH; - if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 67 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HH_LL; - if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 68 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HH_LL; - if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 69 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASFP24S_HL_LH; - if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 70 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HH_LL; - if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 71 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZASP24S_HL_LH; - if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 72 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZAAFP24S_HL_LH; - if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 73 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HH_LL; - if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 74 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAFP24S_HL_LH; - if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 75 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HL_LH; - if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 76 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSAP24S_HH_LL; - if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 77 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HH_LL; - if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 78 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSFP24S_HL_LH; - if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 79 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6) - return OPCODE_AE_MULZSSP24S_HH_LL; - if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HH_LL; - if (Field_ftsf209ae_slot1_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZSSP24S_HL_LH; - if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULZAAP24S_HL_LH; - if (Field_ftsf211ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && - Field_ftsf332ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULAFS32P16S_HH; - if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXBP24S; - if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINBP24S; - if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVFP48; - if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVTP48; - if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDP24; - if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ANDP48; - if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 22 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MAXP24S; - if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 23 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MINP24S; - if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 24 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ADDSP24S; - if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_NANDP48; - if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ORP48; - if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 27 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HL; - if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 28 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_HH; - if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 29 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LH; - if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 30 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SELP24_LL; - if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_L; - if (Field_ftsf39ae_slot1_Slot_ae_slot1_get (insn) == 177 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_H; - if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 178 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16U_L; - if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 179 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_H; - if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 180 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_H; - if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 181 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16U_L; - if (Field_ftsf44ae_slot1_Slot_ae_slot1_get (insn) == 182 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_H; - if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 183 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16S_L; - if (Field_ftsf46ae_slot1_Slot_ae_slot1_get (insn) == 184 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAQ32SP16S_L; - if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 185 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_H; - if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 186 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULFQ32SP16U_L; - if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 187 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_L; - if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 188 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16S_H; - if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 189 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_H; - if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 190 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULQ32SP16U_L; - if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 191 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_H; - if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 192 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULAFQ32SP16S_H; - if (Field_ftsf55ae_slot1_Slot_ae_slot1_get (insn) == 193 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16S_L; - if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 194 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_H; - if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 195 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSQ32SP16U_L; - if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 196 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MULSFQ32SP16U_L; - if (Field_ftsf59ae_slot1_Slot_ae_slot1_get (insn) == 773 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_CVTQ48P24S_H; - if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 789 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROQ56; - if (Field_ftsf61ae_slot1_Slot_ae_slot1_get (insn) == 405 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf330ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_NOP; - if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 198 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_CVTQ48P24S_L; - if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 1543 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVQ56; - if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 1559 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSQ32ASYM; - if (Field_ftsf67ae_slot1_Slot_ae_slot1_get (insn) == 791 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSQ32SYM; - if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 407 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_TRUNCQ32; - if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_H; - if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 26 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16S_L; - if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 417 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_MOVP48; - if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 419 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16ASYM; - if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 421 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16SYM; - if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 423 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRASP24; - if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 425 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLSP24; - if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 427 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLSP24; - if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 429 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_TRUNCP16; - if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 431 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ZEROP48; - if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 109 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r10_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_SLLSSP24S; - if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 881 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48ASYM; - if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 883 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_ROUNDSP16Q48SYM; - if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 443 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48ASYM; - if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 223 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf340_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ROUNDSP24Q48SYM; - if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MULSQ32SP16U_H; - if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 96 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_EQP24; - if (Field_ftsf91ae_slot1_Slot_ae_slot1_get (insn) == 97 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_LEP24S; - if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 49 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf208_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_LTP24S; - if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 25 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ftsf347_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVFP24X2; - if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_s20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_MOVTP24X2; - if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 112 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SUBSP24S; - if (Field_ftsf98ae_slot1_Slot_ae_slot1_get (insn) == 113 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_XORP48; - if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 114 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && - Field_ae_r20_Slot_ae_slot1_get (insn) == 0) - return OPCODE_AE_ABSP24; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 0 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 1 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 2 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 3 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 4 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 5 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 6 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 7 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 8 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 9 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 10 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 11 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 12 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 13 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 14 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_t_Slot_ae_slot1_get (insn) == 15 && - Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - return XTENSA_UNDEFINED; -} - - -/* Instruction slots. */ - -static void -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffffff); -} - -static void -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); -} - -static void -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = (insn[0] & 0xffff); -} - -static void -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); -} - -static void -Slot_ae_format_Format_ae_slot1_31_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x80000000) >> 31); - slotbuf[0] = (slotbuf[0] & ~0x7ffffe) | ((insn[1] & 0x3fffff) << 1); -} - -static void -Slot_ae_format_Format_ae_slot1_31_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); - insn[1] = (insn[1] & ~0x3fffff) | ((slotbuf[0] & 0x7ffffe) >> 1); -} - -static void -Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, - xtensa_insnbuf slotbuf) -{ - slotbuf[1] = 0; - slotbuf[0] = ((insn[0] & 0x7ffffff0) >> 4); -} - -static void -Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, - const xtensa_insnbuf slotbuf) -{ - insn[0] = (insn[0] & ~0x7ffffff0) | ((slotbuf[0] & 0x7ffffff) << 4); -} - -static xtensa_get_field_fn -Slot_inst_get_field_fns[] = { - Field_t_Slot_inst_get, - Field_bbi4_Slot_inst_get, - Field_bbi_Slot_inst_get, - Field_imm12_Slot_inst_get, - Field_imm8_Slot_inst_get, - Field_s_Slot_inst_get, - Field_imm12b_Slot_inst_get, - Field_imm16_Slot_inst_get, - Field_m_Slot_inst_get, - Field_n_Slot_inst_get, - Field_offset_Slot_inst_get, - Field_op0_Slot_inst_get, - Field_op1_Slot_inst_get, - Field_op2_Slot_inst_get, - Field_r_Slot_inst_get, - Field_sa4_Slot_inst_get, - Field_sae4_Slot_inst_get, - Field_sae_Slot_inst_get, - Field_sal_Slot_inst_get, - Field_sargt_Slot_inst_get, - Field_sas4_Slot_inst_get, - Field_sas_Slot_inst_get, - Field_sr_Slot_inst_get, - Field_st_Slot_inst_get, - Field_thi3_Slot_inst_get, - Field_imm4_Slot_inst_get, - Field_mn_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_get, - Field_s2_Slot_inst_get, - Field_r2_Slot_inst_get, - Field_t4_Slot_inst_get, - Field_s4_Slot_inst_get, - Field_r4_Slot_inst_get, - Field_t8_Slot_inst_get, - Field_s8_Slot_inst_get, - Field_r8_Slot_inst_get, - Field_xt_wbr15_imm_Slot_inst_get, - Field_xt_wbr18_imm_Slot_inst_get, - Field_ae_r3_Slot_inst_get, - Field_ae_s_non_samt_Slot_inst_get, - Field_ae_s3_Slot_inst_get, - Field_ae_r32_Slot_inst_get, - Field_ae_samt_s_t_Slot_inst_get, - Field_ae_r20_Slot_inst_get, - Field_ae_r10_Slot_inst_get, - Field_ae_s20_Slot_inst_get, - Field_ae_fld_ohba_Slot_inst_get, - Field_ae_fld_ohba2_Slot_inst_get, - 0, - Field_ftsf12_Slot_inst_get, - Field_ftsf13_Slot_inst_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst_set_field_fns[] = { - Field_t_Slot_inst_set, - Field_bbi4_Slot_inst_set, - Field_bbi_Slot_inst_set, - Field_imm12_Slot_inst_set, - Field_imm8_Slot_inst_set, - Field_s_Slot_inst_set, - Field_imm12b_Slot_inst_set, - Field_imm16_Slot_inst_set, - Field_m_Slot_inst_set, - Field_n_Slot_inst_set, - Field_offset_Slot_inst_set, - Field_op0_Slot_inst_set, - Field_op1_Slot_inst_set, - Field_op2_Slot_inst_set, - Field_r_Slot_inst_set, - Field_sa4_Slot_inst_set, - Field_sae4_Slot_inst_set, - Field_sae_Slot_inst_set, - Field_sal_Slot_inst_set, - Field_sargt_Slot_inst_set, - Field_sas4_Slot_inst_set, - Field_sas_Slot_inst_set, - Field_sr_Slot_inst_set, - Field_st_Slot_inst_set, - Field_thi3_Slot_inst_set, - Field_imm4_Slot_inst_set, - Field_mn_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_inst_set, - Field_s2_Slot_inst_set, - Field_r2_Slot_inst_set, - Field_t4_Slot_inst_set, - Field_s4_Slot_inst_set, - Field_r4_Slot_inst_set, - Field_t8_Slot_inst_set, - Field_s8_Slot_inst_set, - Field_r8_Slot_inst_set, - Field_xt_wbr15_imm_Slot_inst_set, - Field_xt_wbr18_imm_Slot_inst_set, - Field_ae_r3_Slot_inst_set, - Field_ae_s_non_samt_Slot_inst_set, - Field_ae_s3_Slot_inst_set, - Field_ae_r32_Slot_inst_set, - Field_ae_samt_s_t_Slot_inst_set, - Field_ae_r20_Slot_inst_set, - Field_ae_r10_Slot_inst_set, - Field_ae_s20_Slot_inst_set, - Field_ae_fld_ohba_Slot_inst_set, - Field_ae_fld_ohba2_Slot_inst_set, - 0, - Field_ftsf12_Slot_inst_set, - Field_ftsf13_Slot_inst_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16a_get_field_fns[] = { - Field_t_Slot_inst16a_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_get, - 0, - 0, - Field_r_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_get, - Field_st_Slot_inst16a_get, - 0, - Field_imm4_Slot_inst16a_get, - 0, - Field_i_Slot_inst16a_get, - Field_imm6lo_Slot_inst16a_get, - Field_imm6hi_Slot_inst16a_get, - Field_imm7lo_Slot_inst16a_get, - Field_imm7hi_Slot_inst16a_get, - Field_z_Slot_inst16a_get, - Field_imm6_Slot_inst16a_get, - Field_imm7_Slot_inst16a_get, - Field_t2_Slot_inst16a_get, - Field_s2_Slot_inst16a_get, - Field_r2_Slot_inst16a_get, - Field_t4_Slot_inst16a_get, - Field_s4_Slot_inst16a_get, - Field_r4_Slot_inst16a_get, - Field_t8_Slot_inst16a_get, - Field_s8_Slot_inst16a_get, - Field_r8_Slot_inst16a_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16a_set_field_fns[] = { - Field_t_Slot_inst16a_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16a_set, - 0, - 0, - Field_r_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16a_set, - Field_st_Slot_inst16a_set, - 0, - Field_imm4_Slot_inst16a_set, - 0, - Field_i_Slot_inst16a_set, - Field_imm6lo_Slot_inst16a_set, - Field_imm6hi_Slot_inst16a_set, - Field_imm7lo_Slot_inst16a_set, - Field_imm7hi_Slot_inst16a_set, - Field_z_Slot_inst16a_set, - Field_imm6_Slot_inst16a_set, - Field_imm7_Slot_inst16a_set, - Field_t2_Slot_inst16a_set, - Field_s2_Slot_inst16a_set, - Field_r2_Slot_inst16a_set, - Field_t4_Slot_inst16a_set, - Field_s4_Slot_inst16a_set, - Field_r4_Slot_inst16a_set, - Field_t8_Slot_inst16a_set, - Field_s8_Slot_inst16a_set, - Field_r8_Slot_inst16a_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_inst16b_get_field_fns[] = { - Field_t_Slot_inst16b_get, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_get, - 0, - 0, - Field_r_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_get, - Field_st_Slot_inst16b_get, - 0, - Field_imm4_Slot_inst16b_get, - 0, - Field_i_Slot_inst16b_get, - Field_imm6lo_Slot_inst16b_get, - Field_imm6hi_Slot_inst16b_get, - Field_imm7lo_Slot_inst16b_get, - Field_imm7hi_Slot_inst16b_get, - Field_z_Slot_inst16b_get, - Field_imm6_Slot_inst16b_get, - Field_imm7_Slot_inst16b_get, - Field_t2_Slot_inst16b_get, - Field_s2_Slot_inst16b_get, - Field_r2_Slot_inst16b_get, - Field_t4_Slot_inst16b_get, - Field_s4_Slot_inst16b_get, - Field_r4_Slot_inst16b_get, - Field_t8_Slot_inst16b_get, - Field_s8_Slot_inst16b_get, - Field_r8_Slot_inst16b_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_inst16b_set_field_fns[] = { - Field_t_Slot_inst16b_set, - 0, - 0, - 0, - 0, - Field_s_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - Field_op0_Slot_inst16b_set, - 0, - 0, - Field_r_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_sr_Slot_inst16b_set, - Field_st_Slot_inst16b_set, - 0, - Field_imm4_Slot_inst16b_set, - 0, - Field_i_Slot_inst16b_set, - Field_imm6lo_Slot_inst16b_set, - Field_imm6hi_Slot_inst16b_set, - Field_imm7lo_Slot_inst16b_set, - Field_imm7hi_Slot_inst16b_set, - Field_z_Slot_inst16b_set, - Field_imm6_Slot_inst16b_set, - Field_imm7_Slot_inst16b_set, - Field_t2_Slot_inst16b_set, - Field_s2_Slot_inst16b_set, - Field_r2_Slot_inst16b_set, - Field_t4_Slot_inst16b_set, - Field_s4_Slot_inst16b_set, - Field_r4_Slot_inst16b_set, - Field_t8_Slot_inst16b_set, - Field_s8_Slot_inst16b_set, - Field_r8_Slot_inst16b_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot1_get_field_fns[] = { - Field_t_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_get, - 0, - Field_ae_r20_Slot_ae_slot1_get, - Field_ae_r10_Slot_ae_slot1_get, - Field_ae_s20_Slot_ae_slot1_get, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_get, - Field_ftsf12_Slot_ae_slot1_get, - Field_ftsf13_Slot_ae_slot1_get, - Field_ftsf14_Slot_ae_slot1_get, - Field_ftsf21ae_slot1_Slot_ae_slot1_get, - Field_ftsf22ae_slot1_Slot_ae_slot1_get, - Field_ftsf23ae_slot1_Slot_ae_slot1_get, - Field_ftsf24ae_slot1_Slot_ae_slot1_get, - Field_ftsf25ae_slot1_Slot_ae_slot1_get, - Field_ftsf26ae_slot1_Slot_ae_slot1_get, - Field_ftsf27ae_slot1_Slot_ae_slot1_get, - Field_ftsf28ae_slot1_Slot_ae_slot1_get, - Field_ftsf29ae_slot1_Slot_ae_slot1_get, - Field_ftsf30ae_slot1_Slot_ae_slot1_get, - Field_ftsf31ae_slot1_Slot_ae_slot1_get, - Field_ftsf32ae_slot1_Slot_ae_slot1_get, - Field_ftsf33ae_slot1_Slot_ae_slot1_get, - Field_ftsf34ae_slot1_Slot_ae_slot1_get, - Field_ftsf35ae_slot1_Slot_ae_slot1_get, - Field_ftsf36ae_slot1_Slot_ae_slot1_get, - Field_ftsf37ae_slot1_Slot_ae_slot1_get, - Field_ftsf38ae_slot1_Slot_ae_slot1_get, - Field_ftsf39ae_slot1_Slot_ae_slot1_get, - Field_ftsf40ae_slot1_Slot_ae_slot1_get, - Field_ftsf41ae_slot1_Slot_ae_slot1_get, - Field_ftsf42ae_slot1_Slot_ae_slot1_get, - Field_ftsf43ae_slot1_Slot_ae_slot1_get, - Field_ftsf44ae_slot1_Slot_ae_slot1_get, - Field_ftsf45ae_slot1_Slot_ae_slot1_get, - Field_ftsf46ae_slot1_Slot_ae_slot1_get, - Field_ftsf47ae_slot1_Slot_ae_slot1_get, - Field_ftsf48ae_slot1_Slot_ae_slot1_get, - Field_ftsf49ae_slot1_Slot_ae_slot1_get, - Field_ftsf50ae_slot1_Slot_ae_slot1_get, - Field_ftsf51ae_slot1_Slot_ae_slot1_get, - Field_ftsf52ae_slot1_Slot_ae_slot1_get, - Field_ftsf53ae_slot1_Slot_ae_slot1_get, - Field_ftsf54ae_slot1_Slot_ae_slot1_get, - Field_ftsf55ae_slot1_Slot_ae_slot1_get, - Field_ftsf56ae_slot1_Slot_ae_slot1_get, - Field_ftsf57ae_slot1_Slot_ae_slot1_get, - Field_ftsf58ae_slot1_Slot_ae_slot1_get, - Field_ftsf59ae_slot1_Slot_ae_slot1_get, - Field_ftsf60ae_slot1_Slot_ae_slot1_get, - Field_ftsf61ae_slot1_Slot_ae_slot1_get, - Field_ftsf63ae_slot1_Slot_ae_slot1_get, - Field_ftsf64ae_slot1_Slot_ae_slot1_get, - Field_ftsf66ae_slot1_Slot_ae_slot1_get, - Field_ftsf67ae_slot1_Slot_ae_slot1_get, - Field_ftsf69ae_slot1_Slot_ae_slot1_get, - Field_ftsf71ae_slot1_Slot_ae_slot1_get, - Field_ftsf72ae_slot1_Slot_ae_slot1_get, - Field_ftsf73ae_slot1_Slot_ae_slot1_get, - Field_ftsf75ae_slot1_Slot_ae_slot1_get, - Field_ftsf76ae_slot1_Slot_ae_slot1_get, - Field_ftsf77ae_slot1_Slot_ae_slot1_get, - Field_ftsf78ae_slot1_Slot_ae_slot1_get, - Field_ftsf79ae_slot1_Slot_ae_slot1_get, - Field_ftsf80ae_slot1_Slot_ae_slot1_get, - Field_ftsf81ae_slot1_Slot_ae_slot1_get, - Field_ftsf82ae_slot1_Slot_ae_slot1_get, - Field_ftsf84ae_slot1_Slot_ae_slot1_get, - Field_ftsf86ae_slot1_Slot_ae_slot1_get, - Field_ftsf87ae_slot1_Slot_ae_slot1_get, - Field_ftsf88ae_slot1_Slot_ae_slot1_get, - Field_ftsf89ae_slot1_Slot_ae_slot1_get, - Field_ftsf90ae_slot1_Slot_ae_slot1_get, - Field_ftsf91ae_slot1_Slot_ae_slot1_get, - Field_ftsf92ae_slot1_Slot_ae_slot1_get, - Field_ftsf94ae_slot1_Slot_ae_slot1_get, - Field_ftsf96ae_slot1_Slot_ae_slot1_get, - Field_ftsf97ae_slot1_Slot_ae_slot1_get, - Field_ftsf98ae_slot1_Slot_ae_slot1_get, - Field_ftsf99ae_slot1_Slot_ae_slot1_get, - Field_ftsf100ae_slot1_Slot_ae_slot1_get, - Field_ftsf101ae_slot1_Slot_ae_slot1_get, - Field_ftsf103ae_slot1_Slot_ae_slot1_get, - Field_ftsf104ae_slot1_Slot_ae_slot1_get, - Field_ftsf105ae_slot1_Slot_ae_slot1_get, - Field_ftsf106ae_slot1_Slot_ae_slot1_get, - Field_ftsf107ae_slot1_Slot_ae_slot1_get, - Field_ftsf108ae_slot1_Slot_ae_slot1_get, - Field_ftsf109ae_slot1_Slot_ae_slot1_get, - Field_ftsf110ae_slot1_Slot_ae_slot1_get, - Field_ftsf111ae_slot1_Slot_ae_slot1_get, - Field_ftsf112ae_slot1_Slot_ae_slot1_get, - Field_ftsf113ae_slot1_Slot_ae_slot1_get, - Field_ftsf114ae_slot1_Slot_ae_slot1_get, - Field_ftsf115ae_slot1_Slot_ae_slot1_get, - Field_ftsf116ae_slot1_Slot_ae_slot1_get, - Field_ftsf118ae_slot1_Slot_ae_slot1_get, - Field_ftsf119ae_slot1_Slot_ae_slot1_get, - Field_ftsf120ae_slot1_Slot_ae_slot1_get, - Field_ftsf122ae_slot1_Slot_ae_slot1_get, - Field_ftsf124ae_slot1_Slot_ae_slot1_get, - Field_ftsf125ae_slot1_Slot_ae_slot1_get, - Field_ftsf126ae_slot1_Slot_ae_slot1_get, - Field_ftsf127ae_slot1_Slot_ae_slot1_get, - Field_ftsf128ae_slot1_Slot_ae_slot1_get, - Field_ftsf129ae_slot1_Slot_ae_slot1_get, - Field_ftsf130ae_slot1_Slot_ae_slot1_get, - Field_ftsf131ae_slot1_Slot_ae_slot1_get, - Field_ftsf132ae_slot1_Slot_ae_slot1_get, - Field_ftsf133ae_slot1_Slot_ae_slot1_get, - Field_ftsf134ae_slot1_Slot_ae_slot1_get, - Field_ftsf135ae_slot1_Slot_ae_slot1_get, - Field_ftsf136ae_slot1_Slot_ae_slot1_get, - Field_ftsf137ae_slot1_Slot_ae_slot1_get, - Field_ftsf138ae_slot1_Slot_ae_slot1_get, - Field_ftsf139ae_slot1_Slot_ae_slot1_get, - Field_ftsf140ae_slot1_Slot_ae_slot1_get, - Field_ftsf141ae_slot1_Slot_ae_slot1_get, - Field_ftsf142ae_slot1_Slot_ae_slot1_get, - Field_ftsf143ae_slot1_Slot_ae_slot1_get, - Field_ftsf144ae_slot1_Slot_ae_slot1_get, - Field_ftsf145ae_slot1_Slot_ae_slot1_get, - Field_ftsf146ae_slot1_Slot_ae_slot1_get, - Field_ftsf147ae_slot1_Slot_ae_slot1_get, - Field_ftsf148ae_slot1_Slot_ae_slot1_get, - Field_ftsf149ae_slot1_Slot_ae_slot1_get, - Field_ftsf150ae_slot1_Slot_ae_slot1_get, - Field_ftsf151ae_slot1_Slot_ae_slot1_get, - Field_ftsf152ae_slot1_Slot_ae_slot1_get, - Field_ftsf153ae_slot1_Slot_ae_slot1_get, - Field_ftsf154ae_slot1_Slot_ae_slot1_get, - Field_ftsf155ae_slot1_Slot_ae_slot1_get, - Field_ftsf156ae_slot1_Slot_ae_slot1_get, - Field_ftsf157ae_slot1_Slot_ae_slot1_get, - Field_ftsf158ae_slot1_Slot_ae_slot1_get, - Field_ftsf159ae_slot1_Slot_ae_slot1_get, - Field_ftsf160ae_slot1_Slot_ae_slot1_get, - Field_ftsf161ae_slot1_Slot_ae_slot1_get, - Field_ftsf162ae_slot1_Slot_ae_slot1_get, - Field_ftsf163ae_slot1_Slot_ae_slot1_get, - Field_ftsf164ae_slot1_Slot_ae_slot1_get, - Field_ftsf165ae_slot1_Slot_ae_slot1_get, - Field_ftsf166ae_slot1_Slot_ae_slot1_get, - Field_ftsf167ae_slot1_Slot_ae_slot1_get, - Field_ftsf168ae_slot1_Slot_ae_slot1_get, - Field_ftsf169ae_slot1_Slot_ae_slot1_get, - Field_ftsf170ae_slot1_Slot_ae_slot1_get, - Field_ftsf171ae_slot1_Slot_ae_slot1_get, - Field_ftsf172ae_slot1_Slot_ae_slot1_get, - Field_ftsf173ae_slot1_Slot_ae_slot1_get, - Field_ftsf174ae_slot1_Slot_ae_slot1_get, - Field_ftsf175ae_slot1_Slot_ae_slot1_get, - Field_ftsf176ae_slot1_Slot_ae_slot1_get, - Field_ftsf177ae_slot1_Slot_ae_slot1_get, - Field_ftsf178ae_slot1_Slot_ae_slot1_get, - Field_ftsf179ae_slot1_Slot_ae_slot1_get, - Field_ftsf180ae_slot1_Slot_ae_slot1_get, - Field_ftsf181ae_slot1_Slot_ae_slot1_get, - Field_ftsf182ae_slot1_Slot_ae_slot1_get, - Field_ftsf183ae_slot1_Slot_ae_slot1_get, - Field_ftsf184ae_slot1_Slot_ae_slot1_get, - Field_ftsf185ae_slot1_Slot_ae_slot1_get, - Field_ftsf186ae_slot1_Slot_ae_slot1_get, - Field_ftsf187ae_slot1_Slot_ae_slot1_get, - Field_ftsf188ae_slot1_Slot_ae_slot1_get, - Field_ftsf189ae_slot1_Slot_ae_slot1_get, - Field_ftsf190ae_slot1_Slot_ae_slot1_get, - Field_ftsf191ae_slot1_Slot_ae_slot1_get, - Field_ftsf192ae_slot1_Slot_ae_slot1_get, - Field_ftsf193ae_slot1_Slot_ae_slot1_get, - Field_ftsf194ae_slot1_Slot_ae_slot1_get, - Field_ftsf195ae_slot1_Slot_ae_slot1_get, - Field_ftsf196ae_slot1_Slot_ae_slot1_get, - Field_ftsf197ae_slot1_Slot_ae_slot1_get, - Field_ftsf198ae_slot1_Slot_ae_slot1_get, - Field_ftsf199ae_slot1_Slot_ae_slot1_get, - Field_ftsf200ae_slot1_Slot_ae_slot1_get, - Field_ftsf201ae_slot1_Slot_ae_slot1_get, - Field_ftsf202ae_slot1_Slot_ae_slot1_get, - Field_ftsf203ae_slot1_Slot_ae_slot1_get, - Field_ftsf204ae_slot1_Slot_ae_slot1_get, - Field_ftsf205ae_slot1_Slot_ae_slot1_get, - Field_ftsf206ae_slot1_Slot_ae_slot1_get, - Field_ftsf207ae_slot1_Slot_ae_slot1_get, - Field_ftsf208_Slot_ae_slot1_get, - Field_ftsf209ae_slot1_Slot_ae_slot1_get, - Field_ftsf210ae_slot1_Slot_ae_slot1_get, - Field_ftsf211ae_slot1_Slot_ae_slot1_get, - Field_ftsf330ae_slot1_Slot_ae_slot1_get, - Field_ftsf332ae_slot1_Slot_ae_slot1_get, - Field_ftsf334ae_slot1_Slot_ae_slot1_get, - Field_ftsf336ae_slot1_Slot_ae_slot1_get, - Field_ftsf337ae_slot1_Slot_ae_slot1_get, - Field_ftsf338_Slot_ae_slot1_get, - Field_ftsf339ae_slot1_Slot_ae_slot1_get, - Field_ftsf340_Slot_ae_slot1_get, - Field_ftsf341ae_slot1_Slot_ae_slot1_get, - Field_ftsf342ae_slot1_Slot_ae_slot1_get, - Field_ftsf343ae_slot1_Slot_ae_slot1_get, - Field_ftsf344ae_slot1_Slot_ae_slot1_get, - Field_ftsf346ae_slot1_Slot_ae_slot1_get, - Field_ftsf347_Slot_ae_slot1_get, - Field_ftsf348ae_slot1_Slot_ae_slot1_get, - Field_ftsf349ae_slot1_Slot_ae_slot1_get, - Field_ftsf350ae_slot1_Slot_ae_slot1_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot1_set_field_fns[] = { - Field_t_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_t2_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot1_set, - 0, - Field_ae_r20_Slot_ae_slot1_set, - Field_ae_r10_Slot_ae_slot1_set, - Field_ae_s20_Slot_ae_slot1_set, - 0, - 0, - Field_op0_s3_Slot_ae_slot1_set, - Field_ftsf12_Slot_ae_slot1_set, - Field_ftsf13_Slot_ae_slot1_set, - Field_ftsf14_Slot_ae_slot1_set, - Field_ftsf21ae_slot1_Slot_ae_slot1_set, - Field_ftsf22ae_slot1_Slot_ae_slot1_set, - Field_ftsf23ae_slot1_Slot_ae_slot1_set, - Field_ftsf24ae_slot1_Slot_ae_slot1_set, - Field_ftsf25ae_slot1_Slot_ae_slot1_set, - Field_ftsf26ae_slot1_Slot_ae_slot1_set, - Field_ftsf27ae_slot1_Slot_ae_slot1_set, - Field_ftsf28ae_slot1_Slot_ae_slot1_set, - Field_ftsf29ae_slot1_Slot_ae_slot1_set, - Field_ftsf30ae_slot1_Slot_ae_slot1_set, - Field_ftsf31ae_slot1_Slot_ae_slot1_set, - Field_ftsf32ae_slot1_Slot_ae_slot1_set, - Field_ftsf33ae_slot1_Slot_ae_slot1_set, - Field_ftsf34ae_slot1_Slot_ae_slot1_set, - Field_ftsf35ae_slot1_Slot_ae_slot1_set, - Field_ftsf36ae_slot1_Slot_ae_slot1_set, - Field_ftsf37ae_slot1_Slot_ae_slot1_set, - Field_ftsf38ae_slot1_Slot_ae_slot1_set, - Field_ftsf39ae_slot1_Slot_ae_slot1_set, - Field_ftsf40ae_slot1_Slot_ae_slot1_set, - Field_ftsf41ae_slot1_Slot_ae_slot1_set, - Field_ftsf42ae_slot1_Slot_ae_slot1_set, - Field_ftsf43ae_slot1_Slot_ae_slot1_set, - Field_ftsf44ae_slot1_Slot_ae_slot1_set, - Field_ftsf45ae_slot1_Slot_ae_slot1_set, - Field_ftsf46ae_slot1_Slot_ae_slot1_set, - Field_ftsf47ae_slot1_Slot_ae_slot1_set, - Field_ftsf48ae_slot1_Slot_ae_slot1_set, - Field_ftsf49ae_slot1_Slot_ae_slot1_set, - Field_ftsf50ae_slot1_Slot_ae_slot1_set, - Field_ftsf51ae_slot1_Slot_ae_slot1_set, - Field_ftsf52ae_slot1_Slot_ae_slot1_set, - Field_ftsf53ae_slot1_Slot_ae_slot1_set, - Field_ftsf54ae_slot1_Slot_ae_slot1_set, - Field_ftsf55ae_slot1_Slot_ae_slot1_set, - Field_ftsf56ae_slot1_Slot_ae_slot1_set, - Field_ftsf57ae_slot1_Slot_ae_slot1_set, - Field_ftsf58ae_slot1_Slot_ae_slot1_set, - Field_ftsf59ae_slot1_Slot_ae_slot1_set, - Field_ftsf60ae_slot1_Slot_ae_slot1_set, - Field_ftsf61ae_slot1_Slot_ae_slot1_set, - Field_ftsf63ae_slot1_Slot_ae_slot1_set, - Field_ftsf64ae_slot1_Slot_ae_slot1_set, - Field_ftsf66ae_slot1_Slot_ae_slot1_set, - Field_ftsf67ae_slot1_Slot_ae_slot1_set, - Field_ftsf69ae_slot1_Slot_ae_slot1_set, - Field_ftsf71ae_slot1_Slot_ae_slot1_set, - Field_ftsf72ae_slot1_Slot_ae_slot1_set, - Field_ftsf73ae_slot1_Slot_ae_slot1_set, - Field_ftsf75ae_slot1_Slot_ae_slot1_set, - Field_ftsf76ae_slot1_Slot_ae_slot1_set, - Field_ftsf77ae_slot1_Slot_ae_slot1_set, - Field_ftsf78ae_slot1_Slot_ae_slot1_set, - Field_ftsf79ae_slot1_Slot_ae_slot1_set, - Field_ftsf80ae_slot1_Slot_ae_slot1_set, - Field_ftsf81ae_slot1_Slot_ae_slot1_set, - Field_ftsf82ae_slot1_Slot_ae_slot1_set, - Field_ftsf84ae_slot1_Slot_ae_slot1_set, - Field_ftsf86ae_slot1_Slot_ae_slot1_set, - Field_ftsf87ae_slot1_Slot_ae_slot1_set, - Field_ftsf88ae_slot1_Slot_ae_slot1_set, - Field_ftsf89ae_slot1_Slot_ae_slot1_set, - Field_ftsf90ae_slot1_Slot_ae_slot1_set, - Field_ftsf91ae_slot1_Slot_ae_slot1_set, - Field_ftsf92ae_slot1_Slot_ae_slot1_set, - Field_ftsf94ae_slot1_Slot_ae_slot1_set, - Field_ftsf96ae_slot1_Slot_ae_slot1_set, - Field_ftsf97ae_slot1_Slot_ae_slot1_set, - Field_ftsf98ae_slot1_Slot_ae_slot1_set, - Field_ftsf99ae_slot1_Slot_ae_slot1_set, - Field_ftsf100ae_slot1_Slot_ae_slot1_set, - Field_ftsf101ae_slot1_Slot_ae_slot1_set, - Field_ftsf103ae_slot1_Slot_ae_slot1_set, - Field_ftsf104ae_slot1_Slot_ae_slot1_set, - Field_ftsf105ae_slot1_Slot_ae_slot1_set, - Field_ftsf106ae_slot1_Slot_ae_slot1_set, - Field_ftsf107ae_slot1_Slot_ae_slot1_set, - Field_ftsf108ae_slot1_Slot_ae_slot1_set, - Field_ftsf109ae_slot1_Slot_ae_slot1_set, - Field_ftsf110ae_slot1_Slot_ae_slot1_set, - Field_ftsf111ae_slot1_Slot_ae_slot1_set, - Field_ftsf112ae_slot1_Slot_ae_slot1_set, - Field_ftsf113ae_slot1_Slot_ae_slot1_set, - Field_ftsf114ae_slot1_Slot_ae_slot1_set, - Field_ftsf115ae_slot1_Slot_ae_slot1_set, - Field_ftsf116ae_slot1_Slot_ae_slot1_set, - Field_ftsf118ae_slot1_Slot_ae_slot1_set, - Field_ftsf119ae_slot1_Slot_ae_slot1_set, - Field_ftsf120ae_slot1_Slot_ae_slot1_set, - Field_ftsf122ae_slot1_Slot_ae_slot1_set, - Field_ftsf124ae_slot1_Slot_ae_slot1_set, - Field_ftsf125ae_slot1_Slot_ae_slot1_set, - Field_ftsf126ae_slot1_Slot_ae_slot1_set, - Field_ftsf127ae_slot1_Slot_ae_slot1_set, - Field_ftsf128ae_slot1_Slot_ae_slot1_set, - Field_ftsf129ae_slot1_Slot_ae_slot1_set, - Field_ftsf130ae_slot1_Slot_ae_slot1_set, - Field_ftsf131ae_slot1_Slot_ae_slot1_set, - Field_ftsf132ae_slot1_Slot_ae_slot1_set, - Field_ftsf133ae_slot1_Slot_ae_slot1_set, - Field_ftsf134ae_slot1_Slot_ae_slot1_set, - Field_ftsf135ae_slot1_Slot_ae_slot1_set, - Field_ftsf136ae_slot1_Slot_ae_slot1_set, - Field_ftsf137ae_slot1_Slot_ae_slot1_set, - Field_ftsf138ae_slot1_Slot_ae_slot1_set, - Field_ftsf139ae_slot1_Slot_ae_slot1_set, - Field_ftsf140ae_slot1_Slot_ae_slot1_set, - Field_ftsf141ae_slot1_Slot_ae_slot1_set, - Field_ftsf142ae_slot1_Slot_ae_slot1_set, - Field_ftsf143ae_slot1_Slot_ae_slot1_set, - Field_ftsf144ae_slot1_Slot_ae_slot1_set, - Field_ftsf145ae_slot1_Slot_ae_slot1_set, - Field_ftsf146ae_slot1_Slot_ae_slot1_set, - Field_ftsf147ae_slot1_Slot_ae_slot1_set, - Field_ftsf148ae_slot1_Slot_ae_slot1_set, - Field_ftsf149ae_slot1_Slot_ae_slot1_set, - Field_ftsf150ae_slot1_Slot_ae_slot1_set, - Field_ftsf151ae_slot1_Slot_ae_slot1_set, - Field_ftsf152ae_slot1_Slot_ae_slot1_set, - Field_ftsf153ae_slot1_Slot_ae_slot1_set, - Field_ftsf154ae_slot1_Slot_ae_slot1_set, - Field_ftsf155ae_slot1_Slot_ae_slot1_set, - Field_ftsf156ae_slot1_Slot_ae_slot1_set, - Field_ftsf157ae_slot1_Slot_ae_slot1_set, - Field_ftsf158ae_slot1_Slot_ae_slot1_set, - Field_ftsf159ae_slot1_Slot_ae_slot1_set, - Field_ftsf160ae_slot1_Slot_ae_slot1_set, - Field_ftsf161ae_slot1_Slot_ae_slot1_set, - Field_ftsf162ae_slot1_Slot_ae_slot1_set, - Field_ftsf163ae_slot1_Slot_ae_slot1_set, - Field_ftsf164ae_slot1_Slot_ae_slot1_set, - Field_ftsf165ae_slot1_Slot_ae_slot1_set, - Field_ftsf166ae_slot1_Slot_ae_slot1_set, - Field_ftsf167ae_slot1_Slot_ae_slot1_set, - Field_ftsf168ae_slot1_Slot_ae_slot1_set, - Field_ftsf169ae_slot1_Slot_ae_slot1_set, - Field_ftsf170ae_slot1_Slot_ae_slot1_set, - Field_ftsf171ae_slot1_Slot_ae_slot1_set, - Field_ftsf172ae_slot1_Slot_ae_slot1_set, - Field_ftsf173ae_slot1_Slot_ae_slot1_set, - Field_ftsf174ae_slot1_Slot_ae_slot1_set, - Field_ftsf175ae_slot1_Slot_ae_slot1_set, - Field_ftsf176ae_slot1_Slot_ae_slot1_set, - Field_ftsf177ae_slot1_Slot_ae_slot1_set, - Field_ftsf178ae_slot1_Slot_ae_slot1_set, - Field_ftsf179ae_slot1_Slot_ae_slot1_set, - Field_ftsf180ae_slot1_Slot_ae_slot1_set, - Field_ftsf181ae_slot1_Slot_ae_slot1_set, - Field_ftsf182ae_slot1_Slot_ae_slot1_set, - Field_ftsf183ae_slot1_Slot_ae_slot1_set, - Field_ftsf184ae_slot1_Slot_ae_slot1_set, - Field_ftsf185ae_slot1_Slot_ae_slot1_set, - Field_ftsf186ae_slot1_Slot_ae_slot1_set, - Field_ftsf187ae_slot1_Slot_ae_slot1_set, - Field_ftsf188ae_slot1_Slot_ae_slot1_set, - Field_ftsf189ae_slot1_Slot_ae_slot1_set, - Field_ftsf190ae_slot1_Slot_ae_slot1_set, - Field_ftsf191ae_slot1_Slot_ae_slot1_set, - Field_ftsf192ae_slot1_Slot_ae_slot1_set, - Field_ftsf193ae_slot1_Slot_ae_slot1_set, - Field_ftsf194ae_slot1_Slot_ae_slot1_set, - Field_ftsf195ae_slot1_Slot_ae_slot1_set, - Field_ftsf196ae_slot1_Slot_ae_slot1_set, - Field_ftsf197ae_slot1_Slot_ae_slot1_set, - Field_ftsf198ae_slot1_Slot_ae_slot1_set, - Field_ftsf199ae_slot1_Slot_ae_slot1_set, - Field_ftsf200ae_slot1_Slot_ae_slot1_set, - Field_ftsf201ae_slot1_Slot_ae_slot1_set, - Field_ftsf202ae_slot1_Slot_ae_slot1_set, - Field_ftsf203ae_slot1_Slot_ae_slot1_set, - Field_ftsf204ae_slot1_Slot_ae_slot1_set, - Field_ftsf205ae_slot1_Slot_ae_slot1_set, - Field_ftsf206ae_slot1_Slot_ae_slot1_set, - Field_ftsf207ae_slot1_Slot_ae_slot1_set, - Field_ftsf208_Slot_ae_slot1_set, - Field_ftsf209ae_slot1_Slot_ae_slot1_set, - Field_ftsf210ae_slot1_Slot_ae_slot1_set, - Field_ftsf211ae_slot1_Slot_ae_slot1_set, - Field_ftsf330ae_slot1_Slot_ae_slot1_set, - Field_ftsf332ae_slot1_Slot_ae_slot1_set, - Field_ftsf334ae_slot1_Slot_ae_slot1_set, - Field_ftsf336ae_slot1_Slot_ae_slot1_set, - Field_ftsf337ae_slot1_Slot_ae_slot1_set, - Field_ftsf338_Slot_ae_slot1_set, - Field_ftsf339ae_slot1_Slot_ae_slot1_set, - Field_ftsf340_Slot_ae_slot1_set, - Field_ftsf341ae_slot1_Slot_ae_slot1_set, - Field_ftsf342ae_slot1_Slot_ae_slot1_set, - Field_ftsf343ae_slot1_Slot_ae_slot1_set, - Field_ftsf344ae_slot1_Slot_ae_slot1_set, - Field_ftsf346ae_slot1_Slot_ae_slot1_set, - Field_ftsf347_Slot_ae_slot1_set, - Field_ftsf348ae_slot1_Slot_ae_slot1_set, - Field_ftsf349ae_slot1_Slot_ae_slot1_set, - Field_ftsf350ae_slot1_Slot_ae_slot1_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_get_field_fn -Slot_ae_slot0_get_field_fns[] = { - Field_t_Slot_ae_slot0_get, - 0, - Field_bbi_Slot_ae_slot0_get, - Field_imm12_Slot_ae_slot0_get, - Field_imm8_Slot_ae_slot0_get, - Field_s_Slot_ae_slot0_get, - Field_imm12b_Slot_ae_slot0_get, - Field_imm16_Slot_ae_slot0_get, - 0, - 0, - Field_offset_Slot_ae_slot0_get, - 0, - 0, - Field_op2_Slot_ae_slot0_get, - Field_r_Slot_ae_slot0_get, - 0, - 0, - Field_sae_Slot_ae_slot0_get, - Field_sal_Slot_ae_slot0_get, - Field_sargt_Slot_ae_slot0_get, - 0, - Field_sas_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_get, - 0, - 0, - Field_s8_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_get, - Field_ae_samt_s_t_Slot_ae_slot0_get, - Field_ae_r20_Slot_ae_slot0_get, - Field_ae_r10_Slot_ae_slot0_get, - Field_ae_s20_Slot_ae_slot0_get, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_get, - Field_ftsf212ae_slot0_Slot_ae_slot0_get, - Field_ftsf213ae_slot0_Slot_ae_slot0_get, - Field_ftsf214ae_slot0_Slot_ae_slot0_get, - Field_ftsf215ae_slot0_Slot_ae_slot0_get, - Field_ftsf216ae_slot0_Slot_ae_slot0_get, - Field_ftsf217_Slot_ae_slot0_get, - Field_ftsf218ae_slot0_Slot_ae_slot0_get, - Field_ftsf219ae_slot0_Slot_ae_slot0_get, - Field_ftsf220ae_slot0_Slot_ae_slot0_get, - Field_ftsf221ae_slot0_Slot_ae_slot0_get, - Field_ftsf222ae_slot0_Slot_ae_slot0_get, - Field_ftsf223ae_slot0_Slot_ae_slot0_get, - Field_ftsf224ae_slot0_Slot_ae_slot0_get, - Field_ftsf225ae_slot0_Slot_ae_slot0_get, - Field_ftsf226ae_slot0_Slot_ae_slot0_get, - Field_ftsf227ae_slot0_Slot_ae_slot0_get, - Field_ftsf228ae_slot0_Slot_ae_slot0_get, - Field_ftsf229ae_slot0_Slot_ae_slot0_get, - Field_ftsf230ae_slot0_Slot_ae_slot0_get, - Field_ftsf231ae_slot0_Slot_ae_slot0_get, - Field_ftsf232ae_slot0_Slot_ae_slot0_get, - Field_ftsf233ae_slot0_Slot_ae_slot0_get, - Field_ftsf234ae_slot0_Slot_ae_slot0_get, - Field_ftsf235ae_slot0_Slot_ae_slot0_get, - Field_ftsf236ae_slot0_Slot_ae_slot0_get, - Field_ftsf237ae_slot0_Slot_ae_slot0_get, - Field_ftsf238ae_slot0_Slot_ae_slot0_get, - Field_ftsf239ae_slot0_Slot_ae_slot0_get, - Field_ftsf240ae_slot0_Slot_ae_slot0_get, - Field_ftsf241ae_slot0_Slot_ae_slot0_get, - Field_ftsf242ae_slot0_Slot_ae_slot0_get, - Field_ftsf243ae_slot0_Slot_ae_slot0_get, - Field_ftsf244ae_slot0_Slot_ae_slot0_get, - Field_ftsf245ae_slot0_Slot_ae_slot0_get, - Field_ftsf246ae_slot0_Slot_ae_slot0_get, - Field_ftsf247ae_slot0_Slot_ae_slot0_get, - Field_ftsf248ae_slot0_Slot_ae_slot0_get, - Field_ftsf249ae_slot0_Slot_ae_slot0_get, - Field_ftsf250ae_slot0_Slot_ae_slot0_get, - Field_ftsf251ae_slot0_Slot_ae_slot0_get, - Field_ftsf252ae_slot0_Slot_ae_slot0_get, - Field_ftsf253ae_slot0_Slot_ae_slot0_get, - Field_ftsf254ae_slot0_Slot_ae_slot0_get, - Field_ftsf255ae_slot0_Slot_ae_slot0_get, - Field_ftsf256ae_slot0_Slot_ae_slot0_get, - Field_ftsf257ae_slot0_Slot_ae_slot0_get, - Field_ftsf258ae_slot0_Slot_ae_slot0_get, - Field_ftsf259ae_slot0_Slot_ae_slot0_get, - Field_ftsf260ae_slot0_Slot_ae_slot0_get, - Field_ftsf261ae_slot0_Slot_ae_slot0_get, - Field_ftsf262ae_slot0_Slot_ae_slot0_get, - Field_ftsf263ae_slot0_Slot_ae_slot0_get, - Field_ftsf264ae_slot0_Slot_ae_slot0_get, - Field_ftsf265ae_slot0_Slot_ae_slot0_get, - Field_ftsf266ae_slot0_Slot_ae_slot0_get, - Field_ftsf267ae_slot0_Slot_ae_slot0_get, - Field_ftsf268ae_slot0_Slot_ae_slot0_get, - Field_ftsf269ae_slot0_Slot_ae_slot0_get, - Field_ftsf270ae_slot0_Slot_ae_slot0_get, - Field_ftsf271ae_slot0_Slot_ae_slot0_get, - Field_ftsf272ae_slot0_Slot_ae_slot0_get, - Field_ftsf273ae_slot0_Slot_ae_slot0_get, - Field_ftsf274ae_slot0_Slot_ae_slot0_get, - Field_ftsf275ae_slot0_Slot_ae_slot0_get, - Field_ftsf276ae_slot0_Slot_ae_slot0_get, - Field_ftsf277ae_slot0_Slot_ae_slot0_get, - Field_ftsf278ae_slot0_Slot_ae_slot0_get, - Field_ftsf279ae_slot0_Slot_ae_slot0_get, - Field_ftsf281ae_slot0_Slot_ae_slot0_get, - Field_ftsf282ae_slot0_Slot_ae_slot0_get, - Field_ftsf283ae_slot0_Slot_ae_slot0_get, - Field_ftsf284ae_slot0_Slot_ae_slot0_get, - Field_ftsf286ae_slot0_Slot_ae_slot0_get, - Field_ftsf288ae_slot0_Slot_ae_slot0_get, - Field_ftsf290ae_slot0_Slot_ae_slot0_get, - Field_ftsf292ae_slot0_Slot_ae_slot0_get, - Field_ftsf293_Slot_ae_slot0_get, - Field_ftsf294ae_slot0_Slot_ae_slot0_get, - Field_ftsf295ae_slot0_Slot_ae_slot0_get, - Field_ftsf296ae_slot0_Slot_ae_slot0_get, - Field_ftsf297ae_slot0_Slot_ae_slot0_get, - Field_ftsf298ae_slot0_Slot_ae_slot0_get, - Field_ftsf299ae_slot0_Slot_ae_slot0_get, - Field_ftsf300ae_slot0_Slot_ae_slot0_get, - Field_ftsf301ae_slot0_Slot_ae_slot0_get, - Field_ftsf302ae_slot0_Slot_ae_slot0_get, - Field_ftsf303ae_slot0_Slot_ae_slot0_get, - Field_ftsf304ae_slot0_Slot_ae_slot0_get, - Field_ftsf306ae_slot0_Slot_ae_slot0_get, - Field_ftsf308ae_slot0_Slot_ae_slot0_get, - Field_ftsf309ae_slot0_Slot_ae_slot0_get, - Field_ftsf310ae_slot0_Slot_ae_slot0_get, - Field_ftsf311ae_slot0_Slot_ae_slot0_get, - Field_ftsf312ae_slot0_Slot_ae_slot0_get, - Field_ftsf313ae_slot0_Slot_ae_slot0_get, - Field_ftsf314ae_slot0_Slot_ae_slot0_get, - Field_ftsf315ae_slot0_Slot_ae_slot0_get, - Field_ftsf316ae_slot0_Slot_ae_slot0_get, - Field_ftsf317ae_slot0_Slot_ae_slot0_get, - Field_ftsf318ae_slot0_Slot_ae_slot0_get, - Field_ftsf319_Slot_ae_slot0_get, - Field_ftsf320ae_slot0_Slot_ae_slot0_get, - Field_ftsf321_Slot_ae_slot0_get, - Field_ftsf322ae_slot0_Slot_ae_slot0_get, - Field_ftsf323ae_slot0_Slot_ae_slot0_get, - Field_ftsf324ae_slot0_Slot_ae_slot0_get, - Field_ftsf325ae_slot0_Slot_ae_slot0_get, - Field_ftsf326ae_slot0_Slot_ae_slot0_get, - Field_ftsf328ae_slot0_Slot_ae_slot0_get, - Field_ftsf329ae_slot0_Slot_ae_slot0_get, - Field_ftsf352ae_slot0_Slot_ae_slot0_get, - Field_ftsf353_Slot_ae_slot0_get, - Field_ftsf354ae_slot0_Slot_ae_slot0_get, - Field_ftsf356ae_slot0_Slot_ae_slot0_get, - Field_ftsf357_Slot_ae_slot0_get, - Field_ftsf358ae_slot0_Slot_ae_slot0_get, - Field_ftsf359ae_slot0_Slot_ae_slot0_get, - Field_ftsf360ae_slot0_Slot_ae_slot0_get, - Field_ftsf361ae_slot0_Slot_ae_slot0_get, - Field_ftsf362ae_slot0_Slot_ae_slot0_get, - Field_ftsf364ae_slot0_Slot_ae_slot0_get, - Field_ftsf365ae_slot0_Slot_ae_slot0_get, - Field_ftsf366ae_slot0_Slot_ae_slot0_get, - Field_ftsf368ae_slot0_Slot_ae_slot0_get, - Field_ftsf369ae_slot0_Slot_ae_slot0_get, - Implicit_Field_ar0_get, - Implicit_Field_ar4_get, - Implicit_Field_ar8_get, - Implicit_Field_ar12_get, - Implicit_Field_bt16_get, - Implicit_Field_bs16_get, - Implicit_Field_br16_get, - Implicit_Field_brall_get -}; - -static xtensa_set_field_fn -Slot_ae_slot0_set_field_fns[] = { - Field_t_Slot_ae_slot0_set, - 0, - Field_bbi_Slot_ae_slot0_set, - Field_imm12_Slot_ae_slot0_set, - Field_imm8_Slot_ae_slot0_set, - Field_s_Slot_ae_slot0_set, - Field_imm12b_Slot_ae_slot0_set, - Field_imm16_Slot_ae_slot0_set, - 0, - 0, - Field_offset_Slot_ae_slot0_set, - 0, - 0, - Field_op2_Slot_ae_slot0_set, - Field_r_Slot_ae_slot0_set, - 0, - 0, - Field_sae_Slot_ae_slot0_set, - Field_sal_Slot_ae_slot0_set, - Field_sargt_Slot_ae_slot0_set, - 0, - Field_sas_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_s4_Slot_ae_slot0_set, - 0, - 0, - Field_s8_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - Field_ae_r32_Slot_ae_slot0_set, - Field_ae_samt_s_t_Slot_ae_slot0_set, - Field_ae_r20_Slot_ae_slot0_set, - Field_ae_r10_Slot_ae_slot0_set, - Field_ae_s20_Slot_ae_slot0_set, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - Field_op0_s4_Slot_ae_slot0_set, - Field_ftsf212ae_slot0_Slot_ae_slot0_set, - Field_ftsf213ae_slot0_Slot_ae_slot0_set, - Field_ftsf214ae_slot0_Slot_ae_slot0_set, - Field_ftsf215ae_slot0_Slot_ae_slot0_set, - Field_ftsf216ae_slot0_Slot_ae_slot0_set, - Field_ftsf217_Slot_ae_slot0_set, - Field_ftsf218ae_slot0_Slot_ae_slot0_set, - Field_ftsf219ae_slot0_Slot_ae_slot0_set, - Field_ftsf220ae_slot0_Slot_ae_slot0_set, - Field_ftsf221ae_slot0_Slot_ae_slot0_set, - Field_ftsf222ae_slot0_Slot_ae_slot0_set, - Field_ftsf223ae_slot0_Slot_ae_slot0_set, - Field_ftsf224ae_slot0_Slot_ae_slot0_set, - Field_ftsf225ae_slot0_Slot_ae_slot0_set, - Field_ftsf226ae_slot0_Slot_ae_slot0_set, - Field_ftsf227ae_slot0_Slot_ae_slot0_set, - Field_ftsf228ae_slot0_Slot_ae_slot0_set, - Field_ftsf229ae_slot0_Slot_ae_slot0_set, - Field_ftsf230ae_slot0_Slot_ae_slot0_set, - Field_ftsf231ae_slot0_Slot_ae_slot0_set, - Field_ftsf232ae_slot0_Slot_ae_slot0_set, - Field_ftsf233ae_slot0_Slot_ae_slot0_set, - Field_ftsf234ae_slot0_Slot_ae_slot0_set, - Field_ftsf235ae_slot0_Slot_ae_slot0_set, - Field_ftsf236ae_slot0_Slot_ae_slot0_set, - Field_ftsf237ae_slot0_Slot_ae_slot0_set, - Field_ftsf238ae_slot0_Slot_ae_slot0_set, - Field_ftsf239ae_slot0_Slot_ae_slot0_set, - Field_ftsf240ae_slot0_Slot_ae_slot0_set, - Field_ftsf241ae_slot0_Slot_ae_slot0_set, - Field_ftsf242ae_slot0_Slot_ae_slot0_set, - Field_ftsf243ae_slot0_Slot_ae_slot0_set, - Field_ftsf244ae_slot0_Slot_ae_slot0_set, - Field_ftsf245ae_slot0_Slot_ae_slot0_set, - Field_ftsf246ae_slot0_Slot_ae_slot0_set, - Field_ftsf247ae_slot0_Slot_ae_slot0_set, - Field_ftsf248ae_slot0_Slot_ae_slot0_set, - Field_ftsf249ae_slot0_Slot_ae_slot0_set, - Field_ftsf250ae_slot0_Slot_ae_slot0_set, - Field_ftsf251ae_slot0_Slot_ae_slot0_set, - Field_ftsf252ae_slot0_Slot_ae_slot0_set, - Field_ftsf253ae_slot0_Slot_ae_slot0_set, - Field_ftsf254ae_slot0_Slot_ae_slot0_set, - Field_ftsf255ae_slot0_Slot_ae_slot0_set, - Field_ftsf256ae_slot0_Slot_ae_slot0_set, - Field_ftsf257ae_slot0_Slot_ae_slot0_set, - Field_ftsf258ae_slot0_Slot_ae_slot0_set, - Field_ftsf259ae_slot0_Slot_ae_slot0_set, - Field_ftsf260ae_slot0_Slot_ae_slot0_set, - Field_ftsf261ae_slot0_Slot_ae_slot0_set, - Field_ftsf262ae_slot0_Slot_ae_slot0_set, - Field_ftsf263ae_slot0_Slot_ae_slot0_set, - Field_ftsf264ae_slot0_Slot_ae_slot0_set, - Field_ftsf265ae_slot0_Slot_ae_slot0_set, - Field_ftsf266ae_slot0_Slot_ae_slot0_set, - Field_ftsf267ae_slot0_Slot_ae_slot0_set, - Field_ftsf268ae_slot0_Slot_ae_slot0_set, - Field_ftsf269ae_slot0_Slot_ae_slot0_set, - Field_ftsf270ae_slot0_Slot_ae_slot0_set, - Field_ftsf271ae_slot0_Slot_ae_slot0_set, - Field_ftsf272ae_slot0_Slot_ae_slot0_set, - Field_ftsf273ae_slot0_Slot_ae_slot0_set, - Field_ftsf274ae_slot0_Slot_ae_slot0_set, - Field_ftsf275ae_slot0_Slot_ae_slot0_set, - Field_ftsf276ae_slot0_Slot_ae_slot0_set, - Field_ftsf277ae_slot0_Slot_ae_slot0_set, - Field_ftsf278ae_slot0_Slot_ae_slot0_set, - Field_ftsf279ae_slot0_Slot_ae_slot0_set, - Field_ftsf281ae_slot0_Slot_ae_slot0_set, - Field_ftsf282ae_slot0_Slot_ae_slot0_set, - Field_ftsf283ae_slot0_Slot_ae_slot0_set, - Field_ftsf284ae_slot0_Slot_ae_slot0_set, - Field_ftsf286ae_slot0_Slot_ae_slot0_set, - Field_ftsf288ae_slot0_Slot_ae_slot0_set, - Field_ftsf290ae_slot0_Slot_ae_slot0_set, - Field_ftsf292ae_slot0_Slot_ae_slot0_set, - Field_ftsf293_Slot_ae_slot0_set, - Field_ftsf294ae_slot0_Slot_ae_slot0_set, - Field_ftsf295ae_slot0_Slot_ae_slot0_set, - Field_ftsf296ae_slot0_Slot_ae_slot0_set, - Field_ftsf297ae_slot0_Slot_ae_slot0_set, - Field_ftsf298ae_slot0_Slot_ae_slot0_set, - Field_ftsf299ae_slot0_Slot_ae_slot0_set, - Field_ftsf300ae_slot0_Slot_ae_slot0_set, - Field_ftsf301ae_slot0_Slot_ae_slot0_set, - Field_ftsf302ae_slot0_Slot_ae_slot0_set, - Field_ftsf303ae_slot0_Slot_ae_slot0_set, - Field_ftsf304ae_slot0_Slot_ae_slot0_set, - Field_ftsf306ae_slot0_Slot_ae_slot0_set, - Field_ftsf308ae_slot0_Slot_ae_slot0_set, - Field_ftsf309ae_slot0_Slot_ae_slot0_set, - Field_ftsf310ae_slot0_Slot_ae_slot0_set, - Field_ftsf311ae_slot0_Slot_ae_slot0_set, - Field_ftsf312ae_slot0_Slot_ae_slot0_set, - Field_ftsf313ae_slot0_Slot_ae_slot0_set, - Field_ftsf314ae_slot0_Slot_ae_slot0_set, - Field_ftsf315ae_slot0_Slot_ae_slot0_set, - Field_ftsf316ae_slot0_Slot_ae_slot0_set, - Field_ftsf317ae_slot0_Slot_ae_slot0_set, - Field_ftsf318ae_slot0_Slot_ae_slot0_set, - Field_ftsf319_Slot_ae_slot0_set, - Field_ftsf320ae_slot0_Slot_ae_slot0_set, - Field_ftsf321_Slot_ae_slot0_set, - Field_ftsf322ae_slot0_Slot_ae_slot0_set, - Field_ftsf323ae_slot0_Slot_ae_slot0_set, - Field_ftsf324ae_slot0_Slot_ae_slot0_set, - Field_ftsf325ae_slot0_Slot_ae_slot0_set, - Field_ftsf326ae_slot0_Slot_ae_slot0_set, - Field_ftsf328ae_slot0_Slot_ae_slot0_set, - Field_ftsf329ae_slot0_Slot_ae_slot0_set, - Field_ftsf352ae_slot0_Slot_ae_slot0_set, - Field_ftsf353_Slot_ae_slot0_set, - Field_ftsf354ae_slot0_Slot_ae_slot0_set, - Field_ftsf356ae_slot0_Slot_ae_slot0_set, - Field_ftsf357_Slot_ae_slot0_set, - Field_ftsf358ae_slot0_Slot_ae_slot0_set, - Field_ftsf359ae_slot0_Slot_ae_slot0_set, - Field_ftsf360ae_slot0_Slot_ae_slot0_set, - Field_ftsf361ae_slot0_Slot_ae_slot0_set, - Field_ftsf362ae_slot0_Slot_ae_slot0_set, - Field_ftsf364ae_slot0_Slot_ae_slot0_set, - Field_ftsf365ae_slot0_Slot_ae_slot0_set, - Field_ftsf366ae_slot0_Slot_ae_slot0_set, - Field_ftsf368ae_slot0_Slot_ae_slot0_set, - Field_ftsf369ae_slot0_Slot_ae_slot0_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set, - Implicit_Field_set -}; - -static xtensa_slot_internal slots[] = { - { "Inst", "x24", 0, - Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, - Slot_inst_get_field_fns, Slot_inst_set_field_fns, - Slot_inst_decode, "nop" }, - { "Inst16a", "x16a", 0, - Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, - Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, - Slot_inst16a_decode, "" }, - { "Inst16b", "x16b", 0, - Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, - Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, - Slot_inst16b_decode, "nop.n" }, - { "ae_slot1", "ae_format", 1, - Slot_ae_format_Format_ae_slot1_31_get, Slot_ae_format_Format_ae_slot1_31_set, - Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, - Slot_ae_slot1_decode, "nop" }, - { "ae_slot0", "ae_format", 0, - Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, - Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, - Slot_ae_slot0_decode, "nop" } -}; - - -/* Instruction formats. */ - -static void -Format_x24_encode (xtensa_insnbuf insn) -{ - insn[0] = 0; - insn[1] = 0; -} - -static void -Format_x16a_encode (xtensa_insnbuf insn) -{ - insn[0] = 0x8; - insn[1] = 0; -} - -static void -Format_x16b_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xc; - insn[1] = 0; -} - -static void -Format_ae_format_encode (xtensa_insnbuf insn) -{ - insn[0] = 0xf; - insn[1] = 0; -} - -static int Format_x24_slots[] = { 0 }; - -static int Format_x16a_slots[] = { 1 }; - -static int Format_x16b_slots[] = { 2 }; - -static int Format_ae_format_slots[] = { 4, 3 }; - -static xtensa_format_internal formats[] = { - { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, - { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, - { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } -}; - - -static int -format_decoder (const xtensa_insnbuf insn) -{ - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) - return 0; /* x24 */ - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) - return 1; /* x16a */ - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) - return 2; /* x16b */ - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0xffc00000) == 0) - return 3; /* ae_format */ - return -1; -} - -static int length_table[256] = { - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 3, - 2, - 2, - 2, - 2, - 2, - 2, - -1, - 8 -}; - -static int -length_decoder (const unsigned char *insn) -{ - int l = insn[0]; - return length_table[l]; -} - - -/* Top-level ISA structure. */ - -xtensa_isa_internal xtensa_modules = { - 0 /* little-endian */, - 8 /* insn_size */, 0, - 4, formats, format_decoder, length_decoder, - 5, slots, - 389 /* num_fields */, - 454, operands, - 588, iclasses, - 656, opcodes, 0, - 8, regfiles, - NUM_STATES, states, 0, - NUM_SYSREGS, sysregs, 0, - { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, - 2, interfaces, 0, - 4, funcUnits, 0 -}; diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index 8f844cf9e2..c8626a8c02 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -23,7 +23,7 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \ xtensa/config/core-isa.h \ xtensa/config/core-matmap.h tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ - sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c + sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc # # Fix up known issues in the xtensa-modules.c # @@ -35,7 +35,7 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \ -e '/^#include "ansidecl.h"/d' \ -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \ -e 's/#include /#include "xtensa-isa.h"/' \ - > "$TARGET"/xtensa-modules.inc.c + > "$TARGET"/xtensa-modules.c.inc cat < "${TARGET}.c" #include "qemu/osdep.h" @@ -49,13 +49,13 @@ cat < "${TARGET}.c" #include "overlay_tool.h" #define xtensa_modules xtensa_modules_$NAME -#include "core-$NAME/xtensa-modules.inc.c" +#include "core-$NAME/xtensa-modules.c.inc" static XtensaConfig $NAME __attribute__((unused)) = { .name = "$NAME", .gdb_regmap = { .reg = { -#include "core-$NAME/gdb-config.inc.c" +#include "core-$NAME/gdb-config.c.inc" } }, .isa_internal = &xtensa_modules, diff --git a/tcg/README b/tcg/README index a64f67809b..2f051e5c97 100644 --- a/tcg/README +++ b/tcg/README @@ -652,7 +652,7 @@ function tcg_gen_xxx(args). 4) Backend -tcg-target.h contains the target specific definitions. tcg-target.inc.c +tcg-target.h contains the target specific definitions. tcg-target.c.inc contains the target specific code; it is #included by tcg/tcg.c, rather than being a standalone C file. diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc new file mode 100644 index 0000000000..948c35d825 --- /dev/null +++ b/tcg/aarch64/tcg-target.c.inc @@ -0,0 +1,2973 @@ +/* + * Initial TCG Implementation for aarch64 + * + * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH + * Written by Claudio Fontana + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + */ + +#include "../tcg-pool.c.inc" +#include "qemu/bitops.h" + +/* We're going to re-use TCGType in setting of the SF bit, which controls + the size of the operation performed. If we know the values match, it + makes things much cleaner. */ +QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1); + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", + "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp", + + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31", +}; +#endif /* CONFIG_DEBUG_TCG */ + +static const int tcg_target_reg_alloc_order[] = { + TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, + TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, + TCG_REG_X28, /* we will reserve this for guest_base if configured */ + + TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, + TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15, + TCG_REG_X16, TCG_REG_X17, + + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, + TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, + + /* X18 reserved by system */ + /* X19 reserved for AREG0 */ + /* X29 reserved as fp */ + /* X30 reserved as temporary */ + + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + /* V8 - V15 are call-saved, and skipped. */ + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, +}; + +static const int tcg_target_call_iarg_regs[8] = { + TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, + TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 +}; +static const int tcg_target_call_oarg_regs[1] = { + TCG_REG_X0 +}; + +#define TCG_REG_TMP TCG_REG_X30 +#define TCG_VEC_TMP TCG_REG_V31 + +#ifndef CONFIG_SOFTMMU +/* Note that XZR cannot be encoded in the address base register slot, + as that actaully encodes SP. So if we need to zero-extend the guest + address, via the address index register slot, we need to load even + a zero guest base into a register. */ +#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32) +#define TCG_REG_GUEST_BASE TCG_REG_X28 +#endif + +static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + ptrdiff_t offset = target - code_ptr; + if (offset == sextract64(offset, 0, 26)) { + /* read instruction, mask away previous PC_REL26 parameter contents, + set the proper offset, then write back the instruction. */ + *code_ptr = deposit32(*code_ptr, 0, 26, offset); + return true; + } + return false; +} + +static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + ptrdiff_t offset = target - code_ptr; + if (offset == sextract64(offset, 0, 19)) { + *code_ptr = deposit32(*code_ptr, 5, 19, offset); + return true; + } + return false; +} + +static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(addend == 0); + switch (type) { + case R_AARCH64_JUMP26: + case R_AARCH64_CALL26: + return reloc_pc26(code_ptr, (tcg_insn_unit *)value); + case R_AARCH64_CONDBR19: + return reloc_pc19(code_ptr, (tcg_insn_unit *)value); + default: + g_assert_not_reached(); + } +} + +#define TCG_CT_CONST_AIMM 0x100 +#define TCG_CT_CONST_LIMM 0x200 +#define TCG_CT_CONST_ZERO 0x400 +#define TCG_CT_CONST_MONE 0x800 +#define TCG_CT_CONST_ORRI 0x1000 +#define TCG_CT_CONST_ANDI 0x2000 + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': /* general registers */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= 0xffffffffu; + break; + case 'w': /* advsimd registers */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= 0xffffffff00000000ull; + break; + case 'l': /* qemu_ld / qemu_st address, data_reg */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffffu; +#ifdef CONFIG_SOFTMMU + /* x0 and x1 will be overwritten when reading the tlb entry, + and x2, and x3 for helper args, better to avoid using them. */ + tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); +#endif + break; + case 'A': /* Valid for arithmetic immediate (positive or negative). */ + ct->ct |= TCG_CT_CONST_AIMM; + break; + case 'L': /* Valid for logical immediate. */ + ct->ct |= TCG_CT_CONST_LIMM; + break; + case 'M': /* minus one */ + ct->ct |= TCG_CT_CONST_MONE; + break; + case 'O': /* vector orr/bic immediate */ + ct->ct |= TCG_CT_CONST_ORRI; + break; + case 'N': /* vector orr/bic immediate, inverted */ + ct->ct |= TCG_CT_CONST_ANDI; + break; + case 'Z': /* zero */ + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* Match a constant valid for addition (12-bit, optionally shifted). */ +static inline bool is_aimm(uint64_t val) +{ + return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0; +} + +/* Match a constant valid for logical operations. */ +static inline bool is_limm(uint64_t val) +{ + /* Taking a simplified view of the logical immediates for now, ignoring + the replication that can happen across the field. Match bit patterns + of the forms + 0....01....1 + 0..01..10..0 + and their inverses. */ + + /* Make things easier below, by testing the form with msb clear. */ + if ((int64_t)val < 0) { + val = ~val; + } + if (val == 0) { + return false; + } + val += val & -val; + return (val & (val - 1)) == 0; +} + +/* Return true if v16 is a valid 16-bit shifted immediate. */ +static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) +{ + if (v16 == (v16 & 0xff)) { + *cmode = 0x8; + *imm8 = v16 & 0xff; + return true; + } else if (v16 == (v16 & 0xff00)) { + *cmode = 0xa; + *imm8 = v16 >> 8; + return true; + } + return false; +} + +/* Return true if v32 is a valid 32-bit shifted immediate. */ +static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 == (v32 & 0xff)) { + *cmode = 0x0; + *imm8 = v32 & 0xff; + return true; + } else if (v32 == (v32 & 0xff00)) { + *cmode = 0x2; + *imm8 = (v32 >> 8) & 0xff; + return true; + } else if (v32 == (v32 & 0xff0000)) { + *cmode = 0x4; + *imm8 = (v32 >> 16) & 0xff; + return true; + } else if (v32 == (v32 & 0xff000000)) { + *cmode = 0x6; + *imm8 = v32 >> 24; + return true; + } + return false; +} + +/* Return true if v32 is a valid 32-bit shifting ones immediate. */ +static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) +{ + if ((v32 & 0xffff00ff) == 0xff) { + *cmode = 0xc; + *imm8 = (v32 >> 8) & 0xff; + return true; + } else if ((v32 & 0xff00ffff) == 0xffff) { + *cmode = 0xd; + *imm8 = (v32 >> 16) & 0xff; + return true; + } + return false; +} + +/* Return true if v32 is a valid float32 immediate. */ +static bool is_fimm32(uint32_t v32, int *cmode, int *imm8) +{ + if (extract32(v32, 0, 19) == 0 + && (extract32(v32, 25, 6) == 0x20 + || extract32(v32, 25, 6) == 0x1f)) { + *cmode = 0xf; + *imm8 = (extract32(v32, 31, 1) << 7) + | (extract32(v32, 25, 1) << 6) + | extract32(v32, 19, 6); + return true; + } + return false; +} + +/* Return true if v64 is a valid float64 immediate. */ +static bool is_fimm64(uint64_t v64, int *cmode, int *imm8) +{ + if (extract64(v64, 0, 48) == 0 + && (extract64(v64, 54, 9) == 0x100 + || extract64(v64, 54, 9) == 0x0ff)) { + *cmode = 0xf; + *imm8 = (extract64(v64, 63, 1) << 7) + | (extract64(v64, 54, 1) << 6) + | extract64(v64, 48, 6); + return true; + } + return false; +} + +/* + * Return non-zero if v32 can be formed by MOVI+ORR. + * Place the parameters for MOVI in (cmode, imm8). + * Return the cmode for ORR; the imm8 can be had via extraction from v32. + */ +static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) +{ + int i; + + for (i = 6; i > 0; i -= 2) { + /* Mask out one byte we can add with ORR. */ + uint32_t tmp = v32 & ~(0xffu << (i * 4)); + if (is_shimm32(tmp, cmode, imm8) || + is_soimm32(tmp, cmode, imm8)) { + break; + } + } + return i; +} + +/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ +static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) +{ + if (v32 == deposit32(v32, 16, 16, v32)) { + return is_shimm16(v32, cmode, imm8); + } else { + return is_shimm32(v32, cmode, imm8); + } +} + +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + + if (ct & TCG_CT_CONST) { + return 1; + } + if (type == TCG_TYPE_I32) { + val = (int32_t)val; + } + if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) { + return 1; + } + if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if ((ct & TCG_CT_CONST_MONE) && val == -1) { + return 1; + } + + switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { + case 0: + break; + case TCG_CT_CONST_ANDI: + val = ~val; + /* fallthru */ + case TCG_CT_CONST_ORRI: + if (val == deposit64(val, 32, 32, val)) { + int cmode, imm8; + return is_shimm1632(val, &cmode, &imm8); + } + break; + default: + /* Both bits should not be set for the same insn. */ + g_assert_not_reached(); + } + + return 0; +} + +enum aarch64_cond_code { + COND_EQ = 0x0, + COND_NE = 0x1, + COND_CS = 0x2, /* Unsigned greater or equal */ + COND_HS = COND_CS, /* ALIAS greater or equal */ + COND_CC = 0x3, /* Unsigned less than */ + COND_LO = COND_CC, /* ALIAS Lower */ + COND_MI = 0x4, /* Negative */ + COND_PL = 0x5, /* Zero or greater */ + COND_VS = 0x6, /* Overflow */ + COND_VC = 0x7, /* No overflow */ + COND_HI = 0x8, /* Unsigned greater than */ + COND_LS = 0x9, /* Unsigned less or equal */ + COND_GE = 0xa, + COND_LT = 0xb, + COND_GT = 0xc, + COND_LE = 0xd, + COND_AL = 0xe, + COND_NV = 0xf, /* behaves like COND_AL here */ +}; + +static const enum aarch64_cond_code tcg_cond_to_aarch64[] = { + [TCG_COND_EQ] = COND_EQ, + [TCG_COND_NE] = COND_NE, + [TCG_COND_LT] = COND_LT, + [TCG_COND_GE] = COND_GE, + [TCG_COND_LE] = COND_LE, + [TCG_COND_GT] = COND_GT, + /* unsigned */ + [TCG_COND_LTU] = COND_LO, + [TCG_COND_GTU] = COND_HI, + [TCG_COND_GEU] = COND_HS, + [TCG_COND_LEU] = COND_LS, +}; + +typedef enum { + LDST_ST = 0, /* store */ + LDST_LD = 1, /* load */ + LDST_LD_S_X = 2, /* load and sign-extend into Xt */ + LDST_LD_S_W = 3, /* load and sign-extend into Wt */ +} AArch64LdstType; + +/* We encode the format of the insn into the beginning of the name, so that + we can have the preprocessor help "typecheck" the insn vs the output + function. Arm didn't provide us with nice names for the formats, so we + use the section number of the architecture reference manual in which the + instruction group is described. */ +typedef enum { + /* Compare and branch (immediate). */ + I3201_CBZ = 0x34000000, + I3201_CBNZ = 0x35000000, + + /* Conditional branch (immediate). */ + I3202_B_C = 0x54000000, + + /* Unconditional branch (immediate). */ + I3206_B = 0x14000000, + I3206_BL = 0x94000000, + + /* Unconditional branch (register). */ + I3207_BR = 0xd61f0000, + I3207_BLR = 0xd63f0000, + I3207_RET = 0xd65f0000, + + /* AdvSIMD load/store single structure. */ + I3303_LD1R = 0x0d40c000, + + /* Load literal for loading the address at pc-relative offset */ + I3305_LDR = 0x58000000, + I3305_LDR_v64 = 0x5c000000, + I3305_LDR_v128 = 0x9c000000, + + /* Load/store register. Described here as 3.3.12, but the helper + that emits them can transform to 3.3.10 or 3.3.13. */ + I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30, + I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30, + I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30, + I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30, + + I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30, + I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30, + I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30, + I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30, + + I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30, + I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30, + + I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30, + I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30, + I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30, + + I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30, + I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30, + + I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30, + I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30, + + I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30, + I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30, + + I3312_TO_I3310 = 0x00200800, + I3312_TO_I3313 = 0x01000000, + + /* Load/store register pair instructions. */ + I3314_LDP = 0x28400000, + I3314_STP = 0x28000000, + + /* Add/subtract immediate instructions. */ + I3401_ADDI = 0x11000000, + I3401_ADDSI = 0x31000000, + I3401_SUBI = 0x51000000, + I3401_SUBSI = 0x71000000, + + /* Bitfield instructions. */ + I3402_BFM = 0x33000000, + I3402_SBFM = 0x13000000, + I3402_UBFM = 0x53000000, + + /* Extract instruction. */ + I3403_EXTR = 0x13800000, + + /* Logical immediate instructions. */ + I3404_ANDI = 0x12000000, + I3404_ORRI = 0x32000000, + I3404_EORI = 0x52000000, + + /* Move wide immediate instructions. */ + I3405_MOVN = 0x12800000, + I3405_MOVZ = 0x52800000, + I3405_MOVK = 0x72800000, + + /* PC relative addressing instructions. */ + I3406_ADR = 0x10000000, + I3406_ADRP = 0x90000000, + + /* Add/subtract shifted register instructions (without a shift). */ + I3502_ADD = 0x0b000000, + I3502_ADDS = 0x2b000000, + I3502_SUB = 0x4b000000, + I3502_SUBS = 0x6b000000, + + /* Add/subtract shifted register instructions (with a shift). */ + I3502S_ADD_LSL = I3502_ADD, + + /* Add/subtract with carry instructions. */ + I3503_ADC = 0x1a000000, + I3503_SBC = 0x5a000000, + + /* Conditional select instructions. */ + I3506_CSEL = 0x1a800000, + I3506_CSINC = 0x1a800400, + I3506_CSINV = 0x5a800000, + I3506_CSNEG = 0x5a800400, + + /* Data-processing (1 source) instructions. */ + I3507_CLZ = 0x5ac01000, + I3507_RBIT = 0x5ac00000, + I3507_REV16 = 0x5ac00400, + I3507_REV32 = 0x5ac00800, + I3507_REV64 = 0x5ac00c00, + + /* Data-processing (2 source) instructions. */ + I3508_LSLV = 0x1ac02000, + I3508_LSRV = 0x1ac02400, + I3508_ASRV = 0x1ac02800, + I3508_RORV = 0x1ac02c00, + I3508_SMULH = 0x9b407c00, + I3508_UMULH = 0x9bc07c00, + I3508_UDIV = 0x1ac00800, + I3508_SDIV = 0x1ac00c00, + + /* Data-processing (3 source) instructions. */ + I3509_MADD = 0x1b000000, + I3509_MSUB = 0x1b008000, + + /* Logical shifted register instructions (without a shift). */ + I3510_AND = 0x0a000000, + I3510_BIC = 0x0a200000, + I3510_ORR = 0x2a000000, + I3510_ORN = 0x2a200000, + I3510_EOR = 0x4a000000, + I3510_EON = 0x4a200000, + I3510_ANDS = 0x6a000000, + + /* Logical shifted register instructions (with a shift). */ + I3502S_AND_LSR = I3510_AND | (1 << 22), + + /* AdvSIMD copy */ + I3605_DUP = 0x0e000400, + I3605_INS = 0x4e001c00, + I3605_UMOV = 0x0e003c00, + + /* AdvSIMD modified immediate */ + I3606_MOVI = 0x0f000400, + I3606_MVNI = 0x2f000400, + I3606_BIC = 0x2f001400, + I3606_ORR = 0x0f001400, + + /* AdvSIMD shift by immediate */ + I3614_SSHR = 0x0f000400, + I3614_SSRA = 0x0f001400, + I3614_SHL = 0x0f005400, + I3614_SLI = 0x2f005400, + I3614_USHR = 0x2f000400, + I3614_USRA = 0x2f001400, + + /* AdvSIMD three same. */ + I3616_ADD = 0x0e208400, + I3616_AND = 0x0e201c00, + I3616_BIC = 0x0e601c00, + I3616_BIF = 0x2ee01c00, + I3616_BIT = 0x2ea01c00, + I3616_BSL = 0x2e601c00, + I3616_EOR = 0x2e201c00, + I3616_MUL = 0x0e209c00, + I3616_ORR = 0x0ea01c00, + I3616_ORN = 0x0ee01c00, + I3616_SUB = 0x2e208400, + I3616_CMGT = 0x0e203400, + I3616_CMGE = 0x0e203c00, + I3616_CMTST = 0x0e208c00, + I3616_CMHI = 0x2e203400, + I3616_CMHS = 0x2e203c00, + I3616_CMEQ = 0x2e208c00, + I3616_SMAX = 0x0e206400, + I3616_SMIN = 0x0e206c00, + I3616_SSHL = 0x0e204400, + I3616_SQADD = 0x0e200c00, + I3616_SQSUB = 0x0e202c00, + I3616_UMAX = 0x2e206400, + I3616_UMIN = 0x2e206c00, + I3616_UQADD = 0x2e200c00, + I3616_UQSUB = 0x2e202c00, + I3616_USHL = 0x2e204400, + + /* AdvSIMD two-reg misc. */ + I3617_CMGT0 = 0x0e208800, + I3617_CMEQ0 = 0x0e209800, + I3617_CMLT0 = 0x0e20a800, + I3617_CMGE0 = 0x2e208800, + I3617_CMLE0 = 0x2e20a800, + I3617_NOT = 0x2e205800, + I3617_ABS = 0x0e20b800, + I3617_NEG = 0x2e20b800, + + /* System instructions. */ + NOP = 0xd503201f, + DMB_ISH = 0xd50338bf, + DMB_LD = 0x00000100, + DMB_ST = 0x00000200, +} AArch64Insn; + +static inline uint32_t tcg_in32(TCGContext *s) +{ + uint32_t v = *(uint32_t *)s->code_ptr; + return v; +} + +/* Emit an opcode with "type-checking" of the format. */ +#define tcg_out_insn(S, FMT, OP, ...) \ + glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__) + +static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rt, TCGReg rn, unsigned size) +{ + tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30)); +} + +static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, + int imm19, TCGReg rt) +{ + tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); +} + +static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rt, int imm19) +{ + tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt); +} + +static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn, + TCGCond c, int imm19) +{ + tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); +} + +static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26) +{ + tcg_out32(s, insn | (imm26 & 0x03ffffff)); +} + +static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn) +{ + tcg_out32(s, insn | rn << 5); +} + +static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn, + TCGReg r1, TCGReg r2, TCGReg rn, + tcg_target_long ofs, bool pre, bool w) +{ + insn |= 1u << 31; /* ext */ + insn |= pre << 24; + insn |= w << 23; + + tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0); + insn |= (ofs & (0x7f << 3)) << (15 - 3); + + tcg_out32(s, insn | r2 << 10 | rn << 5 | r1); +} + +static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, uint64_t aimm) +{ + if (aimm > 0xfff) { + tcg_debug_assert((aimm & 0xfff) == 0); + aimm >>= 12; + tcg_debug_assert(aimm <= 0xfff); + aimm |= 1 << 12; /* apply LSL 12 */ + } + tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd); +} + +/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4 + (Logical immediate). Both insn groups have N, IMMR and IMMS fields + that feed the DecodeBitMasks pseudo function. */ +static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, int n, int immr, int imms) +{ + tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10 + | rn << 5 | rd); +} + +#define tcg_out_insn_3404 tcg_out_insn_3402 + +static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, int imms) +{ + tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10 + | rn << 5 | rd); +} + +/* This function is used for the Move (wide immediate) instruction group. + Note that SHIFT is a full shift count, not the 2 bit HW field. */ +static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, uint16_t half, unsigned shift) +{ + tcg_debug_assert((shift & ~0x30) == 0); + tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); +} + +static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn, + TCGReg rd, int64_t disp) +{ + tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd); +} + +/* This function is for both 3.5.2 (Add/Subtract shifted register), for + the rare occasion when we actually want to supply a shift amount. */ +static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, + TCGType ext, TCGReg rd, TCGReg rn, + TCGReg rm, int imm6) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd); +} + +/* This function is for 3.5.2 (Add/subtract shifted register), + and 3.5.10 (Logical shifted register), for the vast majorty of cases + when we don't want to apply a shift. Thus it can also be used for + 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */ +static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd); +} + +#define tcg_out_insn_3503 tcg_out_insn_3502 +#define tcg_out_insn_3508 tcg_out_insn_3502 +#define tcg_out_insn_3510 tcg_out_insn_3502 + +static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd + | tcg_cond_to_aarch64[c] << 12); +} + +static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn) +{ + tcg_out32(s, insn | ext << 31 | rn << 5 | rd); +} + +static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); +} + +static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, TCGReg rn, int dst_idx, int src_idx) +{ + /* Note that bit 11 set means general register input. Therefore + we can handle both register sets with one function. */ + tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11) + | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5); +} + +static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, bool op, int cmode, uint8_t imm8) +{ + tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f) + | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5); +} + +static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, TCGReg rn, unsigned immhb) +{ + tcg_out32(s, insn | q << 30 | immhb << 16 + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q, + unsigned size, TCGReg rd, TCGReg rn, TCGReg rm) +{ + tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16 + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q, + unsigned size, TCGReg rd, TCGReg rn) +{ + tcg_out32(s, insn | q << 30 | (size << 22) + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg base, TCGType ext, + TCGReg regoff) +{ + /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ + tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | + 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, intptr_t offset) +{ + tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) +{ + /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ + tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 + | rn << 5 | (rd & 0x1f)); +} + +/* Register to register move using ORR (shifted register with no shift). */ +static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm) +{ + tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm); +} + +/* Register to register move using ADDI (move to/from SP). */ +static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn) +{ + tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0); +} + +/* This function is used for the Logical (immediate) instruction group. + The value of LIMM must satisfy IS_LIMM. See the comment above about + only supporting simplified logical immediates. */ +static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, + TCGReg rd, TCGReg rn, uint64_t limm) +{ + unsigned h, l, r, c; + + tcg_debug_assert(is_limm(limm)); + + h = clz64(limm); + l = ctz64(limm); + if (l == 0) { + r = 0; /* form 0....01....1 */ + c = ctz64(~limm) - 1; + if (h == 0) { + r = clz64(~limm); /* form 1..10..01..1 */ + c += r; + } + } else { + r = 64 - l; /* form 1....10....0 or 0..01..10..0 */ + c = r - h - 1; + } + if (ext == TCG_TYPE_I32) { + r &= 31; + c &= 31; + } + + tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg rd, tcg_target_long v64) +{ + bool q = type == TCG_TYPE_V128; + int cmode, imm8, i; + + /* Test all bytes equal first. */ + if (v64 == dup_const(MO_8, v64)) { + imm8 = (uint8_t)v64; + tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); + return; + } + + /* + * Test all bytes 0x00 or 0xff second. This can match cases that + * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. + */ + for (i = imm8 = 0; i < 8; i++) { + uint8_t byte = v64 >> (i * 8); + if (byte == 0xff) { + imm8 |= 1 << i; + } else if (byte != 0) { + goto fail_bytes; + } + } + tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8); + return; + fail_bytes: + + /* + * Tests for various replications. For each element width, if we + * cannot find an expansion there's no point checking a larger + * width because we already know by replication it cannot match. + */ + if (v64 == dup_const(MO_16, v64)) { + uint16_t v16 = v64; + + if (is_shimm16(v16, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + return; + } + if (is_shimm16(~v16, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + return; + } + + /* + * Otherwise, all remaining constants can be loaded in two insns: + * rd = v16 & 0xff, rd |= v16 & 0xff00. + */ + tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); + tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); + return; + } else if (v64 == dup_const(MO_32, v64)) { + uint32_t v32 = v64; + uint32_t n32 = ~v32; + + if (is_shimm32(v32, &cmode, &imm8) || + is_soimm32(v32, &cmode, &imm8) || + is_fimm32(v32, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + return; + } + if (is_shimm32(n32, &cmode, &imm8) || + is_soimm32(n32, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + return; + } + + /* + * Restrict the set of constants to those we can load with + * two instructions. Others we load from the pool. + */ + i = is_shimm32_pair(v32, &cmode, &imm8); + if (i) { + tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); + tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8)); + return; + } + i = is_shimm32_pair(n32, &cmode, &imm8); + if (i) { + tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); + tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8)); + return; + } + } else if (is_fimm64(v64, &cmode, &imm8)) { + tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); + return; + } + + /* + * As a last resort, load from the constant pool. Sadly there + * is no LD1R (literal), so store the full 16-byte vector. + */ + if (type == TCG_TYPE_V128) { + new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64); + tcg_out_insn(s, 3305, LDR_v128, 0, rd); + } else { + new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0); + tcg_out_insn(s, 3305, LDR_v64, 0, rd); + } +} + +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg rs) +{ + int is_q = type - TCG_TYPE_V64; + tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); + return true; +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + TCGReg temp = TCG_REG_TMP; + + if (offset < -0xffffff || offset > 0xffffff) { + tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); + tcg_out_insn(s, 3502, ADD, 1, temp, temp, base); + base = temp; + } else { + AArch64Insn add_insn = I3401_ADDI; + + if (offset < 0) { + add_insn = I3401_SUBI; + offset = -offset; + } + if (offset & 0xfff000) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000); + base = temp; + } + if (offset & 0xfff) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff); + base = temp; + } + } + tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece); + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, + tcg_target_long value) +{ + tcg_target_long svalue = value; + tcg_target_long ivalue = ~value; + tcg_target_long t0, t1, t2; + int s0, s1; + AArch64Insn opc; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(rd < 32); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(rd >= 32); + tcg_out_dupi_vec(s, type, rd, value); + return; + + default: + g_assert_not_reached(); + } + + /* For 32-bit values, discard potential garbage in value. For 64-bit + values within [2**31, 2**32-1], we can create smaller sequences by + interpreting this as a negative 32-bit number, while ensuring that + the high 32 bits are cleared by setting SF=0. */ + if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) { + svalue = (int32_t)value; + value = (uint32_t)value; + ivalue = (uint32_t)ivalue; + type = TCG_TYPE_I32; + } + + /* Speed things up by handling the common case of small positive + and negative values specially. */ + if ((value & ~0xffffull) == 0) { + tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0); + return; + } else if ((ivalue & ~0xffffull) == 0) { + tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0); + return; + } + + /* Check for bitfield immediates. For the benefit of 32-bit quantities, + use the sign-extended value. That lets us match rotated values such + as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */ + if (is_limm(svalue)) { + tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue); + return; + } + + /* Look for host pointer values within 4G of the PC. This happens + often when loading pointers to QEMU's own data structures. */ + if (type == TCG_TYPE_I64) { + tcg_target_long disp = value - (intptr_t)s->code_ptr; + if (disp == sextract64(disp, 0, 21)) { + tcg_out_insn(s, 3406, ADR, rd, disp); + return; + } + disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); + if (disp == sextract64(disp, 0, 21)) { + tcg_out_insn(s, 3406, ADRP, rd, disp); + if (value & 0xfff) { + tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff); + } + return; + } + } + + /* Would it take fewer insns to begin with MOVN? */ + if (ctpop64(value) >= 32) { + t0 = ivalue; + opc = I3405_MOVN; + } else { + t0 = value; + opc = I3405_MOVZ; + } + s0 = ctz64(t0) & (63 & -16); + t1 = t0 & ~(0xffffUL << s0); + s1 = ctz64(t1) & (63 & -16); + t2 = t1 & ~(0xffffUL << s1); + if (t2 == 0) { + tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); + if (t1 != 0) { + tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); + } + return; + } + + /* For more than 2 insns, dump it into the constant pool. */ + new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); + tcg_out_insn(s, 3305, LDR, 0, rd); +} + +/* Define something more legible for general use. */ +#define tcg_out_ldst_r tcg_out_insn_3310 + +static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, + TCGReg rn, intptr_t offset, int lgsize) +{ + /* If the offset is naturally aligned and in range, then we can + use the scaled uimm12 encoding */ + if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) { + uintptr_t scaled_uimm = offset >> lgsize; + if (scaled_uimm <= 0xfff) { + tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); + return; + } + } + + /* Small signed offsets can use the unscaled encoding. */ + if (offset >= -256 && offset < 256) { + tcg_out_insn_3312(s, insn, rd, rn, offset); + return; + } + + /* Worst-case scenario, move offset to temp register, use reg offset. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); + tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); +} + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + if (ret == arg) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + if (ret < 32 && arg < 32) { + tcg_out_movr(s, type, ret, arg); + break; + } else if (ret < 32) { + tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0); + break; + } else if (arg < 32) { + tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0); + break; + } + /* FALLTHRU */ + + case TCG_TYPE_V64: + tcg_debug_assert(ret >= 32 && arg >= 32); + tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >= 32 && arg >= 32); + tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg); + break; + + default: + g_assert_not_reached(); + } + return true; +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg base, intptr_t ofs) +{ + AArch64Insn insn; + int lgsz; + + switch (type) { + case TCG_TYPE_I32: + insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS); + lgsz = 2; + break; + case TCG_TYPE_I64: + insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD); + lgsz = 3; + break; + case TCG_TYPE_V64: + insn = I3312_LDRVD; + lgsz = 3; + break; + case TCG_TYPE_V128: + insn = I3312_LDRVQ; + lgsz = 4; + break; + default: + g_assert_not_reached(); + } + tcg_out_ldst(s, insn, ret, base, ofs, lgsz); +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, + TCGReg base, intptr_t ofs) +{ + AArch64Insn insn; + int lgsz; + + switch (type) { + case TCG_TYPE_I32: + insn = (src < 32 ? I3312_STRW : I3312_STRVS); + lgsz = 2; + break; + case TCG_TYPE_I64: + insn = (src < 32 ? I3312_STRX : I3312_STRVD); + lgsz = 3; + break; + case TCG_TYPE_V64: + insn = I3312_STRVD; + lgsz = 3; + break; + case TCG_TYPE_V128: + insn = I3312_STRVQ; + lgsz = 4; + break; + default: + g_assert_not_reached(); + } + tcg_out_ldst(s, insn, src, base, ofs, lgsz); +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (type <= TCG_TYPE_I64 && val == 0) { + tcg_out_st(s, type, TCG_REG_XZR, base, ofs); + return true; + } + return false; +} + +static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) +{ + tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b); +} + +static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) +{ + tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b); +} + +static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned int a, unsigned int b) +{ + tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b); +} + +static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, TCGReg rm, unsigned int a) +{ + tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a); +} + +static inline void tcg_out_shl(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rn, unsigned int m) +{ + int bits = ext ? 64 : 32; + int max = bits - 1; + tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max)); +} + +static inline void tcg_out_shr(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rn, unsigned int m) +{ + int max = ext ? 63 : 31; + tcg_out_ubfm(s, ext, rd, rn, m & max, max); +} + +static inline void tcg_out_sar(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rn, unsigned int m) +{ + int max = ext ? 63 : 31; + tcg_out_sbfm(s, ext, rd, rn, m & max, max); +} + +static inline void tcg_out_rotr(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rn, unsigned int m) +{ + int max = ext ? 63 : 31; + tcg_out_extr(s, ext, rd, rn, rn, m & max); +} + +static inline void tcg_out_rotl(TCGContext *s, TCGType ext, + TCGReg rd, TCGReg rn, unsigned int m) +{ + int bits = ext ? 64 : 32; + int max = bits - 1; + tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max)); +} + +static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd, + TCGReg rn, unsigned lsb, unsigned width) +{ + unsigned size = ext ? 64 : 32; + unsigned a = (size - lsb) & (size - 1); + unsigned b = width - 1; + tcg_out_bfm(s, ext, rd, rn, a, b); +} + +static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, + tcg_target_long b, bool const_b) +{ + if (const_b) { + /* Using CMP or CMN aliases. */ + if (b >= 0) { + tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); + } else { + tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); + } + } else { + /* Using CMP alias SUBS wzr, Wn, Wm */ + tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); + } +} + +static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +{ + ptrdiff_t offset = target - s->code_ptr; + tcg_debug_assert(offset == sextract64(offset, 0, 26)); + tcg_out_insn(s, 3206, B, offset); +} + +static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +{ + ptrdiff_t offset = target - s->code_ptr; + if (offset == sextract64(offset, 0, 26)) { + tcg_out_insn(s, 3206, BL, offset); + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); + tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + } +} + +static inline void tcg_out_callr(TCGContext *s, TCGReg reg) +{ + tcg_out_insn(s, 3207, BLR, reg); +} + +static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +{ + ptrdiff_t offset = target - s->code_ptr; + if (offset == sextract64(offset, 0, 26)) { + tcg_out_insn(s, 3206, BL, offset); + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); + tcg_out_callr(s, TCG_REG_TMP); + } +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + tcg_insn_unit i1, i2; + TCGType rt = TCG_TYPE_I64; + TCGReg rd = TCG_REG_TMP; + uint64_t pair; + + ptrdiff_t offset = addr - jmp_addr; + + if (offset == sextract64(offset, 0, 26)) { + i1 = I3206_B | ((offset >> 2) & 0x3ffffff); + i2 = NOP; + } else { + offset = (addr >> 12) - (jmp_addr >> 12); + + /* patch ADRP */ + i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd; + /* patch ADDI */ + i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; + } + pair = (uint64_t)i2 << 32 | i1; + atomic_set((uint64_t *)jmp_addr, pair); + flush_icache_range(jmp_addr, jmp_addr + 8); +} + +static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) +{ + if (!l->has_value) { + tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0); + tcg_out_insn(s, 3206, B, 0); + } else { + tcg_out_goto(s, l->u.value_ptr); + } +} + +static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, + TCGArg b, bool b_const, TCGLabel *l) +{ + intptr_t offset; + bool need_cmp; + + if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) { + need_cmp = false; + } else { + need_cmp = true; + tcg_out_cmp(s, ext, a, b, b_const); + } + + if (!l->has_value) { + tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); + offset = tcg_in32(s) >> 5; + } else { + offset = l->u.value_ptr - s->code_ptr; + tcg_debug_assert(offset == sextract64(offset, 0, 19)); + } + + if (need_cmp) { + tcg_out_insn(s, 3202, B_C, c, offset); + } else if (c == TCG_COND_EQ) { + tcg_out_insn(s, 3201, CBZ, ext, a, offset); + } else { + tcg_out_insn(s, 3201, CBNZ, ext, a, offset); + } +} + +static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn); +} + +static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn); +} + +static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn); +} + +static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits, + TCGReg rd, TCGReg rn) +{ + /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */ + int bits = (8 << s_bits) - 1; + tcg_out_sbfm(s, ext, rd, rn, 0, bits); +} + +static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, + TCGReg rd, TCGReg rn) +{ + /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */ + int bits = (8 << s_bits) - 1; + tcg_out_ubfm(s, 0, rd, rn, 0, bits); +} + +static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, + TCGReg rn, int64_t aimm) +{ + if (aimm >= 0) { + tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm); + } else { + tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm); + } +} + +static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, + TCGReg rh, TCGReg al, TCGReg ah, + tcg_target_long bl, tcg_target_long bh, + bool const_bl, bool const_bh, bool sub) +{ + TCGReg orig_rl = rl; + AArch64Insn insn; + + if (rl == ah || (!const_bh && rl == bh)) { + rl = TCG_REG_TMP; + } + + if (const_bl) { + insn = I3401_ADDSI; + if ((bl < 0) ^ sub) { + insn = I3401_SUBSI; + bl = -bl; + } + if (unlikely(al == TCG_REG_XZR)) { + /* ??? We want to allow al to be zero for the benefit of + negation via subtraction. However, that leaves open the + possibility of adding 0+const in the low part, and the + immediate add instructions encode XSP not XZR. Don't try + anything more elaborate here than loading another zero. */ + al = TCG_REG_TMP; + tcg_out_movi(s, ext, al, 0); + } + tcg_out_insn_3401(s, insn, ext, rl, al, bl); + } else { + tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); + } + + insn = I3503_ADC; + if (const_bh) { + /* Note that the only two constants we support are 0 and -1, and + that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */ + if ((bh != 0) ^ sub) { + insn = I3503_SBC; + } + bh = TCG_REG_XZR; + } else if (sub) { + insn = I3503_SBC; + } + tcg_out_insn_3503(s, insn, ext, rh, ah, bh); + + tcg_out_mov(s, ext, orig_rl, rl); +} + +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + static const uint32_t sync[] = { + [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST, + [TCG_MO_ST_ST] = DMB_ISH | DMB_ST, + [TCG_MO_LD_LD] = DMB_ISH | DMB_LD, + [TCG_MO_LD_ST] = DMB_ISH | DMB_LD, + [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD, + }; + tcg_out32(s, sync[a0 & TCG_MO_ALL]); +} + +static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, + TCGReg a0, TCGArg b, bool const_b, bool is_ctz) +{ + TCGReg a1 = a0; + if (is_ctz) { + a1 = TCG_REG_TMP; + tcg_out_insn(s, 3507, RBIT, ext, a1, a0); + } + if (const_b && b == (ext ? 64 : 32)) { + tcg_out_insn(s, 3507, CLZ, ext, d, a1); + } else { + AArch64Insn sel = I3506_CSEL; + + tcg_out_cmp(s, ext, a0, 0, 1); + tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1); + + if (const_b) { + if (b == -1) { + b = TCG_REG_XZR; + sel = I3506_CSINV; + } else if (b == 0) { + b = TCG_REG_XZR; + } else { + tcg_out_movi(s, ext, d, b); + b = d; + } + } + tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE); + } +} + +#ifdef CONFIG_SOFTMMU +#include "../tcg-ldst.c.inc" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * TCGMemOpIdx oi, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, TCGMemOpIdx oi, + * uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) +{ + ptrdiff_t offset = tcg_pcrel_diff(s, target); + tcg_debug_assert(offset == sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + MemOp size = opc & MO_SIZE; + + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); + tcg_out_adr(s, TCG_REG_X3, lb->raddr); + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + if (opc & MO_SIGN) { + tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); + } else { + tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0); + } + + tcg_out_goto(s, lb->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + MemOp size = opc & MO_SIZE; + + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); + tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); + tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); + tcg_out_adr(s, TCG_REG_X4, lb->raddr); + tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_goto(s, lb->raddr); + return true; +} + +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, + TCGType ext, TCGReg data_reg, TCGReg addr_reg, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = data_reg; + label->addrlo_reg = addr_reg; + label->raddr = raddr; + label->label_ptr[0] = label_ptr; +} + +/* We expect to use a 7-bit scaled negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); + +/* These offsets are built into the LDP below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8); + +/* Load and compare a TLB entry, emitting the conditional jump to the + slow path for the failure case, which will be patched later when finalizing + the slow path. Generated code returns the host addend in X1, + clobbers X0,X2,X3,TMP. */ +static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, + tcg_insn_unit **label_ptr, int mem_index, + bool is_read) +{ + unsigned a_bits = get_alignment_bits(opc); + unsigned s_bits = opc & MO_SIZE; + unsigned a_mask = (1u << a_bits) - 1; + unsigned s_mask = (1u << s_bits) - 1; + TCGReg x3; + TCGType mask_type; + uint64_t compare_mask; + + mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64, + TCG_REG_X0, TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1. */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); + + /* Load the tlb comparator into X0, and the fast path addend into X1. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read + ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, + offsetof(CPUTLBEntry, addend)); + + /* For aligned accesses, we check the first byte and include the alignment + bits within the address. For unaligned access, we check that we don't + cross pages using the address of the last byte of the access. */ + if (a_bits >= s_bits) { + x3 = addr_reg; + } else { + tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64, + TCG_REG_X3, addr_reg, s_mask - a_mask); + x3 = TCG_REG_X3; + } + compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; + + /* Store the page mask part of the address into X3. */ + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, + TCG_REG_X3, x3, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, TARGET_LONG_BITS == 64, TCG_REG_X0, TCG_REG_X3, 0); + + /* If not equal, we jump to the slow path. */ + *label_ptr = s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); +} + +#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, + TCGReg data_r, TCGReg addr_r, + TCGType otype, TCGReg off_r) +{ + const MemOp bswap = memop & MO_BSWAP; + + switch (memop & MO_SSIZE) { + case MO_UB: + tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + break; + case MO_SB: + tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, + data_r, addr_r, otype, off_r); + break; + case MO_UW: + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + if (bswap) { + tcg_out_rev16(s, data_r, data_r); + } + break; + case MO_SW: + if (bswap) { + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_rev16(s, data_r, data_r); + tcg_out_sxt(s, ext, MO_16, data_r, data_r); + } else { + tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), + data_r, addr_r, otype, off_r); + } + break; + case MO_UL: + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + if (bswap) { + tcg_out_rev32(s, data_r, data_r); + } + break; + case MO_SL: + if (bswap) { + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_rev32(s, data_r, data_r); + tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r); + } else { + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + } + break; + case MO_Q: + tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + if (bswap) { + tcg_out_rev64(s, data_r, data_r); + } + break; + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, + TCGReg data_r, TCGReg addr_r, + TCGType otype, TCGReg off_r) +{ + const MemOp bswap = memop & MO_BSWAP; + + switch (memop & MO_SIZE) { + case MO_8: + tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + break; + case MO_16: + if (bswap && data_r != TCG_REG_XZR) { + tcg_out_rev16(s, TCG_REG_TMP, data_r); + data_r = TCG_REG_TMP; + } + tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + break; + case MO_32: + if (bswap && data_r != TCG_REG_XZR) { + tcg_out_rev32(s, TCG_REG_TMP, data_r); + data_r = TCG_REG_TMP; + } + tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + break; + case MO_64: + if (bswap && data_r != TCG_REG_XZR) { + tcg_out_rev64(s, TCG_REG_TMP, data_r); + data_r = TCG_REG_TMP; + } + tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + break; + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, + TCGMemOpIdx oi, TCGType ext) +{ + MemOp memop = get_memop(oi); + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; +#ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr; + + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + TCG_REG_X1, otype, addr_reg); + add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, + s->code_ptr, label_ptr); +#else /* !CONFIG_SOFTMMU */ + if (USE_GUEST_BASE) { + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + TCG_REG_GUEST_BASE, otype, addr_reg); + } else { + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + } +#endif /* CONFIG_SOFTMMU */ +} + +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, + TCGMemOpIdx oi) +{ + MemOp memop = get_memop(oi); + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; +#ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr; + + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); + tcg_out_qemu_st_direct(s, memop, data_reg, + TCG_REG_X1, otype, addr_reg); + add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, + data_reg, addr_reg, s->code_ptr, label_ptr); +#else /* !CONFIG_SOFTMMU */ + if (USE_GUEST_BASE) { + tcg_out_qemu_st_direct(s, memop, data_reg, + TCG_REG_GUEST_BASE, otype, addr_reg); + } else { + tcg_out_qemu_st_direct(s, memop, data_reg, + addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + } +#endif /* CONFIG_SOFTMMU */ +} + +static tcg_insn_unit *tb_ret_addr; + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + /* 99% of the time, we can signal the use of extension registers + by looking to see if the opcode handles 64-bit data. */ + TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0; + + /* Hoist the loads of the most common arguments. */ + TCGArg a0 = args[0]; + TCGArg a1 = args[1]; + TCGArg a2 = args[2]; + int c2 = const_args[2]; + + /* Some operands are defined with "rZ" constraint, a register or + the zero register. These need not actually test args[I] == 0. */ +#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) + + switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_goto_long(s, s->code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); + tcg_out_goto_long(s, tb_ret_addr); + } + break; + + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset != NULL) { + /* TCG_TARGET_HAS_direct_jump */ + /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic + write can be used to patch the target address. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + /* actual branch destination will be patched by + tb_target_set_jmp_target later. */ + tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0); + } else { + /* !TCG_TARGET_HAS_direct_jump */ + tcg_debug_assert(s->tb_jmp_target_addr != NULL); + intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2; + tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); + } + tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + set_jmp_reset_offset(s, a0); + break; + + case INDEX_op_goto_ptr: + tcg_out_insn(s, 3207, BR, a0); + break; + + case INDEX_op_br: + tcg_out_goto_label(s, arg_label(a0)); + break; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0); + break; + case INDEX_op_ld8s_i32: + tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0); + break; + case INDEX_op_ld8s_i64: + tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0); + break; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1); + break; + case INDEX_op_ld16s_i32: + tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1); + break; + case INDEX_op_ld16s_i64: + tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2); + break; + case INDEX_op_ld32s_i64: + tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2); + break; + case INDEX_op_ld_i64: + tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3); + break; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0); + break; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2); + break; + case INDEX_op_st_i64: + tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3); + break; + + case INDEX_op_add_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_add_i64: + if (c2) { + tcg_out_addsubi(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2); + } + break; + + case INDEX_op_sub_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_sub_i64: + if (c2) { + tcg_out_addsubi(s, ext, a0, a1, -a2); + } else { + tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2); + } + break; + + case INDEX_op_neg_i64: + case INDEX_op_neg_i32: + tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1); + break; + + case INDEX_op_and_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_and_i64: + if (c2) { + tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, AND, ext, a0, a1, a2); + } + break; + + case INDEX_op_andc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_andc_i64: + if (c2) { + tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); + } + break; + + case INDEX_op_or_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_or_i64: + if (c2) { + tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2); + } + break; + + case INDEX_op_orc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_orc_i64: + if (c2) { + tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); + } + break; + + case INDEX_op_xor_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_xor_i64: + if (c2) { + tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2); + } + break; + + case INDEX_op_eqv_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_eqv_i64: + if (c2) { + tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2); + } else { + tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); + } + break; + + case INDEX_op_not_i64: + case INDEX_op_not_i32: + tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1); + break; + + case INDEX_op_mul_i64: + case INDEX_op_mul_i32: + tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR); + break; + + case INDEX_op_div_i64: + case INDEX_op_div_i32: + tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2); + break; + case INDEX_op_divu_i64: + case INDEX_op_divu_i32: + tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2); + break; + + case INDEX_op_rem_i64: + case INDEX_op_rem_i32: + tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + break; + case INDEX_op_remu_i64: + case INDEX_op_remu_i32: + tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + break; + + case INDEX_op_shl_i64: + case INDEX_op_shl_i32: + if (c2) { + tcg_out_shl(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2); + } + break; + + case INDEX_op_shr_i64: + case INDEX_op_shr_i32: + if (c2) { + tcg_out_shr(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2); + } + break; + + case INDEX_op_sar_i64: + case INDEX_op_sar_i32: + if (c2) { + tcg_out_sar(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2); + } + break; + + case INDEX_op_rotr_i64: + case INDEX_op_rotr_i32: + if (c2) { + tcg_out_rotr(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2); + } + break; + + case INDEX_op_rotl_i64: + case INDEX_op_rotl_i32: + if (c2) { + tcg_out_rotl(s, ext, a0, a1, a2); + } else { + tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2); + tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP); + } + break; + + case INDEX_op_clz_i64: + case INDEX_op_clz_i32: + tcg_out_cltz(s, ext, a0, a1, a2, c2, false); + break; + case INDEX_op_ctz_i64: + case INDEX_op_ctz_i32: + tcg_out_cltz(s, ext, a0, a1, a2, c2, true); + break; + + case INDEX_op_brcond_i32: + a1 = (int32_t)a1; + /* FALLTHRU */ + case INDEX_op_brcond_i64: + tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3])); + break; + + case INDEX_op_setcond_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_setcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */ + tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR, + TCG_REG_XZR, tcg_invert_cond(args[3])); + break; + + case INDEX_op_movcond_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_movcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]); + break; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, a0, a1, a2, ext); + break; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, REG0(0), a1, a2); + break; + + case INDEX_op_bswap64_i64: + tcg_out_rev64(s, a0, a1); + break; + case INDEX_op_bswap32_i64: + case INDEX_op_bswap32_i32: + tcg_out_rev32(s, a0, a1); + break; + case INDEX_op_bswap16_i64: + case INDEX_op_bswap16_i32: + tcg_out_rev16(s, a0, a1); + break; + + case INDEX_op_ext8s_i64: + case INDEX_op_ext8s_i32: + tcg_out_sxt(s, ext, MO_8, a0, a1); + break; + case INDEX_op_ext16s_i64: + case INDEX_op_ext16s_i32: + tcg_out_sxt(s, ext, MO_16, a0, a1); + break; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); + break; + case INDEX_op_ext8u_i64: + case INDEX_op_ext8u_i32: + tcg_out_uxt(s, MO_8, a0, a1); + break; + case INDEX_op_ext16u_i64: + case INDEX_op_ext16u_i32: + tcg_out_uxt(s, MO_16, a0, a1); + break; + case INDEX_op_extu_i32_i64: + case INDEX_op_ext32u_i64: + tcg_out_movr(s, TCG_TYPE_I32, a0, a1); + break; + + case INDEX_op_deposit_i64: + case INDEX_op_deposit_i32: + tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]); + break; + + case INDEX_op_extract_i64: + case INDEX_op_extract_i32: + tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1); + break; + + case INDEX_op_sextract_i64: + case INDEX_op_sextract_i32: + tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1); + break; + + case INDEX_op_extract2_i64: + case INDEX_op_extract2_i32: + tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]); + break; + + case INDEX_op_add2_i32: + tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), + (int32_t)args[4], args[5], const_args[4], + const_args[5], false); + break; + case INDEX_op_add2_i64: + tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], + args[5], const_args[4], const_args[5], false); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), + (int32_t)args[4], args[5], const_args[4], + const_args[5], true); + break; + case INDEX_op_sub2_i64: + tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], + args[5], const_args[4], const_args[5], true); + break; + + case INDEX_op_muluh_i64: + tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + g_assert_not_reached(); + } + +#undef REG0 +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + static const AArch64Insn cmp_insn[16] = { + [TCG_COND_EQ] = I3616_CMEQ, + [TCG_COND_GT] = I3616_CMGT, + [TCG_COND_GE] = I3616_CMGE, + [TCG_COND_GTU] = I3616_CMHI, + [TCG_COND_GEU] = I3616_CMHS, + }; + static const AArch64Insn cmp0_insn[16] = { + [TCG_COND_EQ] = I3617_CMEQ0, + [TCG_COND_GT] = I3617_CMGT0, + [TCG_COND_GE] = I3617_CMGE0, + [TCG_COND_LT] = I3617_CMLT0, + [TCG_COND_LE] = I3617_CMLE0, + }; + + TCGType type = vecl + TCG_TYPE_V64; + unsigned is_q = vecl; + TCGArg a0, a1, a2, a3; + int cmode, imm8; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; + case INDEX_op_add_vec: + tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_sub_vec: + tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); + break; + case INDEX_op_mul_vec: + tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2); + break; + case INDEX_op_neg_vec: + tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); + break; + case INDEX_op_abs_vec: + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + break; + case INDEX_op_and_vec: + if (const_args[2]) { + is_shimm1632(~a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } + tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); + break; + case INDEX_op_or_vec: + if (const_args[2]) { + is_shimm1632(a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } + tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2); + break; + case INDEX_op_andc_vec: + if (const_args[2]) { + is_shimm1632(a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } + tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2); + break; + case INDEX_op_orc_vec: + if (const_args[2]) { + is_shimm1632(~a2, &cmode, &imm8); + if (a0 == a1) { + tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); + return; + } + tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); + a2 = a0; + } + tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); + break; + case INDEX_op_xor_vec: + tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); + break; + case INDEX_op_ssadd_vec: + tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_sssub_vec: + tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + break; + case INDEX_op_usadd_vec: + tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_ussub_vec: + tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + break; + case INDEX_op_smax_vec: + tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); + break; + case INDEX_op_smin_vec: + tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2); + break; + case INDEX_op_umax_vec: + tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2); + break; + case INDEX_op_umin_vec: + tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2); + break; + case INDEX_op_not_vec: + tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); + break; + case INDEX_op_shli_vec: + tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); + break; + case INDEX_op_shri_vec: + tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); + break; + case INDEX_op_sari_vec: + tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); + break; + case INDEX_op_aa64_sli_vec: + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + break; + case INDEX_op_aa64_sshl_vec: + tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + break; + case INDEX_op_cmp_vec: + { + TCGCond cond = args[3]; + AArch64Insn insn; + + if (cond == TCG_COND_NE) { + if (const_args[2]) { + tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); + } else { + tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); + tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); + } + } else { + if (const_args[2]) { + insn = cmp0_insn[cond]; + if (insn) { + tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); + break; + } + tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0); + a2 = TCG_VEC_TMP; + } + insn = cmp_insn[cond]; + if (insn == 0) { + TCGArg t; + t = a1, a1 = a2, a2 = t; + cond = tcg_swap_cond(cond); + insn = cmp_insn[cond]; + tcg_debug_assert(insn != 0); + } + tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); + } + } + break; + + case INDEX_op_bitsel_vec: + a3 = args[3]; + if (a0 == a3) { + tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1); + } else if (a0 == a2) { + tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1); + } else { + if (a0 != a1) { + tcg_out_mov(s, type, a0, a1); + } + tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3); + } + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_orc_vec: + case INDEX_op_neg_vec: + case INDEX_op_abs_vec: + case INDEX_op_not_vec: + case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_bitsel_vec: + return 1; + case INDEX_op_rotli_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return -1; + case INDEX_op_mul_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + return vece < MO_64; + + default: + return 0; + } +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + va_list va; + TCGv_vec v0, v1, v2, t1, t2; + TCGArg a2; + + va_start(va, a0); + v0 = temp_tcgv_vec(arg_temp(a0)); + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 = va_arg(va, TCGArg); + v2 = temp_tcgv_vec(arg_temp(a2)); + + switch (opc) { + case INDEX_op_rotli_vec: + t1 = tcg_temp_new_vec(type); + tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); + vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + /* Right shifts are negative left shifts for AArch64. */ + t1 = tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + opc = (opc == INDEX_op_shrv_vec + ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec); + vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotlv_vec: + t1 = tcg_temp_new_vec(type); + tcg_gen_dupi_vec(vece, t1, 8 << vece); + tcg_gen_sub_vec(vece, t1, v2, t1); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_or_vec(vece, v0, v0, t1); + tcg_temp_free_vec(t1); + break; + + case INDEX_op_rotrv_vec: + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + tcg_gen_dupi_vec(vece, t2, 8 << vece); + tcg_gen_add_vec(vece, t2, t1, t2); + /* Right shifts are negative left shifts for AArch64. */ + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + tcg_gen_or_vec(vece, v0, t1, t2); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + + default: + g_assert_not_reached(); + } + + va_end(va); +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; + static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; + static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; + static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; + static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; + static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; + static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; + static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; + static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; + static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; + static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; + static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; + static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; + static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } }; + static const TCGTargetOpDef r_r_rAL + = { .args_ct_str = { "r", "r", "rAL" } }; + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "0", "rZ" } }; + static const TCGTargetOpDef ext2 + = { .args_ct_str = { "r", "rZ", "rZ" } }; + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; + static const TCGTargetOpDef add2 + = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; + static const TCGTargetOpDef w_w_w_w + = { .args_ct_str = { "w", "w", "w", "w" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_ext8u_i32: + case INDEX_op_ext16u_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return &r_r_rA; + + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_muluh_i64: + case INDEX_op_mulsh_i64: + return &r_r_r; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + return &r_r_rL; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i64: + return &r_r_rAL; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rA; + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + return &movc; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_l; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + return &lZ_l; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return &dep; + + case INDEX_op_extract2_i32: + case INDEX_op_extract2_i64: + return &ext2; + + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + return &add2; + + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_mul_vec: + case INDEX_op_xor_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_aa64_sshl_vec: + return &w_w_w; + case INDEX_op_not_vec: + case INDEX_op_neg_vec: + case INDEX_op_abs_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + return &w_w; + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + case INDEX_op_dupm_vec: + return &w_r; + case INDEX_op_dup_vec: + return &w_wr; + case INDEX_op_or_vec: + case INDEX_op_andc_vec: + return &w_w_wO; + case INDEX_op_and_vec: + case INDEX_op_orc_vec: + return &w_w_wN; + case INDEX_op_cmp_vec: + return &w_w_wZ; + case INDEX_op_bitsel_vec: + return &w_w_w_w; + case INDEX_op_aa64_sli_vec: + return &w_0_w; + + default: + return NULL; + } +} + +static void tcg_target_init(TCGContext *s) +{ + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; + tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + + tcg_target_call_clobber_regs = -1ull; + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */ + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); +} + +/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ +#define PUSH_SIZE ((30 - 19 + 1) * 8) + +#define FRAME_SIZE \ + ((PUSH_SIZE \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_NLONGS * sizeof(long) \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & ~(TCG_TARGET_STACK_ALIGN - 1)) + +/* We're expecting a 2 byte uleb128 encoded value. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); + +/* We're expecting to use a single ADDI insn. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff); + +static void tcg_target_qemu_prologue(TCGContext *s) +{ + TCGReg r; + + /* Push (FP, LR) and allocate space for all saved registers. */ + tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR, + TCG_REG_SP, -PUSH_SIZE, 1, 1); + + /* Set up frame pointer for canonical unwinding. */ + tcg_out_movr_sp(s, TCG_TYPE_I64, TCG_REG_FP, TCG_REG_SP); + + /* Store callee-preserved regs x19..x28. */ + for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { + int ofs = (r - TCG_REG_X19 + 2) * 8; + tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0); + } + + /* Make stack space for TCG locals. */ + tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, + FRAME_SIZE - PUSH_SIZE); + + /* Inform TCG about how to find TCG locals with register, offset, size. */ + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, + CPU_TEMP_BUF_NLONGS * sizeof(long)); + +#if !defined(CONFIG_SOFTMMU) + if (USE_GUEST_BASE) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); + } +#endif + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]); + + /* + * Return path for goto_ptr. Set return value to 0, a-la exit_tb, + * and fall through to the rest of the epilogue. + */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + + /* Remove TCG locals stack space. */ + tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, + FRAME_SIZE - PUSH_SIZE); + + /* Restore registers x19..x28. */ + for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { + int ofs = (r - TCG_REG_X19 + 2) * 8; + tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0); + } + + /* Pop (FP, LR), restore SP to previous frame. */ + tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR, + TCG_REG_SP, PUSH_SIZE, 0, 1); + tcg_out_insn(s, 3207, RET, TCG_REG_LR); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[24]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_AARCH64 + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x78, /* sleb128 -8 */ + .h.cie.return_column = TCG_REG_LR, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */ + 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */ + 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */ + 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */ + 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */ + 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */ + 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */ + 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */ + 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */ + 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */ + 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */ + 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c deleted file mode 100644 index 760b0e742d..0000000000 --- a/tcg/aarch64/tcg-target.inc.c +++ /dev/null @@ -1,2973 +0,0 @@ -/* - * Initial TCG Implementation for aarch64 - * - * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH - * Written by Claudio Fontana - * - * This work is licensed under the terms of the GNU GPL, version 2 or - * (at your option) any later version. - * - * See the COPYING file in the top-level directory for details. - */ - -#include "../tcg-pool.inc.c" -#include "qemu/bitops.h" - -/* We're going to re-use TCGType in setting of the SF bit, which controls - the size of the operation performed. If we know the values match, it - makes things much cleaner. */ -QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1); - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", - "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", - "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", - "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp", - - "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", - "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", - "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", - "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31", -}; -#endif /* CONFIG_DEBUG_TCG */ - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, - TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, - TCG_REG_X28, /* we will reserve this for guest_base if configured */ - - TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, - TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15, - TCG_REG_X16, TCG_REG_X17, - - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, - TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, - - /* X18 reserved by system */ - /* X19 reserved for AREG0 */ - /* X29 reserved as fp */ - /* X30 reserved as temporary */ - - TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, - TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, - /* V8 - V15 are call-saved, and skipped. */ - TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, - TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, - TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, - TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, -}; - -static const int tcg_target_call_iarg_regs[8] = { - TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, - TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 -}; -static const int tcg_target_call_oarg_regs[1] = { - TCG_REG_X0 -}; - -#define TCG_REG_TMP TCG_REG_X30 -#define TCG_VEC_TMP TCG_REG_V31 - -#ifndef CONFIG_SOFTMMU -/* Note that XZR cannot be encoded in the address base register slot, - as that actaully encodes SP. So if we need to zero-extend the guest - address, via the address index register slot, we need to load even - a zero guest base into a register. */ -#define USE_GUEST_BASE (guest_base != 0 || TARGET_LONG_BITS == 32) -#define TCG_REG_GUEST_BASE TCG_REG_X28 -#endif - -static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - code_ptr; - if (offset == sextract64(offset, 0, 26)) { - /* read instruction, mask away previous PC_REL26 parameter contents, - set the proper offset, then write back the instruction. */ - *code_ptr = deposit32(*code_ptr, 0, 26, offset); - return true; - } - return false; -} - -static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - code_ptr; - if (offset == sextract64(offset, 0, 19)) { - *code_ptr = deposit32(*code_ptr, 5, 19, offset); - return true; - } - return false; -} - -static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_debug_assert(addend == 0); - switch (type) { - case R_AARCH64_JUMP26: - case R_AARCH64_CALL26: - return reloc_pc26(code_ptr, (tcg_insn_unit *)value); - case R_AARCH64_CONDBR19: - return reloc_pc19(code_ptr, (tcg_insn_unit *)value); - default: - g_assert_not_reached(); - } -} - -#define TCG_CT_CONST_AIMM 0x100 -#define TCG_CT_CONST_LIMM 0x200 -#define TCG_CT_CONST_ZERO 0x400 -#define TCG_CT_CONST_MONE 0x800 -#define TCG_CT_CONST_ORRI 0x1000 -#define TCG_CT_CONST_ANDI 0x2000 - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': /* general registers */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffffu; - break; - case 'w': /* advsimd registers */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= 0xffffffff00000000ull; - break; - case 'l': /* qemu_ld / qemu_st address, data_reg */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffffu; -#ifdef CONFIG_SOFTMMU - /* x0 and x1 will be overwritten when reading the tlb entry, - and x2, and x3 for helper args, better to avoid using them. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); -#endif - break; - case 'A': /* Valid for arithmetic immediate (positive or negative). */ - ct->ct |= TCG_CT_CONST_AIMM; - break; - case 'L': /* Valid for logical immediate. */ - ct->ct |= TCG_CT_CONST_LIMM; - break; - case 'M': /* minus one */ - ct->ct |= TCG_CT_CONST_MONE; - break; - case 'O': /* vector orr/bic immediate */ - ct->ct |= TCG_CT_CONST_ORRI; - break; - case 'N': /* vector orr/bic immediate, inverted */ - ct->ct |= TCG_CT_CONST_ANDI; - break; - case 'Z': /* zero */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* Match a constant valid for addition (12-bit, optionally shifted). */ -static inline bool is_aimm(uint64_t val) -{ - return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0; -} - -/* Match a constant valid for logical operations. */ -static inline bool is_limm(uint64_t val) -{ - /* Taking a simplified view of the logical immediates for now, ignoring - the replication that can happen across the field. Match bit patterns - of the forms - 0....01....1 - 0..01..10..0 - and their inverses. */ - - /* Make things easier below, by testing the form with msb clear. */ - if ((int64_t)val < 0) { - val = ~val; - } - if (val == 0) { - return false; - } - val += val & -val; - return (val & (val - 1)) == 0; -} - -/* Return true if v16 is a valid 16-bit shifted immediate. */ -static bool is_shimm16(uint16_t v16, int *cmode, int *imm8) -{ - if (v16 == (v16 & 0xff)) { - *cmode = 0x8; - *imm8 = v16 & 0xff; - return true; - } else if (v16 == (v16 & 0xff00)) { - *cmode = 0xa; - *imm8 = v16 >> 8; - return true; - } - return false; -} - -/* Return true if v32 is a valid 32-bit shifted immediate. */ -static bool is_shimm32(uint32_t v32, int *cmode, int *imm8) -{ - if (v32 == (v32 & 0xff)) { - *cmode = 0x0; - *imm8 = v32 & 0xff; - return true; - } else if (v32 == (v32 & 0xff00)) { - *cmode = 0x2; - *imm8 = (v32 >> 8) & 0xff; - return true; - } else if (v32 == (v32 & 0xff0000)) { - *cmode = 0x4; - *imm8 = (v32 >> 16) & 0xff; - return true; - } else if (v32 == (v32 & 0xff000000)) { - *cmode = 0x6; - *imm8 = v32 >> 24; - return true; - } - return false; -} - -/* Return true if v32 is a valid 32-bit shifting ones immediate. */ -static bool is_soimm32(uint32_t v32, int *cmode, int *imm8) -{ - if ((v32 & 0xffff00ff) == 0xff) { - *cmode = 0xc; - *imm8 = (v32 >> 8) & 0xff; - return true; - } else if ((v32 & 0xff00ffff) == 0xffff) { - *cmode = 0xd; - *imm8 = (v32 >> 16) & 0xff; - return true; - } - return false; -} - -/* Return true if v32 is a valid float32 immediate. */ -static bool is_fimm32(uint32_t v32, int *cmode, int *imm8) -{ - if (extract32(v32, 0, 19) == 0 - && (extract32(v32, 25, 6) == 0x20 - || extract32(v32, 25, 6) == 0x1f)) { - *cmode = 0xf; - *imm8 = (extract32(v32, 31, 1) << 7) - | (extract32(v32, 25, 1) << 6) - | extract32(v32, 19, 6); - return true; - } - return false; -} - -/* Return true if v64 is a valid float64 immediate. */ -static bool is_fimm64(uint64_t v64, int *cmode, int *imm8) -{ - if (extract64(v64, 0, 48) == 0 - && (extract64(v64, 54, 9) == 0x100 - || extract64(v64, 54, 9) == 0x0ff)) { - *cmode = 0xf; - *imm8 = (extract64(v64, 63, 1) << 7) - | (extract64(v64, 54, 1) << 6) - | extract64(v64, 48, 6); - return true; - } - return false; -} - -/* - * Return non-zero if v32 can be formed by MOVI+ORR. - * Place the parameters for MOVI in (cmode, imm8). - * Return the cmode for ORR; the imm8 can be had via extraction from v32. - */ -static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8) -{ - int i; - - for (i = 6; i > 0; i -= 2) { - /* Mask out one byte we can add with ORR. */ - uint32_t tmp = v32 & ~(0xffu << (i * 4)); - if (is_shimm32(tmp, cmode, imm8) || - is_soimm32(tmp, cmode, imm8)) { - break; - } - } - return i; -} - -/* Return true if V is a valid 16-bit or 32-bit shifted immediate. */ -static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8) -{ - if (v32 == deposit32(v32, 16, 16, v32)) { - return is_shimm16(v32, cmode, imm8); - } else { - return is_shimm32(v32, cmode, imm8); - } -} - -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - - if (ct & TCG_CT_CONST) { - return 1; - } - if (type == TCG_TYPE_I32) { - val = (int32_t)val; - } - if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) { - return 1; - } - if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) { - return 1; - } - if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } - if ((ct & TCG_CT_CONST_MONE) && val == -1) { - return 1; - } - - switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) { - case 0: - break; - case TCG_CT_CONST_ANDI: - val = ~val; - /* fallthru */ - case TCG_CT_CONST_ORRI: - if (val == deposit64(val, 32, 32, val)) { - int cmode, imm8; - return is_shimm1632(val, &cmode, &imm8); - } - break; - default: - /* Both bits should not be set for the same insn. */ - g_assert_not_reached(); - } - - return 0; -} - -enum aarch64_cond_code { - COND_EQ = 0x0, - COND_NE = 0x1, - COND_CS = 0x2, /* Unsigned greater or equal */ - COND_HS = COND_CS, /* ALIAS greater or equal */ - COND_CC = 0x3, /* Unsigned less than */ - COND_LO = COND_CC, /* ALIAS Lower */ - COND_MI = 0x4, /* Negative */ - COND_PL = 0x5, /* Zero or greater */ - COND_VS = 0x6, /* Overflow */ - COND_VC = 0x7, /* No overflow */ - COND_HI = 0x8, /* Unsigned greater than */ - COND_LS = 0x9, /* Unsigned less or equal */ - COND_GE = 0xa, - COND_LT = 0xb, - COND_GT = 0xc, - COND_LE = 0xd, - COND_AL = 0xe, - COND_NV = 0xf, /* behaves like COND_AL here */ -}; - -static const enum aarch64_cond_code tcg_cond_to_aarch64[] = { - [TCG_COND_EQ] = COND_EQ, - [TCG_COND_NE] = COND_NE, - [TCG_COND_LT] = COND_LT, - [TCG_COND_GE] = COND_GE, - [TCG_COND_LE] = COND_LE, - [TCG_COND_GT] = COND_GT, - /* unsigned */ - [TCG_COND_LTU] = COND_LO, - [TCG_COND_GTU] = COND_HI, - [TCG_COND_GEU] = COND_HS, - [TCG_COND_LEU] = COND_LS, -}; - -typedef enum { - LDST_ST = 0, /* store */ - LDST_LD = 1, /* load */ - LDST_LD_S_X = 2, /* load and sign-extend into Xt */ - LDST_LD_S_W = 3, /* load and sign-extend into Wt */ -} AArch64LdstType; - -/* We encode the format of the insn into the beginning of the name, so that - we can have the preprocessor help "typecheck" the insn vs the output - function. Arm didn't provide us with nice names for the formats, so we - use the section number of the architecture reference manual in which the - instruction group is described. */ -typedef enum { - /* Compare and branch (immediate). */ - I3201_CBZ = 0x34000000, - I3201_CBNZ = 0x35000000, - - /* Conditional branch (immediate). */ - I3202_B_C = 0x54000000, - - /* Unconditional branch (immediate). */ - I3206_B = 0x14000000, - I3206_BL = 0x94000000, - - /* Unconditional branch (register). */ - I3207_BR = 0xd61f0000, - I3207_BLR = 0xd63f0000, - I3207_RET = 0xd65f0000, - - /* AdvSIMD load/store single structure. */ - I3303_LD1R = 0x0d40c000, - - /* Load literal for loading the address at pc-relative offset */ - I3305_LDR = 0x58000000, - I3305_LDR_v64 = 0x5c000000, - I3305_LDR_v128 = 0x9c000000, - - /* Load/store register. Described here as 3.3.12, but the helper - that emits them can transform to 3.3.10 or 3.3.13. */ - I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30, - I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30, - I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30, - I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30, - - I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30, - I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30, - I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30, - I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30, - - I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30, - I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30, - - I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30, - I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30, - I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30, - - I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30, - I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30, - - I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30, - I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30, - - I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30, - I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30, - - I3312_TO_I3310 = 0x00200800, - I3312_TO_I3313 = 0x01000000, - - /* Load/store register pair instructions. */ - I3314_LDP = 0x28400000, - I3314_STP = 0x28000000, - - /* Add/subtract immediate instructions. */ - I3401_ADDI = 0x11000000, - I3401_ADDSI = 0x31000000, - I3401_SUBI = 0x51000000, - I3401_SUBSI = 0x71000000, - - /* Bitfield instructions. */ - I3402_BFM = 0x33000000, - I3402_SBFM = 0x13000000, - I3402_UBFM = 0x53000000, - - /* Extract instruction. */ - I3403_EXTR = 0x13800000, - - /* Logical immediate instructions. */ - I3404_ANDI = 0x12000000, - I3404_ORRI = 0x32000000, - I3404_EORI = 0x52000000, - - /* Move wide immediate instructions. */ - I3405_MOVN = 0x12800000, - I3405_MOVZ = 0x52800000, - I3405_MOVK = 0x72800000, - - /* PC relative addressing instructions. */ - I3406_ADR = 0x10000000, - I3406_ADRP = 0x90000000, - - /* Add/subtract shifted register instructions (without a shift). */ - I3502_ADD = 0x0b000000, - I3502_ADDS = 0x2b000000, - I3502_SUB = 0x4b000000, - I3502_SUBS = 0x6b000000, - - /* Add/subtract shifted register instructions (with a shift). */ - I3502S_ADD_LSL = I3502_ADD, - - /* Add/subtract with carry instructions. */ - I3503_ADC = 0x1a000000, - I3503_SBC = 0x5a000000, - - /* Conditional select instructions. */ - I3506_CSEL = 0x1a800000, - I3506_CSINC = 0x1a800400, - I3506_CSINV = 0x5a800000, - I3506_CSNEG = 0x5a800400, - - /* Data-processing (1 source) instructions. */ - I3507_CLZ = 0x5ac01000, - I3507_RBIT = 0x5ac00000, - I3507_REV16 = 0x5ac00400, - I3507_REV32 = 0x5ac00800, - I3507_REV64 = 0x5ac00c00, - - /* Data-processing (2 source) instructions. */ - I3508_LSLV = 0x1ac02000, - I3508_LSRV = 0x1ac02400, - I3508_ASRV = 0x1ac02800, - I3508_RORV = 0x1ac02c00, - I3508_SMULH = 0x9b407c00, - I3508_UMULH = 0x9bc07c00, - I3508_UDIV = 0x1ac00800, - I3508_SDIV = 0x1ac00c00, - - /* Data-processing (3 source) instructions. */ - I3509_MADD = 0x1b000000, - I3509_MSUB = 0x1b008000, - - /* Logical shifted register instructions (without a shift). */ - I3510_AND = 0x0a000000, - I3510_BIC = 0x0a200000, - I3510_ORR = 0x2a000000, - I3510_ORN = 0x2a200000, - I3510_EOR = 0x4a000000, - I3510_EON = 0x4a200000, - I3510_ANDS = 0x6a000000, - - /* Logical shifted register instructions (with a shift). */ - I3502S_AND_LSR = I3510_AND | (1 << 22), - - /* AdvSIMD copy */ - I3605_DUP = 0x0e000400, - I3605_INS = 0x4e001c00, - I3605_UMOV = 0x0e003c00, - - /* AdvSIMD modified immediate */ - I3606_MOVI = 0x0f000400, - I3606_MVNI = 0x2f000400, - I3606_BIC = 0x2f001400, - I3606_ORR = 0x0f001400, - - /* AdvSIMD shift by immediate */ - I3614_SSHR = 0x0f000400, - I3614_SSRA = 0x0f001400, - I3614_SHL = 0x0f005400, - I3614_SLI = 0x2f005400, - I3614_USHR = 0x2f000400, - I3614_USRA = 0x2f001400, - - /* AdvSIMD three same. */ - I3616_ADD = 0x0e208400, - I3616_AND = 0x0e201c00, - I3616_BIC = 0x0e601c00, - I3616_BIF = 0x2ee01c00, - I3616_BIT = 0x2ea01c00, - I3616_BSL = 0x2e601c00, - I3616_EOR = 0x2e201c00, - I3616_MUL = 0x0e209c00, - I3616_ORR = 0x0ea01c00, - I3616_ORN = 0x0ee01c00, - I3616_SUB = 0x2e208400, - I3616_CMGT = 0x0e203400, - I3616_CMGE = 0x0e203c00, - I3616_CMTST = 0x0e208c00, - I3616_CMHI = 0x2e203400, - I3616_CMHS = 0x2e203c00, - I3616_CMEQ = 0x2e208c00, - I3616_SMAX = 0x0e206400, - I3616_SMIN = 0x0e206c00, - I3616_SSHL = 0x0e204400, - I3616_SQADD = 0x0e200c00, - I3616_SQSUB = 0x0e202c00, - I3616_UMAX = 0x2e206400, - I3616_UMIN = 0x2e206c00, - I3616_UQADD = 0x2e200c00, - I3616_UQSUB = 0x2e202c00, - I3616_USHL = 0x2e204400, - - /* AdvSIMD two-reg misc. */ - I3617_CMGT0 = 0x0e208800, - I3617_CMEQ0 = 0x0e209800, - I3617_CMLT0 = 0x0e20a800, - I3617_CMGE0 = 0x2e208800, - I3617_CMLE0 = 0x2e20a800, - I3617_NOT = 0x2e205800, - I3617_ABS = 0x0e20b800, - I3617_NEG = 0x2e20b800, - - /* System instructions. */ - NOP = 0xd503201f, - DMB_ISH = 0xd50338bf, - DMB_LD = 0x00000100, - DMB_ST = 0x00000200, -} AArch64Insn; - -static inline uint32_t tcg_in32(TCGContext *s) -{ - uint32_t v = *(uint32_t *)s->code_ptr; - return v; -} - -/* Emit an opcode with "type-checking" of the format. */ -#define tcg_out_insn(S, FMT, OP, ...) \ - glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__) - -static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q, - TCGReg rt, TCGReg rn, unsigned size) -{ - tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30)); -} - -static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, - int imm19, TCGReg rt) -{ - tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); -} - -static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rt, int imm19) -{ - tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt); -} - -static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn, - TCGCond c, int imm19) -{ - tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5); -} - -static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26) -{ - tcg_out32(s, insn | (imm26 & 0x03ffffff)); -} - -static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn) -{ - tcg_out32(s, insn | rn << 5); -} - -static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn, - TCGReg r1, TCGReg r2, TCGReg rn, - tcg_target_long ofs, bool pre, bool w) -{ - insn |= 1u << 31; /* ext */ - insn |= pre << 24; - insn |= w << 23; - - tcg_debug_assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0); - insn |= (ofs & (0x7f << 3)) << (15 - 3); - - tcg_out32(s, insn | r2 << 10 | rn << 5 | r1); -} - -static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, uint64_t aimm) -{ - if (aimm > 0xfff) { - tcg_debug_assert((aimm & 0xfff) == 0); - aimm >>= 12; - tcg_debug_assert(aimm <= 0xfff); - aimm |= 1 << 12; /* apply LSL 12 */ - } - tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd); -} - -/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4 - (Logical immediate). Both insn groups have N, IMMR and IMMS fields - that feed the DecodeBitMasks pseudo function. */ -static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, int n, int immr, int imms) -{ - tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10 - | rn << 5 | rd); -} - -#define tcg_out_insn_3404 tcg_out_insn_3402 - -static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, TCGReg rm, int imms) -{ - tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10 - | rn << 5 | rd); -} - -/* This function is used for the Move (wide immediate) instruction group. - Note that SHIFT is a full shift count, not the 2 bit HW field. */ -static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, uint16_t half, unsigned shift) -{ - tcg_debug_assert((shift & ~0x30) == 0); - tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd); -} - -static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn, - TCGReg rd, int64_t disp) -{ - tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd); -} - -/* This function is for both 3.5.2 (Add/Subtract shifted register), for - the rare occasion when we actually want to supply a shift amount. */ -static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, - TCGType ext, TCGReg rd, TCGReg rn, - TCGReg rm, int imm6) -{ - tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd); -} - -/* This function is for 3.5.2 (Add/subtract shifted register), - and 3.5.10 (Logical shifted register), for the vast majorty of cases - when we don't want to apply a shift. Thus it can also be used for - 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */ -static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, TCGReg rm) -{ - tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd); -} - -#define tcg_out_insn_3503 tcg_out_insn_3502 -#define tcg_out_insn_3508 tcg_out_insn_3502 -#define tcg_out_insn_3510 tcg_out_insn_3502 - -static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c) -{ - tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd - | tcg_cond_to_aarch64[c] << 12); -} - -static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn) -{ - tcg_out32(s, insn | ext << 31 | rn << 5 | rd); -} - -static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) -{ - tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); -} - -static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q, - TCGReg rd, TCGReg rn, int dst_idx, int src_idx) -{ - /* Note that bit 11 set means general register input. Therefore - we can handle both register sets with one function. */ - tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11) - | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5); -} - -static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q, - TCGReg rd, bool op, int cmode, uint8_t imm8) -{ - tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f) - | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5); -} - -static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q, - TCGReg rd, TCGReg rn, unsigned immhb) -{ - tcg_out32(s, insn | q << 30 | immhb << 16 - | (rn & 0x1f) << 5 | (rd & 0x1f)); -} - -static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q, - unsigned size, TCGReg rd, TCGReg rn, TCGReg rm) -{ - tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16 - | (rn & 0x1f) << 5 | (rd & 0x1f)); -} - -static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q, - unsigned size, TCGReg rd, TCGReg rn) -{ - tcg_out32(s, insn | q << 30 | (size << 22) - | (rn & 0x1f) << 5 | (rd & 0x1f)); -} - -static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, - TCGReg regoff) -{ - /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); -} - -static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg rn, intptr_t offset) -{ - tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); -} - -static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) -{ - /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 - | rn << 5 | (rd & 0x1f)); -} - -/* Register to register move using ORR (shifted register with no shift). */ -static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm) -{ - tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm); -} - -/* Register to register move using ADDI (move to/from SP). */ -static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn) -{ - tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0); -} - -/* This function is used for the Logical (immediate) instruction group. - The value of LIMM must satisfy IS_LIMM. See the comment above about - only supporting simplified logical immediates. */ -static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, - TCGReg rd, TCGReg rn, uint64_t limm) -{ - unsigned h, l, r, c; - - tcg_debug_assert(is_limm(limm)); - - h = clz64(limm); - l = ctz64(limm); - if (l == 0) { - r = 0; /* form 0....01....1 */ - c = ctz64(~limm) - 1; - if (h == 0) { - r = clz64(~limm); /* form 1..10..01..1 */ - c += r; - } - } else { - r = 64 - l; /* form 1....10....0 or 0..01..10..0 */ - c = r - h - 1; - } - if (ext == TCG_TYPE_I32) { - r &= 31; - c &= 31; - } - - tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c); -} - -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, tcg_target_long v64) -{ - bool q = type == TCG_TYPE_V128; - int cmode, imm8, i; - - /* Test all bytes equal first. */ - if (v64 == dup_const(MO_8, v64)) { - imm8 = (uint8_t)v64; - tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8); - return; - } - - /* - * Test all bytes 0x00 or 0xff second. This can match cases that - * might otherwise take 2 or 3 insns for MO_16 or MO_32 below. - */ - for (i = imm8 = 0; i < 8; i++) { - uint8_t byte = v64 >> (i * 8); - if (byte == 0xff) { - imm8 |= 1 << i; - } else if (byte != 0) { - goto fail_bytes; - } - } - tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8); - return; - fail_bytes: - - /* - * Tests for various replications. For each element width, if we - * cannot find an expansion there's no point checking a larger - * width because we already know by replication it cannot match. - */ - if (v64 == dup_const(MO_16, v64)) { - uint16_t v16 = v64; - - if (is_shimm16(v16, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); - return; - } - if (is_shimm16(~v16, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); - return; - } - - /* - * Otherwise, all remaining constants can be loaded in two insns: - * rd = v16 & 0xff, rd |= v16 & 0xff00. - */ - tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff); - tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8); - return; - } else if (v64 == dup_const(MO_32, v64)) { - uint32_t v32 = v64; - uint32_t n32 = ~v32; - - if (is_shimm32(v32, &cmode, &imm8) || - is_soimm32(v32, &cmode, &imm8) || - is_fimm32(v32, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); - return; - } - if (is_shimm32(n32, &cmode, &imm8) || - is_soimm32(n32, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); - return; - } - - /* - * Restrict the set of constants to those we can load with - * two instructions. Others we load from the pool. - */ - i = is_shimm32_pair(v32, &cmode, &imm8); - if (i) { - tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8); - tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8)); - return; - } - i = is_shimm32_pair(n32, &cmode, &imm8); - if (i) { - tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8); - tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8)); - return; - } - } else if (is_fimm64(v64, &cmode, &imm8)) { - tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8); - return; - } - - /* - * As a last resort, load from the constant pool. Sadly there - * is no LD1R (literal), so store the full 16-byte vector. - */ - if (type == TCG_TYPE_V128) { - new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64); - tcg_out_insn(s, 3305, LDR_v128, 0, rd); - } else { - new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0); - tcg_out_insn(s, 3305, LDR_v64, 0, rd); - } -} - -static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg rd, TCGReg rs) -{ - int is_q = type - TCG_TYPE_V64; - tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); - return true; -} - -static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg r, TCGReg base, intptr_t offset) -{ - TCGReg temp = TCG_REG_TMP; - - if (offset < -0xffffff || offset > 0xffffff) { - tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); - tcg_out_insn(s, 3502, ADD, 1, temp, temp, base); - base = temp; - } else { - AArch64Insn add_insn = I3401_ADDI; - - if (offset < 0) { - add_insn = I3401_SUBI; - offset = -offset; - } - if (offset & 0xfff000) { - tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000); - base = temp; - } - if (offset & 0xfff) { - tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff); - base = temp; - } - } - tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece); - return true; -} - -static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - tcg_target_long value) -{ - tcg_target_long svalue = value; - tcg_target_long ivalue = ~value; - tcg_target_long t0, t1, t2; - int s0, s1; - AArch64Insn opc; - - switch (type) { - case TCG_TYPE_I32: - case TCG_TYPE_I64: - tcg_debug_assert(rd < 32); - break; - - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(rd >= 32); - tcg_out_dupi_vec(s, type, rd, value); - return; - - default: - g_assert_not_reached(); - } - - /* For 32-bit values, discard potential garbage in value. For 64-bit - values within [2**31, 2**32-1], we can create smaller sequences by - interpreting this as a negative 32-bit number, while ensuring that - the high 32 bits are cleared by setting SF=0. */ - if (type == TCG_TYPE_I32 || (value & ~0xffffffffull) == 0) { - svalue = (int32_t)value; - value = (uint32_t)value; - ivalue = (uint32_t)ivalue; - type = TCG_TYPE_I32; - } - - /* Speed things up by handling the common case of small positive - and negative values specially. */ - if ((value & ~0xffffull) == 0) { - tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0); - return; - } else if ((ivalue & ~0xffffull) == 0) { - tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0); - return; - } - - /* Check for bitfield immediates. For the benefit of 32-bit quantities, - use the sign-extended value. That lets us match rotated values such - as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */ - if (is_limm(svalue)) { - tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue); - return; - } - - /* Look for host pointer values within 4G of the PC. This happens - often when loading pointers to QEMU's own data structures. */ - if (type == TCG_TYPE_I64) { - tcg_target_long disp = value - (intptr_t)s->code_ptr; - if (disp == sextract64(disp, 0, 21)) { - tcg_out_insn(s, 3406, ADR, rd, disp); - return; - } - disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); - if (disp == sextract64(disp, 0, 21)) { - tcg_out_insn(s, 3406, ADRP, rd, disp); - if (value & 0xfff) { - tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff); - } - return; - } - } - - /* Would it take fewer insns to begin with MOVN? */ - if (ctpop64(value) >= 32) { - t0 = ivalue; - opc = I3405_MOVN; - } else { - t0 = value; - opc = I3405_MOVZ; - } - s0 = ctz64(t0) & (63 & -16); - t1 = t0 & ~(0xffffUL << s0); - s1 = ctz64(t1) & (63 & -16); - t2 = t1 & ~(0xffffUL << s1); - if (t2 == 0) { - tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); - if (t1 != 0) { - tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); - } - return; - } - - /* For more than 2 insns, dump it into the constant pool. */ - new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); - tcg_out_insn(s, 3305, LDR, 0, rd); -} - -/* Define something more legible for general use. */ -#define tcg_out_ldst_r tcg_out_insn_3310 - -static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, - TCGReg rn, intptr_t offset, int lgsize) -{ - /* If the offset is naturally aligned and in range, then we can - use the scaled uimm12 encoding */ - if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) { - uintptr_t scaled_uimm = offset >> lgsize; - if (scaled_uimm <= 0xfff) { - tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); - return; - } - } - - /* Small signed offsets can use the unscaled encoding. */ - if (offset >= -256 && offset < 256) { - tcg_out_insn_3312(s, insn, rd, rn, offset); - return; - } - - /* Worst-case scenario, move offset to temp register, use reg offset. */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); -} - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ - if (ret == arg) { - return true; - } - switch (type) { - case TCG_TYPE_I32: - case TCG_TYPE_I64: - if (ret < 32 && arg < 32) { - tcg_out_movr(s, type, ret, arg); - break; - } else if (ret < 32) { - tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0); - break; - } else if (arg < 32) { - tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0); - break; - } - /* FALLTHRU */ - - case TCG_TYPE_V64: - tcg_debug_assert(ret >= 32 && arg >= 32); - tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg); - break; - case TCG_TYPE_V128: - tcg_debug_assert(ret >= 32 && arg >= 32); - tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg); - break; - - default: - g_assert_not_reached(); - } - return true; -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg base, intptr_t ofs) -{ - AArch64Insn insn; - int lgsz; - - switch (type) { - case TCG_TYPE_I32: - insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS); - lgsz = 2; - break; - case TCG_TYPE_I64: - insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD); - lgsz = 3; - break; - case TCG_TYPE_V64: - insn = I3312_LDRVD; - lgsz = 3; - break; - case TCG_TYPE_V128: - insn = I3312_LDRVQ; - lgsz = 4; - break; - default: - g_assert_not_reached(); - } - tcg_out_ldst(s, insn, ret, base, ofs, lgsz); -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, - TCGReg base, intptr_t ofs) -{ - AArch64Insn insn; - int lgsz; - - switch (type) { - case TCG_TYPE_I32: - insn = (src < 32 ? I3312_STRW : I3312_STRVS); - lgsz = 2; - break; - case TCG_TYPE_I64: - insn = (src < 32 ? I3312_STRX : I3312_STRVD); - lgsz = 3; - break; - case TCG_TYPE_V64: - insn = I3312_STRVD; - lgsz = 3; - break; - case TCG_TYPE_V128: - insn = I3312_STRVQ; - lgsz = 4; - break; - default: - g_assert_not_reached(); - } - tcg_out_ldst(s, insn, src, base, ofs, lgsz); -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - if (type <= TCG_TYPE_I64 && val == 0) { - tcg_out_st(s, type, TCG_REG_XZR, base, ofs); - return true; - } - return false; -} - -static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd, - TCGReg rn, unsigned int a, unsigned int b) -{ - tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b); -} - -static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, - TCGReg rn, unsigned int a, unsigned int b) -{ - tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b); -} - -static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd, - TCGReg rn, unsigned int a, unsigned int b) -{ - tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b); -} - -static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd, - TCGReg rn, TCGReg rm, unsigned int a) -{ - tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a); -} - -static inline void tcg_out_shl(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, unsigned int m) -{ - int bits = ext ? 64 : 32; - int max = bits - 1; - tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max)); -} - -static inline void tcg_out_shr(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, unsigned int m) -{ - int max = ext ? 63 : 31; - tcg_out_ubfm(s, ext, rd, rn, m & max, max); -} - -static inline void tcg_out_sar(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, unsigned int m) -{ - int max = ext ? 63 : 31; - tcg_out_sbfm(s, ext, rd, rn, m & max, max); -} - -static inline void tcg_out_rotr(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, unsigned int m) -{ - int max = ext ? 63 : 31; - tcg_out_extr(s, ext, rd, rn, rn, m & max); -} - -static inline void tcg_out_rotl(TCGContext *s, TCGType ext, - TCGReg rd, TCGReg rn, unsigned int m) -{ - int bits = ext ? 64 : 32; - int max = bits - 1; - tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max)); -} - -static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd, - TCGReg rn, unsigned lsb, unsigned width) -{ - unsigned size = ext ? 64 : 32; - unsigned a = (size - lsb) & (size - 1); - unsigned b = width - 1; - tcg_out_bfm(s, ext, rd, rn, a, b); -} - -static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, - tcg_target_long b, bool const_b) -{ - if (const_b) { - /* Using CMP or CMN aliases. */ - if (b >= 0) { - tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b); - } else { - tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b); - } - } else { - /* Using CMP alias SUBS wzr, Wn, Wm */ - tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b); - } -} - -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - s->code_ptr; - tcg_debug_assert(offset == sextract64(offset, 0, 26)); - tcg_out_insn(s, 3206, B, offset); -} - -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - s->code_ptr; - if (offset == sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); - } -} - -static inline void tcg_out_callr(TCGContext *s, TCGReg reg) -{ - tcg_out_insn(s, 3207, BLR, reg); -} - -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = target - s->code_ptr; - if (offset == sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_callr(s, TCG_REG_TMP); - } -} - -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) -{ - tcg_insn_unit i1, i2; - TCGType rt = TCG_TYPE_I64; - TCGReg rd = TCG_REG_TMP; - uint64_t pair; - - ptrdiff_t offset = addr - jmp_addr; - - if (offset == sextract64(offset, 0, 26)) { - i1 = I3206_B | ((offset >> 2) & 0x3ffffff); - i2 = NOP; - } else { - offset = (addr >> 12) - (jmp_addr >> 12); - - /* patch ADRP */ - i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd; - /* patch ADDI */ - i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; - } - pair = (uint64_t)i2 << 32 | i1; - atomic_set((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); -} - -static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) -{ - if (!l->has_value) { - tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0); - tcg_out_insn(s, 3206, B, 0); - } else { - tcg_out_goto(s, l->u.value_ptr); - } -} - -static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, - TCGArg b, bool b_const, TCGLabel *l) -{ - intptr_t offset; - bool need_cmp; - - if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) { - need_cmp = false; - } else { - need_cmp = true; - tcg_out_cmp(s, ext, a, b, b_const); - } - - if (!l->has_value) { - tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); - offset = tcg_in32(s) >> 5; - } else { - offset = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(offset == sextract64(offset, 0, 19)); - } - - if (need_cmp) { - tcg_out_insn(s, 3202, B_C, c, offset); - } else if (c == TCG_COND_EQ) { - tcg_out_insn(s, 3201, CBZ, ext, a, offset); - } else { - tcg_out_insn(s, 3201, CBNZ, ext, a, offset); - } -} - -static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn) -{ - tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn); -} - -static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn) -{ - tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn); -} - -static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn) -{ - tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn); -} - -static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits, - TCGReg rd, TCGReg rn) -{ - /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */ - int bits = (8 << s_bits) - 1; - tcg_out_sbfm(s, ext, rd, rn, 0, bits); -} - -static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, - TCGReg rd, TCGReg rn) -{ - /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */ - int bits = (8 << s_bits) - 1; - tcg_out_ubfm(s, 0, rd, rn, 0, bits); -} - -static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, - TCGReg rn, int64_t aimm) -{ - if (aimm >= 0) { - tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm); - } else { - tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm); - } -} - -static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, - TCGReg rh, TCGReg al, TCGReg ah, - tcg_target_long bl, tcg_target_long bh, - bool const_bl, bool const_bh, bool sub) -{ - TCGReg orig_rl = rl; - AArch64Insn insn; - - if (rl == ah || (!const_bh && rl == bh)) { - rl = TCG_REG_TMP; - } - - if (const_bl) { - insn = I3401_ADDSI; - if ((bl < 0) ^ sub) { - insn = I3401_SUBSI; - bl = -bl; - } - if (unlikely(al == TCG_REG_XZR)) { - /* ??? We want to allow al to be zero for the benefit of - negation via subtraction. However, that leaves open the - possibility of adding 0+const in the low part, and the - immediate add instructions encode XSP not XZR. Don't try - anything more elaborate here than loading another zero. */ - al = TCG_REG_TMP; - tcg_out_movi(s, ext, al, 0); - } - tcg_out_insn_3401(s, insn, ext, rl, al, bl); - } else { - tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); - } - - insn = I3503_ADC; - if (const_bh) { - /* Note that the only two constants we support are 0 and -1, and - that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */ - if ((bh != 0) ^ sub) { - insn = I3503_SBC; - } - bh = TCG_REG_XZR; - } else if (sub) { - insn = I3503_SBC; - } - tcg_out_insn_3503(s, insn, ext, rh, ah, bh); - - tcg_out_mov(s, ext, orig_rl, rl); -} - -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - static const uint32_t sync[] = { - [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST, - [TCG_MO_ST_ST] = DMB_ISH | DMB_ST, - [TCG_MO_LD_LD] = DMB_ISH | DMB_LD, - [TCG_MO_LD_ST] = DMB_ISH | DMB_LD, - [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD, - }; - tcg_out32(s, sync[a0 & TCG_MO_ALL]); -} - -static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, - TCGReg a0, TCGArg b, bool const_b, bool is_ctz) -{ - TCGReg a1 = a0; - if (is_ctz) { - a1 = TCG_REG_TMP; - tcg_out_insn(s, 3507, RBIT, ext, a1, a0); - } - if (const_b && b == (ext ? 64 : 32)) { - tcg_out_insn(s, 3507, CLZ, ext, d, a1); - } else { - AArch64Insn sel = I3506_CSEL; - - tcg_out_cmp(s, ext, a0, 0, 1); - tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1); - - if (const_b) { - if (b == -1) { - b = TCG_REG_XZR; - sel = I3506_CSINV; - } else if (b == 0) { - b = TCG_REG_XZR; - } else { - tcg_out_movi(s, ext, d, b); - b = d; - } - } - tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE); - } -} - -#ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.inc.c" - -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * TCGMemOpIdx oi, uintptr_t ra) - */ -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, TCGMemOpIdx oi, - * uintptr_t ra) - */ -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - MemOp size = opc & MO_SIZE; - - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - if (opc & MO_SIGN) { - tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); - } else { - tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0); - } - - tcg_out_goto(s, lb->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - MemOp size = opc & MO_SIZE; - - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - tcg_out_goto(s, lb->raddr); - return true; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_reg, - tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->type = ext; - label->datalo_reg = data_reg; - label->addrlo_reg = addr_reg; - label->raddr = raddr; - label->label_ptr[0] = label_ptr; -} - -/* We expect to use a 7-bit scaled negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); - -/* These offsets are built into the LDP below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8); - -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finalizing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) -{ - unsigned a_bits = get_alignment_bits(opc); - unsigned s_bits = opc & MO_SIZE; - unsigned a_mask = (1u << a_bits) - 1; - unsigned s_mask = (1u << s_bits) - 1; - TCGReg x3; - TCGType mask_type; - uint64_t compare_mask; - - mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64, - TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1. */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); - - /* Load the tlb comparator into X0, and the fast path addend into X1. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, - offsetof(CPUTLBEntry, addend)); - - /* For aligned accesses, we check the first byte and include the alignment - bits within the address. For unaligned access, we check that we don't - cross pages using the address of the last byte of the access. */ - if (a_bits >= s_bits) { - x3 = addr_reg; - } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS == 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 = TCG_REG_X3; - } - compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; - - /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, - TCG_REG_X3, x3, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS == 64, TCG_REG_X0, TCG_REG_X3, 0); - - /* If not equal, we jump to the slow path. */ - *label_ptr = s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); -} - -#endif /* CONFIG_SOFTMMU */ - -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) -{ - const MemOp bswap = memop & MO_BSWAP; - - switch (memop & MO_SSIZE) { - case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); - break; - case MO_SB: - tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); - break; - case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev16(s, data_r, data_r); - } - break; - case MO_SW: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); - tcg_out_rev16(s, data_r, data_r); - tcg_out_sxt(s, ext, MO_16, data_r, data_r); - } else { - tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); - } - break; - case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev32(s, data_r, data_r); - } - break; - case MO_SL: - if (bswap) { - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); - tcg_out_rev32(s, data_r, data_r); - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r); - } else { - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); - } - break; - case MO_Q: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); - if (bswap) { - tcg_out_rev64(s, data_r, data_r); - } - break; - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) -{ - const MemOp bswap = memop & MO_BSWAP; - - switch (memop & MO_SIZE) { - case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); - break; - case MO_16: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev16(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); - break; - case MO_32: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev32(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); - break; - case MO_64: - if (bswap && data_r != TCG_REG_XZR) { - tcg_out_rev64(s, TCG_REG_TMP, data_r); - data_r = TCG_REG_TMP; - } - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); - break; - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOpIdx oi, TCGType ext) -{ - MemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); - } else { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); - } -#endif /* CONFIG_SOFTMMU */ -} - -static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOpIdx oi) -{ - MemOp memop = get_memop(oi); - const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - if (USE_GUEST_BASE) { - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); - } else { - tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); - } -#endif /* CONFIG_SOFTMMU */ -} - -static tcg_insn_unit *tb_ret_addr; - -static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - /* 99% of the time, we can signal the use of extension registers - by looking to see if the opcode handles 64-bit data. */ - TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0; - - /* Hoist the loads of the most common arguments. */ - TCGArg a0 = args[0]; - TCGArg a1 = args[1]; - TCGArg a2 = args[2]; - int c2 = const_args[2]; - - /* Some operands are defined with "rZ" constraint, a register or - the zero register. These need not actually test args[I] == 0. */ -#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I]) - - switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 == 0) { - tcg_out_goto_long(s, s->code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); - tcg_out_goto_long(s, tb_ret_addr); - } - break; - - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset != NULL) { - /* TCG_TARGET_HAS_direct_jump */ - /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic - write can be used to patch the target address. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* actual branch destination will be patched by - tb_target_set_jmp_target later. */ - tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0); - } else { - /* !TCG_TARGET_HAS_direct_jump */ - tcg_debug_assert(s->tb_jmp_target_addr != NULL); - intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2; - tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); - } - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); - set_jmp_reset_offset(s, a0); - break; - - case INDEX_op_goto_ptr: - tcg_out_insn(s, 3207, BR, a0); - break; - - case INDEX_op_br: - tcg_out_goto_label(s, arg_label(a0)); - break; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0); - break; - case INDEX_op_ld8s_i32: - tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0); - break; - case INDEX_op_ld8s_i64: - tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0); - break; - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1); - break; - case INDEX_op_ld16s_i32: - tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1); - break; - case INDEX_op_ld16s_i64: - tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1); - break; - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2); - break; - case INDEX_op_ld32s_i64: - tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2); - break; - case INDEX_op_ld_i64: - tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3); - break; - - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0); - break; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1); - break; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2); - break; - case INDEX_op_st_i64: - tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3); - break; - - case INDEX_op_add_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_add_i64: - if (c2) { - tcg_out_addsubi(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2); - } - break; - - case INDEX_op_sub_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_sub_i64: - if (c2) { - tcg_out_addsubi(s, ext, a0, a1, -a2); - } else { - tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2); - } - break; - - case INDEX_op_neg_i64: - case INDEX_op_neg_i32: - tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1); - break; - - case INDEX_op_and_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_and_i64: - if (c2) { - tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3510, AND, ext, a0, a1, a2); - } - break; - - case INDEX_op_andc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_andc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); - } - break; - - case INDEX_op_or_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_or_i64: - if (c2) { - tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2); - } - break; - - case INDEX_op_orc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_orc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); - } - break; - - case INDEX_op_xor_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_xor_i64: - if (c2) { - tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2); - } - break; - - case INDEX_op_eqv_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_eqv_i64: - if (c2) { - tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); - } - break; - - case INDEX_op_not_i64: - case INDEX_op_not_i32: - tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1); - break; - - case INDEX_op_mul_i64: - case INDEX_op_mul_i32: - tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR); - break; - - case INDEX_op_div_i64: - case INDEX_op_div_i32: - tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2); - break; - case INDEX_op_divu_i64: - case INDEX_op_divu_i32: - tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2); - break; - - case INDEX_op_rem_i64: - case INDEX_op_rem_i32: - tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); - break; - case INDEX_op_remu_i64: - case INDEX_op_remu_i32: - tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); - break; - - case INDEX_op_shl_i64: - case INDEX_op_shl_i32: - if (c2) { - tcg_out_shl(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2); - } - break; - - case INDEX_op_shr_i64: - case INDEX_op_shr_i32: - if (c2) { - tcg_out_shr(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2); - } - break; - - case INDEX_op_sar_i64: - case INDEX_op_sar_i32: - if (c2) { - tcg_out_sar(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2); - } - break; - - case INDEX_op_rotr_i64: - case INDEX_op_rotr_i32: - if (c2) { - tcg_out_rotr(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2); - } - break; - - case INDEX_op_rotl_i64: - case INDEX_op_rotl_i32: - if (c2) { - tcg_out_rotl(s, ext, a0, a1, a2); - } else { - tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2); - tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP); - } - break; - - case INDEX_op_clz_i64: - case INDEX_op_clz_i32: - tcg_out_cltz(s, ext, a0, a1, a2, c2, false); - break; - case INDEX_op_ctz_i64: - case INDEX_op_ctz_i32: - tcg_out_cltz(s, ext, a0, a1, a2, c2, true); - break; - - case INDEX_op_brcond_i32: - a1 = (int32_t)a1; - /* FALLTHRU */ - case INDEX_op_brcond_i64: - tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3])); - break; - - case INDEX_op_setcond_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_setcond_i64: - tcg_out_cmp(s, ext, a1, a2, c2); - /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */ - tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR, - TCG_REG_XZR, tcg_invert_cond(args[3])); - break; - - case INDEX_op_movcond_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_movcond_i64: - tcg_out_cmp(s, ext, a1, a2, c2); - tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]); - break; - - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, ext); - break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, REG0(0), a1, a2); - break; - - case INDEX_op_bswap64_i64: - tcg_out_rev64(s, a0, a1); - break; - case INDEX_op_bswap32_i64: - case INDEX_op_bswap32_i32: - tcg_out_rev32(s, a0, a1); - break; - case INDEX_op_bswap16_i64: - case INDEX_op_bswap16_i32: - tcg_out_rev16(s, a0, a1); - break; - - case INDEX_op_ext8s_i64: - case INDEX_op_ext8s_i32: - tcg_out_sxt(s, ext, MO_8, a0, a1); - break; - case INDEX_op_ext16s_i64: - case INDEX_op_ext16s_i32: - tcg_out_sxt(s, ext, MO_16, a0, a1); - break; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); - break; - case INDEX_op_ext8u_i64: - case INDEX_op_ext8u_i32: - tcg_out_uxt(s, MO_8, a0, a1); - break; - case INDEX_op_ext16u_i64: - case INDEX_op_ext16u_i32: - tcg_out_uxt(s, MO_16, a0, a1); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_movr(s, TCG_TYPE_I32, a0, a1); - break; - - case INDEX_op_deposit_i64: - case INDEX_op_deposit_i32: - tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]); - break; - - case INDEX_op_extract_i64: - case INDEX_op_extract_i32: - tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1); - break; - - case INDEX_op_sextract_i64: - case INDEX_op_sextract_i32: - tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1); - break; - - case INDEX_op_extract2_i64: - case INDEX_op_extract2_i32: - tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]); - break; - - case INDEX_op_add2_i32: - tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), - (int32_t)args[4], args[5], const_args[4], - const_args[5], false); - break; - case INDEX_op_add2_i64: - tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], - args[5], const_args[4], const_args[5], false); - break; - case INDEX_op_sub2_i32: - tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), - (int32_t)args[4], args[5], const_args[4], - const_args[5], true); - break; - case INDEX_op_sub2_i64: - tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4], - args[5], const_args[4], const_args[5], true); - break; - - case INDEX_op_muluh_i64: - tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); - break; - case INDEX_op_mulsh_i64: - tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - g_assert_not_reached(); - } - -#undef REG0 -} - -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, - unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) -{ - static const AArch64Insn cmp_insn[16] = { - [TCG_COND_EQ] = I3616_CMEQ, - [TCG_COND_GT] = I3616_CMGT, - [TCG_COND_GE] = I3616_CMGE, - [TCG_COND_GTU] = I3616_CMHI, - [TCG_COND_GEU] = I3616_CMHS, - }; - static const AArch64Insn cmp0_insn[16] = { - [TCG_COND_EQ] = I3617_CMEQ0, - [TCG_COND_GT] = I3617_CMGT0, - [TCG_COND_GE] = I3617_CMGE0, - [TCG_COND_LT] = I3617_CMLT0, - [TCG_COND_LE] = I3617_CMLE0, - }; - - TCGType type = vecl + TCG_TYPE_V64; - unsigned is_q = vecl; - TCGArg a0, a1, a2, a3; - int cmode, imm8; - - a0 = args[0]; - a1 = args[1]; - a2 = args[2]; - - switch (opc) { - case INDEX_op_ld_vec: - tcg_out_ld(s, type, a0, a1, a2); - break; - case INDEX_op_st_vec: - tcg_out_st(s, type, a0, a1, a2); - break; - case INDEX_op_dupm_vec: - tcg_out_dupm_vec(s, type, vece, a0, a1, a2); - break; - case INDEX_op_add_vec: - tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); - break; - case INDEX_op_sub_vec: - tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); - break; - case INDEX_op_mul_vec: - tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2); - break; - case INDEX_op_neg_vec: - tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); - break; - case INDEX_op_abs_vec: - tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); - break; - case INDEX_op_and_vec: - if (const_args[2]) { - is_shimm1632(~a2, &cmode, &imm8); - if (a0 == a1) { - tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); - return; - } - tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); - a2 = a0; - } - tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); - break; - case INDEX_op_or_vec: - if (const_args[2]) { - is_shimm1632(a2, &cmode, &imm8); - if (a0 == a1) { - tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); - return; - } - tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); - a2 = a0; - } - tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2); - break; - case INDEX_op_andc_vec: - if (const_args[2]) { - is_shimm1632(a2, &cmode, &imm8); - if (a0 == a1) { - tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8); - return; - } - tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8); - a2 = a0; - } - tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2); - break; - case INDEX_op_orc_vec: - if (const_args[2]) { - is_shimm1632(~a2, &cmode, &imm8); - if (a0 == a1) { - tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8); - return; - } - tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8); - a2 = a0; - } - tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); - break; - case INDEX_op_xor_vec: - tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); - break; - case INDEX_op_ssadd_vec: - tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); - break; - case INDEX_op_sssub_vec: - tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); - break; - case INDEX_op_usadd_vec: - tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); - break; - case INDEX_op_ussub_vec: - tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); - break; - case INDEX_op_smax_vec: - tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); - break; - case INDEX_op_smin_vec: - tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2); - break; - case INDEX_op_umax_vec: - tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2); - break; - case INDEX_op_umin_vec: - tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2); - break; - case INDEX_op_not_vec: - tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); - break; - case INDEX_op_shli_vec: - tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); - break; - case INDEX_op_shri_vec: - tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); - break; - case INDEX_op_sari_vec: - tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); - break; - case INDEX_op_aa64_sli_vec: - tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); - break; - case INDEX_op_shlv_vec: - tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); - break; - case INDEX_op_aa64_sshl_vec: - tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); - break; - case INDEX_op_cmp_vec: - { - TCGCond cond = args[3]; - AArch64Insn insn; - - if (cond == TCG_COND_NE) { - if (const_args[2]) { - tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); - } else { - tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); - tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); - } - } else { - if (const_args[2]) { - insn = cmp0_insn[cond]; - if (insn) { - tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); - break; - } - tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0); - a2 = TCG_VEC_TMP; - } - insn = cmp_insn[cond]; - if (insn == 0) { - TCGArg t; - t = a1, a1 = a2, a2 = t; - cond = tcg_swap_cond(cond); - insn = cmp_insn[cond]; - tcg_debug_assert(insn != 0); - } - tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); - } - } - break; - - case INDEX_op_bitsel_vec: - a3 = args[3]; - if (a0 == a3) { - tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1); - } else if (a0 == a2) { - tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1); - } else { - if (a0 != a1) { - tcg_out_mov(s, type, a0, a1); - } - tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3); - } - break; - - case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ - case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ - default: - g_assert_not_reached(); - } -} - -int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) -{ - switch (opc) { - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_orc_vec: - case INDEX_op_neg_vec: - case INDEX_op_abs_vec: - case INDEX_op_not_vec: - case INDEX_op_cmp_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - case INDEX_op_shlv_vec: - case INDEX_op_bitsel_vec: - return 1; - case INDEX_op_rotli_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_rotlv_vec: - case INDEX_op_rotrv_vec: - return -1; - case INDEX_op_mul_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - return vece < MO_64; - - default: - return 0; - } -} - -void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, - TCGArg a0, ...) -{ - va_list va; - TCGv_vec v0, v1, v2, t1, t2; - TCGArg a2; - - va_start(va, a0); - v0 = temp_tcgv_vec(arg_temp(a0)); - v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - a2 = va_arg(va, TCGArg); - v2 = temp_tcgv_vec(arg_temp(a2)); - - switch (opc) { - case INDEX_op_rotli_vec: - t1 = tcg_temp_new_vec(type); - tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1)); - vec_gen_4(INDEX_op_aa64_sli_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - /* Right shifts are negative left shifts for AArch64. */ - t1 = tcg_temp_new_vec(type); - tcg_gen_neg_vec(vece, t1, v2); - opc = (opc == INDEX_op_shrv_vec - ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec); - vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_rotlv_vec: - t1 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t1, 8 << vece); - tcg_gen_sub_vec(vece, t1, v2, t1); - /* Right shifts are negative left shifts for AArch64. */ - vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - tcg_gen_or_vec(vece, v0, v0, t1); - tcg_temp_free_vec(t1); - break; - - case INDEX_op_rotrv_vec: - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - tcg_gen_neg_vec(vece, t1, v2); - tcg_gen_dupi_vec(vece, t2, 8 << vece); - tcg_gen_add_vec(vece, t2, t1, t2); - /* Right shifts are negative left shifts for AArch64. */ - vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2), - tcgv_vec_arg(v1), tcgv_vec_arg(t2)); - tcg_gen_or_vec(vece, v0, t1, t2); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; - - default: - g_assert_not_reached(); - } - - va_end(va); -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } }; - static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } }; - static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } }; - static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } }; - static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } }; - static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } }; - static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } }; - static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } }; - static const TCGTargetOpDef r_r_rAL - = { .args_ct_str = { "r", "r", "rAL" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; - static const TCGTargetOpDef w_w_w_w - = { .args_ct_str = { "w", "w", "w", "w" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_neg_i32: - case INDEX_op_neg_i64: - case INDEX_op_not_i32: - case INDEX_op_not_i64: - case INDEX_op_bswap16_i32: - case INDEX_op_bswap32_i32: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_ext8s_i32: - case INDEX_op_ext16s_i32: - case INDEX_op_ext8u_i32: - case INDEX_op_ext16u_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext16s_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext8u_i64: - case INDEX_op_ext16u_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extract_i32: - case INDEX_op_extract_i64: - case INDEX_op_sextract_i32: - case INDEX_op_sextract_i64: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return &rZ_r; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_rA; - - case INDEX_op_mul_i32: - case INDEX_op_mul_i64: - case INDEX_op_div_i32: - case INDEX_op_div_i64: - case INDEX_op_divu_i32: - case INDEX_op_divu_i64: - case INDEX_op_rem_i32: - case INDEX_op_rem_i64: - case INDEX_op_remu_i32: - case INDEX_op_remu_i64: - case INDEX_op_muluh_i64: - case INDEX_op_mulsh_i64: - return &r_r_r; - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - case INDEX_op_or_i32: - case INDEX_op_or_i64: - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - case INDEX_op_orc_i32: - case INDEX_op_orc_i64: - case INDEX_op_eqv_i32: - case INDEX_op_eqv_i64: - return &r_r_rL; - - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i64: - return &r_r_ri; - - case INDEX_op_clz_i32: - case INDEX_op_ctz_i32: - case INDEX_op_clz_i64: - case INDEX_op_ctz_i64: - return &r_r_rAL; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &r_rA; - - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - return &movc; - - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - return &r_l; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return &lZ_l; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - return &dep; - - case INDEX_op_extract2_i32: - case INDEX_op_extract2_i64: - return &ext2; - - case INDEX_op_add2_i32: - case INDEX_op_add2_i64: - case INDEX_op_sub2_i32: - case INDEX_op_sub2_i64: - return &add2; - - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_mul_vec: - case INDEX_op_xor_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_aa64_sshl_vec: - return &w_w_w; - case INDEX_op_not_vec: - case INDEX_op_neg_vec: - case INDEX_op_abs_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - return &w_w; - case INDEX_op_ld_vec: - case INDEX_op_st_vec: - case INDEX_op_dupm_vec: - return &w_r; - case INDEX_op_dup_vec: - return &w_wr; - case INDEX_op_or_vec: - case INDEX_op_andc_vec: - return &w_w_wO; - case INDEX_op_and_vec: - case INDEX_op_orc_vec: - return &w_w_wN; - case INDEX_op_cmp_vec: - return &w_w_wZ; - case INDEX_op_bitsel_vec: - return &w_w_w_w; - case INDEX_op_aa64_sli_vec: - return &w_0_w; - - default: - return NULL; - } -} - -static void tcg_target_init(TCGContext *s) -{ - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; - tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; - tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; - - tcg_target_call_clobber_regs = -1ull; - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */ - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); -} - -/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ -#define PUSH_SIZE ((30 - 19 + 1) * 8) - -#define FRAME_SIZE \ - ((PUSH_SIZE \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long) \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & ~(TCG_TARGET_STACK_ALIGN - 1)) - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); - -/* We're expecting to use a single ADDI insn. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff); - -static void tcg_target_qemu_prologue(TCGContext *s) -{ - TCGReg r; - - /* Push (FP, LR) and allocate space for all saved registers. */ - tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR, - TCG_REG_SP, -PUSH_SIZE, 1, 1); - - /* Set up frame pointer for canonical unwinding. */ - tcg_out_movr_sp(s, TCG_TYPE_I64, TCG_REG_FP, TCG_REG_SP); - - /* Store callee-preserved regs x19..x28. */ - for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { - int ofs = (r - TCG_REG_X19 + 2) * 8; - tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0); - } - - /* Make stack space for TCG locals. */ - tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, - FRAME_SIZE - PUSH_SIZE); - - /* Inform TCG about how to find TCG locals with register, offset, size. */ - tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - -#if !defined(CONFIG_SOFTMMU) - if (USE_GUEST_BASE) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); - } -#endif - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]); - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); - - /* TB epilogue */ - tb_ret_addr = s->code_ptr; - - /* Remove TCG locals stack space. */ - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, - FRAME_SIZE - PUSH_SIZE); - - /* Restore registers x19..x28. */ - for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { - int ofs = (r - TCG_REG_X19 + 2) * 8; - tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0); - } - - /* Pop (FP, LR), restore SP to previous frame. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR, - TCG_REG_SP, PUSH_SIZE, 0, 1); - tcg_out_insn(s, 3207, RET, TCG_REG_LR); -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i = 0; i < count; ++i) { - p[i] = NOP; - } -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[24]; -} DebugFrame; - -#define ELF_HOST_MACHINE EM_AARCH64 - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x78, /* sleb128 -8 */ - .h.cie.return_column = TCG_REG_LR, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x80 + 28, 1, /* DW_CFA_offset, x28, -8 */ - 0x80 + 27, 2, /* DW_CFA_offset, x27, -16 */ - 0x80 + 26, 3, /* DW_CFA_offset, x26, -24 */ - 0x80 + 25, 4, /* DW_CFA_offset, x25, -32 */ - 0x80 + 24, 5, /* DW_CFA_offset, x24, -40 */ - 0x80 + 23, 6, /* DW_CFA_offset, x23, -48 */ - 0x80 + 22, 7, /* DW_CFA_offset, x22, -56 */ - 0x80 + 21, 8, /* DW_CFA_offset, x21, -64 */ - 0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */ - 0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */ - 0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */ - 0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */ - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc new file mode 100644 index 0000000000..bc1e1b5a71 --- /dev/null +++ b/tcg/arm/tcg-target.c.inc @@ -0,0 +1,2362 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Andrzej Zaborowski + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "elf.h" +#include "../tcg-pool.c.inc" + +int arm_arch = __ARM_ARCH; + +#ifndef use_idiv_instructions +bool use_idiv_instructions; +#endif + +/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ +#ifdef CONFIG_SOFTMMU +# define USING_SOFTMMU 1 +#else +# define USING_SOFTMMU 0 +#endif + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "%r0", + "%r1", + "%r2", + "%r3", + "%r4", + "%r5", + "%r6", + "%r7", + "%r8", + "%r9", + "%r10", + "%r11", + "%r12", + "%r13", + "%r14", + "%pc", +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R13, + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R12, + TCG_REG_R14, +}; + +static const int tcg_target_call_iarg_regs[4] = { + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 +}; +static const int tcg_target_call_oarg_regs[2] = { + TCG_REG_R0, TCG_REG_R1 +}; + +#define TCG_REG_TMP TCG_REG_R12 + +enum arm_cond_code_e { + COND_EQ = 0x0, + COND_NE = 0x1, + COND_CS = 0x2, /* Unsigned greater or equal */ + COND_CC = 0x3, /* Unsigned less than */ + COND_MI = 0x4, /* Negative */ + COND_PL = 0x5, /* Zero or greater */ + COND_VS = 0x6, /* Overflow */ + COND_VC = 0x7, /* No overflow */ + COND_HI = 0x8, /* Unsigned greater than */ + COND_LS = 0x9, /* Unsigned less or equal */ + COND_GE = 0xa, + COND_LT = 0xb, + COND_GT = 0xc, + COND_LE = 0xd, + COND_AL = 0xe, +}; + +#define TO_CPSR (1 << 20) + +#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) +#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) +#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) +#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) +#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) +#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) +#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) +#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) + +typedef enum { + ARITH_AND = 0x0 << 21, + ARITH_EOR = 0x1 << 21, + ARITH_SUB = 0x2 << 21, + ARITH_RSB = 0x3 << 21, + ARITH_ADD = 0x4 << 21, + ARITH_ADC = 0x5 << 21, + ARITH_SBC = 0x6 << 21, + ARITH_RSC = 0x7 << 21, + ARITH_TST = 0x8 << 21 | TO_CPSR, + ARITH_CMP = 0xa << 21 | TO_CPSR, + ARITH_CMN = 0xb << 21 | TO_CPSR, + ARITH_ORR = 0xc << 21, + ARITH_MOV = 0xd << 21, + ARITH_BIC = 0xe << 21, + ARITH_MVN = 0xf << 21, + + INSN_CLZ = 0x016f0f10, + INSN_RBIT = 0x06ff0f30, + + INSN_LDR_IMM = 0x04100000, + INSN_LDR_REG = 0x06100000, + INSN_STR_IMM = 0x04000000, + INSN_STR_REG = 0x06000000, + + INSN_LDRH_IMM = 0x005000b0, + INSN_LDRH_REG = 0x001000b0, + INSN_LDRSH_IMM = 0x005000f0, + INSN_LDRSH_REG = 0x001000f0, + INSN_STRH_IMM = 0x004000b0, + INSN_STRH_REG = 0x000000b0, + + INSN_LDRB_IMM = 0x04500000, + INSN_LDRB_REG = 0x06500000, + INSN_LDRSB_IMM = 0x005000d0, + INSN_LDRSB_REG = 0x001000d0, + INSN_STRB_IMM = 0x04400000, + INSN_STRB_REG = 0x06400000, + + INSN_LDRD_IMM = 0x004000d0, + INSN_LDRD_REG = 0x000000d0, + INSN_STRD_IMM = 0x004000f0, + INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0xf57ff05b, + INSN_DMB_MCR = 0xee070fba, + + /* Architected nop introduced in v6k. */ + /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this + also Just So Happened to do nothing on pre-v6k so that we + don't need to conditionalize it? */ + INSN_NOP_v6k = 0xe320f000, + /* Otherwise the assembler uses mov r0,r0 */ + INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, +} ARMInsn; + +#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) + +static const uint8_t tcg_cond_to_arm_cond[] = { + [TCG_COND_EQ] = COND_EQ, + [TCG_COND_NE] = COND_NE, + [TCG_COND_LT] = COND_LT, + [TCG_COND_GE] = COND_GE, + [TCG_COND_LE] = COND_LE, + [TCG_COND_GT] = COND_GT, + /* unsigned */ + [TCG_COND_LTU] = COND_CC, + [TCG_COND_GEU] = COND_CS, + [TCG_COND_LEU] = COND_LS, + [TCG_COND_GTU] = COND_HI, +}; + +static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; + if (offset == sextract32(offset, 0, 24)) { + *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + return true; + } + return false; +} + +static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8; + + if (offset >= -0xfff && offset <= 0xfff) { + tcg_insn_unit insn = *code_ptr; + bool u = (offset >= 0); + if (!u) { + offset = -offset; + } + insn = deposit32(insn, 23, 1, u); + insn = deposit32(insn, 0, 12, offset); + *code_ptr = insn; + return true; + } + return false; +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(addend == 0); + + if (type == R_ARM_PC24) { + return reloc_pc24(code_ptr, (tcg_insn_unit *)value); + } else if (type == R_ARM_PC13) { + return reloc_pc13(code_ptr, (tcg_insn_unit *)value); + } else { + g_assert_not_reached(); + } +} + +#define TCG_CT_CONST_ARM 0x100 +#define TCG_CT_CONST_INV 0x200 +#define TCG_CT_CONST_NEG 0x400 +#define TCG_CT_CONST_ZERO 0x800 + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'I': + ct->ct |= TCG_CT_CONST_ARM; + break; + case 'K': + ct->ct |= TCG_CT_CONST_INV; + break; + case 'N': /* The gcc constraint letter is L, already used here. */ + ct->ct |= TCG_CT_CONST_NEG; + break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; + + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffff; + break; + + /* qemu_ld address */ + case 'l': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffff; +#ifdef CONFIG_SOFTMMU + /* r0-r2,lr will be overwritten when reading the tlb entry, + so don't use these. */ + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); +#endif + break; + + /* qemu_st address & data */ + case 's': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffff; + /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) + and r0-r1 doing the byte swapping, so don't use these. */ + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); +#if defined(CONFIG_SOFTMMU) + /* Avoid clashes with registers being used for helper args */ + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); +#if TARGET_LONG_BITS == 64 + /* Avoid clashes with registers being used for helper args */ + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); +#endif + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); +#endif + break; + + default: + return NULL; + } + return ct_str; +} + +static inline uint32_t rotl(uint32_t val, int n) +{ + return (val << n) | (val >> (32 - n)); +} + +/* ARM immediates for ALU instructions are made of an unsigned 8-bit + right-rotated by an even amount between 0 and 30. */ +static inline int encode_imm(uint32_t imm) +{ + int shift; + + /* simple case, only lower bits */ + if ((imm & ~0xff) == 0) + return 0; + /* then try a simple even shift */ + shift = ctz32(imm) & ~1; + if (((imm >> shift) & ~0xff) == 0) + return 32 - shift; + /* now try harder with rotations */ + if ((rotl(imm, 2) & ~0xff) == 0) + return 2; + if ((rotl(imm, 4) & ~0xff) == 0) + return 4; + if ((rotl(imm, 6) & ~0xff) == 0) + return 6; + /* imm can't be encoded */ + return -1; +} + +static inline int check_fit_imm(uint32_t imm) +{ + return encode_imm(imm) >= 0; +} + +/* Test if a constant matches the constraint. + * TODO: define constraints for: + * + * ldr/str offset: between -0xfff and 0xfff + * ldrh/strh offset: between -0xff and 0xff + * mov operand2: values represented with x << (2 * y), x < 0x100 + * add, sub, eor...: ditto + */ +static inline int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct; + ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { + return 1; + } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { + return 1; + } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { + return 1; + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } else { + return 0; + } +} + +static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) +{ + tcg_out32(s, (cond << 28) | 0x0a000000 | + (((offset - 8) >> 2) & 0x00ffffff)); +} + +static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) +{ + tcg_out32(s, (cond << 28) | 0x0b000000 | + (((offset - 8) >> 2) & 0x00ffffff)); +} + +static inline void tcg_out_blx(TCGContext *s, int cond, int rn) +{ + tcg_out32(s, (cond << 28) | 0x012fff30 | rn); +} + +static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) +{ + tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | + (((offset - 8) >> 2) & 0x00ffffff)); +} + +static inline void tcg_out_dat_reg(TCGContext *s, + int cond, int opc, int rd, int rn, int rm, int shift) +{ + tcg_out32(s, (cond << 28) | (0 << 25) | opc | + (rn << 16) | (rd << 12) | shift | rm); +} + +static inline void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, INSN_NOP); +} + +static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +{ + /* Simple reg-reg move, optimising out the 'do nothing' case */ + if (rd != rm) { + tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); + } +} + +static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) +{ + /* Unless the C portion of QEMU is compiled as thumb, we don't + actually need true BX semantics; merely a branch to an address + held in a register. */ + if (use_armv5t_instructions) { + tcg_out32(s, (cond << 28) | 0x012fff10 | rn); + } else { + tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); + } +} + +static inline void tcg_out_dat_imm(TCGContext *s, + int cond, int opc, int rd, int rn, int im) +{ + tcg_out32(s, (cond << 28) | (1 << 25) | opc | + (rn << 16) | (rd << 12) | im); +} + +/* Note that this routine is used for both LDR and LDRH formats, so we do + not wish to include an immediate shift at this point. */ +static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, TCGReg rm, bool u, bool p, bool w) +{ + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) + | (w << 21) | (rn << 16) | (rt << 12) | rm); +} + +static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, int imm8, bool p, bool w) +{ + bool u = 1; + if (imm8 < 0) { + imm8 = -imm8; + u = 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); +} + +static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, int imm12, bool p, bool w) +{ + bool u = 1; + if (imm12 < 0) { + imm12 = -imm12; + u = 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | imm12); +} + +static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); +} + +/* Register pre-increment with base writeback. */ +static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); +} + +static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg) +{ + new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); + tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); +} + +static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) +{ + int rot, diff, opc, sh1, sh2; + uint32_t tt0, tt1, tt2; + + /* Check a single MOV/MVN before anything else. */ + rot = encode_imm(arg); + if (rot >= 0) { + tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, + rotl(arg, rot) | (rot << 7)); + return; + } + rot = encode_imm(~arg); + if (rot >= 0) { + tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, + rotl(~arg, rot) | (rot << 7)); + return; + } + + /* Check for a pc-relative address. This will usually be the TB, + or within the TB, which is immediately before the code block. */ + diff = arg - ((intptr_t)s->code_ptr + 8); + if (diff >= 0) { + rot = encode_imm(diff); + if (rot >= 0) { + tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, + rotl(diff, rot) | (rot << 7)); + return; + } + } else { + rot = encode_imm(-diff); + if (rot >= 0) { + tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, + rotl(-diff, rot) | (rot << 7)); + return; + } + } + + /* Use movw + movt. */ + if (use_armv7_instructions) { + /* movw */ + tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) + | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); + if (arg & 0xffff0000) { + /* movt */ + tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) + | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); + } + return; + } + + /* Look for sequences of two insns. If we have lots of 1's, we can + shorten the sequence by beginning with mvn and then clearing + higher bits with eor. */ + tt0 = arg; + opc = ARITH_MOV; + if (ctpop32(arg) > 16) { + tt0 = ~arg; + opc = ARITH_MVN; + } + sh1 = ctz32(tt0) & ~1; + tt1 = tt0 & ~(0xff << sh1); + sh2 = ctz32(tt1) & ~1; + tt2 = tt1 & ~(0xff << sh2); + if (tt2 == 0) { + rot = ((32 - sh1) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); + rot = ((32 - sh2) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, + ((tt0 >> sh2) & 0xff) | rot); + return; + } + + /* Otherwise, drop it into the constant pool. */ + tcg_out_movi_pool(s, cond, rd, arg); +} + +static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, + TCGArg lhs, TCGArg rhs, int rhs_is_const) +{ + /* Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rI" constraint. + */ + if (rhs_is_const) { + int rot = encode_imm(rhs); + tcg_debug_assert(rot >= 0); + tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); + } else { + tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); + } +} + +static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, + TCGReg dst, TCGReg lhs, TCGArg rhs, + bool rhs_is_const) +{ + /* Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIK" constraint. + */ + if (rhs_is_const) { + int rot = encode_imm(rhs); + if (rot < 0) { + rhs = ~rhs; + rot = encode_imm(rhs); + tcg_debug_assert(rot >= 0); + opc = opinv; + } + tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); + } else { + tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); + } +} + +static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg, + TCGArg dst, TCGArg lhs, TCGArg rhs, + bool rhs_is_const) +{ + /* Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIN" constraint. + */ + if (rhs_is_const) { + int rot = encode_imm(rhs); + if (rot < 0) { + rhs = -rhs; + rot = encode_imm(rhs); + tcg_debug_assert(rot >= 0); + opc = opneg; + } + tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); + } else { + tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); + } +} + +static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, + TCGReg rn, TCGReg rm) +{ + /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */ + if (!use_armv6_instructions && rd == rn) { + if (rd == rm) { + /* rd == rn == rm; copy an input to tmp first. */ + tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); + rm = rn = TCG_REG_TMP; + } else { + rn = rm; + rm = rd; + } + } + /* mul */ + tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); +} + +static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) +{ + /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */ + if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) { + if (rd0 == rm || rd1 == rm) { + tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); + rn = TCG_REG_TMP; + } else { + TCGReg t = rn; + rn = rm; + rm = t; + } + } + /* umull */ + tcg_out32(s, (cond << 28) | 0x00800090 | + (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); +} + +static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, + TCGReg rd1, TCGReg rn, TCGReg rm) +{ + /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */ + if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) { + if (rd0 == rm || rd1 == rm) { + tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); + rn = TCG_REG_TMP; + } else { + TCGReg t = rn; + rn = rm; + rm = t; + } + } + /* smull */ + tcg_out32(s, (cond << 28) | 0x00c00090 | + (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); +} + +static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + +static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + +static inline void tcg_out_ext8s(TCGContext *s, int cond, + int rd, int rn) +{ + if (use_armv6_instructions) { + /* sxtb */ + tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rn, SHIFT_IMM_LSL(24)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rd, SHIFT_IMM_ASR(24)); + } +} + +static inline void tcg_out_ext8u(TCGContext *s, int cond, + int rd, int rn) +{ + tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); +} + +static inline void tcg_out_ext16s(TCGContext *s, int cond, + int rd, int rn) +{ + if (use_armv6_instructions) { + /* sxth */ + tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rn, SHIFT_IMM_LSL(16)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rd, SHIFT_IMM_ASR(16)); + } +} + +static inline void tcg_out_ext16u(TCGContext *s, int cond, + int rd, int rn) +{ + if (use_armv6_instructions) { + /* uxth */ + tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rn, SHIFT_IMM_LSL(16)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rd, SHIFT_IMM_LSR(16)); + } +} + +static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn) +{ + if (use_armv6_instructions) { + /* revsh */ + tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16)); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8)); + } +} + +static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) +{ + if (use_armv6_instructions) { + /* rev16 */ + tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24)); + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16)); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8)); + } +} + +/* swap the two low bytes assuming that the two high input bytes and the + two high output bit can hold any value. */ +static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn) +{ + if (use_armv6_instructions) { + /* rev16 */ + tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8)); + tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8)); + } +} + +static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) +{ + if (use_armv6_instructions) { + /* rev */ + tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_EOR, + TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16)); + tcg_out_dat_imm(s, cond, ARITH_BIC, + TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800); + tcg_out_dat_reg(s, cond, ARITH_MOV, + rd, 0, rn, SHIFT_IMM_ROR(8)); + tcg_out_dat_reg(s, cond, ARITH_EOR, + rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8)); + } +} + +static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) +{ + if (const_a1) { + /* bfi becomes bfc with rn == 15. */ + a1 = 15; + } + /* bfi/bfc */ + tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((ofs + len - 1) << 16)); +} + +static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) +{ + /* ubfx */ + tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((len - 1) << 16)); +} + +static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len) +{ + /* sbfx */ + tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((len - 1) << 16)); +} + +static inline void tcg_out_ld32u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xfff || offset < -0xfff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_ld32_12(s, cond, rd, rn, offset); +} + +static inline void tcg_out_st32(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xfff || offset < -0xfff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_st32_12(s, cond, rd, rn, offset); +} + +static inline void tcg_out_ld16u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xff || offset < -0xff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_ld16u_8(s, cond, rd, rn, offset); +} + +static inline void tcg_out_ld16s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xff || offset < -0xff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_ld16s_8(s, cond, rd, rn, offset); +} + +static inline void tcg_out_st16(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xff || offset < -0xff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_st16_8(s, cond, rd, rn, offset); +} + +static inline void tcg_out_ld8u(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xfff || offset < -0xfff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_ld8_12(s, cond, rd, rn, offset); +} + +static inline void tcg_out_ld8s(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xff || offset < -0xff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_ld8s_8(s, cond, rd, rn, offset); +} + +static inline void tcg_out_st8(TCGContext *s, int cond, + int rd, int rn, int32_t offset) +{ + if (offset > 0xfff || offset < -0xfff) { + tcg_out_movi32(s, cond, TCG_REG_TMP, offset); + tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); + } else + tcg_out_st8_12(s, cond, rd, rn, offset); +} + +/* The _goto case is normally between TBs within the same code buffer, and + * with the code buffer limited to 16MB we wouldn't need the long case. + * But we also use it for the tail-call to the qemu_ld/st helpers, which does. + */ +static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) +{ + intptr_t addri = (intptr_t)addr; + ptrdiff_t disp = tcg_pcrel_diff(s, addr); + + if ((addri & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { + tcg_out_b(s, cond, disp); + return; + } + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); +} + +/* The call case is mostly used for helpers - so it's not unreasonable + * for them to be beyond branch range */ +static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) +{ + intptr_t addri = (intptr_t)addr; + ptrdiff_t disp = tcg_pcrel_diff(s, addr); + + if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { + if (addri & 1) { + /* Use BLX if the target is in Thumb mode */ + if (!use_armv5t_instructions) { + tcg_abort(); + } + tcg_out_blx_imm(s, disp); + } else { + tcg_out_bl(s, COND_AL, disp); + } + } else if (use_armv7_instructions) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); + tcg_out_blx(s, COND_AL, TCG_REG_TMP); + } else { + /* ??? Know that movi_pool emits exactly 1 insn. */ + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); + tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); + } +} + +static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) +{ + if (l->has_value) { + tcg_out_goto(s, cond, l->u.value_ptr); + } else { + tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); + tcg_out_b(s, cond, 0); + } +} + +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } +} + +static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGReg al = args[0]; + TCGReg ah = args[1]; + TCGArg bl = args[2]; + TCGArg bh = args[3]; + TCGCond cond = args[4]; + int const_bl = const_args[2]; + int const_bh = const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + /* We perform a conditional comparision. If the high half is + equal, then overwrite the flags with the comparison of the + low half. The resulting flags cover the whole. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); + tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); + return cond; + + case TCG_COND_LT: + case TCG_COND_GE: + /* We perform a double-word subtraction and examine the result. + We do not actually need the result of the subtract, so the + low part "subtract" is a compare. For the high half we have + no choice but to compute into a temporary. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return cond; + + case TCG_COND_LE: + case TCG_COND_GT: + /* Similar, but with swapped arguments, via reversed subtract. */ + tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, + TCG_REG_TMP, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return tcg_swap_cond(cond); + + default: + g_assert_not_reached(); + } +} + +#ifdef CONFIG_SOFTMMU +#include "../tcg-ldst.c.inc" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * int mmu_idx, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LESL] = helper_le_ldul_mmu, + + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BESL] = helper_be_ldul_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, int mmu_idx, uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +/* Helper routines for marshalling helper function arguments into + * the correct registers and stack. + * argreg is where we want to put this argument, arg is the argument itself. + * Return value is the updated argreg ready for the next call. + * Note that argreg 0..3 is real registers, 4+ on stack. + * + * We provide routines for arguments which are: immediate, 32 bit + * value in register, 16 and 8 bit values in register (which must be zero + * extended before use) and 64 bit value in a lo:hi register pair. + */ +#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \ +static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \ +{ \ + if (argreg < 4) { \ + MOV_ARG(s, COND_AL, argreg, arg); \ + } else { \ + int ofs = (argreg - 4) * 4; \ + EXT_ARG; \ + tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \ + tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \ + } \ + return argreg + 1; \ +} + +DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, + (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u, + (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, + (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) + +static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, + TCGReg arglo, TCGReg arghi) +{ + /* 64 bit arguments must go in even/odd register pairs + * and in 8-aligned stack slots. + */ + if (argreg & 1) { + argreg++; + } + if (use_armv6_instructions && argreg >= 4 + && (arglo & 1) == 0 && arghi == arglo + 1) { + tcg_out_strd_8(s, COND_AL, arglo, + TCG_REG_CALL_STACK, (argreg - 4) * 4); + return argreg + 2; + } else { + argreg = tcg_out_arg_reg32(s, argreg, arglo); + argreg = tcg_out_arg_reg32(s, argreg, arghi); + return argreg; + } +} + +#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) + +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); + +/* These offsets are built into the LDRD below. */ +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); + +/* Load and compare a TLB entry, leaving the flags set. Returns the register + containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ + +static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + MemOp opc, int mem_index, bool is_load) +{ + int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + + /* + * We don't support inline unaligned acceses, but we can easily + * support overalignment checks. + */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + if (use_armv6_instructions) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + } else { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); + } + + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off == 0) { + if (use_armv6_instructions && TARGET_LONG_BITS == 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (use_armv6_instructions && TARGET_LONG_BITS == 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + if (!use_armv6_instructions && TARGET_LONG_BITS == 64) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); + } + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* + * Check alignment, check comparators. + * Do this in no more than 3 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we need + * to clear at least 9 bits even for an 8-byte memory, which means it + * isn't worth checking for an immediate operand for BIC. + */ + if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) { + tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)); + + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + addrlo, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0); + } else { + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, + (1 << a_bits) - 1); + } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R2, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } + + if (TARGET_LONG_BITS == 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); + } + + return TCG_REG_R1; +} + +/* Record the context of a call to the out of line helper code for the slow + path for a load or store, so that we can later generate the correct + helper code. */ +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, + TCGReg datalo, TCGReg datahi, TCGReg addrlo, + TCGReg addrhi, tcg_insn_unit *raddr, + tcg_insn_unit *label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0] = label_ptr; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGReg argreg, datalo, datahi; + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + void *func; + + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); + if (TARGET_LONG_BITS == 64) { + argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); + } else { + argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); + } + argreg = tcg_out_arg_imm32(s, argreg, oi); + argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + + /* For armv6 we can use the canonical unsigned helpers and minimize + icache usage. For pre-armv6, use the signed helpers since we do + not have a single insn sign-extend. */ + if (use_armv6_instructions) { + func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]; + } else { + func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; + if (opc & MO_SIGN) { + opc = MO_UL; + } + } + tcg_out_call(s, func); + + datalo = lb->datalo_reg; + datahi = lb->datahi_reg; + switch (opc & MO_SSIZE) { + case MO_SB: + tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); + break; + case MO_SW: + tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); + break; + default: + tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); + break; + case MO_Q: + if (datalo != TCG_REG_R1) { + tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); + tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); + } else if (datahi != TCG_REG_R0) { + tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); + tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); + } else { + tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); + tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); + tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); + } + break; + } + + tcg_out_goto(s, COND_AL, lb->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGReg argreg, datalo, datahi; + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + argreg = TCG_REG_R0; + argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); + if (TARGET_LONG_BITS == 64) { + argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); + } else { + argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); + } + + datalo = lb->datalo_reg; + datahi = lb->datahi_reg; + switch (opc & MO_SIZE) { + case MO_8: + argreg = tcg_out_arg_reg8(s, argreg, datalo); + break; + case MO_16: + argreg = tcg_out_arg_reg16(s, argreg, datalo); + break; + case MO_32: + default: + argreg = tcg_out_arg_reg32(s, argreg, datalo); + break; + case MO_64: + argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi); + break; + } + + argreg = tcg_out_arg_imm32(s, argreg, oi); + argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + + /* Tail-call to the helper, which will return to the fast path. */ + tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; +} +#endif /* SOFTMMU */ + +static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) +{ + MemOp bswap = opc & MO_BSWAP; + + switch (opc & MO_SSIZE) { + case MO_UB: + tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); + break; + case MO_SB: + tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); + break; + case MO_UW: + tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); + if (bswap) { + tcg_out_bswap16(s, COND_AL, datalo, datalo); + } + break; + case MO_SW: + if (bswap) { + tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); + tcg_out_bswap16s(s, COND_AL, datalo, datalo); + } else { + tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); + } + break; + case MO_UL: + default: + tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); + if (bswap) { + tcg_out_bswap32(s, COND_AL, datalo, datalo); + } + break; + case MO_Q: + { + TCGReg dl = (bswap ? datahi : datalo); + TCGReg dh = (bswap ? datalo : datahi); + + /* Avoid ldrd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (dl & 1) == 0 && dh == dl + 1) { + tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend); + } else if (dl != addend) { + tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo); + tcg_out_ld32_12(s, COND_AL, dh, addend, 4); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, + addend, addrlo, SHIFT_IMM_LSL(0)); + tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0); + tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4); + } + if (bswap) { + tcg_out_bswap32(s, COND_AL, dl, dl); + tcg_out_bswap32(s, COND_AL, dh, dh); + } + } + break; + } +} + +static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo) +{ + MemOp bswap = opc & MO_BSWAP; + + switch (opc & MO_SSIZE) { + case MO_UB: + tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); + break; + case MO_SB: + tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); + break; + case MO_UW: + tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); + if (bswap) { + tcg_out_bswap16(s, COND_AL, datalo, datalo); + } + break; + case MO_SW: + if (bswap) { + tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); + tcg_out_bswap16s(s, COND_AL, datalo, datalo); + } else { + tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); + } + break; + case MO_UL: + default: + tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); + if (bswap) { + tcg_out_bswap32(s, COND_AL, datalo, datalo); + } + break; + case MO_Q: + { + TCGReg dl = (bswap ? datahi : datalo); + TCGReg dh = (bswap ? datalo : datahi); + + /* Avoid ldrd for user-only emulation, to handle unaligned. */ + if (USING_SOFTMMU && use_armv6_instructions + && (dl & 1) == 0 && dh == dl + 1) { + tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0); + } else if (dl == addrlo) { + tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); + tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); + } else { + tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); + tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); + } + if (bswap) { + tcg_out_bswap32(s, COND_AL, dl, dl); + tcg_out_bswap32(s, COND_AL, dh, dh); + } + } + break; + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +{ + TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc; +#ifdef CONFIG_SOFTMMU + int mem_index; + TCGReg addend; + tcg_insn_unit *label_ptr; +#endif + + datalo = *args++; + datahi = (is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#ifdef CONFIG_SOFTMMU + mem_index = get_mmuidx(oi); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + + /* This a conditional BL only to load a pointer within this opcode into LR + for the slow path. We will not be using the value for a tail call. */ + label_ptr = s->code_ptr; + tcg_out_bl(s, COND_NE, 0); + + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); + + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#else /* !CONFIG_SOFTMMU */ + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); + tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); + } else { + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); + } +#endif +} + +static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addend) +{ + MemOp bswap = opc & MO_BSWAP; + + switch (opc & MO_SIZE) { + case MO_8: + tcg_out_st8_r(s, cond, datalo, addrlo, addend); + break; + case MO_16: + if (bswap) { + tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo); + tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend); + } else { + tcg_out_st16_r(s, cond, datalo, addrlo, addend); + } + break; + case MO_32: + default: + if (bswap) { + tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); + tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend); + } else { + tcg_out_st32_r(s, cond, datalo, addrlo, addend); + } + break; + case MO_64: + /* Avoid strd for user-only emulation, to handle unaligned. */ + if (bswap) { + tcg_out_bswap32(s, cond, TCG_REG_R0, datahi); + tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo); + tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); + tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4); + } else if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) == 0 && datahi == datalo + 1) { + tcg_out_strd_r(s, cond, datalo, addrlo, addend); + } else { + tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); + tcg_out_st32_12(s, cond, datahi, addend, 4); + } + break; + } +} + +static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo) +{ + MemOp bswap = opc & MO_BSWAP; + + switch (opc & MO_SIZE) { + case MO_8: + tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); + break; + case MO_16: + if (bswap) { + tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo); + tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0); + } else { + tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); + } + break; + case MO_32: + default: + if (bswap) { + tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); + tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); + } else { + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + } + break; + case MO_64: + /* Avoid strd for user-only emulation, to handle unaligned. */ + if (bswap) { + tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi); + tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); + tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); + tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4); + } else if (USING_SOFTMMU && use_armv6_instructions + && (datalo & 1) == 0 && datahi == datalo + 1) { + tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + } else { + tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); + } + break; + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +{ + TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc; +#ifdef CONFIG_SOFTMMU + int mem_index; + TCGReg addend; + tcg_insn_unit *label_ptr; +#endif + + datalo = *args++; + datahi = (is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#ifdef CONFIG_SOFTMMU + mem_index = get_mmuidx(oi); + addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + + tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); + + /* The conditional call must come last, as we're going to return here. */ + label_ptr = s->code_ptr; + tcg_out_bl(s, COND_NE, 0); + + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#else /* !CONFIG_SOFTMMU */ + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); + tcg_out_qemu_st_index(s, COND_AL, opc, datalo, + datahi, addrlo, TCG_REG_TMP); + } else { + tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); + } +#endif +} + +static void tcg_out_epilogue(TCGContext *s); + +static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + TCGArg a0, a1, a2, a3, a4, a5; + int c; + + switch (opc) { + case INDEX_op_exit_tb: + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); + tcg_out_epilogue(s); + break; + case INDEX_op_goto_tb: + { + /* Indirect jump method */ + intptr_t ptr, dif, dil; + TCGReg base = TCG_REG_PC; + + tcg_debug_assert(s->tb_jmp_insn_offset == 0); + ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]); + dif = ptr - ((intptr_t)s->code_ptr + 8); + dil = sextract32(dif, 0, 12); + if (dif != dil) { + /* The TB is close, but outside the 12 bits addressable by + the load. We can extend this to 20 bits with a sub of a + shifted immediate from pc. In the vastly unlikely event + the code requires more than 1MB, we'll use 2 insns and + be no worse off. */ + base = TCG_REG_R0; + tcg_out_movi32(s, COND_AL, base, ptr - dil); + } + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); + set_jmp_reset_offset(s, args[0]); + } + break; + case INDEX_op_goto_ptr: + tcg_out_bx(s, COND_AL, args[0]); + break; + case INDEX_op_br: + tcg_out_goto_label(s, COND_AL, arg_label(args[0])); + break; + + case INDEX_op_ld8u_i32: + tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_ld8s_i32: + tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_ld16u_i32: + tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_ld16s_i32: + tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_ld_i32: + tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_st8_i32: + tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_st16_i32: + tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_st_i32: + tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); + break; + + case INDEX_op_movcond_i32: + /* Constraints mean that v2 is always in the same register as dest, + * so we only need to do "if condition passed, move v1 to dest". + */ + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, + ARITH_MVN, args[0], 0, args[3], const_args[3]); + break; + case INDEX_op_add_i32: + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, + args[0], args[1], args[2], const_args[2]); + break; + case INDEX_op_sub_i32: + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } + break; + case INDEX_op_and_i32: + tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, + args[0], args[1], args[2], const_args[2]); + break; + case INDEX_op_andc_i32: + tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, + args[0], args[1], args[2], const_args[2]); + break; + case INDEX_op_or_i32: + c = ARITH_ORR; + goto gen_arith; + case INDEX_op_xor_i32: + c = ARITH_EOR; + /* Fall through. */ + gen_arith: + tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); + break; + case INDEX_op_add2_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + a3 = args[3], a4 = args[4], a5 = args[5]; + if (a0 == a3 || (a0 == a5 && !const_args[5])) { + a0 = TCG_REG_TMP; + } + tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, + a0, a2, a4, const_args[4]); + tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, + a1, a3, a5, const_args[5]); + tcg_out_mov_reg(s, COND_AL, args[0], a0); + break; + case INDEX_op_sub2_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + a3 = args[3], a4 = args[4], a5 = args[5]; + if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { + a0 = TCG_REG_TMP; + } + if (const_args[2]) { + if (const_args[4]) { + tcg_out_movi32(s, COND_AL, a0, a4); + a4 = a0; + } + tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, + ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); + } + if (const_args[3]) { + if (const_args[5]) { + tcg_out_movi32(s, COND_AL, a1, a5); + a5 = a1; + } + tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); + } else { + tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, + a1, a3, a5, const_args[5]); + } + tcg_out_mov_reg(s, COND_AL, args[0], a0); + break; + case INDEX_op_neg_i32: + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); + break; + case INDEX_op_not_i32: + tcg_out_dat_reg(s, COND_AL, + ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); + break; + case INDEX_op_mul_i32: + tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_mulu2_i32: + tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); + break; + case INDEX_op_muls2_i32: + tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); + break; + /* XXX: Perhaps args[2] & 0x1f is wrong */ + case INDEX_op_shl_i32: + c = const_args[2] ? + SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); + goto gen_shift32; + case INDEX_op_shr_i32: + c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); + goto gen_shift32; + case INDEX_op_sar_i32: + c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); + goto gen_shift32; + case INDEX_op_rotr_i32: + c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : + SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); + /* Fall through. */ + gen_shift32: + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); + break; + + case INDEX_op_rotl_i32: + if (const_args[2]) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + ((0x20 - args[2]) & 0x1f) ? + SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : + SHIFT_IMM_LSL(0)); + } else { + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], + SHIFT_REG_ROR(TCG_REG_TMP)); + } + break; + + case INDEX_op_ctz_i32: + tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); + a1 = TCG_REG_TMP; + goto do_clz; + + case INDEX_op_clz_i32: + a1 = args[1]; + do_clz: + a0 = args[0]; + a2 = args[2]; + c = const_args[2]; + if (c && a2 == 32) { + tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); + break; + } + tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); + tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); + if (c || a0 != a2) { + tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); + } + break; + + case INDEX_op_brcond_i32: + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[0], args[1], const_args[1]); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], + arg_label(args[3])); + break; + case INDEX_op_setcond_i32: + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], + ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], + ARITH_MOV, args[0], 0, 0); + break; + + case INDEX_op_brcond2_i32: + c = tcg_out_cmp2(s, args, const_args); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + break; + case INDEX_op_setcond2_i32: + c = tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], + ARITH_MOV, args[0], 0, 0); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, 0); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, 1); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, 0); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, 1); + break; + + case INDEX_op_bswap16_i32: + tcg_out_bswap16(s, COND_AL, args[0], args[1]); + break; + case INDEX_op_bswap32_i32: + tcg_out_bswap32(s, COND_AL, args[0], args[1]); + break; + + case INDEX_op_ext8s_i32: + tcg_out_ext8s(s, COND_AL, args[0], args[1]); + break; + case INDEX_op_ext16s_i32: + tcg_out_ext16s(s, COND_AL, args[0], args[1]); + break; + case INDEX_op_ext16u_i32: + tcg_out_ext16u(s, COND_AL, args[0], args[1]); + break; + + case INDEX_op_deposit_i32: + tcg_out_deposit(s, COND_AL, args[0], args[2], + args[3], args[4], const_args[2]); + break; + case INDEX_op_extract_i32: + tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); + break; + case INDEX_op_sextract_i32: + tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); + break; + case INDEX_op_extract2_i32: + /* ??? These optimization vs zero should be generic. */ + /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, + args[2], SHIFT_IMM_LSL(32 - args[3])); + } + } else if (const_args[2]) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, + args[1], SHIFT_IMM_LSR(args[3])); + } else { + /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, + args[2], SHIFT_IMM_LSL(32 - args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, + args[1], SHIFT_IMM_LSR(args[3])); + } + break; + + case INDEX_op_div_i32: + tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_divu_i32: + tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + break; + + case INDEX_op_mb: + tcg_out_mb(s, args[0]); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; + static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; + static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; + static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } }; + static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } }; + static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; + static const TCGTargetOpDef r_r_rIN + = { .args_ct_str = { "r", "r", "rIN" } }; + static const TCGTargetOpDef r_r_rIK + = { .args_ct_str = { "r", "r", "rIK" } }; + static const TCGTargetOpDef r_r_r_r + = { .args_ct_str = { "r", "r", "r", "r" } }; + static const TCGTargetOpDef r_r_l_l + = { .args_ct_str = { "r", "r", "l", "l" } }; + static const TCGTargetOpDef s_s_s_s + = { .args_ct_str = { "s", "s", "s", "s" } }; + static const TCGTargetOpDef br + = { .args_ct_str = { "r", "rIN" } }; + static const TCGTargetOpDef ext2 + = { .args_ct_str = { "r", "rZ", "rZ" } }; + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "0", "rZ" } }; + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } }; + static const TCGTargetOpDef add2 + = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } }; + static const TCGTargetOpDef sub2 + = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; + static const TCGTargetOpDef br2 + = { .args_ct_str = { "r", "r", "rI", "rI" } }; + static const TCGTargetOpDef setc2 + = { .args_ct_str = { "r", "r", "r", "rI", "rI" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16u_i32: + case INDEX_op_extract_i32: + case INDEX_op_sextract_i32: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_setcond_i32: + return &r_r_rIN; + case INDEX_op_and_i32: + case INDEX_op_andc_i32: + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + return &r_r_rIK; + case INDEX_op_mul_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return &r_r_r; + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i32: + return &r_r_r_r; + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + return &r_r_rI; + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return &r_r_ri; + + case INDEX_op_brcond_i32: + return &br; + case INDEX_op_deposit_i32: + return &dep; + case INDEX_op_extract2_i32: + return &ext2; + case INDEX_op_movcond_i32: + return &movc; + case INDEX_op_add2_i32: + return &add2; + case INDEX_op_sub2_i32: + return &sub2; + case INDEX_op_brcond2_i32: + return &br2; + case INDEX_op_setcond2_i32: + return &setc2; + + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + case INDEX_op_qemu_ld_i64: + return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + case INDEX_op_qemu_st_i64: + return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + + default: + return NULL; + } +} + +static void tcg_target_init(TCGContext *s) +{ + /* Only probe for the platform and capabilities if we havn't already + determined maximum values at compile time. */ +#ifndef use_idiv_instructions + { + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; + } +#endif + if (__ARM_ARCH < 7) { + const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); + if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { + arm_arch = pl[1] - '0'; + } + } + + tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; + + tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); +} + +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); +} + +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + tcg_out_st32(s, COND_AL, arg, arg1, arg2); +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + return false; +} + +static inline bool tcg_out_mov(TCGContext *s, TCGType type, + TCGReg ret, TCGReg arg) +{ + tcg_out_mov_reg(s, COND_AL, ret, arg); + return true; +} + +static inline void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_out_movi32(s, COND_AL, ret, arg); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = INSN_NOP; + } +} + +/* Compute frame size via macros, to share between tcg_target_qemu_prologue + and tcg_register_jit. */ + +#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) + +#define FRAME_SIZE \ + ((PUSH_SIZE \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_NLONGS * sizeof(long) \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) + +#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) + +static void tcg_target_qemu_prologue(TCGContext *s) +{ + /* Calling convention requires us to save r4-r11 and lr. */ + /* stmdb sp!, { r4 - r11, lr } */ + tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); + + /* Reserve callee argument and tcg temp space. */ + tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, + TCG_REG_CALL_STACK, STACK_ADDEND, 1); + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + CPU_TEMP_BUF_NLONGS * sizeof(long)); + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + + tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]); + + /* + * Return path for goto_ptr. Set return value to 0, a-la exit_tb, + * and fall through to the rest of the epilogue. + */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); + tcg_out_epilogue(s); +} + +static void tcg_out_epilogue(TCGContext *s) +{ + /* Release local stack frame. */ + tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, + TCG_REG_CALL_STACK, STACK_ADDEND, 1); + + /* ldmia sp!, { r4 - r11, pc } */ + tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[18]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_ARM + +/* We're expecting a 2 byte uleb128 encoded value. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x7c, /* sleb128 -4 */ + .h.cie.return_column = 14, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, 13, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + /* The following must match the stmdb in the prologue. */ + 0x8e, 1, /* DW_CFA_offset, lr, -4 */ + 0x8b, 2, /* DW_CFA_offset, r11, -8 */ + 0x8a, 3, /* DW_CFA_offset, r10, -12 */ + 0x89, 4, /* DW_CFA_offset, r9, -16 */ + 0x88, 5, /* DW_CFA_offset, r8, -20 */ + 0x87, 6, /* DW_CFA_offset, r7, -24 */ + 0x86, 7, /* DW_CFA_offset, r6, -28 */ + 0x85, 8, /* DW_CFA_offset, r5, -32 */ + 0x84, 9, /* DW_CFA_offset, r4, -36 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c deleted file mode 100644 index 6aa7757aac..0000000000 --- a/tcg/arm/tcg-target.inc.c +++ /dev/null @@ -1,2362 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Andrzej Zaborowski - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "elf.h" -#include "../tcg-pool.inc.c" - -int arm_arch = __ARM_ARCH; - -#ifndef use_idiv_instructions -bool use_idiv_instructions; -#endif - -/* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */ -#ifdef CONFIG_SOFTMMU -# define USING_SOFTMMU 1 -#else -# define USING_SOFTMMU 0 -#endif - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "%r0", - "%r1", - "%r2", - "%r3", - "%r4", - "%r5", - "%r6", - "%r7", - "%r8", - "%r9", - "%r10", - "%r11", - "%r12", - "%r13", - "%r14", - "%pc", -}; -#endif - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R13, - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R12, - TCG_REG_R14, -}; - -static const int tcg_target_call_iarg_regs[4] = { - TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 -}; -static const int tcg_target_call_oarg_regs[2] = { - TCG_REG_R0, TCG_REG_R1 -}; - -#define TCG_REG_TMP TCG_REG_R12 - -enum arm_cond_code_e { - COND_EQ = 0x0, - COND_NE = 0x1, - COND_CS = 0x2, /* Unsigned greater or equal */ - COND_CC = 0x3, /* Unsigned less than */ - COND_MI = 0x4, /* Negative */ - COND_PL = 0x5, /* Zero or greater */ - COND_VS = 0x6, /* Overflow */ - COND_VC = 0x7, /* No overflow */ - COND_HI = 0x8, /* Unsigned greater than */ - COND_LS = 0x9, /* Unsigned less or equal */ - COND_GE = 0xa, - COND_LT = 0xb, - COND_GT = 0xc, - COND_LE = 0xd, - COND_AL = 0xe, -}; - -#define TO_CPSR (1 << 20) - -#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) -#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) -#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) -#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) -#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) -#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) -#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) -#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) - -typedef enum { - ARITH_AND = 0x0 << 21, - ARITH_EOR = 0x1 << 21, - ARITH_SUB = 0x2 << 21, - ARITH_RSB = 0x3 << 21, - ARITH_ADD = 0x4 << 21, - ARITH_ADC = 0x5 << 21, - ARITH_SBC = 0x6 << 21, - ARITH_RSC = 0x7 << 21, - ARITH_TST = 0x8 << 21 | TO_CPSR, - ARITH_CMP = 0xa << 21 | TO_CPSR, - ARITH_CMN = 0xb << 21 | TO_CPSR, - ARITH_ORR = 0xc << 21, - ARITH_MOV = 0xd << 21, - ARITH_BIC = 0xe << 21, - ARITH_MVN = 0xf << 21, - - INSN_CLZ = 0x016f0f10, - INSN_RBIT = 0x06ff0f30, - - INSN_LDR_IMM = 0x04100000, - INSN_LDR_REG = 0x06100000, - INSN_STR_IMM = 0x04000000, - INSN_STR_REG = 0x06000000, - - INSN_LDRH_IMM = 0x005000b0, - INSN_LDRH_REG = 0x001000b0, - INSN_LDRSH_IMM = 0x005000f0, - INSN_LDRSH_REG = 0x001000f0, - INSN_STRH_IMM = 0x004000b0, - INSN_STRH_REG = 0x000000b0, - - INSN_LDRB_IMM = 0x04500000, - INSN_LDRB_REG = 0x06500000, - INSN_LDRSB_IMM = 0x005000d0, - INSN_LDRSB_REG = 0x001000d0, - INSN_STRB_IMM = 0x04400000, - INSN_STRB_REG = 0x06400000, - - INSN_LDRD_IMM = 0x004000d0, - INSN_LDRD_REG = 0x000000d0, - INSN_STRD_IMM = 0x004000f0, - INSN_STRD_REG = 0x000000f0, - - INSN_DMB_ISH = 0xf57ff05b, - INSN_DMB_MCR = 0xee070fba, - - /* Architected nop introduced in v6k. */ - /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this - also Just So Happened to do nothing on pre-v6k so that we - don't need to conditionalize it? */ - INSN_NOP_v6k = 0xe320f000, - /* Otherwise the assembler uses mov r0,r0 */ - INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, -} ARMInsn; - -#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) - -static const uint8_t tcg_cond_to_arm_cond[] = { - [TCG_COND_EQ] = COND_EQ, - [TCG_COND_NE] = COND_NE, - [TCG_COND_LT] = COND_LT, - [TCG_COND_GE] = COND_GE, - [TCG_COND_LE] = COND_LE, - [TCG_COND_GT] = COND_GT, - /* unsigned */ - [TCG_COND_LTU] = COND_CC, - [TCG_COND_GEU] = COND_CS, - [TCG_COND_LEU] = COND_LS, - [TCG_COND_GTU] = COND_HI, -}; - -static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; - if (offset == sextract32(offset, 0, 24)) { - *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); - return true; - } - return false; -} - -static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8; - - if (offset >= -0xfff && offset <= 0xfff) { - tcg_insn_unit insn = *code_ptr; - bool u = (offset >= 0); - if (!u) { - offset = -offset; - } - insn = deposit32(insn, 23, 1, u); - insn = deposit32(insn, 0, 12, offset); - *code_ptr = insn; - return true; - } - return false; -} - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_debug_assert(addend == 0); - - if (type == R_ARM_PC24) { - return reloc_pc24(code_ptr, (tcg_insn_unit *)value); - } else if (type == R_ARM_PC13) { - return reloc_pc13(code_ptr, (tcg_insn_unit *)value); - } else { - g_assert_not_reached(); - } -} - -#define TCG_CT_CONST_ARM 0x100 -#define TCG_CT_CONST_INV 0x200 -#define TCG_CT_CONST_NEG 0x400 -#define TCG_CT_CONST_ZERO 0x800 - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'I': - ct->ct |= TCG_CT_CONST_ARM; - break; - case 'K': - ct->ct |= TCG_CT_CONST_INV; - break; - case 'N': /* The gcc constraint letter is L, already used here. */ - ct->ct |= TCG_CT_CONST_NEG; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - - case 'r': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - break; - - /* qemu_ld address */ - case 'l': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; -#ifdef CONFIG_SOFTMMU - /* r0-r2,lr will be overwritten when reading the tlb entry, - so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif - break; - - /* qemu_st address & data */ - case 's': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) - and r0-r1 doing the byte swapping, so don't use these. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); -#if defined(CONFIG_SOFTMMU) - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); -#if TARGET_LONG_BITS == 64 - /* Avoid clashes with registers being used for helper args */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#endif - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); -#endif - break; - - default: - return NULL; - } - return ct_str; -} - -static inline uint32_t rotl(uint32_t val, int n) -{ - return (val << n) | (val >> (32 - n)); -} - -/* ARM immediates for ALU instructions are made of an unsigned 8-bit - right-rotated by an even amount between 0 and 30. */ -static inline int encode_imm(uint32_t imm) -{ - int shift; - - /* simple case, only lower bits */ - if ((imm & ~0xff) == 0) - return 0; - /* then try a simple even shift */ - shift = ctz32(imm) & ~1; - if (((imm >> shift) & ~0xff) == 0) - return 32 - shift; - /* now try harder with rotations */ - if ((rotl(imm, 2) & ~0xff) == 0) - return 2; - if ((rotl(imm, 4) & ~0xff) == 0) - return 4; - if ((rotl(imm, 6) & ~0xff) == 0) - return 6; - /* imm can't be encoded */ - return -1; -} - -static inline int check_fit_imm(uint32_t imm) -{ - return encode_imm(imm) >= 0; -} - -/* Test if a constant matches the constraint. - * TODO: define constraints for: - * - * ldr/str offset: between -0xfff and 0xfff - * ldrh/strh offset: between -0xff and 0xff - * mov operand2: values represented with x << (2 * y), x < 0x100 - * add, sub, eor...: ditto - */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct; - ct = arg_ct->ct; - if (ct & TCG_CT_CONST) { - return 1; - } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { - return 1; - } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { - return 1; - } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { - return 1; - } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } else { - return 0; - } -} - -static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) -{ - tcg_out32(s, (cond << 28) | 0x0a000000 | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) -{ - tcg_out32(s, (cond << 28) | 0x0b000000 | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static inline void tcg_out_blx(TCGContext *s, int cond, int rn) -{ - tcg_out32(s, (cond << 28) | 0x012fff30 | rn); -} - -static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) -{ - tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | - (((offset - 8) >> 2) & 0x00ffffff)); -} - -static inline void tcg_out_dat_reg(TCGContext *s, - int cond, int opc, int rd, int rn, int rm, int shift) -{ - tcg_out32(s, (cond << 28) | (0 << 25) | opc | - (rn << 16) | (rd << 12) | shift | rm); -} - -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, INSN_NOP); -} - -static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) -{ - /* Simple reg-reg move, optimising out the 'do nothing' case */ - if (rd != rm) { - tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); - } -} - -static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) -{ - /* Unless the C portion of QEMU is compiled as thumb, we don't - actually need true BX semantics; merely a branch to an address - held in a register. */ - if (use_armv5t_instructions) { - tcg_out32(s, (cond << 28) | 0x012fff10 | rn); - } else { - tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); - } -} - -static inline void tcg_out_dat_imm(TCGContext *s, - int cond, int opc, int rd, int rn, int im) -{ - tcg_out32(s, (cond << 28) | (1 << 25) | opc | - (rn << 16) | (rd << 12) | im); -} - -/* Note that this routine is used for both LDR and LDRH formats, so we do - not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, TCGReg rm, bool u, bool p, bool w) -{ - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) - | (w << 21) | (rn << 16) | (rt << 12) | rm); -} - -static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, int imm8, bool p, bool w) -{ - bool u = 1; - if (imm8 < 0) { - imm8 = -imm8; - u = 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); -} - -static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, int imm12, bool p, bool w) -{ - bool u = 1; - if (imm12 < 0) { - imm12 = -imm12; - u = 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | imm12); -} - -static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ldrd_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); -} - -/* Register pre-increment with base writeback. */ -static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); -} - -static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg) -{ - new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); - tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); -} - -static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) -{ - int rot, diff, opc, sh1, sh2; - uint32_t tt0, tt1, tt2; - - /* Check a single MOV/MVN before anything else. */ - rot = encode_imm(arg); - if (rot >= 0) { - tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, - rotl(arg, rot) | (rot << 7)); - return; - } - rot = encode_imm(~arg); - if (rot >= 0) { - tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, - rotl(~arg, rot) | (rot << 7)); - return; - } - - /* Check for a pc-relative address. This will usually be the TB, - or within the TB, which is immediately before the code block. */ - diff = arg - ((intptr_t)s->code_ptr + 8); - if (diff >= 0) { - rot = encode_imm(diff); - if (rot >= 0) { - tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, - rotl(diff, rot) | (rot << 7)); - return; - } - } else { - rot = encode_imm(-diff); - if (rot >= 0) { - tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, - rotl(-diff, rot) | (rot << 7)); - return; - } - } - - /* Use movw + movt. */ - if (use_armv7_instructions) { - /* movw */ - tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12) - | ((arg << 4) & 0x000f0000) | (arg & 0xfff)); - if (arg & 0xffff0000) { - /* movt */ - tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12) - | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff)); - } - return; - } - - /* Look for sequences of two insns. If we have lots of 1's, we can - shorten the sequence by beginning with mvn and then clearing - higher bits with eor. */ - tt0 = arg; - opc = ARITH_MOV; - if (ctpop32(arg) > 16) { - tt0 = ~arg; - opc = ARITH_MVN; - } - sh1 = ctz32(tt0) & ~1; - tt1 = tt0 & ~(0xff << sh1); - sh2 = ctz32(tt1) & ~1; - tt2 = tt1 & ~(0xff << sh2); - if (tt2 == 0) { - rot = ((32 - sh1) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); - rot = ((32 - sh2) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, - ((tt0 >> sh2) & 0xff) | rot); - return; - } - - /* Otherwise, drop it into the constant pool. */ - tcg_out_movi_pool(s, cond, rd, arg); -} - -static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, - TCGArg lhs, TCGArg rhs, int rhs_is_const) -{ - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rI" constraint. - */ - if (rhs_is_const) { - int rot = encode_imm(rhs); - tcg_debug_assert(rot >= 0); - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, - TCGReg dst, TCGReg lhs, TCGArg rhs, - bool rhs_is_const) -{ - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIK" constraint. - */ - if (rhs_is_const) { - int rot = encode_imm(rhs); - if (rot < 0) { - rhs = ~rhs; - rot = encode_imm(rhs); - tcg_debug_assert(rot >= 0); - opc = opinv; - } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -static void tcg_out_dat_rIN(TCGContext *s, int cond, int opc, int opneg, - TCGArg dst, TCGArg lhs, TCGArg rhs, - bool rhs_is_const) -{ - /* Emit either the reg,imm or reg,reg form of a data-processing insn. - * rhs must satisfy the "rIN" constraint. - */ - if (rhs_is_const) { - int rot = encode_imm(rhs); - if (rot < 0) { - rhs = -rhs; - rot = encode_imm(rhs); - tcg_debug_assert(rot >= 0); - opc = opneg; - } - tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); - } else { - tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); - } -} - -static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd, - TCGReg rn, TCGReg rm) -{ - /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */ - if (!use_armv6_instructions && rd == rn) { - if (rd == rm) { - /* rd == rn == rm; copy an input to tmp first. */ - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rm = rn = TCG_REG_TMP; - } else { - rn = rm; - rm = rd; - } - } - /* mul */ - tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn); -} - -static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) -{ - /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */ - if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) { - if (rd0 == rm || rd1 == rm) { - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rn = TCG_REG_TMP; - } else { - TCGReg t = rn; - rn = rm; - rm = t; - } - } - /* umull */ - tcg_out32(s, (cond << 28) | 0x00800090 | - (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); -} - -static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0, - TCGReg rd1, TCGReg rn, TCGReg rm) -{ - /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */ - if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) { - if (rd0 == rm || rd1 == rm) { - tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn); - rn = TCG_REG_TMP; - } else { - TCGReg t = rn; - rn = rm; - rm = t; - } - } - /* smull */ - tcg_out32(s, (cond << 28) | 0x00c00090 | - (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn); -} - -static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) -{ - tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); -} - -static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) -{ - tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); -} - -static inline void tcg_out_ext8s(TCGContext *s, int cond, - int rd, int rn) -{ - if (use_armv6_instructions) { - /* sxtb */ - tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(24)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_ASR(24)); - } -} - -static inline void tcg_out_ext8u(TCGContext *s, int cond, - int rd, int rn) -{ - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); -} - -static inline void tcg_out_ext16s(TCGContext *s, int cond, - int rd, int rn) -{ - if (use_armv6_instructions) { - /* sxth */ - tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(16)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_ASR(16)); - } -} - -static inline void tcg_out_ext16u(TCGContext *s, int cond, - int rd, int rn) -{ - if (use_armv6_instructions) { - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_LSL(16)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rd, SHIFT_IMM_LSR(16)); - } -} - -static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn) -{ - if (use_armv6_instructions) { - /* revsh */ - tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16)); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8)); - } -} - -static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) -{ - if (use_armv6_instructions) { - /* rev16 */ - tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24)); - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16)); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8)); - } -} - -/* swap the two low bytes assuming that the two high input bytes and the - two high output bit can hold any value. */ -static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn) -{ - if (use_armv6_instructions) { - /* rev16 */ - tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_MOV, - TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8)); - tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff); - tcg_out_dat_reg(s, cond, ARITH_ORR, - rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8)); - } -} - -static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) -{ - if (use_armv6_instructions) { - /* rev */ - tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn); - } else { - tcg_out_dat_reg(s, cond, ARITH_EOR, - TCG_REG_TMP, rn, rn, SHIFT_IMM_ROR(16)); - tcg_out_dat_imm(s, cond, ARITH_BIC, - TCG_REG_TMP, TCG_REG_TMP, 0xff | 0x800); - tcg_out_dat_reg(s, cond, ARITH_MOV, - rd, 0, rn, SHIFT_IMM_ROR(8)); - tcg_out_dat_reg(s, cond, ARITH_EOR, - rd, rd, TCG_REG_TMP, SHIFT_IMM_LSR(8)); - } -} - -static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len, bool const_a1) -{ - if (const_a1) { - /* bfi becomes bfc with rn == 15. */ - a1 = 15; - } - /* bfi/bfc */ - tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 - | (ofs << 7) | ((ofs + len - 1) << 16)); -} - -static inline void tcg_out_extract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) -{ - /* ubfx */ - tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | a1 - | (ofs << 7) | ((len - 1) << 16)); -} - -static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, - TCGArg a1, int ofs, int len) -{ - /* sbfx */ - tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | a1 - | (ofs << 7) | ((len - 1) << 16)); -} - -static inline void tcg_out_ld32u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld32_12(s, cond, rd, rn, offset); -} - -static inline void tcg_out_st32(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_st32_12(s, cond, rd, rn, offset); -} - -static inline void tcg_out_ld16u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld16u_8(s, cond, rd, rn, offset); -} - -static inline void tcg_out_ld16s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld16s_8(s, cond, rd, rn, offset); -} - -static inline void tcg_out_st16(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_st16_8(s, cond, rd, rn, offset); -} - -static inline void tcg_out_ld8u(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld8_12(s, cond, rd, rn, offset); -} - -static inline void tcg_out_ld8s(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xff || offset < -0xff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_ld8s_8(s, cond, rd, rn, offset); -} - -static inline void tcg_out_st8(TCGContext *s, int cond, - int rd, int rn, int32_t offset) -{ - if (offset > 0xfff || offset < -0xfff) { - tcg_out_movi32(s, cond, TCG_REG_TMP, offset); - tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP); - } else - tcg_out_st8_12(s, cond, rd, rn, offset); -} - -/* The _goto case is normally between TBs within the same code buffer, and - * with the code buffer limited to 16MB we wouldn't need the long case. - * But we also use it for the tail-call to the qemu_ld/st helpers, which does. - */ -static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) -{ - intptr_t addri = (intptr_t)addr; - ptrdiff_t disp = tcg_pcrel_diff(s, addr); - - if ((addri & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) { - tcg_out_b(s, cond, disp); - return; - } - tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); -} - -/* The call case is mostly used for helpers - so it's not unreasonable - * for them to be beyond branch range */ -static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) -{ - intptr_t addri = (intptr_t)addr; - ptrdiff_t disp = tcg_pcrel_diff(s, addr); - - if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) { - if (addri & 1) { - /* Use BLX if the target is in Thumb mode */ - if (!use_armv5t_instructions) { - tcg_abort(); - } - tcg_out_blx_imm(s, disp); - } else { - tcg_out_bl(s, COND_AL, disp); - } - } else if (use_armv7_instructions) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); - tcg_out_blx(s, COND_AL, TCG_REG_TMP); - } else { - /* ??? Know that movi_pool emits exactly 1 insn. */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); - tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); - } -} - -static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) -{ - if (l->has_value) { - tcg_out_goto(s, cond, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0); - tcg_out_b(s, cond, 0); - } -} - -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - if (use_armv7_instructions) { - tcg_out32(s, INSN_DMB_ISH); - } else if (use_armv6_instructions) { - tcg_out32(s, INSN_DMB_MCR); - } -} - -static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, - const int *const_args) -{ - TCGReg al = args[0]; - TCGReg ah = args[1]; - TCGArg bl = args[2]; - TCGArg bh = args[3]; - TCGCond cond = args[4]; - int const_bl = const_args[2]; - int const_bh = const_args[3]; - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - case TCG_COND_LTU: - case TCG_COND_LEU: - case TCG_COND_GTU: - case TCG_COND_GEU: - /* We perform a conditional comparision. If the high half is - equal, then overwrite the flags with the comparison of the - low half. The resulting flags cover the whole. */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); - tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); - return cond; - - case TCG_COND_LT: - case TCG_COND_GE: - /* We perform a double-word subtraction and examine the result. - We do not actually need the result of the subtract, so the - low part "subtract" is a compare. For the high half we have - no choice but to compute into a temporary. */ - tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); - tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, - TCG_REG_TMP, ah, bh, const_bh); - return cond; - - case TCG_COND_LE: - case TCG_COND_GT: - /* Similar, but with swapped arguments, via reversed subtract. */ - tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, - TCG_REG_TMP, al, bl, const_bl); - tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, - TCG_REG_TMP, ah, bh, const_bh); - return tcg_swap_cond(cond); - - default: - g_assert_not_reached(); - } -} - -#ifdef CONFIG_SOFTMMU -#include "../tcg-ldst.inc.c" - -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_SB] = helper_ret_ldsb_mmu, - - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_LESW] = helper_le_ldsw_mmu, - [MO_LESL] = helper_le_ldul_mmu, - - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, - [MO_BESW] = helper_be_ldsw_mmu, - [MO_BESL] = helper_be_ldul_mmu, -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_t ra) - */ -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * argreg is where we want to put this argument, arg is the argument itself. - * Return value is the updated argreg ready for the next call. - * Note that argreg 0..3 is real registers, 4+ on stack. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ -#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \ -static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \ -{ \ - if (argreg < 4) { \ - MOV_ARG(s, COND_AL, argreg, arg); \ - } else { \ - int ofs = (argreg - 4) * 4; \ - EXT_ARG; \ - tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \ - tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \ - } \ - return argreg + 1; \ -} - -DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, - (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u, - (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, - (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) - -static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, - TCGReg arglo, TCGReg arghi) -{ - /* 64 bit arguments must go in even/odd register pairs - * and in 8-aligned stack slots. - */ - if (argreg & 1) { - argreg++; - } - if (use_armv6_instructions && argreg >= 4 - && (arglo & 1) == 0 && arghi == arglo + 1) { - tcg_out_strd_8(s, COND_AL, arglo, - TCG_REG_CALL_STACK, (argreg - 4) * 4); - return argreg + 2; - } else { - argreg = tcg_out_arg_reg32(s, argreg, arglo); - argreg = tcg_out_arg_reg32(s, argreg, arghi); - return argreg; - } -} - -#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) - -/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); - -/* These offsets are built into the LDRD below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); - -/* Load and compare a TLB entry, leaving the flags set. Returns the register - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - MemOp opc, int mem_index, bool is_load) -{ - int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); - int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); - int table_off = fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - - /* - * We don't support inline unaligned acceses, but we can easily - * support overalignment checks. - */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - if (use_armv6_instructions) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - } else { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off); - } - - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. - * Load the tlb comparator into R2/R3 and the fast path addend into R1. - */ - if (cmp_off == 0) { - if (use_armv6_instructions && TARGET_LONG_BITS == 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (use_armv6_instructions && TARGET_LONG_BITS == 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } - } - if (!use_armv6_instructions && TARGET_LONG_BITS == 64) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4); - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in no more than 3 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we need - * to clear at least 9 bits even for an 8-byte memory, which means it - * isn't worth checking for an immediate operand for BIC. - */ - if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) { - tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)); - - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - addrlo, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0); - } else { - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, - (1 << a_bits) - 1); - } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - } - - if (TARGET_LONG_BITS == 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); - } - - return TCG_REG_R1; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrlo, - TCGReg addrhi, tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - void *func; - - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); - } else { - argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg = tcg_out_arg_imm32(s, argreg, oi); - argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* For armv6 we can use the canonical unsigned helpers and minimize - icache usage. For pre-armv6, use the signed helpers since we do - not have a single insn sign-extend. */ - if (use_armv6_instructions) { - func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]; - } else { - func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]; - if (opc & MO_SIGN) { - opc = MO_UL; - } - } - tcg_out_call(s, func); - - datalo = lb->datalo_reg; - datahi = lb->datahi_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_SW: - tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); - break; - default: - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_Q: - if (datalo != TCG_REG_R1) { - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - } else if (datahi != TCG_REG_R0) { - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - } else { - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); - } - break; - } - - tcg_out_goto(s, COND_AL, lb->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg argreg, datalo, datahi; - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - argreg = TCG_REG_R0; - argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg); - } else { - argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo = lb->datalo_reg; - datahi = lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg = tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg = tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg = tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg = tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg = tcg_out_arg_imm32(s, argreg, oi); - argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Tail-call to the helper, which will return to the fast path. */ - tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - return true; -} -#endif /* SOFTMMU */ - -static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) -{ - MemOp bswap = opc & MO_BSWAP; - - switch (opc & MO_SSIZE) { - case MO_UB: - tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); - break; - case MO_SB: - tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); - break; - case MO_UW: - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } - break; - case MO_SW: - if (bswap) { - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); - } - break; - case MO_UL: - default: - tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } - break; - case MO_Q: - { - TCGReg dl = (bswap ? datahi : datalo); - TCGReg dh = (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) == 0 && dh == dl + 1) { - tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend); - } else if (dl != addend) { - tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo); - tcg_out_ld32_12(s, COND_AL, dh, addend, 4); - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0); - tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } - } - break; - } -} - -static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) -{ - MemOp bswap = opc & MO_BSWAP; - - switch (opc & MO_SSIZE) { - case MO_UB: - tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SB: - tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UW: - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap16(s, COND_AL, datalo, datalo); - } - break; - case MO_SW: - if (bswap) { - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - tcg_out_bswap16s(s, COND_AL, datalo, datalo); - } else { - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - } - break; - case MO_UL: - default: - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - if (bswap) { - tcg_out_bswap32(s, COND_AL, datalo, datalo); - } - break; - case MO_Q: - { - TCGReg dl = (bswap ? datahi : datalo); - TCGReg dh = (bswap ? datalo : datahi); - - /* Avoid ldrd for user-only emulation, to handle unaligned. */ - if (USING_SOFTMMU && use_armv6_instructions - && (dl & 1) == 0 && dh == dl + 1) { - tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0); - } else if (dl == addrlo) { - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - } else { - tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0); - tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4); - } - if (bswap) { - tcg_out_bswap32(s, COND_AL, dl, dl); - tcg_out_bswap32(s, COND_AL, dh, dh); - } - } - break; - } -} - -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) -{ - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#endif - - datalo = *args++; - datahi = (is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); - - /* This a conditional BL only to load a pointer within this opcode into LR - for the slow path. We will not be using the value for a tail call. */ - label_ptr = s->code_ptr; - tcg_out_bl(s, COND_NE, 0); - - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend); - - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, TCG_REG_TMP); - } else { - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); - } -#endif -} - -static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend) -{ - MemOp bswap = opc & MO_BSWAP; - - switch (opc & MO_SIZE) { - case MO_8: - tcg_out_st8_r(s, cond, datalo, addrlo, addend); - break; - case MO_16: - if (bswap) { - tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo); - tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend); - } else { - tcg_out_st16_r(s, cond, datalo, addrlo, addend); - } - break; - case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend); - } else { - tcg_out_st32_r(s, cond, datalo, addrlo, addend); - } - break; - case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, cond, TCG_REG_R0, datahi); - tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo); - tcg_out_bswap32(s, cond, TCG_REG_R0, datalo); - tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) == 0 && datahi == datalo + 1) { - tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else { - tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); - tcg_out_st32_12(s, cond, datahi, addend, 4); - } - break; - } -} - -static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo) -{ - MemOp bswap = opc & MO_BSWAP; - - switch (opc & MO_SIZE) { - case MO_8: - tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_16: - if (bswap) { - tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); - } - break; - case MO_32: - default: - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - } - break; - case MO_64: - /* Avoid strd for user-only emulation, to handle unaligned. */ - if (bswap) { - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0); - tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo); - tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4); - } else if (USING_SOFTMMU && use_armv6_instructions - && (datalo & 1) == 0 && datahi == datalo + 1) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); - } - break; - } -} - -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) -{ - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#endif - - datalo = *args++; - datahi = (is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend); - - /* The conditional call must come last, as we're going to return here. */ - label_ptr = s->code_ptr; - tcg_out_bl(s, COND_NE, 0); - - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, guest_base); - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, - datahi, addrlo, TCG_REG_TMP); - } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); - } -#endif -} - -static void tcg_out_epilogue(TCGContext *s); - -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - TCGArg a0, a1, a2, a3, a4, a5; - int c; - - switch (opc) { - case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, args[0]); - tcg_out_epilogue(s); - break; - case INDEX_op_goto_tb: - { - /* Indirect jump method */ - intptr_t ptr, dif, dil; - TCGReg base = TCG_REG_PC; - - tcg_debug_assert(s->tb_jmp_insn_offset == 0); - ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]); - dif = ptr - ((intptr_t)s->code_ptr + 8); - dil = sextract32(dif, 0, 12); - if (dif != dil) { - /* The TB is close, but outside the 12 bits addressable by - the load. We can extend this to 20 bits with a sub of a - shifted immediate from pc. In the vastly unlikely event - the code requires more than 1MB, we'll use 2 insns and - be no worse off. */ - base = TCG_REG_R0; - tcg_out_movi32(s, COND_AL, base, ptr - dil); - } - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); - set_jmp_reset_offset(s, args[0]); - } - break; - case INDEX_op_goto_ptr: - tcg_out_bx(s, COND_AL, args[0]); - break; - case INDEX_op_br: - tcg_out_goto_label(s, COND_AL, arg_label(args[0])); - break; - - case INDEX_op_ld8u_i32: - tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_ld8s_i32: - tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_ld16u_i32: - tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_ld16s_i32: - tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_ld_i32: - tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_st8_i32: - tcg_out_st8(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_st16_i32: - tcg_out_st16(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_st_i32: - tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); - break; - - case INDEX_op_movcond_i32: - /* Constraints mean that v2 is always in the same register as dest, - * so we only need to do "if condition passed, move v1 to dest". - */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV, - ARITH_MVN, args[0], 0, args[3], const_args[3]); - break; - case INDEX_op_add_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB, - args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_sub_i32: - if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); - } else { - tcg_out_dat_rI(s, COND_AL, ARITH_RSB, - args[0], args[2], args[1], 1); - } - } else { - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); - } - break; - case INDEX_op_and_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, - args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_andc_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_or_i32: - c = ARITH_ORR; - goto gen_arith; - case INDEX_op_xor_i32: - c = ARITH_EOR; - /* Fall through. */ - gen_arith: - tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_add2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; - if (a0 == a3 || (a0 == a5 && !const_args[5])) { - a0 = TCG_REG_TMP; - } - tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR, - a0, a2, a4, const_args[4]); - tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC, - a1, a3, a5, const_args[5]); - tcg_out_mov_reg(s, COND_AL, args[0], a0); - break; - case INDEX_op_sub2_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - a3 = args[3], a4 = args[4], a5 = args[5]; - if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) { - a0 = TCG_REG_TMP; - } - if (const_args[2]) { - if (const_args[4]) { - tcg_out_movi32(s, COND_AL, a0, a4); - a4 = a0; - } - tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1); - } else { - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR, - ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]); - } - if (const_args[3]) { - if (const_args[5]) { - tcg_out_movi32(s, COND_AL, a1, a5); - a5 = a1; - } - tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1); - } else { - tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC, - a1, a3, a5, const_args[5]); - } - tcg_out_mov_reg(s, COND_AL, args[0], a0); - break; - case INDEX_op_neg_i32: - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); - break; - case INDEX_op_not_i32: - tcg_out_dat_reg(s, COND_AL, - ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0)); - break; - case INDEX_op_mul_i32: - tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_mulu2_i32: - tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); - break; - case INDEX_op_muls2_i32: - tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]); - break; - /* XXX: Perhaps args[2] & 0x1f is wrong */ - case INDEX_op_shl_i32: - c = const_args[2] ? - SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); - goto gen_shift32; - case INDEX_op_shr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); - goto gen_shift32; - case INDEX_op_sar_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); - goto gen_shift32; - case INDEX_op_rotr_i32: - c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) : - SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]); - /* Fall through. */ - gen_shift32: - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); - break; - - case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], - ((0x20 - args[2]) & 0x1f) ? - SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : - SHIFT_IMM_LSL(0)); - } else { - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], - SHIFT_REG_ROR(TCG_REG_TMP)); - } - break; - - case INDEX_op_ctz_i32: - tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0); - a1 = TCG_REG_TMP; - goto do_clz; - - case INDEX_op_clz_i32: - a1 = args[1]; - do_clz: - a0 = args[0]; - a2 = args[2]; - c = const_args[2]; - if (c && a2 == 32) { - tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0); - break; - } - tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0); - tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0); - if (c || a0 != a2) { - tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c); - } - break; - - case INDEX_op_brcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[0], args[1], const_args[1]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], - arg_label(args[3])); - break; - case INDEX_op_setcond_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[2], const_args[2]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], - ARITH_MOV, args[0], 0, 0); - break; - - case INDEX_op_brcond2_i32: - c = tcg_out_cmp2(s, args, const_args); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); - break; - case INDEX_op_setcond2_i32: - c = tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], - ARITH_MOV, args[0], 0, 0); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); - break; - - case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, COND_AL, args[0], args[1]); - break; - case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, COND_AL, args[0], args[1]); - break; - - case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, COND_AL, args[0], args[1]); - break; - case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, COND_AL, args[0], args[1]); - break; - case INDEX_op_ext16u_i32: - tcg_out_ext16u(s, COND_AL, args[0], args[1]); - break; - - case INDEX_op_deposit_i32: - tcg_out_deposit(s, COND_AL, args[0], args[2], - args[3], args[4], const_args[2]); - break; - case INDEX_op_extract_i32: - tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]); - break; - case INDEX_op_sextract_i32: - tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); - break; - case INDEX_op_extract2_i32: - /* ??? These optimization vs zero should be generic. */ - /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */ - if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); - } - } else if (const_args[2]) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, - args[1], SHIFT_IMM_LSR(args[3])); - } else { - /* We can do extract2 in 2 insns, vs the 3 required otherwise. */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, - args[2], SHIFT_IMM_LSL(32 - args[3])); - tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, - args[1], SHIFT_IMM_LSR(args[3])); - } - break; - - case INDEX_op_div_i32: - tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); - break; - case INDEX_op_divu_i32: - tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); - break; - - case INDEX_op_mb: - tcg_out_mb(s, args[0]); - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } }; - static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } }; - static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rIN - = { .args_ct_str = { "r", "r", "rIN" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_l_l - = { .args_ct_str = { "r", "r", "l", "l" } }; - static const TCGTargetOpDef s_s_s_s - = { .args_ct_str = { "s", "s", "s", "s" } }; - static const TCGTargetOpDef br - = { .args_ct_str = { "r", "rIN" } }; - static const TCGTargetOpDef ext2 - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "rI", "rI" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "rI", "rI" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_neg_i32: - case INDEX_op_not_i32: - case INDEX_op_bswap16_i32: - case INDEX_op_bswap32_i32: - case INDEX_op_ext8s_i32: - case INDEX_op_ext16s_i32: - case INDEX_op_ext16u_i32: - case INDEX_op_extract_i32: - case INDEX_op_sextract_i32: - return &r_r; - - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_setcond_i32: - return &r_r_rIN; - case INDEX_op_and_i32: - case INDEX_op_andc_i32: - case INDEX_op_clz_i32: - case INDEX_op_ctz_i32: - return &r_r_rIK; - case INDEX_op_mul_i32: - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - return &r_r_r; - case INDEX_op_mulu2_i32: - case INDEX_op_muls2_i32: - return &r_r_r_r; - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - return &r_r_rI; - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: - return &r_r_ri; - - case INDEX_op_brcond_i32: - return &br; - case INDEX_op_deposit_i32: - return &dep; - case INDEX_op_extract2_i32: - return &ext2; - case INDEX_op_movcond_i32: - return &movc; - case INDEX_op_add2_i32: - return &add2; - case INDEX_op_sub2_i32: - return &sub2; - case INDEX_op_brcond2_i32: - return &br2; - case INDEX_op_setcond2_i32: - return &setc2; - - case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; - case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; - case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; - - default: - return NULL; - } -} - -static void tcg_target_init(TCGContext *s) -{ - /* Only probe for the platform and capabilities if we havn't already - determined maximum values at compile time. */ -#ifndef use_idiv_instructions - { - unsigned long hwcap = qemu_getauxval(AT_HWCAP); - use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; - } -#endif - if (__ARM_ARCH < 7) { - const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); - if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { - arm_arch = pl[1] - '0'; - } - } - - tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; - - tcg_target_call_clobber_regs = 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); -} - -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); -} - -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - tcg_out_st32(s, COND_AL, arg, arg1, arg2); -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - return false; -} - -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) -{ - tcg_out_mov_reg(s, COND_AL, ret, arg); - return true; -} - -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - tcg_out_movi32(s, COND_AL, ret, arg); -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i = 0; i < count; ++i) { - p[i] = INSN_NOP; - } -} - -/* Compute frame size via macros, to share between tcg_target_qemu_prologue - and tcg_register_jit. */ - -#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) - -#define FRAME_SIZE \ - ((PUSH_SIZE \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long) \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & -TCG_TARGET_STACK_ALIGN) - -#define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE) - -static void tcg_target_qemu_prologue(TCGContext *s) -{ - /* Calling convention requires us to save r4-r11 and lr. */ - /* stmdb sp!, { r4 - r11, lr } */ - tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); - - /* Reserve callee argument and tcg temp space. */ - tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, STACK_ADDEND, 1); - tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - - tcg_out_bx(s, COND_AL, tcg_target_call_iarg_regs[1]); - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); - tcg_out_epilogue(s); -} - -static void tcg_out_epilogue(TCGContext *s) -{ - /* Release local stack frame. */ - tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK, - TCG_REG_CALL_STACK, STACK_ADDEND, 1); - - /* ldmia sp!, { r4 - r11, pc } */ - tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[18]; -} DebugFrame; - -#define ELF_HOST_MACHINE EM_ARM - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x7c, /* sleb128 -4 */ - .h.cie.return_column = 14, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, 13, /* DW_CFA_def_cfa sp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - /* The following must match the stmdb in the prologue. */ - 0x8e, 1, /* DW_CFA_offset, lr, -4 */ - 0x8b, 2, /* DW_CFA_offset, r11, -8 */ - 0x8a, 3, /* DW_CFA_offset, r10, -12 */ - 0x89, 4, /* DW_CFA_offset, r9, -16 */ - 0x88, 5, /* DW_CFA_offset, r8, -20 */ - 0x87, 6, /* DW_CFA_offset, r7, -24 */ - 0x86, 7, /* DW_CFA_offset, r6, -28 */ - 0x85, 8, /* DW_CFA_offset, r5, -32 */ - 0x84, 9, /* DW_CFA_offset, r4, -36 */ - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc new file mode 100644 index 0000000000..0155c0691c --- /dev/null +++ b/tcg/i386/tcg-target.c.inc @@ -0,0 +1,4016 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "../tcg-pool.c.inc" + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { +#if TCG_TARGET_REG_BITS == 64 + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", +#else + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", +#endif + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", +#if TCG_TARGET_REG_BITS == 64 + "%xmm8", "%xmm9", "%xmm10", "%xmm11", + "%xmm12", "%xmm13", "%xmm14", "%xmm15", +#endif +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { +#if TCG_TARGET_REG_BITS == 64 + TCG_REG_RBP, + TCG_REG_RBX, + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, + TCG_REG_R15, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R9, + TCG_REG_R8, + TCG_REG_RCX, + TCG_REG_RDX, + TCG_REG_RSI, + TCG_REG_RDI, + TCG_REG_RAX, +#else + TCG_REG_EBX, + TCG_REG_ESI, + TCG_REG_EDI, + TCG_REG_EBP, + TCG_REG_ECX, + TCG_REG_EDX, + TCG_REG_EAX, +#endif + TCG_REG_XMM0, + TCG_REG_XMM1, + TCG_REG_XMM2, + TCG_REG_XMM3, + TCG_REG_XMM4, + TCG_REG_XMM5, +#ifndef _WIN64 + /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save + any of them. Therefore only allow xmm0-xmm5 to be allocated. */ + TCG_REG_XMM6, + TCG_REG_XMM7, +#if TCG_TARGET_REG_BITS == 64 + TCG_REG_XMM8, + TCG_REG_XMM9, + TCG_REG_XMM10, + TCG_REG_XMM11, + TCG_REG_XMM12, + TCG_REG_XMM13, + TCG_REG_XMM14, + TCG_REG_XMM15, +#endif +#endif +}; + +static const int tcg_target_call_iarg_regs[] = { +#if TCG_TARGET_REG_BITS == 64 +#if defined(_WIN64) + TCG_REG_RCX, + TCG_REG_RDX, +#else + TCG_REG_RDI, + TCG_REG_RSI, + TCG_REG_RDX, + TCG_REG_RCX, +#endif + TCG_REG_R8, + TCG_REG_R9, +#else + /* 32 bit mode uses stack based calling convention (GCC default). */ +#endif +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_EAX, +#if TCG_TARGET_REG_BITS == 32 + TCG_REG_EDX +#endif +}; + +/* Constants we accept. */ +#define TCG_CT_CONST_S32 0x100 +#define TCG_CT_CONST_U32 0x200 +#define TCG_CT_CONST_I32 0x400 +#define TCG_CT_CONST_WSZ 0x800 + +/* Registers used with L constraint, which are the first argument + registers on x86_64, and two random call clobbered registers on + i386. */ +#if TCG_TARGET_REG_BITS == 64 +# define TCG_REG_L0 tcg_target_call_iarg_regs[0] +# define TCG_REG_L1 tcg_target_call_iarg_regs[1] +#else +# define TCG_REG_L0 TCG_REG_EAX +# define TCG_REG_L1 TCG_REG_EDX +#endif + +/* The host compiler should supply to enable runtime features + detection, as we're not going to go so far as our own inline assembly. + If not available, default values will be assumed. */ +#if defined(CONFIG_CPUID_H) +#include "qemu/cpuid.h" +#endif + +/* For 64-bit, we always know that CMOV is available. */ +#if TCG_TARGET_REG_BITS == 64 +# define have_cmov 1 +#elif defined(CONFIG_CPUID_H) +static bool have_cmov; +#else +# define have_cmov 0 +#endif + +/* We need these symbols in tcg-target.h, and we can't properly conditionalize + it there. Therefore we always define the variable. */ +bool have_bmi1; +bool have_popcnt; +bool have_avx1; +bool have_avx2; + +#ifdef CONFIG_CPUID_H +static bool have_movbe; +static bool have_bmi2; +static bool have_lzcnt; +#else +# define have_movbe 0 +# define have_bmi2 0 +# define have_lzcnt 0 +#endif + +static tcg_insn_unit *tb_ret_addr; + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + value += addend; + switch(type) { + case R_386_PC32: + value -= (uintptr_t)code_ptr; + if (value != (int32_t)value) { + return false; + } + /* FALLTHRU */ + case R_386_32: + tcg_patch32(code_ptr, value); + break; + case R_386_PC8: + value -= (uintptr_t)code_ptr; + if (value != (int8_t)value) { + return false; + } + tcg_patch8(code_ptr, value); + break; + default: + tcg_abort(); + } + return true; +} + +#if TCG_TARGET_REG_BITS == 64 +#define ALL_GENERAL_REGS 0x0000ffffu +#define ALL_VECTOR_REGS 0xffff0000u +#else +#define ALL_GENERAL_REGS 0x000000ffu +#define ALL_VECTOR_REGS 0x00ff0000u +#endif + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch(*ct_str++) { + case 'a': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); + break; + case 'b': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); + break; + case 'c': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); + break; + case 'd': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); + break; + case 'S': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); + break; + case 'D': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); + break; + case 'q': + /* A register that can be used as a byte operand. */ + ct->ct |= TCG_CT_REG; + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; + break; + case 'Q': + /* A register with an addressable second byte (e.g. %ah). */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xf; + break; + case 'r': + /* A general register. */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= ALL_GENERAL_REGS; + break; + case 'W': + /* With TZCNT/LZCNT, we can have operand-size as an input. */ + ct->ct |= TCG_CT_CONST_WSZ; + break; + case 'x': + /* A vector register. */ + ct->ct |= TCG_CT_REG; + ct->u.regs |= ALL_VECTOR_REGS; + break; + + /* qemu_ld/st address constraint */ + case 'L': + ct->ct |= TCG_CT_REG; + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); + break; + + case 'e': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); + break; + case 'Z': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32); + break; + case 'I': + ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32); + break; + + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static inline int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + return 1; + } + if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { + return 1; + } + if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { + return 1; + } + return 0; +} + +# define LOWREGMASK(x) ((x) & 7) + +#define P_EXT 0x100 /* 0x0f opcode prefix */ +#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ +#define P_DATA16 0x400 /* 0x66 opcode prefix */ +#if TCG_TARGET_REG_BITS == 64 +# define P_REXW 0x1000 /* Set REX.W = 1 */ +# define P_REXB_R 0x2000 /* REG field as byte register */ +# define P_REXB_RM 0x4000 /* R/M field as byte register */ +# define P_GS 0x8000 /* gs segment override */ +#else +# define P_REXW 0 +# define P_REXB_R 0 +# define P_REXB_RM 0 +# define P_GS 0 +#endif +#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ +#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ +#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ +#define P_VEXL 0x80000 /* Set VEX.L = 1 */ + +#define OPC_ARITH_EvIz (0x81) +#define OPC_ARITH_EvIb (0x83) +#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ +#define OPC_ANDN (0xf2 | P_EXT38) +#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) +#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) +#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) +#define OPC_BSF (0xbc | P_EXT) +#define OPC_BSR (0xbd | P_EXT) +#define OPC_BSWAP (0xc8 | P_EXT) +#define OPC_CALL_Jz (0xe8) +#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ +#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) +#define OPC_DEC_r32 (0x48) +#define OPC_IMUL_GvEv (0xaf | P_EXT) +#define OPC_IMUL_GvEvIb (0x6b) +#define OPC_IMUL_GvEvIz (0x69) +#define OPC_INC_r32 (0x40) +#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ +#define OPC_JCC_short (0x70) /* ... plus condition code */ +#define OPC_JMP_long (0xe9) +#define OPC_JMP_short (0xeb) +#define OPC_LEA (0x8d) +#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) +#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ +#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ +#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ +#define OPC_MOVB_EvIz (0xc6) +#define OPC_MOVL_EvIz (0xc7) +#define OPC_MOVL_Iv (0xb8) +#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) +#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) +#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) +#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) +#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) +#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) +#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) +#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) +#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) +#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) +#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) +#define OPC_MOVSBL (0xbe | P_EXT) +#define OPC_MOVSWL (0xbf | P_EXT) +#define OPC_MOVSLQ (0x63 | P_REXW) +#define OPC_MOVZBL (0xb6 | P_EXT) +#define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) +#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) +#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) +#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) +#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) +#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) +#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) +#define OPC_PADDB (0xfc | P_EXT | P_DATA16) +#define OPC_PADDW (0xfd | P_EXT | P_DATA16) +#define OPC_PADDD (0xfe | P_EXT | P_DATA16) +#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PADDSB (0xec | P_EXT | P_DATA16) +#define OPC_PADDSW (0xed | P_EXT | P_DATA16) +#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) +#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) +#define OPC_PAND (0xdb | P_EXT | P_DATA16) +#define OPC_PANDN (0xdf | P_EXT | P_DATA16) +#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) +#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) +#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) +#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) +#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) +#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) +#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) +#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) +#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) +#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) +#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) +#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) +#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) +#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) +#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) +#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) +#define OPC_PMINSW (0xea | P_EXT | P_DATA16) +#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) +#define OPC_PMINUB (0xda | P_EXT | P_DATA16) +#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) +#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) +#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) +#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) +#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) +#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) +#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) +#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) +#define OPC_POR (0xeb | P_EXT | P_DATA16) +#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) +#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) +#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) +#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) +#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) +#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) +#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) +#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) +#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) +#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) +#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) +#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) +#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) +#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) +#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) +#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) +#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) +#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) +#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) +#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) +#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) +#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) +#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) +#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) +#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) +#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) +#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) +#define OPC_PXOR (0xef | P_EXT | P_DATA16) +#define OPC_POP_r32 (0x58) +#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) +#define OPC_PUSH_r32 (0x50) +#define OPC_PUSH_Iv (0x68) +#define OPC_PUSH_Ib (0x6a) +#define OPC_RET (0xc3) +#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ +#define OPC_SHIFT_1 (0xd1) +#define OPC_SHIFT_Ib (0xc1) +#define OPC_SHIFT_cl (0xd3) +#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) +#define OPC_SHUFPS (0xc6 | P_EXT) +#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) +#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) +#define OPC_SHRD_Ib (0xac | P_EXT) +#define OPC_TESTL (0x85) +#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) +#define OPC_UD2 (0x0b | P_EXT) +#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) +#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) +#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) +#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) +#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) +#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) +#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) +#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) +#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) +#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) +#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) +#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VZEROUPPER (0x77 | P_EXT) +#define OPC_XCHG_ax_r32 (0x90) + +#define OPC_GRP3_Ev (0xf7) +#define OPC_GRP5 (0xff) +#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) + +/* Group 1 opcode extensions for 0x80-0x83. + These are also used as modifiers for OPC_ARITH. */ +#define ARITH_ADD 0 +#define ARITH_OR 1 +#define ARITH_ADC 2 +#define ARITH_SBB 3 +#define ARITH_AND 4 +#define ARITH_SUB 5 +#define ARITH_XOR 6 +#define ARITH_CMP 7 + +/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ +#define SHIFT_ROL 0 +#define SHIFT_ROR 1 +#define SHIFT_SHL 4 +#define SHIFT_SHR 5 +#define SHIFT_SAR 7 + +/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ +#define EXT3_NOT 2 +#define EXT3_NEG 3 +#define EXT3_MUL 4 +#define EXT3_IMUL 5 +#define EXT3_DIV 6 +#define EXT3_IDIV 7 + +/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ +#define EXT5_INC_Ev 0 +#define EXT5_DEC_Ev 1 +#define EXT5_CALLN_Ev 2 +#define EXT5_JMPN_Ev 4 + +/* Condition codes to be added to OPC_JCC_{long,short}. */ +#define JCC_JMP (-1) +#define JCC_JO 0x0 +#define JCC_JNO 0x1 +#define JCC_JB 0x2 +#define JCC_JAE 0x3 +#define JCC_JE 0x4 +#define JCC_JNE 0x5 +#define JCC_JBE 0x6 +#define JCC_JA 0x7 +#define JCC_JS 0x8 +#define JCC_JNS 0x9 +#define JCC_JP 0xa +#define JCC_JNP 0xb +#define JCC_JL 0xc +#define JCC_JGE 0xd +#define JCC_JLE 0xe +#define JCC_JG 0xf + +static const uint8_t tcg_cond_to_jcc[] = { + [TCG_COND_EQ] = JCC_JE, + [TCG_COND_NE] = JCC_JNE, + [TCG_COND_LT] = JCC_JL, + [TCG_COND_GE] = JCC_JGE, + [TCG_COND_LE] = JCC_JLE, + [TCG_COND_GT] = JCC_JG, + [TCG_COND_LTU] = JCC_JB, + [TCG_COND_GEU] = JCC_JAE, + [TCG_COND_LEU] = JCC_JBE, + [TCG_COND_GTU] = JCC_JA, +}; + +#if TCG_TARGET_REG_BITS == 64 +static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) +{ + int rex; + + if (opc & P_GS) { + tcg_out8(s, 0x65); + } + if (opc & P_DATA16) { + /* We should never be asking for both 16 and 64-bit operation. */ + tcg_debug_assert((opc & P_REXW) == 0); + tcg_out8(s, 0x66); + } + if (opc & P_SIMDF3) { + tcg_out8(s, 0xf3); + } else if (opc & P_SIMDF2) { + tcg_out8(s, 0xf2); + } + + rex = 0; + rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ + rex |= (r & 8) >> 1; /* REX.R */ + rex |= (x & 8) >> 2; /* REX.X */ + rex |= (rm & 8) >> 3; /* REX.B */ + + /* P_REXB_{R,RM} indicates that the given register is the low byte. + For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, + as otherwise the encoding indicates %[abcd]h. Note that the values + that are ORed in merely indicate that the REX byte must be present; + those bits get discarded in output. */ + rex |= opc & (r >= 4 ? P_REXB_R : 0); + rex |= opc & (rm >= 4 ? P_REXB_RM : 0); + + if (rex) { + tcg_out8(s, (uint8_t)(rex | 0x40)); + } + + if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { + tcg_out8(s, 0x0f); + if (opc & P_EXT38) { + tcg_out8(s, 0x38); + } else if (opc & P_EXT3A) { + tcg_out8(s, 0x3a); + } + } + + tcg_out8(s, opc); +} +#else +static void tcg_out_opc(TCGContext *s, int opc) +{ + if (opc & P_DATA16) { + tcg_out8(s, 0x66); + } + if (opc & P_SIMDF3) { + tcg_out8(s, 0xf3); + } else if (opc & P_SIMDF2) { + tcg_out8(s, 0xf2); + } + if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { + tcg_out8(s, 0x0f); + if (opc & P_EXT38) { + tcg_out8(s, 0x38); + } else if (opc & P_EXT3A) { + tcg_out8(s, 0x3a); + } + } + tcg_out8(s, opc); +} +/* Discard the register arguments to tcg_out_opc early, so as not to penalize + the 32-bit compilation paths. This method works with all versions of gcc, + whereas relying on optimization may not be able to exclude them. */ +#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) +#endif + +static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) +{ + tcg_out_opc(s, opc, r, rm, 0); + tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); +} + +static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, + int rm, int index) +{ + int tmp; + + /* Use the two byte form if possible, which cannot encode + VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ + if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT + && ((rm | index) & 8) == 0) { + /* Two byte VEX prefix. */ + tcg_out8(s, 0xc5); + + tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ + } else { + /* Three byte VEX prefix. */ + tcg_out8(s, 0xc4); + + /* VEX.m-mmmm */ + if (opc & P_EXT3A) { + tmp = 3; + } else if (opc & P_EXT38) { + tmp = 2; + } else if (opc & P_EXT) { + tmp = 1; + } else { + g_assert_not_reached(); + } + tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ + tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ + tcg_out8(s, tmp); + + tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + } + + tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ + /* VEX.pp */ + if (opc & P_DATA16) { + tmp |= 1; /* 0x66 */ + } else if (opc & P_SIMDF3) { + tmp |= 2; /* 0xf3 */ + } else if (opc & P_SIMDF2) { + tmp |= 3; /* 0xf2 */ + } + tmp |= (~v & 15) << 3; /* VEX.vvvv */ + tcg_out8(s, tmp); + tcg_out8(s, opc); +} + +static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +{ + tcg_out_vex_opc(s, opc, r, v, rm, 0); + tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); +} + +/* Output an opcode with a full "rm + (index<code_ptr + 5 + ~rm; + intptr_t disp = offset - pc; + if (disp == (int32_t)disp) { + tcg_out8(s, (LOWREGMASK(r) << 3) | 5); + tcg_out32(s, disp); + return; + } + + /* Try for an absolute address encoding. This requires the + use of the MODRM+SIB encoding and is therefore larger than + rip-relative addressing. */ + if (offset == (int32_t)offset) { + tcg_out8(s, (LOWREGMASK(r) << 3) | 4); + tcg_out8(s, (4 << 3) | 5); + tcg_out32(s, offset); + return; + } + + /* ??? The memory isn't directly addressable. */ + g_assert_not_reached(); + } else { + /* Absolute address. */ + tcg_out8(s, (r << 3) | 5); + tcg_out32(s, offset); + return; + } + } + + /* Find the length of the immediate addend. Note that the encoding + that would be used for (%ebp) indicates absolute addressing. */ + if (rm < 0) { + mod = 0, len = 4, rm = 5; + } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { + mod = 0, len = 0; + } else if (offset == (int8_t)offset) { + mod = 0x40, len = 1; + } else { + mod = 0x80, len = 4; + } + + /* Use a single byte MODRM format if possible. Note that the encoding + that would be used for %esp is the escape to the two byte form. */ + if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { + /* Single byte MODRM format. */ + tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); + } else { + /* Two byte MODRM+SIB format. */ + + /* Note that the encoding that would place %esp into the index + field indicates no index register. In 64-bit mode, the REX.X + bit counts, so %r12 can be used as the index. */ + if (index < 0) { + index = 4; + } else { + tcg_debug_assert(index != TCG_REG_ESP); + } + + tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); + tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); + } + + if (len == 1) { + tcg_out8(s, offset); + } else if (len == 4) { + tcg_out32(s, offset); + } +} + +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, + int index, int shift, intptr_t offset) +{ + tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, + int rm, int index, int shift, + intptr_t offset) +{ + tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + +/* A simplification of the above with no index or shift. */ +static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, + int rm, intptr_t offset) +{ + tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); +} + +static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, + int v, int rm, intptr_t offset) +{ + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); +} + +/* Output an opcode with an expected reference to the constant pool. */ +static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) +{ + tcg_out_opc(s, opc, r, 0, 0); + /* Absolute for 32-bit, pc-relative for 64-bit. */ + tcg_out8(s, LOWREGMASK(r) << 3 | 5); + tcg_out32(s, 0); +} + +/* Output an opcode with an expected reference to the constant pool. */ +static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) +{ + tcg_out_vex_opc(s, opc, r, 0, 0, 0); + /* Absolute for 32-bit, pc-relative for 64-bit. */ + tcg_out8(s, LOWREGMASK(r) << 3 | 5); + tcg_out32(s, 0); +} + +/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ +static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) +{ + /* Propagate an opcode prefix, such as P_REXW. */ + int ext = subop & ~0x7; + subop &= 0x7; + + tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); +} + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + int rexw = 0; + + if (arg == ret) { + return true; + } + switch (type) { + case TCG_TYPE_I64: + rexw = P_REXW; + /* fallthru */ + case TCG_TYPE_I32: + if (ret < 16) { + if (arg < 16) { + tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); + } else { + tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); + } + } else { + if (arg < 16) { + tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); + } else { + tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); + } + } + break; + + case TCG_TYPE_V64: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); + break; + case TCG_TYPE_V256: + tcg_debug_assert(ret >= 16 && arg >= 16); + tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); + break; + + default: + g_assert_not_reached(); + } + return true; +} + +static const int avx2_dup_insn[4] = { + OPC_VPBROADCASTB, OPC_VPBROADCASTW, + OPC_VPBROADCASTD, OPC_VPBROADCASTQ, +}; + +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg a) +{ + if (have_avx2) { + int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); + tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a); + } else { + switch (vece) { + case MO_8: + /* ??? With zero in a register, use PSHUFB. */ + tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); + a = r; + /* FALLTHRU */ + case MO_16: + tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); + a = r; + /* FALLTHRU */ + case MO_32: + tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); + /* imm8 operand: all output lanes selected from input lane 0. */ + tcg_out8(s, 0); + break; + case MO_64: + tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); + break; + default: + g_assert_not_reached(); + } + } + return true; +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + if (have_avx2) { + int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); + tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, + r, 0, base, offset); + } else { + switch (vece) { + case MO_64: + tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); + break; + case MO_32: + tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); + break; + case MO_16: + tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + case MO_8: + tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + default: + g_assert_not_reached(); + } + } + return true; +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); + + if (arg == 0) { + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); + return; + } + if (arg == -1) { + tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); + return; + } + + if (TCG_TARGET_REG_BITS == 64) { + if (type == TCG_TYPE_V64) { + tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); + } else if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); + } + new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); + } else { + if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + } + new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); + } +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_target_long diff; + + switch (type) { + case TCG_TYPE_I32: +#if TCG_TARGET_REG_BITS == 64 + case TCG_TYPE_I64: +#endif + if (ret < 16) { + break; + } + /* fallthru */ + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + tcg_debug_assert(ret >= 16); + tcg_out_dupi_vec(s, type, ret, arg); + return; + default: + g_assert_not_reached(); + } + + if (arg == 0) { + tgen_arithr(s, ARITH_XOR, ret, ret); + return; + } + if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { + tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); + tcg_out32(s, arg); + return; + } + if (arg == (int32_t)arg) { + tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); + tcg_out32(s, arg); + return; + } + + /* Try a 7 byte pc-relative lea before the 10 byte movq. */ + diff = arg - ((uintptr_t)s->code_ptr + 7); + if (diff == (int32_t)diff) { + tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); + tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); + tcg_out32(s, diff); + return; + } + + tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); + tcg_out64(s, arg); +} + +static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) +{ + if (val == (int8_t)val) { + tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); + tcg_out8(s, val); + } else if (val == (int32_t)val) { + tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); + tcg_out32(s, val); + } else { + tcg_abort(); + } +} + +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* Given the strength of x86 memory ordering, we only need care for + store-load ordering. Experimentally, "lock orl $0,0(%esp)" is + faster than "mfence", so don't bother with the sse insn. */ + if (a0 & TCG_MO_ST_LD) { + tcg_out8(s, 0xf0); + tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); + tcg_out8(s, 0); + } +} + +static inline void tcg_out_push(TCGContext *s, int reg) +{ + tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); +} + +static inline void tcg_out_pop(TCGContext *s, int reg) +{ + tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) +{ + switch (type) { + case TCG_TYPE_I32: + if (ret < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); + } else { + tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); + } + break; + case TCG_TYPE_I64: + if (ret < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); + break; + } + /* FALLTHRU */ + case TCG_TYPE_V64: + /* There is no instruction that can validate 8-byte alignment. */ + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); + break; + case TCG_TYPE_V128: + /* + * The gvec infrastructure is asserts that v128 vector loads + * and stores use a 16-byte aligned offset. Validate that the + * final pointer is aligned by using an insn that will SIGSEGV. + */ + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); + break; + case TCG_TYPE_V256: + /* + * The gvec infrastructure only requires 16-byte alignment, + * so here we must use an unaligned load. + */ + tcg_debug_assert(ret >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, + ret, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + switch (type) { + case TCG_TYPE_I32: + if (arg < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); + } else { + tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); + } + break; + case TCG_TYPE_I64: + if (arg < 16) { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); + break; + } + /* FALLTHRU */ + case TCG_TYPE_V64: + /* There is no instruction that can validate 8-byte alignment. */ + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); + break; + case TCG_TYPE_V128: + /* + * The gvec infrastructure is asserts that v128 vector loads + * and stores use a 16-byte aligned offset. Validate that the + * final pointer is aligned by using an insn that will SIGSEGV. + */ + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + break; + case TCG_TYPE_V256: + /* + * The gvec infrastructure only requires 16-byte alignment, + * so here we must use an unaligned store. + */ + tcg_debug_assert(arg >= 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, + arg, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } +} + +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + int rexw = 0; + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { + if (val != (int32_t)val) { + return false; + } + rexw = P_REXW; + } else if (type != TCG_TYPE_I32) { + return false; + } + tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); + tcg_out32(s, val); + return true; +} + +static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) +{ + /* Propagate an opcode prefix, such as P_DATA16. */ + int ext = subopc & ~0x7; + subopc &= 0x7; + + if (count == 1) { + tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); + } else { + tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); + tcg_out8(s, count); + } +} + +static inline void tcg_out_bswap32(TCGContext *s, int reg) +{ + tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); +} + +static inline void tcg_out_rolw_8(TCGContext *s, int reg) +{ + tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); +} + +static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) +{ + /* movzbl */ + tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); + tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); +} + +static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw) +{ + /* movsbl */ + tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); + tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); +} + +static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) +{ + /* movzwl */ + tcg_out_modrm(s, OPC_MOVZWL, dest, src); +} + +static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw) +{ + /* movsw[lq] */ + tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); +} + +static inline void tcg_out_ext32u(TCGContext *s, int dest, int src) +{ + /* 32-bit mov zero extends. */ + tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); +} + +static inline void tcg_out_ext32s(TCGContext *s, int dest, int src) +{ + tcg_out_modrm(s, OPC_MOVSLQ, dest, src); +} + +static inline void tcg_out_bswap64(TCGContext *s, int reg) +{ + tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); +} + +static void tgen_arithi(TCGContext *s, int c, int r0, + tcg_target_long val, int cf) +{ + int rexw = 0; + + if (TCG_TARGET_REG_BITS == 64) { + rexw = c & -8; + c &= 7; + } + + /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce + partial flags update stalls on Pentium4 and are not recommended + by current Intel optimization manuals. */ + if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) { + int is_inc = (c == ARITH_ADD) ^ (val < 0); + if (TCG_TARGET_REG_BITS == 64) { + /* The single-byte increment encodings are re-tasked as the + REX prefixes. Use the MODRM encoding. */ + tcg_out_modrm(s, OPC_GRP5 + rexw, + (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); + } else { + tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); + } + return; + } + + if (c == ARITH_AND) { + if (TCG_TARGET_REG_BITS == 64) { + if (val == 0xffffffffu) { + tcg_out_ext32u(s, r0, r0); + return; + } + if (val == (uint32_t)val) { + /* AND with no high bits set can use a 32-bit operation. */ + rexw = 0; + } + } + if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { + tcg_out_ext8u(s, r0, r0); + return; + } + if (val == 0xffffu) { + tcg_out_ext16u(s, r0, r0); + return; + } + } + + if (val == (int8_t)val) { + tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); + tcg_out8(s, val); + return; + } + if (rexw == 0 || val == (int32_t)val) { + tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); + tcg_out32(s, val); + return; + } + + tcg_abort(); +} + +static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) +{ + if (val != 0) { + tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); + } +} + +/* Use SMALL != 0 to force a short forward branch. */ +static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) +{ + int32_t val, val1; + + if (l->has_value) { + val = tcg_pcrel_diff(s, l->u.value_ptr); + val1 = val - 2; + if ((int8_t)val1 == val1) { + if (opc == -1) { + tcg_out8(s, OPC_JMP_short); + } else { + tcg_out8(s, OPC_JCC_short + opc); + } + tcg_out8(s, val1); + } else { + if (small) { + tcg_abort(); + } + if (opc == -1) { + tcg_out8(s, OPC_JMP_long); + tcg_out32(s, val - 5); + } else { + tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); + tcg_out32(s, val - 6); + } + } + } else if (small) { + if (opc == -1) { + tcg_out8(s, OPC_JMP_short); + } else { + tcg_out8(s, OPC_JCC_short + opc); + } + tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); + s->code_ptr += 1; + } else { + if (opc == -1) { + tcg_out8(s, OPC_JMP_long); + } else { + tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); + } + tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); + s->code_ptr += 4; + } +} + +static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, + int const_arg2, int rexw) +{ + if (const_arg2) { + if (arg2 == 0) { + /* test r, r */ + tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); + } else { + tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); + } + } else { + tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); + } +} + +static void tcg_out_brcond32(TCGContext *s, TCGCond cond, + TCGArg arg1, TCGArg arg2, int const_arg2, + TCGLabel *label, int small) +{ + tcg_out_cmp(s, arg1, arg2, const_arg2, 0); + tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); +} + +#if TCG_TARGET_REG_BITS == 64 +static void tcg_out_brcond64(TCGContext *s, TCGCond cond, + TCGArg arg1, TCGArg arg2, int const_arg2, + TCGLabel *label, int small) +{ + tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); + tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); +} +#else +/* XXX: we implement it at the target level to avoid having to + handle cross basic blocks temporaries */ +static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, + const int *const_args, int small) +{ + TCGLabel *label_next = gen_new_label(); + TCGLabel *label_this = arg_label(args[5]); + + switch(args[4]) { + case TCG_COND_EQ: + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], + label_next, 1); + tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], + label_this, small); + break; + case TCG_COND_NE: + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], + label_this, small); + tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], + label_this, small); + break; + case TCG_COND_LT: + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_LE: + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_GT: + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_GE: + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_LTU: + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_LEU: + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_GTU: + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], + label_this, small); + break; + case TCG_COND_GEU: + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], + label_this, small); + tcg_out_jxx(s, JCC_JNE, label_next, 1); + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], + label_this, small); + break; + default: + tcg_abort(); + } + tcg_out_label(s, label_next, s->code_ptr); +} +#endif + +static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, + TCGArg arg1, TCGArg arg2, int const_arg2) +{ + tcg_out_cmp(s, arg1, arg2, const_arg2, 0); + tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); + tcg_out_ext8u(s, dest, dest); +} + +#if TCG_TARGET_REG_BITS == 64 +static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, + TCGArg arg1, TCGArg arg2, int const_arg2) +{ + tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); + tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); + tcg_out_ext8u(s, dest, dest); +} +#else +static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGArg new_args[6]; + TCGLabel *label_true, *label_over; + + memcpy(new_args, args+1, 5*sizeof(TCGArg)); + + if (args[0] == args[1] || args[0] == args[2] + || (!const_args[3] && args[0] == args[3]) + || (!const_args[4] && args[0] == args[4])) { + /* When the destination overlaps with one of the argument + registers, don't do anything tricky. */ + label_true = gen_new_label(); + label_over = gen_new_label(); + + new_args[5] = label_arg(label_true); + tcg_out_brcond2(s, new_args, const_args+1, 1); + + tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); + tcg_out_jxx(s, JCC_JMP, label_over, 1); + tcg_out_label(s, label_true, s->code_ptr); + + tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); + tcg_out_label(s, label_over, s->code_ptr); + } else { + /* When the destination does not overlap one of the arguments, + clear the destination first, jump if cond false, and emit an + increment in the true case. This results in smaller code. */ + + tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); + + label_over = gen_new_label(); + new_args[4] = tcg_invert_cond(new_args[4]); + new_args[5] = label_arg(label_over); + tcg_out_brcond2(s, new_args, const_args+1, 1); + + tgen_arithi(s, ARITH_ADD, args[0], 1, 0); + tcg_out_label(s, label_over, s->code_ptr); + } +} +#endif + +static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, + TCGReg dest, TCGReg v1) +{ + if (have_cmov) { + tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1); + } else { + TCGLabel *over = gen_new_label(); + tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); + tcg_out_mov(s, TCG_TYPE_I32, dest, v1); + tcg_out_label(s, over, s->code_ptr); + } +} + +static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, + TCGReg c1, TCGArg c2, int const_c2, + TCGReg v1) +{ + tcg_out_cmp(s, c1, c2, const_c2, 0); + tcg_out_cmov(s, cond, 0, dest, v1); +} + +#if TCG_TARGET_REG_BITS == 64 +static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, + TCGReg c1, TCGArg c2, int const_c2, + TCGReg v1) +{ + tcg_out_cmp(s, c1, c2, const_c2, P_REXW); + tcg_out_cmov(s, cond, P_REXW, dest, v1); +} +#endif + +static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, + TCGArg arg2, bool const_a2) +{ + if (have_bmi1) { + tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); + if (const_a2) { + tcg_debug_assert(arg2 == (rexw ? 64 : 32)); + } else { + tcg_debug_assert(dest != arg2); + tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); + } + } else { + tcg_debug_assert(dest != arg2); + tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); + tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); + } +} + +static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, + TCGArg arg2, bool const_a2) +{ + if (have_lzcnt) { + tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); + if (const_a2) { + tcg_debug_assert(arg2 == (rexw ? 64 : 32)); + } else { + tcg_debug_assert(dest != arg2); + tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); + } + } else { + tcg_debug_assert(!const_a2); + tcg_debug_assert(dest != arg1); + tcg_debug_assert(dest != arg2); + + /* Recall that the output of BSR is the index not the count. */ + tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1); + tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); + + /* Since we have destroyed the flags from BSR, we have to re-test. */ + tcg_out_cmp(s, arg1, 0, 1, rexw); + tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); + } +} + +static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) +{ + intptr_t disp = tcg_pcrel_diff(s, dest) - 5; + + if (disp == (int32_t)disp) { + tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); + tcg_out32(s, disp); + } else { + /* rip-relative addressing into the constant pool. + This is 6 + 8 = 14 bytes, as compared to using an + an immediate load 10 + 6 = 16 bytes, plus we may + be able to re-use the pool constant for more calls. */ + tcg_out_opc(s, OPC_GRP5, 0, 0, 0); + tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); + new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); + tcg_out32(s, 0); + } +} + +static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +{ + tcg_out_branch(s, 1, dest); +} + +static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) +{ + tcg_out_branch(s, 0, dest); +} + +static void tcg_out_nopn(TCGContext *s, int n) +{ + int i; + /* Emit 1 or 2 operand size prefixes for the standard one byte nop, + * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the + * duplicate prefix, and all of the interesting recent cores can + * decode and discard the duplicates in a single cycle. + */ + tcg_debug_assert(n >= 1); + for (i = 1; i < n; ++i) { + tcg_out8(s, 0x66); + } + tcg_out8(s, 0x90); +} + +#if defined(CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * int mmu_idx, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, int mmu_idx, uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +/* Perform the TLB load and compare. + + Inputs: + ADDRLO and ADDRHI contain the low and high part of the address. + + MEM_INDEX and S_BITS are the memory context and log2 size of the load. + + WHICH is the offset into the CPUTLBEntry structure of the slot to read. + This should be offsetof addr_read or addr_write. + + Outputs: + LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses) + positions of the displacements of forward jumps to the TLB miss case. + + Second argument register is loaded with the low part of the address. + In the TLB hit case, it has been adjusted as indicated by the TLB + and so is a host address. In the TLB miss case, it continues to + hold a guest address. + + First argument register is clobbered. */ + +static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, MemOp opc, + tcg_insn_unit **label_ptr, int which) +{ + const TCGReg r0 = TCG_REG_L0; + const TCGReg r1 = TCG_REG_L1; + TCGType ttype = TCG_TYPE_I32; + TCGType tlbtype = TCG_TYPE_I32; + int trexw = 0, hrexw = 0, tlbrexw = 0; + unsigned a_bits = get_alignment_bits(opc); + unsigned s_bits = opc & MO_SIZE; + unsigned a_mask = (1 << a_bits) - 1; + unsigned s_mask = (1 << s_bits) - 1; + target_ulong tlb_mask; + + if (TCG_TARGET_REG_BITS == 64) { + if (TARGET_LONG_BITS == 64) { + ttype = TCG_TYPE_I64; + trexw = P_REXW; + } + if (TCG_TYPE_PTR == TCG_TYPE_I64) { + hrexw = P_REXW; + if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { + tlbtype = TCG_TYPE_I64; + tlbrexw = P_REXW; + } + } + } + + tcg_out_mov(s, tlbtype, r0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); + + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); + + /* If the required alignment is at least as large as the access, simply + copy the address and mask. For lesser alignments, check that we don't + cross pages for the complete access. */ + if (a_bits >= s_bits) { + tcg_out_mov(s, ttype, r1, addrlo); + } else { + tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask); + } + tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; + tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); + + /* cmp 0(r0), r1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which); + + /* Prepare for both the fast path add of the tlb addend, and the slow + path function argument setup. */ + tcg_out_mov(s, ttype, r1, addrlo); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + label_ptr[0] = s->code_ptr; + s->code_ptr += 4; + + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + /* cmp 4(r0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + label_ptr[1] = s->code_ptr; + s->code_ptr += 4; + } + + /* TLB Hit. */ + + /* add addend(r0), r1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + offsetof(CPUTLBEntry, addend)); +} + +/* + * Record the context of a call to the out of line helper code for the slow path + * for a load or store, so that we can later generate the correct helper code + */ +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, + TCGMemOpIdx oi, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + tcg_insn_unit *raddr, + tcg_insn_unit **label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0] = label_ptr[0]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + label->label_ptr[1] = label_ptr[1]; + } +} + +/* + * Generate code for the slow path for a load at the end of block + */ +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + TCGReg data_reg; + tcg_insn_unit **label_ptr = &l->label_ptr[0]; + int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0); + + /* resolve label address */ + tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); + } + + if (TCG_TARGET_REG_BITS == 32) { + int ofs = 0; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); + ofs += 4; + + tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); + ofs += 4; + + if (TARGET_LONG_BITS == 64) { + tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); + ofs += 4; + } + + tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); + ofs += 4; + + tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs); + } else { + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The second argument is already loaded with addrlo. */ + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); + tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], + (uintptr_t)l->raddr); + } + + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + + data_reg = l->datalo_reg; + switch (opc & MO_SSIZE) { + case MO_SB: + tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw); + break; + case MO_SW: + tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); + break; +#if TCG_TARGET_REG_BITS == 64 + case MO_SL: + tcg_out_ext32s(s, data_reg, TCG_REG_EAX); + break; +#endif + case MO_UB: + case MO_UW: + /* Note that the helpers have zero-extended to tcg_target_long. */ + case MO_UL: + tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); + break; + case MO_Q: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); + } else if (data_reg == TCG_REG_EDX) { + /* xchg %edx, %eax */ + tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); + tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); + } else { + tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); + tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); + } + break; + default: + tcg_abort(); + } + + /* Jump to the code corresponding to next IR of qemu_st */ + tcg_out_jmp(s, l->raddr); + return true; +} + +/* + * Generate code for the slow path for a store at the end of block + */ +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + MemOp s_bits = opc & MO_SIZE; + tcg_insn_unit **label_ptr = &l->label_ptr[0]; + TCGReg retaddr; + + /* resolve label address */ + tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); + } + + if (TCG_TARGET_REG_BITS == 32) { + int ofs = 0; + + tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); + ofs += 4; + + tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); + ofs += 4; + + if (TARGET_LONG_BITS == 64) { + tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); + ofs += 4; + } + + tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); + ofs += 4; + + if (s_bits == MO_64) { + tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); + ofs += 4; + } + + tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); + ofs += 4; + + retaddr = TCG_REG_EAX; + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); + tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); + } else { + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + tcg_target_call_iarg_regs[2], l->datalo_reg); + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); + + if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { + retaddr = tcg_target_call_iarg_regs[4]; + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); + } else { + retaddr = TCG_REG_RAX; + tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); + tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, + TCG_TARGET_CALL_STACK_OFFSET); + } + } + + /* "Tail call" to the helper, with the return address back inline. */ + tcg_out_push(s, retaddr); + tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; +} +#elif TCG_TARGET_REG_BITS == 32 +# define x86_guest_base_seg 0 +# define x86_guest_base_index -1 +# define x86_guest_base_offset guest_base +#else +static int x86_guest_base_seg; +static int x86_guest_base_index = -1; +static int32_t x86_guest_base_offset; +# if defined(__x86_64__) && defined(__linux__) +# include +# include +int arch_prctl(int code, unsigned long addr); +static inline int setup_guest_base_seg(void) +{ + if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { + return P_GS; + } + return 0; +} +# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) +# include +static inline int setup_guest_base_seg(void) +{ + if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { + return P_GS; + } + return 0; +} +# else +static inline int setup_guest_base_seg(void) +{ + return 0; +} +# endif +#endif /* SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg base, int index, intptr_t ofs, + int seg, bool is64, MemOp memop) +{ + const MemOp real_bswap = memop & MO_BSWAP; + MemOp bswap = real_bswap; + int rexw = is64 * P_REXW; + int movop = OPC_MOVL_GvEv; + + if (have_movbe && real_bswap) { + bswap = 0; + movop = OPC_MOVBE_GyMy; + } + + switch (memop & MO_SSIZE) { + case MO_UB: + tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, + base, index, 0, ofs); + break; + case MO_SB: + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, + base, index, 0, ofs); + break; + case MO_UW: + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + base, index, 0, ofs); + if (real_bswap) { + tcg_out_rolw_8(s, datalo); + } + break; + case MO_SW: + if (real_bswap) { + if (have_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + base, index, 0, ofs); + tcg_out_rolw_8(s, datalo); + } + tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, + datalo, base, index, 0, ofs); + } + break; + case MO_UL: + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + if (bswap) { + tcg_out_bswap32(s, datalo); + } + break; +#if TCG_TARGET_REG_BITS == 64 + case MO_SL: + if (real_bswap) { + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + if (bswap) { + tcg_out_bswap32(s, datalo); + } + tcg_out_ext32s(s, datalo, datalo); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, + base, index, 0, ofs); + } + break; +#endif + case MO_Q: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, + base, index, 0, ofs); + if (bswap) { + tcg_out_bswap64(s, datalo); + } + } else { + if (real_bswap) { + int t = datalo; + datalo = datahi; + datahi = t; + } + if (base != datalo) { + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); + } else { + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + } + if (bswap) { + tcg_out_bswap32(s, datalo); + tcg_out_bswap32(s, datahi); + } + } + break; + default: + tcg_abort(); + } +} + +/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and + EAX. It will be useful once fixed registers globals are less + common. */ +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +{ + TCGReg datalo, datahi, addrlo; + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + int mem_index; + tcg_insn_unit *label_ptr[2]; +#endif + + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + mem_index = get_mmuidx(oi); + + tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_read)); + + /* TLB Hit. */ + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc); + + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#else + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, + is64, opc); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg base, int index, intptr_t ofs, + int seg, MemOp memop) +{ + /* ??? Ideally we wouldn't need a scratch register. For user-only, + we could perform the bswap twice to restore the original value + instead of moving to the scratch. But as it is, the L constraint + means that TCG_REG_L0 is definitely free here. */ + const TCGReg scratch = TCG_REG_L0; + const MemOp real_bswap = memop & MO_BSWAP; + MemOp bswap = real_bswap; + int movop = OPC_MOVL_EvGv; + + if (have_movbe && real_bswap) { + bswap = 0; + movop = OPC_MOVBE_MyGy; + } + + switch (memop & MO_SIZE) { + case MO_8: + /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. + Use the scratch register if necessary. */ + if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, + datalo, base, index, 0, ofs); + break; + case MO_16: + if (bswap) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_rolw_8(s, scratch); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, + base, index, 0, ofs); + break; + case MO_32: + if (bswap) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_bswap32(s, scratch); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + if (bswap) { + tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); + tcg_out_bswap64(s, scratch); + datalo = scratch; + } + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, + base, index, 0, ofs); + } else if (bswap) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); + tcg_out_bswap32(s, scratch); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs); + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + tcg_out_bswap32(s, scratch); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs + 4); + } else { + if (real_bswap) { + int t = datalo; + datalo = datahi; + datahi = t; + } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); + } + break; + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +{ + TCGReg datalo, datahi, addrlo; + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + int mem_index; + tcg_insn_unit *label_ptr[2]; +#endif + + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + mem_index = get_mmuidx(oi); + + tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_write)); + + /* TLB Hit. */ + tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#else + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, opc); +#endif +} + +static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + TCGArg a0, a1, a2; + int c, const_a2, vexop, rexw = 0; + +#if TCG_TARGET_REG_BITS == 64 +# define OP_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + rexw = P_REXW; /* FALLTHRU */ \ + case glue(glue(INDEX_op_, x), _i32) +#else +# define OP_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32) +#endif + + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + const_a2 = const_args[2]; + + switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_jmp(s, s->code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); + tcg_out_jmp(s, tb_ret_addr); + } + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* direct jump method */ + int gap; + /* jump displacement must be aligned for atomic patching; + * see if we need to add extra nops before jump + */ + gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4)); + if (gap != 1) { + tcg_out_nopn(s, gap - 1); + } + tcg_out8(s, OPC_JMP_long); /* jmp im */ + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out32(s, 0); + } else { + /* indirect jump method */ + tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, + (intptr_t)(s->tb_jmp_target_addr + a0)); + } + set_jmp_reset_offset(s, a0); + break; + case INDEX_op_goto_ptr: + /* jmp to the given host address (could be epilogue) */ + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); + break; + case INDEX_op_br: + tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); + break; + OP_32_64(ld8u): + /* Note that we can ignore REXW for the zero-extend to 64-bit. */ + tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); + break; + OP_32_64(ld8s): + tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); + break; + OP_32_64(ld16u): + /* Note that we can ignore REXW for the zero-extend to 64-bit. */ + tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); + break; + OP_32_64(ld16s): + tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); + break; +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_ld32u_i64: +#endif + case INDEX_op_ld_i32: + tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); + break; + + OP_32_64(st8): + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); + tcg_out8(s, a0); + } else { + tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); + } + break; + OP_32_64(st16): + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); + tcg_out16(s, a0); + } else { + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); + } + break; +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_st32_i64: +#endif + case INDEX_op_st_i32: + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); + tcg_out32(s, a0); + } else { + tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); + } + break; + + OP_32_64(add): + /* For 3-operand addition, use LEA. */ + if (a0 != a1) { + TCGArg c3 = 0; + if (const_a2) { + c3 = a2, a2 = -1; + } else if (a0 == a2) { + /* Watch out for dest = src + dest, since we've removed + the matching constraint on the add. */ + tgen_arithr(s, ARITH_ADD + rexw, a0, a1); + break; + } + + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); + break; + } + c = ARITH_ADD; + goto gen_arith; + OP_32_64(sub): + c = ARITH_SUB; + goto gen_arith; + OP_32_64(and): + c = ARITH_AND; + goto gen_arith; + OP_32_64(or): + c = ARITH_OR; + goto gen_arith; + OP_32_64(xor): + c = ARITH_XOR; + goto gen_arith; + gen_arith: + if (const_a2) { + tgen_arithi(s, c + rexw, a0, a2, 0); + } else { + tgen_arithr(s, c + rexw, a0, a2); + } + break; + + OP_32_64(andc): + if (const_a2) { + tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); + tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); + } else { + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); + } + break; + + OP_32_64(mul): + if (const_a2) { + int32_t val; + val = a2; + if (val == (int8_t)val) { + tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); + tcg_out8(s, val); + } else { + tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); + tcg_out32(s, val); + } + } else { + tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); + } + break; + + OP_32_64(div2): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); + break; + OP_32_64(divu2): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); + break; + + OP_32_64(shl): + /* For small constant 3-operand shift, use LEA. */ + if (const_a2 && a0 != a1 && (a2 - 1) < 3) { + if (a2 - 1 == 0) { + /* shl $1,a1,a0 -> lea (a1,a1),a0 */ + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); + } else { + /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); + } + break; + } + c = SHIFT_SHL; + vexop = OPC_SHLX; + goto gen_shift_maybe_vex; + OP_32_64(shr): + c = SHIFT_SHR; + vexop = OPC_SHRX; + goto gen_shift_maybe_vex; + OP_32_64(sar): + c = SHIFT_SAR; + vexop = OPC_SARX; + goto gen_shift_maybe_vex; + OP_32_64(rotl): + c = SHIFT_ROL; + goto gen_shift; + OP_32_64(rotr): + c = SHIFT_ROR; + goto gen_shift; + gen_shift_maybe_vex: + if (have_bmi2) { + if (!const_a2) { + tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); + break; + } + tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); + } + /* FALLTHRU */ + gen_shift: + if (const_a2) { + tcg_out_shifti(s, c + rexw, a0, a2); + } else { + tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); + } + break; + + OP_32_64(ctz): + tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); + break; + OP_32_64(clz): + tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); + break; + OP_32_64(ctpop): + tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); + break; + + case INDEX_op_brcond_i32: + tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); + break; + case INDEX_op_setcond_i32: + tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); + break; + case INDEX_op_movcond_i32: + tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); + break; + + OP_32_64(bswap16): + tcg_out_rolw_8(s, a0); + break; + OP_32_64(bswap32): + tcg_out_bswap32(s, a0); + break; + + OP_32_64(neg): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); + break; + OP_32_64(not): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); + break; + + OP_32_64(ext8s): + tcg_out_ext8s(s, a0, a1, rexw); + break; + OP_32_64(ext16s): + tcg_out_ext16s(s, a0, a1, rexw); + break; + OP_32_64(ext8u): + tcg_out_ext8u(s, a0, a1); + break; + OP_32_64(ext16u): + tcg_out_ext16u(s, a0, a1); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, 0); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, 1); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, 0); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, 1); + break; + + OP_32_64(mulu2): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); + break; + OP_32_64(muls2): + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); + break; + OP_32_64(add2): + if (const_args[4]) { + tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); + } else { + tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); + } + if (const_args[5]) { + tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); + } else { + tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); + } + break; + OP_32_64(sub2): + if (const_args[4]) { + tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); + } else { + tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); + } + if (const_args[5]) { + tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); + } else { + tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); + } + break; + +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args, const_args, 0); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args, const_args); + break; +#else /* TCG_TARGET_REG_BITS == 64 */ + case INDEX_op_ld32s_i64: + tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); + break; + case INDEX_op_ld_i64: + tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_st_i64: + if (const_args[0]) { + tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); + tcg_out32(s, a0); + } else { + tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); + } + break; + + case INDEX_op_brcond_i64: + tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); + break; + case INDEX_op_setcond_i64: + tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); + break; + case INDEX_op_movcond_i64: + tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); + break; + + case INDEX_op_bswap64_i64: + tcg_out_bswap64(s, a0); + break; + case INDEX_op_extu_i32_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_extrl_i64_i32: + tcg_out_ext32u(s, a0, a1); + break; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + tcg_out_ext32s(s, a0, a1); + break; + case INDEX_op_extrh_i64_i32: + tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); + break; +#endif + + OP_32_64(deposit): + if (args[3] == 0 && args[4] == 8) { + /* load bits 0..7 */ + tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); + } else if (args[3] == 8 && args[4] == 8) { + /* load bits 8..15 */ + tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); + } else if (args[3] == 0 && args[4] == 16) { + /* load bits 0..15 */ + tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); + } else { + tcg_abort(); + } + break; + + case INDEX_op_extract_i64: + if (a2 + args[3] == 32) { + /* This is a 32-bit zero-extending right shift. */ + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tcg_out_shifti(s, SHIFT_SHR, a0, a2); + break; + } + /* FALLTHRU */ + case INDEX_op_extract_i32: + /* On the off-chance that we can use the high-byte registers. + Otherwise we emit the same ext16 + shift pattern that we + would have gotten from the normal tcg-op.c expansion. */ + tcg_debug_assert(a2 == 8 && args[3] == 8); + if (a1 < 4 && a0 < 8) { + tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); + } else { + tcg_out_ext16u(s, a0, a1); + tcg_out_shifti(s, SHIFT_SHR, a0, 8); + } + break; + + case INDEX_op_sextract_i32: + /* We don't implement sextract_i64, as we cannot sign-extend to + 64-bits without using the REX prefix that explicitly excludes + access to the high-byte registers. */ + tcg_debug_assert(a2 == 8 && args[3] == 8); + if (a1 < 4 && a0 < 8) { + tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); + } else { + tcg_out_ext16s(s, a0, a1, 0); + tcg_out_shifti(s, SHIFT_SAR, a0, 8); + } + break; + + OP_32_64(extract2): + /* Note that SHRD outputs to the r/m operand. */ + tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); + tcg_out8(s, args[3]); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } + +#undef OP_32_64 +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + static int const add_insn[4] = { + OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ + }; + static int const ssadd_insn[4] = { + OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 + }; + static int const usadd_insn[4] = { + OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 + }; + static int const sub_insn[4] = { + OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ + }; + static int const sssub_insn[4] = { + OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 + }; + static int const ussub_insn[4] = { + OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 + }; + static int const mul_insn[4] = { + OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2 + }; + static int const shift_imm_insn[4] = { + OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib + }; + static int const cmpeq_insn[4] = { + OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ + }; + static int const cmpgt_insn[4] = { + OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ + }; + static int const punpckl_insn[4] = { + OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ + }; + static int const punpckh_insn[4] = { + OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ + }; + static int const packss_insn[4] = { + OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 + }; + static int const packus_insn[4] = { + OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 + }; + static int const smin_insn[4] = { + OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2 + }; + static int const smax_insn[4] = { + OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2 + }; + static int const umin_insn[4] = { + OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2 + }; + static int const umax_insn[4] = { + OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 + }; + static int const shlv_insn[4] = { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ + }; + static int const shrv_insn[4] = { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ + }; + static int const sarv_insn[4] = { + /* TODO: AVX512 adds support for MO_16, MO_64. */ + OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 + }; + static int const shls_insn[4] = { + OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ + }; + static int const shrs_insn[4] = { + OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ + }; + static int const sars_insn[4] = { + OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 + }; + static int const abs_insn[4] = { + /* TODO: AVX512 adds support for MO_64. */ + OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2 + }; + + TCGType type = vecl + TCG_TYPE_V64; + int insn, sub; + TCGArg a0, a1, a2; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + + switch (opc) { + case INDEX_op_add_vec: + insn = add_insn[vece]; + goto gen_simd; + case INDEX_op_ssadd_vec: + insn = ssadd_insn[vece]; + goto gen_simd; + case INDEX_op_usadd_vec: + insn = usadd_insn[vece]; + goto gen_simd; + case INDEX_op_sub_vec: + insn = sub_insn[vece]; + goto gen_simd; + case INDEX_op_sssub_vec: + insn = sssub_insn[vece]; + goto gen_simd; + case INDEX_op_ussub_vec: + insn = ussub_insn[vece]; + goto gen_simd; + case INDEX_op_mul_vec: + insn = mul_insn[vece]; + goto gen_simd; + case INDEX_op_and_vec: + insn = OPC_PAND; + goto gen_simd; + case INDEX_op_or_vec: + insn = OPC_POR; + goto gen_simd; + case INDEX_op_xor_vec: + insn = OPC_PXOR; + goto gen_simd; + case INDEX_op_smin_vec: + insn = smin_insn[vece]; + goto gen_simd; + case INDEX_op_umin_vec: + insn = umin_insn[vece]; + goto gen_simd; + case INDEX_op_smax_vec: + insn = smax_insn[vece]; + goto gen_simd; + case INDEX_op_umax_vec: + insn = umax_insn[vece]; + goto gen_simd; + case INDEX_op_shlv_vec: + insn = shlv_insn[vece]; + goto gen_simd; + case INDEX_op_shrv_vec: + insn = shrv_insn[vece]; + goto gen_simd; + case INDEX_op_sarv_vec: + insn = sarv_insn[vece]; + goto gen_simd; + case INDEX_op_shls_vec: + insn = shls_insn[vece]; + goto gen_simd; + case INDEX_op_shrs_vec: + insn = shrs_insn[vece]; + goto gen_simd; + case INDEX_op_sars_vec: + insn = sars_insn[vece]; + goto gen_simd; + case INDEX_op_x86_punpckl_vec: + insn = punpckl_insn[vece]; + goto gen_simd; + case INDEX_op_x86_punpckh_vec: + insn = punpckh_insn[vece]; + goto gen_simd; + case INDEX_op_x86_packss_vec: + insn = packss_insn[vece]; + goto gen_simd; + case INDEX_op_x86_packus_vec: + insn = packus_insn[vece]; + goto gen_simd; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: + /* First merge the two 32-bit inputs to a single 64-bit element. */ + tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); + /* Then replicate the 64-bit elements across the rest of the vector. */ + if (type != TCG_TYPE_V64) { + tcg_out_dup_vec(s, type, MO_64, a0, a0); + } + break; +#endif + case INDEX_op_abs_vec: + insn = abs_insn[vece]; + a2 = a1; + a1 = 0; + goto gen_simd; + gen_simd: + tcg_debug_assert(insn != OPC_UD2); + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + break; + + case INDEX_op_cmp_vec: + sub = args[3]; + if (sub == TCG_COND_EQ) { + insn = cmpeq_insn[vece]; + } else if (sub == TCG_COND_GT) { + insn = cmpgt_insn[vece]; + } else { + g_assert_not_reached(); + } + goto gen_simd; + + case INDEX_op_andc_vec: + insn = OPC_PANDN; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a2, a1); + break; + + case INDEX_op_shli_vec: + sub = 6; + goto gen_shift; + case INDEX_op_shri_vec: + sub = 2; + goto gen_shift; + case INDEX_op_sari_vec: + tcg_debug_assert(vece != MO_64); + sub = 4; + gen_shift: + tcg_debug_assert(vece != MO_8); + insn = shift_imm_insn[vece]; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, sub, a0, a1); + tcg_out8(s, a2); + break; + + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; + + case INDEX_op_x86_shufps_vec: + insn = OPC_SHUFPS; + sub = args[3]; + goto gen_simd_imm8; + case INDEX_op_x86_blend_vec: + if (vece == MO_16) { + insn = OPC_PBLENDW; + } else if (vece == MO_32) { + insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); + } else { + g_assert_not_reached(); + } + sub = args[3]; + goto gen_simd_imm8; + case INDEX_op_x86_vperm2i128_vec: + insn = OPC_VPERM2I128; + sub = args[3]; + goto gen_simd_imm8; + gen_simd_imm8: + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + tcg_out8(s, sub); + break; + + case INDEX_op_x86_vpblendvb_vec: + insn = OPC_VPBLENDVB; + if (type == TCG_TYPE_V256) { + insn |= P_VEXL; + } + tcg_out_vex_modrm(s, insn, a0, a1, a2); + tcg_out8(s, args[3] << 4); + break; + + case INDEX_op_x86_psrldq_vec: + tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); + tcg_out8(s, a2); + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } }; + static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } }; + static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } }; + static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } }; + static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; + static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; + static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; + static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; + static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; + static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; + static const TCGTargetOpDef r_r_L_L + = { .args_ct_str = { "r", "r", "L", "L" } }; + static const TCGTargetOpDef L_L_L_L + = { .args_ct_str = { "L", "L", "L", "L" } }; + static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; + static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; + static const TCGTargetOpDef x_x_x_x + = { .args_ct_str = { "x", "x", "x", "x" } }; + static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + return &qi_r; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + return &ri_r; + case INDEX_op_st_i64: + return &re_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_re; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_re; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + { + static const TCGTargetOpDef and + = { .args_ct_str = { "r", "0", "reZ" } }; + return ∧ + } + break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + { + static const TCGTargetOpDef andc + = { .args_ct_str = { "r", "r", "rI" } }; + return &andc; + } + break; + + case INDEX_op_shl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i32: + case INDEX_op_shr_i64: + case INDEX_op_sar_i32: + case INDEX_op_sar_i64: + return have_bmi2 ? &r_r_ri : &r_0_ci; + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_0_ci; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_re; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_extrh_i64_i32: + return &r_0; + + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + return &r_q; + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: + return &r_r; + case INDEX_op_extract2_i32: + case INDEX_op_extract2_i64: + return &r_0_r; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + = { .args_ct_str = { "Q", "0", "Q" } }; + return &dep; + } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + static const TCGTargetOpDef setc + = { .args_ct_str = { "q", "r", "re" } }; + return &setc; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "re", "r", "0" } }; + return &movc; + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + = { .args_ct_str = { "a", "d", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: + { + static const TCGTargetOpDef mul2 + = { .args_ct_str = { "a", "d", "a", "r" } }; + return &mul2; + } + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + { + static const TCGTargetOpDef arith2 + = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } }; + return &arith2; + } + case INDEX_op_ctz_i32: + case INDEX_op_ctz_i64: + { + static const TCGTargetOpDef ctz[2] = { + { .args_ct_str = { "&r", "r", "r" } }, + { .args_ct_str = { "&r", "r", "rW" } }, + }; + return &ctz[have_bmi1]; + } + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + { + static const TCGTargetOpDef clz[2] = { + { .args_ct_str = { "&r", "r", "r" } }, + { .args_ct_str = { "&r", "r", "rW" } }, + }; + return &clz[have_lzcnt]; + } + + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? &r_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L + : &r_r_L_L); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? &L_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L + : &L_L_L_L); + + case INDEX_op_brcond2_i32: + { + static const TCGTargetOpDef b2 + = { .args_ct_str = { "r", "r", "ri", "ri" } }; + return &b2; + } + case INDEX_op_setcond2_i32: + { + static const TCGTargetOpDef s2 + = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; + return &s2; + } + + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + case INDEX_op_dupm_vec: + return &x_r; + + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_mul_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + case INDEX_op_smin_vec: + case INDEX_op_umin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umax_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + case INDEX_op_rotls_vec: + case INDEX_op_cmp_vec: + case INDEX_op_x86_shufps_vec: + case INDEX_op_x86_blend_vec: + case INDEX_op_x86_packss_vec: + case INDEX_op_x86_packus_vec: + case INDEX_op_x86_vperm2i128_vec: + case INDEX_op_x86_punpckl_vec: + case INDEX_op_x86_punpckh_vec: +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: +#endif + return &x_x_x; + case INDEX_op_abs_vec: + case INDEX_op_dup_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_x86_psrldq_vec: + return &x_x; + case INDEX_op_x86_vpblendvb_vec: + return &x_x_x_x; + + default: + break; + } + return NULL; +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + return 1; + case INDEX_op_rotli_vec: + case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: + return -1; + + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + /* We must expand the operation for MO_8. */ + return vece == MO_8 ? -1 : 1; + + case INDEX_op_sari_vec: + /* We must expand the operation for MO_8. */ + if (vece == MO_8) { + return -1; + } + /* We can emulate this for MO_64, but it does not pay off + unless we're producing at least 4 values. */ + if (vece == MO_64) { + return type >= TCG_TYPE_V256 ? -1 : 0; + } + return 1; + + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + return vece >= MO_16; + case INDEX_op_sars_vec: + return vece >= MO_16 && vece <= MO_32; + case INDEX_op_rotls_vec: + return vece >= MO_16 ? -1 : 0; + + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + return have_avx2 && vece >= MO_32; + case INDEX_op_sarv_vec: + return have_avx2 && vece == MO_32; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_avx2 && vece >= MO_32 ? -1 : 0; + + case INDEX_op_mul_vec: + if (vece == MO_8) { + /* We can expand the operation for MO_8. */ + return -1; + } + if (vece == MO_64) { + return 0; + } + return 1; + + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return vece <= MO_16; + case INDEX_op_smin_vec: + case INDEX_op_smax_vec: + case INDEX_op_umin_vec: + case INDEX_op_umax_vec: + case INDEX_op_abs_vec: + return vece <= MO_32; + + default: + return 0; + } +} + +static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t1, t2; + + tcg_debug_assert(vece == MO_8); + + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + + /* + * Unpack to W, shift, and repack. Tricky bits: + * (1) Use punpck*bw x,x to produce DDCCBBAA, + * i.e. duplicate in other half of the 16-bit lane. + * (2) For right-shift, add 8 so that the high half of the lane + * becomes zero. For left-shift, and left-rotate, we must + * shift up and down again. + * (3) Step 2 leaves high half zero such that PACKUSWB + * (pack with unsigned saturation) does not modify + * the quantity. + */ + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, + tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + + if (opc != INDEX_op_rotli_vec) { + imm += 8; + } + if (opc == INDEX_op_shri_vec) { + tcg_gen_shri_vec(MO_16, t1, t1, imm); + tcg_gen_shri_vec(MO_16, t2, t2, imm); + } else { + tcg_gen_shli_vec(MO_16, t1, t1, imm); + tcg_gen_shli_vec(MO_16, t2, t2, imm); + tcg_gen_shri_vec(MO_16, t1, t1, 8); + tcg_gen_shri_vec(MO_16, t2, t2, 8); + } + + vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + +static void expand_vec_sari(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t1, t2; + + switch (vece) { + case MO_8: + /* Unpack to W, shift, and repack, as in expand_vec_shi. */ + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, + tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); + tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); + tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); + vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + + case MO_64: + if (imm <= 32) { + /* + * We can emulate a small sign extend by performing an arithmetic + * 32-bit shift and overwriting the high half of a 64-bit logical + * shift. Note that the ISA says shift of 32 is valid, but TCG + * does not, so we have to bound the smaller shift -- we get the + * same result in the high half either way. + */ + t1 = tcg_temp_new_vec(type); + tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); + tcg_gen_shri_vec(MO_64, v0, v1, imm); + vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, + tcgv_vec_arg(v0), tcgv_vec_arg(v0), + tcgv_vec_arg(t1), 0xaa); + tcg_temp_free_vec(t1); + } else { + /* Otherwise we will need to use a compare vs 0 to produce + * the sign-extend, shift and merge. + */ + t1 = tcg_const_zeros_vec(type); + tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1); + tcg_gen_shri_vec(MO_64, v0, v1, imm); + tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); + tcg_gen_or_vec(MO_64, v0, v0, t1); + tcg_temp_free_vec(t1); + } + break; + + default: + g_assert_not_reached(); + } +} + +static void expand_vec_rotli(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGArg imm) +{ + TCGv_vec t; + + if (vece == MO_8) { + expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); + return; + } + + t = tcg_temp_new_vec(type); + tcg_gen_shli_vec(vece, t, v1, imm); + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + +static void expand_vec_rotls(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) +{ + TCGv_i32 rsh; + TCGv_vec t; + + tcg_debug_assert(vece != MO_8); + + t = tcg_temp_new_vec(type); + rsh = tcg_temp_new_i32(); + + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); + tcg_gen_shls_vec(vece, t, v1, lsh); + tcg_gen_shrs_vec(vece, v0, v1, rsh); + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); + tcg_temp_free_i32(rsh); +} + +static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec sh, bool right) +{ + TCGv_vec t = tcg_temp_new_vec(type); + + tcg_gen_dupi_vec(vece, t, 8 << vece); + tcg_gen_sub_vec(vece, t, t, sh); + if (right) { + tcg_gen_shlv_vec(vece, t, v1, t); + tcg_gen_shrv_vec(vece, v0, v1, sh); + } else { + tcg_gen_shrv_vec(vece, t, v1, t); + tcg_gen_shlv_vec(vece, v0, v1, sh); + } + tcg_gen_or_vec(vece, v0, v0, t); + tcg_temp_free_vec(t); +} + +static void expand_vec_mul(TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) +{ + TCGv_vec t1, t2, t3, t4; + + tcg_debug_assert(vece == MO_8); + + /* + * Unpack v1 bytes to words, 0 | x. + * Unpack v2 bytes to words, y | 0. + * This leaves the 8-bit result, x * y, with 8 bits of right padding. + * Shift logical right by 8 bits to clear the high 8 bytes before + * using an unsigned saturated pack. + * + * The difference between the V64, V128 and V256 cases is merely how + * we distribute the expansion between temporaries. + */ + switch (type) { + case TCG_TYPE_V64: + t1 = tcg_temp_new_vec(TCG_TYPE_V128); + t2 = tcg_temp_new_vec(TCG_TYPE_V128); + tcg_gen_dup16i_vec(t2, 0); + vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, + tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); + tcg_gen_mul_vec(MO_16, t1, t1, t2); + tcg_gen_shri_vec(MO_16, t1, t1, 8); + vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + break; + + case TCG_TYPE_V128: + case TCG_TYPE_V256: + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + t3 = tcg_temp_new_vec(type); + t4 = tcg_temp_new_vec(type); + tcg_gen_dup16i_vec(t4, 0); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, + tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, + tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, + tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, + tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); + tcg_gen_mul_vec(MO_16, t1, t1, t2); + tcg_gen_mul_vec(MO_16, t3, t3, t4); + tcg_gen_shri_vec(MO_16, t1, t1, 8); + tcg_gen_shri_vec(MO_16, t3, t3, 8); + vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, + tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + + default: + g_assert_not_reached(); + } +} + +static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + enum { + NEED_INV = 1, + NEED_SWAP = 2, + NEED_BIAS = 4, + NEED_UMIN = 8, + NEED_UMAX = 16, + }; + TCGv_vec t1, t2; + uint8_t fixup; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + fixup = 0; + break; + case TCG_COND_NE: + case TCG_COND_LE: + fixup = NEED_INV; + break; + case TCG_COND_LT: + fixup = NEED_SWAP; + break; + case TCG_COND_GE: + fixup = NEED_SWAP | NEED_INV; + break; + case TCG_COND_LEU: + if (vece <= MO_32) { + fixup = NEED_UMIN; + } else { + fixup = NEED_BIAS | NEED_INV; + } + break; + case TCG_COND_GTU: + if (vece <= MO_32) { + fixup = NEED_UMIN | NEED_INV; + } else { + fixup = NEED_BIAS; + } + break; + case TCG_COND_GEU: + if (vece <= MO_32) { + fixup = NEED_UMAX; + } else { + fixup = NEED_BIAS | NEED_SWAP | NEED_INV; + } + break; + case TCG_COND_LTU: + if (vece <= MO_32) { + fixup = NEED_UMAX | NEED_INV; + } else { + fixup = NEED_BIAS | NEED_SWAP; + } + break; + default: + g_assert_not_reached(); + } + + if (fixup & NEED_INV) { + cond = tcg_invert_cond(cond); + } + if (fixup & NEED_SWAP) { + t1 = v1, v1 = v2, v2 = t1; + cond = tcg_swap_cond(cond); + } + + t1 = t2 = NULL; + if (fixup & (NEED_UMIN | NEED_UMAX)) { + t1 = tcg_temp_new_vec(type); + if (fixup & NEED_UMIN) { + tcg_gen_umin_vec(vece, t1, v1, v2); + } else { + tcg_gen_umax_vec(vece, t1, v1, v2); + } + v2 = t1; + cond = TCG_COND_EQ; + } else if (fixup & NEED_BIAS) { + t1 = tcg_temp_new_vec(type); + t2 = tcg_temp_new_vec(type); + tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); + tcg_gen_sub_vec(vece, t1, v1, t2); + tcg_gen_sub_vec(vece, t2, v2, t2); + v1 = t1; + v2 = t2; + cond = tcg_signed_cond(cond); + } + + tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT); + /* Expand directly; do not recurse. */ + vec_gen_4(INDEX_op_cmp_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + if (t1) { + tcg_temp_free_vec(t1); + if (t2) { + tcg_temp_free_vec(t2); + } + } + return fixup & NEED_INV; +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { + tcg_gen_not_vec(vece, v0, v0); + } +} + +static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec c1, TCGv_vec c2, + TCGv_vec v3, TCGv_vec v4, TCGCond cond) +{ + TCGv_vec t = tcg_temp_new_vec(type); + + if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { + /* Invert the sense of the compare by swapping arguments. */ + TCGv_vec x; + x = v3, v3 = v4, v4 = x; + } + vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(v4), + tcgv_vec_arg(v3), tcgv_vec_arg(t)); + tcg_temp_free_vec(t); +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + va_list va; + TCGArg a2; + TCGv_vec v0, v1, v2, v3, v4; + + va_start(va, a0); + v0 = temp_tcgv_vec(arg_temp(a0)); + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 = va_arg(va, TCGArg); + + switch (opc) { + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, opc, v0, v1, a2); + break; + + case INDEX_op_sari_vec: + expand_vec_sari(type, vece, v0, v1, a2); + break; + + case INDEX_op_rotli_vec: + expand_vec_rotli(type, vece, v0, v1, a2); + break; + + case INDEX_op_rotls_vec: + expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); + break; + + case INDEX_op_rotlv_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, false); + break; + case INDEX_op_rotrv_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_rotv(type, vece, v0, v1, v2, true); + break; + + case INDEX_op_mul_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; + + case INDEX_op_cmp_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + + case INDEX_op_cmpsel_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); + break; + + default: + break; + } + + va_end(va); +} + +static const int tcg_target_callee_save_regs[] = { +#if TCG_TARGET_REG_BITS == 64 + TCG_REG_RBP, + TCG_REG_RBX, +#if defined(_WIN64) + TCG_REG_RDI, + TCG_REG_RSI, +#endif + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, /* Currently used for the global env. */ + TCG_REG_R15, +#else + TCG_REG_EBP, /* Currently used for the global env. */ + TCG_REG_EBX, + TCG_REG_ESI, + TCG_REG_EDI, +#endif +}; + +/* Compute frame size via macros, to share between tcg_target_qemu_prologue + and tcg_register_jit. */ + +#define PUSH_SIZE \ + ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ + * (TCG_TARGET_REG_BITS / 8)) + +#define FRAME_SIZE \ + ((PUSH_SIZE \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_NLONGS * sizeof(long) \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & ~(TCG_TARGET_STACK_ALIGN - 1)) + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i, stack_addend; + + /* TB prologue */ + + /* Reserve some stack space, also for TCG temps. */ + stack_addend = FRAME_SIZE - PUSH_SIZE; + tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, + CPU_TEMP_BUF_NLONGS * sizeof(long)); + + /* Save all callee saved registers. */ + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_push(s, tcg_target_callee_save_regs[i]); + } + +#if TCG_TARGET_REG_BITS == 32 + tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); + /* jmp *tb. */ + tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + + stack_addend); +#else +# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64 + if (guest_base) { + int seg = setup_guest_base_seg(); + if (seg != 0) { + x86_guest_base_seg = seg; + } else if (guest_base == (int32_t)guest_base) { + x86_guest_base_offset = guest_base; + } else { + /* Choose R12 because, as a base, it requires a SIB byte. */ + x86_guest_base_index = TCG_REG_R12; + tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + } + } +# endif + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); + /* jmp *tb. */ + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); +#endif + + /* + * Return path for goto_ptr. Set return value to 0, a-la exit_tb, + * and fall through to the rest of the epilogue. + */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + + tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); + + if (have_avx2) { + tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); + } + for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { + tcg_out_pop(s, tcg_target_callee_save_regs[i]); + } + tcg_out_opc(s, OPC_RET, 0, 0, 0); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x90, count); +} + +static void tcg_target_init(TCGContext *s) +{ +#ifdef CONFIG_CPUID_H + unsigned a, b, c, d, b7 = 0; + int max = __get_cpuid_max(0, 0); + + if (max >= 7) { + /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ + __cpuid_count(7, 0, a, b7, c, d); + have_bmi1 = (b7 & bit_BMI) != 0; + have_bmi2 = (b7 & bit_BMI2) != 0; + } + + if (max >= 1) { + __cpuid(1, a, b, c, d); +#ifndef have_cmov + /* For 32-bit, 99% certainty that we're running on hardware that + supports cmov, but we still need to check. In case cmov is not + available, we'll use a small forward branch. */ + have_cmov = (d & bit_CMOV) != 0; +#endif + + /* MOVBE is only available on Intel Atom and Haswell CPUs, so we + need to probe for it. */ + have_movbe = (c & bit_MOVBE) != 0; + have_popcnt = (c & bit_POPCNT) != 0; + + /* There are a number of things we must check before we can be + sure of not hitting invalid opcode. */ + if (c & bit_OSXSAVE) { + unsigned xcrl, xcrh; + /* The xgetbv instruction is not available to older versions of + * the assembler, so we encode the instruction manually. + */ + asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); + if ((xcrl & 6) == 6) { + have_avx1 = (c & bit_AVX) != 0; + have_avx2 = (b7 & bit_AVX2) != 0; + } + } + } + + max = __get_cpuid_max(0x8000000, 0); + if (max >= 1) { + __cpuid(0x80000001, a, b, c, d); + /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs. */ + have_lzcnt = (c & bit_LZCNT) != 0; + } +#endif /* CONFIG_CPUID_H */ + + tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; + if (TCG_TARGET_REG_BITS == 64) { + tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; + } + if (have_avx1) { + tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; + tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; + } + if (have_avx2) { + tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; + } + + tcg_target_call_clobber_regs = ALL_VECTOR_REGS; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); + if (TCG_TARGET_REG_BITS == 64) { +#if !defined(_WIN64) + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); +#endif + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); + } + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[14]; +} DebugFrame; + +/* We're expecting a 2 byte uleb128 encoded value. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); + +#if !defined(__ELF__) + /* Host machine without ELF. */ +#elif TCG_TARGET_REG_BITS == 64 +#define ELF_HOST_MACHINE EM_X86_64 +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x78, /* sleb128 -8 */ + .h.cie.return_column = 16, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, 7, /* DW_CFA_def_cfa %rsp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x90, 1, /* DW_CFA_offset, %rip, -8 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ + 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ + 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ + 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ + 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ + 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ + } +}; +#else +#define ELF_HOST_MACHINE EM_386 +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 0x7c, /* sleb128 -4 */ + .h.cie.return_column = 8, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, 4, /* DW_CFA_def_cfa %esp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x88, 1, /* DW_CFA_offset, %eip, -4 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ + 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ + 0x86, 4, /* DW_CFA_offset, %esi, -16 */ + 0x87, 5, /* DW_CFA_offset, %edi, -20 */ + } +}; +#endif + +#if defined(ELF_HOST_MACHINE) +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} +#endif diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c deleted file mode 100644 index ae0228238b..0000000000 --- a/tcg/i386/tcg-target.inc.c +++ /dev/null @@ -1,4016 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "../tcg-pool.inc.c" - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { -#if TCG_TARGET_REG_BITS == 64 - "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", -#else - "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", -#endif - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", - "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", -#if TCG_TARGET_REG_BITS == 64 - "%xmm8", "%xmm9", "%xmm10", "%xmm11", - "%xmm12", "%xmm13", "%xmm14", "%xmm15", -#endif -}; -#endif - -static const int tcg_target_reg_alloc_order[] = { -#if TCG_TARGET_REG_BITS == 64 - TCG_REG_RBP, - TCG_REG_RBX, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R9, - TCG_REG_R8, - TCG_REG_RCX, - TCG_REG_RDX, - TCG_REG_RSI, - TCG_REG_RDI, - TCG_REG_RAX, -#else - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, - TCG_REG_EBP, - TCG_REG_ECX, - TCG_REG_EDX, - TCG_REG_EAX, -#endif - TCG_REG_XMM0, - TCG_REG_XMM1, - TCG_REG_XMM2, - TCG_REG_XMM3, - TCG_REG_XMM4, - TCG_REG_XMM5, -#ifndef _WIN64 - /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save - any of them. Therefore only allow xmm0-xmm5 to be allocated. */ - TCG_REG_XMM6, - TCG_REG_XMM7, -#if TCG_TARGET_REG_BITS == 64 - TCG_REG_XMM8, - TCG_REG_XMM9, - TCG_REG_XMM10, - TCG_REG_XMM11, - TCG_REG_XMM12, - TCG_REG_XMM13, - TCG_REG_XMM14, - TCG_REG_XMM15, -#endif -#endif -}; - -static const int tcg_target_call_iarg_regs[] = { -#if TCG_TARGET_REG_BITS == 64 -#if defined(_WIN64) - TCG_REG_RCX, - TCG_REG_RDX, -#else - TCG_REG_RDI, - TCG_REG_RSI, - TCG_REG_RDX, - TCG_REG_RCX, -#endif - TCG_REG_R8, - TCG_REG_R9, -#else - /* 32 bit mode uses stack based calling convention (GCC default). */ -#endif -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_EDX -#endif -}; - -/* Constants we accept. */ -#define TCG_CT_CONST_S32 0x100 -#define TCG_CT_CONST_U32 0x200 -#define TCG_CT_CONST_I32 0x400 -#define TCG_CT_CONST_WSZ 0x800 - -/* Registers used with L constraint, which are the first argument - registers on x86_64, and two random call clobbered registers on - i386. */ -#if TCG_TARGET_REG_BITS == 64 -# define TCG_REG_L0 tcg_target_call_iarg_regs[0] -# define TCG_REG_L1 tcg_target_call_iarg_regs[1] -#else -# define TCG_REG_L0 TCG_REG_EAX -# define TCG_REG_L1 TCG_REG_EDX -#endif - -/* The host compiler should supply to enable runtime features - detection, as we're not going to go so far as our own inline assembly. - If not available, default values will be assumed. */ -#if defined(CONFIG_CPUID_H) -#include "qemu/cpuid.h" -#endif - -/* For 64-bit, we always know that CMOV is available. */ -#if TCG_TARGET_REG_BITS == 64 -# define have_cmov 1 -#elif defined(CONFIG_CPUID_H) -static bool have_cmov; -#else -# define have_cmov 0 -#endif - -/* We need these symbols in tcg-target.h, and we can't properly conditionalize - it there. Therefore we always define the variable. */ -bool have_bmi1; -bool have_popcnt; -bool have_avx1; -bool have_avx2; - -#ifdef CONFIG_CPUID_H -static bool have_movbe; -static bool have_bmi2; -static bool have_lzcnt; -#else -# define have_movbe 0 -# define have_bmi2 0 -# define have_lzcnt 0 -#endif - -static tcg_insn_unit *tb_ret_addr; - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - value += addend; - switch(type) { - case R_386_PC32: - value -= (uintptr_t)code_ptr; - if (value != (int32_t)value) { - return false; - } - /* FALLTHRU */ - case R_386_32: - tcg_patch32(code_ptr, value); - break; - case R_386_PC8: - value -= (uintptr_t)code_ptr; - if (value != (int8_t)value) { - return false; - } - tcg_patch8(code_ptr, value); - break; - default: - tcg_abort(); - } - return true; -} - -#if TCG_TARGET_REG_BITS == 64 -#define ALL_GENERAL_REGS 0x0000ffffu -#define ALL_VECTOR_REGS 0xffff0000u -#else -#define ALL_GENERAL_REGS 0x000000ffu -#define ALL_VECTOR_REGS 0x00ff0000u -#endif - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'a': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); - break; - case 'b': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); - break; - case 'c': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); - break; - case 'd': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); - break; - case 'S': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); - break; - case 'D': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); - break; - case 'q': - /* A register that can be used as a byte operand. */ - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; - break; - case 'Q': - /* A register with an addressable second byte (e.g. %ah). */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xf; - break; - case 'r': - /* A general register. */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_GENERAL_REGS; - break; - case 'W': - /* With TZCNT/LZCNT, we can have operand-size as an input. */ - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'x': - /* A vector register. */ - ct->ct |= TCG_CT_REG; - ct->u.regs |= ALL_VECTOR_REGS; - break; - - /* qemu_ld/st address constraint */ - case 'L': - ct->ct |= TCG_CT_REG; - ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); - break; - - case 'e': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32); - break; - case 'Z': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32); - break; - case 'I': - ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32); - break; - - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - if (ct & TCG_CT_CONST) { - return 1; - } - if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { - return 1; - } - if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { - return 1; - } - if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { - return 1; - } - return 0; -} - -# define LOWREGMASK(x) ((x) & 7) - -#define P_EXT 0x100 /* 0x0f opcode prefix */ -#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ -#define P_DATA16 0x400 /* 0x66 opcode prefix */ -#if TCG_TARGET_REG_BITS == 64 -# define P_REXW 0x1000 /* Set REX.W = 1 */ -# define P_REXB_R 0x2000 /* REG field as byte register */ -# define P_REXB_RM 0x4000 /* R/M field as byte register */ -# define P_GS 0x8000 /* gs segment override */ -#else -# define P_REXW 0 -# define P_REXB_R 0 -# define P_REXB_RM 0 -# define P_GS 0 -#endif -#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */ -#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ -#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ -#define P_VEXL 0x80000 /* Set VEX.L = 1 */ - -#define OPC_ARITH_EvIz (0x81) -#define OPC_ARITH_EvIb (0x83) -#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ -#define OPC_ANDN (0xf2 | P_EXT38) -#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) -#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) -#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) -#define OPC_BSF (0xbc | P_EXT) -#define OPC_BSR (0xbd | P_EXT) -#define OPC_BSWAP (0xc8 | P_EXT) -#define OPC_CALL_Jz (0xe8) -#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */ -#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3)) -#define OPC_DEC_r32 (0x48) -#define OPC_IMUL_GvEv (0xaf | P_EXT) -#define OPC_IMUL_GvEvIb (0x6b) -#define OPC_IMUL_GvEvIz (0x69) -#define OPC_INC_r32 (0x40) -#define OPC_JCC_long (0x80 | P_EXT) /* ... plus condition code */ -#define OPC_JCC_short (0x70) /* ... plus condition code */ -#define OPC_JMP_long (0xe9) -#define OPC_JMP_short (0xeb) -#define OPC_LEA (0x8d) -#define OPC_LZCNT (0xbd | P_EXT | P_SIMDF3) -#define OPC_MOVB_EvGv (0x88) /* stores, more or less */ -#define OPC_MOVL_EvGv (0x89) /* stores, more or less */ -#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */ -#define OPC_MOVB_EvIz (0xc6) -#define OPC_MOVL_EvIz (0xc7) -#define OPC_MOVL_Iv (0xb8) -#define OPC_MOVBE_GyMy (0xf0 | P_EXT38) -#define OPC_MOVBE_MyGy (0xf1 | P_EXT38) -#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) -#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) -#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) -#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) -#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) -#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) -#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3) -#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3) -#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16) -#define OPC_MOVSBL (0xbe | P_EXT) -#define OPC_MOVSWL (0xbf | P_EXT) -#define OPC_MOVSLQ (0x63 | P_REXW) -#define OPC_MOVZBL (0xb6 | P_EXT) -#define OPC_MOVZWL (0xb7 | P_EXT) -#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) -#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) -#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) -#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) -#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) -#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) -#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16) -#define OPC_PADDB (0xfc | P_EXT | P_DATA16) -#define OPC_PADDW (0xfd | P_EXT | P_DATA16) -#define OPC_PADDD (0xfe | P_EXT | P_DATA16) -#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) -#define OPC_PADDSB (0xec | P_EXT | P_DATA16) -#define OPC_PADDSW (0xed | P_EXT | P_DATA16) -#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) -#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) -#define OPC_PAND (0xdb | P_EXT | P_DATA16) -#define OPC_PANDN (0xdf | P_EXT | P_DATA16) -#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) -#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16) -#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16) -#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16) -#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16) -#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16) -#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) -#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) -#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) -#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) -#define OPC_PMAXSW (0xee | P_EXT | P_DATA16) -#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) -#define OPC_PMAXUB (0xde | P_EXT | P_DATA16) -#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16) -#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16) -#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16) -#define OPC_PMINSW (0xea | P_EXT | P_DATA16) -#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16) -#define OPC_PMINUB (0xda | P_EXT | P_DATA16) -#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16) -#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16) -#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16) -#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16) -#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16) -#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16) -#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16) -#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16) -#define OPC_POR (0xeb | P_EXT | P_DATA16) -#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16) -#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16) -#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2) -#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3) -#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ -#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) -#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) -#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) -#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) -#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) -#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) -#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) -#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) -#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) -#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) -#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) -#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) -#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) -#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) -#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) -#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) -#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) -#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) -#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) -#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16) -#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16) -#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16) -#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16) -#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16) -#define OPC_PXOR (0xef | P_EXT | P_DATA16) -#define OPC_POP_r32 (0x58) -#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) -#define OPC_PUSH_r32 (0x50) -#define OPC_PUSH_Iv (0x68) -#define OPC_PUSH_Ib (0x6a) -#define OPC_RET (0xc3) -#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ -#define OPC_SHIFT_1 (0xd1) -#define OPC_SHIFT_Ib (0xc1) -#define OPC_SHIFT_cl (0xd3) -#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3) -#define OPC_SHUFPS (0xc6 | P_EXT) -#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) -#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) -#define OPC_SHRD_Ib (0xac | P_EXT) -#define OPC_TESTL (0x85) -#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) -#define OPC_UD2 (0x0b | P_EXT) -#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) -#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) -#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) -#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) -#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) -#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) -#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) -#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) -#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) -#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) -#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) -#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) -#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) -#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) -#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) -#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) -#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) -#define OPC_VZEROUPPER (0x77 | P_EXT) -#define OPC_XCHG_ax_r32 (0x90) - -#define OPC_GRP3_Ev (0xf7) -#define OPC_GRP5 (0xff) -#define OPC_GRP14 (0x73 | P_EXT | P_DATA16) - -/* Group 1 opcode extensions for 0x80-0x83. - These are also used as modifiers for OPC_ARITH. */ -#define ARITH_ADD 0 -#define ARITH_OR 1 -#define ARITH_ADC 2 -#define ARITH_SBB 3 -#define ARITH_AND 4 -#define ARITH_SUB 5 -#define ARITH_XOR 6 -#define ARITH_CMP 7 - -/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */ -#define SHIFT_ROL 0 -#define SHIFT_ROR 1 -#define SHIFT_SHL 4 -#define SHIFT_SHR 5 -#define SHIFT_SAR 7 - -/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */ -#define EXT3_NOT 2 -#define EXT3_NEG 3 -#define EXT3_MUL 4 -#define EXT3_IMUL 5 -#define EXT3_DIV 6 -#define EXT3_IDIV 7 - -/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */ -#define EXT5_INC_Ev 0 -#define EXT5_DEC_Ev 1 -#define EXT5_CALLN_Ev 2 -#define EXT5_JMPN_Ev 4 - -/* Condition codes to be added to OPC_JCC_{long,short}. */ -#define JCC_JMP (-1) -#define JCC_JO 0x0 -#define JCC_JNO 0x1 -#define JCC_JB 0x2 -#define JCC_JAE 0x3 -#define JCC_JE 0x4 -#define JCC_JNE 0x5 -#define JCC_JBE 0x6 -#define JCC_JA 0x7 -#define JCC_JS 0x8 -#define JCC_JNS 0x9 -#define JCC_JP 0xa -#define JCC_JNP 0xb -#define JCC_JL 0xc -#define JCC_JGE 0xd -#define JCC_JLE 0xe -#define JCC_JG 0xf - -static const uint8_t tcg_cond_to_jcc[] = { - [TCG_COND_EQ] = JCC_JE, - [TCG_COND_NE] = JCC_JNE, - [TCG_COND_LT] = JCC_JL, - [TCG_COND_GE] = JCC_JGE, - [TCG_COND_LE] = JCC_JLE, - [TCG_COND_GT] = JCC_JG, - [TCG_COND_LTU] = JCC_JB, - [TCG_COND_GEU] = JCC_JAE, - [TCG_COND_LEU] = JCC_JBE, - [TCG_COND_GTU] = JCC_JA, -}; - -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) -{ - int rex; - - if (opc & P_GS) { - tcg_out8(s, 0x65); - } - if (opc & P_DATA16) { - /* We should never be asking for both 16 and 64-bit operation. */ - tcg_debug_assert((opc & P_REXW) == 0); - tcg_out8(s, 0x66); - } - if (opc & P_SIMDF3) { - tcg_out8(s, 0xf3); - } else if (opc & P_SIMDF2) { - tcg_out8(s, 0xf2); - } - - rex = 0; - rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */ - rex |= (r & 8) >> 1; /* REX.R */ - rex |= (x & 8) >> 2; /* REX.X */ - rex |= (rm & 8) >> 3; /* REX.B */ - - /* P_REXB_{R,RM} indicates that the given register is the low byte. - For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do, - as otherwise the encoding indicates %[abcd]h. Note that the values - that are ORed in merely indicate that the REX byte must be present; - those bits get discarded in output. */ - rex |= opc & (r >= 4 ? P_REXB_R : 0); - rex |= opc & (rm >= 4 ? P_REXB_RM : 0); - - if (rex) { - tcg_out8(s, (uint8_t)(rex | 0x40)); - } - - if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { - tcg_out8(s, 0x0f); - if (opc & P_EXT38) { - tcg_out8(s, 0x38); - } else if (opc & P_EXT3A) { - tcg_out8(s, 0x3a); - } - } - - tcg_out8(s, opc); -} -#else -static void tcg_out_opc(TCGContext *s, int opc) -{ - if (opc & P_DATA16) { - tcg_out8(s, 0x66); - } - if (opc & P_SIMDF3) { - tcg_out8(s, 0xf3); - } else if (opc & P_SIMDF2) { - tcg_out8(s, 0xf2); - } - if (opc & (P_EXT | P_EXT38 | P_EXT3A)) { - tcg_out8(s, 0x0f); - if (opc & P_EXT38) { - tcg_out8(s, 0x38); - } else if (opc & P_EXT3A) { - tcg_out8(s, 0x3a); - } - } - tcg_out8(s, opc); -} -/* Discard the register arguments to tcg_out_opc early, so as not to penalize - the 32-bit compilation paths. This method works with all versions of gcc, - whereas relying on optimization may not be able to exclude them. */ -#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) -#endif - -static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) -{ - tcg_out_opc(s, opc, r, rm, 0); - tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); -} - -static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, - int rm, int index) -{ - int tmp; - - /* Use the two byte form if possible, which cannot encode - VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ - if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT - && ((rm | index) & 8) == 0) { - /* Two byte VEX prefix. */ - tcg_out8(s, 0xc5); - - tmp = (r & 8 ? 0 : 0x80); /* VEX.R */ - } else { - /* Three byte VEX prefix. */ - tcg_out8(s, 0xc4); - - /* VEX.m-mmmm */ - if (opc & P_EXT3A) { - tmp = 3; - } else if (opc & P_EXT38) { - tmp = 2; - } else if (opc & P_EXT) { - tmp = 1; - } else { - g_assert_not_reached(); - } - tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */ - tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */ - tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ - tcg_out8(s, tmp); - - tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ - } - - tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ - /* VEX.pp */ - if (opc & P_DATA16) { - tmp |= 1; /* 0x66 */ - } else if (opc & P_SIMDF3) { - tmp |= 2; /* 0xf3 */ - } else if (opc & P_SIMDF2) { - tmp |= 3; /* 0xf2 */ - } - tmp |= (~v & 15) << 3; /* VEX.vvvv */ - tcg_out8(s, tmp); - tcg_out8(s, opc); -} - -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) -{ - tcg_out_vex_opc(s, opc, r, v, rm, 0); - tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); -} - -/* Output an opcode with a full "rm + (index<code_ptr + 5 + ~rm; - intptr_t disp = offset - pc; - if (disp == (int32_t)disp) { - tcg_out8(s, (LOWREGMASK(r) << 3) | 5); - tcg_out32(s, disp); - return; - } - - /* Try for an absolute address encoding. This requires the - use of the MODRM+SIB encoding and is therefore larger than - rip-relative addressing. */ - if (offset == (int32_t)offset) { - tcg_out8(s, (LOWREGMASK(r) << 3) | 4); - tcg_out8(s, (4 << 3) | 5); - tcg_out32(s, offset); - return; - } - - /* ??? The memory isn't directly addressable. */ - g_assert_not_reached(); - } else { - /* Absolute address. */ - tcg_out8(s, (r << 3) | 5); - tcg_out32(s, offset); - return; - } - } - - /* Find the length of the immediate addend. Note that the encoding - that would be used for (%ebp) indicates absolute addressing. */ - if (rm < 0) { - mod = 0, len = 4, rm = 5; - } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) { - mod = 0, len = 0; - } else if (offset == (int8_t)offset) { - mod = 0x40, len = 1; - } else { - mod = 0x80, len = 4; - } - - /* Use a single byte MODRM format if possible. Note that the encoding - that would be used for %esp is the escape to the two byte form. */ - if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) { - /* Single byte MODRM format. */ - tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); - } else { - /* Two byte MODRM+SIB format. */ - - /* Note that the encoding that would place %esp into the index - field indicates no index register. In 64-bit mode, the REX.X - bit counts, so %r12 can be used as the index. */ - if (index < 0) { - index = 4; - } else { - tcg_debug_assert(index != TCG_REG_ESP); - } - - tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); - tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm)); - } - - if (len == 1) { - tcg_out8(s, offset); - } else if (len == 4) { - tcg_out32(s, offset); - } -} - -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) -{ - tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); - tcg_out_sib_offset(s, r, rm, index, shift, offset); -} - -static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v, - int rm, int index, int shift, - intptr_t offset) -{ - tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); - tcg_out_sib_offset(s, r, rm, index, shift, offset); -} - -/* A simplification of the above with no index or shift. */ -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, - int rm, intptr_t offset) -{ - tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); -} - -static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, - int v, int rm, intptr_t offset) -{ - tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); -} - -/* Output an opcode with an expected reference to the constant pool. */ -static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r) -{ - tcg_out_opc(s, opc, r, 0, 0); - /* Absolute for 32-bit, pc-relative for 64-bit. */ - tcg_out8(s, LOWREGMASK(r) << 3 | 5); - tcg_out32(s, 0); -} - -/* Output an opcode with an expected reference to the constant pool. */ -static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r) -{ - tcg_out_vex_opc(s, opc, r, 0, 0, 0); - /* Absolute for 32-bit, pc-relative for 64-bit. */ - tcg_out8(s, LOWREGMASK(r) << 3 | 5); - tcg_out32(s, 0); -} - -/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */ -static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) -{ - /* Propagate an opcode prefix, such as P_REXW. */ - int ext = subop & ~0x7; - subop &= 0x7; - - tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); -} - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ - int rexw = 0; - - if (arg == ret) { - return true; - } - switch (type) { - case TCG_TYPE_I64: - rexw = P_REXW; - /* fallthru */ - case TCG_TYPE_I32: - if (ret < 16) { - if (arg < 16) { - tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg); - } else { - tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret); - } - } else { - if (arg < 16) { - tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg); - } else { - tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); - } - } - break; - - case TCG_TYPE_V64: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg); - break; - case TCG_TYPE_V128: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg); - break; - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16 && arg >= 16); - tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg); - break; - - default: - g_assert_not_reached(); - } - return true; -} - -static const int avx2_dup_insn[4] = { - OPC_VPBROADCASTB, OPC_VPBROADCASTW, - OPC_VPBROADCASTD, OPC_VPBROADCASTQ, -}; - -static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg r, TCGReg a) -{ - if (have_avx2) { - int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); - tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a); - } else { - switch (vece) { - case MO_8: - /* ??? With zero in a register, use PSHUFB. */ - tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, a, a); - a = r; - /* FALLTHRU */ - case MO_16: - tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, a, a); - a = r; - /* FALLTHRU */ - case MO_32: - tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a); - /* imm8 operand: all output lanes selected from input lane 0. */ - tcg_out8(s, 0); - break; - case MO_64: - tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, a, a); - break; - default: - g_assert_not_reached(); - } - } - return true; -} - -static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg r, TCGReg base, intptr_t offset) -{ - if (have_avx2) { - int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); - tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, - r, 0, base, offset); - } else { - switch (vece) { - case MO_64: - tcg_out_vex_modrm_offset(s, OPC_MOVDDUP, r, 0, base, offset); - break; - case MO_32: - tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset); - break; - case MO_16: - tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); - tcg_out8(s, 0); /* imm8 */ - tcg_out_dup_vec(s, type, vece, r, r); - break; - case MO_8: - tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); - tcg_out8(s, 0); /* imm8 */ - tcg_out_dup_vec(s, type, vece, r, r); - break; - default: - g_assert_not_reached(); - } - } - return true; -} - -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0); - - if (arg == 0) { - tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); - return; - } - if (arg == -1) { - tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret); - return; - } - - if (TCG_TARGET_REG_BITS == 64) { - if (type == TCG_TYPE_V64) { - tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret); - } else if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); - } else { - tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); - } - new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else { - if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret); - } else { - tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); - } - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); - } -} - -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - tcg_target_long diff; - - switch (type) { - case TCG_TYPE_I32: -#if TCG_TARGET_REG_BITS == 64 - case TCG_TYPE_I64: -#endif - if (ret < 16) { - break; - } - /* fallthru */ - case TCG_TYPE_V64: - case TCG_TYPE_V128: - case TCG_TYPE_V256: - tcg_debug_assert(ret >= 16); - tcg_out_dupi_vec(s, type, ret, arg); - return; - default: - g_assert_not_reached(); - } - - if (arg == 0) { - tgen_arithr(s, ARITH_XOR, ret, ret); - return; - } - if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { - tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0); - tcg_out32(s, arg); - return; - } - if (arg == (int32_t)arg) { - tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret); - tcg_out32(s, arg); - return; - } - - /* Try a 7 byte pc-relative lea before the 10 byte movq. */ - diff = arg - ((uintptr_t)s->code_ptr + 7); - if (diff == (int32_t)diff) { - tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); - tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); - tcg_out32(s, diff); - return; - } - - tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0); - tcg_out64(s, arg); -} - -static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) -{ - if (val == (int8_t)val) { - tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); - tcg_out8(s, val); - } else if (val == (int32_t)val) { - tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); - tcg_out32(s, val); - } else { - tcg_abort(); - } -} - -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - /* Given the strength of x86 memory ordering, we only need care for - store-load ordering. Experimentally, "lock orl $0,0(%esp)" is - faster than "mfence", so don't bother with the sse insn. */ - if (a0 & TCG_MO_ST_LD) { - tcg_out8(s, 0xf0); - tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); - tcg_out8(s, 0); - } -} - -static inline void tcg_out_push(TCGContext *s, int reg) -{ - tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); -} - -static inline void tcg_out_pop(TCGContext *s, int reg) -{ - tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) -{ - switch (type) { - case TCG_TYPE_I32: - if (ret < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); - } else { - tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2); - } - break; - case TCG_TYPE_I64: - if (ret < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); - break; - } - /* FALLTHRU */ - case TCG_TYPE_V64: - /* There is no instruction that can validate 8-byte alignment. */ - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2); - break; - case TCG_TYPE_V128: - /* - * The gvec infrastructure is asserts that v128 vector loads - * and stores use a 16-byte aligned offset. Validate that the - * final pointer is aligned by using an insn that will SIGSEGV. - */ - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2); - break; - case TCG_TYPE_V256: - /* - * The gvec infrastructure only requires 16-byte alignment, - * so here we must use an unaligned load. - */ - tcg_debug_assert(ret >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL, - ret, 0, arg1, arg2); - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - switch (type) { - case TCG_TYPE_I32: - if (arg < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); - } else { - tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2); - } - break; - case TCG_TYPE_I64: - if (arg < 16) { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); - break; - } - /* FALLTHRU */ - case TCG_TYPE_V64: - /* There is no instruction that can validate 8-byte alignment. */ - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2); - break; - case TCG_TYPE_V128: - /* - * The gvec infrastructure is asserts that v128 vector loads - * and stores use a 16-byte aligned offset. Validate that the - * final pointer is aligned by using an insn that will SIGSEGV. - */ - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); - break; - case TCG_TYPE_V256: - /* - * The gvec infrastructure only requires 16-byte alignment, - * so here we must use an unaligned store. - */ - tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL, - arg, 0, arg1, arg2); - break; - default: - g_assert_not_reached(); - } -} - -static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - int rexw = 0; - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { - if (val != (int32_t)val) { - return false; - } - rexw = P_REXW; - } else if (type != TCG_TYPE_I32) { - return false; - } - tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); - tcg_out32(s, val); - return true; -} - -static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) -{ - /* Propagate an opcode prefix, such as P_DATA16. */ - int ext = subopc & ~0x7; - subopc &= 0x7; - - if (count == 1) { - tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg); - } else { - tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg); - tcg_out8(s, count); - } -} - -static inline void tcg_out_bswap32(TCGContext *s, int reg) -{ - tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0); -} - -static inline void tcg_out_rolw_8(TCGContext *s, int reg) -{ - tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); -} - -static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) -{ - /* movzbl */ - tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); - tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); -} - -static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw) -{ - /* movsbl */ - tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); - tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); -} - -static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) -{ - /* movzwl */ - tcg_out_modrm(s, OPC_MOVZWL, dest, src); -} - -static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw) -{ - /* movsw[lq] */ - tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); -} - -static inline void tcg_out_ext32u(TCGContext *s, int dest, int src) -{ - /* 32-bit mov zero extends. */ - tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); -} - -static inline void tcg_out_ext32s(TCGContext *s, int dest, int src) -{ - tcg_out_modrm(s, OPC_MOVSLQ, dest, src); -} - -static inline void tcg_out_bswap64(TCGContext *s, int reg) -{ - tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); -} - -static void tgen_arithi(TCGContext *s, int c, int r0, - tcg_target_long val, int cf) -{ - int rexw = 0; - - if (TCG_TARGET_REG_BITS == 64) { - rexw = c & -8; - c &= 7; - } - - /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce - partial flags update stalls on Pentium4 and are not recommended - by current Intel optimization manuals. */ - if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) { - int is_inc = (c == ARITH_ADD) ^ (val < 0); - if (TCG_TARGET_REG_BITS == 64) { - /* The single-byte increment encodings are re-tasked as the - REX prefixes. Use the MODRM encoding. */ - tcg_out_modrm(s, OPC_GRP5 + rexw, - (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); - } else { - tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); - } - return; - } - - if (c == ARITH_AND) { - if (TCG_TARGET_REG_BITS == 64) { - if (val == 0xffffffffu) { - tcg_out_ext32u(s, r0, r0); - return; - } - if (val == (uint32_t)val) { - /* AND with no high bits set can use a 32-bit operation. */ - rexw = 0; - } - } - if (val == 0xffu && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) { - tcg_out_ext8u(s, r0, r0); - return; - } - if (val == 0xffffu) { - tcg_out_ext16u(s, r0, r0); - return; - } - } - - if (val == (int8_t)val) { - tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0); - tcg_out8(s, val); - return; - } - if (rexw == 0 || val == (int32_t)val) { - tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0); - tcg_out32(s, val); - return; - } - - tcg_abort(); -} - -static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) -{ - if (val != 0) { - tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); - } -} - -/* Use SMALL != 0 to force a short forward branch. */ -static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) -{ - int32_t val, val1; - - if (l->has_value) { - val = tcg_pcrel_diff(s, l->u.value_ptr); - val1 = val - 2; - if ((int8_t)val1 == val1) { - if (opc == -1) { - tcg_out8(s, OPC_JMP_short); - } else { - tcg_out8(s, OPC_JCC_short + opc); - } - tcg_out8(s, val1); - } else { - if (small) { - tcg_abort(); - } - if (opc == -1) { - tcg_out8(s, OPC_JMP_long); - tcg_out32(s, val - 5); - } else { - tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); - tcg_out32(s, val - 6); - } - } - } else if (small) { - if (opc == -1) { - tcg_out8(s, OPC_JMP_short); - } else { - tcg_out8(s, OPC_JCC_short + opc); - } - tcg_out_reloc(s, s->code_ptr, R_386_PC8, l, -1); - s->code_ptr += 1; - } else { - if (opc == -1) { - tcg_out8(s, OPC_JMP_long); - } else { - tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0); - } - tcg_out_reloc(s, s->code_ptr, R_386_PC32, l, -4); - s->code_ptr += 4; - } -} - -static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, - int const_arg2, int rexw) -{ - if (const_arg2) { - if (arg2 == 0) { - /* test r, r */ - tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); - } else { - tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); - } - } else { - tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); - } -} - -static void tcg_out_brcond32(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, 0); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); -} - -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_brcond64(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); -} -#else -/* XXX: we implement it at the target level to avoid having to - handle cross basic blocks temporaries */ -static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, - const int *const_args, int small) -{ - TCGLabel *label_next = gen_new_label(); - TCGLabel *label_this = arg_label(args[5]); - - switch(args[4]) { - case TCG_COND_EQ: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_next, 1); - tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], - label_this, small); - break; - case TCG_COND_NE: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_this, small); - tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], - label_this, small); - break; - case TCG_COND_LT: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LE: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GT: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GE: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LTU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_LEU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GTU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); - break; - case TCG_COND_GEU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); - tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); - break; - default: - tcg_abort(); - } - tcg_out_label(s, label_next, s->code_ptr); -} -#endif - -static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, 0); - tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); - tcg_out_ext8u(s, dest, dest); -} - -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); - tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); - tcg_out_ext8u(s, dest, dest); -} -#else -static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, - const int *const_args) -{ - TCGArg new_args[6]; - TCGLabel *label_true, *label_over; - - memcpy(new_args, args+1, 5*sizeof(TCGArg)); - - if (args[0] == args[1] || args[0] == args[2] - || (!const_args[3] && args[0] == args[3]) - || (!const_args[4] && args[0] == args[4])) { - /* When the destination overlaps with one of the argument - registers, don't do anything tricky. */ - label_true = gen_new_label(); - label_over = gen_new_label(); - - new_args[5] = label_arg(label_true); - tcg_out_brcond2(s, new_args, const_args+1, 1); - - tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); - tcg_out_jxx(s, JCC_JMP, label_over, 1); - tcg_out_label(s, label_true, s->code_ptr); - - tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); - tcg_out_label(s, label_over, s->code_ptr); - } else { - /* When the destination does not overlap one of the arguments, - clear the destination first, jump if cond false, and emit an - increment in the true case. This results in smaller code. */ - - tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); - - label_over = gen_new_label(); - new_args[4] = tcg_invert_cond(new_args[4]); - new_args[5] = label_arg(label_over); - tcg_out_brcond2(s, new_args, const_args+1, 1); - - tgen_arithi(s, ARITH_ADD, args[0], 1, 0); - tcg_out_label(s, label_over, s->code_ptr); - } -} -#endif - -static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, - TCGReg dest, TCGReg v1) -{ - if (have_cmov) { - tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | rexw, dest, v1); - } else { - TCGLabel *over = gen_new_label(); - tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); - tcg_out_mov(s, TCG_TYPE_I32, dest, v1); - tcg_out_label(s, over, s->code_ptr); - } -} - -static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) -{ - tcg_out_cmp(s, c1, c2, const_c2, 0); - tcg_out_cmov(s, cond, 0, dest, v1); -} - -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) -{ - tcg_out_cmp(s, c1, c2, const_c2, P_REXW); - tcg_out_cmov(s, cond, P_REXW, dest, v1); -} -#endif - -static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, - TCGArg arg2, bool const_a2) -{ - if (have_bmi1) { - tcg_out_modrm(s, OPC_TZCNT + rexw, dest, arg1); - if (const_a2) { - tcg_debug_assert(arg2 == (rexw ? 64 : 32)); - } else { - tcg_debug_assert(dest != arg2); - tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); - } - } else { - tcg_debug_assert(dest != arg2); - tcg_out_modrm(s, OPC_BSF + rexw, dest, arg1); - tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); - } -} - -static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, - TCGArg arg2, bool const_a2) -{ - if (have_lzcnt) { - tcg_out_modrm(s, OPC_LZCNT + rexw, dest, arg1); - if (const_a2) { - tcg_debug_assert(arg2 == (rexw ? 64 : 32)); - } else { - tcg_debug_assert(dest != arg2); - tcg_out_cmov(s, TCG_COND_LTU, rexw, dest, arg2); - } - } else { - tcg_debug_assert(!const_a2); - tcg_debug_assert(dest != arg1); - tcg_debug_assert(dest != arg2); - - /* Recall that the output of BSR is the index not the count. */ - tcg_out_modrm(s, OPC_BSR + rexw, dest, arg1); - tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); - - /* Since we have destroyed the flags from BSR, we have to re-test. */ - tcg_out_cmp(s, arg1, 0, 1, rexw); - tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); - } -} - -static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) -{ - intptr_t disp = tcg_pcrel_diff(s, dest) - 5; - - if (disp == (int32_t)disp) { - tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); - tcg_out32(s, disp); - } else { - /* rip-relative addressing into the constant pool. - This is 6 + 8 = 14 bytes, as compared to using an - an immediate load 10 + 6 = 16 bytes, plus we may - be able to re-use the pool constant for more calls. */ - tcg_out_opc(s, OPC_GRP5, 0, 0, 0); - tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); - new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); - tcg_out32(s, 0); - } -} - -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) -{ - tcg_out_branch(s, 1, dest); -} - -static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) -{ - tcg_out_branch(s, 0, dest); -} - -static void tcg_out_nopn(TCGContext *s, int n) -{ - int i; - /* Emit 1 or 2 operand size prefixes for the standard one byte nop, - * "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the - * duplicate prefix, and all of the interesting recent cores can - * decode and discard the duplicates in a single cycle. - */ - tcg_debug_assert(n >= 1); - for (i = 1; i < n; ++i) { - tcg_out8(s, 0x66); - } - tcg_out8(s, 0x90); -} - -#if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.inc.c" - -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_t ra) - */ -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the low and high part of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - Outputs: - LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses) - positions of the displacements of forward jumps to the TLB miss case. - - Second argument register is loaded with the low part of the address. - In the TLB hit case, it has been adjusted as indicated by the TLB - and so is a host address. In the TLB miss case, it continues to - hold a guest address. - - First argument register is clobbered. */ - -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - int mem_index, MemOp opc, - tcg_insn_unit **label_ptr, int which) -{ - const TCGReg r0 = TCG_REG_L0; - const TCGReg r1 = TCG_REG_L1; - TCGType ttype = TCG_TYPE_I32; - TCGType tlbtype = TCG_TYPE_I32; - int trexw = 0, hrexw = 0, tlbrexw = 0; - unsigned a_bits = get_alignment_bits(opc); - unsigned s_bits = opc & MO_SIZE; - unsigned a_mask = (1 << a_bits) - 1; - unsigned s_mask = (1 << s_bits) - 1; - target_ulong tlb_mask; - - if (TCG_TARGET_REG_BITS == 64) { - if (TARGET_LONG_BITS == 64) { - ttype = TCG_TYPE_I64; - trexw = P_REXW; - } - if (TCG_TYPE_PTR == TCG_TYPE_I64) { - hrexw = P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { - tlbtype = TCG_TYPE_I64; - tlbrexw = P_REXW; - } - } - } - - tcg_out_mov(s, tlbtype, r0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); - - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); - - /* If the required alignment is at least as large as the access, simply - copy the address and mask. For lesser alignments, check that we don't - cross pages for the complete access. */ - if (a_bits >= s_bits) { - tcg_out_mov(s, ttype, r1, addrlo); - } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_mask); - } - tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); - - /* cmp 0(r0), r1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which); - - /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. */ - tcg_out_mov(s, ttype, r1, addrlo); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[0] = s->code_ptr; - s->code_ptr += 4; - - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(r0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[1] = s->code_ptr; - s->code_ptr += 4; - } - - /* TLB Hit. */ - - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, - offsetof(CPUTLBEntry, addend)); -} - -/* - * Record the context of a call to the out of line helper code for the slow path - * for a load or store, so that we can later generate the correct helper code - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - TCGMemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->type = is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] = label_ptr[1]; - } -} - -/* - * Generate code for the slow path for a load at the end of block - */ -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - TCGReg data_reg; - tcg_insn_unit **label_ptr = &l->label_ptr[0]; - int rexw = (l->type == TCG_TYPE_I64 ? P_REXW : 0); - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS == 32) { - int ofs = 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (TARGET_LONG_BITS == 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - data_reg = l->datalo_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw); - break; - case MO_SW: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); - break; -#if TCG_TARGET_REG_BITS == 64 - case MO_SL: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; -#endif - case MO_UB: - case MO_UW: - /* Note that the helpers have zero-extended to tcg_target_long. */ - case MO_UL: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; - case MO_Q: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg == TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } - break; - default: - tcg_abort(); - } - - /* Jump to the code corresponding to next IR of qemu_st */ - tcg_out_jmp(s, l->raddr); - return true; -} - -/* - * Generate code for the slow path for a store at the end of block - */ -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - MemOp s_bits = opc & MO_SIZE; - tcg_insn_unit **label_ptr = &l->label_ptr[0]; - TCGReg retaddr; - - /* resolve label address */ - tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); - } - - if (TCG_TARGET_REG_BITS == 32) { - int ofs = 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs += 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (TARGET_LONG_BITS == 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs += 4; - - if (s_bits == MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs += 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs += 4; - - retaddr = TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr = tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr = TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - return true; -} -#elif TCG_TARGET_REG_BITS == 32 -# define x86_guest_base_seg 0 -# define x86_guest_base_index -1 -# define x86_guest_base_offset guest_base -#else -static int x86_guest_base_seg; -static int x86_guest_base_index = -1; -static int32_t x86_guest_base_offset; -# if defined(__x86_64__) && defined(__linux__) -# include -# include -int arch_prctl(int code, unsigned long addr); -static inline int setup_guest_base_seg(void) -{ - if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { - return P_GS; - } - return 0; -} -# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) -# include -static inline int setup_guest_base_seg(void) -{ - if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { - return P_GS; - } - return 0; -} -# else -static inline int setup_guest_base_seg(void) -{ - return 0; -} -# endif -#endif /* SOFTMMU */ - -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg base, int index, intptr_t ofs, - int seg, bool is64, MemOp memop) -{ - const MemOp real_bswap = memop & MO_BSWAP; - MemOp bswap = real_bswap; - int rexw = is64 * P_REXW; - int movop = OPC_MOVL_GvEv; - - if (have_movbe && real_bswap) { - bswap = 0; - movop = OPC_MOVBE_GyMy; - } - - switch (memop & MO_SSIZE) { - case MO_UB: - tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, - base, index, 0, ofs); - break; - case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, - base, index, 0, ofs); - break; - case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); - } - break; - case MO_SW: - if (real_bswap) { - if (have_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, - datalo, base, index, 0, ofs); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - tcg_out_rolw_8(s, datalo); - } - tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, - datalo, base, index, 0, ofs); - } - break; - case MO_UL: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } - break; -#if TCG_TARGET_REG_BITS == 64 - case MO_SL: - if (real_bswap) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } - tcg_out_ext32s(s, datalo, datalo); - } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, - base, index, 0, ofs); - } - break; -#endif - case MO_Q: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); - if (bswap) { - tcg_out_bswap64(s, datalo); - } - } else { - if (real_bswap) { - int t = datalo; - datalo = datahi; - datahi = t; - } - if (base != datalo) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - } else { - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - } - if (bswap) { - tcg_out_bswap32(s, datalo); - tcg_out_bswap32(s, datahi); - } - } - break; - default: - tcg_abort(); - } -} - -/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and - EAX. It will be useful once fixed registers globals are less - common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) -{ - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif - - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); - - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else - tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, - is64, opc); -#endif -} - -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg base, int index, intptr_t ofs, - int seg, MemOp memop) -{ - /* ??? Ideally we wouldn't need a scratch register. For user-only, - we could perform the bswap twice to restore the original value - instead of moving to the scratch. But as it is, the L constraint - means that TCG_REG_L0 is definitely free here. */ - const TCGReg scratch = TCG_REG_L0; - const MemOp real_bswap = memop & MO_BSWAP; - MemOp bswap = real_bswap; - int movop = OPC_MOVL_EvGv; - - if (have_movbe && real_bswap) { - bswap = 0; - movop = OPC_MOVBE_MyGy; - } - - switch (memop & MO_SIZE) { - case MO_8: - /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. - Use the scratch register if necessary. */ - if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, index, 0, ofs); - break; - case MO_16: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_rolw_8(s, scratch); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, - base, index, 0, ofs); - break; - case MO_32: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - break; - case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); - tcg_out_bswap64(s, scratch); - datalo = scratch; - } - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); - } else if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs); - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs + 4); - } else { - if (real_bswap) { - int t = datalo; - datalo = datahi; - datahi = t; - } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - } - break; - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) -{ - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif - - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); - - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#else - tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, opc); -#endif -} - -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - TCGArg a0, a1, a2; - int c, const_a2, vexop, rexw = 0; - -#if TCG_TARGET_REG_BITS == 64 -# define OP_32_64(x) \ - case glue(glue(INDEX_op_, x), _i64): \ - rexw = P_REXW; /* FALLTHRU */ \ - case glue(glue(INDEX_op_, x), _i32) -#else -# define OP_32_64(x) \ - case glue(glue(INDEX_op_, x), _i32) -#endif - - /* Hoist the loads of the most common arguments. */ - a0 = args[0]; - a1 = args[1]; - a2 = args[2]; - const_a2 = const_args[2]; - - switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 == 0) { - tcg_out_jmp(s, s->code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); - tcg_out_jmp(s, tb_ret_addr); - } - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - int gap; - /* jump displacement must be aligned for atomic patching; - * see if we need to add extra nops before jump - */ - gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4)); - if (gap != 1) { - tcg_out_nopn(s, gap - 1); - } - tcg_out8(s, OPC_JMP_long); /* jmp im */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* indirect jump method */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, -1, - (intptr_t)(s->tb_jmp_target_addr + a0)); - } - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: - /* jmp to the given host address (could be epilogue) */ - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, a0); - break; - case INDEX_op_br: - tcg_out_jxx(s, JCC_JMP, arg_label(a0), 0); - break; - OP_32_64(ld8u): - /* Note that we can ignore REXW for the zero-extend to 64-bit. */ - tcg_out_modrm_offset(s, OPC_MOVZBL, a0, a1, a2); - break; - OP_32_64(ld8s): - tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, a0, a1, a2); - break; - OP_32_64(ld16u): - /* Note that we can ignore REXW for the zero-extend to 64-bit. */ - tcg_out_modrm_offset(s, OPC_MOVZWL, a0, a1, a2); - break; - OP_32_64(ld16s): - tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, a0, a1, a2); - break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_ld32u_i64: -#endif - case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, a0, a1, a2); - break; - - OP_32_64(st8): - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2); - tcg_out8(s, a0); - } else { - tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2); - } - break; - OP_32_64(st16): - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2); - tcg_out16(s, a0); - } else { - tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2); - } - break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_st32_i64: -#endif - case INDEX_op_st_i32: - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2); - tcg_out32(s, a0); - } else { - tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2); - } - break; - - OP_32_64(add): - /* For 3-operand addition, use LEA. */ - if (a0 != a1) { - TCGArg c3 = 0; - if (const_a2) { - c3 = a2, a2 = -1; - } else if (a0 == a2) { - /* Watch out for dest = src + dest, since we've removed - the matching constraint on the add. */ - tgen_arithr(s, ARITH_ADD + rexw, a0, a1); - break; - } - - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3); - break; - } - c = ARITH_ADD; - goto gen_arith; - OP_32_64(sub): - c = ARITH_SUB; - goto gen_arith; - OP_32_64(and): - c = ARITH_AND; - goto gen_arith; - OP_32_64(or): - c = ARITH_OR; - goto gen_arith; - OP_32_64(xor): - c = ARITH_XOR; - goto gen_arith; - gen_arith: - if (const_a2) { - tgen_arithi(s, c + rexw, a0, a2, 0); - } else { - tgen_arithr(s, c + rexw, a0, a2); - } - break; - - OP_32_64(andc): - if (const_a2) { - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); - } else { - tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); - } - break; - - OP_32_64(mul): - if (const_a2) { - int32_t val; - val = a2; - if (val == (int8_t)val) { - tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, a0, a0); - tcg_out8(s, val); - } else { - tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, a0, a0); - tcg_out32(s, val); - } - } else { - tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, a0, a2); - } - break; - - OP_32_64(div2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]); - break; - OP_32_64(divu2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]); - break; - - OP_32_64(shl): - /* For small constant 3-operand shift, use LEA. */ - if (const_a2 && a0 != a1 && (a2 - 1) < 3) { - if (a2 - 1 == 0) { - /* shl $1,a1,a0 -> lea (a1,a1),a0 */ - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a1, 0, 0); - } else { - /* shl $n,a1,a0 -> lea 0(,a1,n),a0 */ - tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, -1, a1, a2, 0); - } - break; - } - c = SHIFT_SHL; - vexop = OPC_SHLX; - goto gen_shift_maybe_vex; - OP_32_64(shr): - c = SHIFT_SHR; - vexop = OPC_SHRX; - goto gen_shift_maybe_vex; - OP_32_64(sar): - c = SHIFT_SAR; - vexop = OPC_SARX; - goto gen_shift_maybe_vex; - OP_32_64(rotl): - c = SHIFT_ROL; - goto gen_shift; - OP_32_64(rotr): - c = SHIFT_ROR; - goto gen_shift; - gen_shift_maybe_vex: - if (have_bmi2) { - if (!const_a2) { - tcg_out_vex_modrm(s, vexop + rexw, a0, a2, a1); - break; - } - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - } - /* FALLTHRU */ - gen_shift: - if (const_a2) { - tcg_out_shifti(s, c + rexw, a0, a2); - } else { - tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, a0); - } - break; - - OP_32_64(ctz): - tcg_out_ctz(s, rexw, args[0], args[1], args[2], const_args[2]); - break; - OP_32_64(clz): - tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]); - break; - OP_32_64(ctpop): - tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); - break; - - case INDEX_op_brcond_i32: - tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); - break; - case INDEX_op_setcond_i32: - tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); - break; - case INDEX_op_movcond_i32: - tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); - break; - - OP_32_64(bswap16): - tcg_out_rolw_8(s, a0); - break; - OP_32_64(bswap32): - tcg_out_bswap32(s, a0); - break; - - OP_32_64(neg): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, a0); - break; - OP_32_64(not): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); - break; - - OP_32_64(ext8s): - tcg_out_ext8s(s, a0, a1, rexw); - break; - OP_32_64(ext16s): - tcg_out_ext16s(s, a0, a1, rexw); - break; - OP_32_64(ext8u): - tcg_out_ext8u(s, a0, a1); - break; - OP_32_64(ext16u): - tcg_out_ext16u(s, a0, a1); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); - break; - - OP_32_64(mulu2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); - break; - OP_32_64(muls2): - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]); - break; - OP_32_64(add2): - if (const_args[4]) { - tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); - } - break; - OP_32_64(sub2): - if (const_args[4]) { - tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); - } - break; - -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args, const_args, 0); - break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args, const_args); - break; -#else /* TCG_TARGET_REG_BITS == 64 */ - case INDEX_op_ld32s_i64: - tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); - break; - case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, a0, a1, a2); - break; - case INDEX_op_st_i64: - if (const_args[0]) { - tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2); - tcg_out32(s, a0); - } else { - tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2); - } - break; - - case INDEX_op_brcond_i64: - tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); - break; - case INDEX_op_setcond_i64: - tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); - break; - case INDEX_op_movcond_i64: - tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); - break; - - case INDEX_op_bswap64_i64: - tcg_out_bswap64(s, a0); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_extrl_i64_i32: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_ext32s(s, a0, a1); - break; - case INDEX_op_extrh_i64_i32: - tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); - break; -#endif - - OP_32_64(deposit): - if (args[3] == 0 && args[4] == 8) { - /* load bits 0..7 */ - tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); - } else if (args[3] == 8 && args[4] == 8) { - /* load bits 8..15 */ - tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); - } else if (args[3] == 0 && args[4] == 16) { - /* load bits 0..15 */ - tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); - } else { - tcg_abort(); - } - break; - - case INDEX_op_extract_i64: - if (a2 + args[3] == 32) { - /* This is a 32-bit zero-extending right shift. */ - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tcg_out_shifti(s, SHIFT_SHR, a0, a2); - break; - } - /* FALLTHRU */ - case INDEX_op_extract_i32: - /* On the off-chance that we can use the high-byte registers. - Otherwise we emit the same ext16 + shift pattern that we - would have gotten from the normal tcg-op.c expansion. */ - tcg_debug_assert(a2 == 8 && args[3] == 8); - if (a1 < 4 && a0 < 8) { - tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4); - } else { - tcg_out_ext16u(s, a0, a1); - tcg_out_shifti(s, SHIFT_SHR, a0, 8); - } - break; - - case INDEX_op_sextract_i32: - /* We don't implement sextract_i64, as we cannot sign-extend to - 64-bits without using the REX prefix that explicitly excludes - access to the high-byte registers. */ - tcg_debug_assert(a2 == 8 && args[3] == 8); - if (a1 < 4 && a0 < 8) { - tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); - } else { - tcg_out_ext16s(s, a0, a1, 0); - tcg_out_shifti(s, SHIFT_SAR, a0, 8); - } - break; - - OP_32_64(extract2): - /* Note that SHRD outputs to the r/m operand. */ - tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); - tcg_out8(s, args[3]); - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } - -#undef OP_32_64 -} - -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, - unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) -{ - static int const add_insn[4] = { - OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ - }; - static int const ssadd_insn[4] = { - OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 - }; - static int const usadd_insn[4] = { - OPC_PADDUB, OPC_PADDUW, OPC_UD2, OPC_UD2 - }; - static int const sub_insn[4] = { - OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ - }; - static int const sssub_insn[4] = { - OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 - }; - static int const ussub_insn[4] = { - OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2 - }; - static int const mul_insn[4] = { - OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2 - }; - static int const shift_imm_insn[4] = { - OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib - }; - static int const cmpeq_insn[4] = { - OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ - }; - static int const cmpgt_insn[4] = { - OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ - }; - static int const punpckl_insn[4] = { - OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ - }; - static int const punpckh_insn[4] = { - OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ - }; - static int const packss_insn[4] = { - OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2 - }; - static int const packus_insn[4] = { - OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2 - }; - static int const smin_insn[4] = { - OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2 - }; - static int const smax_insn[4] = { - OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2 - }; - static int const umin_insn[4] = { - OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2 - }; - static int const umax_insn[4] = { - OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 - }; - static int const shlv_insn[4] = { - /* TODO: AVX512 adds support for MO_16. */ - OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ - }; - static int const shrv_insn[4] = { - /* TODO: AVX512 adds support for MO_16. */ - OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ - }; - static int const sarv_insn[4] = { - /* TODO: AVX512 adds support for MO_16, MO_64. */ - OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 - }; - static int const shls_insn[4] = { - OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ - }; - static int const shrs_insn[4] = { - OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ - }; - static int const sars_insn[4] = { - OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 - }; - static int const abs_insn[4] = { - /* TODO: AVX512 adds support for MO_64. */ - OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2 - }; - - TCGType type = vecl + TCG_TYPE_V64; - int insn, sub; - TCGArg a0, a1, a2; - - a0 = args[0]; - a1 = args[1]; - a2 = args[2]; - - switch (opc) { - case INDEX_op_add_vec: - insn = add_insn[vece]; - goto gen_simd; - case INDEX_op_ssadd_vec: - insn = ssadd_insn[vece]; - goto gen_simd; - case INDEX_op_usadd_vec: - insn = usadd_insn[vece]; - goto gen_simd; - case INDEX_op_sub_vec: - insn = sub_insn[vece]; - goto gen_simd; - case INDEX_op_sssub_vec: - insn = sssub_insn[vece]; - goto gen_simd; - case INDEX_op_ussub_vec: - insn = ussub_insn[vece]; - goto gen_simd; - case INDEX_op_mul_vec: - insn = mul_insn[vece]; - goto gen_simd; - case INDEX_op_and_vec: - insn = OPC_PAND; - goto gen_simd; - case INDEX_op_or_vec: - insn = OPC_POR; - goto gen_simd; - case INDEX_op_xor_vec: - insn = OPC_PXOR; - goto gen_simd; - case INDEX_op_smin_vec: - insn = smin_insn[vece]; - goto gen_simd; - case INDEX_op_umin_vec: - insn = umin_insn[vece]; - goto gen_simd; - case INDEX_op_smax_vec: - insn = smax_insn[vece]; - goto gen_simd; - case INDEX_op_umax_vec: - insn = umax_insn[vece]; - goto gen_simd; - case INDEX_op_shlv_vec: - insn = shlv_insn[vece]; - goto gen_simd; - case INDEX_op_shrv_vec: - insn = shrv_insn[vece]; - goto gen_simd; - case INDEX_op_sarv_vec: - insn = sarv_insn[vece]; - goto gen_simd; - case INDEX_op_shls_vec: - insn = shls_insn[vece]; - goto gen_simd; - case INDEX_op_shrs_vec: - insn = shrs_insn[vece]; - goto gen_simd; - case INDEX_op_sars_vec: - insn = sars_insn[vece]; - goto gen_simd; - case INDEX_op_x86_punpckl_vec: - insn = punpckl_insn[vece]; - goto gen_simd; - case INDEX_op_x86_punpckh_vec: - insn = punpckh_insn[vece]; - goto gen_simd; - case INDEX_op_x86_packss_vec: - insn = packss_insn[vece]; - goto gen_simd; - case INDEX_op_x86_packus_vec: - insn = packus_insn[vece]; - goto gen_simd; -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_dup2_vec: - /* First merge the two 32-bit inputs to a single 64-bit element. */ - tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); - /* Then replicate the 64-bit elements across the rest of the vector. */ - if (type != TCG_TYPE_V64) { - tcg_out_dup_vec(s, type, MO_64, a0, a0); - } - break; -#endif - case INDEX_op_abs_vec: - insn = abs_insn[vece]; - a2 = a1; - a1 = 0; - goto gen_simd; - gen_simd: - tcg_debug_assert(insn != OPC_UD2); - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - break; - - case INDEX_op_cmp_vec: - sub = args[3]; - if (sub == TCG_COND_EQ) { - insn = cmpeq_insn[vece]; - } else if (sub == TCG_COND_GT) { - insn = cmpgt_insn[vece]; - } else { - g_assert_not_reached(); - } - goto gen_simd; - - case INDEX_op_andc_vec: - insn = OPC_PANDN; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a2, a1); - break; - - case INDEX_op_shli_vec: - sub = 6; - goto gen_shift; - case INDEX_op_shri_vec: - sub = 2; - goto gen_shift; - case INDEX_op_sari_vec: - tcg_debug_assert(vece != MO_64); - sub = 4; - gen_shift: - tcg_debug_assert(vece != MO_8); - insn = shift_imm_insn[vece]; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, sub, a0, a1); - tcg_out8(s, a2); - break; - - case INDEX_op_ld_vec: - tcg_out_ld(s, type, a0, a1, a2); - break; - case INDEX_op_st_vec: - tcg_out_st(s, type, a0, a1, a2); - break; - case INDEX_op_dupm_vec: - tcg_out_dupm_vec(s, type, vece, a0, a1, a2); - break; - - case INDEX_op_x86_shufps_vec: - insn = OPC_SHUFPS; - sub = args[3]; - goto gen_simd_imm8; - case INDEX_op_x86_blend_vec: - if (vece == MO_16) { - insn = OPC_PBLENDW; - } else if (vece == MO_32) { - insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS); - } else { - g_assert_not_reached(); - } - sub = args[3]; - goto gen_simd_imm8; - case INDEX_op_x86_vperm2i128_vec: - insn = OPC_VPERM2I128; - sub = args[3]; - goto gen_simd_imm8; - gen_simd_imm8: - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - tcg_out8(s, sub); - break; - - case INDEX_op_x86_vpblendvb_vec: - insn = OPC_VPBLENDVB; - if (type == TCG_TYPE_V256) { - insn |= P_VEXL; - } - tcg_out_vex_modrm(s, insn, a0, a1, a2); - tcg_out8(s, args[3] << 4); - break; - - case INDEX_op_x86_psrldq_vec: - tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1); - tcg_out8(s, a2); - break; - - case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ - case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ - default: - g_assert_not_reached(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } }; - static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } }; - static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } }; - static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } }; - static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } }; - static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; - static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } }; - static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } }; - static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } }; - static const TCGTargetOpDef x_x_x_x - = { .args_ct_str = { "x", "x", "x", "x" } }; - static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - return &qi_r; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - return &ri_r; - case INDEX_op_st_i64: - return &re_r; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - return &r_r_re; - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - case INDEX_op_mul_i32: - case INDEX_op_mul_i64: - case INDEX_op_or_i32: - case INDEX_op_or_i64: - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - return &r_0_re; - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - { - static const TCGTargetOpDef and - = { .args_ct_str = { "r", "0", "reZ" } }; - return ∧ - } - break; - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - { - static const TCGTargetOpDef andc - = { .args_ct_str = { "r", "r", "rI" } }; - return &andc; - } - break; - - case INDEX_op_shl_i32: - case INDEX_op_shl_i64: - case INDEX_op_shr_i32: - case INDEX_op_shr_i64: - case INDEX_op_sar_i32: - case INDEX_op_sar_i64: - return have_bmi2 ? &r_r_ri : &r_0_ci; - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_0_ci; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &r_re; - - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_neg_i32: - case INDEX_op_neg_i64: - case INDEX_op_not_i32: - case INDEX_op_not_i64: - case INDEX_op_extrh_i64_i32: - return &r_0; - - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - return &r_q; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extract_i32: - case INDEX_op_extract_i64: - case INDEX_op_sextract_i32: - case INDEX_op_ctpop_i32: - case INDEX_op_ctpop_i64: - return &r_r; - case INDEX_op_extract2_i32: - case INDEX_op_extract2_i64: - return &r_0_r; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "Q", "0", "Q" } }; - return &dep; - } - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - { - static const TCGTargetOpDef setc - = { .args_ct_str = { "q", "r", "re" } }; - return &setc; - } - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "re", "r", "0" } }; - return &movc; - } - case INDEX_op_div2_i32: - case INDEX_op_div2_i64: - case INDEX_op_divu2_i32: - case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "a", "d", "0", "1", "r" } }; - return &div2; - } - case INDEX_op_mulu2_i32: - case INDEX_op_mulu2_i64: - case INDEX_op_muls2_i32: - case INDEX_op_muls2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "a", "d", "a", "r" } }; - return &mul2; - } - case INDEX_op_add2_i32: - case INDEX_op_add2_i64: - case INDEX_op_sub2_i32: - case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } }; - return &arith2; - } - case INDEX_op_ctz_i32: - case INDEX_op_ctz_i64: - { - static const TCGTargetOpDef ctz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &ctz[have_bmi1]; - } - case INDEX_op_clz_i32: - case INDEX_op_clz_i64: - { - static const TCGTargetOpDef clz[2] = { - { .args_ct_str = { "&r", "r", "r" } }, - { .args_ct_str = { "&r", "r", "rW" } }, - }; - return &clz[have_lzcnt]; - } - - case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L); - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &L_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L - : &L_L_L_L); - - case INDEX_op_brcond2_i32: - { - static const TCGTargetOpDef b2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - return &b2; - } - case INDEX_op_setcond2_i32: - { - static const TCGTargetOpDef s2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - return &s2; - } - - case INDEX_op_ld_vec: - case INDEX_op_st_vec: - case INDEX_op_dupm_vec: - return &x_r; - - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_mul_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_usadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_ussub_vec: - case INDEX_op_smin_vec: - case INDEX_op_umin_vec: - case INDEX_op_smax_vec: - case INDEX_op_umax_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_shls_vec: - case INDEX_op_shrs_vec: - case INDEX_op_sars_vec: - case INDEX_op_rotls_vec: - case INDEX_op_cmp_vec: - case INDEX_op_x86_shufps_vec: - case INDEX_op_x86_blend_vec: - case INDEX_op_x86_packss_vec: - case INDEX_op_x86_packus_vec: - case INDEX_op_x86_vperm2i128_vec: - case INDEX_op_x86_punpckl_vec: - case INDEX_op_x86_punpckh_vec: -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_dup2_vec: -#endif - return &x_x_x; - case INDEX_op_abs_vec: - case INDEX_op_dup_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - case INDEX_op_x86_psrldq_vec: - return &x_x; - case INDEX_op_x86_vpblendvb_vec: - return &x_x_x_x; - - default: - break; - } - return NULL; -} - -int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) -{ - switch (opc) { - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - return 1; - case INDEX_op_rotli_vec: - case INDEX_op_cmp_vec: - case INDEX_op_cmpsel_vec: - return -1; - - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - /* We must expand the operation for MO_8. */ - return vece == MO_8 ? -1 : 1; - - case INDEX_op_sari_vec: - /* We must expand the operation for MO_8. */ - if (vece == MO_8) { - return -1; - } - /* We can emulate this for MO_64, but it does not pay off - unless we're producing at least 4 values. */ - if (vece == MO_64) { - return type >= TCG_TYPE_V256 ? -1 : 0; - } - return 1; - - case INDEX_op_shls_vec: - case INDEX_op_shrs_vec: - return vece >= MO_16; - case INDEX_op_sars_vec: - return vece >= MO_16 && vece <= MO_32; - case INDEX_op_rotls_vec: - return vece >= MO_16 ? -1 : 0; - - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - return have_avx2 && vece >= MO_32; - case INDEX_op_sarv_vec: - return have_avx2 && vece == MO_32; - case INDEX_op_rotlv_vec: - case INDEX_op_rotrv_vec: - return have_avx2 && vece >= MO_32 ? -1 : 0; - - case INDEX_op_mul_vec: - if (vece == MO_8) { - /* We can expand the operation for MO_8. */ - return -1; - } - if (vece == MO_64) { - return 0; - } - return 1; - - case INDEX_op_ssadd_vec: - case INDEX_op_usadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_ussub_vec: - return vece <= MO_16; - case INDEX_op_smin_vec: - case INDEX_op_smax_vec: - case INDEX_op_umin_vec: - case INDEX_op_umax_vec: - case INDEX_op_abs_vec: - return vece <= MO_32; - - default: - return 0; - } -} - -static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, - TCGv_vec v0, TCGv_vec v1, TCGArg imm) -{ - TCGv_vec t1, t2; - - tcg_debug_assert(vece == MO_8); - - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - - /* - * Unpack to W, shift, and repack. Tricky bits: - * (1) Use punpck*bw x,x to produce DDCCBBAA, - * i.e. duplicate in other half of the 16-bit lane. - * (2) For right-shift, add 8 so that the high half of the lane - * becomes zero. For left-shift, and left-rotate, we must - * shift up and down again. - * (3) Step 2 leaves high half zero such that PACKUSWB - * (pack with unsigned saturation) does not modify - * the quantity. - */ - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - - if (opc != INDEX_op_rotli_vec) { - imm += 8; - } - if (opc == INDEX_op_shri_vec) { - tcg_gen_shri_vec(MO_16, t1, t1, imm); - tcg_gen_shri_vec(MO_16, t2, t2, imm); - } else { - tcg_gen_shli_vec(MO_16, t1, t1, imm); - tcg_gen_shli_vec(MO_16, t2, t2, imm); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - tcg_gen_shri_vec(MO_16, t2, t2, 8); - } - - vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); -} - -static void expand_vec_sari(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGArg imm) -{ - TCGv_vec t1, t2; - - switch (vece) { - case MO_8: - /* Unpack to W, shift, and repack, as in expand_vec_shi. */ - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - tcg_gen_sari_vec(MO_16, t1, t1, imm + 8); - tcg_gen_sari_vec(MO_16, t2, t2, imm + 8); - vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; - - case MO_64: - if (imm <= 32) { - /* - * We can emulate a small sign extend by performing an arithmetic - * 32-bit shift and overwriting the high half of a 64-bit logical - * shift. Note that the ISA says shift of 32 is valid, but TCG - * does not, so we have to bound the smaller shift -- we get the - * same result in the high half either way. - */ - t1 = tcg_temp_new_vec(type); - tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); - tcg_gen_shri_vec(MO_64, v0, v1, imm); - vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, - tcgv_vec_arg(v0), tcgv_vec_arg(v0), - tcgv_vec_arg(t1), 0xaa); - tcg_temp_free_vec(t1); - } else { - /* Otherwise we will need to use a compare vs 0 to produce - * the sign-extend, shift and merge. - */ - t1 = tcg_const_zeros_vec(type); - tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1); - tcg_gen_shri_vec(MO_64, v0, v1, imm); - tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm); - tcg_gen_or_vec(MO_64, v0, v0, t1); - tcg_temp_free_vec(t1); - } - break; - - default: - g_assert_not_reached(); - } -} - -static void expand_vec_rotli(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGArg imm) -{ - TCGv_vec t; - - if (vece == MO_8) { - expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); - return; - } - - t = tcg_temp_new_vec(type); - tcg_gen_shli_vec(vece, t, v1, imm); - tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm); - tcg_gen_or_vec(vece, v0, v0, t); - tcg_temp_free_vec(t); -} - -static void expand_vec_rotls(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh) -{ - TCGv_i32 rsh; - TCGv_vec t; - - tcg_debug_assert(vece != MO_8); - - t = tcg_temp_new_vec(type); - rsh = tcg_temp_new_i32(); - - tcg_gen_neg_i32(rsh, lsh); - tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1); - tcg_gen_shls_vec(vece, t, v1, lsh); - tcg_gen_shrs_vec(vece, v0, v1, rsh); - tcg_gen_or_vec(vece, v0, v0, t); - tcg_temp_free_vec(t); - tcg_temp_free_i32(rsh); -} - -static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec sh, bool right) -{ - TCGv_vec t = tcg_temp_new_vec(type); - - tcg_gen_dupi_vec(vece, t, 8 << vece); - tcg_gen_sub_vec(vece, t, t, sh); - if (right) { - tcg_gen_shlv_vec(vece, t, v1, t); - tcg_gen_shrv_vec(vece, v0, v1, sh); - } else { - tcg_gen_shrv_vec(vece, t, v1, t); - tcg_gen_shlv_vec(vece, v0, v1, sh); - } - tcg_gen_or_vec(vece, v0, v0, t); - tcg_temp_free_vec(t); -} - -static void expand_vec_mul(TCGType type, unsigned vece, - TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) -{ - TCGv_vec t1, t2, t3, t4; - - tcg_debug_assert(vece == MO_8); - - /* - * Unpack v1 bytes to words, 0 | x. - * Unpack v2 bytes to words, y | 0. - * This leaves the 8-bit result, x * y, with 8 bits of right padding. - * Shift logical right by 8 bits to clear the high 8 bytes before - * using an unsigned saturated pack. - * - * The difference between the V64, V128 and V256 cases is merely how - * we distribute the expansion between temporaries. - */ - switch (type) { - case TCG_TYPE_V64: - t1 = tcg_temp_new_vec(TCG_TYPE_V128); - t2 = tcg_temp_new_vec(TCG_TYPE_V128); - tcg_gen_dup16i_vec(t2, 0); - vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2)); - vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2)); - tcg_gen_mul_vec(MO_16, t1, t1, t2); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - break; - - case TCG_TYPE_V128: - case TCG_TYPE_V256: - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - t3 = tcg_temp_new_vec(type); - t4 = tcg_temp_new_vec(type); - tcg_gen_dup16i_vec(t4, 0); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2)); - tcg_gen_mul_vec(MO_16, t1, t1, t2); - tcg_gen_mul_vec(MO_16, t3, t3, t4); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - tcg_gen_shri_vec(MO_16, t3, t3, 8); - vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - tcg_temp_free_vec(t3); - tcg_temp_free_vec(t4); - break; - - default: - g_assert_not_reached(); - } -} - -static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - enum { - NEED_INV = 1, - NEED_SWAP = 2, - NEED_BIAS = 4, - NEED_UMIN = 8, - NEED_UMAX = 16, - }; - TCGv_vec t1, t2; - uint8_t fixup; - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_GT: - fixup = 0; - break; - case TCG_COND_NE: - case TCG_COND_LE: - fixup = NEED_INV; - break; - case TCG_COND_LT: - fixup = NEED_SWAP; - break; - case TCG_COND_GE: - fixup = NEED_SWAP | NEED_INV; - break; - case TCG_COND_LEU: - if (vece <= MO_32) { - fixup = NEED_UMIN; - } else { - fixup = NEED_BIAS | NEED_INV; - } - break; - case TCG_COND_GTU: - if (vece <= MO_32) { - fixup = NEED_UMIN | NEED_INV; - } else { - fixup = NEED_BIAS; - } - break; - case TCG_COND_GEU: - if (vece <= MO_32) { - fixup = NEED_UMAX; - } else { - fixup = NEED_BIAS | NEED_SWAP | NEED_INV; - } - break; - case TCG_COND_LTU: - if (vece <= MO_32) { - fixup = NEED_UMAX | NEED_INV; - } else { - fixup = NEED_BIAS | NEED_SWAP; - } - break; - default: - g_assert_not_reached(); - } - - if (fixup & NEED_INV) { - cond = tcg_invert_cond(cond); - } - if (fixup & NEED_SWAP) { - t1 = v1, v1 = v2, v2 = t1; - cond = tcg_swap_cond(cond); - } - - t1 = t2 = NULL; - if (fixup & (NEED_UMIN | NEED_UMAX)) { - t1 = tcg_temp_new_vec(type); - if (fixup & NEED_UMIN) { - tcg_gen_umin_vec(vece, t1, v1, v2); - } else { - tcg_gen_umax_vec(vece, t1, v1, v2); - } - v2 = t1; - cond = TCG_COND_EQ; - } else if (fixup & NEED_BIAS) { - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1)); - tcg_gen_sub_vec(vece, t1, v1, t2); - tcg_gen_sub_vec(vece, t2, v2, t2); - v1 = t1; - v2 = t2; - cond = tcg_signed_cond(cond); - } - - tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT); - /* Expand directly; do not recurse. */ - vec_gen_4(INDEX_op_cmp_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); - - if (t1) { - tcg_temp_free_vec(t1); - if (t2) { - tcg_temp_free_vec(t2); - } - } - return fixup & NEED_INV; -} - -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { - tcg_gen_not_vec(vece, v0, v0); - } -} - -static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec c1, TCGv_vec c2, - TCGv_vec v3, TCGv_vec v4, TCGCond cond) -{ - TCGv_vec t = tcg_temp_new_vec(type); - - if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { - /* Invert the sense of the compare by swapping arguments. */ - TCGv_vec x; - x = v3, v3 = v4, v4 = x; - } - vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, vece, - tcgv_vec_arg(v0), tcgv_vec_arg(v4), - tcgv_vec_arg(v3), tcgv_vec_arg(t)); - tcg_temp_free_vec(t); -} - -void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, - TCGArg a0, ...) -{ - va_list va; - TCGArg a2; - TCGv_vec v0, v1, v2, v3, v4; - - va_start(va, a0); - v0 = temp_tcgv_vec(arg_temp(a0)); - v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - a2 = va_arg(va, TCGArg); - - switch (opc) { - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc, v0, v1, a2); - break; - - case INDEX_op_sari_vec: - expand_vec_sari(type, vece, v0, v1, a2); - break; - - case INDEX_op_rotli_vec: - expand_vec_rotli(type, vece, v0, v1, a2); - break; - - case INDEX_op_rotls_vec: - expand_vec_rotls(type, vece, v0, v1, temp_tcgv_i32(arg_temp(a2))); - break; - - case INDEX_op_rotlv_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_rotv(type, vece, v0, v1, v2, false); - break; - case INDEX_op_rotrv_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_rotv(type, vece, v0, v1, v2, true); - break; - - case INDEX_op_mul_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_mul(type, vece, v0, v1, v2); - break; - - case INDEX_op_cmp_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); - break; - - case INDEX_op_cmpsel_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); - break; - - default: - break; - } - - va_end(va); -} - -static const int tcg_target_callee_save_regs[] = { -#if TCG_TARGET_REG_BITS == 64 - TCG_REG_RBP, - TCG_REG_RBX, -#if defined(_WIN64) - TCG_REG_RDI, - TCG_REG_RSI, -#endif - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, /* Currently used for the global env. */ - TCG_REG_R15, -#else - TCG_REG_EBP, /* Currently used for the global env. */ - TCG_REG_EBX, - TCG_REG_ESI, - TCG_REG_EDI, -#endif -}; - -/* Compute frame size via macros, to share between tcg_target_qemu_prologue - and tcg_register_jit. */ - -#define PUSH_SIZE \ - ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ - * (TCG_TARGET_REG_BITS / 8)) - -#define FRAME_SIZE \ - ((PUSH_SIZE \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long) \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & ~(TCG_TARGET_STACK_ALIGN - 1)) - -/* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int i, stack_addend; - - /* TB prologue */ - - /* Reserve some stack space, also for TCG temps. */ - stack_addend = FRAME_SIZE - PUSH_SIZE; - tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - - /* Save all callee saved registers. */ - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { - tcg_out_push(s, tcg_target_callee_save_regs[i]); - } - -#if TCG_TARGET_REG_BITS == 32 - tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 - + stack_addend); -#else -# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS == 64 - if (guest_base) { - int seg = setup_guest_base_seg(); - if (seg != 0) { - x86_guest_base_seg = seg; - } else if (guest_base == (int32_t)guest_base) { - x86_guest_base_offset = guest_base; - } else { - /* Choose R12 because, as a base, it requires a SIB byte. */ - x86_guest_base_index = TCG_REG_R12; - tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); - tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); - } - } -# endif - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); -#endif - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); - - /* TB epilogue */ - tb_ret_addr = s->code_ptr; - - tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); - - if (have_avx2) { - tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); - } - for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { - tcg_out_pop(s, tcg_target_callee_save_regs[i]); - } - tcg_out_opc(s, OPC_RET, 0, 0, 0); -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - memset(p, 0x90, count); -} - -static void tcg_target_init(TCGContext *s) -{ -#ifdef CONFIG_CPUID_H - unsigned a, b, c, d, b7 = 0; - int max = __get_cpuid_max(0, 0); - - if (max >= 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b7, c, d); - have_bmi1 = (b7 & bit_BMI) != 0; - have_bmi2 = (b7 & bit_BMI2) != 0; - } - - if (max >= 1) { - __cpuid(1, a, b, c, d); -#ifndef have_cmov - /* For 32-bit, 99% certainty that we're running on hardware that - supports cmov, but we still need to check. In case cmov is not - available, we'll use a small forward branch. */ - have_cmov = (d & bit_CMOV) != 0; -#endif - - /* MOVBE is only available on Intel Atom and Haswell CPUs, so we - need to probe for it. */ - have_movbe = (c & bit_MOVBE) != 0; - have_popcnt = (c & bit_POPCNT) != 0; - - /* There are a number of things we must check before we can be - sure of not hitting invalid opcode. */ - if (c & bit_OSXSAVE) { - unsigned xcrl, xcrh; - /* The xgetbv instruction is not available to older versions of - * the assembler, so we encode the instruction manually. - */ - asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (0)); - if ((xcrl & 6) == 6) { - have_avx1 = (c & bit_AVX) != 0; - have_avx2 = (b7 & bit_AVX2) != 0; - } - } - } - - max = __get_cpuid_max(0x8000000, 0); - if (max >= 1) { - __cpuid(0x80000001, a, b, c, d); - /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs. */ - have_lzcnt = (c & bit_LZCNT) != 0; - } -#endif /* CONFIG_CPUID_H */ - - tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; - if (TCG_TARGET_REG_BITS == 64) { - tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; - } - if (have_avx1) { - tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; - tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; - } - if (have_avx2) { - tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; - } - - tcg_target_call_clobber_regs = ALL_VECTOR_REGS; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); - if (TCG_TARGET_REG_BITS == 64) { -#if !defined(_WIN64) - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); -#endif - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); - } - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[14]; -} DebugFrame; - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); - -#if !defined(__ELF__) - /* Host machine without ELF. */ -#elif TCG_TARGET_REG_BITS == 64 -#define ELF_HOST_MACHINE EM_X86_64 -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x78, /* sleb128 -8 */ - .h.cie.return_column = 16, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, 7, /* DW_CFA_def_cfa %rsp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x90, 1, /* DW_CFA_offset, %rip, -8 */ - /* The following ordering must match tcg_target_callee_save_regs. */ - 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ - 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ - 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ - 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ - 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ - 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ - } -}; -#else -#define ELF_HOST_MACHINE EM_386 -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 0x7c, /* sleb128 -4 */ - .h.cie.return_column = 8, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, 4, /* DW_CFA_def_cfa %esp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x88, 1, /* DW_CFA_offset, %eip, -4 */ - /* The following ordering must match tcg_target_callee_save_regs. */ - 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ - 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ - 0x86, 4, /* DW_CFA_offset, %esi, -16 */ - 0x87, 5, /* DW_CFA_offset, %edi, -20 */ - } -}; -#endif - -#if defined(ELF_HOST_MACHINE) -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} -#endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc new file mode 100644 index 0000000000..bd5b8e09a0 --- /dev/null +++ b/tcg/mips/tcg-target.c.inc @@ -0,0 +1,2711 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008-2009 Arnaud Patard + * Copyright (c) 2009 Aurelien Jarno + * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifdef HOST_WORDS_BIGENDIAN +# define MIPS_BE 1 +#else +# define MIPS_BE 0 +#endif + +#if TCG_TARGET_REG_BITS == 32 +# define LO_OFF (MIPS_BE * 4) +# define HI_OFF (4 - LO_OFF) +#else +/* To assert at compile-time that these values are never used + for TCG_TARGET_REG_BITS == 64. */ +int link_error(void); +# define LO_OFF link_error() +# define HI_OFF link_error() +#endif + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "zero", + "at", + "v0", + "v1", + "a0", + "a1", + "a2", + "a3", + "t0", + "t1", + "t2", + "t3", + "t4", + "t5", + "t6", + "t7", + "s0", + "s1", + "s2", + "s3", + "s4", + "s5", + "s6", + "s7", + "t8", + "t9", + "k0", + "k1", + "gp", + "sp", + "s8", + "ra", +}; +#endif + +#define TCG_TMP0 TCG_REG_AT +#define TCG_TMP1 TCG_REG_T9 +#define TCG_TMP2 TCG_REG_T8 +#define TCG_TMP3 TCG_REG_T7 + +#ifndef CONFIG_SOFTMMU +#define TCG_GUEST_BASE_REG TCG_REG_S1 +#endif + +/* check if we really need so many registers :P */ +static const int tcg_target_reg_alloc_order[] = { + /* Call saved registers. */ + TCG_REG_S0, + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + + /* Call clobbered registers. */ + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + TCG_REG_T7, + TCG_REG_T8, + TCG_REG_T9, + TCG_REG_V1, + TCG_REG_V0, + + /* Argument registers, opposite order of allocation. */ + TCG_REG_T3, + TCG_REG_T2, + TCG_REG_T1, + TCG_REG_T0, + TCG_REG_A3, + TCG_REG_A2, + TCG_REG_A1, + TCG_REG_A0, +}; + +static const TCGReg tcg_target_call_iarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, +#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, +#endif +}; + +static const TCGReg tcg_target_call_oarg_regs[2] = { + TCG_REG_V0, + TCG_REG_V1 +}; + +static tcg_insn_unit *tb_ret_addr; +static tcg_insn_unit *bswap32_addr; +static tcg_insn_unit *bswap32u_addr; +static tcg_insn_unit *bswap64_addr; + +static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + /* Let the compiler perform the right-shift as part of the arithmetic. */ + ptrdiff_t disp = target - (pc + 1); + tcg_debug_assert(disp == (int16_t)disp); + return disp & 0xffff; +} + +static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); +} + +static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); + return ((uintptr_t)target >> 2) & 0x3ffffff; +} + +static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_debug_assert(type == R_MIPS_PC16); + tcg_debug_assert(addend == 0); + reloc_pc16(code_ptr, (tcg_insn_unit *)value); + return true; +} + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ +#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ +#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ +#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ +#define TCG_CT_CONST_WSZ 0x2000 /* word size */ + +static inline bool is_p2m1(tcg_target_long val) +{ + return val && ((val + 1) & val) == 0; +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch(*ct_str++) { + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + break; + case 'L': /* qemu_ld input arg constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); +#if defined(CONFIG_SOFTMMU) + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); + } +#endif + break; + case 'S': /* qemu_st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); +#if defined(CONFIG_SOFTMMU) + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); + } else { + tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); + } +#endif + break; + case 'I': + ct->ct |= TCG_CT_CONST_U16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'K': + ct->ct |= TCG_CT_CONST_P2M1; + break; + case 'N': + ct->ct |= TCG_CT_CONST_N16; + break; + case 'W': + ct->ct |= TCG_CT_CONST_WSZ; + break; + case 'Z': + /* We are cheating a bit here, using the fact that the register + ZERO is also the register number 0. Hence there is no need + to check for const_args in each instruction. */ + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static inline int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct; + ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { + return 1; + } else if ((ct & TCG_CT_CONST_P2M1) + && use_mips32r2_instructions && is_p2m1(val)) { + return 1; + } else if ((ct & TCG_CT_CONST_WSZ) + && val == (type == TCG_TYPE_I32 ? 32 : 64)) { + return 1; + } + return 0; +} + +/* instruction opcodes */ +typedef enum { + OPC_J = 002 << 26, + OPC_JAL = 003 << 26, + OPC_BEQ = 004 << 26, + OPC_BNE = 005 << 26, + OPC_BLEZ = 006 << 26, + OPC_BGTZ = 007 << 26, + OPC_ADDIU = 011 << 26, + OPC_SLTI = 012 << 26, + OPC_SLTIU = 013 << 26, + OPC_ANDI = 014 << 26, + OPC_ORI = 015 << 26, + OPC_XORI = 016 << 26, + OPC_LUI = 017 << 26, + OPC_DADDIU = 031 << 26, + OPC_LB = 040 << 26, + OPC_LH = 041 << 26, + OPC_LW = 043 << 26, + OPC_LBU = 044 << 26, + OPC_LHU = 045 << 26, + OPC_LWU = 047 << 26, + OPC_SB = 050 << 26, + OPC_SH = 051 << 26, + OPC_SW = 053 << 26, + OPC_LD = 067 << 26, + OPC_SD = 077 << 26, + + OPC_SPECIAL = 000 << 26, + OPC_SLL = OPC_SPECIAL | 000, + OPC_SRL = OPC_SPECIAL | 002, + OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), + OPC_SRA = OPC_SPECIAL | 003, + OPC_SLLV = OPC_SPECIAL | 004, + OPC_SRLV = OPC_SPECIAL | 006, + OPC_ROTRV = OPC_SPECIAL | 006 | 0100, + OPC_SRAV = OPC_SPECIAL | 007, + OPC_JR_R5 = OPC_SPECIAL | 010, + OPC_JALR = OPC_SPECIAL | 011, + OPC_MOVZ = OPC_SPECIAL | 012, + OPC_MOVN = OPC_SPECIAL | 013, + OPC_SYNC = OPC_SPECIAL | 017, + OPC_MFHI = OPC_SPECIAL | 020, + OPC_MFLO = OPC_SPECIAL | 022, + OPC_DSLLV = OPC_SPECIAL | 024, + OPC_DSRLV = OPC_SPECIAL | 026, + OPC_DROTRV = OPC_SPECIAL | 026 | 0100, + OPC_DSRAV = OPC_SPECIAL | 027, + OPC_MULT = OPC_SPECIAL | 030, + OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, + OPC_MUH = OPC_SPECIAL | 030 | 0300, + OPC_MULTU = OPC_SPECIAL | 031, + OPC_MULU = OPC_SPECIAL | 031 | 0200, + OPC_MUHU = OPC_SPECIAL | 031 | 0300, + OPC_DIV = OPC_SPECIAL | 032, + OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, + OPC_MOD = OPC_SPECIAL | 032 | 0300, + OPC_DIVU = OPC_SPECIAL | 033, + OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, + OPC_MODU = OPC_SPECIAL | 033 | 0300, + OPC_DMULT = OPC_SPECIAL | 034, + OPC_DMUL = OPC_SPECIAL | 034 | 0200, + OPC_DMUH = OPC_SPECIAL | 034 | 0300, + OPC_DMULTU = OPC_SPECIAL | 035, + OPC_DMULU = OPC_SPECIAL | 035 | 0200, + OPC_DMUHU = OPC_SPECIAL | 035 | 0300, + OPC_DDIV = OPC_SPECIAL | 036, + OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, + OPC_DMOD = OPC_SPECIAL | 036 | 0300, + OPC_DDIVU = OPC_SPECIAL | 037, + OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, + OPC_DMODU = OPC_SPECIAL | 037 | 0300, + OPC_ADDU = OPC_SPECIAL | 041, + OPC_SUBU = OPC_SPECIAL | 043, + OPC_AND = OPC_SPECIAL | 044, + OPC_OR = OPC_SPECIAL | 045, + OPC_XOR = OPC_SPECIAL | 046, + OPC_NOR = OPC_SPECIAL | 047, + OPC_SLT = OPC_SPECIAL | 052, + OPC_SLTU = OPC_SPECIAL | 053, + OPC_DADDU = OPC_SPECIAL | 055, + OPC_DSUBU = OPC_SPECIAL | 057, + OPC_SELEQZ = OPC_SPECIAL | 065, + OPC_SELNEZ = OPC_SPECIAL | 067, + OPC_DSLL = OPC_SPECIAL | 070, + OPC_DSRL = OPC_SPECIAL | 072, + OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), + OPC_DSRA = OPC_SPECIAL | 073, + OPC_DSLL32 = OPC_SPECIAL | 074, + OPC_DSRL32 = OPC_SPECIAL | 076, + OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), + OPC_DSRA32 = OPC_SPECIAL | 077, + OPC_CLZ_R6 = OPC_SPECIAL | 0120, + OPC_DCLZ_R6 = OPC_SPECIAL | 0122, + + OPC_REGIMM = 001 << 26, + OPC_BLTZ = OPC_REGIMM | (000 << 16), + OPC_BGEZ = OPC_REGIMM | (001 << 16), + + OPC_SPECIAL2 = 034 << 26, + OPC_MUL_R5 = OPC_SPECIAL2 | 002, + OPC_CLZ = OPC_SPECIAL2 | 040, + OPC_DCLZ = OPC_SPECIAL2 | 044, + + OPC_SPECIAL3 = 037 << 26, + OPC_EXT = OPC_SPECIAL3 | 000, + OPC_DEXTM = OPC_SPECIAL3 | 001, + OPC_DEXTU = OPC_SPECIAL3 | 002, + OPC_DEXT = OPC_SPECIAL3 | 003, + OPC_INS = OPC_SPECIAL3 | 004, + OPC_DINSM = OPC_SPECIAL3 | 005, + OPC_DINSU = OPC_SPECIAL3 | 006, + OPC_DINS = OPC_SPECIAL3 | 007, + OPC_WSBH = OPC_SPECIAL3 | 00240, + OPC_DSBH = OPC_SPECIAL3 | 00244, + OPC_DSHD = OPC_SPECIAL3 | 00544, + OPC_SEB = OPC_SPECIAL3 | 02040, + OPC_SEH = OPC_SPECIAL3 | 03040, + + /* MIPS r6 doesn't have JR, JALR should be used instead */ + OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, + + /* + * MIPS r6 replaces MUL with an alternative encoding which is + * backwards-compatible at the assembly level. + */ + OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, + + /* MIPS r6 introduced names for weaker variants of SYNC. These are + backward compatible to previous architecture revisions. */ + OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, + OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, + OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, + OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, + OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, + + /* Aliases for convenience. */ + ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, + ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, + ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 + ? OPC_SRL : OPC_DSRL, +} MIPSInsn; + +/* + * Type reg + */ +static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rs, TCGReg rt) +{ + int32_t inst; + + inst = opc; + inst |= (rs & 0x1F) << 21; + inst |= (rt & 0x1F) << 16; + inst |= (rd & 0x1F) << 11; + tcg_out32(s, inst); +} + +/* + * Type immediate + */ +static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs, TCGArg imm) +{ + int32_t inst; + + inst = opc; + inst |= (rs & 0x1F) << 21; + inst |= (rt & 0x1F) << 16; + inst |= (imm & 0xffff); + tcg_out32(s, inst); +} + +/* + * Type bitfield + */ +static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, + TCGReg rs, int msb, int lsb) +{ + int32_t inst; + + inst = opc; + inst |= (rs & 0x1F) << 21; + inst |= (rt & 0x1F) << 16; + inst |= (msb & 0x1F) << 11; + inst |= (lsb & 0x1F) << 6; + tcg_out32(s, inst); +} + +static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, + MIPSInsn oph, TCGReg rt, TCGReg rs, + int msb, int lsb) +{ + if (lsb >= 32) { + opc = oph; + msb -= 32; + lsb -= 32; + } else if (msb >= 32) { + opc = opm; + msb -= 32; + } + tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); +} + +/* + * Type branch + */ +static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs) +{ + tcg_out_opc_imm(s, opc, rt, rs, 0); +} + +/* + * Type sa + */ +static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rt, TCGArg sa) +{ + int32_t inst; + + inst = opc; + inst |= (rt & 0x1F) << 16; + inst |= (rd & 0x1F) << 11; + inst |= (sa & 0x1F) << 6; + tcg_out32(s, inst); + +} + +static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, + TCGReg rd, TCGReg rt, TCGArg sa) +{ + int32_t inst; + + inst = (sa & 32 ? opc2 : opc1); + inst |= (rt & 0x1F) << 16; + inst |= (rd & 0x1F) << 11; + inst |= (sa & 0x1F) << 6; + tcg_out32(s, inst); +} + +/* + * Type jump. + * Returns true if the branch was in range and the insn was emitted. + */ +static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) +{ + uintptr_t dest = (uintptr_t)target; + uintptr_t from = (uintptr_t)s->code_ptr + 4; + int32_t inst; + + /* The pc-region branch happens within the 256MB region of + the delay slot (thus the +4). */ + if ((from ^ dest) & -(1 << 28)) { + return false; + } + tcg_debug_assert((dest & 3) == 0); + + inst = opc; + inst |= (dest >> 2) & 0x3ffffff; + tcg_out32(s, inst); + return true; +} + +static inline void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, 0); +} + +static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +{ + tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); +} + +static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +{ + tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); +} + +static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +{ + tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); +} + +static inline bool tcg_out_mov(TCGContext *s, TCGType type, + TCGReg ret, TCGReg arg) +{ + /* Simple reg-reg move, optimising out the 'do nothing' case */ + if (ret != arg) { + tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); + } + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + arg = (int32_t)arg; + } + if (arg == (int16_t)arg) { + tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); + return; + } + if (arg == (uint16_t)arg) { + tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); + return; + } + if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { + tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + } else { + tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); + if (arg & 0xffff0000ull) { + tcg_out_dsll(s, ret, ret, 16); + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); + tcg_out_dsll(s, ret, ret, 16); + } else { + tcg_out_dsll(s, ret, ret, 32); + } + } + if (arg & 0xffff) { + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); + } +} + +static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); + } else { + /* ret and arg can't be register at */ + if (ret == TCG_TMP0 || arg == TCG_TMP0) { + tcg_abort(); + } + + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); + tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); + } +} + +static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); + tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); + } else { + /* ret and arg can't be register at */ + if (ret == TCG_TMP0 || arg == TCG_TMP0) { + tcg_abort(); + } + + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); + tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); + } +} + +static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) +{ + bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); + tcg_debug_assert(ok); +} + +static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); + tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); + } else { + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot -- never omit the insn, like tcg_out_mov might. */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); + tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); + } +} + +static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); + tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); + tcg_out_dsrl(s, ret, ret, 32); + } else { + tcg_out_bswap_subr(s, bswap32u_addr); + /* delay slot -- never omit the insn, like tcg_out_mov might. */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); + tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); + } +} + +static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); + tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); + } else { + tcg_out_bswap_subr(s, bswap64_addr); + /* delay slot -- never omit the insn, like tcg_out_mov might. */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); + tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); + } +} + +static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); + } else { + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); + tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); + } +} + +static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); + } else { + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); + tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); + } +} + +static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + if (use_mips32r2_instructions) { + tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); + } else { + tcg_out_dsll(s, ret, arg, 32); + tcg_out_dsrl(s, ret, ret, 32); + } +} + +static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, + TCGReg addr, intptr_t ofs) +{ + int16_t lo = ofs; + if (ofs != lo) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); + if (addr != TCG_REG_ZERO) { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); + } + addr = TCG_TMP0; + } + tcg_out_opc_imm(s, opc, data, addr, lo); +} + +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + MIPSInsn opc = OPC_LD; + if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + opc = OPC_LW; + } + tcg_out_ldst(s, opc, arg, arg1, arg2); +} + +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + MIPSInsn opc = OPC_SD; + if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { + opc = OPC_SW; + } + tcg_out_ldst(s, opc, arg, arg1, arg2); +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (val == 0) { + tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); + return true; + } + return false; +} + +static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, + TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, + bool cbh, bool is_sub) +{ + TCGReg th = TCG_TMP1; + + /* If we have a negative constant such that negating it would + make the high part zero, we can (usually) eliminate one insn. */ + if (cbl && cbh && bh == -1 && bl != 0) { + bl = -bl; + bh = 0; + is_sub = !is_sub; + } + + /* By operating on the high part first, we get to use the final + carry operation to move back from the temporary. */ + if (!cbh) { + tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); + } else if (bh != 0 || ah == rl) { + tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); + } else { + th = ah; + } + + /* Note that tcg optimization should eliminate the bl == 0 case. */ + if (is_sub) { + if (cbl) { + tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); + tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); + } else { + tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); + tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); + } + tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); + } else { + if (cbl) { + tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); + tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); + } else if (rl == al && rl == bl) { + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); + tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); + } else { + tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); + tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); + } + tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); + } +} + +/* Bit 0 set if inversion required; bit 1 set if swapping required. */ +#define MIPS_CMP_INV 1 +#define MIPS_CMP_SWAP 2 + +static const uint8_t mips_cmp_map[16] = { + [TCG_COND_LT] = 0, + [TCG_COND_LTU] = 0, + [TCG_COND_GE] = MIPS_CMP_INV, + [TCG_COND_GEU] = MIPS_CMP_INV, + [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, + [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, + [TCG_COND_GT] = MIPS_CMP_SWAP, + [TCG_COND_GTU] = MIPS_CMP_SWAP, +}; + +static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, TCGReg arg2) +{ + MIPSInsn s_opc = OPC_SLTU; + int cmp_map; + + switch (cond) { + case TCG_COND_EQ: + if (arg2 != 0) { + tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); + arg1 = ret; + } + tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); + break; + + case TCG_COND_NE: + if (arg2 != 0) { + tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); + arg1 = ret; + } + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); + break; + + case TCG_COND_LT: + case TCG_COND_GE: + case TCG_COND_LE: + case TCG_COND_GT: + s_opc = OPC_SLT; + /* FALLTHRU */ + + case TCG_COND_LTU: + case TCG_COND_GEU: + case TCG_COND_LEU: + case TCG_COND_GTU: + cmp_map = mips_cmp_map[cond]; + if (cmp_map & MIPS_CMP_SWAP) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); + if (cmp_map & MIPS_CMP_INV) { + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + } + break; + + default: + tcg_abort(); + break; + } +} + +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, + TCGReg arg2, TCGLabel *l) +{ + static const MIPSInsn b_zero[16] = { + [TCG_COND_LT] = OPC_BLTZ, + [TCG_COND_GT] = OPC_BGTZ, + [TCG_COND_LE] = OPC_BLEZ, + [TCG_COND_GE] = OPC_BGEZ, + }; + + MIPSInsn s_opc = OPC_SLTU; + MIPSInsn b_opc; + int cmp_map; + + switch (cond) { + case TCG_COND_EQ: + b_opc = OPC_BEQ; + break; + case TCG_COND_NE: + b_opc = OPC_BNE; + break; + + case TCG_COND_LT: + case TCG_COND_GT: + case TCG_COND_LE: + case TCG_COND_GE: + if (arg2 == 0) { + b_opc = b_zero[cond]; + arg2 = arg1; + arg1 = 0; + break; + } + s_opc = OPC_SLT; + /* FALLTHRU */ + + case TCG_COND_LTU: + case TCG_COND_GTU: + case TCG_COND_LEU: + case TCG_COND_GEU: + cmp_map = mips_cmp_map[cond]; + if (cmp_map & MIPS_CMP_SWAP) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); + b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); + arg1 = TCG_TMP0; + arg2 = TCG_REG_ZERO; + break; + + default: + tcg_abort(); + break; + } + + tcg_out_opc_br(s, b_opc, arg1, arg2); + if (l->has_value) { + reloc_pc16(s->code_ptr - 1, l->u.value_ptr); + } else { + tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); + } + tcg_out_nop(s); +} + +static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, + TCGReg al, TCGReg ah, + TCGReg bl, TCGReg bh) +{ + /* Merge highpart comparison into AH. */ + if (bh != 0) { + if (ah != 0) { + tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); + ah = tmp0; + } else { + ah = bh; + } + } + /* Merge lowpart comparison into AL. */ + if (bl != 0) { + if (al != 0) { + tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); + al = tmp1; + } else { + al = bl; + } + } + /* Merge high and low part comparisons into AL. */ + if (ah != 0) { + if (al != 0) { + tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); + al = tmp0; + } else { + al = ah; + } + } + return al; +} + +static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) +{ + TCGReg tmp0 = TCG_TMP0; + TCGReg tmp1 = ret; + + tcg_debug_assert(ret != TCG_TMP0); + if (ret == ah || ret == bh) { + tcg_debug_assert(ret != TCG_TMP1); + tmp1 = TCG_TMP1; + } + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); + tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); + break; + + default: + tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); + tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); + tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); + tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); + tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); + break; + } +} + +static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, + TCGReg bl, TCGReg bh, TCGLabel *l) +{ + TCGCond b_cond = TCG_COND_NE; + TCGReg tmp = TCG_TMP1; + + /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. + With setcond, we emit between 3 and 10 insns and only 1 branch, + which ought to get better branch prediction. */ + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + b_cond = cond; + tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); + break; + + default: + /* Minimize code size by preferring a compare not requiring INV. */ + if (mips_cmp_map[cond] & MIPS_CMP_INV) { + cond = tcg_invert_cond(cond); + b_cond = TCG_COND_EQ; + } + tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); + break; + } + + tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); +} + +static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) +{ + bool eqz = false; + + /* If one of the values is zero, put it last to match SEL*Z instructions */ + if (use_mips32r6_instructions && v1 == 0) { + v1 = v2; + v2 = 0; + cond = tcg_invert_cond(cond); + } + + switch (cond) { + case TCG_COND_EQ: + eqz = true; + /* FALLTHRU */ + case TCG_COND_NE: + if (c2 != 0) { + tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); + c1 = TCG_TMP0; + } + break; + + default: + /* Minimize code size by preferring a compare not requiring INV. */ + if (mips_cmp_map[cond] & MIPS_CMP_INV) { + cond = tcg_invert_cond(cond); + eqz = true; + } + tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); + c1 = TCG_TMP0; + break; + } + + if (use_mips32r6_instructions) { + MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; + MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; + + if (v2 != 0) { + tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); + } + tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); + if (v2 != 0) { + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); + } + } else { + MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; + + tcg_out_opc_reg(s, m_opc, ret, v1, c1); + + /* This should be guaranteed via constraints */ + tcg_debug_assert(v2 == ret); + } +} + +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +{ + /* Note that the ABI requires the called function's address to be + loaded into T9, even if a direct branch is in range. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); + + /* But do try a direct branch, allowing the cpu better insn prefetch. */ + if (tail) { + if (!tcg_out_opc_jmp(s, OPC_J, arg)) { + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); + } + } else { + if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); + } + } +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +{ + tcg_out_call_int(s, arg, false); + tcg_out_nop(s); +} + +#if defined(CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL] = helper_le_ldsl_mmu, + [MO_BESL] = helper_be_ldsl_mmu, +#endif +}; + +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +/* Helper routines for marshalling helper function arguments into + * the correct registers and stack. + * I is where we want to put this argument, and is updated and returned + * for the next call. ARG is the argument itself. + * + * We provide routines for arguments which are: immediate, 32 bit + * value in register, 16 and 8 bit values in register (which must be zero + * extended before use) and 64 bit value in a lo:hi register pair. + */ + +static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) +{ + if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); + } else { + /* For N32 and N64, the initial offset is different. But there + we also have 8 argument register so we don't run out here. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); + } + return i + 1; +} + +static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) +{ + TCGReg tmp = TCG_TMP0; + if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tmp = tcg_target_call_iarg_regs[i]; + } + tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); + return tcg_out_call_iarg_reg(s, i, tmp); +} + +static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) +{ + TCGReg tmp = TCG_TMP0; + if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tmp = tcg_target_call_iarg_regs[i]; + } + tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); + return tcg_out_call_iarg_reg(s, i, tmp); +} + +static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) +{ + TCGReg tmp = TCG_TMP0; + if (arg == 0) { + tmp = TCG_REG_ZERO; + } else { + if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { + tmp = tcg_target_call_iarg_regs[i]; + } + tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); + } + return tcg_out_call_iarg_reg(s, i, tmp); +} + +static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + i = (i + 1) & ~1; + i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); + i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); + return i; +} + +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + +/* + * Perform the tlb comparison operation. + * The complete host address is placed in BASE. + * Clobbers TMP0, TMP1, TMP2, TMP3. + */ +static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, + TCGReg addrh, TCGMemOpIdx oi, + tcg_insn_unit *label_ptr[2], bool is_load) +{ + MemOp opc = get_memop(oi); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + int mem_index = get_mmuidx(oi); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); + int add_off = offsetof(CPUTLBEntry, addend); + int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + target_ulong mask; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); + + /* Extract the TLB index from the address into TMP3. */ + tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* We don't currently support unaligned accesses. + We could do so with mips32r6. */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + + /* Mask the page bits, keeping the alignment bits to compare against. */ + mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); + + /* Load the (low-half) tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); + } else { + tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD + : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), + TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); + /* No second compare is required here; + load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); + + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addrl); + addrl = base; + } + + label_ptr[0] = s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); + + /* Load and test the high half tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* delay slot */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + + label_ptr[1] = s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); + } + + /* delay slot */ + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); +} + +static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, + TCGType ext, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + void *raddr, tcg_insn_unit *label_ptr[2]) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0] = label_ptr[0]; + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + label->label_ptr[1] = label_ptr[1]; + } +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + TCGReg v0; + int i; + + /* resolve label address */ + reloc_pc16(l->label_ptr[0], s->code_ptr); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + reloc_pc16(l->label_ptr[1], s->code_ptr); + } + + i = 1; + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); + } else { + i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); + } + i = tcg_out_call_iarg_imm(s, i, oi); + i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); + /* delay slot */ + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + + v0 = l->datalo_reg; + if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { + /* We eliminated V0 from the possible output registers, so it + cannot be clobbered here. So we must move V1 first. */ + if (MIPS_BE) { + tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); + v0 = l->datahi_reg; + } else { + tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); + } + } + + tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); + reloc_pc16(s->code_ptr - 1, l->raddr); + + /* delay slot */ + if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { + /* we always sign-extend 32-bit loads */ + tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); + } else { + tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); + } + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + MemOp s_bits = opc & MO_SIZE; + int i; + + /* resolve label address */ + reloc_pc16(l->label_ptr[0], s->code_ptr); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + reloc_pc16(l->label_ptr[1], s->code_ptr); + } + + i = 1; + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); + } else { + i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); + } + switch (s_bits) { + case MO_8: + i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); + break; + case MO_16: + i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); + break; + case MO_32: + i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 32) { + i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); + } else { + i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); + } + break; + default: + tcg_abort(); + } + i = tcg_out_call_iarg_imm(s, i, oi); + + /* Tail call to the store helper. Thus force the return address + computation to take place in the return address register. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); + i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); + /* delay slot */ + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + return true; +} +#endif + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc, bool is_64) +{ + switch (opc & (MO_SSIZE | MO_BSWAP)) { + case MO_UB: + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + break; + case MO_UW | MO_BSWAP: + tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); + tcg_out_bswap16(s, lo, TCG_TMP1); + break; + case MO_UW: + tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + break; + case MO_SW | MO_BSWAP: + tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); + tcg_out_bswap16s(s, lo, TCG_TMP1); + break; + case MO_SW: + tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + break; + case MO_UL | MO_BSWAP: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + tcg_out_bswap32u(s, lo, lo); + } else { + tcg_out_bswap_subr(s, bswap32u_addr); + /* delay slot */ + tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); + tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); + } + break; + } + /* FALLTHRU */ + case MO_SL | MO_BSWAP: + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_bswap32(s, lo, lo); + } else { + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); + tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); + } + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + break; + } + /* FALLTHRU */ + case MO_SL: + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + break; + case MO_Q | MO_BSWAP: + if (TCG_TARGET_REG_BITS == 64) { + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + tcg_out_bswap64(s, lo, lo); + } else { + tcg_out_bswap_subr(s, bswap64_addr); + /* delay slot */ + tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); + tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); + } + } else if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); + } else { + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); + } + break; + case MO_Q: + /* Prefer to load from offset 0 first, but allow for overlap. */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + } else if (MIPS_BE ? hi != base : lo == base) { + tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); + tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); + } else { + tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); + tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); + } + break; + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[2]; +#endif + TCGReg base = TCG_REG_A0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + if (guest_base == 0 && data_regl != addr_regl) { + base = addr_regl; + } else if (guest_base == (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc) +{ + /* Don't clutter the code below with checks to avoid bswapping ZERO. */ + if ((lo | hi) == 0) { + opc &= ~MO_BSWAP; + } + + switch (opc & (MO_SIZE | MO_BSWAP)) { + case MO_8: + tcg_out_opc_imm(s, OPC_SB, lo, base, 0); + break; + + case MO_16 | MO_BSWAP: + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); + tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); + lo = TCG_TMP1; + /* FALLTHRU */ + case MO_16: + tcg_out_opc_imm(s, OPC_SH, lo, base, 0); + break; + + case MO_32 | MO_BSWAP: + tcg_out_bswap32(s, TCG_TMP3, lo); + lo = TCG_TMP3; + /* FALLTHRU */ + case MO_32: + tcg_out_opc_imm(s, OPC_SW, lo, base, 0); + break; + + case MO_64 | MO_BSWAP: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_bswap64(s, TCG_TMP3, lo); + tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); + } else if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); + tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); + } else { + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); + tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); + tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); + } + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_SD, lo, base, 0); + } else { + tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); + tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); + } + break; + + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[2]; +#endif + TCGReg base = TCG_REG_A0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + base = TCG_REG_A0; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + if (guest_base == 0) { + base = addr_regl; + } else if (guest_base == (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); +#endif +} + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + static const MIPSInsn sync[] = { + /* Note that SYNC_MB is a slightly weaker than SYNC 0, + as the former is an ordering barrier and the latter + is a completion barrier. */ + [0 ... TCG_MO_ALL] = OPC_SYNC_MB, + [TCG_MO_LD_LD] = OPC_SYNC_RMB, + [TCG_MO_ST_ST] = OPC_SYNC_WMB, + [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, + [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, + [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, + }; + tcg_out32(s, sync[a0 & TCG_MO_ALL]); +} + +static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, + int width, TCGReg a0, TCGReg a1, TCGArg a2) +{ + if (use_mips32r6_instructions) { + if (a2 == width) { + tcg_out_opc_reg(s, opcv6, a0, a1, 0); + } else { + tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); + tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); + } + } else { + if (a2 == width) { + tcg_out_opc_reg(s, opcv2, a0, a1, a1); + } else if (a0 == a2) { + tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); + tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); + } else if (a0 != a1) { + tcg_out_opc_reg(s, opcv2, a0, a1, a1); + tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); + } else { + tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); + tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); + tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); + } + } +} + +static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + MIPSInsn i1, i2; + TCGArg a0, a1, a2; + int c2; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c2 = const_args[2]; + + switch (opc) { + case INDEX_op_exit_tb: + { + TCGReg b0 = TCG_REG_ZERO; + + a0 = (intptr_t)a0; + if (a0 & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); + b0 = TCG_REG_V0; + } + if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, + (uintptr_t)tb_ret_addr); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); + } + tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); + } + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* direct jump method */ + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + /* Avoid clobbering the address during retranslation. */ + tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); + } else { + /* indirect jump method */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); + } + tcg_out_nop(s); + set_jmp_reset_offset(s, a0); + break; + case INDEX_op_goto_ptr: + /* jmp to the given host address (could be epilogue) */ + tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); + tcg_out_nop(s); + break; + case INDEX_op_br: + tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, + arg_label(a0)); + break; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + i1 = OPC_LBU; + goto do_ldst; + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + i1 = OPC_LB; + goto do_ldst; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + i1 = OPC_LHU; + goto do_ldst; + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + i1 = OPC_LH; + goto do_ldst; + case INDEX_op_ld_i32: + case INDEX_op_ld32s_i64: + i1 = OPC_LW; + goto do_ldst; + case INDEX_op_ld32u_i64: + i1 = OPC_LWU; + goto do_ldst; + case INDEX_op_ld_i64: + i1 = OPC_LD; + goto do_ldst; + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + i1 = OPC_SB; + goto do_ldst; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + i1 = OPC_SH; + goto do_ldst; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + i1 = OPC_SW; + goto do_ldst; + case INDEX_op_st_i64: + i1 = OPC_SD; + do_ldst: + tcg_out_ldst(s, i1, a0, a1, a2); + break; + + case INDEX_op_add_i32: + i1 = OPC_ADDU, i2 = OPC_ADDIU; + goto do_binary; + case INDEX_op_add_i64: + i1 = OPC_DADDU, i2 = OPC_DADDIU; + goto do_binary; + case INDEX_op_or_i32: + case INDEX_op_or_i64: + i1 = OPC_OR, i2 = OPC_ORI; + goto do_binary; + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + i1 = OPC_XOR, i2 = OPC_XORI; + do_binary: + if (c2) { + tcg_out_opc_imm(s, i2, a0, a1, a2); + break; + } + do_binaryv: + tcg_out_opc_reg(s, i1, a0, a1, a2); + break; + + case INDEX_op_sub_i32: + i1 = OPC_SUBU, i2 = OPC_ADDIU; + goto do_subtract; + case INDEX_op_sub_i64: + i1 = OPC_DSUBU, i2 = OPC_DADDIU; + do_subtract: + if (c2) { + tcg_out_opc_imm(s, i2, a0, a1, -a2); + break; + } + goto do_binaryv; + case INDEX_op_and_i32: + if (c2 && a2 != (uint16_t)a2) { + int msb = ctz32(~a2) - 1; + tcg_debug_assert(use_mips32r2_instructions); + tcg_debug_assert(is_p2m1(a2)); + tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); + break; + } + i1 = OPC_AND, i2 = OPC_ANDI; + goto do_binary; + case INDEX_op_and_i64: + if (c2 && a2 != (uint16_t)a2) { + int msb = ctz64(~a2) - 1; + tcg_debug_assert(use_mips32r2_instructions); + tcg_debug_assert(is_p2m1(a2)); + tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); + break; + } + i1 = OPC_AND, i2 = OPC_ANDI; + goto do_binary; + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + i1 = OPC_NOR; + goto do_binaryv; + + case INDEX_op_mul_i32: + if (use_mips32_instructions) { + tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); + break; + } + i1 = OPC_MULT, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_mulsh_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); + break; + } + i1 = OPC_MULT, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_muluh_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); + break; + } + i1 = OPC_MULTU, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_div_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); + break; + } + i1 = OPC_DIV, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_divu_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); + break; + } + i1 = OPC_DIVU, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_rem_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); + break; + } + i1 = OPC_DIV, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_remu_i32: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); + break; + } + i1 = OPC_DIVU, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_mul_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); + break; + } + i1 = OPC_DMULT, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_mulsh_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); + break; + } + i1 = OPC_DMULT, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_muluh_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); + break; + } + i1 = OPC_DMULTU, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_div_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); + break; + } + i1 = OPC_DDIV, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_divu_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); + break; + } + i1 = OPC_DDIVU, i2 = OPC_MFLO; + goto do_hilo1; + case INDEX_op_rem_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); + break; + } + i1 = OPC_DDIV, i2 = OPC_MFHI; + goto do_hilo1; + case INDEX_op_remu_i64: + if (use_mips32r6_instructions) { + tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); + break; + } + i1 = OPC_DDIVU, i2 = OPC_MFHI; + do_hilo1: + tcg_out_opc_reg(s, i1, 0, a1, a2); + tcg_out_opc_reg(s, i2, a0, 0, 0); + break; + + case INDEX_op_muls2_i32: + i1 = OPC_MULT; + goto do_hilo2; + case INDEX_op_mulu2_i32: + i1 = OPC_MULTU; + goto do_hilo2; + case INDEX_op_muls2_i64: + i1 = OPC_DMULT; + goto do_hilo2; + case INDEX_op_mulu2_i64: + i1 = OPC_DMULTU; + do_hilo2: + tcg_out_opc_reg(s, i1, 0, a2, args[3]); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); + tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); + break; + + case INDEX_op_not_i32: + case INDEX_op_not_i64: + i1 = OPC_NOR; + goto do_unary; + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + i1 = OPC_WSBH; + goto do_unary; + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + i1 = OPC_SEB; + goto do_unary; + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + i1 = OPC_SEH; + do_unary: + tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); + break; + + case INDEX_op_bswap32_i32: + tcg_out_bswap32(s, a0, a1); + break; + case INDEX_op_bswap32_i64: + tcg_out_bswap32u(s, a0, a1); + break; + case INDEX_op_bswap64_i64: + tcg_out_bswap64(s, a0, a1); + break; + case INDEX_op_extrh_i64_i32: + tcg_out_dsra(s, a0, a1, 32); + break; + case INDEX_op_ext32s_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extrl_i64_i32: + tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); + break; + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + tcg_out_ext32u(s, a0, a1); + break; + + case INDEX_op_sar_i32: + i1 = OPC_SRAV, i2 = OPC_SRA; + goto do_shift; + case INDEX_op_shl_i32: + i1 = OPC_SLLV, i2 = OPC_SLL; + goto do_shift; + case INDEX_op_shr_i32: + i1 = OPC_SRLV, i2 = OPC_SRL; + goto do_shift; + case INDEX_op_rotr_i32: + i1 = OPC_ROTRV, i2 = OPC_ROTR; + do_shift: + if (c2) { + tcg_out_opc_sa(s, i2, a0, a1, a2); + break; + } + do_shiftv: + tcg_out_opc_reg(s, i1, a0, a2, a1); + break; + case INDEX_op_rotl_i32: + if (c2) { + tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); + } else { + tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); + tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); + } + break; + case INDEX_op_sar_i64: + if (c2) { + tcg_out_dsra(s, a0, a1, a2); + break; + } + i1 = OPC_DSRAV; + goto do_shiftv; + case INDEX_op_shl_i64: + if (c2) { + tcg_out_dsll(s, a0, a1, a2); + break; + } + i1 = OPC_DSLLV; + goto do_shiftv; + case INDEX_op_shr_i64: + if (c2) { + tcg_out_dsrl(s, a0, a1, a2); + break; + } + i1 = OPC_DSRLV; + goto do_shiftv; + case INDEX_op_rotr_i64: + if (c2) { + tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); + break; + } + i1 = OPC_DROTRV; + goto do_shiftv; + case INDEX_op_rotl_i64: + if (c2) { + tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); + } else { + tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); + tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); + } + break; + + case INDEX_op_clz_i32: + tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); + break; + case INDEX_op_clz_i64: + tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); + break; + + case INDEX_op_deposit_i32: + tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); + break; + case INDEX_op_deposit_i64: + tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, + args[3] + args[4] - 1, args[3]); + break; + case INDEX_op_extract_i32: + tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); + break; + case INDEX_op_extract_i64: + tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, + args[3] - 1, a2); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); + break; + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); + break; + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tcg_out_setcond(s, args[3], a0, a1, a2); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, true); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, false); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, true); + break; + + case INDEX_op_add2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], false); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], true); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; + static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; + static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; + static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; + static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; + static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; + static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; + static const TCGTargetOpDef SZ_SZ_S + = { .args_ct_str = { "SZ", "SZ", "S" } }; + static const TCGTargetOpDef SZ_SZ_S_S + = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; + static const TCGTargetOpDef r_rZ_rN + = { .args_ct_str = { "r", "rZ", "rN" } }; + static const TCGTargetOpDef r_rZ_rZ + = { .args_ct_str = { "r", "rZ", "rZ" } }; + static const TCGTargetOpDef r_r_rIK + = { .args_ct_str = { "r", "r", "rIK" } }; + static const TCGTargetOpDef r_r_rWZ + = { .args_ct_str = { "r", "r", "rWZ" } }; + static const TCGTargetOpDef r_r_r_r + = { .args_ct_str = { "r", "r", "r", "r" } }; + static const TCGTargetOpDef r_r_L_L + = { .args_ct_str = { "r", "r", "L", "L" } }; + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "0", "rZ" } }; + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; + static const TCGTargetOpDef movc_r6 + = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef add2 + = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; + static const TCGTargetOpDef br2 + = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef setc2 + = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_not_i32: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_extract_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i64: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_rJ; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_rZ_rN; + case INDEX_op_mul_i32: + case INDEX_op_mulsh_i32: + case INDEX_op_muluh_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + case INDEX_op_nor_i32: + case INDEX_op_setcond_i32: + case INDEX_op_mul_i64: + case INDEX_op_mulsh_i64: + case INDEX_op_muluh_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + case INDEX_op_nor_i64: + case INDEX_op_setcond_i64: + return &r_rZ_rZ; + case INDEX_op_muls2_i32: + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i64: + case INDEX_op_mulu2_i64: + return &r_r_r_r; + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return &r_r_rIK; + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + return &r_r_rI; + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotr_i32: + case INDEX_op_rotl_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotr_i64: + case INDEX_op_rotl_i64: + return &r_r_ri; + case INDEX_op_clz_i32: + case INDEX_op_clz_i64: + return &r_r_rWZ; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return &dep; + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &rZ_rZ; + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + return use_mips32r6_instructions ? &movc_r6 : &movc; + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return &add2; + case INDEX_op_setcond2_i32: + return &setc2; + case INDEX_op_brcond2_i32: + return &br2; + + case INDEX_op_qemu_ld_i32: + return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 + ? &r_L : &r_L_L); + case INDEX_op_qemu_st_i32: + return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 + ? &SZ_S : &SZ_S_S); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? &r_L + : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? &SZ_S + : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); + + default: + return NULL; + } +} + +static const int tcg_target_callee_save_regs[] = { + TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_RA, /* should be last for ABI compliance */ +}; + +/* The Linux kernel doesn't provide any information about the available + instruction set. Probe it using a signal handler. */ + + +#ifndef use_movnz_instructions +bool use_movnz_instructions = false; +#endif + +#ifndef use_mips32_instructions +bool use_mips32_instructions = false; +#endif + +#ifndef use_mips32r2_instructions +bool use_mips32r2_instructions = false; +#endif + +static volatile sig_atomic_t got_sigill; + +static void sigill_handler(int signo, siginfo_t *si, void *data) +{ + /* Skip the faulty instruction */ + ucontext_t *uc = (ucontext_t *)data; + uc->uc_mcontext.pc += 4; + + got_sigill = 1; +} + +static void tcg_target_detect_isa(void) +{ + struct sigaction sa_old, sa_new; + + memset(&sa_new, 0, sizeof(sa_new)); + sa_new.sa_flags = SA_SIGINFO; + sa_new.sa_sigaction = sigill_handler; + sigaction(SIGILL, &sa_new, &sa_old); + + /* Probe for movn/movz, necessary to implement movcond. */ +#ifndef use_movnz_instructions + got_sigill = 0; + asm volatile(".set push\n" + ".set mips32\n" + "movn $zero, $zero, $zero\n" + "movz $zero, $zero, $zero\n" + ".set pop\n" + : : : ); + use_movnz_instructions = !got_sigill; +#endif + + /* Probe for MIPS32 instructions. As no subsetting is allowed + by the specification, it is only necessary to probe for one + of the instructions. */ +#ifndef use_mips32_instructions + got_sigill = 0; + asm volatile(".set push\n" + ".set mips32\n" + "mul $zero, $zero\n" + ".set pop\n" + : : : ); + use_mips32_instructions = !got_sigill; +#endif + + /* Probe for MIPS32r2 instructions if MIPS32 instructions are + available. As no subsetting is allowed by the specification, + it is only necessary to probe for one of the instructions. */ +#ifndef use_mips32r2_instructions + if (use_mips32_instructions) { + got_sigill = 0; + asm volatile(".set push\n" + ".set mips32r2\n" + "seb $zero, $zero\n" + ".set pop\n" + : : : ); + use_mips32r2_instructions = !got_sigill; + } +#endif + + sigaction(SIGILL, &sa_old, NULL); +} + +static tcg_insn_unit *align_code_ptr(TCGContext *s) +{ + uintptr_t p = (uintptr_t)s->code_ptr; + if (p & 15) { + p = (p + 15) & -16; + s->code_ptr = (void *)p; + } + return s->code_ptr; +} + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) + +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); + + /* TB prologue */ + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + +#ifndef CONFIG_SOFTMMU + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } +#endif + + /* Call generated code */ + tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); + /* delay slot */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + + /* + * Return path for goto_ptr. Set return value to 0, a-la exit_tb, + * and fall through to the rest of the epilogue. + */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); + /* delay slot */ + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); + + if (use_mips32r2_instructions) { + return; + } + + /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; + clobbers TCG_TMP1, TCG_TMP2. */ + + /* + * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. + */ + bswap32_addr = align_code_ptr(s); + /* t3 = (ssss)d000 */ + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); + /* t1 = 000a */ + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); + /* t2 = 00c0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); + /* t3 = d00a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + /* t1 = 0abc */ + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); + /* t2 = 0c00 */ + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); + /* t1 = 00b0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); + /* t3 = dc0a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); + /* t3 = dcba -- delay slot */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + if (TCG_TARGET_REG_BITS == 32) { + return; + } + + /* + * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. + */ + bswap32u_addr = align_code_ptr(s); + /* t1 = (0000)000d */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); + /* t3 = 000a */ + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); + /* t1 = (0000)d000 */ + tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); + /* t2 = 00c0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); + /* t3 = d00a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + /* t1 = 0abc */ + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); + /* t2 = 0c00 */ + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); + /* t1 = 00b0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); + /* t3 = dc0a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); + /* t3 = dcba -- delay slot */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* + * bswap64 -- 64-bit swap. a0 = abcdefgh + */ + bswap64_addr = align_code_ptr(s); + /* t3 = h0000000 */ + tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); + /* t1 = 0000000a */ + tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); + + /* t2 = 000000g0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); + /* t3 = h000000a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + /* t1 = 00000abc */ + tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); + /* t2 = 0g000000 */ + tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); + /* t1 = 000000b0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); + + /* t3 = hg00000a */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); + /* t2 = 0000abcd */ + tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); + /* t3 = hg0000ba */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* t1 = 000000c0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); + /* t2 = 0000000d */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); + /* t1 = 00000c00 */ + tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); + /* t2 = 0000d000 */ + tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); + + /* t3 = hg000cba */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); + /* t1 = 00abcdef */ + tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); + /* t3 = hg00dcba */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); + + /* t2 = 0000000f */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); + /* t1 = 000000e0 */ + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); + /* t2 = 00f00000 */ + tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); + /* t1 = 000e0000 */ + tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); + + /* t3 = hgf0dcba */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); + /* t3 = hgfedcba -- delay slot */ + tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); +} + +static void tcg_target_init(TCGContext *s) +{ + tcg_target_detect_isa(); + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + if (TCG_TARGET_REG_BITS == 64) { + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + } + + tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ + tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ + tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ + tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ + tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); + flush_icache_range(jmp_addr, jmp_addr + 4); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_MIPS +/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, + which is good because they're really quite complicated for MIPS. */ + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.return_column = TCG_REG_RA, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ + 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ + 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ + 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ + 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ + 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ + 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ + 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ + 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c deleted file mode 100644 index 4d32ebc1df..0000000000 --- a/tcg/mips/tcg-target.inc.c +++ /dev/null @@ -1,2711 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008-2009 Arnaud Patard - * Copyright (c) 2009 Aurelien Jarno - * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifdef HOST_WORDS_BIGENDIAN -# define MIPS_BE 1 -#else -# define MIPS_BE 0 -#endif - -#if TCG_TARGET_REG_BITS == 32 -# define LO_OFF (MIPS_BE * 4) -# define HI_OFF (4 - LO_OFF) -#else -/* To assert at compile-time that these values are never used - for TCG_TARGET_REG_BITS == 64. */ -int link_error(void); -# define LO_OFF link_error() -# define HI_OFF link_error() -#endif - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "zero", - "at", - "v0", - "v1", - "a0", - "a1", - "a2", - "a3", - "t0", - "t1", - "t2", - "t3", - "t4", - "t5", - "t6", - "t7", - "s0", - "s1", - "s2", - "s3", - "s4", - "s5", - "s6", - "s7", - "t8", - "t9", - "k0", - "k1", - "gp", - "sp", - "s8", - "ra", -}; -#endif - -#define TCG_TMP0 TCG_REG_AT -#define TCG_TMP1 TCG_REG_T9 -#define TCG_TMP2 TCG_REG_T8 -#define TCG_TMP3 TCG_REG_T7 - -#ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG TCG_REG_S1 -#endif - -/* check if we really need so many registers :P */ -static const int tcg_target_reg_alloc_order[] = { - /* Call saved registers. */ - TCG_REG_S0, - TCG_REG_S1, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - - /* Call clobbered registers. */ - TCG_REG_T4, - TCG_REG_T5, - TCG_REG_T6, - TCG_REG_T7, - TCG_REG_T8, - TCG_REG_T9, - TCG_REG_V1, - TCG_REG_V0, - - /* Argument registers, opposite order of allocation. */ - TCG_REG_T3, - TCG_REG_T2, - TCG_REG_T1, - TCG_REG_T0, - TCG_REG_A3, - TCG_REG_A2, - TCG_REG_A1, - TCG_REG_A0, -}; - -static const TCGReg tcg_target_call_iarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, - TCG_REG_A2, - TCG_REG_A3, -#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_T3, -#endif -}; - -static const TCGReg tcg_target_call_oarg_regs[2] = { - TCG_REG_V0, - TCG_REG_V1 -}; - -static tcg_insn_unit *tb_ret_addr; -static tcg_insn_unit *bswap32_addr; -static tcg_insn_unit *bswap32u_addr; -static tcg_insn_unit *bswap64_addr; - -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - /* Let the compiler perform the right-shift as part of the arithmetic. */ - ptrdiff_t disp = target - (pc + 1); - tcg_debug_assert(disp == (int16_t)disp); - return disp & 0xffff; -} - -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); -} - -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); - return ((uintptr_t)target >> 2) & 0x3ffffff; -} - -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); -} - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_debug_assert(type == R_MIPS_PC16); - tcg_debug_assert(addend == 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); - return true; -} - -#define TCG_CT_CONST_ZERO 0x100 -#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ -#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ -#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ -#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ -#define TCG_CT_CONST_WSZ 0x2000 /* word size */ - -static inline bool is_p2m1(tcg_target_long val) -{ - return val && ((val + 1) & val) == 0; -} - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'r': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - break; - case 'L': /* qemu_ld input arg constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); - } -#endif - break; - case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); -#if defined(CONFIG_SOFTMMU) - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); - } else { - tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); - } -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_U16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'K': - ct->ct |= TCG_CT_CONST_P2M1; - break; - case 'N': - ct->ct |= TCG_CT_CONST_N16; - break; - case 'W': - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'Z': - /* We are cheating a bit here, using the fact that the register - ZERO is also the register number 0. Hence there is no need - to check for const_args in each instruction. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct; - ct = arg_ct->ct; - if (ct & TCG_CT_CONST) { - return 1; - } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { - return 1; - } else if ((ct & TCG_CT_CONST_P2M1) - && use_mips32r2_instructions && is_p2m1(val)) { - return 1; - } else if ((ct & TCG_CT_CONST_WSZ) - && val == (type == TCG_TYPE_I32 ? 32 : 64)) { - return 1; - } - return 0; -} - -/* instruction opcodes */ -typedef enum { - OPC_J = 002 << 26, - OPC_JAL = 003 << 26, - OPC_BEQ = 004 << 26, - OPC_BNE = 005 << 26, - OPC_BLEZ = 006 << 26, - OPC_BGTZ = 007 << 26, - OPC_ADDIU = 011 << 26, - OPC_SLTI = 012 << 26, - OPC_SLTIU = 013 << 26, - OPC_ANDI = 014 << 26, - OPC_ORI = 015 << 26, - OPC_XORI = 016 << 26, - OPC_LUI = 017 << 26, - OPC_DADDIU = 031 << 26, - OPC_LB = 040 << 26, - OPC_LH = 041 << 26, - OPC_LW = 043 << 26, - OPC_LBU = 044 << 26, - OPC_LHU = 045 << 26, - OPC_LWU = 047 << 26, - OPC_SB = 050 << 26, - OPC_SH = 051 << 26, - OPC_SW = 053 << 26, - OPC_LD = 067 << 26, - OPC_SD = 077 << 26, - - OPC_SPECIAL = 000 << 26, - OPC_SLL = OPC_SPECIAL | 000, - OPC_SRL = OPC_SPECIAL | 002, - OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), - OPC_SRA = OPC_SPECIAL | 003, - OPC_SLLV = OPC_SPECIAL | 004, - OPC_SRLV = OPC_SPECIAL | 006, - OPC_ROTRV = OPC_SPECIAL | 006 | 0100, - OPC_SRAV = OPC_SPECIAL | 007, - OPC_JR_R5 = OPC_SPECIAL | 010, - OPC_JALR = OPC_SPECIAL | 011, - OPC_MOVZ = OPC_SPECIAL | 012, - OPC_MOVN = OPC_SPECIAL | 013, - OPC_SYNC = OPC_SPECIAL | 017, - OPC_MFHI = OPC_SPECIAL | 020, - OPC_MFLO = OPC_SPECIAL | 022, - OPC_DSLLV = OPC_SPECIAL | 024, - OPC_DSRLV = OPC_SPECIAL | 026, - OPC_DROTRV = OPC_SPECIAL | 026 | 0100, - OPC_DSRAV = OPC_SPECIAL | 027, - OPC_MULT = OPC_SPECIAL | 030, - OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, - OPC_MUH = OPC_SPECIAL | 030 | 0300, - OPC_MULTU = OPC_SPECIAL | 031, - OPC_MULU = OPC_SPECIAL | 031 | 0200, - OPC_MUHU = OPC_SPECIAL | 031 | 0300, - OPC_DIV = OPC_SPECIAL | 032, - OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, - OPC_MOD = OPC_SPECIAL | 032 | 0300, - OPC_DIVU = OPC_SPECIAL | 033, - OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, - OPC_MODU = OPC_SPECIAL | 033 | 0300, - OPC_DMULT = OPC_SPECIAL | 034, - OPC_DMUL = OPC_SPECIAL | 034 | 0200, - OPC_DMUH = OPC_SPECIAL | 034 | 0300, - OPC_DMULTU = OPC_SPECIAL | 035, - OPC_DMULU = OPC_SPECIAL | 035 | 0200, - OPC_DMUHU = OPC_SPECIAL | 035 | 0300, - OPC_DDIV = OPC_SPECIAL | 036, - OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, - OPC_DMOD = OPC_SPECIAL | 036 | 0300, - OPC_DDIVU = OPC_SPECIAL | 037, - OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, - OPC_DMODU = OPC_SPECIAL | 037 | 0300, - OPC_ADDU = OPC_SPECIAL | 041, - OPC_SUBU = OPC_SPECIAL | 043, - OPC_AND = OPC_SPECIAL | 044, - OPC_OR = OPC_SPECIAL | 045, - OPC_XOR = OPC_SPECIAL | 046, - OPC_NOR = OPC_SPECIAL | 047, - OPC_SLT = OPC_SPECIAL | 052, - OPC_SLTU = OPC_SPECIAL | 053, - OPC_DADDU = OPC_SPECIAL | 055, - OPC_DSUBU = OPC_SPECIAL | 057, - OPC_SELEQZ = OPC_SPECIAL | 065, - OPC_SELNEZ = OPC_SPECIAL | 067, - OPC_DSLL = OPC_SPECIAL | 070, - OPC_DSRL = OPC_SPECIAL | 072, - OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), - OPC_DSRA = OPC_SPECIAL | 073, - OPC_DSLL32 = OPC_SPECIAL | 074, - OPC_DSRL32 = OPC_SPECIAL | 076, - OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), - OPC_DSRA32 = OPC_SPECIAL | 077, - OPC_CLZ_R6 = OPC_SPECIAL | 0120, - OPC_DCLZ_R6 = OPC_SPECIAL | 0122, - - OPC_REGIMM = 001 << 26, - OPC_BLTZ = OPC_REGIMM | (000 << 16), - OPC_BGEZ = OPC_REGIMM | (001 << 16), - - OPC_SPECIAL2 = 034 << 26, - OPC_MUL_R5 = OPC_SPECIAL2 | 002, - OPC_CLZ = OPC_SPECIAL2 | 040, - OPC_DCLZ = OPC_SPECIAL2 | 044, - - OPC_SPECIAL3 = 037 << 26, - OPC_EXT = OPC_SPECIAL3 | 000, - OPC_DEXTM = OPC_SPECIAL3 | 001, - OPC_DEXTU = OPC_SPECIAL3 | 002, - OPC_DEXT = OPC_SPECIAL3 | 003, - OPC_INS = OPC_SPECIAL3 | 004, - OPC_DINSM = OPC_SPECIAL3 | 005, - OPC_DINSU = OPC_SPECIAL3 | 006, - OPC_DINS = OPC_SPECIAL3 | 007, - OPC_WSBH = OPC_SPECIAL3 | 00240, - OPC_DSBH = OPC_SPECIAL3 | 00244, - OPC_DSHD = OPC_SPECIAL3 | 00544, - OPC_SEB = OPC_SPECIAL3 | 02040, - OPC_SEH = OPC_SPECIAL3 | 03040, - - /* MIPS r6 doesn't have JR, JALR should be used instead */ - OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, - - /* - * MIPS r6 replaces MUL with an alternative encoding which is - * backwards-compatible at the assembly level. - */ - OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, - - /* MIPS r6 introduced names for weaker variants of SYNC. These are - backward compatible to previous architecture revisions. */ - OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, - OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, - OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, - OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, - OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, - - /* Aliases for convenience. */ - ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, - ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, - ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 - ? OPC_SRL : OPC_DSRL, -} MIPSInsn; - -/* - * Type reg - */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rs, TCGReg rt) -{ - int32_t inst; - - inst = opc; - inst |= (rs & 0x1F) << 21; - inst |= (rt & 0x1F) << 16; - inst |= (rd & 0x1F) << 11; - tcg_out32(s, inst); -} - -/* - * Type immediate - */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs, TCGArg imm) -{ - int32_t inst; - - inst = opc; - inst |= (rs & 0x1F) << 21; - inst |= (rt & 0x1F) << 16; - inst |= (imm & 0xffff); - tcg_out32(s, inst); -} - -/* - * Type bitfield - */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, - TCGReg rs, int msb, int lsb) -{ - int32_t inst; - - inst = opc; - inst |= (rs & 0x1F) << 21; - inst |= (rt & 0x1F) << 16; - inst |= (msb & 0x1F) << 11; - inst |= (lsb & 0x1F) << 6; - tcg_out32(s, inst); -} - -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, - MIPSInsn oph, TCGReg rt, TCGReg rs, - int msb, int lsb) -{ - if (lsb >= 32) { - opc = oph; - msb -= 32; - lsb -= 32; - } else if (msb >= 32) { - opc = opm; - msb -= 32; - } - tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); -} - -/* - * Type branch - */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs) -{ - tcg_out_opc_imm(s, opc, rt, rs, 0); -} - -/* - * Type sa - */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rt, TCGArg sa) -{ - int32_t inst; - - inst = opc; - inst |= (rt & 0x1F) << 16; - inst |= (rd & 0x1F) << 11; - inst |= (sa & 0x1F) << 6; - tcg_out32(s, inst); - -} - -static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, - TCGReg rd, TCGReg rt, TCGArg sa) -{ - int32_t inst; - - inst = (sa & 32 ? opc2 : opc1); - inst |= (rt & 0x1F) << 16; - inst |= (rd & 0x1F) << 11; - inst |= (sa & 0x1F) << 6; - tcg_out32(s, inst); -} - -/* - * Type jump. - * Returns true if the branch was in range and the insn was emitted. - */ -static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) -{ - uintptr_t dest = (uintptr_t)target; - uintptr_t from = (uintptr_t)s->code_ptr + 4; - int32_t inst; - - /* The pc-region branch happens within the 256MB region of - the delay slot (thus the +4). */ - if ((from ^ dest) & -(1 << 28)) { - return false; - } - tcg_debug_assert((dest & 3) == 0); - - inst = opc; - inst |= (dest >> 2) & 0x3ffffff; - tcg_out32(s, inst); - return true; -} - -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, 0); -} - -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) -{ - tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); -} - -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) -{ - tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); -} - -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) -{ - tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); -} - -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) -{ - /* Simple reg-reg move, optimising out the 'do nothing' case */ - if (ret != arg) { - tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); - } - return true; -} - -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - arg = (int32_t)arg; - } - if (arg == (int16_t)arg) { - tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); - return; - } - if (arg == (uint16_t)arg) { - tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); - return; - } - if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { - tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); - } else { - tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); - if (arg & 0xffff0000ull) { - tcg_out_dsll(s, ret, ret, 16); - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); - tcg_out_dsll(s, ret, ret, 16); - } else { - tcg_out_dsll(s, ret, ret, 32); - } - } - if (arg & 0xffff) { - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); - } -} - -static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); - } else { - /* ret and arg can't be register at */ - if (ret == TCG_TMP0 || arg == TCG_TMP0) { - tcg_abort(); - } - - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); - tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); - tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); - } -} - -static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); - tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); - } else { - /* ret and arg can't be register at */ - if (ret == TCG_TMP0 || arg == TCG_TMP0) { - tcg_abort(); - } - - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); - } -} - -static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) -{ - bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); - tcg_debug_assert(ok); -} - -static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); - tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot -- never omit the insn, like tcg_out_mov might. */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); - tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); - } -} - -static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); - tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); - tcg_out_dsrl(s, ret, ret, 32); - } else { - tcg_out_bswap_subr(s, bswap32u_addr); - /* delay slot -- never omit the insn, like tcg_out_mov might. */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); - tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); - } -} - -static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); - tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); - } else { - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot -- never omit the insn, like tcg_out_mov might. */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); - tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); - } -} - -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); - } -} - -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - } -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); - } else { - tcg_out_dsll(s, ret, arg, 32); - tcg_out_dsrl(s, ret, ret, 32); - } -} - -static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, - TCGReg addr, intptr_t ofs) -{ - int16_t lo = ofs; - if (ofs != lo) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); - if (addr != TCG_REG_ZERO) { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); - } - addr = TCG_TMP0; - } - tcg_out_opc_imm(s, opc, data, addr, lo); -} - -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - MIPSInsn opc = OPC_LD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { - opc = OPC_LW; - } - tcg_out_ldst(s, opc, arg, arg1, arg2); -} - -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - MIPSInsn opc = OPC_SD; - if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { - opc = OPC_SW; - } - tcg_out_ldst(s, opc, arg, arg1, arg2); -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - if (val == 0) { - tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); - return true; - } - return false; -} - -static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, - TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, - bool cbh, bool is_sub) -{ - TCGReg th = TCG_TMP1; - - /* If we have a negative constant such that negating it would - make the high part zero, we can (usually) eliminate one insn. */ - if (cbl && cbh && bh == -1 && bl != 0) { - bl = -bl; - bh = 0; - is_sub = !is_sub; - } - - /* By operating on the high part first, we get to use the final - carry operation to move back from the temporary. */ - if (!cbh) { - tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); - } else if (bh != 0 || ah == rl) { - tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); - } else { - th = ah; - } - - /* Note that tcg optimization should eliminate the bl == 0 case. */ - if (is_sub) { - if (cbl) { - tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); - tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); - } else { - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); - } - tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); - } else { - if (cbl) { - tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); - tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); - } else if (rl == al && rl == bl) { - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); - tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); - } else { - tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); - } - tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); - } -} - -/* Bit 0 set if inversion required; bit 1 set if swapping required. */ -#define MIPS_CMP_INV 1 -#define MIPS_CMP_SWAP 2 - -static const uint8_t mips_cmp_map[16] = { - [TCG_COND_LT] = 0, - [TCG_COND_LTU] = 0, - [TCG_COND_GE] = MIPS_CMP_INV, - [TCG_COND_GEU] = MIPS_CMP_INV, - [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, - [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, - [TCG_COND_GT] = MIPS_CMP_SWAP, - [TCG_COND_GTU] = MIPS_CMP_SWAP, -}; - -static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg arg1, TCGReg arg2) -{ - MIPSInsn s_opc = OPC_SLTU; - int cmp_map; - - switch (cond) { - case TCG_COND_EQ: - if (arg2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); - arg1 = ret; - } - tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); - break; - - case TCG_COND_NE: - if (arg2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); - arg1 = ret; - } - tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); - break; - - case TCG_COND_LT: - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GT: - s_opc = OPC_SLT; - /* FALLTHRU */ - - case TCG_COND_LTU: - case TCG_COND_GEU: - case TCG_COND_LEU: - case TCG_COND_GTU: - cmp_map = mips_cmp_map[cond]; - if (cmp_map & MIPS_CMP_SWAP) { - TCGReg t = arg1; - arg1 = arg2; - arg2 = t; - } - tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); - if (cmp_map & MIPS_CMP_INV) { - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - } - break; - - default: - tcg_abort(); - break; - } -} - -static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, - TCGReg arg2, TCGLabel *l) -{ - static const MIPSInsn b_zero[16] = { - [TCG_COND_LT] = OPC_BLTZ, - [TCG_COND_GT] = OPC_BGTZ, - [TCG_COND_LE] = OPC_BLEZ, - [TCG_COND_GE] = OPC_BGEZ, - }; - - MIPSInsn s_opc = OPC_SLTU; - MIPSInsn b_opc; - int cmp_map; - - switch (cond) { - case TCG_COND_EQ: - b_opc = OPC_BEQ; - break; - case TCG_COND_NE: - b_opc = OPC_BNE; - break; - - case TCG_COND_LT: - case TCG_COND_GT: - case TCG_COND_LE: - case TCG_COND_GE: - if (arg2 == 0) { - b_opc = b_zero[cond]; - arg2 = arg1; - arg1 = 0; - break; - } - s_opc = OPC_SLT; - /* FALLTHRU */ - - case TCG_COND_LTU: - case TCG_COND_GTU: - case TCG_COND_LEU: - case TCG_COND_GEU: - cmp_map = mips_cmp_map[cond]; - if (cmp_map & MIPS_CMP_SWAP) { - TCGReg t = arg1; - arg1 = arg2; - arg2 = t; - } - tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); - b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); - arg1 = TCG_TMP0; - arg2 = TCG_REG_ZERO; - break; - - default: - tcg_abort(); - break; - } - - tcg_out_opc_br(s, b_opc, arg1, arg2); - if (l->has_value) { - reloc_pc16(s->code_ptr - 1, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); - } - tcg_out_nop(s); -} - -static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, - TCGReg al, TCGReg ah, - TCGReg bl, TCGReg bh) -{ - /* Merge highpart comparison into AH. */ - if (bh != 0) { - if (ah != 0) { - tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); - ah = tmp0; - } else { - ah = bh; - } - } - /* Merge lowpart comparison into AL. */ - if (bl != 0) { - if (al != 0) { - tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); - al = tmp1; - } else { - al = bl; - } - } - /* Merge high and low part comparisons into AL. */ - if (ah != 0) { - if (al != 0) { - tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); - al = tmp0; - } else { - al = ah; - } - } - return al; -} - -static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - TCGReg tmp0 = TCG_TMP0; - TCGReg tmp1 = ret; - - tcg_debug_assert(ret != TCG_TMP0); - if (ret == ah || ret == bh) { - tcg_debug_assert(ret != TCG_TMP1); - tmp1 = TCG_TMP1; - } - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); - tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); - break; - - default: - tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); - tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); - tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); - tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); - break; - } -} - -static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGReg bl, TCGReg bh, TCGLabel *l) -{ - TCGCond b_cond = TCG_COND_NE; - TCGReg tmp = TCG_TMP1; - - /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. - With setcond, we emit between 3 and 10 insns and only 1 branch, - which ought to get better branch prediction. */ - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - b_cond = cond; - tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); - break; - - default: - /* Minimize code size by preferring a compare not requiring INV. */ - if (mips_cmp_map[cond] & MIPS_CMP_INV) { - cond = tcg_invert_cond(cond); - b_cond = TCG_COND_EQ; - } - tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); - break; - } - - tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); -} - -static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) -{ - bool eqz = false; - - /* If one of the values is zero, put it last to match SEL*Z instructions */ - if (use_mips32r6_instructions && v1 == 0) { - v1 = v2; - v2 = 0; - cond = tcg_invert_cond(cond); - } - - switch (cond) { - case TCG_COND_EQ: - eqz = true; - /* FALLTHRU */ - case TCG_COND_NE: - if (c2 != 0) { - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); - c1 = TCG_TMP0; - } - break; - - default: - /* Minimize code size by preferring a compare not requiring INV. */ - if (mips_cmp_map[cond] & MIPS_CMP_INV) { - cond = tcg_invert_cond(cond); - eqz = true; - } - tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); - c1 = TCG_TMP0; - break; - } - - if (use_mips32r6_instructions) { - MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; - MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; - - if (v2 != 0) { - tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); - } - tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); - if (v2 != 0) { - tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); - } - } else { - MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; - - tcg_out_opc_reg(s, m_opc, ret, v1, c1); - - /* This should be guaranteed via constraints */ - tcg_debug_assert(v2 == ret); - } -} - -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) -{ - /* Note that the ABI requires the called function's address to be - loaded into T9, even if a direct branch is in range. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); - - /* But do try a direct branch, allowing the cpu better insn prefetch. */ - if (tail) { - if (!tcg_out_opc_jmp(s, OPC_J, arg)) { - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); - } - } else { - if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { - tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); - } - } -} - -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) -{ - tcg_out_call_int(s, arg, false); - tcg_out_nop(s); -} - -#if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.inc.c" - -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_SB] = helper_ret_ldsb_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LESW] = helper_le_ldsw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BESW] = helper_be_ldsw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, -#if TCG_TARGET_REG_BITS == 64 - [MO_LESL] = helper_le_ldsl_mmu, - [MO_BESL] = helper_be_ldsl_mmu, -#endif -}; - -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * I is where we want to put this argument, and is updated and returned - * for the next call. ARG is the argument itself. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ - -static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) -{ - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); - } else { - /* For N32 and N64, the initial offset is different. But there - we also have 8 argument register so we don't run out here. */ - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); - } - return i + 1; -} - -static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp = TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp = tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp = TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp = tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) -{ - TCGReg tmp = TCG_TMP0; - if (arg == 0) { - tmp = TCG_REG_ZERO; - } else { - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp = tcg_target_call_iarg_regs[i]; - } - tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); - } - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS == 32); - i = (i + 1) & ~1; - i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); - i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); - return i; -} - -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* - * Perform the tlb comparison operation. - * The complete host address is placed in BASE. - * Clobbers TMP0, TMP1, TMP2, TMP3. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, TCGMemOpIdx oi, - tcg_insn_unit *label_ptr[2], bool is_load) -{ - MemOp opc = get_memop(oi); - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - int mem_index = get_mmuidx(oi); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); - int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); - int table_off = fast_off + offsetof(CPUTLBDescFast, table); - int add_off = offsetof(CPUTLBEntry, addend); - int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - target_ulong mask; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); - - /* Extract the TLB index from the address into TMP3. */ - tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* We don't currently support unaligned accesses. - We could do so with mips32r6. */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - - /* Mask the page bits, keeping the alignment bits to compare against. */ - mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); - - /* Load the (low-half) tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); - } else { - tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD - : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), - TCG_TMP0, TCG_TMP3, cmp_off); - tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); - /* No second compare is required here; - load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); - - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl = base; - } - - label_ptr[0] = s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); - - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - /* delay slot */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - - label_ptr[1] = s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); - } - - /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit *label_ptr[2]) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->type = ext; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr[0]; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - label->label_ptr[1] = label_ptr[1]; - } -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - TCGReg v0; - int i; - - /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); - } - - i = 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - i = tcg_out_call_iarg_imm(s, i, oi); - i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - - v0 = l->datalo_reg; - if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { - /* We eliminated V0 from the possible output registers, so it - cannot be clobbered here. So we must move V1 first. */ - if (MIPS_BE) { - tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); - v0 = l->datahi_reg; - } else { - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); - } - } - - tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); - reloc_pc16(s->code_ptr - 1, l->raddr); - - /* delay slot */ - if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { - /* we always sign-extend 32-bit loads */ - tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); - } else { - tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); - } - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - MemOp s_bits = opc & MO_SIZE; - int i; - - /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); - } - - i = 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - switch (s_bits) { - case MO_8: - i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); - break; - case MO_16: - i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); - break; - case MO_32: - i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); - break; - case MO_64: - if (TCG_TARGET_REG_BITS == 32) { - i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); - } else { - i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); - } - break; - default: - tcg_abort(); - } - i = tcg_out_call_iarg_imm(s, i, oi); - - /* Tail call to the store helper. Thus force the return address - computation to take place in the return address register. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); - i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); - return true; -} -#endif - -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) -{ - switch (opc & (MO_SSIZE | MO_BSWAP)) { - case MO_UB: - tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); - break; - case MO_SB: - tcg_out_opc_imm(s, OPC_LB, lo, base, 0); - break; - case MO_UW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1); - break; - case MO_UW: - tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); - break; - case MO_SW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16s(s, lo, TCG_TMP1); - break; - case MO_SW: - tcg_out_opc_imm(s, OPC_LH, lo, base, 0); - break; - case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS == 64 && is_64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - tcg_out_bswap32u(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap32u_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - break; - } - /* FALLTHRU */ - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_bswap32(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); - } - break; - case MO_UL: - if (TCG_TARGET_REG_BITS == 64 && is_64) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - break; - } - /* FALLTHRU */ - case MO_SL: - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - break; - case MO_Q | MO_BSWAP: - if (TCG_TARGET_REG_BITS == 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; - case MO_Q: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (MIPS_BE ? hi != base : lo == base) { - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - } else { - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - } - break; - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#endif - TCGReg base = TCG_REG_A0; - - data_regl = *args++; - data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addr_regl = *args++; - addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); -#else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } - if (guest_base == 0 && data_regl != addr_regl) { - base = addr_regl; - } else if (guest_base == (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); - } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); -#endif -} - -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc) -{ - /* Don't clutter the code below with checks to avoid bswapping ZERO. */ - if ((lo | hi) == 0) { - opc &= ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { - case MO_8: - tcg_out_opc_imm(s, OPC_SB, lo, base, 0); - break; - - case MO_16 | MO_BSWAP: - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); - tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); - lo = TCG_TMP1; - /* FALLTHRU */ - case MO_16: - tcg_out_opc_imm(s, OPC_SH, lo, base, 0); - break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo); - lo = TCG_TMP3; - /* FALLTHRU */ - case MO_32: - tcg_out_opc_imm(s, OPC_SW, lo, base, 0); - break; - - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); - } - break; - case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_SD, lo, base, 0); - } else { - tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); - tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); - } - break; - - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#endif - TCGReg base = TCG_REG_A0; - - data_regl = *args++; - data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addr_regl = *args++; - addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); -#else - base = TCG_REG_A0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } - if (guest_base == 0) { - base = addr_regl; - } else if (guest_base == (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); - } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); -#endif -} - -static void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - static const MIPSInsn sync[] = { - /* Note that SYNC_MB is a slightly weaker than SYNC 0, - as the former is an ordering barrier and the latter - is a completion barrier. */ - [0 ... TCG_MO_ALL] = OPC_SYNC_MB, - [TCG_MO_LD_LD] = OPC_SYNC_RMB, - [TCG_MO_ST_ST] = OPC_SYNC_WMB, - [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, - [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, - [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, - }; - tcg_out32(s, sync[a0 & TCG_MO_ALL]); -} - -static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, - int width, TCGReg a0, TCGReg a1, TCGArg a2) -{ - if (use_mips32r6_instructions) { - if (a2 == width) { - tcg_out_opc_reg(s, opcv6, a0, a1, 0); - } else { - tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); - tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); - } - } else { - if (a2 == width) { - tcg_out_opc_reg(s, opcv2, a0, a1, a1); - } else if (a0 == a2) { - tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); - tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); - } else if (a0 != a1) { - tcg_out_opc_reg(s, opcv2, a0, a1, a1); - tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); - } else { - tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); - tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); - tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); - } - } -} - -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - MIPSInsn i1, i2; - TCGArg a0, a1, a2; - int c2; - - a0 = args[0]; - a1 = args[1]; - a2 = args[2]; - c2 = const_args[2]; - - switch (opc) { - case INDEX_op_exit_tb: - { - TCGReg b0 = TCG_REG_ZERO; - - a0 = (intptr_t)a0; - if (a0 & ~0xffff) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); - b0 = TCG_REG_V0; - } - if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, - (uintptr_t)tb_ret_addr); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } - tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); - } - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* Avoid clobbering the address during retranslation. */ - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); - } else { - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } - tcg_out_nop(s); - set_jmp_reset_offset(s, a0); - break; - case INDEX_op_goto_ptr: - /* jmp to the given host address (could be epilogue) */ - tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - tcg_out_nop(s); - break; - case INDEX_op_br: - tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, - arg_label(a0)); - break; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - i1 = OPC_LBU; - goto do_ldst; - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - i1 = OPC_LB; - goto do_ldst; - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - i1 = OPC_LHU; - goto do_ldst; - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - i1 = OPC_LH; - goto do_ldst; - case INDEX_op_ld_i32: - case INDEX_op_ld32s_i64: - i1 = OPC_LW; - goto do_ldst; - case INDEX_op_ld32u_i64: - i1 = OPC_LWU; - goto do_ldst; - case INDEX_op_ld_i64: - i1 = OPC_LD; - goto do_ldst; - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - i1 = OPC_SB; - goto do_ldst; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - i1 = OPC_SH; - goto do_ldst; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - i1 = OPC_SW; - goto do_ldst; - case INDEX_op_st_i64: - i1 = OPC_SD; - do_ldst: - tcg_out_ldst(s, i1, a0, a1, a2); - break; - - case INDEX_op_add_i32: - i1 = OPC_ADDU, i2 = OPC_ADDIU; - goto do_binary; - case INDEX_op_add_i64: - i1 = OPC_DADDU, i2 = OPC_DADDIU; - goto do_binary; - case INDEX_op_or_i32: - case INDEX_op_or_i64: - i1 = OPC_OR, i2 = OPC_ORI; - goto do_binary; - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - i1 = OPC_XOR, i2 = OPC_XORI; - do_binary: - if (c2) { - tcg_out_opc_imm(s, i2, a0, a1, a2); - break; - } - do_binaryv: - tcg_out_opc_reg(s, i1, a0, a1, a2); - break; - - case INDEX_op_sub_i32: - i1 = OPC_SUBU, i2 = OPC_ADDIU; - goto do_subtract; - case INDEX_op_sub_i64: - i1 = OPC_DSUBU, i2 = OPC_DADDIU; - do_subtract: - if (c2) { - tcg_out_opc_imm(s, i2, a0, a1, -a2); - break; - } - goto do_binaryv; - case INDEX_op_and_i32: - if (c2 && a2 != (uint16_t)a2) { - int msb = ctz32(~a2) - 1; - tcg_debug_assert(use_mips32r2_instructions); - tcg_debug_assert(is_p2m1(a2)); - tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); - break; - } - i1 = OPC_AND, i2 = OPC_ANDI; - goto do_binary; - case INDEX_op_and_i64: - if (c2 && a2 != (uint16_t)a2) { - int msb = ctz64(~a2) - 1; - tcg_debug_assert(use_mips32r2_instructions); - tcg_debug_assert(is_p2m1(a2)); - tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); - break; - } - i1 = OPC_AND, i2 = OPC_ANDI; - goto do_binary; - case INDEX_op_nor_i32: - case INDEX_op_nor_i64: - i1 = OPC_NOR; - goto do_binaryv; - - case INDEX_op_mul_i32: - if (use_mips32_instructions) { - tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); - break; - } - i1 = OPC_MULT, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_mulsh_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); - break; - } - i1 = OPC_MULT, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_muluh_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); - break; - } - i1 = OPC_MULTU, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_div_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); - break; - } - i1 = OPC_DIV, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_divu_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); - break; - } - i1 = OPC_DIVU, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_rem_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); - break; - } - i1 = OPC_DIV, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_remu_i32: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); - break; - } - i1 = OPC_DIVU, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_mul_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); - break; - } - i1 = OPC_DMULT, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_mulsh_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); - break; - } - i1 = OPC_DMULT, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_muluh_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); - break; - } - i1 = OPC_DMULTU, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_div_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); - break; - } - i1 = OPC_DDIV, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_divu_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); - break; - } - i1 = OPC_DDIVU, i2 = OPC_MFLO; - goto do_hilo1; - case INDEX_op_rem_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); - break; - } - i1 = OPC_DDIV, i2 = OPC_MFHI; - goto do_hilo1; - case INDEX_op_remu_i64: - if (use_mips32r6_instructions) { - tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); - break; - } - i1 = OPC_DDIVU, i2 = OPC_MFHI; - do_hilo1: - tcg_out_opc_reg(s, i1, 0, a1, a2); - tcg_out_opc_reg(s, i2, a0, 0, 0); - break; - - case INDEX_op_muls2_i32: - i1 = OPC_MULT; - goto do_hilo2; - case INDEX_op_mulu2_i32: - i1 = OPC_MULTU; - goto do_hilo2; - case INDEX_op_muls2_i64: - i1 = OPC_DMULT; - goto do_hilo2; - case INDEX_op_mulu2_i64: - i1 = OPC_DMULTU; - do_hilo2: - tcg_out_opc_reg(s, i1, 0, a2, args[3]); - tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); - tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); - break; - - case INDEX_op_not_i32: - case INDEX_op_not_i64: - i1 = OPC_NOR; - goto do_unary; - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - i1 = OPC_WSBH; - goto do_unary; - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - i1 = OPC_SEB; - goto do_unary; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - i1 = OPC_SEH; - do_unary: - tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); - break; - - case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, a0, a1); - break; - case INDEX_op_bswap32_i64: - tcg_out_bswap32u(s, a0, a1); - break; - case INDEX_op_bswap64_i64: - tcg_out_bswap64(s, a0, a1); - break; - case INDEX_op_extrh_i64_i32: - tcg_out_dsra(s, a0, a1, 32); - break; - case INDEX_op_ext32s_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extrl_i64_i32: - tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); - break; - case INDEX_op_ext32u_i64: - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - - case INDEX_op_sar_i32: - i1 = OPC_SRAV, i2 = OPC_SRA; - goto do_shift; - case INDEX_op_shl_i32: - i1 = OPC_SLLV, i2 = OPC_SLL; - goto do_shift; - case INDEX_op_shr_i32: - i1 = OPC_SRLV, i2 = OPC_SRL; - goto do_shift; - case INDEX_op_rotr_i32: - i1 = OPC_ROTRV, i2 = OPC_ROTR; - do_shift: - if (c2) { - tcg_out_opc_sa(s, i2, a0, a1, a2); - break; - } - do_shiftv: - tcg_out_opc_reg(s, i1, a0, a2, a1); - break; - case INDEX_op_rotl_i32: - if (c2) { - tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); - } else { - tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); - tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); - } - break; - case INDEX_op_sar_i64: - if (c2) { - tcg_out_dsra(s, a0, a1, a2); - break; - } - i1 = OPC_DSRAV; - goto do_shiftv; - case INDEX_op_shl_i64: - if (c2) { - tcg_out_dsll(s, a0, a1, a2); - break; - } - i1 = OPC_DSLLV; - goto do_shiftv; - case INDEX_op_shr_i64: - if (c2) { - tcg_out_dsrl(s, a0, a1, a2); - break; - } - i1 = OPC_DSRLV; - goto do_shiftv; - case INDEX_op_rotr_i64: - if (c2) { - tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); - break; - } - i1 = OPC_DROTRV; - goto do_shiftv; - case INDEX_op_rotl_i64: - if (c2) { - tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); - } else { - tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); - tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); - } - break; - - case INDEX_op_clz_i32: - tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); - break; - case INDEX_op_clz_i64: - tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); - break; - - case INDEX_op_deposit_i32: - tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); - break; - case INDEX_op_deposit_i64: - tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, - args[3] + args[4] - 1, args[3]); - break; - case INDEX_op_extract_i32: - tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); - break; - case INDEX_op_extract_i64: - tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, - args[3] - 1, a2); - break; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); - break; - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); - break; - - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); - break; - - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - tcg_out_setcond(s, args[3], a0, a1, a2); - break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); - break; - - case INDEX_op_add2_i32: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], false); - break; - case INDEX_op_sub2_i32: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], true); - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; - static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; - static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; - static const TCGTargetOpDef SZ_SZ_S - = { .args_ct_str = { "SZ", "SZ", "S" } }; - static const TCGTargetOpDef SZ_SZ_S_S - = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_rIK - = { .args_ct_str = { "r", "r", "rIK" } }; - static const TCGTargetOpDef r_r_rWZ - = { .args_ct_str = { "r", "r", "rWZ" } }; - static const TCGTargetOpDef r_r_r_r - = { .args_ct_str = { "r", "r", "r", "r" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; - static const TCGTargetOpDef movc_r6 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_not_i32: - case INDEX_op_bswap16_i32: - case INDEX_op_bswap32_i32: - case INDEX_op_ext8s_i32: - case INDEX_op_ext16s_i32: - case INDEX_op_extract_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld_i64: - case INDEX_op_not_i64: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_ext8s_i64: - case INDEX_op_ext16s_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return &rZ_r; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - return &r_r_rJ; - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - return &r_rZ_rN; - case INDEX_op_mul_i32: - case INDEX_op_mulsh_i32: - case INDEX_op_muluh_i32: - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - case INDEX_op_rem_i32: - case INDEX_op_remu_i32: - case INDEX_op_nor_i32: - case INDEX_op_setcond_i32: - case INDEX_op_mul_i64: - case INDEX_op_mulsh_i64: - case INDEX_op_muluh_i64: - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - case INDEX_op_nor_i64: - case INDEX_op_setcond_i64: - return &r_rZ_rZ; - case INDEX_op_muls2_i32: - case INDEX_op_mulu2_i32: - case INDEX_op_muls2_i64: - case INDEX_op_mulu2_i64: - return &r_r_r_r; - case INDEX_op_and_i32: - case INDEX_op_and_i64: - return &r_r_rIK; - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - return &r_r_rI; - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotr_i32: - case INDEX_op_rotl_i32: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotr_i64: - case INDEX_op_rotl_i64: - return &r_r_ri; - case INDEX_op_clz_i32: - case INDEX_op_clz_i64: - return &r_r_rWZ; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - return &dep; - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &rZ_rZ; - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - return use_mips32r6_instructions ? &movc_r6 : &movc; - - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - return &add2; - case INDEX_op_setcond2_i32: - return &setc2; - case INDEX_op_brcond2_i32: - return &br2; - - case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); - case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &SZ_S : &SZ_S_S); - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &SZ_S - : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); - - default: - return NULL; - } -} - -static const int tcg_target_callee_save_regs[] = { - TCG_REG_S0, /* used for the global env (TCG_AREG0) */ - TCG_REG_S1, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - TCG_REG_RA, /* should be last for ABI compliance */ -}; - -/* The Linux kernel doesn't provide any information about the available - instruction set. Probe it using a signal handler. */ - - -#ifndef use_movnz_instructions -bool use_movnz_instructions = false; -#endif - -#ifndef use_mips32_instructions -bool use_mips32_instructions = false; -#endif - -#ifndef use_mips32r2_instructions -bool use_mips32r2_instructions = false; -#endif - -static volatile sig_atomic_t got_sigill; - -static void sigill_handler(int signo, siginfo_t *si, void *data) -{ - /* Skip the faulty instruction */ - ucontext_t *uc = (ucontext_t *)data; - uc->uc_mcontext.pc += 4; - - got_sigill = 1; -} - -static void tcg_target_detect_isa(void) -{ - struct sigaction sa_old, sa_new; - - memset(&sa_new, 0, sizeof(sa_new)); - sa_new.sa_flags = SA_SIGINFO; - sa_new.sa_sigaction = sigill_handler; - sigaction(SIGILL, &sa_new, &sa_old); - - /* Probe for movn/movz, necessary to implement movcond. */ -#ifndef use_movnz_instructions - got_sigill = 0; - asm volatile(".set push\n" - ".set mips32\n" - "movn $zero, $zero, $zero\n" - "movz $zero, $zero, $zero\n" - ".set pop\n" - : : : ); - use_movnz_instructions = !got_sigill; -#endif - - /* Probe for MIPS32 instructions. As no subsetting is allowed - by the specification, it is only necessary to probe for one - of the instructions. */ -#ifndef use_mips32_instructions - got_sigill = 0; - asm volatile(".set push\n" - ".set mips32\n" - "mul $zero, $zero\n" - ".set pop\n" - : : : ); - use_mips32_instructions = !got_sigill; -#endif - - /* Probe for MIPS32r2 instructions if MIPS32 instructions are - available. As no subsetting is allowed by the specification, - it is only necessary to probe for one of the instructions. */ -#ifndef use_mips32r2_instructions - if (use_mips32_instructions) { - got_sigill = 0; - asm volatile(".set push\n" - ".set mips32r2\n" - "seb $zero, $zero\n" - ".set pop\n" - : : : ); - use_mips32r2_instructions = !got_sigill; - } -#endif - - sigaction(SIGILL, &sa_old, NULL); -} - -static tcg_insn_unit *align_code_ptr(TCGContext *s) -{ - uintptr_t p = (uintptr_t)s->code_ptr; - if (p & 15) { - p = (p + 15) & -16; - s->code_ptr = (void *)p; - } - return s->code_ptr; -} - -/* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) -#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) -#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) - -#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & -TCG_TARGET_STACK_ALIGN) -#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) - -/* We're expecting to be able to use an immediate for frame allocation. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); - -/* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int i; - - tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); - - /* TB prologue */ - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { - tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_SP, SAVE_OFS + i * REG_SIZE); - } - -#ifndef CONFIG_SOFTMMU - if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); - } -#endif - - /* Call generated code */ - tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); - - /* TB epilogue */ - tb_ret_addr = s->code_ptr; - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { - tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_SP, SAVE_OFS + i * REG_SIZE); - } - - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); - /* delay slot */ - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); - - if (use_mips32r2_instructions) { - return; - } - - /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; - clobbers TCG_TMP1, TCG_TMP2. */ - - /* - * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. - */ - bswap32_addr = align_code_ptr(s); - /* t3 = (ssss)d000 */ - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); - /* t1 = 000a */ - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); - /* t2 = 00c0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); - /* t3 = d00a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - /* t1 = 0abc */ - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); - /* t2 = 0c00 */ - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); - /* t1 = 00b0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); - /* t3 = dc0a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); - /* t3 = dcba -- delay slot */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - if (TCG_TARGET_REG_BITS == 32) { - return; - } - - /* - * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. - */ - bswap32u_addr = align_code_ptr(s); - /* t1 = (0000)000d */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); - /* t3 = 000a */ - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); - /* t1 = (0000)d000 */ - tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); - /* t2 = 00c0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); - /* t3 = d00a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - /* t1 = 0abc */ - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); - /* t2 = 0c00 */ - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); - /* t1 = 00b0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); - /* t3 = dc0a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); - /* t3 = dcba -- delay slot */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* - * bswap64 -- 64-bit swap. a0 = abcdefgh - */ - bswap64_addr = align_code_ptr(s); - /* t3 = h0000000 */ - tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); - /* t1 = 0000000a */ - tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); - - /* t2 = 000000g0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); - /* t3 = h000000a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - /* t1 = 00000abc */ - tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); - /* t2 = 0g000000 */ - tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); - /* t1 = 000000b0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); - - /* t3 = hg00000a */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); - /* t2 = 0000abcd */ - tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); - /* t3 = hg0000ba */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* t1 = 000000c0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); - /* t2 = 0000000d */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); - /* t1 = 00000c00 */ - tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); - /* t2 = 0000d000 */ - tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); - - /* t3 = hg000cba */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); - /* t1 = 00abcdef */ - tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); - /* t3 = hg00dcba */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); - - /* t2 = 0000000f */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); - /* t1 = 000000e0 */ - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); - /* t2 = 00f00000 */ - tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); - /* t1 = 000e0000 */ - tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); - - /* t3 = hgf0dcba */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); - /* t3 = hgfedcba -- delay slot */ - tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); -} - -static void tcg_target_init(TCGContext *s) -{ - tcg_target_detect_isa(); - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - if (TCG_TARGET_REG_BITS == 64) { - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - } - - tcg_target_call_clobber_regs = 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ - tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ -} - -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) -{ - atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; -} DebugFrame; - -#define ELF_HOST_MACHINE EM_MIPS -/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, - which is good because they're really quite complicated for MIPS. */ - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ - .h.cie.return_column = TCG_REG_RA, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ - 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ - 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ - 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ - 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ - 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ - 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ - 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ - 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc new file mode 100644 index 0000000000..3bef3789b3 --- /dev/null +++ b/tcg/ppc/tcg-target.c.inc @@ -0,0 +1,3884 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "elf.h" +#include "../tcg-pool.c.inc" + +#if defined _CALL_DARWIN || defined __APPLE__ +#define TCG_TARGET_CALL_DARWIN +#endif +#ifdef _CALL_SYSV +# define TCG_TARGET_CALL_ALIGN_ARGS 1 +#endif + +/* For some memory operations, we need a scratch that isn't R0. For the AIX + calling convention, we can re-use the TOC register since we'll be reloading + it at every call. Otherwise R12 will do nicely as neither a call-saved + register nor a parameter register. */ +#ifdef _CALL_AIX +# define TCG_REG_TMP1 TCG_REG_R2 +#else +# define TCG_REG_TMP1 TCG_REG_R12 +#endif + +#define TCG_VEC_TMP1 TCG_REG_V0 +#define TCG_VEC_TMP2 TCG_REG_V1 + +#define TCG_REG_TB TCG_REG_R31 +#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) + +/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ +#define SZP ((int)sizeof(void *)) + +/* Shorthand for size of a register. */ +#define SZR (TCG_TARGET_REG_BITS / 8) + +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_U16 0x200 +#define TCG_CT_CONST_S32 0x400 +#define TCG_CT_CONST_U32 0x800 +#define TCG_CT_CONST_ZERO 0x1000 +#define TCG_CT_CONST_MONE 0x2000 +#define TCG_CT_CONST_WSZ 0x4000 + +static tcg_insn_unit *tb_ret_addr; + +TCGPowerISA have_isa; +static bool have_isel; +bool have_altivec; +bool have_vsx; + +#ifndef CONFIG_SOFTMMU +#define TCG_GUEST_BASE_REG 30 +#endif + +#ifdef CONFIG_DEBUG_TCG +static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { + TCG_REG_R14, /* call saved registers */ + TCG_REG_R15, + TCG_REG_R16, + TCG_REG_R17, + TCG_REG_R18, + TCG_REG_R19, + TCG_REG_R20, + TCG_REG_R21, + TCG_REG_R22, + TCG_REG_R23, + TCG_REG_R24, + TCG_REG_R25, + TCG_REG_R26, + TCG_REG_R27, + TCG_REG_R28, + TCG_REG_R29, + TCG_REG_R30, + TCG_REG_R31, + TCG_REG_R12, /* call clobbered, non-arguments */ + TCG_REG_R11, + TCG_REG_R2, + TCG_REG_R13, + TCG_REG_R10, /* call clobbered, arguments */ + TCG_REG_R9, + TCG_REG_R8, + TCG_REG_R7, + TCG_REG_R6, + TCG_REG_R5, + TCG_REG_R4, + TCG_REG_R3, + + /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ + TCG_REG_V2, /* call clobbered, vectors */ + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V8, + TCG_REG_V9, + TCG_REG_V10, + TCG_REG_V11, + TCG_REG_V12, + TCG_REG_V13, + TCG_REG_V14, + TCG_REG_V15, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, +}; + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_R3, + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10 +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_R3, + TCG_REG_R4 +}; + +static const int tcg_target_callee_save_regs[] = { +#ifdef TCG_TARGET_CALL_DARWIN + TCG_REG_R11, +#endif + TCG_REG_R14, + TCG_REG_R15, + TCG_REG_R16, + TCG_REG_R17, + TCG_REG_R18, + TCG_REG_R19, + TCG_REG_R20, + TCG_REG_R21, + TCG_REG_R22, + TCG_REG_R23, + TCG_REG_R24, + TCG_REG_R25, + TCG_REG_R26, + TCG_REG_R27, /* currently used for the global env */ + TCG_REG_R28, + TCG_REG_R29, + TCG_REG_R30, + TCG_REG_R31 +}; + +static inline bool in_range_b(tcg_target_long target) +{ + return target == sextract64(target, 0, 26); +} + +static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + tcg_debug_assert(in_range_b(disp)); + return disp & 0x3fffffc; +} + +static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + if (in_range_b(disp)) { + *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + return true; + } + return false; +} + +static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + tcg_debug_assert(disp == (int16_t) disp); + return disp & 0xfffc; +} + +static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + if (disp == (int16_t) disp) { + *pc = (*pc & ~0xfffc) | (disp & 0xfffc); + return true; + } + return false; +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'A': case 'B': case 'C': case 'D': + ct->ct |= TCG_CT_REG; + tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); + break; + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + break; + case 'v': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff00000000ull; + break; + case 'L': /* qemu_ld constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); +#ifdef CONFIG_SOFTMMU + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); +#endif + break; + case 'S': /* qemu_st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); +#ifdef CONFIG_SOFTMMU + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); +#endif + break; + case 'I': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_U16; + break; + case 'M': + ct->ct |= TCG_CT_CONST_MONE; + break; + case 'T': + ct->ct |= TCG_CT_CONST_S32; + break; + case 'U': + ct->ct |= TCG_CT_CONST_U32; + break; + case 'W': + ct->ct |= TCG_CT_CONST_WSZ; + break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } + + /* The only 32-bit constraint we use aside from + TCG_CT_CONST is TCG_CT_CONST_S16. */ + if (type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { + return 1; + } else if ((ct & TCG_CT_CONST_WSZ) + && val == (type == TCG_TYPE_I32 ? 32 : 64)) { + return 1; + } + return 0; +} + +#define OPCD(opc) ((opc)<<26) +#define XO19(opc) (OPCD(19)|((opc)<<1)) +#define MD30(opc) (OPCD(30)|((opc)<<2)) +#define MDS30(opc) (OPCD(30)|((opc)<<1)) +#define XO31(opc) (OPCD(31)|((opc)<<1)) +#define XO58(opc) (OPCD(58)|(opc)) +#define XO62(opc) (OPCD(62)|(opc)) +#define VX4(opc) (OPCD(4)|(opc)) + +#define B OPCD( 18) +#define BC OPCD( 16) +#define LBZ OPCD( 34) +#define LHZ OPCD( 40) +#define LHA OPCD( 42) +#define LWZ OPCD( 32) +#define LWZUX XO31( 55) +#define STB OPCD( 38) +#define STH OPCD( 44) +#define STW OPCD( 36) + +#define STD XO62( 0) +#define STDU XO62( 1) +#define STDX XO31(149) + +#define LD XO58( 0) +#define LDX XO31( 21) +#define LDU XO58( 1) +#define LDUX XO31( 53) +#define LWA XO58( 2) +#define LWAX XO31(341) + +#define ADDIC OPCD( 12) +#define ADDI OPCD( 14) +#define ADDIS OPCD( 15) +#define ORI OPCD( 24) +#define ORIS OPCD( 25) +#define XORI OPCD( 26) +#define XORIS OPCD( 27) +#define ANDI OPCD( 28) +#define ANDIS OPCD( 29) +#define MULLI OPCD( 7) +#define CMPLI OPCD( 10) +#define CMPI OPCD( 11) +#define SUBFIC OPCD( 8) + +#define LWZU OPCD( 33) +#define STWU OPCD( 37) + +#define RLWIMI OPCD( 20) +#define RLWINM OPCD( 21) +#define RLWNM OPCD( 23) + +#define RLDICL MD30( 0) +#define RLDICR MD30( 1) +#define RLDIMI MD30( 3) +#define RLDCL MDS30( 8) + +#define BCLR XO19( 16) +#define BCCTR XO19(528) +#define CRAND XO19(257) +#define CRANDC XO19(129) +#define CRNAND XO19(225) +#define CROR XO19(449) +#define CRNOR XO19( 33) + +#define EXTSB XO31(954) +#define EXTSH XO31(922) +#define EXTSW XO31(986) +#define ADD XO31(266) +#define ADDE XO31(138) +#define ADDME XO31(234) +#define ADDZE XO31(202) +#define ADDC XO31( 10) +#define AND XO31( 28) +#define SUBF XO31( 40) +#define SUBFC XO31( 8) +#define SUBFE XO31(136) +#define SUBFME XO31(232) +#define SUBFZE XO31(200) +#define OR XO31(444) +#define XOR XO31(316) +#define MULLW XO31(235) +#define MULHW XO31( 75) +#define MULHWU XO31( 11) +#define DIVW XO31(491) +#define DIVWU XO31(459) +#define CMP XO31( 0) +#define CMPL XO31( 32) +#define LHBRX XO31(790) +#define LWBRX XO31(534) +#define LDBRX XO31(532) +#define STHBRX XO31(918) +#define STWBRX XO31(662) +#define STDBRX XO31(660) +#define MFSPR XO31(339) +#define MTSPR XO31(467) +#define SRAWI XO31(824) +#define NEG XO31(104) +#define MFCR XO31( 19) +#define MFOCRF (MFCR | (1u << 20)) +#define NOR XO31(124) +#define CNTLZW XO31( 26) +#define CNTLZD XO31( 58) +#define CNTTZW XO31(538) +#define CNTTZD XO31(570) +#define CNTPOPW XO31(378) +#define CNTPOPD XO31(506) +#define ANDC XO31( 60) +#define ORC XO31(412) +#define EQV XO31(284) +#define NAND XO31(476) +#define ISEL XO31( 15) + +#define MULLD XO31(233) +#define MULHD XO31( 73) +#define MULHDU XO31( 9) +#define DIVD XO31(489) +#define DIVDU XO31(457) + +#define LBZX XO31( 87) +#define LHZX XO31(279) +#define LHAX XO31(343) +#define LWZX XO31( 23) +#define STBX XO31(215) +#define STHX XO31(407) +#define STWX XO31(151) + +#define EIEIO XO31(854) +#define HWSYNC XO31(598) +#define LWSYNC (HWSYNC | (1u << 21)) + +#define SPR(a, b) ((((a)<<5)|(b))<<11) +#define LR SPR(8, 0) +#define CTR SPR(9, 0) + +#define SLW XO31( 24) +#define SRW XO31(536) +#define SRAW XO31(792) + +#define SLD XO31( 27) +#define SRD XO31(539) +#define SRAD XO31(794) +#define SRADI XO31(413<<1) + +#define TW XO31( 4) +#define TRAP (TW | TO(31)) + +#define NOP ORI /* ori 0,0,0 */ + +#define LVX XO31(103) +#define LVEBX XO31(7) +#define LVEHX XO31(39) +#define LVEWX XO31(71) +#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ +#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ +#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ +#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ +#define LXSD (OPCD(57) | 2) /* v3.00 */ +#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ + +#define STVX XO31(231) +#define STVEWX XO31(199) +#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ +#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ +#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ +#define STXSD (OPCD(61) | 2) /* v3.00 */ + +#define VADDSBS VX4(768) +#define VADDUBS VX4(512) +#define VADDUBM VX4(0) +#define VADDSHS VX4(832) +#define VADDUHS VX4(576) +#define VADDUHM VX4(64) +#define VADDSWS VX4(896) +#define VADDUWS VX4(640) +#define VADDUWM VX4(128) +#define VADDUDM VX4(192) /* v2.07 */ + +#define VSUBSBS VX4(1792) +#define VSUBUBS VX4(1536) +#define VSUBUBM VX4(1024) +#define VSUBSHS VX4(1856) +#define VSUBUHS VX4(1600) +#define VSUBUHM VX4(1088) +#define VSUBSWS VX4(1920) +#define VSUBUWS VX4(1664) +#define VSUBUWM VX4(1152) +#define VSUBUDM VX4(1216) /* v2.07 */ + +#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ +#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ + +#define VMAXSB VX4(258) +#define VMAXSH VX4(322) +#define VMAXSW VX4(386) +#define VMAXSD VX4(450) /* v2.07 */ +#define VMAXUB VX4(2) +#define VMAXUH VX4(66) +#define VMAXUW VX4(130) +#define VMAXUD VX4(194) /* v2.07 */ +#define VMINSB VX4(770) +#define VMINSH VX4(834) +#define VMINSW VX4(898) +#define VMINSD VX4(962) /* v2.07 */ +#define VMINUB VX4(514) +#define VMINUH VX4(578) +#define VMINUW VX4(642) +#define VMINUD VX4(706) /* v2.07 */ + +#define VCMPEQUB VX4(6) +#define VCMPEQUH VX4(70) +#define VCMPEQUW VX4(134) +#define VCMPEQUD VX4(199) /* v2.07 */ +#define VCMPGTSB VX4(774) +#define VCMPGTSH VX4(838) +#define VCMPGTSW VX4(902) +#define VCMPGTSD VX4(967) /* v2.07 */ +#define VCMPGTUB VX4(518) +#define VCMPGTUH VX4(582) +#define VCMPGTUW VX4(646) +#define VCMPGTUD VX4(711) /* v2.07 */ +#define VCMPNEB VX4(7) /* v3.00 */ +#define VCMPNEH VX4(71) /* v3.00 */ +#define VCMPNEW VX4(135) /* v3.00 */ + +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSLD VX4(1476) /* v2.07 */ +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRD VX4(1732) /* v2.07 */ +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) +#define VSRAD VX4(964) /* v2.07 */ +#define VRLB VX4(4) +#define VRLH VX4(68) +#define VRLW VX4(132) +#define VRLD VX4(196) /* v2.07 */ + +#define VMULEUB VX4(520) +#define VMULEUH VX4(584) +#define VMULEUW VX4(648) /* v2.07 */ +#define VMULOUB VX4(8) +#define VMULOUH VX4(72) +#define VMULOUW VX4(136) /* v2.07 */ +#define VMULUWM VX4(137) /* v2.07 */ +#define VMSUMUHM VX4(38) + +#define VMRGHB VX4(12) +#define VMRGHH VX4(76) +#define VMRGHW VX4(140) +#define VMRGLB VX4(268) +#define VMRGLH VX4(332) +#define VMRGLW VX4(396) + +#define VPKUHUM VX4(14) +#define VPKUWUM VX4(78) + +#define VAND VX4(1028) +#define VANDC VX4(1092) +#define VNOR VX4(1284) +#define VOR VX4(1156) +#define VXOR VX4(1220) +#define VEQV VX4(1668) /* v2.07 */ +#define VNAND VX4(1412) /* v2.07 */ +#define VORC VX4(1348) /* v2.07 */ + +#define VSPLTB VX4(524) +#define VSPLTH VX4(588) +#define VSPLTW VX4(652) +#define VSPLTISB VX4(780) +#define VSPLTISH VX4(844) +#define VSPLTISW VX4(908) + +#define VSLDOI VX4(44) + +#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ +#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ +#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ + +#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ +#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ +#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ +#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ +#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ +#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ + +#define RT(r) ((r)<<21) +#define RS(r) ((r)<<21) +#define RA(r) ((r)<<16) +#define RB(r) ((r)<<11) +#define TO(t) ((t)<<21) +#define SH(s) ((s)<<11) +#define MB(b) ((b)<<6) +#define ME(e) ((e)<<1) +#define BO(o) ((o)<<21) +#define MB64(b) ((b)<<5) +#define FXM(b) (1 << (19 - (b))) + +#define VRT(r) (((r) & 31) << 21) +#define VRA(r) (((r) & 31) << 16) +#define VRB(r) (((r) & 31) << 11) +#define VRC(r) (((r) & 31) << 6) + +#define LK 1 + +#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) +#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) +#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) +#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) + +#define BF(n) ((n)<<23) +#define BI(n, c) (((c)+((n)*4))<<16) +#define BT(n, c) (((c)+((n)*4))<<21) +#define BA(n, c) (((c)+((n)*4))<<16) +#define BB(n, c) (((c)+((n)*4))<<11) +#define BC_(n, c) (((c)+((n)*4))<<6) + +#define BO_COND_TRUE BO(12) +#define BO_COND_FALSE BO( 4) +#define BO_ALWAYS BO(20) + +enum { + CR_LT, + CR_GT, + CR_EQ, + CR_SO +}; + +static const uint32_t tcg_to_bc[] = { + [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, + [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, + [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, + [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, + [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, + [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, + [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, + [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, + [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, + [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, +}; + +/* The low bit here is set if the RA and RB fields must be inverted. */ +static const uint32_t tcg_to_isel[] = { + [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), + [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, + [TCG_COND_LT] = ISEL | BC_(7, CR_LT), + [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, + [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, + [TCG_COND_GT] = ISEL | BC_(7, CR_GT), + [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), + [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, + [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, + [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), +}; + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_insn_unit *target; + int16_t lo; + int32_t hi; + + value += addend; + target = (tcg_insn_unit *)value; + + switch (type) { + case R_PPC_REL14: + return reloc_pc14(code_ptr, target); + case R_PPC_REL24: + return reloc_pc24(code_ptr, target); + case R_PPC_ADDR16: + /* + * We are (slightly) abusing this relocation type. In particular, + * assert that the low 2 bits are zero, and do not modify them. + * That way we can use this with LD et al that have opcode bits + * in the low 2 bits of the insn. + */ + if ((value & 3) || value != (int16_t)value) { + return false; + } + *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); + break; + case R_PPC_ADDR32: + /* + * We are abusing this relocation type. Again, this points to + * a pair of insns, lis + load. This is an absolute address + * relocation for PPC32 so the lis cannot be removed. + */ + lo = value; + hi = value - lo; + if (hi + lo != value) { + return false; + } + code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, + TCGReg base, tcg_target_long offset); + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + if (ret == arg) { + return true; + } + switch (type) { + case TCG_TYPE_I64: + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); + /* fallthru */ + case TCG_TYPE_I32: + if (ret < TCG_REG_V0) { + if (arg < TCG_REG_V0) { + tcg_out32(s, OR | SAB(arg, ret, arg)); + break; + } else if (have_isa_2_07) { + tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) + | VRT(arg) | RA(ret)); + break; + } else { + /* Altivec does not support vector->integer moves. */ + return false; + } + } else if (arg < TCG_REG_V0) { + if (have_isa_2_07) { + tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) + | VRT(ret) | RA(arg)); + break; + } else { + /* Altivec does not support integer->vector moves. */ + return false; + } + } + /* fallthru */ + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); + tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, + int sh, int mb) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); + sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); + mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); + tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); +} + +static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, + int sh, int mb, int me) +{ + tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); +} + +static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out_rld(s, RLDICL, dst, src, 0, 32); +} + +static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) +{ + tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); +} + +static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) +{ + tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); +} + +static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) +{ + tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); +} + +static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) +{ + tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); +} + +/* Emit a move into ret of arg, if it can be done in one insn. */ +static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) +{ + if (arg == (int16_t)arg) { + tcg_out32(s, ADDI | TAI(ret, 0, arg)); + return true; + } + if (arg == (int32_t)arg && (arg & 0xffff) == 0) { + tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); + return true; + } + return false; +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) +{ + intptr_t tb_diff; + tcg_target_long tmp; + int shift; + + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + arg = (int32_t)arg; + } + + /* Load 16-bit immediates with one insn. */ + if (tcg_out_movi_one(s, ret, arg)) { + return; + } + + /* Load addresses within the TB with one insn. */ + tb_diff = arg - (intptr_t)s->code_gen_ptr; + if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { + tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); + return; + } + + /* Load 32-bit immediates with two insns. Note that we've already + eliminated bare ADDIS, so we know both insns are required. */ + if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { + tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); + tcg_out32(s, ORI | SAI(ret, ret, arg)); + return; + } + if (arg == (uint32_t)arg && !(arg & 0x8000)) { + tcg_out32(s, ADDI | TAI(ret, 0, arg)); + tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); + return; + } + + /* Load masked 16-bit value. */ + if (arg > 0 && (arg & 0x8000)) { + tmp = arg | 0x7fff; + if ((tmp & (tmp + 1)) == 0) { + int mb = clz64(tmp + 1) + 1; + tcg_out32(s, ADDI | TAI(ret, 0, arg)); + tcg_out_rld(s, RLDICL, ret, ret, 0, mb); + return; + } + } + + /* Load common masks with 2 insns. */ + shift = ctz64(arg); + tmp = arg >> shift; + if (tmp == (int16_t)tmp) { + tcg_out32(s, ADDI | TAI(ret, 0, tmp)); + tcg_out_shli64(s, ret, ret, shift); + return; + } + shift = clz64(arg); + if (tcg_out_movi_one(s, ret, arg << shift)) { + tcg_out_shri64(s, ret, ret, shift); + return; + } + + /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ + if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { + tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); + return; + } + + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + return; + } + + tmp = arg >> 31 >> 1; + tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); + if (tmp) { + tcg_out_shli64(s, ret, ret, 32); + } + if (arg & 0xffff0000) { + tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); + } + if (arg & 0xffff) { + tcg_out32(s, ORI | SAI(ret, ret, arg)); + } +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long val) +{ + uint32_t load_insn; + int rel, low; + intptr_t add; + + low = (int8_t)val; + if (low >= -16 && low < 16) { + if (val == (tcg_target_long)dup_const(MO_8, low)) { + tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val == (tcg_target_long)dup_const(MO_16, low)) { + tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); + return; + } + if (val == (tcg_target_long)dup_const(MO_32, low)) { + tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); + return; + } + } + if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) { + tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); + return; + } + + /* + * Otherwise we must load the value from the constant pool. + */ + if (USE_REG_TB) { + rel = R_PPC_ADDR16; + add = -(intptr_t)s->code_gen_ptr; + } else { + rel = R_PPC_ADDR32; + add = 0; + } + + if (have_vsx) { + load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; + load_insn |= VRT(ret) | RB(TCG_REG_TMP1); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_label(s, val, rel, s->code_ptr, add); + } else { + new_pool_l2(s, rel, s->code_ptr, add, val, val); + } + } else { + load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); + if (TCG_TARGET_REG_BITS == 64) { + new_pool_l2(s, rel, s->code_ptr, add, val, val); + } else { + new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); + } + } + + if (USE_REG_TB) { + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); + load_insn |= RA(TCG_REG_TB); + } else { + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); + } + tcg_out32(s, load_insn); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg) +{ + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(ret < TCG_REG_V0); + tcg_out_movi_int(s, type, ret, arg, false); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(ret >= TCG_REG_V0); + tcg_out_dupi_vec(s, type, ret, arg); + break; + + default: + g_assert_not_reached(); + } +} + +static bool mask_operand(uint32_t c, int *mb, int *me) +{ + uint32_t lsb, test; + + /* Accept a bit pattern like: + 0....01....1 + 1....10....0 + 0..01..10..0 + Keep track of the transitions. */ + if (c == 0 || c == -1) { + return false; + } + test = c; + lsb = test & -test; + test += lsb; + if (test & (test - 1)) { + return false; + } + + *me = clz32(lsb); + *mb = test ? clz32(test & -test) + 1 : 0; + return true; +} + +static bool mask64_operand(uint64_t c, int *mb, int *me) +{ + uint64_t lsb; + + if (c == 0) { + return false; + } + + lsb = c & -c; + /* Accept 1..10..0. */ + if (c == -lsb) { + *mb = 0; + *me = clz64(lsb); + return true; + } + /* Accept 0..01..1. */ + if (lsb == 1 && (c & (c + 1)) == 0) { + *mb = clz64(c + 1) + 1; + *me = 63; + return true; + } + return false; +} + +static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) +{ + int mb, me; + + if (mask_operand(c, &mb, &me)) { + tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); + } else if ((c & 0xffff) == c) { + tcg_out32(s, ANDI | SAI(src, dst, c)); + return; + } else if ((c & 0xffff0000) == c) { + tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); + return; + } else { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); + tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); + } +} + +static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) +{ + int mb, me; + + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); + if (mask64_operand(c, &mb, &me)) { + if (mb == 0) { + tcg_out_rld(s, RLDICR, dst, src, 0, me); + } else { + tcg_out_rld(s, RLDICL, dst, src, 0, mb); + } + } else if ((c & 0xffff) == c) { + tcg_out32(s, ANDI | SAI(src, dst, c)); + return; + } else if ((c & 0xffff0000) == c) { + tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); + return; + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); + tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); + } +} + +static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, + int op_lo, int op_hi) +{ + if (c >> 16) { + tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); + src = dst; + } + if (c & 0xffff) { + tcg_out32(s, op_lo | SAI(src, dst, c)); + src = dst; + } +} + +static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) +{ + tcg_out_zori32(s, dst, src, c, ORI, ORIS); +} + +static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) +{ + tcg_out_zori32(s, dst, src, c, XORI, XORIS); +} + +static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) +{ + ptrdiff_t disp = tcg_pcrel_diff(s, target); + if (in_range_b(disp)) { + tcg_out32(s, B | (disp & 0x3fffffc) | mask); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); + tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS | mask); + } +} + +static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, + TCGReg base, tcg_target_long offset) +{ + tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; + bool is_int_store = false; + TCGReg rs = TCG_REG_TMP1; + + switch (opi) { + case LD: case LWA: + align = 3; + /* FALLTHRU */ + default: + if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { + rs = rt; + break; + } + break; + case LXSD: + case STXSD: + align = 3; + break; + case LXV: + case STXV: + align = 15; + break; + case STD: + align = 3; + /* FALLTHRU */ + case STB: case STH: case STW: + is_int_store = true; + break; + } + + /* For unaligned, or very large offsets, use the indexed form. */ + if (offset & align || offset != (int32_t)offset || opi == 0) { + if (rs == base) { + rs = TCG_REG_R0; + } + tcg_debug_assert(!is_int_store || rs != rt); + tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); + tcg_out32(s, opx | TAB(rt & 31, base, rs)); + return; + } + + l0 = (int16_t)offset; + offset = (offset - l0) >> 16; + l1 = (int16_t)offset; + + if (l1 < 0 && orig >= 0) { + extra = 0x4000; + l1 = (int16_t)(offset - 0x4000); + } + if (l1) { + tcg_out32(s, ADDIS | TAI(rs, base, l1)); + base = rs; + } + if (extra) { + tcg_out32(s, ADDIS | TAI(rs, base, extra)); + base = rs; + } + if (opi != ADDI || base != rt || l0 != 0) { + tcg_out32(s, opi | TAI(rt & 31, base, l0)); + } +} + +static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, + TCGReg va, TCGReg vb, int shb) +{ + tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg base, intptr_t offset) +{ + int shift; + + switch (type) { + case TCG_TYPE_I32: + if (ret < TCG_REG_V0) { + tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); + break; + } + if (have_isa_2_07 && have_vsx) { + tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); + break; + } + tcg_debug_assert((offset & 3) == 0); + tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); + shift = (offset - 4) & 0xc; + if (shift) { + tcg_out_vsldoi(s, ret, ret, ret, shift); + } + break; + case TCG_TYPE_I64: + if (ret < TCG_REG_V0) { + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); + tcg_out_mem_long(s, LD, LDX, ret, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(ret >= TCG_REG_V0); + if (have_vsx) { + tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, + ret, base, offset); + break; + } + tcg_debug_assert((offset & 7) == 0); + tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); + if (offset & 8) { + tcg_out_vsldoi(s, ret, ret, ret, 8); + } + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >= TCG_REG_V0); + tcg_debug_assert((offset & 15) == 0); + tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, + LVX, ret, base, offset); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg base, intptr_t offset) +{ + int shift; + + switch (type) { + case TCG_TYPE_I32: + if (arg < TCG_REG_V0) { + tcg_out_mem_long(s, STW, STWX, arg, base, offset); + break; + } + if (have_isa_2_07 && have_vsx) { + tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); + break; + } + assert((offset & 3) == 0); + tcg_debug_assert((offset & 3) == 0); + shift = (offset - 4) & 0xc; + if (shift) { + tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); + arg = TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); + break; + case TCG_TYPE_I64: + if (arg < TCG_REG_V0) { + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); + tcg_out_mem_long(s, STD, STDX, arg, base, offset); + break; + } + /* fallthru */ + case TCG_TYPE_V64: + tcg_debug_assert(arg >= TCG_REG_V0); + if (have_vsx) { + tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, + STXSDX, arg, base, offset); + break; + } + tcg_debug_assert((offset & 7) == 0); + if (offset & 8) { + tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); + arg = TCG_VEC_TMP1; + } + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); + tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); + break; + case TCG_TYPE_V128: + tcg_debug_assert(arg >= TCG_REG_V0); + tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, + STVX, arg, base, offset); + break; + default: + g_assert_not_reached(); + } +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + return false; +} + +static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, + int const_arg2, int cr, TCGType type) +{ + int imm; + uint32_t op; + + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + + /* Simplify the comparisons below wrt CMPI. */ + if (type == TCG_TYPE_I32) { + arg2 = (int32_t)arg2; + } + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + if (const_arg2) { + if ((int16_t) arg2 == arg2) { + op = CMPI; + imm = 1; + break; + } else if ((uint16_t) arg2 == arg2) { + op = CMPLI; + imm = 1; + break; + } + } + op = CMPL; + imm = 0; + break; + + case TCG_COND_LT: + case TCG_COND_GE: + case TCG_COND_LE: + case TCG_COND_GT: + if (const_arg2) { + if ((int16_t) arg2 == arg2) { + op = CMPI; + imm = 1; + break; + } + } + op = CMP; + imm = 0; + break; + + case TCG_COND_LTU: + case TCG_COND_GEU: + case TCG_COND_LEU: + case TCG_COND_GTU: + if (const_arg2) { + if ((uint16_t) arg2 == arg2) { + op = CMPLI; + imm = 1; + break; + } + } + op = CMPL; + imm = 0; + break; + + default: + tcg_abort(); + } + op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); + + if (imm) { + tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); + } else { + if (const_arg2) { + tcg_out_movi(s, type, TCG_REG_R0, arg2); + arg2 = TCG_REG_R0; + } + tcg_out32(s, op | RA(arg1) | RB(arg2)); + } +} + +static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, + TCGReg dst, TCGReg src) +{ + if (type == TCG_TYPE_I32) { + tcg_out32(s, CNTLZW | RS(src) | RA(dst)); + tcg_out_shri32(s, dst, dst, 5); + } else { + tcg_out32(s, CNTLZD | RS(src) | RA(dst)); + tcg_out_shri64(s, dst, dst, 6); + } +} + +static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) +{ + /* X != 0 implies X + -1 generates a carry. Extra addition + trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ + if (dst != src) { + tcg_out32(s, ADDIC | TAI(dst, src, -1)); + tcg_out32(s, SUBFE | TAB(dst, dst, src)); + } else { + tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); + tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); + } +} + +static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, + bool const_arg2) +{ + if (const_arg2) { + if ((uint32_t)arg2 == arg2) { + tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); + } else { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); + tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); + } + } else { + tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); + } + return TCG_REG_R0; +} + +static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, + TCGArg arg0, TCGArg arg1, TCGArg arg2, + int const_arg2) +{ + int crop, sh; + + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); + + /* Ignore high bits of a potential constant arg2. */ + if (type == TCG_TYPE_I32) { + arg2 = (uint32_t)arg2; + } + + /* Handle common and trivial cases before handling anything else. */ + if (arg2 == 0) { + switch (cond) { + case TCG_COND_EQ: + tcg_out_setcond_eq0(s, type, arg0, arg1); + return; + case TCG_COND_NE: + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + tcg_out_ext32u(s, TCG_REG_R0, arg1); + arg1 = TCG_REG_R0; + } + tcg_out_setcond_ne0(s, arg0, arg1); + return; + case TCG_COND_GE: + tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); + arg1 = arg0; + /* FALLTHRU */ + case TCG_COND_LT: + /* Extract the sign bit. */ + if (type == TCG_TYPE_I32) { + tcg_out_shri32(s, arg0, arg1, 31); + } else { + tcg_out_shri64(s, arg0, arg1, 63); + } + return; + default: + break; + } + } + + /* If we have ISEL, we can implement everything with 3 or 4 insns. + All other cases below are also at least 3 insns, so speed up the + code generator by not considering them and always using ISEL. */ + if (have_isel) { + int isel, tab; + + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + + isel = tcg_to_isel[cond]; + + tcg_out_movi(s, type, arg0, 1); + if (isel & 1) { + /* arg0 = (bc ? 0 : 1) */ + tab = TAB(arg0, 0, arg0); + isel &= ~1; + } else { + /* arg0 = (bc ? 1 : 0) */ + tcg_out_movi(s, type, TCG_REG_R0, 0); + tab = TAB(arg0, arg0, TCG_REG_R0); + } + tcg_out32(s, isel | tab); + return; + } + + switch (cond) { + case TCG_COND_EQ: + arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); + tcg_out_setcond_eq0(s, type, arg0, arg1); + return; + + case TCG_COND_NE: + arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); + /* Discard the high bits only once, rather than both inputs. */ + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + tcg_out_ext32u(s, TCG_REG_R0, arg1); + arg1 = TCG_REG_R0; + } + tcg_out_setcond_ne0(s, arg0, arg1); + return; + + case TCG_COND_GT: + case TCG_COND_GTU: + sh = 30; + crop = 0; + goto crtest; + + case TCG_COND_LT: + case TCG_COND_LTU: + sh = 29; + crop = 0; + goto crtest; + + case TCG_COND_GE: + case TCG_COND_GEU: + sh = 31; + crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); + goto crtest; + + case TCG_COND_LE: + case TCG_COND_LEU: + sh = 31; + crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); + crtest: + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + if (crop) { + tcg_out32(s, crop); + } + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); + tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); + break; + + default: + tcg_abort(); + } +} + +static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) +{ + if (l->has_value) { + bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr); + } else { + tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); + } + tcg_out32(s, bc); +} + +static void tcg_out_brcond(TCGContext *s, TCGCond cond, + TCGArg arg1, TCGArg arg2, int const_arg2, + TCGLabel *l, TCGType type) +{ + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_bc(s, tcg_to_bc[cond], l); +} + +static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, + TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, + TCGArg v2, bool const_c2) +{ + /* If for some reason both inputs are zero, don't produce bad code. */ + if (v1 == 0 && v2 == 0) { + tcg_out_movi(s, type, dest, 0); + return; + } + + tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); + + if (have_isel) { + int isel = tcg_to_isel[cond]; + + /* Swap the V operands if the operation indicates inversion. */ + if (isel & 1) { + int t = v1; + v1 = v2; + v2 = t; + isel &= ~1; + } + /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ + if (v2 == 0) { + tcg_out_movi(s, type, TCG_REG_R0, 0); + } + tcg_out32(s, isel | TAB(dest, v1, v2)); + } else { + if (dest == v2) { + cond = tcg_invert_cond(cond); + v2 = v1; + } else if (dest != v1) { + if (v1 == 0) { + tcg_out_movi(s, type, dest, 0); + } else { + tcg_out_mov(s, type, dest, v1); + } + } + /* Branch forward over one insn */ + tcg_out32(s, tcg_to_bc[cond] | 8); + if (v2 == 0) { + tcg_out_movi(s, type, dest, 0); + } else { + tcg_out_mov(s, type, dest, v2); + } + } +} + +static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, + TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) +{ + if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { + tcg_out32(s, opc | RA(a0) | RS(a1)); + } else { + tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); + /* Note that the only other valid constant for a2 is 0. */ + if (have_isel) { + tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); + tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); + } else if (!const_a2 && a0 == a2) { + tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); + tcg_out32(s, opc | RA(a0) | RS(a1)); + } else { + tcg_out32(s, opc | RA(a0) | RS(a1)); + tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); + if (const_a2) { + tcg_out_movi(s, type, a0, 0); + } else { + tcg_out_mov(s, type, a0, a2); + } + } + } +} + +static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + static const struct { uint8_t bit1, bit2; } bits[] = { + [TCG_COND_LT ] = { CR_LT, CR_LT }, + [TCG_COND_LE ] = { CR_LT, CR_GT }, + [TCG_COND_GT ] = { CR_GT, CR_GT }, + [TCG_COND_GE ] = { CR_GT, CR_LT }, + [TCG_COND_LTU] = { CR_LT, CR_LT }, + [TCG_COND_LEU] = { CR_LT, CR_GT }, + [TCG_COND_GTU] = { CR_GT, CR_GT }, + [TCG_COND_GEU] = { CR_GT, CR_LT }, + }; + + TCGCond cond = args[4], cond2; + TCGArg al, ah, bl, bh; + int blconst, bhconst; + int op, bit1, bit2; + + al = args[0]; + ah = args[1]; + bl = args[2]; + bh = args[3]; + blconst = const_args[2]; + bhconst = const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + op = CRAND; + goto do_equality; + case TCG_COND_NE: + op = CRNAND; + do_equality: + tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); + tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); + tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + break; + + case TCG_COND_LT: + case TCG_COND_LE: + case TCG_COND_GT: + case TCG_COND_GE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + bit1 = bits[cond].bit1; + bit2 = bits[cond].bit2; + op = (bit1 != bit2 ? CRANDC : CRAND); + cond2 = tcg_unsigned_cond(cond); + + tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); + tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); + tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); + tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); + break; + + default: + tcg_abort(); + } +} + +static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); + tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); +} + +static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, + const int *const_args) +{ + tcg_out_cmp2(s, args, const_args); + tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); +} + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + uint32_t insn = HWSYNC; + a0 &= TCG_MO_ALL; + if (a0 == TCG_MO_LD_LD) { + insn = LWSYNC; + } else if (a0 == TCG_MO_ST_ST) { + insn = EIEIO; + } + tcg_out32(s, insn); +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + if (TCG_TARGET_REG_BITS == 64) { + tcg_insn_unit i1, i2; + intptr_t tb_diff = addr - tc_ptr; + intptr_t br_diff = addr - (jmp_addr + 4); + uint64_t pair; + + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (tb_diff == (int16_t)tb_diff) { + i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); + i2 = B | (br_diff & 0x3fffffc); + } else { + intptr_t lo = (int16_t)tb_diff; + intptr_t hi = (int32_t)(tb_diff - lo); + assert(tb_diff == hi + lo); + i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); + i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); + } +#ifdef HOST_WORDS_BIGENDIAN + pair = (uint64_t)i1 << 32 | i2; +#else + pair = (uint64_t)i2 << 32 | i1; +#endif + + /* As per the enclosing if, this is ppc64. Avoid the _Static_assert + within atomic_set that would fail to build a ppc32 host. */ + atomic_set__nocheck((uint64_t *)jmp_addr, pair); + flush_icache_range(jmp_addr, jmp_addr + 8); + } else { + intptr_t diff = addr - jmp_addr; + tcg_debug_assert(in_range_b(diff)); + atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); + flush_icache_range(jmp_addr, jmp_addr + 4); + } +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +{ +#ifdef _CALL_AIX + /* Look through the descriptor. If the branch is in range, and we + don't have to spend too much effort on building the toc. */ + void *tgt = ((void **)target)[0]; + uintptr_t toc = ((uintptr_t *)target)[1]; + intptr_t diff = tcg_pcrel_diff(s, tgt); + + if (in_range_b(diff) && toc == (uint32_t)toc) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); + tcg_out_b(s, LK, tgt); + } else { + /* Fold the low bits of the constant into the addresses below. */ + intptr_t arg = (intptr_t)target; + int ofs = (int16_t)arg; + + if (ofs + 8 < 0x8000) { + arg -= ofs; + } else { + ofs = 0; + } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); + tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); + tcg_out32(s, BCCTR | BO_ALWAYS | LK); + } +#elif defined(_CALL_ELF) && _CALL_ELF == 2 + intptr_t diff; + + /* In the ELFv2 ABI, we have to set up r12 to contain the destination + address, which the callee uses to compute its TOC address. */ + /* FIXME: when the branch is in range, we could avoid r12 load if we + knew that the destination uses the same TOC, and what its local + entry point offset is. */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); + + diff = tcg_pcrel_diff(s, target); + if (in_range_b(diff)) { + tcg_out_b(s, LK, target); + } else { + tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS | LK); + } +#else + tcg_out_b(s, LK, target); +#endif +} + +static const uint32_t qemu_ldx_opc[16] = { + [MO_UB] = LBZX, + [MO_UW] = LHZX, + [MO_UL] = LWZX, + [MO_Q] = LDX, + [MO_SW] = LHAX, + [MO_SL] = LWAX, + [MO_BSWAP | MO_UB] = LBZX, + [MO_BSWAP | MO_UW] = LHBRX, + [MO_BSWAP | MO_UL] = LWBRX, + [MO_BSWAP | MO_Q] = LDBRX, +}; + +static const uint32_t qemu_stx_opc[16] = { + [MO_UB] = STBX, + [MO_UW] = STHX, + [MO_UL] = STWX, + [MO_Q] = STDX, + [MO_BSWAP | MO_UB] = STBX, + [MO_BSWAP | MO_UW] = STHBRX, + [MO_BSWAP | MO_UL] = STWBRX, + [MO_BSWAP | MO_Q] = STDBRX, +}; + +static const uint32_t qemu_exts_opc[4] = { + EXTSB, EXTSH, EXTSW, 0 +}; + +#if defined (CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, + * int mmu_idx, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, int mmu_idx, uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +/* We expect to use a 16-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + +/* Perform the TLB load and compare. Places the result of the comparison + in CR7, loads the addend of the TLB into R3, and returns the register + containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ + +static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, + TCGReg addrlo, TCGReg addrhi, + int mem_index, bool is_read) +{ + int cmp_off + = (is_read + ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + + /* Extract the page index, shifted into place for tlb index. */ + if (TCG_TARGET_REG_BITS == 32) { + tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } + tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + + /* Load the TLB comparator. */ + if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { + uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 + ? LWZUX : LDUX); + tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + } else { + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + } + } + + /* Load the TLB addend for use on the fast path. Do this asap + to minimize any load use delay. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, + offsetof(CPUTLBEntry, addend)); + + /* Clear the non-page, non-alignment bits from the address */ + if (TCG_TARGET_REG_BITS == 32) { + /* We don't support unaligned accesses on 32-bits. + * Preserve the bottom bits and thus trigger a comparison + * failure on unaligned accesses. + */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else { + TCGReg t = addrlo; + + /* If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask = (1 << a_bits) - 1; + unsigned s_mask = (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t = TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (TARGET_LONG_BITS == 32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + /* Zero-extend the address for use in the final address. */ + tcg_out_ext32u(s, TCG_REG_R4, addrlo); + addrlo = TCG_REG_R4; + } else if (a_bits == 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS); + } else { + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); + } + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_I32); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); + tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + } else { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_TL); + } + + return addrlo; +} + +/* Record the context of a call to the out of line helper code for the slow + path for a load or store, so that we can later generate the correct + helper code. */ +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, + TCGReg datalo_reg, TCGReg datahi_reg, + TCGReg addrlo_reg, TCGReg addrhi_reg, + tcg_insn_unit *raddr, tcg_insn_unit *lptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->datalo_reg = datalo_reg; + label->datahi_reg = datahi_reg; + label->addrlo_reg = addrlo_reg; + label->addrhi_reg = addrhi_reg; + label->raddr = raddr; + label->label_ptr[0] = lptr; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + TCGReg hi, lo, arg = TCG_REG_R3; + + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); + + lo = lb->addrlo_reg; + hi = lb->addrhi_reg; + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |= 1; +#endif + tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); + tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); + } else { + /* If the address needed to be zero-extended, we'll have already + placed it in R4. The only remaining case is 64-bit guest. */ + tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); + } + + tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); + tcg_out32(s, MFSPR | RT(arg) | LR); + + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + + lo = lb->datalo_reg; + hi = lb->datahi_reg; + if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { + tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); + tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); + } else if (opc & MO_SIGN) { + uint32_t insn = qemu_exts_opc[opc & MO_SIZE]; + tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); + } else { + tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); + } + + tcg_out_b(s, 0, lb->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + MemOp s_bits = opc & MO_SIZE; + TCGReg hi, lo, arg = TCG_REG_R3; + + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); + + lo = lb->addrlo_reg; + hi = lb->addrhi_reg; + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |= 1; +#endif + tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); + tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); + } else { + /* If the address needed to be zero-extended, we'll have already + placed it in R4. The only remaining case is 64-bit guest. */ + tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); + } + + lo = lb->datalo_reg; + hi = lb->datahi_reg; + if (TCG_TARGET_REG_BITS == 32) { + switch (s_bits) { + case MO_64: +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + arg |= 1; +#endif + tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); + /* FALLTHRU */ + case MO_32: + tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); + break; + default: + tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); + break; + } + } else { + if (s_bits == MO_64) { + tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); + } else { + tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); + } + } + + tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); + tcg_out32(s, MFSPR | RT(arg) | LR); + + tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + + tcg_out_b(s, 0, lb->raddr); + return true; +} +#endif /* SOFTMMU */ + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg datalo, datahi, addrlo, rbase; + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc, s_bits; +#ifdef CONFIG_SOFTMMU + int mem_index; + tcg_insn_unit *label_ptr; +#endif + + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + s_bits = opc & MO_SIZE; + +#ifdef CONFIG_SOFTMMU + mem_index = get_mmuidx(oi); + addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + + /* Load a pointer into the current opcode w/conditional branch-link. */ + label_ptr = s->code_ptr; + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + + rbase = TCG_REG_R3; +#else /* !CONFIG_SOFTMMU */ + rbase = guest_base ? TCG_GUEST_BASE_REG : 0; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + addrlo = TCG_REG_TMP1; + } +#endif + + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { + if (opc & MO_BSWAP) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); + tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); + tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); + } else if (rbase != 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); + tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); + tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); + } else if (addrlo == datahi) { + tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); + tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); + } else { + tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); + tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); + } + } else { + uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; + if (!have_isa_2_06 && insn == LDBRX) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); + tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); + tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); + tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); + } else if (insn) { + tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + } else { + insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; + tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + insn = qemu_exts_opc[s_bits]; + tcg_out32(s, insn | RA(datalo) | RS(datalo)); + } + } + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#endif +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg datalo, datahi, addrlo, rbase; + TCGReg addrhi __attribute__((unused)); + TCGMemOpIdx oi; + MemOp opc, s_bits; +#ifdef CONFIG_SOFTMMU + int mem_index; + tcg_insn_unit *label_ptr; +#endif + + datalo = *args++; + datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addrlo = *args++; + addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + s_bits = opc & MO_SIZE; + +#ifdef CONFIG_SOFTMMU + mem_index = get_mmuidx(oi); + addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + + /* Load a pointer into the current opcode w/conditional branch-link. */ + label_ptr = s->code_ptr; + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + + rbase = TCG_REG_R3; +#else /* !CONFIG_SOFTMMU */ + rbase = guest_base ? TCG_GUEST_BASE_REG : 0; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + addrlo = TCG_REG_TMP1; + } +#endif + + if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { + if (opc & MO_BSWAP) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); + tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); + tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); + } else if (rbase != 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); + tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); + tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); + } else { + tcg_out32(s, STW | TAI(datahi, addrlo, 0)); + tcg_out32(s, STW | TAI(datalo, addrlo, 4)); + } + } else { + uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; + if (!have_isa_2_06 && insn == STDBRX) { + tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); + tcg_out_shri64(s, TCG_REG_R0, datalo, 32); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); + } else { + tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); + } + } + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); +#endif +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + +/* Parameters for function call generation, used in tcg.c. */ +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_EXTEND_ARGS 1 + +#ifdef _CALL_AIX +# define LINK_AREA_SIZE (6 * SZR) +# define LR_OFFSET (1 * SZR) +# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) +#elif defined(TCG_TARGET_CALL_DARWIN) +# define LINK_AREA_SIZE (6 * SZR) +# define LR_OFFSET (2 * SZR) +#elif TCG_TARGET_REG_BITS == 64 +# if defined(_CALL_ELF) && _CALL_ELF == 2 +# define LINK_AREA_SIZE (4 * SZR) +# define LR_OFFSET (1 * SZR) +# endif +#else /* TCG_TARGET_REG_BITS == 32 */ +# if defined(_CALL_SYSV) +# define LINK_AREA_SIZE (2 * SZR) +# define LR_OFFSET (1 * SZR) +# endif +#endif +#ifndef LR_OFFSET +# error "Unhandled abi" +#endif +#ifndef TCG_TARGET_CALL_STACK_OFFSET +# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE +#endif + +#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) + +#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_SIZE \ + + REG_SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) + +#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) + +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + +#ifdef _CALL_AIX + void **desc = (void **)s->code_ptr; + desc[0] = desc + 2; /* entry point */ + desc[1] = 0; /* environment pointer */ + s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ +#endif + + tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, + CPU_TEMP_BUF_SIZE); + + /* Prologue */ + tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); + tcg_out32(s, (SZR == 8 ? STDU : STWU) + | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); + + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_R1, REG_SAVE_BOT + i * SZR); + } + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); + +#ifndef CONFIG_SOFTMMU + if (guest_base) { + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } +#endif + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); + } + tcg_out32(s, BCCTR | BO_ALWAYS); + + /* Epilogue */ + s->code_gen_epilogue = tb_ret_addr = s->code_ptr; + + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_R1, REG_SAVE_BOT + i * SZR); + } + tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); + tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); + tcg_out32(s, BCLR | BO_ALWAYS); +} + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, + const int *const_args) +{ + TCGArg a0, a1, a2; + int c; + + switch (opc) { + case INDEX_op_exit_tb: + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); + tcg_out_b(s, 0, tb_ret_addr); + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* Direct jump. */ + if (TCG_TARGET_REG_BITS == 64) { + /* Ensure the next insns are 8-byte aligned. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + } else { + s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + tcg_out32(s, B); + s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + break; + } + } else { + /* Indirect jump. */ + tcg_debug_assert(s->tb_jmp_insn_offset == NULL); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, + (intptr_t)(s->tb_jmp_insn_offset + args[0])); + } + tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS); + set_jmp_reset_offset(s, args[0]); + if (USE_REG_TB) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + c = -tcg_current_code_size(s); + assert(c == (int16_t)c); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); + } + break; + case INDEX_op_goto_ptr: + tcg_out32(s, MTSPR | RS(args[0]) | CTR); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + } + tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); + tcg_out32(s, BCCTR | BO_ALWAYS); + break; + case INDEX_op_br: + { + TCGLabel *l = arg_label(args[0]); + uint32_t insn = B; + + if (l->has_value) { + insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr); + } else { + tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); + } + tcg_out32(s, insn); + } + break; + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + break; + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); + tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); + break; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); + break; + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); + break; + case INDEX_op_ld32s_i64: + tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); + break; + case INDEX_op_ld_i64: + tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); + break; + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); + break; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); + break; + case INDEX_op_st_i64: + tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); + break; + + case INDEX_op_add_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + do_addi_32: + tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); + } else { + tcg_out32(s, ADD | TAB(a0, a1, a2)); + } + break; + case INDEX_op_sub_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); + } else { + tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); + } + } else if (const_args[2]) { + a2 = -a2; + goto do_addi_32; + } else { + tcg_out32(s, SUBF | TAB(a0, a2, a1)); + } + break; + + case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, a2); + } else { + tcg_out32(s, AND | SAB(a1, a0, a2)); + } + break; + case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, a2); + } else { + tcg_out32(s, AND | SAB(a1, a0, a2)); + } + break; + case INDEX_op_or_i64: + case INDEX_op_or_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_ori32(s, a0, a1, a2); + } else { + tcg_out32(s, OR | SAB(a1, a0, a2)); + } + break; + case INDEX_op_xor_i64: + case INDEX_op_xor_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_xori32(s, a0, a1, a2); + } else { + tcg_out32(s, XOR | SAB(a1, a0, a2)); + } + break; + case INDEX_op_andc_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; + case INDEX_op_andc_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; + case INDEX_op_orc_i32: + if (const_args[2]) { + tcg_out_ori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ + case INDEX_op_orc_i64: + tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_eqv_i32: + if (const_args[2]) { + tcg_out_xori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ + case INDEX_op_eqv_i64: + tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + break; + + case INDEX_op_clz_i32: + tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_ctz_i32: + tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_ctpop_i32: + tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); + break; + + case INDEX_op_clz_i64: + tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_ctz_i64: + tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_ctpop_i64: + tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); + break; + + case INDEX_op_mul_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLW | TAB(a0, a1, a2)); + } + break; + + case INDEX_op_div_i32: + tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); + break; + + case INDEX_op_divu_i32: + tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); + break; + + case INDEX_op_shl_i32: + if (const_args[2]) { + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_shli32(s, args[0], args[1], args[2] & 31); + } else { + tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_shr_i32: + if (const_args[2]) { + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_shri32(s, args[0], args[1], args[2] & 31); + } else { + tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_sar_i32: + if (const_args[2]) { + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31)); + } else { + tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_rotl_i32: + if (const_args[2]) { + tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); + } else { + tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) + | MB(0) | ME(31)); + } + break; + case INDEX_op_rotr_i32: + if (const_args[2]) { + tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); + } else { + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); + tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) + | MB(0) | ME(31)); + } + break; + + case INDEX_op_brcond_i32: + tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + arg_label(args[3]), TCG_TYPE_I32); + break; + case INDEX_op_brcond_i64: + tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], + arg_label(args[3]), TCG_TYPE_I64); + break; + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args, const_args); + break; + + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); + break; + + case INDEX_op_not_i32: + case INDEX_op_not_i64: + tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); + break; + + case INDEX_op_add_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + do_addi_64: + tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); + } else { + tcg_out32(s, ADD | TAB(a0, a1, a2)); + } + break; + case INDEX_op_sub_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); + } else { + tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); + } + } else if (const_args[2]) { + a2 = -a2; + goto do_addi_64; + } else { + tcg_out32(s, SUBF | TAB(a0, a2, a1)); + } + break; + + case INDEX_op_shl_i64: + if (const_args[2]) { + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_shli64(s, args[0], args[1], args[2] & 63); + } else { + tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_shr_i64: + if (const_args[2]) { + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_shri64(s, args[0], args[1], args[2] & 63); + } else { + tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_sar_i64: + if (const_args[2]) { + int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); + tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); + } else { + tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); + } + break; + case INDEX_op_rotl_i64: + if (const_args[2]) { + tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); + } else { + tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); + } + break; + case INDEX_op_rotr_i64: + if (const_args[2]) { + tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); + } else { + tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); + tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); + } + break; + + case INDEX_op_mul_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLD | TAB(a0, a1, a2)); + } + break; + case INDEX_op_div_i64: + tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); + break; + case INDEX_op_divu_i64: + tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, true); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, false); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, true); + break; + + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + c = EXTSB; + goto gen_ext; + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + c = EXTSH; + goto gen_ext; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + c = EXTSW; + goto gen_ext; + gen_ext: + tcg_out32(s, c | RS(args[1]) | RA(args[0])); + break; + case INDEX_op_extu_i32_i64: + tcg_out_ext32u(s, args[0], args[1]); + break; + + case INDEX_op_setcond_i32: + tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], + const_args[2]); + break; + case INDEX_op_setcond_i64: + tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], + const_args[2]); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args, const_args); + break; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + a0 = args[0], a1 = args[1]; + /* a1 = abcd */ + if (a0 != a1) { + /* a0 = (a1 r<< 24) & 0xff # 000c */ + tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); + /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */ + tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23); + } else { + /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */ + tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23); + /* a0 = (a1 r<< 24) & 0xff # 000c */ + tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); + /* a0 = a0 | r0 # 00dc */ + tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0)); + } + break; + + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + /* Stolen from gcc's builtin_bswap32 */ + a1 = args[1]; + a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; + + /* a1 = args[1] # abcd */ + /* a0 = rotate_left (a1, 8) # bcda */ + tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); + /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); + /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */ + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); + + if (a0 == TCG_REG_R0) { + tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + } + break; + + case INDEX_op_bswap64_i64: + a0 = args[0], a1 = args[1], a2 = TCG_REG_R0; + if (a0 == a1) { + a0 = TCG_REG_R0; + a2 = a1; + } + + /* a1 = # abcd efgh */ + /* a0 = rl32(a1, 8) # 0000 fghe */ + tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); + /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */ + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); + /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */ + tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); + + /* a0 = rl64(a0, 32) # hgfe 0000 */ + /* a2 = rl64(a1, 32) # efgh abcd */ + tcg_out_rld(s, RLDICL, a0, a0, 32, 0); + tcg_out_rld(s, RLDICL, a2, a1, 32, 0); + + /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */ + tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31); + /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */ + tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7); + /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */ + tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23); + + if (a0 == 0) { + tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + } + break; + + case INDEX_op_deposit_i32: + if (const_args[2]) { + uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi32(s, args[0], args[0], ~mask); + } else { + tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + 32 - args[3] - args[4], 31 - args[3]); + } + break; + case INDEX_op_deposit_i64: + if (const_args[2]) { + uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi64(s, args[0], args[0], ~mask); + } else { + tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], + 64 - args[3] - args[4]); + } + break; + + case INDEX_op_extract_i32: + tcg_out_rlw(s, RLWINM, args[0], args[1], + 32 - args[2], 32 - args[3], 31); + break; + case INDEX_op_extract_i64: + tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); + break; + + case INDEX_op_movcond_i32: + tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], + args[3], args[4], const_args[2]); + break; + case INDEX_op_movcond_i64: + tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], + args[3], args[4], const_args[2]); + break; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_add2_i64: +#else + case INDEX_op_add2_i32: +#endif + /* Note that the CA bit is defined based on the word size of the + environment. So in 64-bit mode it's always carry-out of bit 63. + The fallback code using deposit works just as well for 32-bit. */ + a0 = args[0], a1 = args[1]; + if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { + a0 = TCG_REG_R0; + } + if (const_args[4]) { + tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); + } else { + tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); + } + if (const_args[5]) { + tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); + } else { + tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); + } + if (a0 != args[0]) { + tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + } + break; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_sub2_i64: +#else + case INDEX_op_sub2_i32: +#endif + a0 = args[0], a1 = args[1]; + if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { + a0 = TCG_REG_R0; + } + if (const_args[2]) { + tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); + } else { + tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); + } + if (const_args[3]) { + tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); + } else { + tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); + } + if (a0 != args[0]) { + tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); + } + break; + + case INDEX_op_muluh_i32: + tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); + break; + case INDEX_op_mulsh_i32: + tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + break; + case INDEX_op_muluh_i64: + tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); + break; + case INDEX_op_mulsh_i64: + tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); + break; + + case INDEX_op_mb: + tcg_out_mb(s, args[0]); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + switch (opc) { + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_not_vec: + return 1; + case INDEX_op_orc_vec: + return have_isa_2_07; + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + return vece <= MO_32 || have_isa_2_07; + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + return vece <= MO_32; + case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: + case INDEX_op_rotli_vec: + return vece <= MO_32 || have_isa_2_07 ? -1 : 0; + case INDEX_op_neg_vec: + return vece >= MO_32 && have_isa_3_00; + case INDEX_op_mul_vec: + switch (vece) { + case MO_8: + case MO_16: + return -1; + case MO_32: + return have_isa_2_07 ? 1 : -1; + } + return 0; + case INDEX_op_bitsel_vec: + return have_vsx; + case INDEX_op_rotrv_vec: + return -1; + default: + return 0; + } +} + +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + tcg_debug_assert(dst >= TCG_REG_V0); + + /* Splat from integer reg allowed via constraints for v3.00. */ + if (src < TCG_REG_V0) { + tcg_debug_assert(have_isa_3_00); + switch (vece) { + case MO_64: + tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); + return true; + case MO_32: + tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); + return true; + default: + /* Fail, so that we fall back on either dupm or mov+dup. */ + return false; + } + } + + /* + * Recall we use (or emulate) VSX integer loads, so the integer is + * right justified within the left (zero-index) double-word. + */ + switch (vece) { + case MO_8: + tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); + break; + case MO_16: + tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); + break; + case MO_32: + tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); + break; + case MO_64: + if (have_vsx) { + tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); + break; + } + tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); + tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg out, TCGReg base, intptr_t offset) +{ + int elt; + + tcg_debug_assert(out >= TCG_REG_V0); + switch (vece) { + case MO_8: + if (have_isa_3_00) { + tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); + } else { + tcg_out_mem_long(s, 0, LVEBX, out, base, offset); + } + elt = extract32(offset, 0, 4); +#ifndef HOST_WORDS_BIGENDIAN + elt ^= 15; +#endif + tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_16: + tcg_debug_assert((offset & 1) == 0); + if (have_isa_3_00) { + tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); + } else { + tcg_out_mem_long(s, 0, LVEHX, out, base, offset); + } + elt = extract32(offset, 1, 3); +#ifndef HOST_WORDS_BIGENDIAN + elt ^= 7; +#endif + tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_32: + if (have_isa_3_00) { + tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); + break; + } + tcg_debug_assert((offset & 3) == 0); + tcg_out_mem_long(s, 0, LVEWX, out, base, offset); + elt = extract32(offset, 2, 2); +#ifndef HOST_WORDS_BIGENDIAN + elt ^= 3; +#endif + tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); + break; + case MO_64: + if (have_vsx) { + tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); + break; + } + tcg_debug_assert((offset & 7) == 0); + tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); + tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); + elt = extract32(offset, 3, 1); +#ifndef HOST_WORDS_BIGENDIAN + elt = !elt; +#endif + if (elt) { + tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); + } else { + tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); + } + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + static const uint32_t + add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, + sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, + neg_op[4] = { 0, 0, VNEGW, VNEGD }, + eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, + ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, + gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, + gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, + ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, + usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, + sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, + ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, + umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, + smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, + umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, + smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, + shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, + shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, + sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, + mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, + mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, + muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, + mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, + pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, + rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; + + TCGType type = vecl + TCG_TYPE_V64; + TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; + uint32_t insn; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + return; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + return; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + return; + + case INDEX_op_add_vec: + insn = add_op[vece]; + break; + case INDEX_op_sub_vec: + insn = sub_op[vece]; + break; + case INDEX_op_neg_vec: + insn = neg_op[vece]; + a2 = a1; + a1 = 0; + break; + case INDEX_op_mul_vec: + tcg_debug_assert(vece == MO_32 && have_isa_2_07); + insn = VMULUWM; + break; + case INDEX_op_ssadd_vec: + insn = ssadd_op[vece]; + break; + case INDEX_op_sssub_vec: + insn = sssub_op[vece]; + break; + case INDEX_op_usadd_vec: + insn = usadd_op[vece]; + break; + case INDEX_op_ussub_vec: + insn = ussub_op[vece]; + break; + case INDEX_op_smin_vec: + insn = smin_op[vece]; + break; + case INDEX_op_umin_vec: + insn = umin_op[vece]; + break; + case INDEX_op_smax_vec: + insn = smax_op[vece]; + break; + case INDEX_op_umax_vec: + insn = umax_op[vece]; + break; + case INDEX_op_shlv_vec: + insn = shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn = shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn = sarv_op[vece]; + break; + case INDEX_op_and_vec: + insn = VAND; + break; + case INDEX_op_or_vec: + insn = VOR; + break; + case INDEX_op_xor_vec: + insn = VXOR; + break; + case INDEX_op_andc_vec: + insn = VANDC; + break; + case INDEX_op_not_vec: + insn = VNOR; + a2 = a1; + break; + case INDEX_op_orc_vec: + insn = VORC; + break; + + case INDEX_op_cmp_vec: + switch (args[3]) { + case TCG_COND_EQ: + insn = eq_op[vece]; + break; + case TCG_COND_NE: + insn = ne_op[vece]; + break; + case TCG_COND_GT: + insn = gts_op[vece]; + break; + case TCG_COND_GTU: + insn = gtu_op[vece]; + break; + default: + g_assert_not_reached(); + } + break; + + case INDEX_op_bitsel_vec: + tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); + return; + + case INDEX_op_dup2_vec: + assert(TCG_TARGET_REG_BITS == 32); + /* With inputs a1 = xLxx, a2 = xHxx */ + tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ + tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ + tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ + return; + + case INDEX_op_ppc_mrgh_vec: + insn = mrgh_op[vece]; + break; + case INDEX_op_ppc_mrgl_vec: + insn = mrgl_op[vece]; + break; + case INDEX_op_ppc_muleu_vec: + insn = muleu_op[vece]; + break; + case INDEX_op_ppc_mulou_vec: + insn = mulou_op[vece]; + break; + case INDEX_op_ppc_pkum_vec: + insn = pkum_op[vece]; + break; + case INDEX_op_rotlv_vec: + insn = rotl_op[vece]; + break; + case INDEX_op_ppc_msum_vec: + tcg_debug_assert(vece == MO_16); + tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); + return; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } + + tcg_debug_assert(insn != 0); + tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); +} + +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 = tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap = false, need_inv = false; + + tcg_debug_assert(vece <= MO_32 || have_isa_2_07); + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + if (have_isa_3_00 && vece <= MO_32) { + break; + } + /* fall through */ + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv = true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap = true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap = need_inv = true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond = tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 = v1, v1 = v2, v2 = t1; + cond = tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + if (need_inv) { + tcg_gen_not_vec(vece, v0, v0); + } +} + +static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2) +{ + TCGv_vec t1 = tcg_temp_new_vec(type); + TCGv_vec t2 = tcg_temp_new_vec(type); + TCGv_vec t3, t4; + + switch (vece) { + case MO_8: + case MO_16: + vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v0), tcgv_vec_arg(t1)); + break; + + case MO_32: + tcg_debug_assert(!have_isa_2_07); + t3 = tcg_temp_new_vec(type); + t4 = tcg_temp_new_vec(type); + tcg_gen_dupi_vec(MO_8, t4, -16); + vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_dupi_vec(MO_8, t3, 0); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), + tcgv_vec_arg(t3), tcgv_vec_arg(t4)); + tcg_gen_add_vec(MO_32, v0, t2, t3); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + va_list va; + TCGv_vec v0, v1, v2, t0; + TCGArg a2; + + va_start(va, a0); + v0 = temp_tcgv_vec(arg_temp(a0)); + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 = va_arg(va, TCGArg); + + switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; + case INDEX_op_rotli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); + break; + case INDEX_op_cmp_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + case INDEX_op_mul_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; + case INDEX_op_rotlv_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); + t0 = tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; + default: + g_assert_not_reached(); + } + va_end(va); +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } }; + static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; + static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; + static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; + static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; + static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; + static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } }; + static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } }; + static const TCGTargetOpDef r_rI_ri + = { .args_ct_str = { "r", "rI", "ri" } }; + static const TCGTargetOpDef r_rI_rT + = { .args_ct_str = { "r", "rI", "rT" } }; + static const TCGTargetOpDef r_r_rZW + = { .args_ct_str = { "r", "r", "rZW" } }; + static const TCGTargetOpDef L_L_L_L + = { .args_ct_str = { "L", "L", "L", "L" } }; + static const TCGTargetOpDef S_S_S_S + = { .args_ct_str = { "S", "S", "S", "S" } }; + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } }; + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "0", "rZ" } }; + static const TCGTargetOpDef br2 + = { .args_ct_str = { "r", "r", "ri", "ri" } }; + static const TCGTargetOpDef setc2 + = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; + static const TCGTargetOpDef add2 + = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } }; + static const TCGTargetOpDef sub2 + = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } }; + static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } }; + static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } }; + static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } }; + static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } }; + static const TCGTargetOpDef v_v_v_v + = { .args_ct_str = { "v", "v", "v", "v" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_ctpop_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_extract_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + case INDEX_op_ctpop_i64: + case INDEX_op_neg_i64: + case INDEX_op_not_i64: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_andc_i32: + case INDEX_op_orc_i32: + case INDEX_op_eqv_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + case INDEX_op_setcond_i32: + case INDEX_op_and_i64: + case INDEX_op_andc_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + case INDEX_op_setcond_i64: + return &r_r_ri; + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + return &r_r_rI; + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_nand_i32: + case INDEX_op_nor_i32: + case INDEX_op_muluh_i32: + case INDEX_op_mulsh_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i64: + case INDEX_op_nand_i64: + case INDEX_op_nor_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_mulsh_i64: + case INDEX_op_muluh_i64: + return &r_r_r; + case INDEX_op_sub_i32: + return &r_rI_ri; + case INDEX_op_add_i64: + return &r_r_rT; + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + return &r_r_rU; + case INDEX_op_sub_i64: + return &r_rI_rT; + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i64: + return &r_r_rZW; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_ri; + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + return &movc; + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return &dep; + case INDEX_op_brcond2_i32: + return &br2; + case INDEX_op_setcond2_i32: + return &setc2; + case INDEX_op_add2_i64: + case INDEX_op_add2_i32: + return &add2; + case INDEX_op_sub2_i64: + case INDEX_op_sub2_i32: + return &sub2; + + case INDEX_op_qemu_ld_i32: + return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 + ? &r_L : &r_L_L); + case INDEX_op_qemu_st_i32: + return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 + ? &S_S : &S_S_S); + case INDEX_op_qemu_ld_i64: + return (TCG_TARGET_REG_BITS == 64 ? &r_L + : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L); + case INDEX_op_qemu_st_i64: + return (TCG_TARGET_REG_BITS == 64 ? &S_S + : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); + + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_mul_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_andc_vec: + case INDEX_op_orc_vec: + case INDEX_op_cmp_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_ppc_mrgh_vec: + case INDEX_op_ppc_mrgl_vec: + case INDEX_op_ppc_muleu_vec: + case INDEX_op_ppc_mulou_vec: + case INDEX_op_ppc_pkum_vec: + case INDEX_op_dup2_vec: + return &v_v_v; + case INDEX_op_not_vec: + case INDEX_op_neg_vec: + return &v_v; + case INDEX_op_dup_vec: + return have_isa_3_00 ? &v_vr : &v_v; + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + case INDEX_op_dupm_vec: + return &v_r; + case INDEX_op_bitsel_vec: + case INDEX_op_ppc_msum_vec: + return &v_v_v_v; + + default: + return NULL; + } +} + +static void tcg_target_init(TCGContext *s) +{ + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); + + have_isa = tcg_isa_base; + if (hwcap & PPC_FEATURE_ARCH_2_06) { + have_isa = tcg_isa_2_06; + } +#ifdef PPC_FEATURE2_ARCH_2_07 + if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { + have_isa = tcg_isa_2_07; + } +#endif +#ifdef PPC_FEATURE2_ARCH_3_00 + if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { + have_isa = tcg_isa_3_00; + } +#endif + +#ifdef PPC_FEATURE2_HAS_ISEL + /* Prefer explicit instruction from the kernel. */ + have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; +#else + /* Fall back to knowing Power7 (2.06) has ISEL. */ + have_isel = have_isa_2_06; +#endif + + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { + have_altivec = true; + /* We only care about the portion of VSX that overlaps Altivec. */ + if (hwcap & PPC_FEATURE_HAS_VSX) { + have_vsx = true; + } + } + + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + if (have_altivec) { + tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + } + + tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); + + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ +#if defined(_CALL_SYSV) + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ +#endif +#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ +#endif + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ + } +} + +#ifdef __ELF__ +typedef struct { + DebugFrameCIE cie; + DebugFrameFDEHeader fde; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; +} DebugFrame; + +/* We're expecting a 2 byte uleb128 encoded value. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); + +#if TCG_TARGET_REG_BITS == 64 +# define ELF_HOST_MACHINE EM_PPC64 +#else +# define ELF_HOST_MACHINE EM_PPC +#endif + +static DebugFrame debug_frame = { + .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .cie.id = -1, + .cie.version = 1, + .cie.code_align = 1, + .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ + .cie.return_column = 65, + + /* Total FDE size does not include the "len" member. */ + .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ + 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + uint8_t *p = &debug_frame.fde_reg_ofs[3]; + int i; + + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { + p[0] = 0x80 + tcg_target_callee_save_regs[i]; + p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; + } + + debug_frame.fde.func_start = (uintptr_t)buf; + debug_frame.fde.func_len = buf_size; + + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} +#endif /* __ELF__ */ + +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p, start1, stop1; + size_t dsize = qemu_dcache_linesize; + size_t isize = qemu_icache_linesize; + + start1 = start & ~(dsize - 1); + stop1 = (stop + dsize - 1) & ~(dsize - 1); + for (p = start1; p < stop1; p += dsize) { + asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + + start &= start & ~(isize - 1); + stop1 = (stop + isize - 1) & ~(isize - 1); + for (p = start1; p < stop1; p += isize) { + asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + asm volatile ("isync" : : : "memory"); +} diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c deleted file mode 100644 index c8d1e765d9..0000000000 --- a/tcg/ppc/tcg-target.inc.c +++ /dev/null @@ -1,3884 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "elf.h" -#include "../tcg-pool.inc.c" - -#if defined _CALL_DARWIN || defined __APPLE__ -#define TCG_TARGET_CALL_DARWIN -#endif -#ifdef _CALL_SYSV -# define TCG_TARGET_CALL_ALIGN_ARGS 1 -#endif - -/* For some memory operations, we need a scratch that isn't R0. For the AIX - calling convention, we can re-use the TOC register since we'll be reloading - it at every call. Otherwise R12 will do nicely as neither a call-saved - register nor a parameter register. */ -#ifdef _CALL_AIX -# define TCG_REG_TMP1 TCG_REG_R2 -#else -# define TCG_REG_TMP1 TCG_REG_R12 -#endif - -#define TCG_VEC_TMP1 TCG_REG_V0 -#define TCG_VEC_TMP2 TCG_REG_V1 - -#define TCG_REG_TB TCG_REG_R31 -#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) - -/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ -#define SZP ((int)sizeof(void *)) - -/* Shorthand for size of a register. */ -#define SZR (TCG_TARGET_REG_BITS / 8) - -#define TCG_CT_CONST_S16 0x100 -#define TCG_CT_CONST_U16 0x200 -#define TCG_CT_CONST_S32 0x400 -#define TCG_CT_CONST_U32 0x800 -#define TCG_CT_CONST_ZERO 0x1000 -#define TCG_CT_CONST_MONE 0x2000 -#define TCG_CT_CONST_WSZ 0x4000 - -static tcg_insn_unit *tb_ret_addr; - -TCGPowerISA have_isa; -static bool have_isel; -bool have_altivec; -bool have_vsx; - -#ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG 30 -#endif - -#ifdef CONFIG_DEBUG_TCG -static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", - "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", - "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", - "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", - "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", -}; -#endif - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R14, /* call saved registers */ - TCG_REG_R15, - TCG_REG_R16, - TCG_REG_R17, - TCG_REG_R18, - TCG_REG_R19, - TCG_REG_R20, - TCG_REG_R21, - TCG_REG_R22, - TCG_REG_R23, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27, - TCG_REG_R28, - TCG_REG_R29, - TCG_REG_R30, - TCG_REG_R31, - TCG_REG_R12, /* call clobbered, non-arguments */ - TCG_REG_R11, - TCG_REG_R2, - TCG_REG_R13, - TCG_REG_R10, /* call clobbered, arguments */ - TCG_REG_R9, - TCG_REG_R8, - TCG_REG_R7, - TCG_REG_R6, - TCG_REG_R5, - TCG_REG_R4, - TCG_REG_R3, - - /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ - TCG_REG_V2, /* call clobbered, vectors */ - TCG_REG_V3, - TCG_REG_V4, - TCG_REG_V5, - TCG_REG_V6, - TCG_REG_V7, - TCG_REG_V8, - TCG_REG_V9, - TCG_REG_V10, - TCG_REG_V11, - TCG_REG_V12, - TCG_REG_V13, - TCG_REG_V14, - TCG_REG_V15, - TCG_REG_V16, - TCG_REG_V17, - TCG_REG_V18, - TCG_REG_V19, -}; - -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10 -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R3, - TCG_REG_R4 -}; - -static const int tcg_target_callee_save_regs[] = { -#ifdef TCG_TARGET_CALL_DARWIN - TCG_REG_R11, -#endif - TCG_REG_R14, - TCG_REG_R15, - TCG_REG_R16, - TCG_REG_R17, - TCG_REG_R18, - TCG_REG_R19, - TCG_REG_R20, - TCG_REG_R21, - TCG_REG_R22, - TCG_REG_R23, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27, /* currently used for the global env */ - TCG_REG_R28, - TCG_REG_R29, - TCG_REG_R30, - TCG_REG_R31 -}; - -static inline bool in_range_b(tcg_target_long target) -{ - return target == sextract64(target, 0, 26); -} - -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - tcg_debug_assert(in_range_b(disp)); - return disp & 0x3fffffc; -} - -static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - if (in_range_b(disp)) { - *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); - return true; - } - return false; -} - -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - tcg_debug_assert(disp == (int16_t) disp); - return disp & 0xfffc; -} - -static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); - if (disp == (int16_t) disp) { - *pc = (*pc & ~0xfffc) | (disp & 0xfffc); - return true; - } - return false; -} - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'A': case 'B': case 'C': case 'D': - ct->ct |= TCG_CT_REG; - tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); - break; - case 'r': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - break; - case 'v': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff00000000ull; - break; - case 'L': /* qemu_ld constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); -#endif - break; - case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); -#ifdef CONFIG_SOFTMMU - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_U16; - break; - case 'M': - ct->ct |= TCG_CT_CONST_MONE; - break; - case 'T': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'U': - ct->ct |= TCG_CT_CONST_U32; - break; - case 'W': - ct->ct |= TCG_CT_CONST_WSZ; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - if (ct & TCG_CT_CONST) { - return 1; - } - - /* The only 32-bit constraint we use aside from - TCG_CT_CONST is TCG_CT_CONST_S16. */ - if (type == TCG_TYPE_I32) { - val = (int32_t)val; - } - - if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { - return 1; - } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { - return 1; - } else if ((ct & TCG_CT_CONST_WSZ) - && val == (type == TCG_TYPE_I32 ? 32 : 64)) { - return 1; - } - return 0; -} - -#define OPCD(opc) ((opc)<<26) -#define XO19(opc) (OPCD(19)|((opc)<<1)) -#define MD30(opc) (OPCD(30)|((opc)<<2)) -#define MDS30(opc) (OPCD(30)|((opc)<<1)) -#define XO31(opc) (OPCD(31)|((opc)<<1)) -#define XO58(opc) (OPCD(58)|(opc)) -#define XO62(opc) (OPCD(62)|(opc)) -#define VX4(opc) (OPCD(4)|(opc)) - -#define B OPCD( 18) -#define BC OPCD( 16) -#define LBZ OPCD( 34) -#define LHZ OPCD( 40) -#define LHA OPCD( 42) -#define LWZ OPCD( 32) -#define LWZUX XO31( 55) -#define STB OPCD( 38) -#define STH OPCD( 44) -#define STW OPCD( 36) - -#define STD XO62( 0) -#define STDU XO62( 1) -#define STDX XO31(149) - -#define LD XO58( 0) -#define LDX XO31( 21) -#define LDU XO58( 1) -#define LDUX XO31( 53) -#define LWA XO58( 2) -#define LWAX XO31(341) - -#define ADDIC OPCD( 12) -#define ADDI OPCD( 14) -#define ADDIS OPCD( 15) -#define ORI OPCD( 24) -#define ORIS OPCD( 25) -#define XORI OPCD( 26) -#define XORIS OPCD( 27) -#define ANDI OPCD( 28) -#define ANDIS OPCD( 29) -#define MULLI OPCD( 7) -#define CMPLI OPCD( 10) -#define CMPI OPCD( 11) -#define SUBFIC OPCD( 8) - -#define LWZU OPCD( 33) -#define STWU OPCD( 37) - -#define RLWIMI OPCD( 20) -#define RLWINM OPCD( 21) -#define RLWNM OPCD( 23) - -#define RLDICL MD30( 0) -#define RLDICR MD30( 1) -#define RLDIMI MD30( 3) -#define RLDCL MDS30( 8) - -#define BCLR XO19( 16) -#define BCCTR XO19(528) -#define CRAND XO19(257) -#define CRANDC XO19(129) -#define CRNAND XO19(225) -#define CROR XO19(449) -#define CRNOR XO19( 33) - -#define EXTSB XO31(954) -#define EXTSH XO31(922) -#define EXTSW XO31(986) -#define ADD XO31(266) -#define ADDE XO31(138) -#define ADDME XO31(234) -#define ADDZE XO31(202) -#define ADDC XO31( 10) -#define AND XO31( 28) -#define SUBF XO31( 40) -#define SUBFC XO31( 8) -#define SUBFE XO31(136) -#define SUBFME XO31(232) -#define SUBFZE XO31(200) -#define OR XO31(444) -#define XOR XO31(316) -#define MULLW XO31(235) -#define MULHW XO31( 75) -#define MULHWU XO31( 11) -#define DIVW XO31(491) -#define DIVWU XO31(459) -#define CMP XO31( 0) -#define CMPL XO31( 32) -#define LHBRX XO31(790) -#define LWBRX XO31(534) -#define LDBRX XO31(532) -#define STHBRX XO31(918) -#define STWBRX XO31(662) -#define STDBRX XO31(660) -#define MFSPR XO31(339) -#define MTSPR XO31(467) -#define SRAWI XO31(824) -#define NEG XO31(104) -#define MFCR XO31( 19) -#define MFOCRF (MFCR | (1u << 20)) -#define NOR XO31(124) -#define CNTLZW XO31( 26) -#define CNTLZD XO31( 58) -#define CNTTZW XO31(538) -#define CNTTZD XO31(570) -#define CNTPOPW XO31(378) -#define CNTPOPD XO31(506) -#define ANDC XO31( 60) -#define ORC XO31(412) -#define EQV XO31(284) -#define NAND XO31(476) -#define ISEL XO31( 15) - -#define MULLD XO31(233) -#define MULHD XO31( 73) -#define MULHDU XO31( 9) -#define DIVD XO31(489) -#define DIVDU XO31(457) - -#define LBZX XO31( 87) -#define LHZX XO31(279) -#define LHAX XO31(343) -#define LWZX XO31( 23) -#define STBX XO31(215) -#define STHX XO31(407) -#define STWX XO31(151) - -#define EIEIO XO31(854) -#define HWSYNC XO31(598) -#define LWSYNC (HWSYNC | (1u << 21)) - -#define SPR(a, b) ((((a)<<5)|(b))<<11) -#define LR SPR(8, 0) -#define CTR SPR(9, 0) - -#define SLW XO31( 24) -#define SRW XO31(536) -#define SRAW XO31(792) - -#define SLD XO31( 27) -#define SRD XO31(539) -#define SRAD XO31(794) -#define SRADI XO31(413<<1) - -#define TW XO31( 4) -#define TRAP (TW | TO(31)) - -#define NOP ORI /* ori 0,0,0 */ - -#define LVX XO31(103) -#define LVEBX XO31(7) -#define LVEHX XO31(39) -#define LVEWX XO31(71) -#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ -#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ -#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ -#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ -#define LXSD (OPCD(57) | 2) /* v3.00 */ -#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ - -#define STVX XO31(231) -#define STVEWX XO31(199) -#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ -#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ -#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ -#define STXSD (OPCD(61) | 2) /* v3.00 */ - -#define VADDSBS VX4(768) -#define VADDUBS VX4(512) -#define VADDUBM VX4(0) -#define VADDSHS VX4(832) -#define VADDUHS VX4(576) -#define VADDUHM VX4(64) -#define VADDSWS VX4(896) -#define VADDUWS VX4(640) -#define VADDUWM VX4(128) -#define VADDUDM VX4(192) /* v2.07 */ - -#define VSUBSBS VX4(1792) -#define VSUBUBS VX4(1536) -#define VSUBUBM VX4(1024) -#define VSUBSHS VX4(1856) -#define VSUBUHS VX4(1600) -#define VSUBUHM VX4(1088) -#define VSUBSWS VX4(1920) -#define VSUBUWS VX4(1664) -#define VSUBUWM VX4(1152) -#define VSUBUDM VX4(1216) /* v2.07 */ - -#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ -#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ - -#define VMAXSB VX4(258) -#define VMAXSH VX4(322) -#define VMAXSW VX4(386) -#define VMAXSD VX4(450) /* v2.07 */ -#define VMAXUB VX4(2) -#define VMAXUH VX4(66) -#define VMAXUW VX4(130) -#define VMAXUD VX4(194) /* v2.07 */ -#define VMINSB VX4(770) -#define VMINSH VX4(834) -#define VMINSW VX4(898) -#define VMINSD VX4(962) /* v2.07 */ -#define VMINUB VX4(514) -#define VMINUH VX4(578) -#define VMINUW VX4(642) -#define VMINUD VX4(706) /* v2.07 */ - -#define VCMPEQUB VX4(6) -#define VCMPEQUH VX4(70) -#define VCMPEQUW VX4(134) -#define VCMPEQUD VX4(199) /* v2.07 */ -#define VCMPGTSB VX4(774) -#define VCMPGTSH VX4(838) -#define VCMPGTSW VX4(902) -#define VCMPGTSD VX4(967) /* v2.07 */ -#define VCMPGTUB VX4(518) -#define VCMPGTUH VX4(582) -#define VCMPGTUW VX4(646) -#define VCMPGTUD VX4(711) /* v2.07 */ -#define VCMPNEB VX4(7) /* v3.00 */ -#define VCMPNEH VX4(71) /* v3.00 */ -#define VCMPNEW VX4(135) /* v3.00 */ - -#define VSLB VX4(260) -#define VSLH VX4(324) -#define VSLW VX4(388) -#define VSLD VX4(1476) /* v2.07 */ -#define VSRB VX4(516) -#define VSRH VX4(580) -#define VSRW VX4(644) -#define VSRD VX4(1732) /* v2.07 */ -#define VSRAB VX4(772) -#define VSRAH VX4(836) -#define VSRAW VX4(900) -#define VSRAD VX4(964) /* v2.07 */ -#define VRLB VX4(4) -#define VRLH VX4(68) -#define VRLW VX4(132) -#define VRLD VX4(196) /* v2.07 */ - -#define VMULEUB VX4(520) -#define VMULEUH VX4(584) -#define VMULEUW VX4(648) /* v2.07 */ -#define VMULOUB VX4(8) -#define VMULOUH VX4(72) -#define VMULOUW VX4(136) /* v2.07 */ -#define VMULUWM VX4(137) /* v2.07 */ -#define VMSUMUHM VX4(38) - -#define VMRGHB VX4(12) -#define VMRGHH VX4(76) -#define VMRGHW VX4(140) -#define VMRGLB VX4(268) -#define VMRGLH VX4(332) -#define VMRGLW VX4(396) - -#define VPKUHUM VX4(14) -#define VPKUWUM VX4(78) - -#define VAND VX4(1028) -#define VANDC VX4(1092) -#define VNOR VX4(1284) -#define VOR VX4(1156) -#define VXOR VX4(1220) -#define VEQV VX4(1668) /* v2.07 */ -#define VNAND VX4(1412) /* v2.07 */ -#define VORC VX4(1348) /* v2.07 */ - -#define VSPLTB VX4(524) -#define VSPLTH VX4(588) -#define VSPLTW VX4(652) -#define VSPLTISB VX4(780) -#define VSPLTISH VX4(844) -#define VSPLTISW VX4(908) - -#define VSLDOI VX4(44) - -#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ -#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ -#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ - -#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ -#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ -#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ -#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ -#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ -#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ - -#define RT(r) ((r)<<21) -#define RS(r) ((r)<<21) -#define RA(r) ((r)<<16) -#define RB(r) ((r)<<11) -#define TO(t) ((t)<<21) -#define SH(s) ((s)<<11) -#define MB(b) ((b)<<6) -#define ME(e) ((e)<<1) -#define BO(o) ((o)<<21) -#define MB64(b) ((b)<<5) -#define FXM(b) (1 << (19 - (b))) - -#define VRT(r) (((r) & 31) << 21) -#define VRA(r) (((r) & 31) << 16) -#define VRB(r) (((r) & 31) << 11) -#define VRC(r) (((r) & 31) << 6) - -#define LK 1 - -#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) -#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) -#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) -#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) - -#define BF(n) ((n)<<23) -#define BI(n, c) (((c)+((n)*4))<<16) -#define BT(n, c) (((c)+((n)*4))<<21) -#define BA(n, c) (((c)+((n)*4))<<16) -#define BB(n, c) (((c)+((n)*4))<<11) -#define BC_(n, c) (((c)+((n)*4))<<6) - -#define BO_COND_TRUE BO(12) -#define BO_COND_FALSE BO( 4) -#define BO_ALWAYS BO(20) - -enum { - CR_LT, - CR_GT, - CR_EQ, - CR_SO -}; - -static const uint32_t tcg_to_bc[] = { - [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, - [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, - [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, - [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, -}; - -/* The low bit here is set if the RA and RB fields must be inverted. */ -static const uint32_t tcg_to_isel[] = { - [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), - [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, - [TCG_COND_LT] = ISEL | BC_(7, CR_LT), - [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GT] = ISEL | BC_(7, CR_GT), - [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), - [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), -}; - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_insn_unit *target; - int16_t lo; - int32_t hi; - - value += addend; - target = (tcg_insn_unit *)value; - - switch (type) { - case R_PPC_REL14: - return reloc_pc14(code_ptr, target); - case R_PPC_REL24: - return reloc_pc24(code_ptr, target); - case R_PPC_ADDR16: - /* - * We are (slightly) abusing this relocation type. In particular, - * assert that the low 2 bits are zero, and do not modify them. - * That way we can use this with LD et al that have opcode bits - * in the low 2 bits of the insn. - */ - if ((value & 3) || value != (int16_t)value) { - return false; - } - *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); - break; - case R_PPC_ADDR32: - /* - * We are abusing this relocation type. Again, this points to - * a pair of insns, lis + load. This is an absolute address - * relocation for PPC32 so the lis cannot be removed. - */ - lo = value; - hi = value - lo; - if (hi + lo != value) { - return false; - } - code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); - code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); - break; - default: - g_assert_not_reached(); - } - return true; -} - -static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, - TCGReg base, tcg_target_long offset); - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ - if (ret == arg) { - return true; - } - switch (type) { - case TCG_TYPE_I64: - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); - /* fallthru */ - case TCG_TYPE_I32: - if (ret < TCG_REG_V0) { - if (arg < TCG_REG_V0) { - tcg_out32(s, OR | SAB(arg, ret, arg)); - break; - } else if (have_isa_2_07) { - tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) - | VRT(arg) | RA(ret)); - break; - } else { - /* Altivec does not support vector->integer moves. */ - return false; - } - } else if (arg < TCG_REG_V0) { - if (have_isa_2_07) { - tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) - | VRT(ret) | RA(arg)); - break; - } else { - /* Altivec does not support integer->vector moves. */ - return false; - } - } - /* fallthru */ - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); - tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); - break; - default: - g_assert_not_reached(); - } - return true; -} - -static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, - int sh, int mb) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); - sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); - mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); - tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); -} - -static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, - int sh, int mb, int me) -{ - tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) -{ - tcg_out_rld(s, RLDICL, dst, src, 0, 32); -} - -static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) -{ - tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); -} - -static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) -{ - tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); -} - -static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) -{ - tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); -} - -static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) -{ - tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); -} - -/* Emit a move into ret of arg, if it can be done in one insn. */ -static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) -{ - if (arg == (int16_t)arg) { - tcg_out32(s, ADDI | TAI(ret, 0, arg)); - return true; - } - if (arg == (int32_t)arg && (arg & 0xffff) == 0) { - tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); - return true; - } - return false; -} - -static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) -{ - intptr_t tb_diff; - tcg_target_long tmp; - int shift; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); - - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - arg = (int32_t)arg; - } - - /* Load 16-bit immediates with one insn. */ - if (tcg_out_movi_one(s, ret, arg)) { - return; - } - - /* Load addresses within the TB with one insn. */ - tb_diff = arg - (intptr_t)s->code_gen_ptr; - if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { - tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); - return; - } - - /* Load 32-bit immediates with two insns. Note that we've already - eliminated bare ADDIS, so we know both insns are required. */ - if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { - tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); - tcg_out32(s, ORI | SAI(ret, ret, arg)); - return; - } - if (arg == (uint32_t)arg && !(arg & 0x8000)) { - tcg_out32(s, ADDI | TAI(ret, 0, arg)); - tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - return; - } - - /* Load masked 16-bit value. */ - if (arg > 0 && (arg & 0x8000)) { - tmp = arg | 0x7fff; - if ((tmp & (tmp + 1)) == 0) { - int mb = clz64(tmp + 1) + 1; - tcg_out32(s, ADDI | TAI(ret, 0, arg)); - tcg_out_rld(s, RLDICL, ret, ret, 0, mb); - return; - } - } - - /* Load common masks with 2 insns. */ - shift = ctz64(arg); - tmp = arg >> shift; - if (tmp == (int16_t)tmp) { - tcg_out32(s, ADDI | TAI(ret, 0, tmp)); - tcg_out_shli64(s, ret, ret, shift); - return; - } - shift = clz64(arg); - if (tcg_out_movi_one(s, ret, arg << shift)) { - tcg_out_shri64(s, ret, ret, shift); - return; - } - - /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ - if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { - tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); - return; - } - - /* Use the constant pool, if possible. */ - if (!in_prologue && USE_REG_TB) { - new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, - -(intptr_t)s->code_gen_ptr); - tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); - return; - } - - tmp = arg >> 31 >> 1; - tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); - if (tmp) { - tcg_out_shli64(s, ret, ret, 32); - } - if (arg & 0xffff0000) { - tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - } - if (arg & 0xffff) { - tcg_out32(s, ORI | SAI(ret, ret, arg)); - } -} - -static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long val) -{ - uint32_t load_insn; - int rel, low; - intptr_t add; - - low = (int8_t)val; - if (low >= -16 && low < 16) { - if (val == (tcg_target_long)dup_const(MO_8, low)) { - tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); - return; - } - if (val == (tcg_target_long)dup_const(MO_16, low)) { - tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); - return; - } - if (val == (tcg_target_long)dup_const(MO_32, low)) { - tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); - return; - } - } - if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) { - tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); - return; - } - - /* - * Otherwise we must load the value from the constant pool. - */ - if (USE_REG_TB) { - rel = R_PPC_ADDR16; - add = -(intptr_t)s->code_gen_ptr; - } else { - rel = R_PPC_ADDR32; - add = 0; - } - - if (have_vsx) { - load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; - load_insn |= VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS == 64) { - new_pool_label(s, val, rel, s->code_ptr, add); - } else { - new_pool_l2(s, rel, s->code_ptr, add, val, val); - } - } else { - load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS == 64) { - new_pool_l2(s, rel, s->code_ptr, add, val, val); - } else { - new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val); - } - } - - if (USE_REG_TB) { - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); - load_insn |= RA(TCG_REG_TB); - } else { - tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); - } - tcg_out32(s, load_insn); -} - -static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) -{ - switch (type) { - case TCG_TYPE_I32: - case TCG_TYPE_I64: - tcg_debug_assert(ret < TCG_REG_V0); - tcg_out_movi_int(s, type, ret, arg, false); - break; - - case TCG_TYPE_V64: - case TCG_TYPE_V128: - tcg_debug_assert(ret >= TCG_REG_V0); - tcg_out_dupi_vec(s, type, ret, arg); - break; - - default: - g_assert_not_reached(); - } -} - -static bool mask_operand(uint32_t c, int *mb, int *me) -{ - uint32_t lsb, test; - - /* Accept a bit pattern like: - 0....01....1 - 1....10....0 - 0..01..10..0 - Keep track of the transitions. */ - if (c == 0 || c == -1) { - return false; - } - test = c; - lsb = test & -test; - test += lsb; - if (test & (test - 1)) { - return false; - } - - *me = clz32(lsb); - *mb = test ? clz32(test & -test) + 1 : 0; - return true; -} - -static bool mask64_operand(uint64_t c, int *mb, int *me) -{ - uint64_t lsb; - - if (c == 0) { - return false; - } - - lsb = c & -c; - /* Accept 1..10..0. */ - if (c == -lsb) { - *mb = 0; - *me = clz64(lsb); - return true; - } - /* Accept 0..01..1. */ - if (lsb == 1 && (c & (c + 1)) == 0) { - *mb = clz64(c + 1) + 1; - *me = 63; - return true; - } - return false; -} - -static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) -{ - int mb, me; - - if (mask_operand(c, &mb, &me)) { - tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); - } else if ((c & 0xffff) == c) { - tcg_out32(s, ANDI | SAI(src, dst, c)); - return; - } else if ((c & 0xffff0000) == c) { - tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); - return; - } else { - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); - tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); - } -} - -static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) -{ - int mb, me; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); - if (mask64_operand(c, &mb, &me)) { - if (mb == 0) { - tcg_out_rld(s, RLDICR, dst, src, 0, me); - } else { - tcg_out_rld(s, RLDICL, dst, src, 0, mb); - } - } else if ((c & 0xffff) == c) { - tcg_out32(s, ANDI | SAI(src, dst, c)); - return; - } else if ((c & 0xffff0000) == c) { - tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); - return; - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); - tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); - } -} - -static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, - int op_lo, int op_hi) -{ - if (c >> 16) { - tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); - src = dst; - } - if (c & 0xffff) { - tcg_out32(s, op_lo | SAI(src, dst, c)); - src = dst; - } -} - -static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) -{ - tcg_out_zori32(s, dst, src, c, ORI, ORIS); -} - -static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) -{ - tcg_out_zori32(s, dst, src, c, XORI, XORIS); -} - -static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) -{ - ptrdiff_t disp = tcg_pcrel_diff(s, target); - if (in_range_b(disp)) { - tcg_out32(s, B | (disp & 0x3fffffc) | mask); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); - tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | mask); - } -} - -static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, - TCGReg base, tcg_target_long offset) -{ - tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; - bool is_int_store = false; - TCGReg rs = TCG_REG_TMP1; - - switch (opi) { - case LD: case LWA: - align = 3; - /* FALLTHRU */ - default: - if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { - rs = rt; - break; - } - break; - case LXSD: - case STXSD: - align = 3; - break; - case LXV: - case STXV: - align = 15; - break; - case STD: - align = 3; - /* FALLTHRU */ - case STB: case STH: case STW: - is_int_store = true; - break; - } - - /* For unaligned, or very large offsets, use the indexed form. */ - if (offset & align || offset != (int32_t)offset || opi == 0) { - if (rs == base) { - rs = TCG_REG_R0; - } - tcg_debug_assert(!is_int_store || rs != rt); - tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); - tcg_out32(s, opx | TAB(rt & 31, base, rs)); - return; - } - - l0 = (int16_t)offset; - offset = (offset - l0) >> 16; - l1 = (int16_t)offset; - - if (l1 < 0 && orig >= 0) { - extra = 0x4000; - l1 = (int16_t)(offset - 0x4000); - } - if (l1) { - tcg_out32(s, ADDIS | TAI(rs, base, l1)); - base = rs; - } - if (extra) { - tcg_out32(s, ADDIS | TAI(rs, base, extra)); - base = rs; - } - if (opi != ADDI || base != rt || l0 != 0) { - tcg_out32(s, opi | TAI(rt & 31, base, l0)); - } -} - -static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, - TCGReg va, TCGReg vb, int shb) -{ - tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg base, intptr_t offset) -{ - int shift; - - switch (type) { - case TCG_TYPE_I32: - if (ret < TCG_REG_V0) { - tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); - break; - } - if (have_isa_2_07 && have_vsx) { - tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); - break; - } - tcg_debug_assert((offset & 3) == 0); - tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); - shift = (offset - 4) & 0xc; - if (shift) { - tcg_out_vsldoi(s, ret, ret, ret, shift); - } - break; - case TCG_TYPE_I64: - if (ret < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); - tcg_out_mem_long(s, LD, LDX, ret, base, offset); - break; - } - /* fallthru */ - case TCG_TYPE_V64: - tcg_debug_assert(ret >= TCG_REG_V0); - if (have_vsx) { - tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, - ret, base, offset); - break; - } - tcg_debug_assert((offset & 7) == 0); - tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); - if (offset & 8) { - tcg_out_vsldoi(s, ret, ret, ret, 8); - } - break; - case TCG_TYPE_V128: - tcg_debug_assert(ret >= TCG_REG_V0); - tcg_debug_assert((offset & 15) == 0); - tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, - LVX, ret, base, offset); - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg base, intptr_t offset) -{ - int shift; - - switch (type) { - case TCG_TYPE_I32: - if (arg < TCG_REG_V0) { - tcg_out_mem_long(s, STW, STWX, arg, base, offset); - break; - } - if (have_isa_2_07 && have_vsx) { - tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); - break; - } - assert((offset & 3) == 0); - tcg_debug_assert((offset & 3) == 0); - shift = (offset - 4) & 0xc; - if (shift) { - tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); - arg = TCG_VEC_TMP1; - } - tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); - break; - case TCG_TYPE_I64: - if (arg < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS == 64); - tcg_out_mem_long(s, STD, STDX, arg, base, offset); - break; - } - /* fallthru */ - case TCG_TYPE_V64: - tcg_debug_assert(arg >= TCG_REG_V0); - if (have_vsx) { - tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, - STXSDX, arg, base, offset); - break; - } - tcg_debug_assert((offset & 7) == 0); - if (offset & 8) { - tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); - arg = TCG_VEC_TMP1; - } - tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); - tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); - break; - case TCG_TYPE_V128: - tcg_debug_assert(arg >= TCG_REG_V0); - tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, - STVX, arg, base, offset); - break; - default: - g_assert_not_reached(); - } -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - return false; -} - -static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, - int const_arg2, int cr, TCGType type) -{ - int imm; - uint32_t op; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); - - /* Simplify the comparisons below wrt CMPI. */ - if (type == TCG_TYPE_I32) { - arg2 = (int32_t)arg2; - } - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_NE: - if (const_arg2) { - if ((int16_t) arg2 == arg2) { - op = CMPI; - imm = 1; - break; - } else if ((uint16_t) arg2 == arg2) { - op = CMPLI; - imm = 1; - break; - } - } - op = CMPL; - imm = 0; - break; - - case TCG_COND_LT: - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GT: - if (const_arg2) { - if ((int16_t) arg2 == arg2) { - op = CMPI; - imm = 1; - break; - } - } - op = CMP; - imm = 0; - break; - - case TCG_COND_LTU: - case TCG_COND_GEU: - case TCG_COND_LEU: - case TCG_COND_GTU: - if (const_arg2) { - if ((uint16_t) arg2 == arg2) { - op = CMPLI; - imm = 1; - break; - } - } - op = CMPL; - imm = 0; - break; - - default: - tcg_abort(); - } - op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); - - if (imm) { - tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); - } else { - if (const_arg2) { - tcg_out_movi(s, type, TCG_REG_R0, arg2); - arg2 = TCG_REG_R0; - } - tcg_out32(s, op | RA(arg1) | RB(arg2)); - } -} - -static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, - TCGReg dst, TCGReg src) -{ - if (type == TCG_TYPE_I32) { - tcg_out32(s, CNTLZW | RS(src) | RA(dst)); - tcg_out_shri32(s, dst, dst, 5); - } else { - tcg_out32(s, CNTLZD | RS(src) | RA(dst)); - tcg_out_shri64(s, dst, dst, 6); - } -} - -static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) -{ - /* X != 0 implies X + -1 generates a carry. Extra addition - trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ - if (dst != src) { - tcg_out32(s, ADDIC | TAI(dst, src, -1)); - tcg_out32(s, SUBFE | TAB(dst, dst, src)); - } else { - tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); - tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); - } -} - -static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, - bool const_arg2) -{ - if (const_arg2) { - if ((uint32_t)arg2 == arg2) { - tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); - tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); - } - } else { - tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); - } - return TCG_REG_R0; -} - -static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, - TCGArg arg0, TCGArg arg1, TCGArg arg2, - int const_arg2) -{ - int crop, sh; - - tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); - - /* Ignore high bits of a potential constant arg2. */ - if (type == TCG_TYPE_I32) { - arg2 = (uint32_t)arg2; - } - - /* Handle common and trivial cases before handling anything else. */ - if (arg2 == 0) { - switch (cond) { - case TCG_COND_EQ: - tcg_out_setcond_eq0(s, type, arg0, arg1); - return; - case TCG_COND_NE: - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_REG_R0, arg1); - arg1 = TCG_REG_R0; - } - tcg_out_setcond_ne0(s, arg0, arg1); - return; - case TCG_COND_GE: - tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); - arg1 = arg0; - /* FALLTHRU */ - case TCG_COND_LT: - /* Extract the sign bit. */ - if (type == TCG_TYPE_I32) { - tcg_out_shri32(s, arg0, arg1, 31); - } else { - tcg_out_shri64(s, arg0, arg1, 63); - } - return; - default: - break; - } - } - - /* If we have ISEL, we can implement everything with 3 or 4 insns. - All other cases below are also at least 3 insns, so speed up the - code generator by not considering them and always using ISEL. */ - if (have_isel) { - int isel, tab; - - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); - - isel = tcg_to_isel[cond]; - - tcg_out_movi(s, type, arg0, 1); - if (isel & 1) { - /* arg0 = (bc ? 0 : 1) */ - tab = TAB(arg0, 0, arg0); - isel &= ~1; - } else { - /* arg0 = (bc ? 1 : 0) */ - tcg_out_movi(s, type, TCG_REG_R0, 0); - tab = TAB(arg0, arg0, TCG_REG_R0); - } - tcg_out32(s, isel | tab); - return; - } - - switch (cond) { - case TCG_COND_EQ: - arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); - tcg_out_setcond_eq0(s, type, arg0, arg1); - return; - - case TCG_COND_NE: - arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); - /* Discard the high bits only once, rather than both inputs. */ - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_REG_R0, arg1); - arg1 = TCG_REG_R0; - } - tcg_out_setcond_ne0(s, arg0, arg1); - return; - - case TCG_COND_GT: - case TCG_COND_GTU: - sh = 30; - crop = 0; - goto crtest; - - case TCG_COND_LT: - case TCG_COND_LTU: - sh = 29; - crop = 0; - goto crtest; - - case TCG_COND_GE: - case TCG_COND_GEU: - sh = 31; - crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); - goto crtest; - - case TCG_COND_LE: - case TCG_COND_LEU: - sh = 31; - crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); - crtest: - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); - if (crop) { - tcg_out32(s, crop); - } - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); - tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); - break; - - default: - tcg_abort(); - } -} - -static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) -{ - if (l->has_value) { - bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); - } - tcg_out32(s, bc); -} - -static void tcg_out_brcond(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *l, TCGType type) -{ - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); - tcg_out_bc(s, tcg_to_bc[cond], l); -} - -static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, - TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, - TCGArg v2, bool const_c2) -{ - /* If for some reason both inputs are zero, don't produce bad code. */ - if (v1 == 0 && v2 == 0) { - tcg_out_movi(s, type, dest, 0); - return; - } - - tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); - - if (have_isel) { - int isel = tcg_to_isel[cond]; - - /* Swap the V operands if the operation indicates inversion. */ - if (isel & 1) { - int t = v1; - v1 = v2; - v2 = t; - isel &= ~1; - } - /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ - if (v2 == 0) { - tcg_out_movi(s, type, TCG_REG_R0, 0); - } - tcg_out32(s, isel | TAB(dest, v1, v2)); - } else { - if (dest == v2) { - cond = tcg_invert_cond(cond); - v2 = v1; - } else if (dest != v1) { - if (v1 == 0) { - tcg_out_movi(s, type, dest, 0); - } else { - tcg_out_mov(s, type, dest, v1); - } - } - /* Branch forward over one insn */ - tcg_out32(s, tcg_to_bc[cond] | 8); - if (v2 == 0) { - tcg_out_movi(s, type, dest, 0); - } else { - tcg_out_mov(s, type, dest, v2); - } - } -} - -static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, - TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) -{ - if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { - tcg_out32(s, opc | RA(a0) | RS(a1)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); - /* Note that the only other valid constant for a2 is 0. */ - if (have_isel) { - tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); - tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); - } else if (!const_a2 && a0 == a2) { - tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); - tcg_out32(s, opc | RA(a0) | RS(a1)); - } else { - tcg_out32(s, opc | RA(a0) | RS(a1)); - tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); - if (const_a2) { - tcg_out_movi(s, type, a0, 0); - } else { - tcg_out_mov(s, type, a0, a2); - } - } - } -} - -static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, - const int *const_args) -{ - static const struct { uint8_t bit1, bit2; } bits[] = { - [TCG_COND_LT ] = { CR_LT, CR_LT }, - [TCG_COND_LE ] = { CR_LT, CR_GT }, - [TCG_COND_GT ] = { CR_GT, CR_GT }, - [TCG_COND_GE ] = { CR_GT, CR_LT }, - [TCG_COND_LTU] = { CR_LT, CR_LT }, - [TCG_COND_LEU] = { CR_LT, CR_GT }, - [TCG_COND_GTU] = { CR_GT, CR_GT }, - [TCG_COND_GEU] = { CR_GT, CR_LT }, - }; - - TCGCond cond = args[4], cond2; - TCGArg al, ah, bl, bh; - int blconst, bhconst; - int op, bit1, bit2; - - al = args[0]; - ah = args[1]; - bl = args[2]; - bh = args[3]; - blconst = const_args[2]; - bhconst = const_args[3]; - - switch (cond) { - case TCG_COND_EQ: - op = CRAND; - goto do_equality; - case TCG_COND_NE: - op = CRNAND; - do_equality: - tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - break; - - case TCG_COND_LT: - case TCG_COND_LE: - case TCG_COND_GT: - case TCG_COND_GE: - case TCG_COND_LTU: - case TCG_COND_LEU: - case TCG_COND_GTU: - case TCG_COND_GEU: - bit1 = bits[cond].bit1; - bit2 = bits[cond].bit2; - op = (bit1 != bit2 ? CRANDC : CRAND); - cond2 = tcg_unsigned_cond(cond); - - tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); - tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); - break; - - default: - tcg_abort(); - } -} - -static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, - const int *const_args) -{ - tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); - tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); -} - -static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, - const int *const_args) -{ - tcg_out_cmp2(s, args, const_args); - tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); -} - -static void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - uint32_t insn = HWSYNC; - a0 &= TCG_MO_ALL; - if (a0 == TCG_MO_LD_LD) { - insn = LWSYNC; - } else if (a0 == TCG_MO_ST_ST) { - insn = EIEIO; - } - tcg_out32(s, insn); -} - -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) -{ - if (TCG_TARGET_REG_BITS == 64) { - tcg_insn_unit i1, i2; - intptr_t tb_diff = addr - tc_ptr; - intptr_t br_diff = addr - (jmp_addr + 4); - uint64_t pair; - - /* This does not exercise the range of the branch, but we do - still need to be able to load the new value of TCG_REG_TB. - But this does still happen quite often. */ - if (tb_diff == (int16_t)tb_diff) { - i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); - i2 = B | (br_diff & 0x3fffffc); - } else { - intptr_t lo = (int16_t)tb_diff; - intptr_t hi = (int32_t)(tb_diff - lo); - assert(tb_diff == hi + lo); - i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); - i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); - } -#ifdef HOST_WORDS_BIGENDIAN - pair = (uint64_t)i1 << 32 | i2; -#else - pair = (uint64_t)i2 << 32 | i1; -#endif - - /* As per the enclosing if, this is ppc64. Avoid the _Static_assert - within atomic_set that would fail to build a ppc32 host. */ - atomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); - } else { - intptr_t diff = addr - jmp_addr; - tcg_debug_assert(in_range_b(diff)); - atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_icache_range(jmp_addr, jmp_addr + 4); - } -} - -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) -{ -#ifdef _CALL_AIX - /* Look through the descriptor. If the branch is in range, and we - don't have to spend too much effort on building the toc. */ - void *tgt = ((void **)target)[0]; - uintptr_t toc = ((uintptr_t *)target)[1]; - intptr_t diff = tcg_pcrel_diff(s, tgt); - - if (in_range_b(diff) && toc == (uint32_t)toc) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); - tcg_out_b(s, LK, tgt); - } else { - /* Fold the low bits of the constant into the addresses below. */ - intptr_t arg = (intptr_t)target; - int ofs = (int16_t)arg; - - if (ofs + 8 < 0x8000) { - arg -= ofs; - } else { - ofs = 0; - } - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); - tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); - } -#elif defined(_CALL_ELF) && _CALL_ELF == 2 - intptr_t diff; - - /* In the ELFv2 ABI, we have to set up r12 to contain the destination - address, which the callee uses to compute its TOC address. */ - /* FIXME: when the branch is in range, we could avoid r12 load if we - knew that the destination uses the same TOC, and what its local - entry point offset is. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); - - diff = tcg_pcrel_diff(s, target); - if (in_range_b(diff)) { - tcg_out_b(s, LK, target); - } else { - tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS | LK); - } -#else - tcg_out_b(s, LK, target); -#endif -} - -static const uint32_t qemu_ldx_opc[16] = { - [MO_UB] = LBZX, - [MO_UW] = LHZX, - [MO_UL] = LWZX, - [MO_Q] = LDX, - [MO_SW] = LHAX, - [MO_SL] = LWAX, - [MO_BSWAP | MO_UB] = LBZX, - [MO_BSWAP | MO_UW] = LHBRX, - [MO_BSWAP | MO_UL] = LWBRX, - [MO_BSWAP | MO_Q] = LDBRX, -}; - -static const uint32_t qemu_stx_opc[16] = { - [MO_UB] = STBX, - [MO_UW] = STHX, - [MO_UL] = STWX, - [MO_Q] = STDX, - [MO_BSWAP | MO_UB] = STBX, - [MO_BSWAP | MO_UW] = STHBRX, - [MO_BSWAP | MO_UL] = STWBRX, - [MO_BSWAP | MO_Q] = STDBRX, -}; - -static const uint32_t qemu_exts_opc[4] = { - EXTSB, EXTSH, EXTSW, 0 -}; - -#if defined (CONFIG_SOFTMMU) -#include "../tcg-ldst.inc.c" - -/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, -}; - -/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_t ra) - */ -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, - TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) -{ - int cmp_off - = (is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); - int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); - int table_off = fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); - - /* Load the TLB comparator. */ - if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { - uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); - } - } - - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); - - /* Clear the non-page, non-alignment bits from the address */ - if (TCG_TARGET_REG_BITS == 32) { - /* We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else { - TCGReg t = addrlo; - - /* If the access is unaligned, we need to make sure we fail if we - * cross a page boundary. The trick is to add the access size-1 - * to the address before masking the low bits. That will make the - * address overflow to the next page if we cross a page boundary, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask = (1 << a_bits) - 1; - unsigned s_mask = (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t = TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS == 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo = TCG_REG_R4; - } else if (a_bits == 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); - } - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_TL); - } - - return addrlo; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = datalo_reg; - label->datahi_reg = datahi_reg; - label->addrlo_reg = addrlo_reg; - label->addrhi_reg = addrhi_reg; - label->raddr = raddr; - label->label_ptr[0] = lptr; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - TCGReg hi, lo, arg = TCG_REG_R3; - - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo = lb->addrlo_reg; - hi = lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo = lb->datalo_reg; - hi = lb->datahi_reg; - if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else if (opc & MO_SIGN) { - uint32_t insn = qemu_exts_opc[opc & MO_SIZE]; - tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); - } else { - tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); - } - - tcg_out_b(s, 0, lb->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - MemOp s_bits = opc & MO_SIZE; - TCGReg hi, lo, arg = TCG_REG_R3; - - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo = lb->addrlo_reg; - hi = lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo = lb->datalo_reg; - hi = lb->datahi_reg; - if (TCG_TARGET_REG_BITS == 32) { - switch (s_bits) { - case MO_64: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - /* FALLTHRU */ - case MO_32: - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - break; - default: - tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); - break; - } - } else { - if (s_bits == MO_64) { - tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); - } else { - tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); - } - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - tcg_out_b(s, 0, lb->raddr); - return true; -} -#endif /* SOFTMMU */ - -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif - - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - s_bits = opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr = s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase = TCG_REG_R3; -#else /* !CONFIG_SOFTMMU */ - rbase = guest_base ? TCG_GUEST_BASE_REG : 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo = TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase != 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); - tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); - } else if (addrlo == datahi) { - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); - } else { - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); - } - } else { - uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; - if (!have_isa_2_06 && insn == LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); - tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); - } else if (insn) { - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); - } else { - insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); - insn = qemu_exts_opc[s_bits]; - tcg_out32(s, insn | RA(datalo) | RS(datalo)); - } - } - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#endif -} - -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - TCGMemOpIdx oi; - MemOp opc, s_bits; -#ifdef CONFIG_SOFTMMU - int mem_index; - tcg_insn_unit *label_ptr; -#endif - - datalo = *args++; - datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addrlo = *args++; - addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - s_bits = opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index = get_mmuidx(oi); - addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr = s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase = TCG_REG_R3; -#else /* !CONFIG_SOFTMMU */ - rbase = guest_base ? TCG_GUEST_BASE_REG : 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo = TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase != 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); - tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); - } else { - tcg_out32(s, STW | TAI(datahi, addrlo, 0)); - tcg_out32(s, STW | TAI(datalo, addrlo, 4)); - } - } else { - uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; - if (!have_isa_2_06 && insn == STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); - tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); - } else { - tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); - } - } - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); -#endif -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i = 0; i < count; ++i) { - p[i] = NOP; - } -} - -/* Parameters for function call generation, used in tcg.c. */ -#define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_EXTEND_ARGS 1 - -#ifdef _CALL_AIX -# define LINK_AREA_SIZE (6 * SZR) -# define LR_OFFSET (1 * SZR) -# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) -#elif defined(TCG_TARGET_CALL_DARWIN) -# define LINK_AREA_SIZE (6 * SZR) -# define LR_OFFSET (2 * SZR) -#elif TCG_TARGET_REG_BITS == 64 -# if defined(_CALL_ELF) && _CALL_ELF == 2 -# define LINK_AREA_SIZE (4 * SZR) -# define LR_OFFSET (1 * SZR) -# endif -#else /* TCG_TARGET_REG_BITS == 32 */ -# if defined(_CALL_SYSV) -# define LINK_AREA_SIZE (2 * SZR) -# define LR_OFFSET (1 * SZR) -# endif -#endif -#ifndef LR_OFFSET -# error "Unhandled abi" -#endif -#ifndef TCG_TARGET_CALL_STACK_OFFSET -# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE -#endif - -#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) -#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) - -#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_SIZE \ - + REG_SAVE_SIZE \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & -TCG_TARGET_STACK_ALIGN) - -#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) - -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int i; - -#ifdef _CALL_AIX - void **desc = (void **)s->code_ptr; - desc[0] = desc + 2; /* entry point */ - desc[1] = 0; /* environment pointer */ - s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ -#endif - - tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, - CPU_TEMP_BUF_SIZE); - - /* Prologue */ - tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); - tcg_out32(s, (SZR == 8 ? STDU : STWU) - | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); - - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { - tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_R1, REG_SAVE_BOT + i * SZR); - } - tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); - -#ifndef CONFIG_SOFTMMU - if (guest_base) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); - } -#endif - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); - } - tcg_out32(s, BCCTR | BO_ALWAYS); - - /* Epilogue */ - s->code_gen_epilogue = tb_ret_addr = s->code_ptr; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { - tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_R1, REG_SAVE_BOT + i * SZR); - } - tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); - tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); - tcg_out32(s, BCLR | BO_ALWAYS); -} - -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) -{ - TCGArg a0, a1, a2; - int c; - - switch (opc) { - case INDEX_op_exit_tb: - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out_b(s, 0, tb_ret_addr); - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump. */ - if (TCG_TARGET_REG_BITS == 64) { - /* Ensure the next insns are 8-byte aligned. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); - tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); - } else { - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); - tcg_out32(s, B); - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); - break; - } - } else { - /* Indirect jump. */ - tcg_debug_assert(s->tb_jmp_insn_offset == NULL); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, - (intptr_t)(s->tb_jmp_insn_offset + args[0])); - } - tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, args[0]); - if (USE_REG_TB) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - c = -tcg_current_code_size(s); - assert(c == (int16_t)c); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); - } - break; - case INDEX_op_goto_ptr: - tcg_out32(s, MTSPR | RS(args[0]) | CTR); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); - } - tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); - tcg_out32(s, BCCTR | BO_ALWAYS); - break; - case INDEX_op_br: - { - TCGLabel *l = arg_label(args[0]); - uint32_t insn = B; - - if (l->has_value) { - insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); - } - tcg_out32(s, insn); - } - break; - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); - break; - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); - tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0])); - break; - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); - break; - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); - break; - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); - break; - case INDEX_op_ld32s_i64: - tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); - break; - case INDEX_op_ld_i64: - tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); - break; - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); - break; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); - break; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); - break; - case INDEX_op_st_i64: - tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); - break; - - case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - do_addi_32: - tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); - } else { - tcg_out32(s, ADD | TAB(a0, a1, a2)); - } - break; - case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); - } else { - tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); - } - } else if (const_args[2]) { - a2 = -a2; - goto do_addi_32; - } else { - tcg_out32(s, SUBF | TAB(a0, a2, a1)); - } - break; - - case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi32(s, a0, a1, a2); - } else { - tcg_out32(s, AND | SAB(a1, a0, a2)); - } - break; - case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi64(s, a0, a1, a2); - } else { - tcg_out32(s, AND | SAB(a1, a0, a2)); - } - break; - case INDEX_op_or_i64: - case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_ori32(s, a0, a1, a2); - } else { - tcg_out32(s, OR | SAB(a1, a0, a2)); - } - break; - case INDEX_op_xor_i64: - case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_xori32(s, a0, a1, a2); - } else { - tcg_out32(s, XOR | SAB(a1, a0, a2)); - } - break; - case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi32(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } - break; - case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi64(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } - break; - case INDEX_op_orc_i32: - if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ - case INDEX_op_orc_i64: - tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); - break; - case INDEX_op_eqv_i32: - if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ - case INDEX_op_eqv_i64: - tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); - break; - case INDEX_op_nand_i32: - case INDEX_op_nand_i64: - tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); - break; - case INDEX_op_nor_i32: - case INDEX_op_nor_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); - break; - - case INDEX_op_clz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_ctz_i32: - tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_ctpop_i32: - tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); - break; - - case INDEX_op_clz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_ctz_i64: - tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_ctpop_i64: - tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); - break; - - case INDEX_op_mul_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out32(s, MULLI | TAI(a0, a1, a2)); - } else { - tcg_out32(s, MULLW | TAB(a0, a1, a2)); - } - break; - - case INDEX_op_div_i32: - tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); - break; - - case INDEX_op_divu_i32: - tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); - break; - - case INDEX_op_shl_i32: - if (const_args[2]) { - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli32(s, args[0], args[1], args[2] & 31); - } else { - tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_shr_i32: - if (const_args[2]) { - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri32(s, args[0], args[1], args[2] & 31); - } else { - tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_sar_i32: - if (const_args[2]) { - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31)); - } else { - tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); - } else { - tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) - | MB(0) | ME(31)); - } - break; - case INDEX_op_rotr_i32: - if (const_args[2]) { - tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); - } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); - tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) - | MB(0) | ME(31)); - } - break; - - case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], - arg_label(args[3]), TCG_TYPE_I32); - break; - case INDEX_op_brcond_i64: - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], - arg_label(args[3]), TCG_TYPE_I64); - break; - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args, const_args); - break; - - case INDEX_op_neg_i32: - case INDEX_op_neg_i64: - tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); - break; - - case INDEX_op_not_i32: - case INDEX_op_not_i64: - tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); - break; - - case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - do_addi_64: - tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); - } else { - tcg_out32(s, ADD | TAB(a0, a1, a2)); - } - break; - case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { - if (const_args[2]) { - tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); - } else { - tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); - } - } else if (const_args[2]) { - a2 = -a2; - goto do_addi_64; - } else { - tcg_out32(s, SUBF | TAB(a0, a2, a1)); - } - break; - - case INDEX_op_shl_i64: - if (const_args[2]) { - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shli64(s, args[0], args[1], args[2] & 63); - } else { - tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_shr_i64: - if (const_args[2]) { - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_shri64(s, args[0], args[1], args[2] & 63); - } else { - tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_sar_i64: - if (const_args[2]) { - int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); - tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh); - } else { - tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); - } - break; - case INDEX_op_rotl_i64: - if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); - } else { - tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); - } - break; - case INDEX_op_rotr_i64: - if (const_args[2]) { - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); - } else { - tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); - tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); - } - break; - - case INDEX_op_mul_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out32(s, MULLI | TAI(a0, a1, a2)); - } else { - tcg_out32(s, MULLD | TAB(a0, a1, a2)); - } - break; - case INDEX_op_div_i64: - tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); - break; - case INDEX_op_divu_i64: - tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); - break; - - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - c = EXTSB; - goto gen_ext; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - c = EXTSH; - goto gen_ext; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - c = EXTSW; - goto gen_ext; - gen_ext: - tcg_out32(s, c | RS(args[1]) | RA(args[0])); - break; - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); - break; - - case INDEX_op_setcond_i32: - tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], - const_args[2]); - break; - case INDEX_op_setcond_i64: - tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], - const_args[2]); - break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args, const_args); - break; - - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - a0 = args[0], a1 = args[1]; - /* a1 = abcd */ - if (a0 != a1) { - /* a0 = (a1 r<< 24) & 0xff # 000c */ - tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); - /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */ - tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23); - } else { - /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */ - tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23); - /* a0 = (a1 r<< 24) & 0xff # 000c */ - tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31); - /* a0 = a0 | r0 # 00dc */ - tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0)); - } - break; - - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - /* Stolen from gcc's builtin_bswap32 */ - a1 = args[1]; - a0 = args[0] == a1 ? TCG_REG_R0 : args[0]; - - /* a1 = args[1] # abcd */ - /* a0 = rotate_left (a1, 8) # bcda */ - tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); - /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */ - tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); - /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */ - tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); - - if (a0 == TCG_REG_R0) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); - } - break; - - case INDEX_op_bswap64_i64: - a0 = args[0], a1 = args[1], a2 = TCG_REG_R0; - if (a0 == a1) { - a0 = TCG_REG_R0; - a2 = a1; - } - - /* a1 = # abcd efgh */ - /* a0 = rl32(a1, 8) # 0000 fghe */ - tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31); - /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */ - tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7); - /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */ - tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23); - - /* a0 = rl64(a0, 32) # hgfe 0000 */ - /* a2 = rl64(a1, 32) # efgh abcd */ - tcg_out_rld(s, RLDICL, a0, a0, 32, 0); - tcg_out_rld(s, RLDICL, a2, a1, 32, 0); - - /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */ - tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31); - /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */ - tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7); - /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */ - tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23); - - if (a0 == 0) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); - } - break; - - case INDEX_op_deposit_i32: - if (const_args[2]) { - uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi32(s, args[0], args[0], ~mask); - } else { - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], - 32 - args[3] - args[4], 31 - args[3]); - } - break; - case INDEX_op_deposit_i64: - if (const_args[2]) { - uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; - tcg_out_andi64(s, args[0], args[0], ~mask); - } else { - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); - } - break; - - case INDEX_op_extract_i32: - tcg_out_rlw(s, RLWINM, args[0], args[1], - 32 - args[2], 32 - args[3], 31); - break; - case INDEX_op_extract_i64: - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); - break; - - case INDEX_op_movcond_i32: - tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], - args[3], args[4], const_args[2]); - break; - case INDEX_op_movcond_i64: - tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], - args[3], args[4], const_args[2]); - break; - -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_add2_i64: -#else - case INDEX_op_add2_i32: -#endif - /* Note that the CA bit is defined based on the word size of the - environment. So in 64-bit mode it's always carry-out of bit 63. - The fallback code using deposit works just as well for 32-bit. */ - a0 = args[0], a1 = args[1]; - if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { - a0 = TCG_REG_R0; - } - if (const_args[4]) { - tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); - } else { - tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); - } - if (const_args[5]) { - tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); - } else { - tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); - } - if (a0 != args[0]) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); - } - break; - -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_sub2_i64: -#else - case INDEX_op_sub2_i32: -#endif - a0 = args[0], a1 = args[1]; - if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { - a0 = TCG_REG_R0; - } - if (const_args[2]) { - tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); - } else { - tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); - } - if (const_args[3]) { - tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); - } else { - tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); - } - if (a0 != args[0]) { - tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); - } - break; - - case INDEX_op_muluh_i32: - tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); - break; - case INDEX_op_mulsh_i32: - tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); - break; - case INDEX_op_muluh_i64: - tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); - break; - case INDEX_op_mulsh_i64: - tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); - break; - - case INDEX_op_mb: - tcg_out_mb(s, args[0]); - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) -{ - switch (opc) { - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_not_vec: - return 1; - case INDEX_op_orc_vec: - return have_isa_2_07; - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_rotlv_vec: - return vece <= MO_32 || have_isa_2_07; - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - return vece <= MO_32; - case INDEX_op_cmp_vec: - case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - case INDEX_op_sari_vec: - case INDEX_op_rotli_vec: - return vece <= MO_32 || have_isa_2_07 ? -1 : 0; - case INDEX_op_neg_vec: - return vece >= MO_32 && have_isa_3_00; - case INDEX_op_mul_vec: - switch (vece) { - case MO_8: - case MO_16: - return -1; - case MO_32: - return have_isa_2_07 ? 1 : -1; - } - return 0; - case INDEX_op_bitsel_vec: - return have_vsx; - case INDEX_op_rotrv_vec: - return -1; - default: - return 0; - } -} - -static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg dst, TCGReg src) -{ - tcg_debug_assert(dst >= TCG_REG_V0); - - /* Splat from integer reg allowed via constraints for v3.00. */ - if (src < TCG_REG_V0) { - tcg_debug_assert(have_isa_3_00); - switch (vece) { - case MO_64: - tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); - return true; - case MO_32: - tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); - return true; - default: - /* Fail, so that we fall back on either dupm or mov+dup. */ - return false; - } - } - - /* - * Recall we use (or emulate) VSX integer loads, so the integer is - * right justified within the left (zero-index) double-word. - */ - switch (vece) { - case MO_8: - tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); - break; - case MO_16: - tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); - break; - case MO_32: - tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); - break; - case MO_64: - if (have_vsx) { - tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); - break; - } - tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); - tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); - break; - default: - g_assert_not_reached(); - } - return true; -} - -static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, - TCGReg out, TCGReg base, intptr_t offset) -{ - int elt; - - tcg_debug_assert(out >= TCG_REG_V0); - switch (vece) { - case MO_8: - if (have_isa_3_00) { - tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); - } else { - tcg_out_mem_long(s, 0, LVEBX, out, base, offset); - } - elt = extract32(offset, 0, 4); -#ifndef HOST_WORDS_BIGENDIAN - elt ^= 15; -#endif - tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); - break; - case MO_16: - tcg_debug_assert((offset & 1) == 0); - if (have_isa_3_00) { - tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); - } else { - tcg_out_mem_long(s, 0, LVEHX, out, base, offset); - } - elt = extract32(offset, 1, 3); -#ifndef HOST_WORDS_BIGENDIAN - elt ^= 7; -#endif - tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); - break; - case MO_32: - if (have_isa_3_00) { - tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); - break; - } - tcg_debug_assert((offset & 3) == 0); - tcg_out_mem_long(s, 0, LVEWX, out, base, offset); - elt = extract32(offset, 2, 2); -#ifndef HOST_WORDS_BIGENDIAN - elt ^= 3; -#endif - tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); - break; - case MO_64: - if (have_vsx) { - tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); - break; - } - tcg_debug_assert((offset & 7) == 0); - tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); - tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); - elt = extract32(offset, 3, 1); -#ifndef HOST_WORDS_BIGENDIAN - elt = !elt; -#endif - if (elt) { - tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); - } else { - tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); - } - break; - default: - g_assert_not_reached(); - } - return true; -} - -static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, - unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) -{ - static const uint32_t - add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, - sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, - neg_op[4] = { 0, 0, VNEGW, VNEGD }, - eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, - ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, - gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, - gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, - ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, - usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, - sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, - ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, - umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, - smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, - umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, - smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, - shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, - shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, - sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, - mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, - mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, - muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, - mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, - pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, - rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; - - TCGType type = vecl + TCG_TYPE_V64; - TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; - uint32_t insn; - - switch (opc) { - case INDEX_op_ld_vec: - tcg_out_ld(s, type, a0, a1, a2); - return; - case INDEX_op_st_vec: - tcg_out_st(s, type, a0, a1, a2); - return; - case INDEX_op_dupm_vec: - tcg_out_dupm_vec(s, type, vece, a0, a1, a2); - return; - - case INDEX_op_add_vec: - insn = add_op[vece]; - break; - case INDEX_op_sub_vec: - insn = sub_op[vece]; - break; - case INDEX_op_neg_vec: - insn = neg_op[vece]; - a2 = a1; - a1 = 0; - break; - case INDEX_op_mul_vec: - tcg_debug_assert(vece == MO_32 && have_isa_2_07); - insn = VMULUWM; - break; - case INDEX_op_ssadd_vec: - insn = ssadd_op[vece]; - break; - case INDEX_op_sssub_vec: - insn = sssub_op[vece]; - break; - case INDEX_op_usadd_vec: - insn = usadd_op[vece]; - break; - case INDEX_op_ussub_vec: - insn = ussub_op[vece]; - break; - case INDEX_op_smin_vec: - insn = smin_op[vece]; - break; - case INDEX_op_umin_vec: - insn = umin_op[vece]; - break; - case INDEX_op_smax_vec: - insn = smax_op[vece]; - break; - case INDEX_op_umax_vec: - insn = umax_op[vece]; - break; - case INDEX_op_shlv_vec: - insn = shlv_op[vece]; - break; - case INDEX_op_shrv_vec: - insn = shrv_op[vece]; - break; - case INDEX_op_sarv_vec: - insn = sarv_op[vece]; - break; - case INDEX_op_and_vec: - insn = VAND; - break; - case INDEX_op_or_vec: - insn = VOR; - break; - case INDEX_op_xor_vec: - insn = VXOR; - break; - case INDEX_op_andc_vec: - insn = VANDC; - break; - case INDEX_op_not_vec: - insn = VNOR; - a2 = a1; - break; - case INDEX_op_orc_vec: - insn = VORC; - break; - - case INDEX_op_cmp_vec: - switch (args[3]) { - case TCG_COND_EQ: - insn = eq_op[vece]; - break; - case TCG_COND_NE: - insn = ne_op[vece]; - break; - case TCG_COND_GT: - insn = gts_op[vece]; - break; - case TCG_COND_GTU: - insn = gtu_op[vece]; - break; - default: - g_assert_not_reached(); - } - break; - - case INDEX_op_bitsel_vec: - tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); - return; - - case INDEX_op_dup2_vec: - assert(TCG_TARGET_REG_BITS == 32); - /* With inputs a1 = xLxx, a2 = xHxx */ - tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ - tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ - tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ - return; - - case INDEX_op_ppc_mrgh_vec: - insn = mrgh_op[vece]; - break; - case INDEX_op_ppc_mrgl_vec: - insn = mrgl_op[vece]; - break; - case INDEX_op_ppc_muleu_vec: - insn = muleu_op[vece]; - break; - case INDEX_op_ppc_mulou_vec: - insn = mulou_op[vece]; - break; - case INDEX_op_ppc_pkum_vec: - insn = pkum_op[vece]; - break; - case INDEX_op_rotlv_vec: - insn = rotl_op[vece]; - break; - case INDEX_op_ppc_msum_vec: - tcg_debug_assert(vece == MO_16); - tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); - return; - - case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ - case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ - case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ - default: - g_assert_not_reached(); - } - - tcg_debug_assert(insn != 0); - tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); -} - -static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGArg imm, TCGOpcode opci) -{ - TCGv_vec t1 = tcg_temp_new_vec(type); - - /* Splat w/bytes for xxspltib. */ - tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); - vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(t1)); - tcg_temp_free_vec(t1); -} - -static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2, TCGCond cond) -{ - bool need_swap = false, need_inv = false; - - tcg_debug_assert(vece <= MO_32 || have_isa_2_07); - - switch (cond) { - case TCG_COND_EQ: - case TCG_COND_GT: - case TCG_COND_GTU: - break; - case TCG_COND_NE: - if (have_isa_3_00 && vece <= MO_32) { - break; - } - /* fall through */ - case TCG_COND_LE: - case TCG_COND_LEU: - need_inv = true; - break; - case TCG_COND_LT: - case TCG_COND_LTU: - need_swap = true; - break; - case TCG_COND_GE: - case TCG_COND_GEU: - need_swap = need_inv = true; - break; - default: - g_assert_not_reached(); - } - - if (need_inv) { - cond = tcg_invert_cond(cond); - } - if (need_swap) { - TCGv_vec t1; - t1 = v1, v1 = v2, v2 = t1; - cond = tcg_swap_cond(cond); - } - - vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); - - if (need_inv) { - tcg_gen_not_vec(vece, v0, v0); - } -} - -static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, - TCGv_vec v1, TCGv_vec v2) -{ - TCGv_vec t1 = tcg_temp_new_vec(type); - TCGv_vec t2 = tcg_temp_new_vec(type); - TCGv_vec t3, t4; - - switch (vece) { - case MO_8: - case MO_16: - vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), - tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), - tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), - tcgv_vec_arg(v0), tcgv_vec_arg(t1)); - break; - - case MO_32: - tcg_debug_assert(!have_isa_2_07); - t3 = tcg_temp_new_vec(type); - t4 = tcg_temp_new_vec(type); - tcg_gen_dupi_vec(MO_8, t4, -16); - vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), - tcgv_vec_arg(v2), tcgv_vec_arg(t4)); - vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), - tcgv_vec_arg(v1), tcgv_vec_arg(v2)); - tcg_gen_dupi_vec(MO_8, t3, 0); - vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), - tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); - vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), - tcgv_vec_arg(t3), tcgv_vec_arg(t4)); - tcg_gen_add_vec(MO_32, v0, t2, t3); - tcg_temp_free_vec(t3); - tcg_temp_free_vec(t4); - break; - - default: - g_assert_not_reached(); - } - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); -} - -void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, - TCGArg a0, ...) -{ - va_list va; - TCGv_vec v0, v1, v2, t0; - TCGArg a2; - - va_start(va, a0); - v0 = temp_tcgv_vec(arg_temp(a0)); - v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - a2 = va_arg(va, TCGArg); - - switch (opc) { - case INDEX_op_shli_vec: - expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); - break; - case INDEX_op_shri_vec: - expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); - break; - case INDEX_op_sari_vec: - expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); - break; - case INDEX_op_rotli_vec: - expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); - break; - case INDEX_op_cmp_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); - break; - case INDEX_op_mul_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - expand_vec_mul(type, vece, v0, v1, v2); - break; - case INDEX_op_rotlv_vec: - v2 = temp_tcgv_vec(arg_temp(a2)); - t0 = tcg_temp_new_vec(type); - tcg_gen_neg_vec(vece, t0, v2); - tcg_gen_rotlv_vec(vece, v0, v1, t0); - tcg_temp_free_vec(t0); - break; - default: - g_assert_not_reached(); - } - va_end(va); -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } }; - static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } }; - static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } }; - static const TCGTargetOpDef r_rI_ri - = { .args_ct_str = { "r", "rI", "ri" } }; - static const TCGTargetOpDef r_rI_rT - = { .args_ct_str = { "r", "rI", "rT" } }; - static const TCGTargetOpDef r_r_rZW - = { .args_ct_str = { "r", "r", "rZW" } }; - static const TCGTargetOpDef L_L_L_L - = { .args_ct_str = { "L", "L", "L", "L" } }; - static const TCGTargetOpDef S_S_S_S - = { .args_ct_str = { "S", "S", "S", "S" } }; - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } }; - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "0", "rZ" } }; - static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "ri", "ri" } }; - static const TCGTargetOpDef add2 - = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } }; - static const TCGTargetOpDef sub2 - = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } }; - static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } }; - static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } }; - static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } }; - static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } }; - static const TCGTargetOpDef v_v_v_v - = { .args_ct_str = { "v", "v", "v", "v" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_ctpop_i32: - case INDEX_op_neg_i32: - case INDEX_op_not_i32: - case INDEX_op_ext8s_i32: - case INDEX_op_ext16s_i32: - case INDEX_op_bswap16_i32: - case INDEX_op_bswap32_i32: - case INDEX_op_extract_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - case INDEX_op_ctpop_i64: - case INDEX_op_neg_i64: - case INDEX_op_not_i64: - case INDEX_op_ext8s_i64: - case INDEX_op_ext16s_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_add_i32: - case INDEX_op_and_i32: - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_andc_i32: - case INDEX_op_orc_i32: - case INDEX_op_eqv_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: - case INDEX_op_setcond_i32: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i64: - case INDEX_op_setcond_i64: - return &r_r_ri; - case INDEX_op_mul_i32: - case INDEX_op_mul_i64: - return &r_r_rI; - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - case INDEX_op_nand_i32: - case INDEX_op_nor_i32: - case INDEX_op_muluh_i32: - case INDEX_op_mulsh_i32: - case INDEX_op_orc_i64: - case INDEX_op_eqv_i64: - case INDEX_op_nand_i64: - case INDEX_op_nor_i64: - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_mulsh_i64: - case INDEX_op_muluh_i64: - return &r_r_r; - case INDEX_op_sub_i32: - return &r_rI_ri; - case INDEX_op_add_i64: - return &r_r_rT; - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - return &r_r_rU; - case INDEX_op_sub_i64: - return &r_rI_rT; - case INDEX_op_clz_i32: - case INDEX_op_ctz_i32: - case INDEX_op_clz_i64: - case INDEX_op_ctz_i64: - return &r_r_rZW; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &r_ri; - - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - return &movc; - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - return &dep; - case INDEX_op_brcond2_i32: - return &br2; - case INDEX_op_setcond2_i32: - return &setc2; - case INDEX_op_add2_i64: - case INDEX_op_add2_i32: - return &add2; - case INDEX_op_sub2_i64: - case INDEX_op_sub2_i32: - return &sub2; - - case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &r_L : &r_L_L); - case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? &S_S : &S_S_S); - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L); - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? &S_S - : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S); - - case INDEX_op_add_vec: - case INDEX_op_sub_vec: - case INDEX_op_mul_vec: - case INDEX_op_and_vec: - case INDEX_op_or_vec: - case INDEX_op_xor_vec: - case INDEX_op_andc_vec: - case INDEX_op_orc_vec: - case INDEX_op_cmp_vec: - case INDEX_op_ssadd_vec: - case INDEX_op_sssub_vec: - case INDEX_op_usadd_vec: - case INDEX_op_ussub_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: - case INDEX_op_shlv_vec: - case INDEX_op_shrv_vec: - case INDEX_op_sarv_vec: - case INDEX_op_rotlv_vec: - case INDEX_op_rotrv_vec: - case INDEX_op_ppc_mrgh_vec: - case INDEX_op_ppc_mrgl_vec: - case INDEX_op_ppc_muleu_vec: - case INDEX_op_ppc_mulou_vec: - case INDEX_op_ppc_pkum_vec: - case INDEX_op_dup2_vec: - return &v_v_v; - case INDEX_op_not_vec: - case INDEX_op_neg_vec: - return &v_v; - case INDEX_op_dup_vec: - return have_isa_3_00 ? &v_vr : &v_v; - case INDEX_op_ld_vec: - case INDEX_op_st_vec: - case INDEX_op_dupm_vec: - return &v_r; - case INDEX_op_bitsel_vec: - case INDEX_op_ppc_msum_vec: - return &v_v_v_v; - - default: - return NULL; - } -} - -static void tcg_target_init(TCGContext *s) -{ - unsigned long hwcap = qemu_getauxval(AT_HWCAP); - unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); - - have_isa = tcg_isa_base; - if (hwcap & PPC_FEATURE_ARCH_2_06) { - have_isa = tcg_isa_2_06; - } -#ifdef PPC_FEATURE2_ARCH_2_07 - if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { - have_isa = tcg_isa_2_07; - } -#endif -#ifdef PPC_FEATURE2_ARCH_3_00 - if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { - have_isa = tcg_isa_3_00; - } -#endif - -#ifdef PPC_FEATURE2_HAS_ISEL - /* Prefer explicit instruction from the kernel. */ - have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; -#else - /* Fall back to knowing Power7 (2.06) has ISEL. */ - have_isel = have_isa_2_06; -#endif - - if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { - have_altivec = true; - /* We only care about the portion of VSX that overlaps Altivec. */ - if (hwcap & PPC_FEATURE_HAS_VSX) { - have_vsx = true; - } - } - - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - if (have_altivec) { - tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; - tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; - } - - tcg_target_call_clobber_regs = 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); - - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ -#if defined(_CALL_SYSV) - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ -#endif -#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ -#endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); - if (USE_REG_TB) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ - } -} - -#ifdef __ELF__ -typedef struct { - DebugFrameCIE cie; - DebugFrameFDEHeader fde; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; -} DebugFrame; - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); - -#if TCG_TARGET_REG_BITS == 64 -# define ELF_HOST_MACHINE EM_PPC64 -#else -# define ELF_HOST_MACHINE EM_PPC -#endif - -static DebugFrame debug_frame = { - .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .cie.id = -1, - .cie.version = 1, - .cie.code_align = 1, - .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ - .cie.return_column = 65, - - /* Total FDE size does not include the "len" member. */ - .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), - - .fde_def_cfa = { - 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ - 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - uint8_t *p = &debug_frame.fde_reg_ofs[3]; - int i; - - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { - p[0] = 0x80 + tcg_target_callee_save_regs[i]; - p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; - } - - debug_frame.fde.func_start = (uintptr_t)buf; - debug_frame.fde.func_len = buf_size; - - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} -#endif /* __ELF__ */ - -void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p, start1, stop1; - size_t dsize = qemu_dcache_linesize; - size_t isize = qemu_icache_linesize; - - start1 = start & ~(dsize - 1); - stop1 = (stop + dsize - 1) & ~(dsize - 1); - for (p = start1; p < stop1; p += dsize) { - asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - - start &= start & ~(isize - 1); - stop1 = (stop + isize - 1) & ~(isize - 1); - for (p = start1; p < stop1; p += isize) { - asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - asm volatile ("isync" : : : "memory"); -} diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc new file mode 100644 index 0000000000..2dfb07e247 --- /dev/null +++ b/tcg/riscv/tcg-target.c.inc @@ -0,0 +1,1915 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2018 SiFive, Inc + * Copyright (c) 2008-2009 Arnaud Patard + * Copyright (c) 2009 Aurelien Jarno + * Copyright (c) 2008 Fabrice Bellard + * + * Based on i386/tcg-target.c and mips/tcg-target.c + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "../tcg-pool.c.inc" + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "zero", + "ra", + "sp", + "gp", + "tp", + "t0", + "t1", + "t2", + "s0", + "s1", + "a0", + "a1", + "a2", + "a3", + "a4", + "a5", + "a6", + "a7", + "s2", + "s3", + "s4", + "s5", + "s6", + "s7", + "s8", + "s9", + "s10", + "s11", + "t3", + "t4", + "t5", + "t6" +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { + /* Call saved registers */ + /* TCG_REG_S0 reservered for TCG_AREG0 */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + + /* Call clobbered registers */ + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + + /* Argument registers */ + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, +}; + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_M12 0x800 + +static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) +{ + if (TCG_TARGET_REG_BITS == 32) { + return sextract32(val, pos, len); + } else { + return sextract64(val, pos, len); + } +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + break; + case 'L': + /* qemu_ld/qemu_st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ +#if defined(CONFIG_SOFTMMU) + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); +#endif + break; + case 'I': + ct->ct |= TCG_CT_CONST_S12; + break; + case 'N': + ct->ct |= TCG_CT_CONST_N12; + break; + case 'M': + ct->ct |= TCG_CT_CONST_M12; + break; + case 'Z': + /* we can use a zero immediate as a zero register argument. */ + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { + return 1; + } + return 0; +} + +/* + * RISC-V Base ISA opcodes (IM) + */ + +typedef enum { + OPC_ADD = 0x33, + OPC_ADDI = 0x13, + OPC_AND = 0x7033, + OPC_ANDI = 0x7013, + OPC_AUIPC = 0x17, + OPC_BEQ = 0x63, + OPC_BGE = 0x5063, + OPC_BGEU = 0x7063, + OPC_BLT = 0x4063, + OPC_BLTU = 0x6063, + OPC_BNE = 0x1063, + OPC_DIV = 0x2004033, + OPC_DIVU = 0x2005033, + OPC_JAL = 0x6f, + OPC_JALR = 0x67, + OPC_LB = 0x3, + OPC_LBU = 0x4003, + OPC_LD = 0x3003, + OPC_LH = 0x1003, + OPC_LHU = 0x5003, + OPC_LUI = 0x37, + OPC_LW = 0x2003, + OPC_LWU = 0x6003, + OPC_MUL = 0x2000033, + OPC_MULH = 0x2001033, + OPC_MULHSU = 0x2002033, + OPC_MULHU = 0x2003033, + OPC_OR = 0x6033, + OPC_ORI = 0x6013, + OPC_REM = 0x2006033, + OPC_REMU = 0x2007033, + OPC_SB = 0x23, + OPC_SD = 0x3023, + OPC_SH = 0x1023, + OPC_SLL = 0x1033, + OPC_SLLI = 0x1013, + OPC_SLT = 0x2033, + OPC_SLTI = 0x2013, + OPC_SLTIU = 0x3013, + OPC_SLTU = 0x3033, + OPC_SRA = 0x40005033, + OPC_SRAI = 0x40005013, + OPC_SRL = 0x5033, + OPC_SRLI = 0x5013, + OPC_SUB = 0x40000033, + OPC_SW = 0x2023, + OPC_XOR = 0x4033, + OPC_XORI = 0x4013, + +#if TCG_TARGET_REG_BITS == 64 + OPC_ADDIW = 0x1b, + OPC_ADDW = 0x3b, + OPC_DIVUW = 0x200503b, + OPC_DIVW = 0x200403b, + OPC_MULW = 0x200003b, + OPC_REMUW = 0x200703b, + OPC_REMW = 0x200603b, + OPC_SLLIW = 0x101b, + OPC_SLLW = 0x103b, + OPC_SRAIW = 0x4000501b, + OPC_SRAW = 0x4000503b, + OPC_SRLIW = 0x501b, + OPC_SRLW = 0x503b, + OPC_SUBW = 0x4000003b, +#else + /* Simplify code throughout by defining aliases for RV32. */ + OPC_ADDIW = OPC_ADDI, + OPC_ADDW = OPC_ADD, + OPC_DIVUW = OPC_DIVU, + OPC_DIVW = OPC_DIV, + OPC_MULW = OPC_MUL, + OPC_REMUW = OPC_REMU, + OPC_REMW = OPC_REM, + OPC_SLLIW = OPC_SLLI, + OPC_SLLW = OPC_SLL, + OPC_SRAIW = OPC_SRAI, + OPC_SRAW = OPC_SRA, + OPC_SRLIW = OPC_SRLI, + OPC_SRLW = OPC_SRL, + OPC_SUBW = OPC_SUB, +#endif + + OPC_FENCE = 0x0000000f, +} RISCVInsn; + +/* + * RISC-V immediate and instruction encoders (excludes 16-bit RVC) + */ + +/* Type-R */ + +static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; +} + +/* Type-I */ + +static int32_t encode_imm12(uint32_t imm) +{ + return (imm & 0xfff) << 20; +} + +static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); +} + +/* Type-S */ + +static int32_t encode_simm12(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0xFE0) << 20; + ret |= (imm & 0x1F) << 7; + + return ret; +} + +static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0x1000) << 19; + ret |= (imm & 0x7e0) << 20; + ret |= (imm & 0x1e) << 7; + ret |= (imm & 0x800) >> 4; + + return ret; +} + +static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); +} + +/* Type-U */ + +static int32_t encode_uimm20(uint32_t imm) +{ + return imm & 0xfffff000; +} + +static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm20(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0x0007fe) << (21 - 1); + ret |= (imm & 0x000800) << (20 - 11); + ret |= (imm & 0x0ff000) << (12 - 12); + ret |= (imm & 0x100000) << (31 - 20); + + return ret; +} + +static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); +} + +/* + * RISC-V instruction emitters + */ + +static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, + TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + tcg_out32(s, encode_r(opc, rd, rs1, rs2)); +} + +static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, + TCGReg rd, TCGReg rs1, TCGArg imm) +{ + tcg_out32(s, encode_i(opc, rd, rs1, imm)); +} + +static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, + TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + tcg_out32(s, encode_s(opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, + TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t imm) +{ + tcg_out32(s, encode_u(opc, rd, imm)); +} + +static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t imm) +{ + tcg_out32(s, encode_uj(opc, rd, imm)); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + } +} + +/* + * Relocations + */ + +static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + + if (offset == sextreg(offset, 1, 12) << 1) { + code_ptr[0] |= encode_sbimm12(offset); + return true; + } + + return false; +} + +static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + + if (offset == sextreg(offset, 1, 20) << 1) { + code_ptr[0] |= encode_ujimm20(offset); + return true; + } + + return false; +} + +static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + int32_t lo = sextreg(offset, 0, 12); + int32_t hi = offset - lo; + + if (offset == hi + lo) { + code_ptr[0] |= encode_uimm20(hi); + code_ptr[1] |= encode_imm12(lo); + return true; + } + + return false; +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + uint32_t insn = *code_ptr; + intptr_t diff; + bool short_jmp; + + tcg_debug_assert(addend == 0); + + switch (type) { + case R_RISCV_BRANCH: + diff = value - (uintptr_t)code_ptr; + short_jmp = diff == sextreg(diff, 0, 12); + if (short_jmp) { + return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); + } else { + /* Invert the condition */ + insn = insn ^ (1 << 12); + /* Clear the offset */ + insn &= 0x01fff07f; + /* Set the offset to the PC + 8 */ + insn |= encode_sbimm12(8); + + /* Move forward */ + code_ptr[0] = insn; + + /* Overwrite the NOP with jal x0,value */ + diff = value - (uintptr_t)(code_ptr + 1); + insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); + code_ptr[1] = insn; + + return true; + } + break; + case R_RISCV_JAL: + return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); + case R_RISCV_CALL: + return reloc_call(code_ptr, (tcg_insn_unit *)value); + default: + tcg_abort(); + } +} + +/* + * TCG intrinsics + */ + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + if (ret == arg) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, + tcg_target_long val) +{ + tcg_target_long lo, hi, tmp; + int shift, ret; + + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + lo = sextreg(val, 0, 12); + if (val == lo) { + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); + return; + } + + hi = val - lo; + if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { + tcg_out_opc_upper(s, OPC_LUI, rd, hi); + if (lo != 0) { + tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); + } + return; + } + + /* We can only be here if TCG_TARGET_REG_BITS != 32 */ + tmp = tcg_pcrel_diff(s, (void *)val); + if (tmp == (int32_t)tmp) { + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); + ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); + tcg_debug_assert(ret == true); + return; + } + + /* Look for a single 20-bit section. */ + shift = ctz64(val); + tmp = val >> shift; + if (tmp == sextreg(tmp, 0, 20)) { + tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); + if (shift > 12) { + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); + } else { + tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); + } + return; + } + + /* Look for a few high zero bits, with lots of bits set in the middle. */ + shift = clz64(val); + tmp = val << shift; + if (tmp == sextreg(tmp, 12, 20) << 12) { + tcg_out_opc_upper(s, OPC_LUI, rd, tmp); + tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); + return; + } else if (tmp == sextreg(tmp, 0, 12)) { + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); + tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); + return; + } + + /* Drop into the constant pool. */ + new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); + tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); +} + +static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); +} + +static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); + tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); +} + +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); + tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); +} + +static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); +} + +static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); +} + +static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); +} + +static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, + TCGReg addr, intptr_t offset) +{ + intptr_t imm12 = sextreg(offset, 0, 12); + + if (offset != imm12) { + intptr_t diff = offset - (uintptr_t)s->code_ptr; + + if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { + imm12 = sextreg(diff, 0, 12); + tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); + if (addr != TCG_REG_ZERO) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); + } + } + addr = TCG_REG_TMP2; + } + + switch (opc) { + case OPC_SB: + case OPC_SH: + case OPC_SW: + case OPC_SD: + tcg_out_opc_store(s, opc, addr, data, imm12); + break; + case OPC_LB: + case OPC_LBU: + case OPC_LH: + case OPC_LHU: + case OPC_LW: + case OPC_LWU: + case OPC_LD: + tcg_out_opc_imm(s, opc, data, addr, imm12); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); +} + +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (val == 0) { + tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); + return true; + } + return false; +} + +static void tcg_out_addsub2(TCGContext *s, + TCGReg rl, TCGReg rh, + TCGReg al, TCGReg ah, + TCGArg bl, TCGArg bh, + bool cbl, bool cbh, bool is_sub, bool is32bit) +{ + const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; + const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; + const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; + TCGReg th = TCG_REG_TMP1; + + /* If we have a negative constant such that negating it would + make the high part zero, we can (usually) eliminate one insn. */ + if (cbl && cbh && bh == -1 && bl != 0) { + bl = -bl; + bh = 0; + is_sub = !is_sub; + } + + /* By operating on the high part first, we get to use the final + carry operation to move back from the temporary. */ + if (!cbh) { + tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); + } else if (bh != 0 || ah == rl) { + tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); + } else { + th = ah; + } + + /* Note that tcg optimization should eliminate the bl == 0 case. */ + if (is_sub) { + if (cbl) { + tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); + tcg_out_opc_imm(s, opc_addi, rl, al, -bl); + } else { + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); + tcg_out_opc_reg(s, opc_sub, rl, al, bl); + } + tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); + } else { + if (cbl) { + tcg_out_opc_imm(s, opc_addi, rl, al, bl); + tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); + } else if (rl == al && rl == bl) { + tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); + tcg_out_opc_reg(s, opc_addi, rl, al, bl); + } else { + tcg_out_opc_reg(s, opc_add, rl, al, bl); + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, + rl, (rl == bl ? al : bl)); + } + tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); + } +} + +static const struct { + RISCVInsn op; + bool swap; +} tcg_brcond_to_riscv[] = { + [TCG_COND_EQ] = { OPC_BEQ, false }, + [TCG_COND_NE] = { OPC_BNE, false }, + [TCG_COND_LT] = { OPC_BLT, false }, + [TCG_COND_GE] = { OPC_BGE, false }, + [TCG_COND_LE] = { OPC_BGE, true }, + [TCG_COND_GT] = { OPC_BLT, true }, + [TCG_COND_LTU] = { OPC_BLTU, false }, + [TCG_COND_GEU] = { OPC_BGEU, false }, + [TCG_COND_LEU] = { OPC_BGEU, true }, + [TCG_COND_GTU] = { OPC_BLTU, true } +}; + +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, + TCGReg arg2, TCGLabel *l) +{ + RISCVInsn op = tcg_brcond_to_riscv[cond].op; + + tcg_debug_assert(op != 0); + + if (tcg_brcond_to_riscv[cond].swap) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + + if (l->has_value) { + intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); + if (diff == sextreg(diff, 0, 12)) { + tcg_out_opc_branch(s, op, arg1, arg2, diff); + } else { + /* Invert the conditional branch. */ + tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); + } + } else { + tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); + tcg_out_opc_branch(s, op, arg1, arg2, 0); + /* NOP to allow patching later */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + } +} + +static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, TCGReg arg2) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); + break; + case TCG_COND_NE: + tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); + break; + case TCG_COND_LT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + break; + case TCG_COND_GE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + break; + case TCG_COND_LTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + break; + case TCG_COND_GEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + break; + default: + g_assert_not_reached(); + break; + } +} + +static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, + TCGReg bl, TCGReg bh, TCGLabel *l) +{ + /* todo */ + g_assert_not_reached(); +} + +static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) +{ + /* todo */ + g_assert_not_reached(); +} + +static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +{ + ptrdiff_t offset = tcg_pcrel_diff(s, target); + tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); +} + +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +{ + TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; + ptrdiff_t offset = tcg_pcrel_diff(s, arg); + int ret; + + if (offset == sextreg(offset, 1, 20) << 1) { + /* short jump: -2097150 to 2097152 */ + tcg_out_opc_jump(s, OPC_JAL, link, offset); + } else if (TCG_TARGET_REG_BITS == 32 || + offset == sextreg(offset, 1, 31) << 1) { + /* long jump: -2147483646 to 2147483648 */ + tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); + ret = reloc_call(s->code_ptr - 2, arg);\ + tcg_debug_assert(ret == true); + } else if (TCG_TARGET_REG_BITS == 64) { + /* far jump: 64-bit */ + tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); + tcg_target_long base = (tcg_target_long)arg - imm; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); + } else { + g_assert_not_reached(); + } +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +{ + tcg_out_call_int(s, arg, false); +} + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + tcg_insn_unit insn = OPC_FENCE; + + if (a0 & TCG_MO_LD_LD) { + insn |= 0x02200000; + } + if (a0 & TCG_MO_ST_LD) { + insn |= 0x01200000; + } + if (a0 & TCG_MO_LD_ST) { + insn |= 0x02100000; + } + if (a0 & TCG_MO_ST_ST) { + insn |= 0x02200000; + } + tcg_out32(s, insn); +} + +/* + * Load/store and TLB + */ + +#if defined(CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * TCGMemOpIdx oi, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL] = helper_le_ldsl_mmu, +#endif + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_BESL] = helper_be_ldsl_mmu, +#endif + [MO_BEQ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, TCGMemOpIdx oi, + * uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +/* We don't support oversize guests */ +QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); + +/* We expect to use a 12-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + +static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, TCGMemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) +{ + MemOp opc = get_memop(oi); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + tcg_target_long compare_mask; + int mem_index = get_mmuidx(oi); + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); + TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; + + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_load ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); + if (compare_mask == sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + } + + /* Compare masked address with the TLB entry. */ + label_ptr[0] = s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + /* NOP to allow patching later */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + + /* TLB Hit - translate address using addend. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, addrl); + addrl = TCG_REG_TMP0; + } + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); +} + +static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, + TCGType ext, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + void *raddr, tcg_insn_unit **label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0] = label_ptr[0]; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } + + /* call load helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); + + tcg_out_goto(s, l->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + MemOp opc = get_memop(oi); + MemOp s_bits = opc & MO_SIZE; + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + TCGReg a4 = tcg_target_call_iarg_regs[4]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } + + /* call store helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); + switch (s_bits) { + case MO_8: + tcg_out_ext8u(s, a2, a2); + break; + case MO_16: + tcg_out_ext16u(s, a2, a2); + break; + default: + break; + } + tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + + tcg_out_goto(s, l->raddr); + return true; +} +#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc, bool is_64) +{ + const MemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + break; + case MO_UW: + tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + break; + case MO_SW: + tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + break; + } + /* FALLTHRU */ + case MO_SL: + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + break; + case MO_Q: + /* Prefer to load from offset 0 first, but allow for overlap. */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + } else if (lo != base) { + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + } else { + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc) +{ + const MemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_out_opc_store(s, OPC_SB, base, lo, 0); + break; + case MO_16: + tcg_out_opc_store(s, OPC_SH, base, lo, 0); + break; + case MO_32: + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_store(s, OPC_SD, base, lo, 0); + } else { + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, hi, 4); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + MemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); +#endif +} + +static tcg_insn_unit *tb_ret_addr; + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + TCGArg a0 = args[0]; + TCGArg a1 = args[1]; + TCGArg a2 = args[2]; + int c2 = const_args[2]; + + switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_call_int(s, s->code_gen_epilogue, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); + tcg_out_call_int(s, tb_ret_addr, true); + } + break; + + case INDEX_op_goto_tb: + assert(s->tb_jmp_insn_offset == 0); + /* indirect jump method */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); + set_jmp_reset_offset(s, a0); + break; + + case INDEX_op_goto_ptr: + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); + break; + + case INDEX_op_br: + tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); + break; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + tcg_out_ldst(s, OPC_LBU, a0, a1, a2); + break; + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + tcg_out_ldst(s, OPC_LB, a0, a1, a2); + break; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + tcg_out_ldst(s, OPC_LHU, a0, a1, a2); + break; + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + tcg_out_ldst(s, OPC_LH, a0, a1, a2); + break; + case INDEX_op_ld32u_i64: + tcg_out_ldst(s, OPC_LWU, a0, a1, a2); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32s_i64: + tcg_out_ldst(s, OPC_LW, a0, a1, a2); + break; + case INDEX_op_ld_i64: + tcg_out_ldst(s, OPC_LD, a0, a1, a2); + break; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + tcg_out_ldst(s, OPC_SB, a0, a1, a2); + break; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + tcg_out_ldst(s, OPC_SH, a0, a1, a2); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_ldst(s, OPC_SW, a0, a1, a2); + break; + case INDEX_op_st_i64: + tcg_out_ldst(s, OPC_SD, a0, a1, a2); + break; + + case INDEX_op_add_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); + } + break; + case INDEX_op_add_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); + } + break; + + case INDEX_op_sub_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); + } else { + tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); + } + break; + case INDEX_op_sub_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); + } else { + tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); + } + break; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); + } + break; + + case INDEX_op_or_i32: + case INDEX_op_or_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); + } + break; + + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); + } + break; + + case INDEX_op_not_i32: + case INDEX_op_not_i64: + tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); + break; + + case INDEX_op_neg_i32: + tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); + break; + case INDEX_op_neg_i64: + tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); + break; + + case INDEX_op_mul_i32: + tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); + break; + case INDEX_op_mul_i64: + tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); + break; + + case INDEX_op_div_i32: + tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); + break; + case INDEX_op_div_i64: + tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); + break; + + case INDEX_op_divu_i32: + tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); + break; + case INDEX_op_divu_i64: + tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); + break; + + case INDEX_op_rem_i32: + tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); + break; + case INDEX_op_rem_i64: + tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); + break; + + case INDEX_op_remu_i32: + tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); + break; + case INDEX_op_remu_i64: + tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); + break; + + case INDEX_op_shl_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); + } + break; + case INDEX_op_shl_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); + } + break; + + case INDEX_op_shr_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); + } + break; + case INDEX_op_shr_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); + } + break; + + case INDEX_op_sar_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); + } + break; + case INDEX_op_sar_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); + } + break; + + case INDEX_op_add2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], false, true); + break; + case INDEX_op_add2_i64: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], false, false); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], true, true); + break; + case INDEX_op_sub2_i64: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], true, false); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); + break; + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tcg_out_setcond(s, args[3], a0, a1, a2); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, true); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, false); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, true); + break; + + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + tcg_out_ext8u(s, a0, a1); + break; + + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + tcg_out_ext16u(s, a0, a1); + break; + + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + tcg_out_ext32u(s, a0, a1); + break; + + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + tcg_out_ext8s(s, a0, a1); + break; + + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + tcg_out_ext16s(s, a0, a1); + break; + + case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_ext_i32_i64: + tcg_out_ext32s(s, a0, a1); + break; + + case INDEX_op_extrh_i64_i32: + tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); + break; + + case INDEX_op_mulsh_i32: + case INDEX_op_mulsh_i64: + tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); + break; + + case INDEX_op_muluh_i32: + case INDEX_op_muluh_i64: + tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + g_assert_not_reached(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r + = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r + = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef rZ_r + = { .args_ct_str = { "rZ", "r" } }; + static const TCGTargetOpDef rZ_rZ + = { .args_ct_str = { "rZ", "rZ" } }; + static const TCGTargetOpDef rZ_rZ_rZ_rZ + = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef r_r_ri + = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI + = { .args_ct_str = { "r", "r", "rI" } }; + static const TCGTargetOpDef r_rZ_rN + = { .args_ct_str = { "r", "rZ", "rN" } }; + static const TCGTargetOpDef r_rZ_rZ + = { .args_ct_str = { "r", "rZ", "rZ" } }; + static const TCGTargetOpDef r_rZ_rZ_rZ_rZ + = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef r_L + = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef r_r_L + = { .args_ct_str = { "r", "r", "L" } }; + static const TCGTargetOpDef r_L_L + = { .args_ct_str = { "r", "L", "L" } }; + static const TCGTargetOpDef r_r_L_L + = { .args_ct_str = { "r", "r", "L", "L" } }; + static const TCGTargetOpDef LZ_L + = { .args_ct_str = { "LZ", "L" } }; + static const TCGTargetOpDef LZ_L_L + = { .args_ct_str = { "LZ", "L", "L" } }; + static const TCGTargetOpDef LZ_LZ_L + = { .args_ct_str = { "LZ", "LZ", "L" } }; + static const TCGTargetOpDef LZ_LZ_L_L + = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; + static const TCGTargetOpDef r_r_rZ_rZ_rM_rM + = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_not_i32: + case INDEX_op_neg_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i64: + case INDEX_op_neg_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + case INDEX_op_ext_i32_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_add_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + return &r_r_rI; + + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_rZ_rN; + + case INDEX_op_mul_i32: + case INDEX_op_mulsh_i32: + case INDEX_op_muluh_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + case INDEX_op_setcond_i32: + case INDEX_op_mul_i64: + case INDEX_op_mulsh_i64: + case INDEX_op_muluh_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + case INDEX_op_setcond_i64: + return &r_rZ_rZ; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &rZ_rZ; + + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + return &r_r_rZ_rZ_rM_rM; + + case INDEX_op_brcond2_i32: + return &rZ_rZ_rZ_rZ; + + case INDEX_op_setcond2_i32: + return &r_rZ_rZ_rZ_rZ; + + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + case INDEX_op_qemu_ld_i64: + return TCG_TARGET_REG_BITS == 64 ? &r_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L + : &r_r_L_L; + case INDEX_op_qemu_st_i64: + return TCG_TARGET_REG_BITS == 64 ? &LZ_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L + : &LZ_LZ_L_L; + + default: + return NULL; + } +} + +static const int tcg_target_callee_save_regs[] = { + TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + TCG_REG_RA, /* should be last for ABI compliance */ +}; + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); + + /* TB prologue */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + +#if !defined(CONFIG_SOFTMMU) + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); +#endif + + /* Call generated code */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); + + /* Return path for goto_ptr. Set return value to 0 */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); +} + +static void tcg_target_init(TCGContext *s) +{ + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + if (TCG_TARGET_REG_BITS == 64) { + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + } + + tcg_target_call_clobber_regs = -1u; + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_RISCV + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.return_column = TCG_REG_RA, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ + 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ + 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ + 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ + 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ + 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ + 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ + 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ + 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ + 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ + 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ + 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c deleted file mode 100644 index 3c11ab8b7a..0000000000 --- a/tcg/riscv/tcg-target.inc.c +++ /dev/null @@ -1,1915 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2018 SiFive, Inc - * Copyright (c) 2008-2009 Arnaud Patard - * Copyright (c) 2009 Aurelien Jarno - * Copyright (c) 2008 Fabrice Bellard - * - * Based on i386/tcg-target.c and mips/tcg-target.c - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "../tcg-pool.inc.c" - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "zero", - "ra", - "sp", - "gp", - "tp", - "t0", - "t1", - "t2", - "s0", - "s1", - "a0", - "a1", - "a2", - "a3", - "a4", - "a5", - "a6", - "a7", - "s2", - "s3", - "s4", - "s5", - "s6", - "s7", - "s8", - "s9", - "s10", - "s11", - "t3", - "t4", - "t5", - "t6" -}; -#endif - -static const int tcg_target_reg_alloc_order[] = { - /* Call saved registers */ - /* TCG_REG_S0 reservered for TCG_AREG0 */ - TCG_REG_S1, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - TCG_REG_S9, - TCG_REG_S10, - TCG_REG_S11, - - /* Call clobbered registers */ - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_T3, - TCG_REG_T4, - TCG_REG_T5, - TCG_REG_T6, - - /* Argument registers */ - TCG_REG_A0, - TCG_REG_A1, - TCG_REG_A2, - TCG_REG_A3, - TCG_REG_A4, - TCG_REG_A5, - TCG_REG_A6, - TCG_REG_A7, -}; - -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, - TCG_REG_A2, - TCG_REG_A3, - TCG_REG_A4, - TCG_REG_A5, - TCG_REG_A6, - TCG_REG_A7, -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, -}; - -#define TCG_CT_CONST_ZERO 0x100 -#define TCG_CT_CONST_S12 0x200 -#define TCG_CT_CONST_N12 0x400 -#define TCG_CT_CONST_M12 0x800 - -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) -{ - if (TCG_TARGET_REG_BITS == 32) { - return sextract32(val, pos, len); - } else { - return sextract64(val, pos, len); - } -} - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - break; - case 'L': - /* qemu_ld/qemu_st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_S12; - break; - case 'N': - ct->ct |= TCG_CT_CONST_N12; - break; - case 'M': - ct->ct |= TCG_CT_CONST_M12; - break; - case 'Z': - /* we can use a zero immediate as a zero register argument. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - if (ct & TCG_CT_CONST) { - return 1; - } - if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { - return 1; - } - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { - return 1; - } - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { - return 1; - } - return 0; -} - -/* - * RISC-V Base ISA opcodes (IM) - */ - -typedef enum { - OPC_ADD = 0x33, - OPC_ADDI = 0x13, - OPC_AND = 0x7033, - OPC_ANDI = 0x7013, - OPC_AUIPC = 0x17, - OPC_BEQ = 0x63, - OPC_BGE = 0x5063, - OPC_BGEU = 0x7063, - OPC_BLT = 0x4063, - OPC_BLTU = 0x6063, - OPC_BNE = 0x1063, - OPC_DIV = 0x2004033, - OPC_DIVU = 0x2005033, - OPC_JAL = 0x6f, - OPC_JALR = 0x67, - OPC_LB = 0x3, - OPC_LBU = 0x4003, - OPC_LD = 0x3003, - OPC_LH = 0x1003, - OPC_LHU = 0x5003, - OPC_LUI = 0x37, - OPC_LW = 0x2003, - OPC_LWU = 0x6003, - OPC_MUL = 0x2000033, - OPC_MULH = 0x2001033, - OPC_MULHSU = 0x2002033, - OPC_MULHU = 0x2003033, - OPC_OR = 0x6033, - OPC_ORI = 0x6013, - OPC_REM = 0x2006033, - OPC_REMU = 0x2007033, - OPC_SB = 0x23, - OPC_SD = 0x3023, - OPC_SH = 0x1023, - OPC_SLL = 0x1033, - OPC_SLLI = 0x1013, - OPC_SLT = 0x2033, - OPC_SLTI = 0x2013, - OPC_SLTIU = 0x3013, - OPC_SLTU = 0x3033, - OPC_SRA = 0x40005033, - OPC_SRAI = 0x40005013, - OPC_SRL = 0x5033, - OPC_SRLI = 0x5013, - OPC_SUB = 0x40000033, - OPC_SW = 0x2023, - OPC_XOR = 0x4033, - OPC_XORI = 0x4013, - -#if TCG_TARGET_REG_BITS == 64 - OPC_ADDIW = 0x1b, - OPC_ADDW = 0x3b, - OPC_DIVUW = 0x200503b, - OPC_DIVW = 0x200403b, - OPC_MULW = 0x200003b, - OPC_REMUW = 0x200703b, - OPC_REMW = 0x200603b, - OPC_SLLIW = 0x101b, - OPC_SLLW = 0x103b, - OPC_SRAIW = 0x4000501b, - OPC_SRAW = 0x4000503b, - OPC_SRLIW = 0x501b, - OPC_SRLW = 0x503b, - OPC_SUBW = 0x4000003b, -#else - /* Simplify code throughout by defining aliases for RV32. */ - OPC_ADDIW = OPC_ADDI, - OPC_ADDW = OPC_ADD, - OPC_DIVUW = OPC_DIVU, - OPC_DIVW = OPC_DIV, - OPC_MULW = OPC_MUL, - OPC_REMUW = OPC_REMU, - OPC_REMW = OPC_REM, - OPC_SLLIW = OPC_SLLI, - OPC_SLLW = OPC_SLL, - OPC_SRAIW = OPC_SRAI, - OPC_SRAW = OPC_SRA, - OPC_SRLIW = OPC_SRLI, - OPC_SRLW = OPC_SRL, - OPC_SUBW = OPC_SUB, -#endif - - OPC_FENCE = 0x0000000f, -} RISCVInsn; - -/* - * RISC-V immediate and instruction encoders (excludes 16-bit RVC) - */ - -/* Type-R */ - -static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) -{ - return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; -} - -/* Type-I */ - -static int32_t encode_imm12(uint32_t imm) -{ - return (imm & 0xfff) << 20; -} - -static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) -{ - return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); -} - -/* Type-S */ - -static int32_t encode_simm12(uint32_t imm) -{ - int32_t ret = 0; - - ret |= (imm & 0xFE0) << 20; - ret |= (imm & 0x1F) << 7; - - return ret; -} - -static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) -{ - return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); -} - -/* Type-SB */ - -static int32_t encode_sbimm12(uint32_t imm) -{ - int32_t ret = 0; - - ret |= (imm & 0x1000) << 19; - ret |= (imm & 0x7e0) << 20; - ret |= (imm & 0x1e) << 7; - ret |= (imm & 0x800) >> 4; - - return ret; -} - -static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) -{ - return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); -} - -/* Type-U */ - -static int32_t encode_uimm20(uint32_t imm) -{ - return imm & 0xfffff000; -} - -static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) -{ - return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); -} - -/* Type-UJ */ - -static int32_t encode_ujimm20(uint32_t imm) -{ - int32_t ret = 0; - - ret |= (imm & 0x0007fe) << (21 - 1); - ret |= (imm & 0x000800) << (20 - 11); - ret |= (imm & 0x0ff000) << (12 - 12); - ret |= (imm & 0x100000) << (31 - 20); - - return ret; -} - -static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) -{ - return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); -} - -/* - * RISC-V instruction emitters - */ - -static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, - TCGReg rd, TCGReg rs1, TCGReg rs2) -{ - tcg_out32(s, encode_r(opc, rd, rs1, rs2)); -} - -static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, - TCGReg rd, TCGReg rs1, TCGArg imm) -{ - tcg_out32(s, encode_i(opc, rd, rs1, imm)); -} - -static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, - TCGReg rs1, TCGReg rs2, uint32_t imm) -{ - tcg_out32(s, encode_s(opc, rs1, rs2, imm)); -} - -static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, - TCGReg rs1, TCGReg rs2, uint32_t imm) -{ - tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); -} - -static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, - TCGReg rd, uint32_t imm) -{ - tcg_out32(s, encode_u(opc, rd, imm)); -} - -static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, - TCGReg rd, uint32_t imm) -{ - tcg_out32(s, encode_uj(opc, rd, imm)); -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i = 0; i < count; ++i) { - p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); - } -} - -/* - * Relocations - */ - -static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - - if (offset == sextreg(offset, 1, 12) << 1) { - code_ptr[0] |= encode_sbimm12(offset); - return true; - } - - return false; -} - -static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - - if (offset == sextreg(offset, 1, 20) << 1) { - code_ptr[0] |= encode_ujimm20(offset); - return true; - } - - return false; -} - -static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) -{ - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - int32_t lo = sextreg(offset, 0, 12); - int32_t hi = offset - lo; - - if (offset == hi + lo) { - code_ptr[0] |= encode_uimm20(hi); - code_ptr[1] |= encode_imm12(lo); - return true; - } - - return false; -} - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - uint32_t insn = *code_ptr; - intptr_t diff; - bool short_jmp; - - tcg_debug_assert(addend == 0); - - switch (type) { - case R_RISCV_BRANCH: - diff = value - (uintptr_t)code_ptr; - short_jmp = diff == sextreg(diff, 0, 12); - if (short_jmp) { - return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); - } else { - /* Invert the condition */ - insn = insn ^ (1 << 12); - /* Clear the offset */ - insn &= 0x01fff07f; - /* Set the offset to the PC + 8 */ - insn |= encode_sbimm12(8); - - /* Move forward */ - code_ptr[0] = insn; - - /* Overwrite the NOP with jal x0,value */ - diff = value - (uintptr_t)(code_ptr + 1); - insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); - code_ptr[1] = insn; - - return true; - } - break; - case R_RISCV_JAL: - return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); - case R_RISCV_CALL: - return reloc_call(code_ptr, (tcg_insn_unit *)value); - default: - tcg_abort(); - } -} - -/* - * TCG intrinsics - */ - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ - if (ret == arg) { - return true; - } - switch (type) { - case TCG_TYPE_I32: - case TCG_TYPE_I64: - tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); - break; - default: - g_assert_not_reached(); - } - return true; -} - -static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - tcg_target_long val) -{ - tcg_target_long lo, hi, tmp; - int shift, ret; - - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - val = (int32_t)val; - } - - lo = sextreg(val, 0, 12); - if (val == lo) { - tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); - return; - } - - hi = val - lo; - if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { - tcg_out_opc_upper(s, OPC_LUI, rd, hi); - if (lo != 0) { - tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); - } - return; - } - - /* We can only be here if TCG_TARGET_REG_BITS != 32 */ - tmp = tcg_pcrel_diff(s, (void *)val); - if (tmp == (int32_t)tmp) { - tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); - tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); - ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); - tcg_debug_assert(ret == true); - return; - } - - /* Look for a single 20-bit section. */ - shift = ctz64(val); - tmp = val >> shift; - if (tmp == sextreg(tmp, 0, 20)) { - tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); - if (shift > 12) { - tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); - } else { - tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); - } - return; - } - - /* Look for a few high zero bits, with lots of bits set in the middle. */ - shift = clz64(val); - tmp = val << shift; - if (tmp == sextreg(tmp, 12, 20) << 12) { - tcg_out_opc_upper(s, OPC_LUI, rd, tmp); - tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); - return; - } else if (tmp == sextreg(tmp, 0, 12)) { - tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); - tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); - return; - } - - /* Drop into the constant pool. */ - new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); - tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); - tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); -} - -static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); -} - -static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); - tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); -} - -static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); - tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); -} - -static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); - tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); -} - -static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); - tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); -} - -static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); -} - -static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, - TCGReg addr, intptr_t offset) -{ - intptr_t imm12 = sextreg(offset, 0, 12); - - if (offset != imm12) { - intptr_t diff = offset - (uintptr_t)s->code_ptr; - - if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { - imm12 = sextreg(diff, 0, 12); - tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); - if (addr != TCG_REG_ZERO) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); - } - } - addr = TCG_REG_TMP2; - } - - switch (opc) { - case OPC_SB: - case OPC_SH: - case OPC_SW: - case OPC_SD: - tcg_out_opc_store(s, opc, addr, data, imm12); - break; - case OPC_LB: - case OPC_LBU: - case OPC_LH: - case OPC_LHU: - case OPC_LW: - case OPC_LWU: - case OPC_LD: - tcg_out_opc_imm(s, opc, data, addr, imm12); - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); - tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); - tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); -} - -static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - if (val == 0) { - tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); - return true; - } - return false; -} - -static void tcg_out_addsub2(TCGContext *s, - TCGReg rl, TCGReg rh, - TCGReg al, TCGReg ah, - TCGArg bl, TCGArg bh, - bool cbl, bool cbh, bool is_sub, bool is32bit) -{ - const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; - const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; - const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; - TCGReg th = TCG_REG_TMP1; - - /* If we have a negative constant such that negating it would - make the high part zero, we can (usually) eliminate one insn. */ - if (cbl && cbh && bh == -1 && bl != 0) { - bl = -bl; - bh = 0; - is_sub = !is_sub; - } - - /* By operating on the high part first, we get to use the final - carry operation to move back from the temporary. */ - if (!cbh) { - tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); - } else if (bh != 0 || ah == rl) { - tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); - } else { - th = ah; - } - - /* Note that tcg optimization should eliminate the bl == 0 case. */ - if (is_sub) { - if (cbl) { - tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); - tcg_out_opc_imm(s, opc_addi, rl, al, -bl); - } else { - tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); - tcg_out_opc_reg(s, opc_sub, rl, al, bl); - } - tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); - } else { - if (cbl) { - tcg_out_opc_imm(s, opc_addi, rl, al, bl); - tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); - } else if (rl == al && rl == bl) { - tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); - tcg_out_opc_reg(s, opc_addi, rl, al, bl); - } else { - tcg_out_opc_reg(s, opc_add, rl, al, bl); - tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, - rl, (rl == bl ? al : bl)); - } - tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); - } -} - -static const struct { - RISCVInsn op; - bool swap; -} tcg_brcond_to_riscv[] = { - [TCG_COND_EQ] = { OPC_BEQ, false }, - [TCG_COND_NE] = { OPC_BNE, false }, - [TCG_COND_LT] = { OPC_BLT, false }, - [TCG_COND_GE] = { OPC_BGE, false }, - [TCG_COND_LE] = { OPC_BGE, true }, - [TCG_COND_GT] = { OPC_BLT, true }, - [TCG_COND_LTU] = { OPC_BLTU, false }, - [TCG_COND_GEU] = { OPC_BGEU, false }, - [TCG_COND_LEU] = { OPC_BGEU, true }, - [TCG_COND_GTU] = { OPC_BLTU, true } -}; - -static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, - TCGReg arg2, TCGLabel *l) -{ - RISCVInsn op = tcg_brcond_to_riscv[cond].op; - - tcg_debug_assert(op != 0); - - if (tcg_brcond_to_riscv[cond].swap) { - TCGReg t = arg1; - arg1 = arg2; - arg2 = t; - } - - if (l->has_value) { - intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); - if (diff == sextreg(diff, 0, 12)) { - tcg_out_opc_branch(s, op, arg1, arg2, diff); - } else { - /* Invert the conditional branch. */ - tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); - } - } else { - tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); - tcg_out_opc_branch(s, op, arg1, arg2, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); - } -} - -static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg arg1, TCGReg arg2) -{ - switch (cond) { - case TCG_COND_EQ: - tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); - tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); - break; - case TCG_COND_NE: - tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); - tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); - break; - case TCG_COND_LT: - tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); - break; - case TCG_COND_GE: - tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - break; - case TCG_COND_LE: - tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - break; - case TCG_COND_GT: - tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); - break; - case TCG_COND_LTU: - tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); - break; - case TCG_COND_GEU: - tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - break; - case TCG_COND_LEU: - tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); - tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); - break; - case TCG_COND_GTU: - tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); - break; - default: - g_assert_not_reached(); - break; - } -} - -static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGReg bl, TCGReg bh, TCGLabel *l) -{ - /* todo */ - g_assert_not_reached(); -} - -static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - /* todo */ - g_assert_not_reached(); -} - -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); -} - -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) -{ - TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; - ptrdiff_t offset = tcg_pcrel_diff(s, arg); - int ret; - - if (offset == sextreg(offset, 1, 20) << 1) { - /* short jump: -2097150 to 2097152 */ - tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS == 32 || - offset == sextreg(offset, 1, 31) << 1) { - /* long jump: -2147483646 to 2147483648 */ - tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); - tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); - ret = reloc_call(s->code_ptr - 2, arg);\ - tcg_debug_assert(ret == true); - } else if (TCG_TARGET_REG_BITS == 64) { - /* far jump: 64-bit */ - tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); - tcg_target_long base = (tcg_target_long)arg - imm; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); - tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); - } else { - g_assert_not_reached(); - } -} - -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) -{ - tcg_out_call_int(s, arg, false); -} - -static void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - tcg_insn_unit insn = OPC_FENCE; - - if (a0 & TCG_MO_LD_LD) { - insn |= 0x02200000; - } - if (a0 & TCG_MO_ST_LD) { - insn |= 0x01200000; - } - if (a0 & TCG_MO_LD_ST) { - insn |= 0x02100000; - } - if (a0 & TCG_MO_ST_ST) { - insn |= 0x02200000; - } - tcg_out32(s, insn); -} - -/* - * Load/store and TLB - */ - -#if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.inc.c" - -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * TCGMemOpIdx oi, uintptr_t ra) - */ -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_SB] = helper_ret_ldsb_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LESW] = helper_le_ldsw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, -#if TCG_TARGET_REG_BITS == 64 - [MO_LESL] = helper_le_ldsl_mmu, -#endif - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BESW] = helper_be_ldsw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, -#if TCG_TARGET_REG_BITS == 64 - [MO_BESL] = helper_be_ldsl_mmu, -#endif - [MO_BEQ] = helper_be_ldq_mmu, -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, TCGMemOpIdx oi, - * uintptr_t ra) - */ -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; - -/* We don't support oversize guests */ -QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); - -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, TCGMemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc = get_memop(oi); - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index = get_mmuidx(oi); - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); - - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); - if (compare_mask == sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); - } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); - } - - /* Compare masked address with the TLB entry. */ - label_ptr[0] = s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); - - /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl = TCG_REG_TMP0; - } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->type = ext; - label->datalo_reg = datalo; - label->datahi_reg = datahi; - label->addrlo_reg = addrlo; - label->addrhi_reg = addrhi; - label->raddr = raddr; - label->label_ptr[0] = label_ptr[0]; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - TCGReg a0 = tcg_target_call_iarg_regs[0]; - TCGReg a1 = tcg_target_call_iarg_regs[1]; - TCGReg a2 = tcg_target_call_iarg_regs[2]; - TCGReg a3 = tcg_target_call_iarg_regs[3]; - - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - - /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { - return false; - } - - /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); - - tcg_out_goto(s, l->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - TCGMemOpIdx oi = l->oi; - MemOp opc = get_memop(oi); - MemOp s_bits = opc & MO_SIZE; - TCGReg a0 = tcg_target_call_iarg_regs[0]; - TCGReg a1 = tcg_target_call_iarg_regs[1]; - TCGReg a2 = tcg_target_call_iarg_regs[2]; - TCGReg a3 = tcg_target_call_iarg_regs[3]; - TCGReg a4 = tcg_target_call_iarg_regs[4]; - - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - - /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { - return false; - } - - /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); - switch (s_bits) { - case MO_8: - tcg_out_ext8u(s, a2, a2); - break; - case MO_16: - tcg_out_ext16u(s, a2, a2); - break; - default: - break; - } - tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - - tcg_out_goto(s, l->raddr); - return true; -} -#endif /* CONFIG_SOFTMMU */ - -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) -{ - const MemOp bswap = opc & MO_BSWAP; - - /* We don't yet handle byteswapping, assert */ - g_assert(!bswap); - - switch (opc & (MO_SSIZE)) { - case MO_UB: - tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); - break; - case MO_SB: - tcg_out_opc_imm(s, OPC_LB, lo, base, 0); - break; - case MO_UW: - tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); - break; - case MO_SW: - tcg_out_opc_imm(s, OPC_LH, lo, base, 0); - break; - case MO_UL: - if (TCG_TARGET_REG_BITS == 64 && is_64) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - break; - } - /* FALLTHRU */ - case MO_SL: - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - break; - case MO_Q: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (lo != base) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - } else { - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - } - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#endif - TCGReg base = TCG_REG_TMP0; - - data_regl = *args++; - data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addr_regl = *args++; - addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); -#else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } - - if (guest_base == 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); - } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); -#endif -} - -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc) -{ - const MemOp bswap = opc & MO_BSWAP; - - /* We don't yet handle byteswapping, assert */ - g_assert(!bswap); - - switch (opc & (MO_SSIZE)) { - case MO_8: - tcg_out_opc_store(s, OPC_SB, base, lo, 0); - break; - case MO_16: - tcg_out_opc_store(s, OPC_SH, base, lo, 0); - break; - case MO_32: - tcg_out_opc_store(s, OPC_SW, base, lo, 0); - break; - case MO_64: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_opc_store(s, OPC_SD, base, lo, 0); - } else { - tcg_out_opc_store(s, OPC_SW, base, lo, 0); - tcg_out_opc_store(s, OPC_SW, base, hi, 4); - } - break; - default: - g_assert_not_reached(); - } -} - -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - TCGMemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#endif - TCGReg base = TCG_REG_TMP0; - - data_regl = *args++; - data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); - addr_regl = *args++; - addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi = *args++; - opc = get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); -#else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } - - if (guest_base == 0) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); - } else { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); - } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); -#endif -} - -static tcg_insn_unit *tb_ret_addr; - -static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - TCGArg a0 = args[0]; - TCGArg a1 = args[1]; - TCGArg a2 = args[2]; - int c2 = const_args[2]; - - switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - if (a0 == 0) { - tcg_out_call_int(s, s->code_gen_epilogue, true); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); - tcg_out_call_int(s, tb_ret_addr, true); - } - break; - - case INDEX_op_goto_tb: - assert(s->tb_jmp_insn_offset == 0); - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); - set_jmp_reset_offset(s, a0); - break; - - case INDEX_op_goto_ptr: - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); - break; - - case INDEX_op_br: - tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); - break; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - tcg_out_ldst(s, OPC_LBU, a0, a1, a2); - break; - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - tcg_out_ldst(s, OPC_LB, a0, a1, a2); - break; - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - tcg_out_ldst(s, OPC_LHU, a0, a1, a2); - break; - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - tcg_out_ldst(s, OPC_LH, a0, a1, a2); - break; - case INDEX_op_ld32u_i64: - tcg_out_ldst(s, OPC_LWU, a0, a1, a2); - break; - case INDEX_op_ld_i32: - case INDEX_op_ld32s_i64: - tcg_out_ldst(s, OPC_LW, a0, a1, a2); - break; - case INDEX_op_ld_i64: - tcg_out_ldst(s, OPC_LD, a0, a1, a2); - break; - - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - tcg_out_ldst(s, OPC_SB, a0, a1, a2); - break; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - tcg_out_ldst(s, OPC_SH, a0, a1, a2); - break; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - tcg_out_ldst(s, OPC_SW, a0, a1, a2); - break; - case INDEX_op_st_i64: - tcg_out_ldst(s, OPC_SD, a0, a1, a2); - break; - - case INDEX_op_add_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); - } - break; - case INDEX_op_add_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); - } - break; - - case INDEX_op_sub_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); - } - break; - case INDEX_op_sub_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); - } - break; - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); - } - break; - - case INDEX_op_or_i32: - case INDEX_op_or_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); - } - break; - - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); - } - break; - - case INDEX_op_not_i32: - case INDEX_op_not_i64: - tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); - break; - - case INDEX_op_neg_i32: - tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); - break; - case INDEX_op_neg_i64: - tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); - break; - - case INDEX_op_mul_i32: - tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); - break; - case INDEX_op_mul_i64: - tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); - break; - - case INDEX_op_div_i32: - tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); - break; - case INDEX_op_div_i64: - tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); - break; - - case INDEX_op_divu_i32: - tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); - break; - case INDEX_op_divu_i64: - tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); - break; - - case INDEX_op_rem_i32: - tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); - break; - case INDEX_op_rem_i64: - tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); - break; - - case INDEX_op_remu_i32: - tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); - break; - case INDEX_op_remu_i64: - tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); - break; - - case INDEX_op_shl_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); - } - break; - case INDEX_op_shl_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); - } - break; - - case INDEX_op_shr_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); - } - break; - case INDEX_op_shr_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); - } - break; - - case INDEX_op_sar_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); - } - break; - case INDEX_op_sar_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2); - } else { - tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); - } - break; - - case INDEX_op_add2_i32: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], false, true); - break; - case INDEX_op_add2_i64: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], false, false); - break; - case INDEX_op_sub2_i32: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], true, true); - break; - case INDEX_op_sub2_i64: - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], - const_args[4], const_args[5], true, false); - break; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); - break; - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); - break; - - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - tcg_out_setcond(s, args[3], a0, a1, a2); - break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); - break; - - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext8u(s, a0, a1); - break; - - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - tcg_out_ext16u(s, a0, a1); - break; - - case INDEX_op_ext32u_i64: - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext8s(s, a0, a1); - break; - - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext16s(s, a0, a1); - break; - - case INDEX_op_ext32s_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_ext_i32_i64: - tcg_out_ext32s(s, a0, a1); - break; - - case INDEX_op_extrh_i64_i32: - tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); - break; - - case INDEX_op_mulsh_i32: - case INDEX_op_mulsh_i64: - tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); - break; - - case INDEX_op_muluh_i32: - case INDEX_op_muluh_i64: - tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - g_assert_not_reached(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r - = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r - = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef rZ_r - = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef rZ_rZ - = { .args_ct_str = { "rZ", "rZ" } }; - static const TCGTargetOpDef rZ_rZ_rZ_rZ - = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_r_ri - = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rI - = { .args_ct_str = { "r", "r", "rI" } }; - static const TCGTargetOpDef r_rZ_rN - = { .args_ct_str = { "r", "rZ", "rN" } }; - static const TCGTargetOpDef r_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ" } }; - static const TCGTargetOpDef r_rZ_rZ_rZ_rZ - = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; - static const TCGTargetOpDef r_L - = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef r_r_L - = { .args_ct_str = { "r", "r", "L" } }; - static const TCGTargetOpDef r_L_L - = { .args_ct_str = { "r", "L", "L" } }; - static const TCGTargetOpDef r_r_L_L - = { .args_ct_str = { "r", "r", "L", "L" } }; - static const TCGTargetOpDef LZ_L - = { .args_ct_str = { "LZ", "L" } }; - static const TCGTargetOpDef LZ_L_L - = { .args_ct_str = { "LZ", "L", "L" } }; - static const TCGTargetOpDef LZ_LZ_L - = { .args_ct_str = { "LZ", "LZ", "L" } }; - static const TCGTargetOpDef LZ_LZ_L_L - = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; - static const TCGTargetOpDef r_r_rZ_rZ_rM_rM - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_not_i32: - case INDEX_op_neg_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld_i64: - case INDEX_op_not_i64: - case INDEX_op_neg_i64: - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - case INDEX_op_ext_i32_i64: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return &rZ_r; - - case INDEX_op_add_i32: - case INDEX_op_and_i32: - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_add_i64: - case INDEX_op_and_i64: - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - return &r_r_rI; - - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - return &r_rZ_rN; - - case INDEX_op_mul_i32: - case INDEX_op_mulsh_i32: - case INDEX_op_muluh_i32: - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - case INDEX_op_rem_i32: - case INDEX_op_remu_i32: - case INDEX_op_setcond_i32: - case INDEX_op_mul_i64: - case INDEX_op_mulsh_i64: - case INDEX_op_muluh_i64: - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - case INDEX_op_setcond_i64: - return &r_rZ_rZ; - - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &rZ_rZ; - - case INDEX_op_add2_i32: - case INDEX_op_add2_i64: - case INDEX_op_sub2_i32: - case INDEX_op_sub2_i64: - return &r_r_rZ_rZ_rM_rM; - - case INDEX_op_brcond2_i32: - return &rZ_rZ_rZ_rZ; - - case INDEX_op_setcond2_i32: - return &r_rZ_rZ_rZ_rZ; - - case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; - case INDEX_op_qemu_ld_i64: - return TCG_TARGET_REG_BITS == 64 ? &r_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L - : &r_r_L_L; - case INDEX_op_qemu_st_i64: - return TCG_TARGET_REG_BITS == 64 ? &LZ_L - : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L - : &LZ_LZ_L_L; - - default: - return NULL; - } -} - -static const int tcg_target_callee_save_regs[] = { - TCG_REG_S0, /* used for the global env (TCG_AREG0) */ - TCG_REG_S1, - TCG_REG_S2, - TCG_REG_S3, - TCG_REG_S4, - TCG_REG_S5, - TCG_REG_S6, - TCG_REG_S7, - TCG_REG_S8, - TCG_REG_S9, - TCG_REG_S10, - TCG_REG_S11, - TCG_REG_RA, /* should be last for ABI compliance */ -}; - -/* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) -#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) -#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) -#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ - + TCG_TARGET_STACK_ALIGN - 1) \ - & -TCG_TARGET_STACK_ALIGN) -#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) - -/* We're expecting to be able to use an immediate for frame allocation. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); - -/* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int i; - - tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); - - /* TB prologue */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { - tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_SP, SAVE_OFS + i * REG_SIZE); - } - -#if !defined(CONFIG_SOFTMMU) - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); -#endif - - /* Call generated code */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); - - /* Return path for goto_ptr. Set return value to 0 */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); - - /* TB epilogue */ - tb_ret_addr = s->code_ptr; - for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { - tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], - TCG_REG_SP, SAVE_OFS + i * REG_SIZE); - } - - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); - tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); -} - -static void tcg_target_init(TCGContext *s) -{ - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - if (TCG_TARGET_REG_BITS == 64) { - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; - } - - tcg_target_call_clobber_regs = -1u; - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; -} DebugFrame; - -#define ELF_HOST_MACHINE EM_RISCV - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ - .h.cie.return_column = TCG_REG_RA, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ - 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ - 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ - 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ - 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ - 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ - 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ - 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ - 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ - 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ - 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ - 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc new file mode 100644 index 0000000000..985115acfb --- /dev/null +++ b/tcg/s390/tcg-target.c.inc @@ -0,0 +1,2630 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2009 Ulrich Hecht + * Copyright (c) 2009 Alexander Graf + * Copyright (c) 2010 Richard Henderson + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* We only support generating code for 64-bit mode. */ +#if TCG_TARGET_REG_BITS != 64 +#error "unsupported code generation mode" +#endif + +#include "../tcg-pool.c.inc" +#include "elf.h" + +/* ??? The translation blocks produced by TCG are generally small enough to + be entirely reachable with a 16-bit displacement. Leaving the option for + a 32-bit displacement here Just In Case. */ +#define USE_LONG_BRANCHES 0 + +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_S33 0x400 +#define TCG_CT_CONST_ZERO 0x800 + +/* Several places within the instruction set 0 means "no register" + rather than TCG_REG_R0. */ +#define TCG_REG_NONE 0 + +/* A scratch register that may be be used throughout the backend. */ +#define TCG_TMP0 TCG_REG_R1 + +/* A scratch register that holds a pointer to the beginning of the TB. + We don't need this when we have pc-relative loads with the general + instructions extension facility. */ +#define TCG_REG_TB TCG_REG_R12 +#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) + +#ifndef CONFIG_SOFTMMU +#define TCG_GUEST_BASE_REG TCG_REG_R13 +#endif + +/* All of the following instructions are prefixed with their instruction + format, and are defined as 8- or 16-bit quantities, even when the two + halves of the 16-bit quantity may appear 32 bits apart in the insn. + This makes it easy to copy the values from the tables in Appendix B. */ +typedef enum S390Opcode { + RIL_AFI = 0xc209, + RIL_AGFI = 0xc208, + RIL_ALFI = 0xc20b, + RIL_ALGFI = 0xc20a, + RIL_BRASL = 0xc005, + RIL_BRCL = 0xc004, + RIL_CFI = 0xc20d, + RIL_CGFI = 0xc20c, + RIL_CLFI = 0xc20f, + RIL_CLGFI = 0xc20e, + RIL_CLRL = 0xc60f, + RIL_CLGRL = 0xc60a, + RIL_CRL = 0xc60d, + RIL_CGRL = 0xc608, + RIL_IIHF = 0xc008, + RIL_IILF = 0xc009, + RIL_LARL = 0xc000, + RIL_LGFI = 0xc001, + RIL_LGRL = 0xc408, + RIL_LLIHF = 0xc00e, + RIL_LLILF = 0xc00f, + RIL_LRL = 0xc40d, + RIL_MSFI = 0xc201, + RIL_MSGFI = 0xc200, + RIL_NIHF = 0xc00a, + RIL_NILF = 0xc00b, + RIL_OIHF = 0xc00c, + RIL_OILF = 0xc00d, + RIL_SLFI = 0xc205, + RIL_SLGFI = 0xc204, + RIL_XIHF = 0xc006, + RIL_XILF = 0xc007, + + RI_AGHI = 0xa70b, + RI_AHI = 0xa70a, + RI_BRC = 0xa704, + RI_CHI = 0xa70e, + RI_CGHI = 0xa70f, + RI_IIHH = 0xa500, + RI_IIHL = 0xa501, + RI_IILH = 0xa502, + RI_IILL = 0xa503, + RI_LGHI = 0xa709, + RI_LLIHH = 0xa50c, + RI_LLIHL = 0xa50d, + RI_LLILH = 0xa50e, + RI_LLILL = 0xa50f, + RI_MGHI = 0xa70d, + RI_MHI = 0xa70c, + RI_NIHH = 0xa504, + RI_NIHL = 0xa505, + RI_NILH = 0xa506, + RI_NILL = 0xa507, + RI_OIHH = 0xa508, + RI_OIHL = 0xa509, + RI_OILH = 0xa50a, + RI_OILL = 0xa50b, + + RIE_CGIJ = 0xec7c, + RIE_CGRJ = 0xec64, + RIE_CIJ = 0xec7e, + RIE_CLGRJ = 0xec65, + RIE_CLIJ = 0xec7f, + RIE_CLGIJ = 0xec7d, + RIE_CLRJ = 0xec77, + RIE_CRJ = 0xec76, + RIE_LOCGHI = 0xec46, + RIE_RISBG = 0xec55, + + RRE_AGR = 0xb908, + RRE_ALGR = 0xb90a, + RRE_ALCR = 0xb998, + RRE_ALCGR = 0xb988, + RRE_CGR = 0xb920, + RRE_CLGR = 0xb921, + RRE_DLGR = 0xb987, + RRE_DLR = 0xb997, + RRE_DSGFR = 0xb91d, + RRE_DSGR = 0xb90d, + RRE_FLOGR = 0xb983, + RRE_LGBR = 0xb906, + RRE_LCGR = 0xb903, + RRE_LGFR = 0xb914, + RRE_LGHR = 0xb907, + RRE_LGR = 0xb904, + RRE_LLGCR = 0xb984, + RRE_LLGFR = 0xb916, + RRE_LLGHR = 0xb985, + RRE_LRVR = 0xb91f, + RRE_LRVGR = 0xb90f, + RRE_LTGR = 0xb902, + RRE_MLGR = 0xb986, + RRE_MSGR = 0xb90c, + RRE_MSR = 0xb252, + RRE_NGR = 0xb980, + RRE_OGR = 0xb981, + RRE_SGR = 0xb909, + RRE_SLGR = 0xb90b, + RRE_SLBR = 0xb999, + RRE_SLBGR = 0xb989, + RRE_XGR = 0xb982, + + RRF_LOCR = 0xb9f2, + RRF_LOCGR = 0xb9e2, + RRF_NRK = 0xb9f4, + RRF_NGRK = 0xb9e4, + RRF_ORK = 0xb9f6, + RRF_OGRK = 0xb9e6, + RRF_SRK = 0xb9f9, + RRF_SGRK = 0xb9e9, + RRF_SLRK = 0xb9fb, + RRF_SLGRK = 0xb9eb, + RRF_XRK = 0xb9f7, + RRF_XGRK = 0xb9e7, + + RR_AR = 0x1a, + RR_ALR = 0x1e, + RR_BASR = 0x0d, + RR_BCR = 0x07, + RR_CLR = 0x15, + RR_CR = 0x19, + RR_DR = 0x1d, + RR_LCR = 0x13, + RR_LR = 0x18, + RR_LTR = 0x12, + RR_NR = 0x14, + RR_OR = 0x16, + RR_SR = 0x1b, + RR_SLR = 0x1f, + RR_XR = 0x17, + + RSY_RLL = 0xeb1d, + RSY_RLLG = 0xeb1c, + RSY_SLLG = 0xeb0d, + RSY_SLLK = 0xebdf, + RSY_SRAG = 0xeb0a, + RSY_SRAK = 0xebdc, + RSY_SRLG = 0xeb0c, + RSY_SRLK = 0xebde, + + RS_SLL = 0x89, + RS_SRA = 0x8a, + RS_SRL = 0x88, + + RXY_AG = 0xe308, + RXY_AY = 0xe35a, + RXY_CG = 0xe320, + RXY_CLG = 0xe321, + RXY_CLY = 0xe355, + RXY_CY = 0xe359, + RXY_LAY = 0xe371, + RXY_LB = 0xe376, + RXY_LG = 0xe304, + RXY_LGB = 0xe377, + RXY_LGF = 0xe314, + RXY_LGH = 0xe315, + RXY_LHY = 0xe378, + RXY_LLGC = 0xe390, + RXY_LLGF = 0xe316, + RXY_LLGH = 0xe391, + RXY_LMG = 0xeb04, + RXY_LRV = 0xe31e, + RXY_LRVG = 0xe30f, + RXY_LRVH = 0xe31f, + RXY_LY = 0xe358, + RXY_NG = 0xe380, + RXY_OG = 0xe381, + RXY_STCY = 0xe372, + RXY_STG = 0xe324, + RXY_STHY = 0xe370, + RXY_STMG = 0xeb24, + RXY_STRV = 0xe33e, + RXY_STRVG = 0xe32f, + RXY_STRVH = 0xe33f, + RXY_STY = 0xe350, + RXY_XG = 0xe382, + + RX_A = 0x5a, + RX_C = 0x59, + RX_L = 0x58, + RX_LA = 0x41, + RX_LH = 0x48, + RX_ST = 0x50, + RX_STC = 0x42, + RX_STH = 0x40, + + NOP = 0x0707, +} S390Opcode; + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15" +}; +#endif + +/* Since R6 is a potential argument register, choose it last of the + call-saved registers. Likewise prefer the call-clobbered registers + in reverse order to maximize the chance of avoiding the arguments. */ +static const int tcg_target_reg_alloc_order[] = { + /* Call saved registers. */ + TCG_REG_R13, + TCG_REG_R12, + TCG_REG_R11, + TCG_REG_R10, + TCG_REG_R9, + TCG_REG_R8, + TCG_REG_R7, + TCG_REG_R6, + /* Call clobbered registers. */ + TCG_REG_R14, + TCG_REG_R0, + TCG_REG_R1, + /* Argument registers, in reverse order of allocation. */ + TCG_REG_R5, + TCG_REG_R4, + TCG_REG_R3, + TCG_REG_R2, +}; + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R4, + TCG_REG_R5, + TCG_REG_R6, +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_R2, +}; + +#define S390_CC_EQ 8 +#define S390_CC_LT 4 +#define S390_CC_GT 2 +#define S390_CC_OV 1 +#define S390_CC_NE (S390_CC_LT | S390_CC_GT) +#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) +#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) +#define S390_CC_NEVER 0 +#define S390_CC_ALWAYS 15 + +/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ +static const uint8_t tcg_cond_to_s390_cond[] = { + [TCG_COND_EQ] = S390_CC_EQ, + [TCG_COND_NE] = S390_CC_NE, + [TCG_COND_LT] = S390_CC_LT, + [TCG_COND_LE] = S390_CC_LE, + [TCG_COND_GT] = S390_CC_GT, + [TCG_COND_GE] = S390_CC_GE, + [TCG_COND_LTU] = S390_CC_LT, + [TCG_COND_LEU] = S390_CC_LE, + [TCG_COND_GTU] = S390_CC_GT, + [TCG_COND_GEU] = S390_CC_GE, +}; + +/* Condition codes that result from a LOAD AND TEST. Here, we have no + unsigned instruction variation, however since the test is vs zero we + can re-map the outcomes appropriately. */ +static const uint8_t tcg_cond_to_ltr_cond[] = { + [TCG_COND_EQ] = S390_CC_EQ, + [TCG_COND_NE] = S390_CC_NE, + [TCG_COND_LT] = S390_CC_LT, + [TCG_COND_LE] = S390_CC_LE, + [TCG_COND_GT] = S390_CC_GT, + [TCG_COND_GE] = S390_CC_GE, + [TCG_COND_LTU] = S390_CC_NEVER, + [TCG_COND_LEU] = S390_CC_EQ, + [TCG_COND_GTU] = S390_CC_NE, + [TCG_COND_GEU] = S390_CC_ALWAYS, +}; + +#ifdef CONFIG_SOFTMMU +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LESL] = helper_le_ldsl_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BESL] = helper_be_ldsl_mmu, + [MO_BEQ] = helper_be_ldq_mmu, +}; + +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; +#endif + +static tcg_insn_unit *tb_ret_addr; +uint64_t s390_facilities; + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + intptr_t pcrel2; + uint32_t old; + + value += addend; + pcrel2 = (tcg_insn_unit *)value - code_ptr; + + switch (type) { + case R_390_PC16DBL: + if (pcrel2 == (int16_t)pcrel2) { + tcg_patch16(code_ptr, pcrel2); + return true; + } + break; + case R_390_PC32DBL: + if (pcrel2 == (int32_t)pcrel2) { + tcg_patch32(code_ptr, pcrel2); + return true; + } + break; + case R_390_20: + if (value == sextract64(value, 0, 20)) { + old = *(uint32_t *)code_ptr & 0xf00000ff; + old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); + tcg_patch32(code_ptr, old); + return true; + } + break; + default: + g_assert_not_reached(); + } + return false; +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': /* all registers */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffff; + break; + case 'L': /* qemu_ld/st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); + break; + case 'a': /* force R2 for division */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); + break; + case 'b': /* force R3 for division */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0; + tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); + break; + case 'A': + ct->ct |= TCG_CT_CONST_S33; + break; + case 'I': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_S32; + break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* Test if a constant matches the constraint. */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + + if (ct & TCG_CT_CONST) { + return 1; + } + + if (type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + /* The following are mutually exclusive. */ + if (ct & TCG_CT_CONST_S16) { + return val == (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val == (int32_t)val; + } else if (ct & TCG_CT_CONST_S33) { + return val >= -0xffffffffll && val <= 0xffffffffll; + } else if (ct & TCG_CT_CONST_ZERO) { + return val == 0; + } + + return 0; +} + +/* Emit instructions according to the given instruction format. */ + +static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) +{ + tcg_out16(s, (op << 8) | (r1 << 4) | r2); +} + +static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2) +{ + tcg_out32(s, (op << 16) | (r1 << 4) | r2); +} + +static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2, int m3) +{ + tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); +} + +static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) +{ + tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); +} + +static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, + int i2, int m3) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); + tcg_out32(s, (i2 << 16) | (op & 0xff)); +} + +static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) +{ + tcg_out16(s, op | (r1 << 4)); + tcg_out32(s, i2); +} + +static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, + TCGReg b2, TCGReg r3, int disp) +{ + tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) + | (disp & 0xfff)); +} + +static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, + TCGReg b2, TCGReg r3, int disp) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); + tcg_out32(s, (op & 0xff) | (b2 << 28) + | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); +} + +#define tcg_out_insn_RX tcg_out_insn_RS +#define tcg_out_insn_RXY tcg_out_insn_RSY + +/* Emit an opcode with "type-checking" of the format. */ +#define tcg_out_insn(S, FMT, OP, ...) \ + glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) + + +/* emit 64-bit shifts */ +static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, + TCGReg src, TCGReg sh_reg, int sh_imm) +{ + tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); +} + +/* emit 32-bit shifts */ +static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, + TCGReg sh_reg, int sh_imm) +{ + tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); +} + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) +{ + if (src != dst) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, LR, dst, src); + } else { + tcg_out_insn(s, RRE, LGR, dst, src); + } + } + return true; +} + +static const S390Opcode lli_insns[4] = { + RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH +}; + +static bool maybe_out_small_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_target_ulong uval = sval; + int i; + + if (type == TCG_TYPE_I32) { + uval = (uint32_t)sval; + sval = (int32_t)sval; + } + + /* Try all 32-bit insns that can load it in one go. */ + if (sval >= -0x8000 && sval < 0x8000) { + tcg_out_insn(s, RI, LGHI, ret, sval); + return true; + } + + for (i = 0; i < 4; i++) { + tcg_target_long mask = 0xffffull << i*16; + if ((uval & mask) == uval) { + tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); + return true; + } + } + + return false; +} + +/* load a register with an immediate value */ +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) +{ + tcg_target_ulong uval; + + /* Try all 32-bit insns that can load it in one go. */ + if (maybe_out_small_movi(s, type, ret, sval)) { + return; + } + + uval = sval; + if (type == TCG_TYPE_I32) { + uval = (uint32_t)sval; + sval = (int32_t)sval; + } + + /* Try all 48-bit insns that can load it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + if (sval == (int32_t)sval) { + tcg_out_insn(s, RIL, LGFI, ret, sval); + return; + } + if (uval <= 0xffffffff) { + tcg_out_insn(s, RIL, LLILF, ret, uval); + return; + } + if ((uval & 0xffffffff) == 0) { + tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); + return; + } + } + + /* Try for PC-relative address load. For odd addresses, + attempt to use an offset from the start of the TB. */ + if ((sval & 1) == 0) { + ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1; + if (off == (int32_t)off) { + tcg_out_insn(s, RIL, LARL, ret, off); + return; + } + } else if (USE_REG_TB && !in_prologue) { + ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; + if (off == sextract64(off, 0, 20)) { + /* This is certain to be an address within TB, and therefore + OFF will be negative; don't try RX_LA. */ + tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); + return; + } + } + + /* A 32-bit unsigned value can be loaded in 2 insns. And given + that LLILL, LLIHL, LLILF above did not succeed, we know that + both insns are required. */ + if (uval <= 0xffffffff) { + tcg_out_insn(s, RI, LLILL, ret, uval); + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } + + /* Otherwise, stuff it in the constant pool. */ + if (s390_facilities & FACILITY_GEN_INST_EXT) { + tcg_out_insn(s, RIL, LGRL, ret, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); + } else if (USE_REG_TB && !in_prologue) { + tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, sval, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + TCGReg base = ret ? ret : TCG_TMP0; + tcg_out_insn(s, RIL, LARL, base, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0); + } +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_out_movi_int(s, type, ret, sval, false); +} + +/* Emit a load/store type instruction. Inputs are: + DATA: The register to be loaded or stored. + BASE+OFS: The effective address. + OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. + OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ + +static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, + TCGReg data, TCGReg base, TCGReg index, + tcg_target_long ofs) +{ + if (ofs < -0x80000 || ofs >= 0x80000) { + /* Combine the low 20 bits of the offset with the actual load insn; + the high 44 bits must come from an immediate load. */ + tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); + ofs = low; + + /* If we were already given an index register, add it in. */ + if (index != TCG_REG_NONE) { + tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); + } + index = TCG_TMP0; + } + + if (opc_rx && ofs >= 0 && ofs < 0x1000) { + tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); + } else { + tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); + } +} + + +/* load data without address translation or endianness conversion */ +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) +{ + if (type == TCG_TYPE_I32) { + tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); + } else { + tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + } +} + +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) +{ + if (type == TCG_TYPE_I32) { + tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); + } else { + tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + } +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + return false; +} + +/* load data from an absolute host address */ +static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) +{ + intptr_t addr = (intptr_t)abs; + + if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) { + ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1; + if (disp == (int32_t)disp) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RIL, LRL, dest, disp); + } else { + tcg_out_insn(s, RIL, LGRL, dest, disp); + } + return; + } + } + if (USE_REG_TB) { + ptrdiff_t disp = abs - (void *)s->code_gen_ptr; + if (disp == sextract64(disp, 0, 20)) { + tcg_out_ld(s, type, dest, TCG_REG_TB, disp); + return; + } + } + + tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); + tcg_out_ld(s, type, dest, dest, addr & 0xffff); +} + +static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, + int msb, int lsb, int ofs, int z) +{ + /* Format RIE-f */ + tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src); + tcg_out16(s, (msb << 8) | (z << 7) | lsb); + tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff)); +} + +static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) +{ + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RRE, LGBR, dest, src); + return; + } + + if (type == TCG_TYPE_I32) { + if (dest == src) { + tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24); + } else { + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24); + } + tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24); + } else { + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56); + tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56); + } +} + +static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) +{ + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RRE, LLGCR, dest, src); + return; + } + + if (dest == src) { + tcg_out_movi(s, type, TCG_TMP0, 0xff); + src = TCG_TMP0; + } else { + tcg_out_movi(s, type, dest, 0xff); + } + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, NR, dest, src); + } else { + tcg_out_insn(s, RRE, NGR, dest, src); + } +} + +static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) +{ + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RRE, LGHR, dest, src); + return; + } + + if (type == TCG_TYPE_I32) { + if (dest == src) { + tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16); + } else { + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16); + } + tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16); + } else { + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48); + tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48); + } +} + +static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) +{ + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RRE, LLGHR, dest, src); + return; + } + + if (dest == src) { + tcg_out_movi(s, type, TCG_TMP0, 0xffff); + src = TCG_TMP0; + } else { + tcg_out_movi(s, type, dest, 0xffff); + } + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, NR, dest, src); + } else { + tcg_out_insn(s, RRE, NGR, dest, src); + } +} + +static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_insn(s, RRE, LGFR, dest, src); +} + +static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_insn(s, RRE, LLGFR, dest, src); +} + +/* Accept bit patterns like these: + 0....01....1 + 1....10....0 + 1..10..01..1 + 0..01..10..0 + Copied from gcc sources. */ +static inline bool risbg_mask(uint64_t c) +{ + uint64_t lsb; + /* We don't change the number of transitions by inverting, + so make sure we start with the LSB zero. */ + if (c & 1) { + c = ~c; + } + /* Reject all zeros or all ones. */ + if (c == 0) { + return false; + } + /* Find the first transition. */ + lsb = c & -c; + /* Invert to look for a second transition. */ + c = ~c; + /* Erase the first transition. */ + c &= -lsb; + /* Find the second transition, if any. */ + lsb = c & -c; + /* Match if all the bits are 1's, or if c is zero. */ + return c == -lsb; +} + +static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) +{ + int msb, lsb; + if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { + /* Achieve wraparound by swapping msb and lsb. */ + msb = 64 - ctz64(~val); + lsb = clz64(~val) - 1; + } else { + msb = clz64(val); + lsb = 63 - ctz64(val); + } + tcg_out_risbg(s, out, in, msb, lsb, 0, 1); +} + +static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) +{ + static const S390Opcode ni_insns[4] = { + RI_NILL, RI_NILH, RI_NIHL, RI_NIHH + }; + static const S390Opcode nif_insns[2] = { + RIL_NILF, RIL_NIHF + }; + uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); + int i; + + /* Look for the zero-extensions. */ + if ((val & valid) == 0xffffffff) { + tgen_ext32u(s, dest, dest); + return; + } + if (s390_facilities & FACILITY_EXT_IMM) { + if ((val & valid) == 0xff) { + tgen_ext8u(s, TCG_TYPE_I64, dest, dest); + return; + } + if ((val & valid) == 0xffff) { + tgen_ext16u(s, TCG_TYPE_I64, dest, dest); + return; + } + } + + /* Try all 32-bit insns that can perform it in one go. */ + for (i = 0; i < 4; i++) { + tcg_target_ulong mask = ~(0xffffull << i*16); + if (((val | ~valid) & mask) == mask) { + tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16); + return; + } + } + + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + for (i = 0; i < 2; i++) { + tcg_target_ulong mask = ~(0xffffffffull << i*32); + if (((val | ~valid) & mask) == mask) { + tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); + return; + } + } + } + if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) { + tgen_andi_risbg(s, dest, dest, val); + return; + } + + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (USE_REG_TB) { + if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { + tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + return; + } + } else { + tcg_out_movi(s, type, TCG_TMP0, val); + } + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, NR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0); + } +} + +static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) +{ + static const S390Opcode oi_insns[4] = { + RI_OILL, RI_OILH, RI_OIHL, RI_OIHH + }; + static const S390Opcode oif_insns[2] = { + RIL_OILF, RIL_OIHF + }; + + int i; + + /* Look for no-op. */ + if (unlikely(val == 0)) { + return; + } + + /* Try all 32-bit insns that can perform it in one go. */ + for (i = 0; i < 4; i++) { + tcg_target_ulong mask = (0xffffull << i*16); + if ((val & mask) != 0 && (val & ~mask) == 0) { + tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); + return; + } + } + + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + for (i = 0; i < 2; i++) { + tcg_target_ulong mask = (0xffffffffull << i*32); + if ((val & mask) != 0 && (val & ~mask) == 0) { + tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); + return; + } + } + } + + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, OR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + /* Perform the OR via sequential modifications to the high and + low parts. Do this via recursion to handle 16-bit vs 32-bit + masks in each half. */ + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tgen_ori(s, type, dest, val & 0x00000000ffffffffull); + tgen_ori(s, type, dest, val & 0xffffffff00000000ull); + } +} + +static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) +{ + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + if ((val & 0xffffffff00000000ull) == 0) { + tcg_out_insn(s, RIL, XILF, dest, val); + return; + } + if ((val & 0x00000000ffffffffull) == 0) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + return; + } + } + + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, XR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + /* Perform the xor by parts. */ + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + if (val & 0xffffffff) { + tcg_out_insn(s, RIL, XILF, dest, val); + } + if (val > 0xffffffff) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + } + } +} + +static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, + TCGArg c2, bool c2const, bool need_carry) +{ + bool is_unsigned = is_unsigned_cond(c); + S390Opcode op; + + if (c2const) { + if (c2 == 0) { + if (!(is_unsigned && need_carry)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, LTR, r1, r1); + } else { + tcg_out_insn(s, RRE, LTGR, r1, r1); + } + return tcg_cond_to_ltr_cond[c]; + } + } + + if (!is_unsigned && c2 == (int16_t)c2) { + op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); + tcg_out_insn_RI(s, op, r1, c2); + goto exit; + } + + if (s390_facilities & FACILITY_EXT_IMM) { + if (type == TCG_TYPE_I32) { + op = (is_unsigned ? RIL_CLFI : RIL_CFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; + } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) { + op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; + } + } + + /* Use the constant pool, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { + c2 = TCG_TMP0; + /* fall through to reg-reg */ + } else if (USE_REG_TB) { + if (type == TCG_TYPE_I32) { + op = (is_unsigned ? RXY_CLY : RXY_CY); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, + 4 - (intptr_t)s->code_gen_ptr); + } else { + op = (is_unsigned ? RXY_CLG : RXY_CG); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, c2, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } + goto exit; + } else { + if (type == TCG_TYPE_I32) { + op = (is_unsigned ? RIL_CLRL : RIL_CRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, (uint32_t)c2, R_390_PC32DBL, + s->code_ptr - 2, 2 + 4); + } else { + op = (is_unsigned ? RIL_CLGRL : RIL_CGRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2); + } + goto exit; + } + } + + if (type == TCG_TYPE_I32) { + op = (is_unsigned ? RR_CLR : RR_CR); + tcg_out_insn_RR(s, op, r1, c2); + } else { + op = (is_unsigned ? RRE_CLGR : RRE_CGR); + tcg_out_insn_RRE(s, op, r1, c2); + } + + exit: + return tcg_cond_to_s390_cond[c]; +} + +static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, + TCGReg dest, TCGReg c1, TCGArg c2, int c2const) +{ + int cc; + bool have_loc; + + /* With LOC2, we can always emit the minimum 3 insns. */ + if (s390_facilities & FACILITY_LOAD_ON_COND2) { + /* Emit: d = 0, d = (cc ? 1 : d). */ + cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + return; + } + + have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; + + /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ + restart: + switch (cond) { + case TCG_COND_NE: + /* X != 0 is X > 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_GTU; + } else { + break; + } + /* fallthru */ + + case TCG_COND_GTU: + case TCG_COND_GT: + /* The result of a compare has CC=2 for GT and CC=3 unused. + ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_movi(s, type, dest, 0); + tcg_out_insn(s, RRE, ALCGR, dest, dest); + return; + + case TCG_COND_EQ: + /* X == 0 is X <= 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_LEU; + } else { + break; + } + /* fallthru */ + + case TCG_COND_LEU: + case TCG_COND_LE: + /* As above, but we're looking for borrow, or !carry. + The second insn computes d - d - borrow, or -1 for true + and 0 for false. So we must mask to 1 bit afterward. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_insn(s, RRE, SLBGR, dest, dest); + tgen_andi(s, type, dest, 1); + return; + + case TCG_COND_GEU: + case TCG_COND_LTU: + case TCG_COND_LT: + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ + if (c2const) { + if (have_loc) { + break; + } + tcg_out_movi(s, type, TCG_TMP0, c2); + c2 = c1; + c2const = 0; + c1 = TCG_TMP0; + } else { + TCGReg t = c1; + c1 = c2; + c2 = t; + } + cond = tcg_swap_cond(cond); + goto restart; + + default: + g_assert_not_reached(); + } + + cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); + if (have_loc) { + /* Emit: d = 0, t = 1, d = (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + } else { + /* Emit: d = 1; if (cc) goto over; d = 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + } +} + +static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, + TCGReg c1, TCGArg c2, int c2const, + TCGArg v3, int v3const) +{ + int cc; + if (s390_facilities & FACILITY_LOAD_ON_COND) { + cc = tgen_cmp(s, type, c, c1, c2, c2const, false); + if (v3const) { + tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + } else { + tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + } + } else { + c = tcg_invert_cond(c); + cc = tgen_cmp(s, type, c, c1, c2, c2const, false); + + /* Emit: if (cc) goto over; dest = r3; over: */ + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_insn(s, RRE, LGR, dest, v3); + } +} + +static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, + TCGArg a2, int a2const) +{ + /* Since this sets both R and R+1, we have no choice but to store the + result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ + QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); + tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); + + if (a2const && a2 == 64) { + tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); + } else { + if (a2const) { + tcg_out_movi(s, TCG_TYPE_I64, dest, a2); + } else { + tcg_out_mov(s, TCG_TYPE_I64, dest, a2); + } + if (s390_facilities & FACILITY_LOAD_ON_COND) { + /* Emit: if (one bit found) dest = r0. */ + tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); + } else { + /* Emit: if (no one bit found) goto over; dest = r0; over: */ + tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1); + tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0); + } + } +} + +static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, + int ofs, int len, int z) +{ + int lsb = (63 - ofs); + int msb = lsb - (len - 1); + tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); +} + +static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, + int ofs, int len) +{ + tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); +} + +static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest) +{ + ptrdiff_t off = dest - s->code_ptr; + if (off == (int16_t)off) { + tcg_out_insn(s, RI, BRC, cc, off); + } else if (off == (int32_t)off) { + tcg_out_insn(s, RIL, BRCL, cc, off); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); + tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); + } +} + +static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) +{ + if (l->has_value) { + tgen_gotoi(s, cc, l->u.value_ptr); + } else if (USE_LONG_BRANCHES) { + tcg_out16(s, RIL_BRCL | (cc << 4)); + tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2); + s->code_ptr += 2; + } else { + tcg_out16(s, RI_BRC | (cc << 4)); + tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); + s->code_ptr += 1; + } +} + +static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, + TCGReg r1, TCGReg r2, TCGLabel *l) +{ + intptr_t off = 0; + + if (l->has_value) { + off = l->u.value_ptr - s->code_ptr; + tcg_debug_assert(off == (int16_t)off); + } else { + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); + } + + tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); + tcg_out16(s, off); + tcg_out16(s, cc << 12 | (opc & 0xff)); +} + +static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, + TCGReg r1, int i2, TCGLabel *l) +{ + tcg_target_long off = 0; + + if (l->has_value) { + off = l->u.value_ptr - s->code_ptr; + tcg_debug_assert(off == (int16_t)off); + } else { + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); + } + + tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); + tcg_out16(s, off); + tcg_out16(s, (i2 << 8) | (opc & 0xff)); +} + +static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, + TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) +{ + int cc; + + if (s390_facilities & FACILITY_GEN_INST_EXT) { + bool is_unsigned = is_unsigned_cond(c); + bool in_range; + S390Opcode opc; + + cc = tcg_cond_to_s390_cond[c]; + + if (!c2const) { + opc = (type == TCG_TYPE_I32 + ? (is_unsigned ? RIE_CLRJ : RIE_CRJ) + : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ)); + tgen_compare_branch(s, opc, cc, r1, c2, l); + return; + } + + /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. + If the immediate we've been given does not fit that range, we'll + fall back to separate compare and branch instructions using the + larger comparison range afforded by COMPARE IMMEDIATE. */ + if (type == TCG_TYPE_I32) { + if (is_unsigned) { + opc = RIE_CLIJ; + in_range = (uint32_t)c2 == (uint8_t)c2; + } else { + opc = RIE_CIJ; + in_range = (int32_t)c2 == (int8_t)c2; + } + } else { + if (is_unsigned) { + opc = RIE_CLGIJ; + in_range = (uint64_t)c2 == (uint8_t)c2; + } else { + opc = RIE_CGIJ; + in_range = (int64_t)c2 == (int8_t)c2; + } + } + if (in_range) { + tgen_compare_imm_branch(s, opc, cc, r1, c2, l); + return; + } + } + + cc = tgen_cmp(s, type, c, r1, c2, c2const, false); + tgen_branch(s, cc, l); +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +{ + ptrdiff_t off = dest - s->code_ptr; + if (off == (int32_t)off) { + tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); + tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); + } +} + +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, + TCGReg base, TCGReg index, int disp) +{ + switch (opc & (MO_SSIZE | MO_BSWAP)) { + case MO_UB: + tcg_out_insn(s, RXY, LLGC, data, base, index, disp); + break; + case MO_SB: + tcg_out_insn(s, RXY, LGB, data, base, index, disp); + break; + + case MO_UW | MO_BSWAP: + /* swapped unsigned halfword load with upper bits zeroed */ + tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tgen_ext16u(s, TCG_TYPE_I64, data, data); + break; + case MO_UW: + tcg_out_insn(s, RXY, LLGH, data, base, index, disp); + break; + + case MO_SW | MO_BSWAP: + /* swapped sign-extended halfword load */ + tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tgen_ext16s(s, TCG_TYPE_I64, data, data); + break; + case MO_SW: + tcg_out_insn(s, RXY, LGH, data, base, index, disp); + break; + + case MO_UL | MO_BSWAP: + /* swapped unsigned int load with upper bits zeroed */ + tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tgen_ext32u(s, data, data); + break; + case MO_UL: + tcg_out_insn(s, RXY, LLGF, data, base, index, disp); + break; + + case MO_SL | MO_BSWAP: + /* swapped sign-extended int load */ + tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tgen_ext32s(s, data, data); + break; + case MO_SL: + tcg_out_insn(s, RXY, LGF, data, base, index, disp); + break; + + case MO_Q | MO_BSWAP: + tcg_out_insn(s, RXY, LRVG, data, base, index, disp); + break; + case MO_Q: + tcg_out_insn(s, RXY, LG, data, base, index, disp); + break; + + default: + tcg_abort(); + } +} + +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, + TCGReg base, TCGReg index, int disp) +{ + switch (opc & (MO_SIZE | MO_BSWAP)) { + case MO_UB: + if (disp >= 0 && disp < 0x1000) { + tcg_out_insn(s, RX, STC, data, base, index, disp); + } else { + tcg_out_insn(s, RXY, STCY, data, base, index, disp); + } + break; + + case MO_UW | MO_BSWAP: + tcg_out_insn(s, RXY, STRVH, data, base, index, disp); + break; + case MO_UW: + if (disp >= 0 && disp < 0x1000) { + tcg_out_insn(s, RX, STH, data, base, index, disp); + } else { + tcg_out_insn(s, RXY, STHY, data, base, index, disp); + } + break; + + case MO_UL | MO_BSWAP: + tcg_out_insn(s, RXY, STRV, data, base, index, disp); + break; + case MO_UL: + if (disp >= 0 && disp < 0x1000) { + tcg_out_insn(s, RX, ST, data, base, index, disp); + } else { + tcg_out_insn(s, RXY, STY, data, base, index, disp); + } + break; + + case MO_Q | MO_BSWAP: + tcg_out_insn(s, RXY, STRVG, data, base, index, disp); + break; + case MO_Q: + tcg_out_insn(s, RXY, STG, data, base, index, disp); + break; + + default: + tcg_abort(); + } +} + +#if defined(CONFIG_SOFTMMU) +#include "../tcg-ldst.c.inc" + +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); + +/* Load and compare a TLB entry, leaving the flags set. Loads the TLB + addend into R2. Returns a register with the santitized guest address. */ +static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, + int mem_index, bool is_ld) +{ + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + unsigned s_mask = (1 << s_bits) - 1; + unsigned a_mask = (1 << a_bits) - 1; + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; + + tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off); + + /* For aligned accesses, we check the first byte and include the alignment + bits within the address. For unaligned access, we check that we don't + cross pages using the address of the last byte of the access. */ + a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); + tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; + if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) { + tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + } + + if (is_ld) { + ofs = offsetof(CPUTLBEntry, addr_read); + } else { + ofs = offsetof(CPUTLBEntry, addr_write); + } + if (TARGET_LONG_BITS == 32) { + tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + } + + tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + if (TARGET_LONG_BITS == 32) { + tgen_ext32u(s, TCG_REG_R3, addr_reg); + return TCG_REG_R3; + } + return addr_reg; +} + +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, + TCGReg data, TCGReg addr, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->datalo_reg = data; + label->addrlo_reg = addr; + label->raddr = raddr; + label->label_ptr[0] = label_ptr; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGReg addr_reg = lb->addrlo_reg; + TCGReg data_reg = lb->datalo_reg; + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); + if (TARGET_LONG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); + } + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); + + tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + TCGReg addr_reg = lb->addrlo_reg; + TCGReg data_reg = lb->datalo_reg; + TCGMemOpIdx oi = lb->oi; + MemOp opc = get_memop(oi); + + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); + if (TARGET_LONG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); + } + switch (opc & MO_SIZE) { + case MO_UB: + tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + break; + case MO_UW: + tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + break; + case MO_UL: + tgen_ext32u(s, TCG_REG_R4, data_reg); + break; + case MO_Q: + tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + break; + default: + tcg_abort(); + } + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); + tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + + tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; +} +#else +static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, + TCGReg *index_reg, tcg_target_long *disp) +{ + if (TARGET_LONG_BITS == 32) { + tgen_ext32u(s, TCG_TMP0, *addr_reg); + *addr_reg = TCG_TMP0; + } + if (guest_base < 0x80000) { + *index_reg = TCG_REG_NONE; + *disp = guest_base; + } else { + *index_reg = TCG_GUEST_BASE_REG; + *disp = 0; + } +} +#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, + TCGMemOpIdx oi) +{ + MemOp opc = get_memop(oi); +#ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr; + TCGReg base_reg; + + base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); + label_ptr = s->code_ptr; + s->code_ptr += 1; + + tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + + add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr); +#else + TCGReg index_reg; + tcg_target_long disp; + + tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); + tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); +#endif +} + +static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, + TCGMemOpIdx oi) +{ + MemOp opc = get_memop(oi); +#ifdef CONFIG_SOFTMMU + unsigned mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr; + TCGReg base_reg; + + base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); + label_ptr = s->code_ptr; + s->code_ptr += 1; + + tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + + add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr); +#else + TCGReg index_reg; + tcg_target_long disp; + + tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); + tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); +#endif +} + +# define OP_32_64(x) \ + case glue(glue(INDEX_op_,x),_i32): \ + case glue(glue(INDEX_op_,x),_i64) + +static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + S390Opcode op, op2; + TCGArg a0, a1, a2; + + switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + a0 = args[0]; + if (a0 == 0) { + tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); + tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); + } + break; + + case INDEX_op_goto_tb: + a0 = args[0]; + if (s->tb_jmp_insn_offset) { + /* branch displacement must be aligned for atomic patching; + * see if we need to add extra nop before branch + */ + if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { + tcg_out16(s, NOP); + } + tcg_debug_assert(!USE_REG_TB); + tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + s->code_ptr += 2; + } else { + /* load address stored at s->tb_jmp_target_addr + a0 */ + tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, + s->tb_jmp_target_addr + a0); + /* and go there */ + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + } + set_jmp_reset_offset(s, a0); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + int ofs = -tcg_current_code_size(s); + assert(ofs == (int16_t)ofs); + tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); + } + break; + + case INDEX_op_goto_ptr: + a0 = args[0]; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); + break; + + OP_32_64(ld8u): + /* ??? LLC (RXY format) is only present with the extended-immediate + facility, whereas LLGC is always present. */ + tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); + break; + + OP_32_64(ld8s): + /* ??? LB is no smaller than LGB, so no point to using it. */ + tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); + break; + + OP_32_64(ld16u): + /* ??? LLH (RXY format) is only present with the extended-immediate + facility, whereas LLGH is always present. */ + tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); + break; + + case INDEX_op_ld16s_i32: + tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); + break; + + case INDEX_op_ld_i32: + tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); + break; + + OP_32_64(st8): + tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], + TCG_REG_NONE, args[2]); + break; + + OP_32_64(st16): + tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], + TCG_REG_NONE, args[2]); + break; + + case INDEX_op_st_i32: + tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + break; + + case INDEX_op_add_i32: + a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + if (const_args[2]) { + do_addi_32: + if (a0 == a1) { + if (a2 == (int16_t)a2) { + tcg_out_insn(s, RI, AHI, a0, a2); + break; + } + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RIL, AFI, a0, a2); + break; + } + } + tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, AR, a0, a2); + } else { + tcg_out_insn(s, RX, LA, a0, a1, a2, 0); + } + break; + case INDEX_op_sub_i32: + a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + if (const_args[2]) { + a2 = -a2; + goto do_addi_32; + } else if (a0 == a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); + } + break; + + case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, NR, a0, a2); + } else { + tcg_out_insn(s, RRF, NRK, a0, a1, a2); + } + break; + case INDEX_op_or_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_ori(s, TCG_TYPE_I32, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, OR, a0, a2); + } else { + tcg_out_insn(s, RRF, ORK, a0, a1, a2); + } + break; + case INDEX_op_xor_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_xori(s, TCG_TYPE_I32, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); + } + break; + + case INDEX_op_neg_i32: + tcg_out_insn(s, RR, LCR, args[0], args[1]); + break; + + case INDEX_op_mul_i32: + if (const_args[2]) { + if ((int32_t)args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSR, args[0], args[2]); + } + break; + + case INDEX_op_div2_i32: + tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + break; + case INDEX_op_divu2_i32: + tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + break; + + case INDEX_op_shl_i32: + op = RS_SLL; + op2 = RSY_SLLK; + do_shift32: + a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + if (a0 == a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } + } else { + /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } + } + break; + case INDEX_op_shr_i32: + op = RS_SRL; + op2 = RSY_SRLK; + goto do_shift32; + case INDEX_op_sar_i32: + op = RS_SRA; + op2 = RSY_SRAK; + goto do_shift32; + + case INDEX_op_rotl_i32: + /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); + } else { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); + } + break; + case INDEX_op_rotr_i32: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLL, args[0], args[1], + TCG_REG_NONE, (32 - args[2]) & 31); + } else { + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); + } + break; + + case INDEX_op_ext8s_i32: + tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); + break; + case INDEX_op_ext16s_i32: + tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); + break; + case INDEX_op_ext8u_i32: + tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); + break; + case INDEX_op_ext16u_i32: + tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); + break; + + OP_32_64(bswap16): + /* The TCG bswap definition requires bits 0-47 already be zero. + Thus we don't need the G-type insns to implement bswap16_i64. */ + tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); + break; + OP_32_64(bswap32): + tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + break; + + case INDEX_op_add2_i32: + if (const_args[4]) { + tcg_out_insn(s, RIL, ALFI, args[0], args[4]); + } else { + tcg_out_insn(s, RR, ALR, args[0], args[4]); + } + tcg_out_insn(s, RRE, ALCR, args[1], args[5]); + break; + case INDEX_op_sub2_i32: + if (const_args[4]) { + tcg_out_insn(s, RIL, SLFI, args[0], args[4]); + } else { + tcg_out_insn(s, RR, SLR, args[0], args[4]); + } + tcg_out_insn(s, RRE, SLBR, args[1], args[5]); + break; + + case INDEX_op_br: + tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); + break; + + case INDEX_op_brcond_i32: + tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], + args[1], const_args[1], arg_label(args[3])); + break; + case INDEX_op_setcond_i32: + tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_movcond_i32: + tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], + args[2], const_args[2], args[3], const_args[3]); + break; + + case INDEX_op_qemu_ld_i32: + /* ??? Technically we can use a non-extending instruction. */ + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args[0], args[1], args[2]); + break; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args[0], args[1], args[2]); + break; + + case INDEX_op_ld16s_i64: + tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); + break; + case INDEX_op_ld32u_i64: + tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); + break; + case INDEX_op_ld32s_i64: + tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); + break; + case INDEX_op_ld_i64: + tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); + break; + + case INDEX_op_st32_i64: + tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); + break; + case INDEX_op_st_i64: + tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); + break; + + case INDEX_op_add_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + do_addi_64: + if (a0 == a1) { + if (a2 == (int16_t)a2) { + tcg_out_insn(s, RI, AGHI, a0, a2); + break; + } + if (s390_facilities & FACILITY_EXT_IMM) { + if (a2 == (int32_t)a2) { + tcg_out_insn(s, RIL, AGFI, a0, a2); + break; + } else if (a2 == (uint32_t)a2) { + tcg_out_insn(s, RIL, ALGFI, a0, a2); + break; + } else if (-a2 == (uint32_t)-a2) { + tcg_out_insn(s, RIL, SLGFI, a0, -a2); + break; + } + } + } + tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, AGR, a0, a2); + } else { + tcg_out_insn(s, RX, LA, a0, a1, a2, 0); + } + break; + case INDEX_op_sub_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + a2 = -a2; + goto do_addi_64; + } else if (a0 == a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); + } else { + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); + } + break; + + case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); + } + break; + case INDEX_op_or_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_ori(s, TCG_TYPE_I64, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); + } else { + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); + } + break; + case INDEX_op_xor_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_xori(s, TCG_TYPE_I64, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); + } else { + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); + } + break; + + case INDEX_op_neg_i64: + tcg_out_insn(s, RRE, LCGR, args[0], args[1]); + break; + case INDEX_op_bswap64_i64: + tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); + break; + + case INDEX_op_mul_i64: + if (const_args[2]) { + if (args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MGHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + } + break; + + case INDEX_op_div2_i64: + /* ??? We get an unnecessary sign-extension of the dividend + into R3 with this definition, but as we do in fact always + produce both quotient and remainder using INDEX_op_div_i64 + instead requires jumping through even more hoops. */ + tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + break; + case INDEX_op_divu2_i64: + tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); + break; + case INDEX_op_mulu2_i64: + tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); + break; + + case INDEX_op_shl_i64: + op = RSY_SLLG; + do_shift64: + if (const_args[2]) { + tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); + } else { + tcg_out_sh64(s, op, args[0], args[1], args[2], 0); + } + break; + case INDEX_op_shr_i64: + op = RSY_SRLG; + goto do_shift64; + case INDEX_op_sar_i64: + op = RSY_SRAG; + goto do_shift64; + + case INDEX_op_rotl_i64: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], + TCG_REG_NONE, args[2]); + } else { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); + } + break; + case INDEX_op_rotr_i64: + if (const_args[2]) { + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], + TCG_REG_NONE, (64 - args[2]) & 63); + } else { + /* We can use the smaller 32-bit negate because only the + low 6 bits are examined for the rotate. */ + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); + } + break; + + case INDEX_op_ext8s_i64: + tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); + break; + case INDEX_op_ext16s_i64: + tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); + break; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + tgen_ext32s(s, args[0], args[1]); + break; + case INDEX_op_ext8u_i64: + tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); + break; + case INDEX_op_ext16u_i64: + tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); + break; + case INDEX_op_extu_i32_i64: + case INDEX_op_ext32u_i64: + tgen_ext32u(s, args[0], args[1]); + break; + + case INDEX_op_add2_i64: + if (const_args[4]) { + if ((int64_t)args[4] >= 0) { + tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); + } else { + tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); + } + } else { + tcg_out_insn(s, RRE, ALGR, args[0], args[4]); + } + tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); + break; + case INDEX_op_sub2_i64: + if (const_args[4]) { + if ((int64_t)args[4] >= 0) { + tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); + } else { + tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); + } + } else { + tcg_out_insn(s, RRE, SLGR, args[0], args[4]); + } + tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); + break; + + case INDEX_op_brcond_i64: + tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], + args[1], const_args[1], arg_label(args[3])); + break; + case INDEX_op_setcond_i64: + tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], + args[2], const_args[2]); + break; + case INDEX_op_movcond_i64: + tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], + args[2], const_args[2], args[3], const_args[3]); + break; + + OP_32_64(deposit): + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[1]) { + tgen_deposit(s, a0, a2, args[3], args[4], 1); + } else { + /* Since we can't support "0Z" as a constraint, we allow a1 in + any register. Fix things up as if a matching constraint. */ + if (a0 != a1) { + TCGType type = (opc == INDEX_op_deposit_i64); + if (a0 == a2) { + tcg_out_mov(s, type, TCG_TMP0, a2); + a2 = TCG_TMP0; + } + tcg_out_mov(s, type, a0, a1); + } + tgen_deposit(s, a0, a2, args[3], args[4], 0); + } + break; + + OP_32_64(extract): + tgen_extract(s, args[0], args[1], args[2], args[3]); + break; + + case INDEX_op_clz_i64: + tgen_clz(s, args[0], args[1], args[2], const_args[2]); + break; + + case INDEX_op_mb: + /* The host memory model is quite strong, we simply need to + serialize the instruction stream. */ + if (args[0] & TCG_MO_ST_LD) { + tcg_out_insn(s, RR, BCR, + s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); + } + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; + static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; + static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; + static const TCGTargetOpDef a2_r + = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; + static const TCGTargetOpDef a2_ri + = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; + static const TCGTargetOpDef a2_rA + = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); + case INDEX_op_mul_i64: + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_ri; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return &r_r_ri; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "rZ", "r" } }; + return &dep; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; + static const TCGTargetOpDef movc_l + = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; + return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + = { .args_ct_str = { "b", "a", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + = { .args_ct_str = { "b", "a", "0", "r" } }; + return &mul2; + } + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + case INDEX_op_add2_i64: + case INDEX_op_sub2_i64: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + + default: + break; + } + return NULL; +} + +static void query_s390_facilities(void) +{ + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + + /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this + is present on all 64-bit systems, but let's check for it anyway. */ + if (hwcap & HWCAP_S390_STFLE) { + register int r0 __asm__("0"); + register void *r1 __asm__("1"); + + /* stfle 0(%r1) */ + r1 = &s390_facilities; + asm volatile(".word 0xb2b0,0x1000" + : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); + } +} + +static void tcg_target_init(TCGContext *s) +{ + query_s390_facilities(); + + tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; + tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; + + tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); + /* The r6 register is technically call-saved, but it's also a parameter + register, so it can get killed by setup for the qemu_st helper. */ + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); + /* The return register can be considered call-clobbered. */ + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); + /* XXX many insns can't be used with R0, so we better avoid it for now */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } +} + +#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_NLONGS * sizeof(long))) + +static void tcg_target_qemu_prologue(TCGContext *s) +{ + /* stmg %r6,%r15,48(%r15) (save registers) */ + tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); + + /* aghi %r15,-frame_size */ + tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); + + tcg_set_frame(s, TCG_REG_CALL_STACK, + TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, + CPU_TEMP_BUF_NLONGS * sizeof(long)); + +#ifndef CONFIG_SOFTMMU + if (guest_base >= 0x80000) { + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } +#endif + + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, + tcg_target_call_iarg_regs[1]); + } + + /* br %r3 (go to TB) */ + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); + + /* + * Return path for goto_ptr. Set return value to 0, a-la exit_tb, + * and fall through to the rest of the epilogue. + */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + + /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ + tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, + FRAME_SIZE + 48); + + /* br %r14 (return) */ + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x07, count * sizeof(tcg_insn_unit)); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[18]; +} DebugFrame; + +/* We're expecting a 2 byte uleb128 encoded value. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); + +#define ELF_HOST_MACHINE EM_S390 + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = 8, /* sleb128 8 */ + .h.cie.return_column = TCG_REG_R14, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x86, 6, /* DW_CFA_offset, %r6, 48 */ + 0x87, 7, /* DW_CFA_offset, %r7, 56 */ + 0x88, 8, /* DW_CFA_offset, %r8, 64 */ + 0x89, 9, /* DW_CFA_offset, %r92, 72 */ + 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ + 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ + 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ + 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ + 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c deleted file mode 100644 index b07e9ff7d6..0000000000 --- a/tcg/s390/tcg-target.inc.c +++ /dev/null @@ -1,2630 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2009 Ulrich Hecht - * Copyright (c) 2009 Alexander Graf - * Copyright (c) 2010 Richard Henderson - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* We only support generating code for 64-bit mode. */ -#if TCG_TARGET_REG_BITS != 64 -#error "unsupported code generation mode" -#endif - -#include "../tcg-pool.inc.c" -#include "elf.h" - -/* ??? The translation blocks produced by TCG are generally small enough to - be entirely reachable with a 16-bit displacement. Leaving the option for - a 32-bit displacement here Just In Case. */ -#define USE_LONG_BRANCHES 0 - -#define TCG_CT_CONST_S16 0x100 -#define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_S33 0x400 -#define TCG_CT_CONST_ZERO 0x800 - -/* Several places within the instruction set 0 means "no register" - rather than TCG_REG_R0. */ -#define TCG_REG_NONE 0 - -/* A scratch register that may be be used throughout the backend. */ -#define TCG_TMP0 TCG_REG_R1 - -/* A scratch register that holds a pointer to the beginning of the TB. - We don't need this when we have pc-relative loads with the general - instructions extension facility. */ -#define TCG_REG_TB TCG_REG_R12 -#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) - -#ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG TCG_REG_R13 -#endif - -/* All of the following instructions are prefixed with their instruction - format, and are defined as 8- or 16-bit quantities, even when the two - halves of the 16-bit quantity may appear 32 bits apart in the insn. - This makes it easy to copy the values from the tables in Appendix B. */ -typedef enum S390Opcode { - RIL_AFI = 0xc209, - RIL_AGFI = 0xc208, - RIL_ALFI = 0xc20b, - RIL_ALGFI = 0xc20a, - RIL_BRASL = 0xc005, - RIL_BRCL = 0xc004, - RIL_CFI = 0xc20d, - RIL_CGFI = 0xc20c, - RIL_CLFI = 0xc20f, - RIL_CLGFI = 0xc20e, - RIL_CLRL = 0xc60f, - RIL_CLGRL = 0xc60a, - RIL_CRL = 0xc60d, - RIL_CGRL = 0xc608, - RIL_IIHF = 0xc008, - RIL_IILF = 0xc009, - RIL_LARL = 0xc000, - RIL_LGFI = 0xc001, - RIL_LGRL = 0xc408, - RIL_LLIHF = 0xc00e, - RIL_LLILF = 0xc00f, - RIL_LRL = 0xc40d, - RIL_MSFI = 0xc201, - RIL_MSGFI = 0xc200, - RIL_NIHF = 0xc00a, - RIL_NILF = 0xc00b, - RIL_OIHF = 0xc00c, - RIL_OILF = 0xc00d, - RIL_SLFI = 0xc205, - RIL_SLGFI = 0xc204, - RIL_XIHF = 0xc006, - RIL_XILF = 0xc007, - - RI_AGHI = 0xa70b, - RI_AHI = 0xa70a, - RI_BRC = 0xa704, - RI_CHI = 0xa70e, - RI_CGHI = 0xa70f, - RI_IIHH = 0xa500, - RI_IIHL = 0xa501, - RI_IILH = 0xa502, - RI_IILL = 0xa503, - RI_LGHI = 0xa709, - RI_LLIHH = 0xa50c, - RI_LLIHL = 0xa50d, - RI_LLILH = 0xa50e, - RI_LLILL = 0xa50f, - RI_MGHI = 0xa70d, - RI_MHI = 0xa70c, - RI_NIHH = 0xa504, - RI_NIHL = 0xa505, - RI_NILH = 0xa506, - RI_NILL = 0xa507, - RI_OIHH = 0xa508, - RI_OIHL = 0xa509, - RI_OILH = 0xa50a, - RI_OILL = 0xa50b, - - RIE_CGIJ = 0xec7c, - RIE_CGRJ = 0xec64, - RIE_CIJ = 0xec7e, - RIE_CLGRJ = 0xec65, - RIE_CLIJ = 0xec7f, - RIE_CLGIJ = 0xec7d, - RIE_CLRJ = 0xec77, - RIE_CRJ = 0xec76, - RIE_LOCGHI = 0xec46, - RIE_RISBG = 0xec55, - - RRE_AGR = 0xb908, - RRE_ALGR = 0xb90a, - RRE_ALCR = 0xb998, - RRE_ALCGR = 0xb988, - RRE_CGR = 0xb920, - RRE_CLGR = 0xb921, - RRE_DLGR = 0xb987, - RRE_DLR = 0xb997, - RRE_DSGFR = 0xb91d, - RRE_DSGR = 0xb90d, - RRE_FLOGR = 0xb983, - RRE_LGBR = 0xb906, - RRE_LCGR = 0xb903, - RRE_LGFR = 0xb914, - RRE_LGHR = 0xb907, - RRE_LGR = 0xb904, - RRE_LLGCR = 0xb984, - RRE_LLGFR = 0xb916, - RRE_LLGHR = 0xb985, - RRE_LRVR = 0xb91f, - RRE_LRVGR = 0xb90f, - RRE_LTGR = 0xb902, - RRE_MLGR = 0xb986, - RRE_MSGR = 0xb90c, - RRE_MSR = 0xb252, - RRE_NGR = 0xb980, - RRE_OGR = 0xb981, - RRE_SGR = 0xb909, - RRE_SLGR = 0xb90b, - RRE_SLBR = 0xb999, - RRE_SLBGR = 0xb989, - RRE_XGR = 0xb982, - - RRF_LOCR = 0xb9f2, - RRF_LOCGR = 0xb9e2, - RRF_NRK = 0xb9f4, - RRF_NGRK = 0xb9e4, - RRF_ORK = 0xb9f6, - RRF_OGRK = 0xb9e6, - RRF_SRK = 0xb9f9, - RRF_SGRK = 0xb9e9, - RRF_SLRK = 0xb9fb, - RRF_SLGRK = 0xb9eb, - RRF_XRK = 0xb9f7, - RRF_XGRK = 0xb9e7, - - RR_AR = 0x1a, - RR_ALR = 0x1e, - RR_BASR = 0x0d, - RR_BCR = 0x07, - RR_CLR = 0x15, - RR_CR = 0x19, - RR_DR = 0x1d, - RR_LCR = 0x13, - RR_LR = 0x18, - RR_LTR = 0x12, - RR_NR = 0x14, - RR_OR = 0x16, - RR_SR = 0x1b, - RR_SLR = 0x1f, - RR_XR = 0x17, - - RSY_RLL = 0xeb1d, - RSY_RLLG = 0xeb1c, - RSY_SLLG = 0xeb0d, - RSY_SLLK = 0xebdf, - RSY_SRAG = 0xeb0a, - RSY_SRAK = 0xebdc, - RSY_SRLG = 0xeb0c, - RSY_SRLK = 0xebde, - - RS_SLL = 0x89, - RS_SRA = 0x8a, - RS_SRL = 0x88, - - RXY_AG = 0xe308, - RXY_AY = 0xe35a, - RXY_CG = 0xe320, - RXY_CLG = 0xe321, - RXY_CLY = 0xe355, - RXY_CY = 0xe359, - RXY_LAY = 0xe371, - RXY_LB = 0xe376, - RXY_LG = 0xe304, - RXY_LGB = 0xe377, - RXY_LGF = 0xe314, - RXY_LGH = 0xe315, - RXY_LHY = 0xe378, - RXY_LLGC = 0xe390, - RXY_LLGF = 0xe316, - RXY_LLGH = 0xe391, - RXY_LMG = 0xeb04, - RXY_LRV = 0xe31e, - RXY_LRVG = 0xe30f, - RXY_LRVH = 0xe31f, - RXY_LY = 0xe358, - RXY_NG = 0xe380, - RXY_OG = 0xe381, - RXY_STCY = 0xe372, - RXY_STG = 0xe324, - RXY_STHY = 0xe370, - RXY_STMG = 0xeb24, - RXY_STRV = 0xe33e, - RXY_STRVG = 0xe32f, - RXY_STRVH = 0xe33f, - RXY_STY = 0xe350, - RXY_XG = 0xe382, - - RX_A = 0x5a, - RX_C = 0x59, - RX_L = 0x58, - RX_LA = 0x41, - RX_LH = 0x48, - RX_ST = 0x50, - RX_STC = 0x42, - RX_STH = 0x40, - - NOP = 0x0707, -} S390Opcode; - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15" -}; -#endif - -/* Since R6 is a potential argument register, choose it last of the - call-saved registers. Likewise prefer the call-clobbered registers - in reverse order to maximize the chance of avoiding the arguments. */ -static const int tcg_target_reg_alloc_order[] = { - /* Call saved registers. */ - TCG_REG_R13, - TCG_REG_R12, - TCG_REG_R11, - TCG_REG_R10, - TCG_REG_R9, - TCG_REG_R8, - TCG_REG_R7, - TCG_REG_R6, - /* Call clobbered registers. */ - TCG_REG_R14, - TCG_REG_R0, - TCG_REG_R1, - /* Argument registers, in reverse order of allocation. */ - TCG_REG_R5, - TCG_REG_R4, - TCG_REG_R3, - TCG_REG_R2, -}; - -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R2, -}; - -#define S390_CC_EQ 8 -#define S390_CC_LT 4 -#define S390_CC_GT 2 -#define S390_CC_OV 1 -#define S390_CC_NE (S390_CC_LT | S390_CC_GT) -#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) -#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) -#define S390_CC_NEVER 0 -#define S390_CC_ALWAYS 15 - -/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ -static const uint8_t tcg_cond_to_s390_cond[] = { - [TCG_COND_EQ] = S390_CC_EQ, - [TCG_COND_NE] = S390_CC_NE, - [TCG_COND_LT] = S390_CC_LT, - [TCG_COND_LE] = S390_CC_LE, - [TCG_COND_GT] = S390_CC_GT, - [TCG_COND_GE] = S390_CC_GE, - [TCG_COND_LTU] = S390_CC_LT, - [TCG_COND_LEU] = S390_CC_LE, - [TCG_COND_GTU] = S390_CC_GT, - [TCG_COND_GEU] = S390_CC_GE, -}; - -/* Condition codes that result from a LOAD AND TEST. Here, we have no - unsigned instruction variation, however since the test is vs zero we - can re-map the outcomes appropriately. */ -static const uint8_t tcg_cond_to_ltr_cond[] = { - [TCG_COND_EQ] = S390_CC_EQ, - [TCG_COND_NE] = S390_CC_NE, - [TCG_COND_LT] = S390_CC_LT, - [TCG_COND_LE] = S390_CC_LE, - [TCG_COND_GT] = S390_CC_GT, - [TCG_COND_GE] = S390_CC_GE, - [TCG_COND_LTU] = S390_CC_NEVER, - [TCG_COND_LEU] = S390_CC_EQ, - [TCG_COND_GTU] = S390_CC_NE, - [TCG_COND_GEU] = S390_CC_ALWAYS, -}; - -#ifdef CONFIG_SOFTMMU -static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_SB] = helper_ret_ldsb_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LESW] = helper_le_ldsw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LESL] = helper_le_ldsl_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BESW] = helper_be_ldsw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BESL] = helper_be_ldsl_mmu, - [MO_BEQ] = helper_be_ldq_mmu, -}; - -static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, -}; -#endif - -static tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities; - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - intptr_t pcrel2; - uint32_t old; - - value += addend; - pcrel2 = (tcg_insn_unit *)value - code_ptr; - - switch (type) { - case R_390_PC16DBL: - if (pcrel2 == (int16_t)pcrel2) { - tcg_patch16(code_ptr, pcrel2); - return true; - } - break; - case R_390_PC32DBL: - if (pcrel2 == (int32_t)pcrel2) { - tcg_patch32(code_ptr, pcrel2); - return true; - } - break; - case R_390_20: - if (value == sextract64(value, 0, 20)) { - old = *(uint32_t *)code_ptr & 0xf00000ff; - old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); - return true; - } - break; - default: - g_assert_not_reached(); - } - return false; -} - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': /* all registers */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - break; - case 'L': /* qemu_ld/st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffff; - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); - break; - case 'a': /* force R2 for division */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); - break; - case 'b': /* force R3 for division */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0; - tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); - break; - case 'A': - ct->ct |= TCG_CT_CONST_S33; - break; - case 'I': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* Test if a constant matches the constraint. */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - - if (ct & TCG_CT_CONST) { - return 1; - } - - if (type == TCG_TYPE_I32) { - val = (int32_t)val; - } - - /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_S16) { - return val == (int16_t)val; - } else if (ct & TCG_CT_CONST_S32) { - return val == (int32_t)val; - } else if (ct & TCG_CT_CONST_S33) { - return val >= -0xffffffffll && val <= 0xffffffffll; - } else if (ct & TCG_CT_CONST_ZERO) { - return val == 0; - } - - return 0; -} - -/* Emit instructions according to the given instruction format. */ - -static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) -{ - tcg_out16(s, (op << 8) | (r1 << 4) | r2); -} - -static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, - TCGReg r1, TCGReg r2) -{ - tcg_out32(s, (op << 16) | (r1 << 4) | r2); -} - -static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op, - TCGReg r1, TCGReg r2, int m3) -{ - tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); -} - -static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) -{ - tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); -} - -static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, - int i2, int m3) -{ - tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); - tcg_out32(s, (i2 << 16) | (op & 0xff)); -} - -static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) -{ - tcg_out16(s, op | (r1 << 4)); - tcg_out32(s, i2); -} - -static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, - TCGReg b2, TCGReg r3, int disp) -{ - tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) - | (disp & 0xfff)); -} - -static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, - TCGReg b2, TCGReg r3, int disp) -{ - tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); - tcg_out32(s, (op & 0xff) | (b2 << 28) - | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); -} - -#define tcg_out_insn_RX tcg_out_insn_RS -#define tcg_out_insn_RXY tcg_out_insn_RSY - -/* Emit an opcode with "type-checking" of the format. */ -#define tcg_out_insn(S, FMT, OP, ...) \ - glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) - - -/* emit 64-bit shifts */ -static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, - TCGReg src, TCGReg sh_reg, int sh_imm) -{ - tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); -} - -/* emit 32-bit shifts */ -static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, - TCGReg sh_reg, int sh_imm) -{ - tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); -} - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) -{ - if (src != dst) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, LR, dst, src); - } else { - tcg_out_insn(s, RRE, LGR, dst, src); - } - } - return true; -} - -static const S390Opcode lli_insns[4] = { - RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH -}; - -static bool maybe_out_small_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) -{ - tcg_target_ulong uval = sval; - int i; - - if (type == TCG_TYPE_I32) { - uval = (uint32_t)sval; - sval = (int32_t)sval; - } - - /* Try all 32-bit insns that can load it in one go. */ - if (sval >= -0x8000 && sval < 0x8000) { - tcg_out_insn(s, RI, LGHI, ret, sval); - return true; - } - - for (i = 0; i < 4; i++) { - tcg_target_long mask = 0xffffull << i*16; - if ((uval & mask) == uval) { - tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); - return true; - } - } - - return false; -} - -/* load a register with an immediate value */ -static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long sval, bool in_prologue) -{ - tcg_target_ulong uval; - - /* Try all 32-bit insns that can load it in one go. */ - if (maybe_out_small_movi(s, type, ret, sval)) { - return; - } - - uval = sval; - if (type == TCG_TYPE_I32) { - uval = (uint32_t)sval; - sval = (int32_t)sval; - } - - /* Try all 48-bit insns that can load it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { - if (sval == (int32_t)sval) { - tcg_out_insn(s, RIL, LGFI, ret, sval); - return; - } - if (uval <= 0xffffffff) { - tcg_out_insn(s, RIL, LLILF, ret, uval); - return; - } - if ((uval & 0xffffffff) == 0) { - tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); - return; - } - } - - /* Try for PC-relative address load. For odd addresses, - attempt to use an offset from the start of the TB. */ - if ((sval & 1) == 0) { - ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1; - if (off == (int32_t)off) { - tcg_out_insn(s, RIL, LARL, ret, off); - return; - } - } else if (USE_REG_TB && !in_prologue) { - ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; - if (off == sextract64(off, 0, 20)) { - /* This is certain to be an address within TB, and therefore - OFF will be negative; don't try RX_LA. */ - tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); - return; - } - } - - /* A 32-bit unsigned value can be loaded in 2 insns. And given - that LLILL, LLIHL, LLILF above did not succeed, we know that - both insns are required. */ - if (uval <= 0xffffffff) { - tcg_out_insn(s, RI, LLILL, ret, uval); - tcg_out_insn(s, RI, IILH, ret, uval >> 16); - return; - } - - /* Otherwise, stuff it in the constant pool. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - tcg_out_insn(s, RIL, LGRL, ret, 0); - new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); - } else if (USE_REG_TB && !in_prologue) { - tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, sval, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - } else { - TCGReg base = ret ? ret : TCG_TMP0; - tcg_out_insn(s, RIL, LARL, base, 0); - new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); - tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0); - } -} - -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) -{ - tcg_out_movi_int(s, type, ret, sval, false); -} - -/* Emit a load/store type instruction. Inputs are: - DATA: The register to be loaded or stored. - BASE+OFS: The effective address. - OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. - OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ - -static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, - TCGReg data, TCGReg base, TCGReg index, - tcg_target_long ofs) -{ - if (ofs < -0x80000 || ofs >= 0x80000) { - /* Combine the low 20 bits of the offset with the actual load insn; - the high 44 bits must come from an immediate load. */ - tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); - ofs = low; - - /* If we were already given an index register, add it in. */ - if (index != TCG_REG_NONE) { - tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); - } - index = TCG_TMP0; - } - - if (opc_rx && ofs >= 0 && ofs < 0x1000) { - tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); - } else { - tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); - } -} - - -/* load data without address translation or endianness conversion */ -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) -{ - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); - } -} - -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) -{ - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); - } -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - return false; -} - -/* load data from an absolute host address */ -static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) -{ - intptr_t addr = (intptr_t)abs; - - if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) { - ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1; - if (disp == (int32_t)disp) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RIL, LRL, dest, disp); - } else { - tcg_out_insn(s, RIL, LGRL, dest, disp); - } - return; - } - } - if (USE_REG_TB) { - ptrdiff_t disp = abs - (void *)s->code_gen_ptr; - if (disp == sextract64(disp, 0, 20)) { - tcg_out_ld(s, type, dest, TCG_REG_TB, disp); - return; - } - } - - tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); - tcg_out_ld(s, type, dest, dest, addr & 0xffff); -} - -static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, - int msb, int lsb, int ofs, int z) -{ - /* Format RIE-f */ - tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src); - tcg_out16(s, (msb << 8) | (z << 7) | lsb); - tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff)); -} - -static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RRE, LGBR, dest, src); - return; - } - - if (type == TCG_TYPE_I32) { - if (dest == src) { - tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24); - } else { - tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24); - } - tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24); - } else { - tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56); - tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56); - } -} - -static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RRE, LLGCR, dest, src); - return; - } - - if (dest == src) { - tcg_out_movi(s, type, TCG_TMP0, 0xff); - src = TCG_TMP0; - } else { - tcg_out_movi(s, type, dest, 0xff); - } - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, NR, dest, src); - } else { - tcg_out_insn(s, RRE, NGR, dest, src); - } -} - -static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RRE, LGHR, dest, src); - return; - } - - if (type == TCG_TYPE_I32) { - if (dest == src) { - tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16); - } else { - tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16); - } - tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16); - } else { - tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48); - tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48); - } -} - -static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RRE, LLGHR, dest, src); - return; - } - - if (dest == src) { - tcg_out_movi(s, type, TCG_TMP0, 0xffff); - src = TCG_TMP0; - } else { - tcg_out_movi(s, type, dest, 0xffff); - } - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, NR, dest, src); - } else { - tcg_out_insn(s, RRE, NGR, dest, src); - } -} - -static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src) -{ - tcg_out_insn(s, RRE, LGFR, dest, src); -} - -static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src) -{ - tcg_out_insn(s, RRE, LLGFR, dest, src); -} - -/* Accept bit patterns like these: - 0....01....1 - 1....10....0 - 1..10..01..1 - 0..01..10..0 - Copied from gcc sources. */ -static inline bool risbg_mask(uint64_t c) -{ - uint64_t lsb; - /* We don't change the number of transitions by inverting, - so make sure we start with the LSB zero. */ - if (c & 1) { - c = ~c; - } - /* Reject all zeros or all ones. */ - if (c == 0) { - return false; - } - /* Find the first transition. */ - lsb = c & -c; - /* Invert to look for a second transition. */ - c = ~c; - /* Erase the first transition. */ - c &= -lsb; - /* Find the second transition, if any. */ - lsb = c & -c; - /* Match if all the bits are 1's, or if c is zero. */ - return c == -lsb; -} - -static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) -{ - int msb, lsb; - if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { - /* Achieve wraparound by swapping msb and lsb. */ - msb = 64 - ctz64(~val); - lsb = clz64(~val) - 1; - } else { - msb = clz64(val); - lsb = 63 - ctz64(val); - } - tcg_out_risbg(s, out, in, msb, lsb, 0, 1); -} - -static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) -{ - static const S390Opcode ni_insns[4] = { - RI_NILL, RI_NILH, RI_NIHL, RI_NIHH - }; - static const S390Opcode nif_insns[2] = { - RIL_NILF, RIL_NIHF - }; - uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); - int i; - - /* Look for the zero-extensions. */ - if ((val & valid) == 0xffffffff) { - tgen_ext32u(s, dest, dest); - return; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if ((val & valid) == 0xff) { - tgen_ext8u(s, TCG_TYPE_I64, dest, dest); - return; - } - if ((val & valid) == 0xffff) { - tgen_ext16u(s, TCG_TYPE_I64, dest, dest); - return; - } - } - - /* Try all 32-bit insns that can perform it in one go. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = ~(0xffffull << i*16); - if (((val | ~valid) & mask) == mask) { - tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16); - return; - } - } - - /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { - for (i = 0; i < 2; i++) { - tcg_target_ulong mask = ~(0xffffffffull << i*32); - if (((val | ~valid) & mask) == mask) { - tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); - return; - } - } - } - if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) { - tgen_andi_risbg(s, dest, dest, val); - return; - } - - /* Use the constant pool if USE_REG_TB, but not for small constants. */ - if (USE_REG_TB) { - if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { - tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - return; - } - } else { - tcg_out_movi(s, type, TCG_TMP0, val); - } - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, NR, dest, TCG_TMP0); - } else { - tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0); - } -} - -static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) -{ - static const S390Opcode oi_insns[4] = { - RI_OILL, RI_OILH, RI_OIHL, RI_OIHH - }; - static const S390Opcode oif_insns[2] = { - RIL_OILF, RIL_OIHF - }; - - int i; - - /* Look for no-op. */ - if (unlikely(val == 0)) { - return; - } - - /* Try all 32-bit insns that can perform it in one go. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = (0xffffull << i*16); - if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - return; - } - } - - /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { - for (i = 0; i < 2; i++) { - tcg_target_ulong mask = (0xffffffffull << i*32); - if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); - return; - } - } - } - - /* Use the constant pool if USE_REG_TB, but not for small constants. */ - if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, OR, dest, TCG_TMP0); - } else { - tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); - } - } else if (USE_REG_TB) { - tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - } else { - /* Perform the OR via sequential modifications to the high and - low parts. Do this via recursion to handle 16-bit vs 32-bit - masks in each half. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); - tgen_ori(s, type, dest, val & 0x00000000ffffffffull); - tgen_ori(s, type, dest, val & 0xffffffff00000000ull); - } -} - -static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) -{ - /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { - if ((val & 0xffffffff00000000ull) == 0) { - tcg_out_insn(s, RIL, XILF, dest, val); - return; - } - if ((val & 0x00000000ffffffffull) == 0) { - tcg_out_insn(s, RIL, XIHF, dest, val >> 32); - return; - } - } - - /* Use the constant pool if USE_REG_TB, but not for small constants. */ - if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, XR, dest, TCG_TMP0); - } else { - tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); - } - } else if (USE_REG_TB) { - tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - } else { - /* Perform the xor by parts. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); - if (val & 0xffffffff) { - tcg_out_insn(s, RIL, XILF, dest, val); - } - if (val > 0xffffffff) { - tcg_out_insn(s, RIL, XIHF, dest, val >> 32); - } - } -} - -static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, - TCGArg c2, bool c2const, bool need_carry) -{ - bool is_unsigned = is_unsigned_cond(c); - S390Opcode op; - - if (c2const) { - if (c2 == 0) { - if (!(is_unsigned && need_carry)) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, LTR, r1, r1); - } else { - tcg_out_insn(s, RRE, LTGR, r1, r1); - } - return tcg_cond_to_ltr_cond[c]; - } - } - - if (!is_unsigned && c2 == (int16_t)c2) { - op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); - tcg_out_insn_RI(s, op, r1, c2); - goto exit; - } - - if (s390_facilities & FACILITY_EXT_IMM) { - if (type == TCG_TYPE_I32) { - op = (is_unsigned ? RIL_CLFI : RIL_CFI); - tcg_out_insn_RIL(s, op, r1, c2); - goto exit; - } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) { - op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); - tcg_out_insn_RIL(s, op, r1, c2); - goto exit; - } - } - - /* Use the constant pool, but not for small constants. */ - if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { - c2 = TCG_TMP0; - /* fall through to reg-reg */ - } else if (USE_REG_TB) { - if (type == TCG_TYPE_I32) { - op = (is_unsigned ? RXY_CLY : RXY_CY); - tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, - 4 - (intptr_t)s->code_gen_ptr); - } else { - op = (is_unsigned ? RXY_CLG : RXY_CG); - tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, c2, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - } - goto exit; - } else { - if (type == TCG_TYPE_I32) { - op = (is_unsigned ? RIL_CLRL : RIL_CRL); - tcg_out_insn_RIL(s, op, r1, 0); - new_pool_label(s, (uint32_t)c2, R_390_PC32DBL, - s->code_ptr - 2, 2 + 4); - } else { - op = (is_unsigned ? RIL_CLGRL : RIL_CGRL); - tcg_out_insn_RIL(s, op, r1, 0); - new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2); - } - goto exit; - } - } - - if (type == TCG_TYPE_I32) { - op = (is_unsigned ? RR_CLR : RR_CR); - tcg_out_insn_RR(s, op, r1, c2); - } else { - op = (is_unsigned ? RRE_CLGR : RRE_CGR); - tcg_out_insn_RRE(s, op, r1, c2); - } - - exit: - return tcg_cond_to_s390_cond[c]; -} - -static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg dest, TCGReg c1, TCGArg c2, int c2const) -{ - int cc; - bool have_loc; - - /* With LOC2, we can always emit the minimum 3 insns. */ - if (s390_facilities & FACILITY_LOAD_ON_COND2) { - /* Emit: d = 0, d = (cc ? 1 : d). */ - cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); - return; - } - - have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; - - /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ - restart: - switch (cond) { - case TCG_COND_NE: - /* X != 0 is X > 0. */ - if (c2const && c2 == 0) { - cond = TCG_COND_GTU; - } else { - break; - } - /* fallthru */ - - case TCG_COND_GTU: - case TCG_COND_GT: - /* The result of a compare has CC=2 for GT and CC=3 unused. - ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ - tgen_cmp(s, type, cond, c1, c2, c2const, true); - tcg_out_movi(s, type, dest, 0); - tcg_out_insn(s, RRE, ALCGR, dest, dest); - return; - - case TCG_COND_EQ: - /* X == 0 is X <= 0. */ - if (c2const && c2 == 0) { - cond = TCG_COND_LEU; - } else { - break; - } - /* fallthru */ - - case TCG_COND_LEU: - case TCG_COND_LE: - /* As above, but we're looking for borrow, or !carry. - The second insn computes d - d - borrow, or -1 for true - and 0 for false. So we must mask to 1 bit afterward. */ - tgen_cmp(s, type, cond, c1, c2, c2const, true); - tcg_out_insn(s, RRE, SLBGR, dest, dest); - tgen_andi(s, type, dest, 1); - return; - - case TCG_COND_GEU: - case TCG_COND_LTU: - case TCG_COND_LT: - case TCG_COND_GE: - /* Swap operands so that we can use LEU/GTU/GT/LE. */ - if (c2const) { - if (have_loc) { - break; - } - tcg_out_movi(s, type, TCG_TMP0, c2); - c2 = c1; - c2const = 0; - c1 = TCG_TMP0; - } else { - TCGReg t = c1; - c1 = c2; - c2 = t; - } - cond = tcg_swap_cond(cond); - goto restart; - - default: - g_assert_not_reached(); - } - - cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - if (have_loc) { - /* Emit: d = 0, t = 1, d = (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); - } else { - /* Emit: d = 1; if (cc) goto over; d = 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - } -} - -static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, - TCGReg c1, TCGArg c2, int c2const, - TCGArg v3, int v3const) -{ - int cc; - if (s390_facilities & FACILITY_LOAD_ON_COND) { - cc = tgen_cmp(s, type, c, c1, c2, c2const, false); - if (v3const) { - tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); - } else { - tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); - } - } else { - c = tcg_invert_cond(c); - cc = tgen_cmp(s, type, c, c1, c2, c2const, false); - - /* Emit: if (cc) goto over; dest = r3; over: */ - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, v3); - } -} - -static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, - TCGArg a2, int a2const) -{ - /* Since this sets both R and R+1, we have no choice but to store the - result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ - QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); - tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); - - if (a2const && a2 == 64) { - tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); - } else { - if (a2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, a2); - } else { - tcg_out_mov(s, TCG_TYPE_I64, dest, a2); - } - if (s390_facilities & FACILITY_LOAD_ON_COND) { - /* Emit: if (one bit found) dest = r0. */ - tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); - } else { - /* Emit: if (no one bit found) goto over; dest = r0; over: */ - tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0); - } - } -} - -static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, - int ofs, int len, int z) -{ - int lsb = (63 - ofs); - int msb = lsb - (len - 1); - tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); -} - -static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, - int ofs, int len) -{ - tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); -} - -static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest) -{ - ptrdiff_t off = dest - s->code_ptr; - if (off == (int16_t)off) { - tcg_out_insn(s, RI, BRC, cc, off); - } else if (off == (int32_t)off) { - tcg_out_insn(s, RIL, BRCL, cc, off); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); - tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); - } -} - -static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) -{ - if (l->has_value) { - tgen_gotoi(s, cc, l->u.value_ptr); - } else if (USE_LONG_BRANCHES) { - tcg_out16(s, RIL_BRCL | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2); - s->code_ptr += 2; - } else { - tcg_out16(s, RI_BRC | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); - s->code_ptr += 1; - } -} - -static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, - TCGReg r1, TCGReg r2, TCGLabel *l) -{ - intptr_t off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - - tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); - tcg_out16(s, off); - tcg_out16(s, cc << 12 | (opc & 0xff)); -} - -static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, - TCGReg r1, int i2, TCGLabel *l) -{ - tcg_target_long off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - - tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); - tcg_out16(s, off); - tcg_out16(s, (i2 << 8) | (opc & 0xff)); -} - -static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, - TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) -{ - int cc; - - if (s390_facilities & FACILITY_GEN_INST_EXT) { - bool is_unsigned = is_unsigned_cond(c); - bool in_range; - S390Opcode opc; - - cc = tcg_cond_to_s390_cond[c]; - - if (!c2const) { - opc = (type == TCG_TYPE_I32 - ? (is_unsigned ? RIE_CLRJ : RIE_CRJ) - : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ)); - tgen_compare_branch(s, opc, cc, r1, c2, l); - return; - } - - /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. - If the immediate we've been given does not fit that range, we'll - fall back to separate compare and branch instructions using the - larger comparison range afforded by COMPARE IMMEDIATE. */ - if (type == TCG_TYPE_I32) { - if (is_unsigned) { - opc = RIE_CLIJ; - in_range = (uint32_t)c2 == (uint8_t)c2; - } else { - opc = RIE_CIJ; - in_range = (int32_t)c2 == (int8_t)c2; - } - } else { - if (is_unsigned) { - opc = RIE_CLGIJ; - in_range = (uint64_t)c2 == (uint8_t)c2; - } else { - opc = RIE_CGIJ; - in_range = (int64_t)c2 == (int8_t)c2; - } - } - if (in_range) { - tgen_compare_imm_branch(s, opc, cc, r1, c2, l); - return; - } - } - - cc = tgen_cmp(s, type, c, r1, c2, c2const, false); - tgen_branch(s, cc, l); -} - -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) -{ - ptrdiff_t off = dest - s->code_ptr; - if (off == (int32_t)off) { - tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); - tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); - } -} - -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) -{ - switch (opc & (MO_SSIZE | MO_BSWAP)) { - case MO_UB: - tcg_out_insn(s, RXY, LLGC, data, base, index, disp); - break; - case MO_SB: - tcg_out_insn(s, RXY, LGB, data, base, index, disp); - break; - - case MO_UW | MO_BSWAP: - /* swapped unsigned halfword load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); - tgen_ext16u(s, TCG_TYPE_I64, data, data); - break; - case MO_UW: - tcg_out_insn(s, RXY, LLGH, data, base, index, disp); - break; - - case MO_SW | MO_BSWAP: - /* swapped sign-extended halfword load */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); - tgen_ext16s(s, TCG_TYPE_I64, data, data); - break; - case MO_SW: - tcg_out_insn(s, RXY, LGH, data, base, index, disp); - break; - - case MO_UL | MO_BSWAP: - /* swapped unsigned int load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); - tgen_ext32u(s, data, data); - break; - case MO_UL: - tcg_out_insn(s, RXY, LLGF, data, base, index, disp); - break; - - case MO_SL | MO_BSWAP: - /* swapped sign-extended int load */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); - tgen_ext32s(s, data, data); - break; - case MO_SL: - tcg_out_insn(s, RXY, LGF, data, base, index, disp); - break; - - case MO_Q | MO_BSWAP: - tcg_out_insn(s, RXY, LRVG, data, base, index, disp); - break; - case MO_Q: - tcg_out_insn(s, RXY, LG, data, base, index, disp); - break; - - default: - tcg_abort(); - } -} - -static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) -{ - switch (opc & (MO_SIZE | MO_BSWAP)) { - case MO_UB: - if (disp >= 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STC, data, base, index, disp); - } else { - tcg_out_insn(s, RXY, STCY, data, base, index, disp); - } - break; - - case MO_UW | MO_BSWAP: - tcg_out_insn(s, RXY, STRVH, data, base, index, disp); - break; - case MO_UW: - if (disp >= 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STH, data, base, index, disp); - } else { - tcg_out_insn(s, RXY, STHY, data, base, index, disp); - } - break; - - case MO_UL | MO_BSWAP: - tcg_out_insn(s, RXY, STRV, data, base, index, disp); - break; - case MO_UL: - if (disp >= 0 && disp < 0x1000) { - tcg_out_insn(s, RX, ST, data, base, index, disp); - } else { - tcg_out_insn(s, RXY, STY, data, base, index, disp); - } - break; - - case MO_Q | MO_BSWAP: - tcg_out_insn(s, RXY, STRVG, data, base, index, disp); - break; - case MO_Q: - tcg_out_insn(s, RXY, STG, data, base, index, disp); - break; - - default: - tcg_abort(); - } -} - -#if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.inc.c" - -/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - -/* Load and compare a TLB entry, leaving the flags set. Loads the TLB - addend into R2. Returns a register with the santitized guest address. */ -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - int mem_index, bool is_ld) -{ - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - unsigned s_mask = (1 << s_bits) - 1; - unsigned a_mask = (1 << a_bits) - 1; - int fast_off = TLB_MASK_TABLE_OFS(mem_index); - int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); - int table_off = fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; - - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off); - - /* For aligned accesses, we check the first byte and include the alignment - bits within the address. For unaligned access, we check that we don't - cross pages using the address of the last byte of the access. */ - a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); - tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); - } - - if (is_ld) { - ofs = offsetof(CPUTLBEntry, addr_read); - } else { - ofs = offsetof(CPUTLBEntry, addr_write); - } - if (TARGET_LONG_BITS == 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); - } - - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (TARGET_LONG_BITS == 32) { - tgen_ext32u(s, TCG_REG_R3, addr_reg); - return TCG_REG_R3; - } - return addr_reg; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, - TCGReg data, TCGReg addr, - tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label = new_ldst_label(s); - - label->is_ld = is_ld; - label->oi = oi; - label->datalo_reg = data; - label->addrlo_reg = addr; - label->raddr = raddr; - label->label_ptr[0] = label_ptr; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg addr_reg = lb->addrlo_reg; - TCGReg data_reg = lb->datalo_reg; - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - - if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); - - tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); - return true; -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) -{ - TCGReg addr_reg = lb->addrlo_reg; - TCGReg data_reg = lb->datalo_reg; - TCGMemOpIdx oi = lb->oi; - MemOp opc = get_memop(oi); - - if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - switch (opc & MO_SIZE) { - case MO_UB: - tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); - break; - case MO_UW: - tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); - break; - case MO_UL: - tgen_ext32u(s, TCG_REG_R4, data_reg); - break; - case MO_Q: - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); - break; - default: - tcg_abort(); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); - return true; -} -#else -static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, - TCGReg *index_reg, tcg_target_long *disp) -{ - if (TARGET_LONG_BITS == 32) { - tgen_ext32u(s, TCG_TMP0, *addr_reg); - *addr_reg = TCG_TMP0; - } - if (guest_base < 0x80000) { - *index_reg = TCG_REG_NONE; - *disp = guest_base; - } else { - *index_reg = TCG_GUEST_BASE_REG; - *disp = 0; - } -} -#endif /* CONFIG_SOFTMMU */ - -static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOpIdx oi) -{ - MemOp opc = get_memop(oi); -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base_reg; - - base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr = s->code_ptr; - s->code_ptr += 1; - - tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); - - add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr); -#else - TCGReg index_reg; - tcg_target_long disp; - - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); -#endif -} - -static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, - TCGMemOpIdx oi) -{ - MemOp opc = get_memop(oi); -#ifdef CONFIG_SOFTMMU - unsigned mem_index = get_mmuidx(oi); - tcg_insn_unit *label_ptr; - TCGReg base_reg; - - base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr = s->code_ptr; - s->code_ptr += 1; - - tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); - - add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr); -#else - TCGReg index_reg; - tcg_target_long disp; - - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); -#endif -} - -# define OP_32_64(x) \ - case glue(glue(INDEX_op_,x),_i32): \ - case glue(glue(INDEX_op_,x),_i64) - -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - S390Opcode op, op2; - TCGArg a0, a1, a2; - - switch (opc) { - case INDEX_op_exit_tb: - /* Reuse the zeroing that exists for goto_ptr. */ - a0 = args[0]; - if (a0 == 0) { - tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); - tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); - } - break; - - case INDEX_op_goto_tb: - a0 = args[0]; - if (s->tb_jmp_insn_offset) { - /* branch displacement must be aligned for atomic patching; - * see if we need to add extra nop before branch - */ - if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { - tcg_out16(s, NOP); - } - tcg_debug_assert(!USE_REG_TB); - tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - s->code_ptr += 2; - } else { - /* load address stored at s->tb_jmp_target_addr + a0 */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, - s->tb_jmp_target_addr + a0); - /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); - } - set_jmp_reset_offset(s, a0); - - /* For the unlinked path of goto_tb, we need to reset - TCG_REG_TB to the beginning of this TB. */ - if (USE_REG_TB) { - int ofs = -tcg_current_code_size(s); - assert(ofs == (int16_t)ofs); - tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); - } - break; - - case INDEX_op_goto_ptr: - a0 = args[0]; - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); - } - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); - break; - - OP_32_64(ld8u): - /* ??? LLC (RXY format) is only present with the extended-immediate - facility, whereas LLGC is always present. */ - tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); - break; - - OP_32_64(ld8s): - /* ??? LB is no smaller than LGB, so no point to using it. */ - tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); - break; - - OP_32_64(ld16u): - /* ??? LLH (RXY format) is only present with the extended-immediate - facility, whereas LLGH is always present. */ - tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); - break; - - case INDEX_op_ld16s_i32: - tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); - break; - - case INDEX_op_ld_i32: - tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); - break; - - OP_32_64(st8): - tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], - TCG_REG_NONE, args[2]); - break; - - OP_32_64(st16): - tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], - TCG_REG_NONE, args[2]); - break; - - case INDEX_op_st_i32: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); - break; - - case INDEX_op_add_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; - if (const_args[2]) { - do_addi_32: - if (a0 == a1) { - if (a2 == (int16_t)a2) { - tcg_out_insn(s, RI, AHI, a0, a2); - break; - } - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RIL, AFI, a0, a2); - break; - } - } - tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RR, AR, a0, a2); - } else { - tcg_out_insn(s, RX, LA, a0, a1, a2, 0); - } - break; - case INDEX_op_sub_i32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; - if (const_args[2]) { - a2 = -a2; - goto do_addi_32; - } else if (a0 == a1) { - tcg_out_insn(s, RR, SR, a0, a2); - } else { - tcg_out_insn(s, RRF, SRK, a0, a1, a2); - } - break; - - case INDEX_op_and_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_andi(s, TCG_TYPE_I32, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RR, NR, a0, a2); - } else { - tcg_out_insn(s, RRF, NRK, a0, a1, a2); - } - break; - case INDEX_op_or_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_ori(s, TCG_TYPE_I32, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RR, OR, a0, a2); - } else { - tcg_out_insn(s, RRF, ORK, a0, a1, a2); - } - break; - case INDEX_op_xor_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_xori(s, TCG_TYPE_I32, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RR, XR, args[0], args[2]); - } else { - tcg_out_insn(s, RRF, XRK, a0, a1, a2); - } - break; - - case INDEX_op_neg_i32: - tcg_out_insn(s, RR, LCR, args[0], args[1]); - break; - - case INDEX_op_mul_i32: - if (const_args[2]) { - if ((int32_t)args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MHI, args[0], args[2]); - } else { - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); - } - } else { - tcg_out_insn(s, RRE, MSR, args[0], args[2]); - } - break; - - case INDEX_op_div2_i32: - tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); - break; - case INDEX_op_divu2_i32: - tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); - break; - - case INDEX_op_shl_i32: - op = RS_SLL; - op2 = RSY_SLLK; - do_shift32: - a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; - if (a0 == a1) { - if (const_args[2]) { - tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); - } else { - tcg_out_sh32(s, op, a0, a2, 0); - } - } else { - /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ - if (const_args[2]) { - tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); - } else { - tcg_out_sh64(s, op2, a0, a1, a2, 0); - } - } - break; - case INDEX_op_shr_i32: - op = RS_SRL; - op2 = RSY_SRLK; - goto do_shift32; - case INDEX_op_sar_i32: - op = RS_SRA; - op2 = RSY_SRAK; - goto do_shift32; - - case INDEX_op_rotl_i32: - /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); - } else { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); - } - break; - case INDEX_op_rotr_i32: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLL, args[0], args[1], - TCG_REG_NONE, (32 - args[2]) & 31); - } else { - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); - } - break; - - case INDEX_op_ext8s_i32: - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); - break; - case INDEX_op_ext16s_i32: - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); - break; - case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); - break; - case INDEX_op_ext16u_i32: - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); - break; - - OP_32_64(bswap16): - /* The TCG bswap definition requires bits 0-47 already be zero. - Thus we don't need the G-type insns to implement bswap16_i64. */ - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); - break; - OP_32_64(bswap32): - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - break; - - case INDEX_op_add2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, ALFI, args[0], args[4]); - } else { - tcg_out_insn(s, RR, ALR, args[0], args[4]); - } - tcg_out_insn(s, RRE, ALCR, args[1], args[5]); - break; - case INDEX_op_sub2_i32: - if (const_args[4]) { - tcg_out_insn(s, RIL, SLFI, args[0], args[4]); - } else { - tcg_out_insn(s, RR, SLR, args[0], args[4]); - } - tcg_out_insn(s, RRE, SLBR, args[1], args[5]); - break; - - case INDEX_op_br: - tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); - break; - - case INDEX_op_brcond_i32: - tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); - break; - case INDEX_op_setcond_i32: - tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_movcond_i32: - tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); - break; - - case INDEX_op_qemu_ld_i32: - /* ??? Technically we can use a non-extending instruction. */ - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); - break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); - break; - - case INDEX_op_ld16s_i64: - tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); - break; - case INDEX_op_ld32u_i64: - tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); - break; - case INDEX_op_ld32s_i64: - tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); - break; - case INDEX_op_ld_i64: - tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); - break; - - case INDEX_op_st32_i64: - tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); - break; - case INDEX_op_st_i64: - tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); - break; - - case INDEX_op_add_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - do_addi_64: - if (a0 == a1) { - if (a2 == (int16_t)a2) { - tcg_out_insn(s, RI, AGHI, a0, a2); - break; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if (a2 == (int32_t)a2) { - tcg_out_insn(s, RIL, AGFI, a0, a2); - break; - } else if (a2 == (uint32_t)a2) { - tcg_out_insn(s, RIL, ALGFI, a0, a2); - break; - } else if (-a2 == (uint32_t)-a2) { - tcg_out_insn(s, RIL, SLGFI, a0, -a2); - break; - } - } - } - tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, AGR, a0, a2); - } else { - tcg_out_insn(s, RX, LA, a0, a1, a2, 0); - } - break; - case INDEX_op_sub_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - a2 = -a2; - goto do_addi_64; - } else if (a0 == a1) { - tcg_out_insn(s, RRE, SGR, a0, a2); - } else { - tcg_out_insn(s, RRF, SGRK, a0, a1, a2); - } - break; - - case INDEX_op_and_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, NGR, args[0], args[2]); - } else { - tcg_out_insn(s, RRF, NGRK, a0, a1, a2); - } - break; - case INDEX_op_or_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_ori(s, TCG_TYPE_I64, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, OGR, a0, a2); - } else { - tcg_out_insn(s, RRF, OGRK, a0, a1, a2); - } - break; - case INDEX_op_xor_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_xori(s, TCG_TYPE_I64, a0, a2); - } else if (a0 == a1) { - tcg_out_insn(s, RRE, XGR, a0, a2); - } else { - tcg_out_insn(s, RRF, XGRK, a0, a1, a2); - } - break; - - case INDEX_op_neg_i64: - tcg_out_insn(s, RRE, LCGR, args[0], args[1]); - break; - case INDEX_op_bswap64_i64: - tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); - break; - - case INDEX_op_mul_i64: - if (const_args[2]) { - if (args[2] == (int16_t)args[2]) { - tcg_out_insn(s, RI, MGHI, args[0], args[2]); - } else { - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); - } - } else { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); - } - break; - - case INDEX_op_div2_i64: - /* ??? We get an unnecessary sign-extension of the dividend - into R3 with this definition, but as we do in fact always - produce both quotient and remainder using INDEX_op_div_i64 - instead requires jumping through even more hoops. */ - tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); - break; - case INDEX_op_divu2_i64: - tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); - break; - case INDEX_op_mulu2_i64: - tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); - break; - - case INDEX_op_shl_i64: - op = RSY_SLLG; - do_shift64: - if (const_args[2]) { - tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); - } else { - tcg_out_sh64(s, op, args[0], args[1], args[2], 0); - } - break; - case INDEX_op_shr_i64: - op = RSY_SRLG; - goto do_shift64; - case INDEX_op_sar_i64: - op = RSY_SRAG; - goto do_shift64; - - case INDEX_op_rotl_i64: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, args[2]); - } else { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); - } - break; - case INDEX_op_rotr_i64: - if (const_args[2]) { - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], - TCG_REG_NONE, (64 - args[2]) & 63); - } else { - /* We can use the smaller 32-bit negate because only the - low 6 bits are examined for the rotate. */ - tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); - tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); - } - break; - - case INDEX_op_ext8s_i64: - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); - break; - case INDEX_op_ext16s_i64: - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); - break; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tgen_ext32s(s, args[0], args[1]); - break; - case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); - break; - case INDEX_op_ext16u_i64: - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tgen_ext32u(s, args[0], args[1]); - break; - - case INDEX_op_add2_i64: - if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); - } else { - tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); - } - } else { - tcg_out_insn(s, RRE, ALGR, args[0], args[4]); - } - tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); - break; - case INDEX_op_sub2_i64: - if (const_args[4]) { - if ((int64_t)args[4] >= 0) { - tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); - } else { - tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); - } - } else { - tcg_out_insn(s, RRE, SLGR, args[0], args[4]); - } - tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); - break; - - case INDEX_op_brcond_i64: - tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], - args[1], const_args[1], arg_label(args[3])); - break; - case INDEX_op_setcond_i64: - tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], - args[2], const_args[2]); - break; - case INDEX_op_movcond_i64: - tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); - break; - - OP_32_64(deposit): - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[1]) { - tgen_deposit(s, a0, a2, args[3], args[4], 1); - } else { - /* Since we can't support "0Z" as a constraint, we allow a1 in - any register. Fix things up as if a matching constraint. */ - if (a0 != a1) { - TCGType type = (opc == INDEX_op_deposit_i64); - if (a0 == a2) { - tcg_out_mov(s, type, TCG_TMP0, a2); - a2 = TCG_TMP0; - } - tcg_out_mov(s, type, a0, a1); - } - tgen_deposit(s, a0, a2, args[3], args[4], 0); - } - break; - - OP_32_64(extract): - tgen_extract(s, args[0], args[1], args[2], args[3]); - break; - - case INDEX_op_clz_i64: - tgen_clz(s, args[0], args[1], args[2], const_args[2]); - break; - - case INDEX_op_mb: - /* The host memory model is quite strong, we simply need to - serialize the instruction stream. */ - if (args[0] & TCG_MO_ST_LD) { - tcg_out_insn(s, RR, BCR, - s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); - } - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; - static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; - static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef a2_r - = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return &r_r; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - return &r_r_ri; - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - case INDEX_op_and_i32: - case INDEX_op_and_i64: - case INDEX_op_or_i32: - case INDEX_op_or_i64: - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - - case INDEX_op_mul_i32: - /* If we have the general-instruction-extensions, then we have - MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we - have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); - case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); - - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; - - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return &r_ri; - - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: - case INDEX_op_neg_i32: - case INDEX_op_neg_i64: - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - case INDEX_op_extract_i32: - case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; - - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - return &r_L; - case INDEX_op_qemu_st_i64: - case INDEX_op_qemu_st_i32: - return &L_L; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "rZ", "r" } }; - return &dep; - } - case INDEX_op_movcond_i32: - case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); - } - case INDEX_op_div2_i32: - case INDEX_op_div2_i64: - case INDEX_op_divu2_i32: - case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "b", "a", "0", "1", "r" } }; - return &div2; - } - case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "b", "a", "0", "r" } }; - return &mul2; - } - - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); - case INDEX_op_add2_i64: - case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); - - default: - break; - } - return NULL; -} - -static void query_s390_facilities(void) -{ - unsigned long hwcap = qemu_getauxval(AT_HWCAP); - - /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this - is present on all 64-bit systems, but let's check for it anyway. */ - if (hwcap & HWCAP_S390_STFLE) { - register int r0 __asm__("0"); - register void *r1 __asm__("1"); - - /* stfle 0(%r1) */ - r1 = &s390_facilities; - asm volatile(".word 0xb2b0,0x1000" - : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); - } -} - -static void tcg_target_init(TCGContext *s) -{ - query_s390_facilities(); - - tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; - tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; - - tcg_target_call_clobber_regs = 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); - /* The r6 register is technically call-saved, but it's also a parameter - register, so it can get killed by setup for the qemu_st helper. */ - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); - /* The return register can be considered call-clobbered. */ - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); - /* XXX many insns can't be used with R0, so we better avoid it for now */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - if (USE_REG_TB) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); - } -} - -#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ - + TCG_STATIC_CALL_ARGS_SIZE \ - + CPU_TEMP_BUF_NLONGS * sizeof(long))) - -static void tcg_target_qemu_prologue(TCGContext *s) -{ - /* stmg %r6,%r15,48(%r15) (save registers) */ - tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); - - /* aghi %r15,-frame_size */ - tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); - - tcg_set_frame(s, TCG_REG_CALL_STACK, - TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - -#ifndef CONFIG_SOFTMMU - if (guest_base >= 0x80000) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); - } -#endif - - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, - tcg_target_call_iarg_regs[1]); - } - - /* br %r3 (go to TB) */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); - - /* - * Return path for goto_ptr. Set return value to 0, a-la exit_tb, - * and fall through to the rest of the epilogue. - */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); - - /* TB epilogue */ - tb_ret_addr = s->code_ptr; - - /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ - tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, - FRAME_SIZE + 48); - - /* br %r14 (return) */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - memset(p, 0x07, count * sizeof(tcg_insn_unit)); -} - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[4]; - uint8_t fde_reg_ofs[18]; -} DebugFrame; - -/* We're expecting a 2 byte uleb128 encoded value. */ -QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); - -#define ELF_HOST_MACHINE EM_S390 - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = 8, /* sleb128 8 */ - .h.cie.return_column = TCG_REG_R14, - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { - 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ - (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ - (FRAME_SIZE >> 7) - }, - .fde_reg_ofs = { - 0x86, 6, /* DW_CFA_offset, %r6, 48 */ - 0x87, 7, /* DW_CFA_offset, %r7, 56 */ - 0x88, 8, /* DW_CFA_offset, %r8, 64 */ - 0x89, 9, /* DW_CFA_offset, %r92, 72 */ - 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ - 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ - 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ - 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ - 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ - } -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc new file mode 100644 index 0000000000..0f1d91fc21 --- /dev/null +++ b/tcg/sparc/tcg-target.c.inc @@ -0,0 +1,1868 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "../tcg-pool.c.inc" + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "%g0", + "%g1", + "%g2", + "%g3", + "%g4", + "%g5", + "%g6", + "%g7", + "%o0", + "%o1", + "%o2", + "%o3", + "%o4", + "%o5", + "%o6", + "%o7", + "%l0", + "%l1", + "%l2", + "%l3", + "%l4", + "%l5", + "%l6", + "%l7", + "%i0", + "%i1", + "%i2", + "%i3", + "%i4", + "%i5", + "%i6", + "%i7", +}; +#endif + +#ifdef __arch64__ +# define SPARC64 1 +#else +# define SPARC64 0 +#endif + +/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o + registers. These are saved manually by the kernel in full 64-bit + slots. The %i and %l registers are saved by the register window + mechanism, which only allocates space for 32 bits. Given that this + window spill/fill can happen on any signal, we must consider the + high bits of the %i and %l registers garbage at all times. */ +#if SPARC64 +# define ALL_64 0xffffffffu +#else +# define ALL_64 0xffffu +#endif + +/* Define some temporary registers. T2 is used for constant generation. */ +#define TCG_REG_T1 TCG_REG_G1 +#define TCG_REG_T2 TCG_REG_O7 + +#ifndef CONFIG_SOFTMMU +# define TCG_GUEST_BASE_REG TCG_REG_I5 +#endif + +#define TCG_REG_TB TCG_REG_I1 +#define USE_REG_TB (sizeof(void *) > 4) + +static const int tcg_target_reg_alloc_order[] = { + TCG_REG_L0, + TCG_REG_L1, + TCG_REG_L2, + TCG_REG_L3, + TCG_REG_L4, + TCG_REG_L5, + TCG_REG_L6, + TCG_REG_L7, + + TCG_REG_I0, + TCG_REG_I1, + TCG_REG_I2, + TCG_REG_I3, + TCG_REG_I4, + TCG_REG_I5, + + TCG_REG_G2, + TCG_REG_G3, + TCG_REG_G4, + TCG_REG_G5, + + TCG_REG_O0, + TCG_REG_O1, + TCG_REG_O2, + TCG_REG_O3, + TCG_REG_O4, + TCG_REG_O5, +}; + +static const int tcg_target_call_iarg_regs[6] = { + TCG_REG_O0, + TCG_REG_O1, + TCG_REG_O2, + TCG_REG_O3, + TCG_REG_O4, + TCG_REG_O5, +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_O0, + TCG_REG_O1, + TCG_REG_O2, + TCG_REG_O3, +}; + +#define INSN_OP(x) ((x) << 30) +#define INSN_OP2(x) ((x) << 22) +#define INSN_OP3(x) ((x) << 19) +#define INSN_OPF(x) ((x) << 5) +#define INSN_RD(x) ((x) << 25) +#define INSN_RS1(x) ((x) << 14) +#define INSN_RS2(x) (x) +#define INSN_ASI(x) ((x) << 5) + +#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) +#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) +#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) +#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) +#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) +#define INSN_COND(x) ((x) << 25) + +#define COND_N 0x0 +#define COND_E 0x1 +#define COND_LE 0x2 +#define COND_L 0x3 +#define COND_LEU 0x4 +#define COND_CS 0x5 +#define COND_NEG 0x6 +#define COND_VS 0x7 +#define COND_A 0x8 +#define COND_NE 0x9 +#define COND_G 0xa +#define COND_GE 0xb +#define COND_GU 0xc +#define COND_CC 0xd +#define COND_POS 0xe +#define COND_VC 0xf +#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) + +#define RCOND_Z 1 +#define RCOND_LEZ 2 +#define RCOND_LZ 3 +#define RCOND_NZ 5 +#define RCOND_GZ 6 +#define RCOND_GEZ 7 + +#define MOVCC_ICC (1 << 18) +#define MOVCC_XCC (1 << 18 | 1 << 12) + +#define BPCC_ICC 0 +#define BPCC_XCC (2 << 20) +#define BPCC_PT (1 << 19) +#define BPCC_PN 0 +#define BPCC_A (1 << 29) + +#define BPR_PT BPCC_PT + +#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) +#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) +#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) +#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) +#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) +#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) +#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) +#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) +#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) +#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) +#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) +#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) +#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) +#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) +#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) +#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) +#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) +#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) +#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) +#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) +#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) + +#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) +#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) + +#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) +#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) +#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) + +#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) +#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) +#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) + +#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) +#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) +#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) +#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) +#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) +#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) +#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) +#define CALL INSN_OP(1) +#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) +#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) +#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) +#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) +#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) +#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) +#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) +#define STB (INSN_OP(3) | INSN_OP3(0x05)) +#define STH (INSN_OP(3) | INSN_OP3(0x06)) +#define STW (INSN_OP(3) | INSN_OP3(0x04)) +#define STX (INSN_OP(3) | INSN_OP3(0x0e)) +#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) +#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) +#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) +#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) +#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) +#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) +#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) +#define STBA (INSN_OP(3) | INSN_OP3(0x15)) +#define STHA (INSN_OP(3) | INSN_OP3(0x16)) +#define STWA (INSN_OP(3) | INSN_OP3(0x14)) +#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) + +#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) + +#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) + +#ifndef ASI_PRIMARY_LITTLE +#define ASI_PRIMARY_LITTLE 0x88 +#endif + +#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) + +#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) +#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) + +#ifndef use_vis3_instructions +bool use_vis3_instructions; +#endif + +static inline int check_fit_i64(int64_t val, unsigned int bits) +{ + return val == sextract64(val, 0, bits); +} + +static inline int check_fit_i32(int32_t val, unsigned int bits) +{ + return val == sextract32(val, 0, bits); +} + +#define check_fit_tl check_fit_i64 +#if SPARC64 +# define check_fit_ptr check_fit_i64 +#else +# define check_fit_ptr check_fit_i32 +#endif + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + uint32_t insn = *code_ptr; + intptr_t pcrel; + + value += addend; + pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + + switch (type) { + case R_SPARC_WDISP16: + assert(check_fit_ptr(pcrel >> 2, 16)); + insn &= ~INSN_OFF16(-1); + insn |= INSN_OFF16(pcrel); + break; + case R_SPARC_WDISP19: + assert(check_fit_ptr(pcrel >> 2, 19)); + insn &= ~INSN_OFF19(-1); + insn |= INSN_OFF19(pcrel); + break; + default: + g_assert_not_reached(); + } + + *code_ptr = insn; + return true; +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + break; + case 'R': + ct->ct |= TCG_CT_REG; + ct->u.regs = ALL_64; + break; + case 'A': /* qemu_ld/st address constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; + reserve_helpers: + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); + break; + case 's': /* qemu_st data 32-bit constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + goto reserve_helpers; + case 'S': /* qemu_st data 64-bit constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = ALL_64; + goto reserve_helpers; + case 'I': + ct->ct |= TCG_CT_CONST_S11; + break; + case 'J': + ct->ct |= TCG_CT_CONST_S13; + break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static inline int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + + if (ct & TCG_CT_CONST) { + return 1; + } + + if (type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { + return 1; + } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { + return 1; + } else { + return 0; + } +} + +static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, + TCGReg rs2, int op) +{ + tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); +} + +static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, + int32_t offset, int op) +{ + tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); +} + +static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, + int32_t val2, int val2const, int op) +{ + tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) + | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); +} + +static inline bool tcg_out_mov(TCGContext *s, TCGType type, + TCGReg ret, TCGReg arg) +{ + if (ret != arg) { + tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); + } + return true; +} + +static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) +{ + tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); +} + +static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) +{ + tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) +{ + tcg_target_long hi, lo = (int32_t)arg; + tcg_target_long test, lsb; + + /* Make sure we test 32-bit constants for imm13 properly. */ + if (type == TCG_TYPE_I32) { + arg = lo; + } + + /* A 13-bit constant sign-extended to 64-bits. */ + if (check_fit_tl(arg, 13)) { + tcg_out_movi_imm13(s, ret, arg); + return; + } + + /* A 13-bit constant relative to the TB. */ + if (!in_prologue && USE_REG_TB) { + test = arg - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(test, 13)) { + tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); + return; + } + } + + /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ + if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { + tcg_out_sethi(s, ret, arg); + if (arg & 0x3ff) { + tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); + } + return; + } + + /* A 32-bit constant sign-extended to 64-bits. */ + if (arg == lo) { + tcg_out_sethi(s, ret, ~arg); + tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); + return; + } + + /* A 21-bit constant, shifted. */ + lsb = ctz64(arg); + test = (tcg_target_long)arg >> lsb; + if (check_fit_tl(test, 13)) { + tcg_out_movi_imm13(s, ret, test); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; + } else if (lsb > 10 && test == extract64(test, 0, 21)) { + tcg_out_sethi(s, ret, test << 10); + tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); + return; + } + + /* A 64-bit constant decomposed into 2 32-bit pieces. */ + if (check_fit_i32(lo, 13)) { + hi = (arg - lo) >> 32; + tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); + tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); + } else { + hi = arg >> 32; + tcg_out_movi(s, TCG_TYPE_I32, ret, hi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); + tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); + tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); + } +} + +static inline void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_out_movi_int(s, type, ret, arg, false); +} + +static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, + TCGReg a2, int op) +{ + tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); +} + +static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, + intptr_t offset, int op) +{ + if (check_fit_ptr(offset, 13)) { + tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | + INSN_IMM13(offset)); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); + tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); + } +} + +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) +{ + tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); +} + +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (val == 0) { + tcg_out_st(s, type, TCG_REG_G0, base, ofs); + return true; + } + return false; +} + +static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) +{ + intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; + if (USE_REG_TB && check_fit_ptr(diff, 13)) { + tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); + return; + } + tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); + tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); +} + +static inline void tcg_out_sety(TCGContext *s, TCGReg rs) +{ + tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); +} + +static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) +{ + tcg_out32(s, RDY | INSN_RD(rd)); +} + +static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, + int32_t val2, int val2const, int uns) +{ + /* Load Y with the sign/zero extension of RS1 to 64-bits. */ + if (uns) { + tcg_out_sety(s, TCG_REG_G0); + } else { + tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); + tcg_out_sety(s, TCG_REG_T1); + } + + tcg_out_arithc(s, rd, rs1, val2, val2const, + uns ? ARITH_UDIV : ARITH_SDIV); +} + +static inline void tcg_out_nop(TCGContext *s) +{ + tcg_out32(s, NOP); +} + +static const uint8_t tcg_cond_to_bcond[] = { + [TCG_COND_EQ] = COND_E, + [TCG_COND_NE] = COND_NE, + [TCG_COND_LT] = COND_L, + [TCG_COND_GE] = COND_GE, + [TCG_COND_LE] = COND_LE, + [TCG_COND_GT] = COND_G, + [TCG_COND_LTU] = COND_CS, + [TCG_COND_GEU] = COND_CC, + [TCG_COND_LEU] = COND_LEU, + [TCG_COND_GTU] = COND_GU, +}; + +static const uint8_t tcg_cond_to_rcond[] = { + [TCG_COND_EQ] = RCOND_Z, + [TCG_COND_NE] = RCOND_NZ, + [TCG_COND_LT] = RCOND_LZ, + [TCG_COND_GT] = RCOND_GZ, + [TCG_COND_LE] = RCOND_LEZ, + [TCG_COND_GE] = RCOND_GEZ +}; + +static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) +{ + tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); +} + +static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) +{ + int off19 = 0; + + if (l->has_value) { + off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); + } else { + tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); + } + tcg_out_bpcc0(s, scond, flags, off19); +} + +static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) +{ + tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); +} + +static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, + int32_t arg2, int const_arg2, TCGLabel *l) +{ + tcg_out_cmp(s, arg1, arg2, const_arg2); + tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); + tcg_out_nop(s); +} + +static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, + int32_t v1, int v1const) +{ + tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) + | INSN_RS1(tcg_cond_to_bcond[cond]) + | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); +} + +static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg c1, int32_t c2, int c2const, + int32_t v1, int v1const) +{ + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); +} + +static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, + int32_t arg2, int const_arg2, TCGLabel *l) +{ + /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ + if (arg2 == 0 && !is_unsigned_cond(cond)) { + int off16 = 0; + + if (l->has_value) { + off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); + } else { + tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); + } + tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) + | INSN_COND(tcg_cond_to_rcond[cond]) | off16); + } else { + tcg_out_cmp(s, arg1, arg2, const_arg2); + tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); + } + tcg_out_nop(s); +} + +static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, + int32_t v1, int v1const) +{ + tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) + | (tcg_cond_to_rcond[cond] << 10) + | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); +} + +static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg c1, int32_t c2, int c2const, + int32_t v1, int v1const) +{ + /* For 64-bit signed comparisons vs zero, we can avoid the compare. + Note that the immediate range is one bit smaller, so we must check + for that as well. */ + if (c2 == 0 && !is_unsigned_cond(cond) + && (!v1const || check_fit_i32(v1, 10))) { + tcg_out_movr(s, cond, ret, c1, v1, v1const); + } else { + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); + } +} + +static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg c1, int32_t c2, int c2const) +{ + /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ + switch (cond) { + case TCG_COND_LTU: + case TCG_COND_GEU: + /* The result of the comparison is in the carry bit. */ + break; + + case TCG_COND_EQ: + case TCG_COND_NE: + /* For equality, we can transform to inequality vs zero. */ + if (c2 != 0) { + tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); + c2 = TCG_REG_T1; + } else { + c2 = c1; + } + c1 = TCG_REG_G0, c2const = 0; + cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); + break; + + case TCG_COND_GTU: + case TCG_COND_LEU: + /* If we don't need to load a constant into a register, we can + swap the operands on GTU/LEU. There's no benefit to loading + the constant into a temporary register. */ + if (!c2const || c2 == 0) { + TCGReg t = c1; + c1 = c2; + c2 = t; + c2const = 0; + cond = tcg_swap_cond(cond); + break; + } + /* FALLTHRU */ + + default: + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movi_imm13(s, ret, 0); + tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); + return; + } + + tcg_out_cmp(s, c1, c2, c2const); + if (cond == TCG_COND_LTU) { + tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); + } else { + tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); + } +} + +static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg c1, int32_t c2, int c2const) +{ + if (use_vis3_instructions) { + switch (cond) { + case TCG_COND_NE: + if (c2 != 0) { + break; + } + c2 = c1, c2const = 0, c1 = TCG_REG_G0; + /* FALLTHRU */ + case TCG_COND_LTU: + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); + return; + default: + break; + } + } + + /* For 64-bit signed comparisons vs zero, we can avoid the compare + if the input does not overlap the output. */ + if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { + tcg_out_movi_imm13(s, ret, 0); + tcg_out_movr(s, cond, ret, c1, 1, 1); + } else { + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movi_imm13(s, ret, 0); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); + } +} + +static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, + TCGReg al, TCGReg ah, int32_t bl, int blconst, + int32_t bh, int bhconst, int opl, int oph) +{ + TCGReg tmp = TCG_REG_T1; + + /* Note that the low parts are fully consumed before tmp is set. */ + if (rl != ah && (bhconst || rl != bh)) { + tmp = rl; + } + + tcg_out_arithc(s, tmp, al, bl, blconst, opl); + tcg_out_arithc(s, rh, ah, bh, bhconst, oph); + tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); +} + +static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, + TCGReg al, TCGReg ah, int32_t bl, int blconst, + int32_t bh, int bhconst, bool is_sub) +{ + TCGReg tmp = TCG_REG_T1; + + /* Note that the low parts are fully consumed before tmp is set. */ + if (rl != ah && (bhconst || rl != bh)) { + tmp = rl; + } + + tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); + + if (use_vis3_instructions && !is_sub) { + /* Note that ADDXC doesn't accept immediates. */ + if (bhconst && bh != 0) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh); + bh = TCG_REG_T2; + } + tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); + } else if (bh == TCG_REG_G0) { + /* If we have a zero, we can perform the operation in two insns, + with the arithmetic first, and a conditional move into place. */ + if (rh == ah) { + tcg_out_arithi(s, TCG_REG_T2, ah, 1, + is_sub ? ARITH_SUB : ARITH_ADD); + tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); + } else { + tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); + tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); + } + } else { + /* Otherwise adjust BH as if there is carry into T2 ... */ + if (bhconst) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1)); + } else { + tcg_out_arithi(s, TCG_REG_T2, bh, 1, + is_sub ? ARITH_SUB : ARITH_ADD); + } + /* ... smoosh T2 back to original BH if carry is clear ... */ + tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); + /* ... and finally perform the arithmetic with the new operand. */ + tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); + } + + tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); +} + +static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, + bool in_prologue) +{ + ptrdiff_t disp = tcg_pcrel_diff(s, dest); + + if (disp == (int32_t)disp) { + tcg_out32(s, CALL | (uint32_t)disp >> 2); + } else { + uintptr_t desti = (uintptr_t)dest; + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue); + tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); + } +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +{ + tcg_out_call_nodelay(s, dest, false); + tcg_out_nop(s); +} + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ + tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); +} + +#ifdef CONFIG_SOFTMMU +static tcg_insn_unit *qemu_ld_trampoline[16]; +static tcg_insn_unit *qemu_st_trampoline[16]; + +static void emit_extend(TCGContext *s, TCGReg r, int op) +{ + /* Emit zero extend of 8, 16 or 32 bit data as + * required by the MO_* value op; do nothing for 64 bit. + */ + switch (op & MO_SIZE) { + case MO_8: + tcg_out_arithi(s, r, r, 0xff, ARITH_AND); + break; + case MO_16: + tcg_out_arithi(s, r, r, 16, SHIFT_SLL); + tcg_out_arithi(s, r, r, 16, SHIFT_SRL); + break; + case MO_32: + if (SPARC64) { + tcg_out_arith(s, r, r, 0, SHIFT_SRL); + } + break; + case MO_64: + break; + } +} + +static void build_trampolines(TCGContext *s) +{ + static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, + [MO_BEQ] = helper_be_ldq_mmu, + }; + static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, + }; + + int i; + TCGReg ra; + + for (i = 0; i < 16; ++i) { + if (qemu_ld_helpers[i] == NULL) { + continue; + } + + /* May as well align the trampoline. */ + while ((uintptr_t)s->code_ptr & 15) { + tcg_out_nop(s); + } + qemu_ld_trampoline[i] = s->code_ptr; + + if (SPARC64 || TARGET_LONG_BITS == 32) { + ra = TCG_REG_O3; + } else { + /* Install the high part of the address. */ + tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); + ra = TCG_REG_O4; + } + + /* Set the retaddr operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + /* Set the env operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ + tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + } + + for (i = 0; i < 16; ++i) { + if (qemu_st_helpers[i] == NULL) { + continue; + } + + /* May as well align the trampoline. */ + while ((uintptr_t)s->code_ptr & 15) { + tcg_out_nop(s); + } + qemu_st_trampoline[i] = s->code_ptr; + + if (SPARC64) { + emit_extend(s, TCG_REG_O2, i); + ra = TCG_REG_O4; + } else { + ra = TCG_REG_O1; + if (TARGET_LONG_BITS == 64) { + /* Install the high part of the address. */ + tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); + ra += 2; + } else { + ra += 1; + } + if ((i & MO_SIZE) == MO_64) { + /* Install the high part of the data. */ + tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); + ra += 2; + } else { + emit_extend(s, ra, i); + ra += 1; + } + /* Skip the oi argument. */ + ra += 1; + } + + /* Set the retaddr operand. */ + if (ra >= TCG_REG_O6) { + tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET); + ra = TCG_REG_G1; + } + tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + /* Set the env operand. */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); + /* Tail call. */ + tcg_out_call_nodelay(s, qemu_st_helpers[i], true); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); + } +} +#endif + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int tmp_buf_size, frame_size; + + /* The TCG temp buffer is at the top of the frame, immediately + below the frame pointer. */ + tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); + tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, + tmp_buf_size); + + /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is + otherwise the minimal frame usable by callees. */ + frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; + frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; + frame_size += TCG_TARGET_STACK_ALIGN - 1; + frame_size &= -TCG_TARGET_STACK_ALIGN; + tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | + INSN_IMM13(-frame_size)); + +#ifndef CONFIG_SOFTMMU + if (guest_base != 0) { + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } +#endif + + /* We choose TCG_REG_TB such that no move is required. */ + if (USE_REG_TB) { + QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } + + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); + /* delay slot */ + tcg_out_nop(s); + + /* Epilogue for goto_ptr. */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + /* delay slot */ + tcg_out_movi_imm13(s, TCG_REG_O0, 0); + +#ifdef CONFIG_SOFTMMU + build_trampolines(s); +#endif +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + +#if defined(CONFIG_SOFTMMU) + +/* We expect to use a 13-bit negative offset from ENV. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + +/* Perform the TLB load and compare. + + Inputs: + ADDRLO and ADDRHI contain the possible two parts of the address. + + MEM_INDEX and S_BITS are the memory context and log2 size of the load. + + WHICH is the offset into the CPUTLBEntry structure of the slot to read. + This should be offsetof addr_read or addr_write. + + The result of the TLB comparison is in %[ix]cc. The sanitized address + is in the returned register, maybe %o0. The TLB addend is in %o1. */ + +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, + MemOp opc, int which) +{ + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); + const TCGReg r0 = TCG_REG_O0; + const TCGReg r1 = TCG_REG_O1; + const TCGReg r2 = TCG_REG_O2; + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + tcg_target_long compare_mask; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); + + /* Extract the page index, shifted into place for tlb index. */ + tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, + SHIFT_SRL); + tcg_out_arith(s, r2, r2, r0, ARITH_AND); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ + tcg_out_arith(s, r2, r2, r1, ARITH_ADD); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which); + tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend)); + + /* Mask out the page offset, except for the required alignment. + We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); + if (check_fit_tl(compare_mask, 13)) { + tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND); + } else { + tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask); + tcg_out_arith(s, r2, addr, r2, ARITH_AND); + } + tcg_out_cmp(s, r0, r2, 0); + + /* If the guest address must be zero-extended, do so now. */ + if (SPARC64 && TARGET_LONG_BITS == 32) { + tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); + return r0; + } + return addr; +} +#endif /* CONFIG_SOFTMMU */ + +static const int qemu_ld_opc[16] = { + [MO_UB] = LDUB, + [MO_SB] = LDSB, + + [MO_BEUW] = LDUH, + [MO_BESW] = LDSH, + [MO_BEUL] = LDUW, + [MO_BESL] = LDSW, + [MO_BEQ] = LDX, + + [MO_LEUW] = LDUH_LE, + [MO_LESW] = LDSH_LE, + [MO_LEUL] = LDUW_LE, + [MO_LESL] = LDSW_LE, + [MO_LEQ] = LDX_LE, +}; + +static const int qemu_st_opc[16] = { + [MO_UB] = STB, + + [MO_BEUW] = STH, + [MO_BEUL] = STW, + [MO_BEQ] = STX, + + [MO_LEUW] = STH_LE, + [MO_LEUL] = STW_LE, + [MO_LEQ] = STX_LE, +}; + +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, + TCGMemOpIdx oi, bool is_64) +{ + MemOp memop = get_memop(oi); +#ifdef CONFIG_SOFTMMU + unsigned memi = get_mmuidx(oi); + TCGReg addrz, param; + tcg_insn_unit *func; + tcg_insn_unit *label_ptr; + + addrz = tcg_out_tlb_load(s, addr, memi, memop, + offsetof(CPUTLBEntry, addr_read)); + + /* The fast path is exactly one insn. Thus we can perform the + entire TLB Hit in the (annulled) delay slot of the branch + over the TLB Miss case. */ + + /* beq,a,pt %[xi]cc, label0 */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT + | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, + qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + + /* TLB Miss. */ + + param = TCG_REG_O1; + if (!SPARC64 && TARGET_LONG_BITS == 64) { + /* Skip the high-part; we'll perform the extract in the trampoline. */ + param++; + } + tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); + + /* We use the helpers to extend SB and SW data, leaving the case + of SL needing explicit extending below. */ + if ((memop & MO_SSIZE) == MO_SL) { + func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)]; + } else { + func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; + } + tcg_debug_assert(func != NULL); + tcg_out_call_nodelay(s, func, false); + /* delay slot */ + tcg_out_movi(s, TCG_TYPE_I32, param, oi); + + /* Recall that all of the helpers return 64-bit results. + Which complicates things for sparcv8plus. */ + if (SPARC64) { + /* We let the helper sign-extend SB and SW, but leave SL for here. */ + if (is_64 && (memop & MO_SSIZE) == MO_SL) { + tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); + } else { + tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); + } + } else { + if ((memop & MO_SIZE) == MO_64) { + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); + tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); + tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); + } else if (is_64) { + /* Re-extend from 32-bit rather than reassembling when we + know the high register must be an extension. */ + tcg_out_arithi(s, data, TCG_REG_O1, 0, + memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); + } else { + tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); + } + } + + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); +#else + if (SPARC64 && TARGET_LONG_BITS == 32) { + tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); + addr = TCG_REG_T1; + } + tcg_out_ldst_rr(s, data, addr, + (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); +#endif /* CONFIG_SOFTMMU */ +} + +static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, + TCGMemOpIdx oi) +{ + MemOp memop = get_memop(oi); +#ifdef CONFIG_SOFTMMU + unsigned memi = get_mmuidx(oi); + TCGReg addrz, param; + tcg_insn_unit *func; + tcg_insn_unit *label_ptr; + + addrz = tcg_out_tlb_load(s, addr, memi, memop, + offsetof(CPUTLBEntry, addr_write)); + + /* The fast path is exactly one insn. Thus we can perform the entire + TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */ + /* beq,a,pt %[xi]cc, label0 */ + label_ptr = s->code_ptr; + tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT + | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); + /* delay slot */ + tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, + qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + + /* TLB Miss. */ + + param = TCG_REG_O1; + if (!SPARC64 && TARGET_LONG_BITS == 64) { + /* Skip the high-part; we'll perform the extract in the trampoline. */ + param++; + } + tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); + if (!SPARC64 && (memop & MO_SIZE) == MO_64) { + /* Skip the high-part; we'll perform the extract in the trampoline. */ + param++; + } + tcg_out_mov(s, TCG_TYPE_REG, param++, data); + + func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; + tcg_debug_assert(func != NULL); + tcg_out_call_nodelay(s, func, false); + /* delay slot */ + tcg_out_movi(s, TCG_TYPE_I32, param, oi); + + *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); +#else + if (SPARC64 && TARGET_LONG_BITS == 32) { + tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); + addr = TCG_REG_T1; + } + tcg_out_ldst_rr(s, data, addr, + (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), + qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); +#endif /* CONFIG_SOFTMMU */ +} + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) +{ + TCGArg a0, a1, a2; + int c, c2; + + /* Hoist the loads of the most common arguments. */ + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c2 = const_args[2]; + + switch (opc) { + case INDEX_op_exit_tb: + if (check_fit_ptr(a0, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_movi_imm13(s, TCG_REG_O0, a0); + break; + } else if (USE_REG_TB) { + intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(tb_diff, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + /* Note that TCG_REG_TB has been unwound to O1. */ + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); + break; + } + } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* direct jump method */ + if (USE_REG_TB) { + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { + tcg_out_nop(s); + } + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); + } else { + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out32(s, CALL); + tcg_out_nop(s); + } + } else { + /* indirect jump method */ + tcg_out_ld_ptr(s, TCG_REG_TB, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); + tcg_out_nop(s); + } + set_jmp_reset_offset(s, a0); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + c = -tcg_current_code_size(s); + if (check_fit_i32(c, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, + TCG_REG_T1, ARITH_ADD); + } + } + break; + case INDEX_op_goto_ptr: + tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); + if (USE_REG_TB) { + tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); + } else { + tcg_out_nop(s); + } + break; + case INDEX_op_br: + tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); + tcg_out_nop(s); + break; + +#define OP_32_64(x) \ + glue(glue(case INDEX_op_, x), _i32): \ + glue(glue(case INDEX_op_, x), _i64) + + OP_32_64(ld8u): + tcg_out_ldst(s, a0, a1, a2, LDUB); + break; + OP_32_64(ld8s): + tcg_out_ldst(s, a0, a1, a2, LDSB); + break; + OP_32_64(ld16u): + tcg_out_ldst(s, a0, a1, a2, LDUH); + break; + OP_32_64(ld16s): + tcg_out_ldst(s, a0, a1, a2, LDSH); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + tcg_out_ldst(s, a0, a1, a2, LDUW); + break; + OP_32_64(st8): + tcg_out_ldst(s, a0, a1, a2, STB); + break; + OP_32_64(st16): + tcg_out_ldst(s, a0, a1, a2, STH); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_ldst(s, a0, a1, a2, STW); + break; + OP_32_64(add): + c = ARITH_ADD; + goto gen_arith; + OP_32_64(sub): + c = ARITH_SUB; + goto gen_arith; + OP_32_64(and): + c = ARITH_AND; + goto gen_arith; + OP_32_64(andc): + c = ARITH_ANDN; + goto gen_arith; + OP_32_64(or): + c = ARITH_OR; + goto gen_arith; + OP_32_64(orc): + c = ARITH_ORN; + goto gen_arith; + OP_32_64(xor): + c = ARITH_XOR; + goto gen_arith; + case INDEX_op_shl_i32: + c = SHIFT_SLL; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); + break; + case INDEX_op_shr_i32: + c = SHIFT_SRL; + goto do_shift32; + case INDEX_op_sar_i32: + c = SHIFT_SRA; + goto do_shift32; + case INDEX_op_mul_i32: + c = ARITH_UMUL; + goto gen_arith; + + OP_32_64(neg): + c = ARITH_SUB; + goto gen_arith1; + OP_32_64(not): + c = ARITH_ORN; + goto gen_arith1; + + case INDEX_op_div_i32: + tcg_out_div32(s, a0, a1, a2, c2, 0); + break; + case INDEX_op_divu_i32: + tcg_out_div32(s, a0, a1, a2, c2, 1); + break; + + case INDEX_op_brcond_i32: + tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); + break; + case INDEX_op_setcond_i32: + tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); + break; + case INDEX_op_movcond_i32: + tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); + break; + + case INDEX_op_add2_i32: + tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], + args[4], const_args[4], args[5], const_args[5], + ARITH_ADDCC, ARITH_ADDC); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], + args[4], const_args[4], args[5], const_args[5], + ARITH_SUBCC, ARITH_SUBC); + break; + case INDEX_op_mulu2_i32: + c = ARITH_UMUL; + goto do_mul2; + case INDEX_op_muls2_i32: + c = ARITH_SMUL; + do_mul2: + /* The 32-bit multiply insns produce a full 64-bit result. If the + destination register can hold it, we can avoid the slower RDY. */ + tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); + if (SPARC64 || a0 <= TCG_REG_O7) { + tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); + } else { + tcg_out_rdy(s, a1); + } + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, a0, a1, a2, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, a0, a1, a2, true); + break; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, a0, a1, a2); + break; + + case INDEX_op_ld32s_i64: + tcg_out_ldst(s, a0, a1, a2, LDSW); + break; + case INDEX_op_ld_i64: + tcg_out_ldst(s, a0, a1, a2, LDX); + break; + case INDEX_op_st_i64: + tcg_out_ldst(s, a0, a1, a2, STX); + break; + case INDEX_op_shl_i64: + c = SHIFT_SLLX; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); + break; + case INDEX_op_shr_i64: + c = SHIFT_SRLX; + goto do_shift64; + case INDEX_op_sar_i64: + c = SHIFT_SRAX; + goto do_shift64; + case INDEX_op_mul_i64: + c = ARITH_MULX; + goto gen_arith; + case INDEX_op_div_i64: + c = ARITH_SDIVX; + goto gen_arith; + case INDEX_op_divu_i64: + c = ARITH_UDIVX; + goto gen_arith; + case INDEX_op_ext_i32_i64: + case INDEX_op_ext32s_i64: + tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA); + break; + case INDEX_op_extu_i32_i64: + case INDEX_op_ext32u_i64: + tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL); + break; + case INDEX_op_extrl_i64_i32: + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + break; + case INDEX_op_extrh_i64_i32: + tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); + break; + + case INDEX_op_brcond_i64: + tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); + break; + case INDEX_op_setcond_i64: + tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); + break; + case INDEX_op_movcond_i64: + tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); + break; + case INDEX_op_add2_i64: + tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], + const_args[4], args[5], const_args[5], false); + break; + case INDEX_op_sub2_i64: + tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], + const_args[4], args[5], const_args[5], true); + break; + case INDEX_op_muluh_i64: + tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); + break; + + gen_arith: + tcg_out_arithc(s, a0, a1, a2, c2, c); + break; + + gen_arith1: + tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } }; + static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } }; + static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } }; + static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } }; + static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } }; + static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; + static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } }; + static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } }; + static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } }; + static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } }; + static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } }; + static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } }; + static const TCGTargetOpDef r_rZ_rJ + = { .args_ct_str = { "r", "rZ", "rJ" } }; + static const TCGTargetOpDef R_RZ_RJ + = { .args_ct_str = { "R", "RZ", "RJ" } }; + static const TCGTargetOpDef r_r_rZ_rJ + = { .args_ct_str = { "r", "r", "rZ", "rJ" } }; + static const TCGTargetOpDef movc_32 + = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } }; + static const TCGTargetOpDef movc_64 + = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } }; + static const TCGTargetOpDef add2_32 + = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; + static const TCGTargetOpDef add2_64 + = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_mul_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_sub_i32: + case INDEX_op_and_i32: + case INDEX_op_andc_i32: + case INDEX_op_or_i32: + case INDEX_op_orc_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_setcond_i32: + return &r_rZ_rJ; + + case INDEX_op_brcond_i32: + return &rZ_rJ; + case INDEX_op_movcond_i32: + return &movc_32; + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return &add2_32; + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i32: + return &r_r_rZ_rJ; + + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + return &R_r; + + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &RZ_r; + + case INDEX_op_add_i64: + case INDEX_op_mul_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_sub_i64: + case INDEX_op_and_i64: + case INDEX_op_andc_i64: + case INDEX_op_or_i64: + case INDEX_op_orc_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_setcond_i64: + return &R_RZ_RJ; + + case INDEX_op_neg_i64: + case INDEX_op_not_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + return &R_R; + + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + return &r_R; + + case INDEX_op_brcond_i64: + return &RZ_RJ; + case INDEX_op_movcond_i64: + return &movc_64; + case INDEX_op_add2_i64: + case INDEX_op_sub2_i64: + return &add2_64; + case INDEX_op_muluh_i64: + return &R_R_R; + + case INDEX_op_qemu_ld_i32: + return &r_A; + case INDEX_op_qemu_ld_i64: + return &R_A; + case INDEX_op_qemu_st_i32: + return &sZ_A; + case INDEX_op_qemu_st_i64: + return &SZ_A; + + default: + return NULL; + } +} + +static void tcg_target_init(TCGContext *s) +{ + /* Only probe for the platform and capabilities if we havn't already + determined maximum values at compile time. */ +#ifndef use_vis3_instructions + { + unsigned long hwcap = qemu_getauxval(AT_HWCAP); + use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; + } +#endif + + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + tcg_target_available_regs[TCG_TYPE_I64] = ALL_64; + + tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ +} + +#if SPARC64 +# define ELF_HOST_MACHINE EM_SPARCV9 +#else +# define ELF_HOST_MACHINE EM_SPARC32PLUS +# define ELF_HOST_FLAGS EF_SPARC_32PLUS +#endif + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; + uint8_t fde_win_save; + uint8_t fde_ret_save[3]; +} DebugFrame; + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = -sizeof(void *) & 0x7f, + .h.cie.return_column = 15, /* o7 */ + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { +#if SPARC64 + 12, 30, /* DW_CFA_def_cfa i6, 2047 */ + (2047 & 0x7f) | 0x80, (2047 >> 7) +#else + 13, 30 /* DW_CFA_def_cfa_register i6 */ +#endif + }, + .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ + .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + intptr_t tb_disp = addr - tc_ptr; + intptr_t br_disp = addr - jmp_addr; + tcg_insn_unit i1, i2; + + /* We can reach the entire address space for ILP32. + For LP64, the code_gen_buffer can't be larger than 2GB. */ + tcg_debug_assert(tb_disp == (int32_t)tb_disp); + tcg_debug_assert(br_disp == (int32_t)br_disp); + + if (!USE_REG_TB) { + atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); + flush_icache_range(jmp_addr, jmp_addr + 4); + return; + } + + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (check_fit_ptr(tb_disp, 13)) { + /* ba,pt %icc, addr */ + i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) + | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); + i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) + | INSN_IMM13(tb_disp)); + } else if (tb_disp >= 0) { + i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10); + i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13(tb_disp & 0x3ff)); + } else { + i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10); + i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); + } + + atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); + flush_icache_range(jmp_addr, jmp_addr + 8); +} diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c deleted file mode 100644 index 65fddb310d..0000000000 --- a/tcg/sparc/tcg-target.inc.c +++ /dev/null @@ -1,1868 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "../tcg-pool.inc.c" - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "%g0", - "%g1", - "%g2", - "%g3", - "%g4", - "%g5", - "%g6", - "%g7", - "%o0", - "%o1", - "%o2", - "%o3", - "%o4", - "%o5", - "%o6", - "%o7", - "%l0", - "%l1", - "%l2", - "%l3", - "%l4", - "%l5", - "%l6", - "%l7", - "%i0", - "%i1", - "%i2", - "%i3", - "%i4", - "%i5", - "%i6", - "%i7", -}; -#endif - -#ifdef __arch64__ -# define SPARC64 1 -#else -# define SPARC64 0 -#endif - -/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o - registers. These are saved manually by the kernel in full 64-bit - slots. The %i and %l registers are saved by the register window - mechanism, which only allocates space for 32 bits. Given that this - window spill/fill can happen on any signal, we must consider the - high bits of the %i and %l registers garbage at all times. */ -#if SPARC64 -# define ALL_64 0xffffffffu -#else -# define ALL_64 0xffffu -#endif - -/* Define some temporary registers. T2 is used for constant generation. */ -#define TCG_REG_T1 TCG_REG_G1 -#define TCG_REG_T2 TCG_REG_O7 - -#ifndef CONFIG_SOFTMMU -# define TCG_GUEST_BASE_REG TCG_REG_I5 -#endif - -#define TCG_REG_TB TCG_REG_I1 -#define USE_REG_TB (sizeof(void *) > 4) - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_L0, - TCG_REG_L1, - TCG_REG_L2, - TCG_REG_L3, - TCG_REG_L4, - TCG_REG_L5, - TCG_REG_L6, - TCG_REG_L7, - - TCG_REG_I0, - TCG_REG_I1, - TCG_REG_I2, - TCG_REG_I3, - TCG_REG_I4, - TCG_REG_I5, - - TCG_REG_G2, - TCG_REG_G3, - TCG_REG_G4, - TCG_REG_G5, - - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, - TCG_REG_O4, - TCG_REG_O5, -}; - -static const int tcg_target_call_iarg_regs[6] = { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, - TCG_REG_O4, - TCG_REG_O5, -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; - -#define INSN_OP(x) ((x) << 30) -#define INSN_OP2(x) ((x) << 22) -#define INSN_OP3(x) ((x) << 19) -#define INSN_OPF(x) ((x) << 5) -#define INSN_RD(x) ((x) << 25) -#define INSN_RS1(x) ((x) << 14) -#define INSN_RS2(x) (x) -#define INSN_ASI(x) ((x) << 5) - -#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) -#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) -#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) -#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) -#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) -#define INSN_COND(x) ((x) << 25) - -#define COND_N 0x0 -#define COND_E 0x1 -#define COND_LE 0x2 -#define COND_L 0x3 -#define COND_LEU 0x4 -#define COND_CS 0x5 -#define COND_NEG 0x6 -#define COND_VS 0x7 -#define COND_A 0x8 -#define COND_NE 0x9 -#define COND_G 0xa -#define COND_GE 0xb -#define COND_GU 0xc -#define COND_CC 0xd -#define COND_POS 0xe -#define COND_VC 0xf -#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) - -#define RCOND_Z 1 -#define RCOND_LEZ 2 -#define RCOND_LZ 3 -#define RCOND_NZ 5 -#define RCOND_GZ 6 -#define RCOND_GEZ 7 - -#define MOVCC_ICC (1 << 18) -#define MOVCC_XCC (1 << 18 | 1 << 12) - -#define BPCC_ICC 0 -#define BPCC_XCC (2 << 20) -#define BPCC_PT (1 << 19) -#define BPCC_PN 0 -#define BPCC_A (1 << 29) - -#define BPR_PT BPCC_PT - -#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) -#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) -#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) -#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) -#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) -#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) -#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) -#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) -#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) -#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) -#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) -#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) -#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) -#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) -#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) -#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) -#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) -#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) -#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) -#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) -#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) - -#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) -#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) - -#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) -#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) -#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) - -#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) -#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) -#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) - -#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) -#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) -#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) -#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) -#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) -#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) -#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) -#define CALL INSN_OP(1) -#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) -#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) -#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) -#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) -#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) -#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) -#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) -#define STB (INSN_OP(3) | INSN_OP3(0x05)) -#define STH (INSN_OP(3) | INSN_OP3(0x06)) -#define STW (INSN_OP(3) | INSN_OP3(0x04)) -#define STX (INSN_OP(3) | INSN_OP3(0x0e)) -#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) -#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) -#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) -#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) -#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) -#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) -#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) -#define STBA (INSN_OP(3) | INSN_OP3(0x15)) -#define STHA (INSN_OP(3) | INSN_OP3(0x16)) -#define STWA (INSN_OP(3) | INSN_OP3(0x14)) -#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) - -#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) - -#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) - -#ifndef ASI_PRIMARY_LITTLE -#define ASI_PRIMARY_LITTLE 0x88 -#endif - -#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) - -#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) -#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) - -#ifndef use_vis3_instructions -bool use_vis3_instructions; -#endif - -static inline int check_fit_i64(int64_t val, unsigned int bits) -{ - return val == sextract64(val, 0, bits); -} - -static inline int check_fit_i32(int32_t val, unsigned int bits) -{ - return val == sextract32(val, 0, bits); -} - -#define check_fit_tl check_fit_i64 -#if SPARC64 -# define check_fit_ptr check_fit_i64 -#else -# define check_fit_ptr check_fit_i32 -#endif - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - uint32_t insn = *code_ptr; - intptr_t pcrel; - - value += addend; - pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); - - switch (type) { - case R_SPARC_WDISP16: - assert(check_fit_ptr(pcrel >> 2, 16)); - insn &= ~INSN_OFF16(-1); - insn |= INSN_OFF16(pcrel); - break; - case R_SPARC_WDISP19: - assert(check_fit_ptr(pcrel >> 2, 19)); - insn &= ~INSN_OFF19(-1); - insn |= INSN_OFF19(pcrel); - break; - default: - g_assert_not_reached(); - } - - *code_ptr = insn; - return true; -} - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - break; - case 'R': - ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; - break; - case 'A': /* qemu_ld/st address constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; - reserve_helpers: - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); - break; - case 's': /* qemu_st data 32-bit constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = 0xffffffff; - goto reserve_helpers; - case 'S': /* qemu_st data 64-bit constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = ALL_64; - goto reserve_helpers; - case 'I': - ct->ct |= TCG_CT_CONST_S11; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S13; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct = arg_ct->ct; - - if (ct & TCG_CT_CONST) { - return 1; - } - - if (type == TCG_TYPE_I32) { - val = (int32_t)val; - } - - if ((ct & TCG_CT_CONST_ZERO) && val == 0) { - return 1; - } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { - return 1; - } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { - return 1; - } else { - return 0; - } -} - -static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, - TCGReg rs2, int op) -{ - tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); -} - -static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t offset, int op) -{ - tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); -} - -static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t val2, int val2const, int op) -{ - tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) - | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); -} - -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) -{ - if (ret != arg) { - tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); - } - return true; -} - -static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) -{ - tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); -} - -static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) -{ - tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); -} - -static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) -{ - tcg_target_long hi, lo = (int32_t)arg; - tcg_target_long test, lsb; - - /* Make sure we test 32-bit constants for imm13 properly. */ - if (type == TCG_TYPE_I32) { - arg = lo; - } - - /* A 13-bit constant sign-extended to 64-bits. */ - if (check_fit_tl(arg, 13)) { - tcg_out_movi_imm13(s, ret, arg); - return; - } - - /* A 13-bit constant relative to the TB. */ - if (!in_prologue && USE_REG_TB) { - test = arg - (uintptr_t)s->code_gen_ptr; - if (check_fit_ptr(test, 13)) { - tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); - return; - } - } - - /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ - if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { - tcg_out_sethi(s, ret, arg); - if (arg & 0x3ff) { - tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); - } - return; - } - - /* A 32-bit constant sign-extended to 64-bits. */ - if (arg == lo) { - tcg_out_sethi(s, ret, ~arg); - tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); - return; - } - - /* A 21-bit constant, shifted. */ - lsb = ctz64(arg); - test = (tcg_target_long)arg >> lsb; - if (check_fit_tl(test, 13)) { - tcg_out_movi_imm13(s, ret, test); - tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); - return; - } else if (lsb > 10 && test == extract64(test, 0, 21)) { - tcg_out_sethi(s, ret, test << 10); - tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); - return; - } - - /* A 64-bit constant decomposed into 2 32-bit pieces. */ - if (check_fit_i32(lo, 13)) { - hi = (arg - lo) >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); - tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); - } else { - hi = arg >> 32; - tcg_out_movi(s, TCG_TYPE_I32, ret, hi); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); - tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); - tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); - } -} - -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) -{ - tcg_out_movi_int(s, type, ret, arg, false); -} - -static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, - TCGReg a2, int op) -{ - tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); -} - -static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, - intptr_t offset, int op) -{ - if (check_fit_ptr(offset, 13)) { - tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | - INSN_IMM13(offset)); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); - tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); - } -} - -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) -{ - tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); -} - -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - if (val == 0) { - tcg_out_st(s, type, TCG_REG_G0, base, ofs); - return true; - } - return false; -} - -static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) -{ - intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; - if (USE_REG_TB && check_fit_ptr(diff, 13)) { - tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); - return; - } - tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); - tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); -} - -static inline void tcg_out_sety(TCGContext *s, TCGReg rs) -{ - tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); -} - -static inline void tcg_out_rdy(TCGContext *s, TCGReg rd) -{ - tcg_out32(s, RDY | INSN_RD(rd)); -} - -static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t val2, int val2const, int uns) -{ - /* Load Y with the sign/zero extension of RS1 to 64-bits. */ - if (uns) { - tcg_out_sety(s, TCG_REG_G0); - } else { - tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); - tcg_out_sety(s, TCG_REG_T1); - } - - tcg_out_arithc(s, rd, rs1, val2, val2const, - uns ? ARITH_UDIV : ARITH_SDIV); -} - -static inline void tcg_out_nop(TCGContext *s) -{ - tcg_out32(s, NOP); -} - -static const uint8_t tcg_cond_to_bcond[] = { - [TCG_COND_EQ] = COND_E, - [TCG_COND_NE] = COND_NE, - [TCG_COND_LT] = COND_L, - [TCG_COND_GE] = COND_GE, - [TCG_COND_LE] = COND_LE, - [TCG_COND_GT] = COND_G, - [TCG_COND_LTU] = COND_CS, - [TCG_COND_GEU] = COND_CC, - [TCG_COND_LEU] = COND_LEU, - [TCG_COND_GTU] = COND_GU, -}; - -static const uint8_t tcg_cond_to_rcond[] = { - [TCG_COND_EQ] = RCOND_Z, - [TCG_COND_NE] = RCOND_NZ, - [TCG_COND_LT] = RCOND_LZ, - [TCG_COND_GT] = RCOND_GZ, - [TCG_COND_LE] = RCOND_LEZ, - [TCG_COND_GE] = RCOND_GEZ -}; - -static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) -{ - tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); -} - -static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) -{ - int off19 = 0; - - if (l->has_value) { - off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); - } else { - tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); - } - tcg_out_bpcc0(s, scond, flags, off19); -} - -static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const) -{ - tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); -} - -static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, - int32_t arg2, int const_arg2, TCGLabel *l) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2); - tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); - tcg_out_nop(s); -} - -static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, - int32_t v1, int v1const) -{ - tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) - | INSN_RS1(tcg_cond_to_bcond[cond]) - | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); -} - -static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const, - int32_t v1, int v1const) -{ - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); -} - -static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, - int32_t arg2, int const_arg2, TCGLabel *l) -{ - /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ - if (arg2 == 0 && !is_unsigned_cond(cond)) { - int off16 = 0; - - if (l->has_value) { - off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); - } else { - tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); - } - tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) - | INSN_COND(tcg_cond_to_rcond[cond]) | off16); - } else { - tcg_out_cmp(s, arg1, arg2, const_arg2); - tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); - } - tcg_out_nop(s); -} - -static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1, - int32_t v1, int v1const) -{ - tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) - | (tcg_cond_to_rcond[cond] << 10) - | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); -} - -static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const, - int32_t v1, int v1const) -{ - /* For 64-bit signed comparisons vs zero, we can avoid the compare. - Note that the immediate range is one bit smaller, so we must check - for that as well. */ - if (c2 == 0 && !is_unsigned_cond(cond) - && (!v1const || check_fit_i32(v1, 10))) { - tcg_out_movr(s, cond, ret, c1, v1, v1const); - } else { - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); - } -} - -static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const) -{ - /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ - switch (cond) { - case TCG_COND_LTU: - case TCG_COND_GEU: - /* The result of the comparison is in the carry bit. */ - break; - - case TCG_COND_EQ: - case TCG_COND_NE: - /* For equality, we can transform to inequality vs zero. */ - if (c2 != 0) { - tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); - c2 = TCG_REG_T1; - } else { - c2 = c1; - } - c1 = TCG_REG_G0, c2const = 0; - cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); - break; - - case TCG_COND_GTU: - case TCG_COND_LEU: - /* If we don't need to load a constant into a register, we can - swap the operands on GTU/LEU. There's no benefit to loading - the constant into a temporary register. */ - if (!c2const || c2 == 0) { - TCGReg t = c1; - c1 = c2; - c2 = t; - c2const = 0; - cond = tcg_swap_cond(cond); - break; - } - /* FALLTHRU */ - - default: - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movi_imm13(s, ret, 0); - tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); - return; - } - - tcg_out_cmp(s, c1, c2, c2const); - if (cond == TCG_COND_LTU) { - tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); - } else { - tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); - } -} - -static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const) -{ - if (use_vis3_instructions) { - switch (cond) { - case TCG_COND_NE: - if (c2 != 0) { - break; - } - c2 = c1, c2const = 0, c1 = TCG_REG_G0; - /* FALLTHRU */ - case TCG_COND_LTU: - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); - return; - default: - break; - } - } - - /* For 64-bit signed comparisons vs zero, we can avoid the compare - if the input does not overlap the output. */ - if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { - tcg_out_movi_imm13(s, ret, 0); - tcg_out_movr(s, cond, ret, c1, 1, 1); - } else { - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movi_imm13(s, ret, 0); - tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); - } -} - -static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, - TCGReg al, TCGReg ah, int32_t bl, int blconst, - int32_t bh, int bhconst, int opl, int oph) -{ - TCGReg tmp = TCG_REG_T1; - - /* Note that the low parts are fully consumed before tmp is set. */ - if (rl != ah && (bhconst || rl != bh)) { - tmp = rl; - } - - tcg_out_arithc(s, tmp, al, bl, blconst, opl); - tcg_out_arithc(s, rh, ah, bh, bhconst, oph); - tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); -} - -static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, - TCGReg al, TCGReg ah, int32_t bl, int blconst, - int32_t bh, int bhconst, bool is_sub) -{ - TCGReg tmp = TCG_REG_T1; - - /* Note that the low parts are fully consumed before tmp is set. */ - if (rl != ah && (bhconst || rl != bh)) { - tmp = rl; - } - - tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); - - if (use_vis3_instructions && !is_sub) { - /* Note that ADDXC doesn't accept immediates. */ - if (bhconst && bh != 0) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh); - bh = TCG_REG_T2; - } - tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); - } else if (bh == TCG_REG_G0) { - /* If we have a zero, we can perform the operation in two insns, - with the arithmetic first, and a conditional move into place. */ - if (rh == ah) { - tcg_out_arithi(s, TCG_REG_T2, ah, 1, - is_sub ? ARITH_SUB : ARITH_ADD); - tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); - } else { - tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); - tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); - } - } else { - /* Otherwise adjust BH as if there is carry into T2 ... */ - if (bhconst) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1)); - } else { - tcg_out_arithi(s, TCG_REG_T2, bh, 1, - is_sub ? ARITH_SUB : ARITH_ADD); - } - /* ... smoosh T2 back to original BH if carry is clear ... */ - tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); - /* ... and finally perform the arithmetic with the new operand. */ - tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); - } - - tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); -} - -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, - bool in_prologue) -{ - ptrdiff_t disp = tcg_pcrel_diff(s, dest); - - if (disp == (int32_t)disp) { - tcg_out32(s, CALL | (uint32_t)disp >> 2); - } else { - uintptr_t desti = (uintptr_t)dest; - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue); - tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); - } -} - -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) -{ - tcg_out_call_nodelay(s, dest, false); - tcg_out_nop(s); -} - -static void tcg_out_mb(TCGContext *s, TCGArg a0) -{ - /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ - tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); -} - -#ifdef CONFIG_SOFTMMU -static tcg_insn_unit *qemu_ld_trampoline[16]; -static tcg_insn_unit *qemu_st_trampoline[16]; - -static void emit_extend(TCGContext *s, TCGReg r, int op) -{ - /* Emit zero extend of 8, 16 or 32 bit data as - * required by the MO_* value op; do nothing for 64 bit. - */ - switch (op & MO_SIZE) { - case MO_8: - tcg_out_arithi(s, r, r, 0xff, ARITH_AND); - break; - case MO_16: - tcg_out_arithi(s, r, r, 16, SHIFT_SLL); - tcg_out_arithi(s, r, r, 16, SHIFT_SRL); - break; - case MO_32: - if (SPARC64) { - tcg_out_arith(s, r, r, 0, SHIFT_SRL); - } - break; - case MO_64: - break; - } -} - -static void build_trampolines(TCGContext *s) -{ - static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, - [MO_SB] = helper_ret_ldsb_mmu, - [MO_LEUW] = helper_le_lduw_mmu, - [MO_LESW] = helper_le_ldsw_mmu, - [MO_LEUL] = helper_le_ldul_mmu, - [MO_LEQ] = helper_le_ldq_mmu, - [MO_BEUW] = helper_be_lduw_mmu, - [MO_BESW] = helper_be_ldsw_mmu, - [MO_BEUL] = helper_be_ldul_mmu, - [MO_BEQ] = helper_be_ldq_mmu, - }; - static void * const qemu_st_helpers[16] = { - [MO_UB] = helper_ret_stb_mmu, - [MO_LEUW] = helper_le_stw_mmu, - [MO_LEUL] = helper_le_stl_mmu, - [MO_LEQ] = helper_le_stq_mmu, - [MO_BEUW] = helper_be_stw_mmu, - [MO_BEUL] = helper_be_stl_mmu, - [MO_BEQ] = helper_be_stq_mmu, - }; - - int i; - TCGReg ra; - - for (i = 0; i < 16; ++i) { - if (qemu_ld_helpers[i] == NULL) { - continue; - } - - /* May as well align the trampoline. */ - while ((uintptr_t)s->code_ptr & 15) { - tcg_out_nop(s); - } - qemu_ld_trampoline[i] = s->code_ptr; - - if (SPARC64 || TARGET_LONG_BITS == 32) { - ra = TCG_REG_O3; - } else { - /* Install the high part of the address. */ - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); - ra = TCG_REG_O4; - } - - /* Set the retaddr operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); - /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); - } - - for (i = 0; i < 16; ++i) { - if (qemu_st_helpers[i] == NULL) { - continue; - } - - /* May as well align the trampoline. */ - while ((uintptr_t)s->code_ptr & 15) { - tcg_out_nop(s); - } - qemu_st_trampoline[i] = s->code_ptr; - - if (SPARC64) { - emit_extend(s, TCG_REG_O2, i); - ra = TCG_REG_O4; - } else { - ra = TCG_REG_O1; - if (TARGET_LONG_BITS == 64) { - /* Install the high part of the address. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra += 2; - } else { - ra += 1; - } - if ((i & MO_SIZE) == MO_64) { - /* Install the high part of the data. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra += 2; - } else { - emit_extend(s, ra, i); - ra += 1; - } - /* Skip the oi argument. */ - ra += 1; - } - - /* Set the retaddr operand. */ - if (ra >= TCG_REG_O6) { - tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET); - ra = TCG_REG_G1; - } - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - /* Set the env operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); - /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i], true); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); - } -} -#endif - -/* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int tmp_buf_size, frame_size; - - /* The TCG temp buffer is at the top of the frame, immediately - below the frame pointer. */ - tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); - tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, - tmp_buf_size); - - /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is - otherwise the minimal frame usable by callees. */ - frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; - frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; - frame_size += TCG_TARGET_STACK_ALIGN - 1; - frame_size &= -TCG_TARGET_STACK_ALIGN; - tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | - INSN_IMM13(-frame_size)); - -#ifndef CONFIG_SOFTMMU - if (guest_base != 0) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); - } -#endif - - /* We choose TCG_REG_TB such that no move is required. */ - if (USE_REG_TB) { - QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); - } - - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); - /* delay slot */ - tcg_out_nop(s); - - /* Epilogue for goto_ptr. */ - s->code_gen_epilogue = s->code_ptr; - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - /* delay slot */ - tcg_out_movi_imm13(s, TCG_REG_O0, 0); - -#ifdef CONFIG_SOFTMMU - build_trampolines(s); -#endif -} - -static void tcg_out_nop_fill(tcg_insn_unit *p, int count) -{ - int i; - for (i = 0; i < count; ++i) { - p[i] = NOP; - } -} - -#if defined(CONFIG_SOFTMMU) - -/* We expect to use a 13-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); - -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the possible two parts of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - The result of the TLB comparison is in %[ix]cc. The sanitized address - is in the returned register, maybe %o0. The TLB addend is in %o1. */ - -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, - MemOp opc, int which) -{ - int fast_off = TLB_MASK_TABLE_OFS(mem_index); - int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); - int table_off = fast_off + offsetof(CPUTLBDescFast, table); - const TCGReg r0 = TCG_REG_O0; - const TCGReg r1 = TCG_REG_O1; - const TCGReg r2 = TCG_REG_O2; - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - tcg_target_long compare_mask; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, - SHIFT_SRL); - tcg_out_arith(s, r2, r2, r0, ARITH_AND); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ - tcg_out_arith(s, r2, r2, r1, ARITH_ADD); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which); - tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend)); - - /* Mask out the page offset, except for the required alignment. - We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); - if (check_fit_tl(compare_mask, 13)) { - tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND); - } else { - tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask); - tcg_out_arith(s, r2, addr, r2, ARITH_AND); - } - tcg_out_cmp(s, r0, r2, 0); - - /* If the guest address must be zero-extended, do so now. */ - if (SPARC64 && TARGET_LONG_BITS == 32) { - tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); - return r0; - } - return addr; -} -#endif /* CONFIG_SOFTMMU */ - -static const int qemu_ld_opc[16] = { - [MO_UB] = LDUB, - [MO_SB] = LDSB, - - [MO_BEUW] = LDUH, - [MO_BESW] = LDSH, - [MO_BEUL] = LDUW, - [MO_BESL] = LDSW, - [MO_BEQ] = LDX, - - [MO_LEUW] = LDUH_LE, - [MO_LESW] = LDSH_LE, - [MO_LEUL] = LDUW_LE, - [MO_LESL] = LDSW_LE, - [MO_LEQ] = LDX_LE, -}; - -static const int qemu_st_opc[16] = { - [MO_UB] = STB, - - [MO_BEUW] = STH, - [MO_BEUL] = STW, - [MO_BEQ] = STX, - - [MO_LEUW] = STH_LE, - [MO_LEUL] = STW_LE, - [MO_LEQ] = STX_LE, -}; - -static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOpIdx oi, bool is_64) -{ - MemOp memop = get_memop(oi); -#ifdef CONFIG_SOFTMMU - unsigned memi = get_mmuidx(oi); - TCGReg addrz, param; - tcg_insn_unit *func; - tcg_insn_unit *label_ptr; - - addrz = tcg_out_tlb_load(s, addr, memi, memop, - offsetof(CPUTLBEntry, addr_read)); - - /* The fast path is exactly one insn. Thus we can perform the - entire TLB Hit in the (annulled) delay slot of the branch - over the TLB Miss case. */ - - /* beq,a,pt %[xi]cc, label0 */ - label_ptr = s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT - | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, - qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); - - /* TLB Miss. */ - - param = TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS == 64) { - /* Skip the high-part; we'll perform the extract in the trampoline. */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); - - /* We use the helpers to extend SB and SW data, leaving the case - of SL needing explicit extending below. */ - if ((memop & MO_SSIZE) == MO_SL) { - func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)]; - } else { - func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; - } - tcg_debug_assert(func != NULL); - tcg_out_call_nodelay(s, func, false); - /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); - - /* Recall that all of the helpers return 64-bit results. - Which complicates things for sparcv8plus. */ - if (SPARC64) { - /* We let the helper sign-extend SB and SW, but leave SL for here. */ - if (is_64 && (memop & MO_SSIZE) == MO_SL) { - tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); - } else { - tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); - } - } else { - if ((memop & MO_SIZE) == MO_64) { - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); - tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); - } else if (is_64) { - /* Re-extend from 32-bit rather than reassembling when we - know the high register must be an extension. */ - tcg_out_arithi(s, data, TCG_REG_O1, 0, - memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); - } - } - - *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#else - if (SPARC64 && TARGET_LONG_BITS == 32) { - tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); - addr = TCG_REG_T1; - } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), - qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); -#endif /* CONFIG_SOFTMMU */ -} - -static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, - TCGMemOpIdx oi) -{ - MemOp memop = get_memop(oi); -#ifdef CONFIG_SOFTMMU - unsigned memi = get_mmuidx(oi); - TCGReg addrz, param; - tcg_insn_unit *func; - tcg_insn_unit *label_ptr; - - addrz = tcg_out_tlb_load(s, addr, memi, memop, - offsetof(CPUTLBEntry, addr_write)); - - /* The fast path is exactly one insn. Thus we can perform the entire - TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */ - /* beq,a,pt %[xi]cc, label0 */ - label_ptr = s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT - | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, - qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); - - /* TLB Miss. */ - - param = TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS == 64) { - /* Skip the high-part; we'll perform the extract in the trampoline. */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); - if (!SPARC64 && (memop & MO_SIZE) == MO_64) { - /* Skip the high-part; we'll perform the extract in the trampoline. */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, data); - - func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; - tcg_debug_assert(func != NULL); - tcg_out_call_nodelay(s, func, false); - /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); - - *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#else - if (SPARC64 && TARGET_LONG_BITS == 32) { - tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); - addr = TCG_REG_T1; - } - tcg_out_ldst_rr(s, data, addr, - (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0), - qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); -#endif /* CONFIG_SOFTMMU */ -} - -static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - TCGArg a0, a1, a2; - int c, c2; - - /* Hoist the loads of the most common arguments. */ - a0 = args[0]; - a1 = args[1]; - a2 = args[2]; - c2 = const_args[2]; - - switch (opc) { - case INDEX_op_exit_tb: - if (check_fit_ptr(a0, 13)) { - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_movi_imm13(s, TCG_REG_O0, a0); - break; - } else if (USE_REG_TB) { - intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; - if (check_fit_ptr(tb_diff, 13)) { - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - /* Note that TCG_REG_TB has been unwound to O1. */ - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); - break; - } - } - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - if (USE_REG_TB) { - /* make sure the patch is 8-byte aligned. */ - if ((intptr_t)s->code_ptr & 4) { - tcg_out_nop(s); - } - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - tcg_out_sethi(s, TCG_REG_T1, 0); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); - tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); - } else { - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - tcg_out32(s, CALL); - tcg_out_nop(s); - } - } else { - /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_TB, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); - tcg_out_nop(s); - } - set_jmp_reset_offset(s, a0); - - /* For the unlinked path of goto_tb, we need to reset - TCG_REG_TB to the beginning of this TB. */ - if (USE_REG_TB) { - c = -tcg_current_code_size(s); - if (check_fit_i32(c, 13)) { - tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); - tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, - TCG_REG_T1, ARITH_ADD); - } - } - break; - case INDEX_op_goto_ptr: - tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); - if (USE_REG_TB) { - tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); - } else { - tcg_out_nop(s); - } - break; - case INDEX_op_br: - tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); - tcg_out_nop(s); - break; - -#define OP_32_64(x) \ - glue(glue(case INDEX_op_, x), _i32): \ - glue(glue(case INDEX_op_, x), _i64) - - OP_32_64(ld8u): - tcg_out_ldst(s, a0, a1, a2, LDUB); - break; - OP_32_64(ld8s): - tcg_out_ldst(s, a0, a1, a2, LDSB); - break; - OP_32_64(ld16u): - tcg_out_ldst(s, a0, a1, a2, LDUH); - break; - OP_32_64(ld16s): - tcg_out_ldst(s, a0, a1, a2, LDSH); - break; - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - tcg_out_ldst(s, a0, a1, a2, LDUW); - break; - OP_32_64(st8): - tcg_out_ldst(s, a0, a1, a2, STB); - break; - OP_32_64(st16): - tcg_out_ldst(s, a0, a1, a2, STH); - break; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - tcg_out_ldst(s, a0, a1, a2, STW); - break; - OP_32_64(add): - c = ARITH_ADD; - goto gen_arith; - OP_32_64(sub): - c = ARITH_SUB; - goto gen_arith; - OP_32_64(and): - c = ARITH_AND; - goto gen_arith; - OP_32_64(andc): - c = ARITH_ANDN; - goto gen_arith; - OP_32_64(or): - c = ARITH_OR; - goto gen_arith; - OP_32_64(orc): - c = ARITH_ORN; - goto gen_arith; - OP_32_64(xor): - c = ARITH_XOR; - goto gen_arith; - case INDEX_op_shl_i32: - c = SHIFT_SLL; - do_shift32: - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); - break; - case INDEX_op_shr_i32: - c = SHIFT_SRL; - goto do_shift32; - case INDEX_op_sar_i32: - c = SHIFT_SRA; - goto do_shift32; - case INDEX_op_mul_i32: - c = ARITH_UMUL; - goto gen_arith; - - OP_32_64(neg): - c = ARITH_SUB; - goto gen_arith1; - OP_32_64(not): - c = ARITH_ORN; - goto gen_arith1; - - case INDEX_op_div_i32: - tcg_out_div32(s, a0, a1, a2, c2, 0); - break; - case INDEX_op_divu_i32: - tcg_out_div32(s, a0, a1, a2, c2, 1); - break; - - case INDEX_op_brcond_i32: - tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); - break; - case INDEX_op_setcond_i32: - tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); - break; - case INDEX_op_movcond_i32: - tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); - break; - - case INDEX_op_add2_i32: - tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], - args[4], const_args[4], args[5], const_args[5], - ARITH_ADDCC, ARITH_ADDC); - break; - case INDEX_op_sub2_i32: - tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], - args[4], const_args[4], args[5], const_args[5], - ARITH_SUBCC, ARITH_SUBC); - break; - case INDEX_op_mulu2_i32: - c = ARITH_UMUL; - goto do_mul2; - case INDEX_op_muls2_i32: - c = ARITH_SMUL; - do_mul2: - /* The 32-bit multiply insns produce a full 64-bit result. If the - destination register can hold it, we can avoid the slower RDY. */ - tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); - if (SPARC64 || a0 <= TCG_REG_O7) { - tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); - } else { - tcg_out_rdy(s, a1); - } - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, a1, a2, false); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, true); - break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, a0, a1, a2); - break; - - case INDEX_op_ld32s_i64: - tcg_out_ldst(s, a0, a1, a2, LDSW); - break; - case INDEX_op_ld_i64: - tcg_out_ldst(s, a0, a1, a2, LDX); - break; - case INDEX_op_st_i64: - tcg_out_ldst(s, a0, a1, a2, STX); - break; - case INDEX_op_shl_i64: - c = SHIFT_SLLX; - do_shift64: - /* Limit immediate shift count lest we create an illegal insn. */ - tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); - break; - case INDEX_op_shr_i64: - c = SHIFT_SRLX; - goto do_shift64; - case INDEX_op_sar_i64: - c = SHIFT_SRAX; - goto do_shift64; - case INDEX_op_mul_i64: - c = ARITH_MULX; - goto gen_arith; - case INDEX_op_div_i64: - c = ARITH_SDIVX; - goto gen_arith; - case INDEX_op_divu_i64: - c = ARITH_UDIVX; - goto gen_arith; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL); - break; - case INDEX_op_extrl_i64_i32: - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - break; - case INDEX_op_extrh_i64_i32: - tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); - break; - - case INDEX_op_brcond_i64: - tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); - break; - case INDEX_op_setcond_i64: - tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); - break; - case INDEX_op_movcond_i64: - tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); - break; - case INDEX_op_add2_i64: - tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], - const_args[4], args[5], const_args[5], false); - break; - case INDEX_op_sub2_i64: - tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], - const_args[4], args[5], const_args[5], true); - break; - case INDEX_op_muluh_i64: - tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); - break; - - gen_arith: - tcg_out_arithc(s, a0, a1, a2, c2, c); - break; - - gen_arith1: - tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); - break; - - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } }; - static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } }; - static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } }; - static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } }; - static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } }; - static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; - static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } }; - static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } }; - static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } }; - static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } }; - static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } }; - static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } }; - static const TCGTargetOpDef r_rZ_rJ - = { .args_ct_str = { "r", "rZ", "rJ" } }; - static const TCGTargetOpDef R_RZ_RJ - = { .args_ct_str = { "R", "RZ", "RJ" } }; - static const TCGTargetOpDef r_r_rZ_rJ - = { .args_ct_str = { "r", "r", "rZ", "rJ" } }; - static const TCGTargetOpDef movc_32 - = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } }; - static const TCGTargetOpDef movc_64 - = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } }; - static const TCGTargetOpDef add2_32 - = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; - static const TCGTargetOpDef add2_64 - = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } }; - - switch (op) { - case INDEX_op_goto_ptr: - return &r; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_neg_i32: - case INDEX_op_not_i32: - return &r_r; - - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - return &rZ_r; - - case INDEX_op_add_i32: - case INDEX_op_mul_i32: - case INDEX_op_div_i32: - case INDEX_op_divu_i32: - case INDEX_op_sub_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: - case INDEX_op_or_i32: - case INDEX_op_orc_i32: - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_setcond_i32: - return &r_rZ_rJ; - - case INDEX_op_brcond_i32: - return &rZ_rJ; - case INDEX_op_movcond_i32: - return &movc_32; - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - return &add2_32; - case INDEX_op_mulu2_i32: - case INDEX_op_muls2_i32: - return &r_r_rZ_rJ; - - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: - return &R_r; - - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - return &RZ_r; - - case INDEX_op_add_i64: - case INDEX_op_mul_i64: - case INDEX_op_div_i64: - case INDEX_op_divu_i64: - case INDEX_op_sub_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: - case INDEX_op_or_i64: - case INDEX_op_orc_i64: - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_setcond_i64: - return &R_RZ_RJ; - - case INDEX_op_neg_i64: - case INDEX_op_not_i64: - case INDEX_op_ext32s_i64: - case INDEX_op_ext32u_i64: - return &R_R; - - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - return &r_R; - - case INDEX_op_brcond_i64: - return &RZ_RJ; - case INDEX_op_movcond_i64: - return &movc_64; - case INDEX_op_add2_i64: - case INDEX_op_sub2_i64: - return &add2_64; - case INDEX_op_muluh_i64: - return &R_R_R; - - case INDEX_op_qemu_ld_i32: - return &r_A; - case INDEX_op_qemu_ld_i64: - return &R_A; - case INDEX_op_qemu_st_i32: - return &sZ_A; - case INDEX_op_qemu_st_i64: - return &SZ_A; - - default: - return NULL; - } -} - -static void tcg_target_init(TCGContext *s) -{ - /* Only probe for the platform and capabilities if we havn't already - determined maximum values at compile time. */ -#ifndef use_vis3_instructions - { - unsigned long hwcap = qemu_getauxval(AT_HWCAP); - use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; - } -#endif - - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; - tcg_target_available_regs[TCG_TYPE_I64] = ALL_64; - - tcg_target_call_clobber_regs = 0; - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ -} - -#if SPARC64 -# define ELF_HOST_MACHINE EM_SPARCV9 -#else -# define ELF_HOST_MACHINE EM_SPARC32PLUS -# define ELF_HOST_FLAGS EF_SPARC_32PLUS -#endif - -typedef struct { - DebugFrameHeader h; - uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; - uint8_t fde_win_save; - uint8_t fde_ret_save[3]; -} DebugFrame; - -static const DebugFrame debug_frame = { - .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ - .h.cie.id = -1, - .h.cie.version = 1, - .h.cie.code_align = 1, - .h.cie.data_align = -sizeof(void *) & 0x7f, - .h.cie.return_column = 15, /* o7 */ - - /* Total FDE size does not include the "len" member. */ - .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), - - .fde_def_cfa = { -#if SPARC64 - 12, 30, /* DW_CFA_def_cfa i6, 2047 */ - (2047 & 0x7f) | 0x80, (2047 >> 7) -#else - 13, 30 /* DW_CFA_def_cfa_register i6 */ -#endif - }, - .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ - .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ -}; - -void tcg_register_jit(void *buf, size_t buf_size) -{ - tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -} - -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) -{ - intptr_t tb_disp = addr - tc_ptr; - intptr_t br_disp = addr - jmp_addr; - tcg_insn_unit i1, i2; - - /* We can reach the entire address space for ILP32. - For LP64, the code_gen_buffer can't be larger than 2GB. */ - tcg_debug_assert(tb_disp == (int32_t)tb_disp); - tcg_debug_assert(br_disp == (int32_t)br_disp); - - if (!USE_REG_TB) { - atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); - return; - } - - /* This does not exercise the range of the branch, but we do - still need to be able to load the new value of TCG_REG_TB. - But this does still happen quite often. */ - if (check_fit_ptr(tb_disp, 13)) { - /* ba,pt %icc, addr */ - i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) - | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); - i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) - | INSN_IMM13(tb_disp)); - } else if (tb_disp >= 0) { - i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10); - i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) - | INSN_IMM13(tb_disp & 0x3ff)); - } else { - i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10); - i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) - | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); - } - - atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_icache_range(jmp_addr, jmp_addr + 8); -} diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc new file mode 100644 index 0000000000..05f9b3ccd6 --- /dev/null +++ b/tcg/tcg-ldst.c.inc @@ -0,0 +1,78 @@ +/* + * TCG Backend Data: load-store optimization only. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelQemuLdst { + bool is_ld; /* qemu_ld: true, qemu_st: false */ + TCGMemOpIdx oi; + TCGType type; /* result type of a load */ + TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ + TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ + TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ + TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ + tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ + QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; +} TCGLabelQemuLdst; + + +/* + * Generate TB finalization at the end of block + */ + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); + +static int tcg_out_ldst_finalize(TCGContext *s) +{ + TCGLabelQemuLdst *lb; + + /* qemu_ld/st slow paths */ + QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { + if (lb->is_ld + ? !tcg_out_qemu_ld_slow_path(s, lb) + : !tcg_out_qemu_st_slow_path(s, lb)) { + return -2; + } + + /* Test for (pending) buffer overflow. The assumption is that any + one operation beginning below the high water mark cannot overrun + the buffer completely. Thus we can test for overflow after + generating code without having to check during generation. */ + if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { + return -1; + } + } + return 0; +} + +/* + * Allocate a new TCGLabelQemuLdst entry. + */ + +static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) +{ + TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); + + QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); + + return l; +} diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c deleted file mode 100644 index 05f9b3ccd6..0000000000 --- a/tcg/tcg-ldst.inc.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * TCG Backend Data: load-store optimization only. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -typedef struct TCGLabelQemuLdst { - bool is_ld; /* qemu_ld: true, qemu_st: false */ - TCGMemOpIdx oi; - TCGType type; /* result type of a load */ - TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ - TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ - TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ - TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ - tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ - tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ - QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; -} TCGLabelQemuLdst; - - -/* - * Generate TB finalization at the end of block - */ - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); - -static int tcg_out_ldst_finalize(TCGContext *s) -{ - TCGLabelQemuLdst *lb; - - /* qemu_ld/st slow paths */ - QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { - if (lb->is_ld - ? !tcg_out_qemu_ld_slow_path(s, lb) - : !tcg_out_qemu_st_slow_path(s, lb)) { - return -2; - } - - /* Test for (pending) buffer overflow. The assumption is that any - one operation beginning below the high water mark cannot overrun - the buffer completely. Thus we can test for overflow after - generating code without having to check during generation. */ - if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { - return -1; - } - } - return 0; -} - -/* - * Allocate a new TCGLabelQemuLdst entry. - */ - -static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) -{ - TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); - - QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); - - return l; -} diff --git a/tcg/tcg-pool.c.inc b/tcg/tcg-pool.c.inc new file mode 100644 index 0000000000..82cbcc89bd --- /dev/null +++ b/tcg/tcg-pool.c.inc @@ -0,0 +1,158 @@ +/* + * TCG Backend Data: constant pool. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelPoolData { + struct TCGLabelPoolData *next; + tcg_insn_unit *label; + intptr_t addend; + int rtype; + unsigned nlong; + tcg_target_ulong data[]; +} TCGLabelPoolData; + + +static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, + tcg_insn_unit *label, intptr_t addend) +{ + TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) + + sizeof(tcg_target_ulong) * nlong); + + n->label = label; + n->addend = addend; + n->rtype = rtype; + n->nlong = nlong; + return n; +} + +static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) +{ + TCGLabelPoolData *i, **pp; + int nlong = n->nlong; + + /* Insertion sort on the pool. */ + for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) { + if (nlong > i->nlong) { + break; + } + if (nlong < i->nlong) { + continue; + } + if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) { + break; + } + } + n->next = *pp; + *pp = n; +} + +/* The "usual" for generic integer code. */ +static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, + tcg_insn_unit *label, intptr_t addend) +{ + TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend); + n->data[0] = d; + new_pool_insert(s, n); +} + +/* For v64 or v128, depending on the host. */ +static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, + intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1) +{ + TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend); + n->data[0] = d0; + n->data[1] = d1; + new_pool_insert(s, n); +} + +/* For v128 or v256, depending on the host. */ +static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, + intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1, tcg_target_ulong d2, + tcg_target_ulong d3) +{ + TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend); + n->data[0] = d0; + n->data[1] = d1; + n->data[2] = d2; + n->data[3] = d3; + new_pool_insert(s, n); +} + +/* For v256, for 32-bit host. */ +static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, + intptr_t addend, tcg_target_ulong d0, + tcg_target_ulong d1, tcg_target_ulong d2, + tcg_target_ulong d3, tcg_target_ulong d4, + tcg_target_ulong d5, tcg_target_ulong d6, + tcg_target_ulong d7) +{ + TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend); + n->data[0] = d0; + n->data[1] = d1; + n->data[2] = d2; + n->data[3] = d3; + n->data[4] = d4; + n->data[5] = d5; + n->data[6] = d6; + n->data[7] = d7; + new_pool_insert(s, n); +} + +/* To be provided by cpu/tcg-target.c.inc. */ +static void tcg_out_nop_fill(tcg_insn_unit *p, int count); + +static int tcg_out_pool_finalize(TCGContext *s) +{ + TCGLabelPoolData *p = s->pool_labels; + TCGLabelPoolData *l = NULL; + void *a; + + if (p == NULL) { + return 0; + } + + /* ??? Round up to qemu_icache_linesize, but then do not round + again when allocating the next TranslationBlock structure. */ + a = (void *)ROUND_UP((uintptr_t)s->code_ptr, + sizeof(tcg_target_ulong) * p->nlong); + tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); + s->data_gen_ptr = a; + + for (; p != NULL; p = p->next) { + size_t size = sizeof(tcg_target_ulong) * p->nlong; + if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { + if (unlikely(a > s->code_gen_highwater)) { + return -1; + } + memcpy(a, p->data, size); + a += size; + l = p; + } + if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) { + return -2; + } + } + + s->code_ptr = a; + return 0; +} diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c deleted file mode 100644 index 4eaa84b631..0000000000 --- a/tcg/tcg-pool.inc.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * TCG Backend Data: constant pool. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -typedef struct TCGLabelPoolData { - struct TCGLabelPoolData *next; - tcg_insn_unit *label; - intptr_t addend; - int rtype; - unsigned nlong; - tcg_target_ulong data[]; -} TCGLabelPoolData; - - -static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, - tcg_insn_unit *label, intptr_t addend) -{ - TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) - + sizeof(tcg_target_ulong) * nlong); - - n->label = label; - n->addend = addend; - n->rtype = rtype; - n->nlong = nlong; - return n; -} - -static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) -{ - TCGLabelPoolData *i, **pp; - int nlong = n->nlong; - - /* Insertion sort on the pool. */ - for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) { - if (nlong > i->nlong) { - break; - } - if (nlong < i->nlong) { - continue; - } - if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) { - break; - } - } - n->next = *pp; - *pp = n; -} - -/* The "usual" for generic integer code. */ -static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, - tcg_insn_unit *label, intptr_t addend) -{ - TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend); - n->data[0] = d; - new_pool_insert(s, n); -} - -/* For v64 or v128, depending on the host. */ -static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1) -{ - TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend); - n->data[0] = d0; - n->data[1] = d1; - new_pool_insert(s, n); -} - -/* For v128 or v256, depending on the host. */ -static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3) -{ - TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend); - n->data[0] = d0; - n->data[1] = d1; - n->data[2] = d2; - n->data[3] = d3; - new_pool_insert(s, n); -} - -/* For v256, for 32-bit host. */ -static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3, tcg_target_ulong d4, - tcg_target_ulong d5, tcg_target_ulong d6, - tcg_target_ulong d7) -{ - TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend); - n->data[0] = d0; - n->data[1] = d1; - n->data[2] = d2; - n->data[3] = d3; - n->data[4] = d4; - n->data[5] = d5; - n->data[6] = d6; - n->data[7] = d7; - new_pool_insert(s, n); -} - -/* To be provided by cpu/tcg-target.inc.c. */ -static void tcg_out_nop_fill(tcg_insn_unit *p, int count); - -static int tcg_out_pool_finalize(TCGContext *s) -{ - TCGLabelPoolData *p = s->pool_labels; - TCGLabelPoolData *l = NULL; - void *a; - - if (p == NULL) { - return 0; - } - - /* ??? Round up to qemu_icache_linesize, but then do not round - again when allocating the next TranslationBlock structure. */ - a = (void *)ROUND_UP((uintptr_t)s->code_ptr, - sizeof(tcg_target_ulong) * p->nlong); - tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); - s->data_gen_ptr = a; - - for (; p != NULL; p = p->next) { - size_t size = sizeof(tcg_target_ulong) * p->nlong; - if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { - if (unlikely(a > s->code_gen_highwater)) { - return -1; - } - memcpy(a, p->data, size); - a += size; - l = p; - } - if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) { - return -2; - } - } - - s->code_ptr = a; - return 0; -} diff --git a/tcg/tcg.c b/tcg/tcg.c index 1362bc6101..62f299e36e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -65,7 +65,7 @@ #include "exec/log.h" #include "sysemu/sysemu.h" -/* Forward declarations for functions declared in tcg-target.inc.c and +/* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); @@ -101,7 +101,7 @@ static void tcg_register_jit_int(void *buf, size_t size, size_t debug_frame_size) __attribute__((unused)); -/* Forward declarations for functions declared and used in tcg-target.inc.c. */ +/* Forward declarations for functions declared and used in tcg-target.c.inc. */ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type); static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, @@ -341,7 +341,7 @@ static void set_jmp_reset_offset(TCGContext *s, int which) assert(s->tb_jmp_reset_offset[which] == off); } -#include "tcg-target.inc.c" +#include "tcg-target.c.inc" /* compare a pointer @ptr and a tb_tc @s */ static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) diff --git a/tcg/tci/README b/tcg/tci/README index 386c3c7507..9bb7d7a5d3 100644 --- a/tcg/tci/README +++ b/tcg/tci/README @@ -21,7 +21,7 @@ This is what TCI (Tiny Code Interpreter) does. 2) Implementation Like each TCG host frontend, TCI implements the code generator in -tcg-target.inc.c, tcg-target.h. Both files are in directory tcg/tci. +tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci. The additional file tcg/tci.c adds the interpreter. @@ -123,7 +123,7 @@ u1 = linux-user-test works would also improve speed for hosts which support byte alignment). * A better disassembler for the pseudo code would be nice (a very primitive - disassembler is included in tcg-target.inc.c). + disassembler is included in tcg-target.c.inc). * It might be useful to have a runtime option which selects the native TCG or TCI, so QEMU would have to include two TCGs. Today, selecting TCI diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc new file mode 100644 index 0000000000..992d50cb1e --- /dev/null +++ b/tcg/tci/tcg-target.c.inc @@ -0,0 +1,896 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2009, 2011 Stefan Weil + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* TODO list: + * - See TODO comments in code. + */ + +/* Marker for missing code. */ +#define TODO() \ + do { \ + fprintf(stderr, "TODO %s:%u: %s()\n", \ + __FILE__, __LINE__, __func__); \ + tcg_abort(); \ + } while (0) + +/* Bitfield n...m (in 32 bit value). */ +#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) + +/* Macros used in tcg_target_op_defs. */ +#define R "r" +#define RI "ri" +#if TCG_TARGET_REG_BITS == 32 +# define R64 "r", "r" +#else +# define R64 "r" +#endif +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS +# define L "L", "L" +# define S "S", "S" +#else +# define L "L" +# define S "S" +#endif + +/* TODO: documentation. */ +static const TCGTargetOpDef tcg_target_op_defs[] = { + { INDEX_op_exit_tb, { NULL } }, + { INDEX_op_goto_tb, { NULL } }, + { INDEX_op_br, { NULL } }, + + { INDEX_op_ld8u_i32, { R, R } }, + { INDEX_op_ld8s_i32, { R, R } }, + { INDEX_op_ld16u_i32, { R, R } }, + { INDEX_op_ld16s_i32, { R, R } }, + { INDEX_op_ld_i32, { R, R } }, + { INDEX_op_st8_i32, { R, R } }, + { INDEX_op_st16_i32, { R, R } }, + { INDEX_op_st_i32, { R, R } }, + + { INDEX_op_add_i32, { R, RI, RI } }, + { INDEX_op_sub_i32, { R, RI, RI } }, + { INDEX_op_mul_i32, { R, RI, RI } }, +#if TCG_TARGET_HAS_div_i32 + { INDEX_op_div_i32, { R, R, R } }, + { INDEX_op_divu_i32, { R, R, R } }, + { INDEX_op_rem_i32, { R, R, R } }, + { INDEX_op_remu_i32, { R, R, R } }, +#elif TCG_TARGET_HAS_div2_i32 + { INDEX_op_div2_i32, { R, R, "0", "1", R } }, + { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, +#endif + /* TODO: Does R, RI, RI result in faster code than R, R, RI? + If both operands are constants, we can optimize. */ + { INDEX_op_and_i32, { R, RI, RI } }, +#if TCG_TARGET_HAS_andc_i32 + { INDEX_op_andc_i32, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_eqv_i32 + { INDEX_op_eqv_i32, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_nand_i32 + { INDEX_op_nand_i32, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_nor_i32 + { INDEX_op_nor_i32, { R, RI, RI } }, +#endif + { INDEX_op_or_i32, { R, RI, RI } }, +#if TCG_TARGET_HAS_orc_i32 + { INDEX_op_orc_i32, { R, RI, RI } }, +#endif + { INDEX_op_xor_i32, { R, RI, RI } }, + { INDEX_op_shl_i32, { R, RI, RI } }, + { INDEX_op_shr_i32, { R, RI, RI } }, + { INDEX_op_sar_i32, { R, RI, RI } }, +#if TCG_TARGET_HAS_rot_i32 + { INDEX_op_rotl_i32, { R, RI, RI } }, + { INDEX_op_rotr_i32, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_deposit_i32 + { INDEX_op_deposit_i32, { R, "0", R } }, +#endif + + { INDEX_op_brcond_i32, { R, RI } }, + + { INDEX_op_setcond_i32, { R, R, RI } }, +#if TCG_TARGET_REG_BITS == 64 + { INDEX_op_setcond_i64, { R, R, RI } }, +#endif /* TCG_TARGET_REG_BITS == 64 */ + +#if TCG_TARGET_REG_BITS == 32 + /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ + { INDEX_op_add2_i32, { R, R, R, R, R, R } }, + { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, + { INDEX_op_brcond2_i32, { R, R, RI, RI } }, + { INDEX_op_mulu2_i32, { R, R, R, R } }, + { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, +#endif + +#if TCG_TARGET_HAS_not_i32 + { INDEX_op_not_i32, { R, R } }, +#endif +#if TCG_TARGET_HAS_neg_i32 + { INDEX_op_neg_i32, { R, R } }, +#endif + +#if TCG_TARGET_REG_BITS == 64 + { INDEX_op_ld8u_i64, { R, R } }, + { INDEX_op_ld8s_i64, { R, R } }, + { INDEX_op_ld16u_i64, { R, R } }, + { INDEX_op_ld16s_i64, { R, R } }, + { INDEX_op_ld32u_i64, { R, R } }, + { INDEX_op_ld32s_i64, { R, R } }, + { INDEX_op_ld_i64, { R, R } }, + + { INDEX_op_st8_i64, { R, R } }, + { INDEX_op_st16_i64, { R, R } }, + { INDEX_op_st32_i64, { R, R } }, + { INDEX_op_st_i64, { R, R } }, + + { INDEX_op_add_i64, { R, RI, RI } }, + { INDEX_op_sub_i64, { R, RI, RI } }, + { INDEX_op_mul_i64, { R, RI, RI } }, +#if TCG_TARGET_HAS_div_i64 + { INDEX_op_div_i64, { R, R, R } }, + { INDEX_op_divu_i64, { R, R, R } }, + { INDEX_op_rem_i64, { R, R, R } }, + { INDEX_op_remu_i64, { R, R, R } }, +#elif TCG_TARGET_HAS_div2_i64 + { INDEX_op_div2_i64, { R, R, "0", "1", R } }, + { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, +#endif + { INDEX_op_and_i64, { R, RI, RI } }, +#if TCG_TARGET_HAS_andc_i64 + { INDEX_op_andc_i64, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_eqv_i64 + { INDEX_op_eqv_i64, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_nand_i64 + { INDEX_op_nand_i64, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_nor_i64 + { INDEX_op_nor_i64, { R, RI, RI } }, +#endif + { INDEX_op_or_i64, { R, RI, RI } }, +#if TCG_TARGET_HAS_orc_i64 + { INDEX_op_orc_i64, { R, RI, RI } }, +#endif + { INDEX_op_xor_i64, { R, RI, RI } }, + { INDEX_op_shl_i64, { R, RI, RI } }, + { INDEX_op_shr_i64, { R, RI, RI } }, + { INDEX_op_sar_i64, { R, RI, RI } }, +#if TCG_TARGET_HAS_rot_i64 + { INDEX_op_rotl_i64, { R, RI, RI } }, + { INDEX_op_rotr_i64, { R, RI, RI } }, +#endif +#if TCG_TARGET_HAS_deposit_i64 + { INDEX_op_deposit_i64, { R, "0", R } }, +#endif + { INDEX_op_brcond_i64, { R, RI } }, + +#if TCG_TARGET_HAS_ext8s_i64 + { INDEX_op_ext8s_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext16s_i64 + { INDEX_op_ext16s_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext32s_i64 + { INDEX_op_ext32s_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext8u_i64 + { INDEX_op_ext8u_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext16u_i64 + { INDEX_op_ext16u_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext32u_i64 + { INDEX_op_ext32u_i64, { R, R } }, +#endif + { INDEX_op_ext_i32_i64, { R, R } }, + { INDEX_op_extu_i32_i64, { R, R } }, +#if TCG_TARGET_HAS_bswap16_i64 + { INDEX_op_bswap16_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_bswap32_i64 + { INDEX_op_bswap32_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_bswap64_i64 + { INDEX_op_bswap64_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_not_i64 + { INDEX_op_not_i64, { R, R } }, +#endif +#if TCG_TARGET_HAS_neg_i64 + { INDEX_op_neg_i64, { R, R } }, +#endif +#endif /* TCG_TARGET_REG_BITS == 64 */ + + { INDEX_op_qemu_ld_i32, { R, L } }, + { INDEX_op_qemu_ld_i64, { R64, L } }, + + { INDEX_op_qemu_st_i32, { R, S } }, + { INDEX_op_qemu_st_i64, { R64, S } }, + +#if TCG_TARGET_HAS_ext8s_i32 + { INDEX_op_ext8s_i32, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext16s_i32 + { INDEX_op_ext16s_i32, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext8u_i32 + { INDEX_op_ext8u_i32, { R, R } }, +#endif +#if TCG_TARGET_HAS_ext16u_i32 + { INDEX_op_ext16u_i32, { R, R } }, +#endif + +#if TCG_TARGET_HAS_bswap16_i32 + { INDEX_op_bswap16_i32, { R, R } }, +#endif +#if TCG_TARGET_HAS_bswap32_i32 + { INDEX_op_bswap32_i32, { R, R } }, +#endif + + { INDEX_op_mb, { } }, + { -1 }, +}; + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + int i, n = ARRAY_SIZE(tcg_target_op_defs); + + for (i = 0; i < n; ++i) { + if (tcg_target_op_defs[i].op == op) { + return &tcg_target_op_defs[i]; + } + } + return NULL; +} + +static const int tcg_target_reg_alloc_order[] = { + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, +#if 0 /* used for TCG_REG_CALL_STACK */ + TCG_REG_R4, +#endif + TCG_REG_R5, + TCG_REG_R6, + TCG_REG_R7, +#if TCG_TARGET_NB_REGS >= 16 + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, + TCG_REG_R13, + TCG_REG_R14, + TCG_REG_R15, +#endif +}; + +#if MAX_OPC_PARAM_IARGS != 6 +# error Fix needed, number of supported input arguments changed! +#endif + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, +#if 0 /* used for TCG_REG_CALL_STACK */ + TCG_REG_R4, +#endif + TCG_REG_R5, + TCG_REG_R6, +#if TCG_TARGET_REG_BITS == 32 + /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ + TCG_REG_R7, +#if TCG_TARGET_NB_REGS >= 16 + TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, +#else +# error Too few input registers available +#endif +#endif +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_R0, +#if TCG_TARGET_REG_BITS == 32 + TCG_REG_R1 +#endif +}; + +#ifdef CONFIG_DEBUG_TCG +static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "r00", + "r01", + "r02", + "r03", + "r04", + "r05", + "r06", + "r07", +#if TCG_TARGET_NB_REGS >= 16 + "r08", + "r09", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", +#if TCG_TARGET_NB_REGS >= 32 + "r16", + "r17", + "r18", + "r19", + "r20", + "r21", + "r22", + "r23", + "r24", + "r25", + "r26", + "r27", + "r28", + "r29", + "r30", + "r31" +#endif +#endif +}; +#endif + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + /* tcg_out_reloc always uses the same type, addend. */ + tcg_debug_assert(type == sizeof(tcg_target_long)); + tcg_debug_assert(addend == 0); + tcg_debug_assert(value != 0); + if (TCG_TARGET_REG_BITS == 32) { + tcg_patch32(code_ptr, value); + } else { + tcg_patch64(code_ptr, value); + } + return true; +} + +/* Parse target specific constraints. */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': + case 'L': /* qemu_ld constraint */ + case 'S': /* qemu_st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; + break; + default: + return NULL; + } + return ct_str; +} + +#if defined(CONFIG_DEBUG_TCG_INTERPRETER) +/* Show current bytecode. Used by tcg interpreter. */ +void tci_disas(uint8_t opc) +{ + const TCGOpDef *def = &tcg_op_defs[opc]; + fprintf(stderr, "TCG %s %u, %u, %u\n", + def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); +} +#endif + +/* Write value (native size). */ +static void tcg_out_i(TCGContext *s, tcg_target_ulong v) +{ + if (TCG_TARGET_REG_BITS == 32) { + tcg_out32(s, v); + } else { + tcg_out64(s, v); + } +} + +/* Write opcode. */ +static void tcg_out_op_t(TCGContext *s, TCGOpcode op) +{ + tcg_out8(s, op); + tcg_out8(s, 0); +} + +/* Write register. */ +static void tcg_out_r(TCGContext *s, TCGArg t0) +{ + tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); + tcg_out8(s, t0); +} + +/* Write register or constant (native size). */ +static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) +{ + if (const_arg) { + tcg_debug_assert(const_arg == 1); + tcg_out8(s, TCG_CONST); + tcg_out_i(s, arg); + } else { + tcg_out_r(s, arg); + } +} + +/* Write register or constant (32 bit). */ +static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) +{ + if (const_arg) { + tcg_debug_assert(const_arg == 1); + tcg_out8(s, TCG_CONST); + tcg_out32(s, arg); + } else { + tcg_out_r(s, arg); + } +} + +#if TCG_TARGET_REG_BITS == 64 +/* Write register or constant (64 bit). */ +static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) +{ + if (const_arg) { + tcg_debug_assert(const_arg == 1); + tcg_out8(s, TCG_CONST); + tcg_out64(s, arg); + } else { + tcg_out_r(s, arg); + } +} +#endif + +/* Write label. */ +static void tci_out_label(TCGContext *s, TCGLabel *label) +{ + if (label->has_value) { + tcg_out_i(s, label->u.value); + tcg_debug_assert(label->u.value); + } else { + tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); + s->code_ptr += sizeof(tcg_target_ulong); + } +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, + intptr_t arg2) +{ + uint8_t *old_code_ptr = s->code_ptr; + if (type == TCG_TYPE_I32) { + tcg_out_op_t(s, INDEX_op_ld_i32); + tcg_out_r(s, ret); + tcg_out_r(s, arg1); + tcg_out32(s, arg2); + } else { + tcg_debug_assert(type == TCG_TYPE_I64); +#if TCG_TARGET_REG_BITS == 64 + tcg_out_op_t(s, INDEX_op_ld_i64); + tcg_out_r(s, ret); + tcg_out_r(s, arg1); + tcg_debug_assert(arg2 == (int32_t)arg2); + tcg_out32(s, arg2); +#else + TODO(); +#endif + } + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + uint8_t *old_code_ptr = s->code_ptr; + tcg_debug_assert(ret != arg); +#if TCG_TARGET_REG_BITS == 32 + tcg_out_op_t(s, INDEX_op_mov_i32); +#else + tcg_out_op_t(s, INDEX_op_mov_i64); +#endif + tcg_out_r(s, ret); + tcg_out_r(s, arg); + old_code_ptr[1] = s->code_ptr - old_code_ptr; + return true; +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg t0, tcg_target_long arg) +{ + uint8_t *old_code_ptr = s->code_ptr; + uint32_t arg32 = arg; + if (type == TCG_TYPE_I32 || arg == arg32) { + tcg_out_op_t(s, INDEX_op_movi_i32); + tcg_out_r(s, t0); + tcg_out32(s, arg32); + } else { + tcg_debug_assert(type == TCG_TYPE_I64); +#if TCG_TARGET_REG_BITS == 64 + tcg_out_op_t(s, INDEX_op_movi_i64); + tcg_out_r(s, t0); + tcg_out64(s, arg); +#else + TODO(); +#endif + } + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +{ + uint8_t *old_code_ptr = s->code_ptr; + tcg_out_op_t(s, INDEX_op_call); + tcg_out_ri(s, 1, (uintptr_t)arg); + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, + const int *const_args) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, opc); + + switch (opc) { + case INDEX_op_exit_tb: + tcg_out64(s, args[0]); + break; + case INDEX_op_goto_tb: + if (s->tb_jmp_insn_offset) { + /* Direct jump method. */ + /* Align for atomic patching and thread safety */ + s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4); + s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + tcg_out32(s, 0); + } else { + /* Indirect jump method. */ + TODO(); + } + set_jmp_reset_offset(s, args[0]); + break; + case INDEX_op_br: + tci_out_label(s, arg_label(args[0])); + break; + case INDEX_op_setcond_i32: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_ri32(s, const_args[2], args[2]); + tcg_out8(s, args[3]); /* condition */ + break; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_setcond2_i32: + /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out_ri32(s, const_args[3], args[3]); + tcg_out_ri32(s, const_args[4], args[4]); + tcg_out8(s, args[5]); /* condition */ + break; +#elif TCG_TARGET_REG_BITS == 64 + case INDEX_op_setcond_i64: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_ri64(s, const_args[2], args[2]); + tcg_out8(s, args[3]); /* condition */ + break; +#endif + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_debug_assert(args[2] == (int32_t)args[2]); + tcg_out32(s, args[2]); + break; + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ + case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ + case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ + case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ + case INDEX_op_or_i32: + case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + tcg_out_r(s, args[0]); + tcg_out_ri32(s, const_args[1], args[1]); + tcg_out_ri32(s, const_args[2], args[2]); + break; + case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_debug_assert(args[3] <= UINT8_MAX); + tcg_out8(s, args[3]); + tcg_debug_assert(args[4] <= UINT8_MAX); + tcg_out8(s, args[4]); + break; + +#if TCG_TARGET_REG_BITS == 64 + case INDEX_op_add_i64: + case INDEX_op_sub_i64: + case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ + case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ + case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ + case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ + case INDEX_op_or_i64: + case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ + case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ + tcg_out_r(s, args[0]); + tcg_out_ri64(s, const_args[1], args[1]); + tcg_out_ri64(s, const_args[2], args[2]); + break; + case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_debug_assert(args[3] <= UINT8_MAX); + tcg_out8(s, args[3]); + tcg_debug_assert(args[4] <= UINT8_MAX); + tcg_out8(s, args[4]); + break; + case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ + TODO(); + break; + case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ + case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ + TODO(); + break; + case INDEX_op_brcond_i64: + tcg_out_r(s, args[0]); + tcg_out_ri64(s, const_args[1], args[1]); + tcg_out8(s, args[2]); /* condition */ + tci_out_label(s, arg_label(args[3])); + break; + case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ + case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ + case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ + case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ + case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ + case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ + case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ + case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ + case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ + case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: +#endif /* TCG_TARGET_REG_BITS == 64 */ + case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ + case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ + case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ + case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ + case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ + case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ + case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ + case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + break; + case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ + case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ + case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ + case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ + tcg_out_r(s, args[0]); + tcg_out_ri32(s, const_args[1], args[1]); + tcg_out_ri32(s, const_args[2], args[2]); + break; + case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ + case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ + TODO(); + break; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out_r(s, args[3]); + tcg_out_r(s, args[4]); + tcg_out_r(s, args[5]); + break; + case INDEX_op_brcond2_i32: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_ri32(s, const_args[3], args[3]); + tcg_out8(s, args[4]); /* condition */ + tci_out_label(s, arg_label(args[5])); + break; + case INDEX_op_mulu2_i32: + tcg_out_r(s, args[0]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); + tcg_out_r(s, args[3]); + break; +#endif + case INDEX_op_brcond_i32: + tcg_out_r(s, args[0]); + tcg_out_ri32(s, const_args[1], args[1]); + tcg_out8(s, args[2]); /* condition */ + tci_out_label(s, arg_label(args[3])); + break; + case INDEX_op_qemu_ld_i32: + tcg_out_r(s, *args++); + tcg_out_r(s, *args++); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_out_r(s, *args++); + } + tcg_out_i(s, *args++); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS == 32) { + tcg_out_r(s, *args++); + } + tcg_out_r(s, *args++); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_out_r(s, *args++); + } + tcg_out_i(s, *args++); + break; + case INDEX_op_qemu_st_i32: + tcg_out_r(s, *args++); + tcg_out_r(s, *args++); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_out_r(s, *args++); + } + tcg_out_i(s, *args++); + break; + case INDEX_op_qemu_st_i64: + tcg_out_r(s, *args++); + if (TCG_TARGET_REG_BITS == 32) { + tcg_out_r(s, *args++); + } + tcg_out_r(s, *args++); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + tcg_out_r(s, *args++); + } + tcg_out_i(s, *args++); + break; + case INDEX_op_mb: + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + tcg_abort(); + } + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, + intptr_t arg2) +{ + uint8_t *old_code_ptr = s->code_ptr; + if (type == TCG_TYPE_I32) { + tcg_out_op_t(s, INDEX_op_st_i32); + tcg_out_r(s, arg); + tcg_out_r(s, arg1); + tcg_out32(s, arg2); + } else { + tcg_debug_assert(type == TCG_TYPE_I64); +#if TCG_TARGET_REG_BITS == 64 + tcg_out_op_t(s, INDEX_op_st_i64); + tcg_out_r(s, arg); + tcg_out_r(s, arg1); + tcg_out32(s, arg2); +#else + TODO(); +#endif + } + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + +static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + return false; +} + +/* Test if a constant matches the constraint. */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + /* No need to return 0 or 1, 0 or != 0 is good enough. */ + return arg_ct->ct & TCG_CT_CONST; +} + +static void tcg_target_init(TCGContext *s) +{ +#if defined(CONFIG_DEBUG_TCG_INTERPRETER) + const char *envval = getenv("DEBUG_TCG"); + if (envval) { + qemu_set_log(strtol(envval, NULL, 0)); + } +#endif + + /* The current code uses uint8_t for tcg operations. */ + tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX); + + /* Registers available for 32 bit operations. */ + tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; + /* Registers available for 64 bit operations. */ + tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; + /* TODO: Which registers should be set here? */ + tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + + /* We use negative offsets from "sp" so that we can distinguish + stores that might pretend to be call arguments. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, + -CPU_TEMP_BUF_NLONGS * sizeof(long), + CPU_TEMP_BUF_NLONGS * sizeof(long)); +} + +/* Generate global QEMU prologue and epilogue code. */ +static inline void tcg_target_qemu_prologue(TCGContext *s) +{ +} diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c deleted file mode 100644 index 992d50cb1e..0000000000 --- a/tcg/tci/tcg-target.inc.c +++ /dev/null @@ -1,896 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2009, 2011 Stefan Weil - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* TODO list: - * - See TODO comments in code. - */ - -/* Marker for missing code. */ -#define TODO() \ - do { \ - fprintf(stderr, "TODO %s:%u: %s()\n", \ - __FILE__, __LINE__, __func__); \ - tcg_abort(); \ - } while (0) - -/* Bitfield n...m (in 32 bit value). */ -#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) - -/* Macros used in tcg_target_op_defs. */ -#define R "r" -#define RI "ri" -#if TCG_TARGET_REG_BITS == 32 -# define R64 "r", "r" -#else -# define R64 "r" -#endif -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -# define L "L", "L" -# define S "S", "S" -#else -# define L "L" -# define S "S" -#endif - -/* TODO: documentation. */ -static const TCGTargetOpDef tcg_target_op_defs[] = { - { INDEX_op_exit_tb, { NULL } }, - { INDEX_op_goto_tb, { NULL } }, - { INDEX_op_br, { NULL } }, - - { INDEX_op_ld8u_i32, { R, R } }, - { INDEX_op_ld8s_i32, { R, R } }, - { INDEX_op_ld16u_i32, { R, R } }, - { INDEX_op_ld16s_i32, { R, R } }, - { INDEX_op_ld_i32, { R, R } }, - { INDEX_op_st8_i32, { R, R } }, - { INDEX_op_st16_i32, { R, R } }, - { INDEX_op_st_i32, { R, R } }, - - { INDEX_op_add_i32, { R, RI, RI } }, - { INDEX_op_sub_i32, { R, RI, RI } }, - { INDEX_op_mul_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i32 - { INDEX_op_div_i32, { R, R, R } }, - { INDEX_op_divu_i32, { R, R, R } }, - { INDEX_op_rem_i32, { R, R, R } }, - { INDEX_op_remu_i32, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i32 - { INDEX_op_div2_i32, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i32, { R, R, "0", "1", R } }, -#endif - /* TODO: Does R, RI, RI result in faster code than R, R, RI? - If both operands are constants, we can optimize. */ - { INDEX_op_and_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i32 - { INDEX_op_andc_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i32 - { INDEX_op_eqv_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i32 - { INDEX_op_nand_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i32 - { INDEX_op_nor_i32, { R, RI, RI } }, -#endif - { INDEX_op_or_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i32 - { INDEX_op_orc_i32, { R, RI, RI } }, -#endif - { INDEX_op_xor_i32, { R, RI, RI } }, - { INDEX_op_shl_i32, { R, RI, RI } }, - { INDEX_op_shr_i32, { R, RI, RI } }, - { INDEX_op_sar_i32, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i32 - { INDEX_op_rotl_i32, { R, RI, RI } }, - { INDEX_op_rotr_i32, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i32 - { INDEX_op_deposit_i32, { R, "0", R } }, -#endif - - { INDEX_op_brcond_i32, { R, RI } }, - - { INDEX_op_setcond_i32, { R, R, RI } }, -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_setcond_i64, { R, R, RI } }, -#endif /* TCG_TARGET_REG_BITS == 64 */ - -#if TCG_TARGET_REG_BITS == 32 - /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ - { INDEX_op_add2_i32, { R, R, R, R, R, R } }, - { INDEX_op_sub2_i32, { R, R, R, R, R, R } }, - { INDEX_op_brcond2_i32, { R, R, RI, RI } }, - { INDEX_op_mulu2_i32, { R, R, R, R } }, - { INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, -#endif - -#if TCG_TARGET_HAS_not_i32 - { INDEX_op_not_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i32 - { INDEX_op_neg_i32, { R, R } }, -#endif - -#if TCG_TARGET_REG_BITS == 64 - { INDEX_op_ld8u_i64, { R, R } }, - { INDEX_op_ld8s_i64, { R, R } }, - { INDEX_op_ld16u_i64, { R, R } }, - { INDEX_op_ld16s_i64, { R, R } }, - { INDEX_op_ld32u_i64, { R, R } }, - { INDEX_op_ld32s_i64, { R, R } }, - { INDEX_op_ld_i64, { R, R } }, - - { INDEX_op_st8_i64, { R, R } }, - { INDEX_op_st16_i64, { R, R } }, - { INDEX_op_st32_i64, { R, R } }, - { INDEX_op_st_i64, { R, R } }, - - { INDEX_op_add_i64, { R, RI, RI } }, - { INDEX_op_sub_i64, { R, RI, RI } }, - { INDEX_op_mul_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_div_i64 - { INDEX_op_div_i64, { R, R, R } }, - { INDEX_op_divu_i64, { R, R, R } }, - { INDEX_op_rem_i64, { R, R, R } }, - { INDEX_op_remu_i64, { R, R, R } }, -#elif TCG_TARGET_HAS_div2_i64 - { INDEX_op_div2_i64, { R, R, "0", "1", R } }, - { INDEX_op_divu2_i64, { R, R, "0", "1", R } }, -#endif - { INDEX_op_and_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_andc_i64 - { INDEX_op_andc_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_eqv_i64 - { INDEX_op_eqv_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nand_i64 - { INDEX_op_nand_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_nor_i64 - { INDEX_op_nor_i64, { R, RI, RI } }, -#endif - { INDEX_op_or_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_orc_i64 - { INDEX_op_orc_i64, { R, RI, RI } }, -#endif - { INDEX_op_xor_i64, { R, RI, RI } }, - { INDEX_op_shl_i64, { R, RI, RI } }, - { INDEX_op_shr_i64, { R, RI, RI } }, - { INDEX_op_sar_i64, { R, RI, RI } }, -#if TCG_TARGET_HAS_rot_i64 - { INDEX_op_rotl_i64, { R, RI, RI } }, - { INDEX_op_rotr_i64, { R, RI, RI } }, -#endif -#if TCG_TARGET_HAS_deposit_i64 - { INDEX_op_deposit_i64, { R, "0", R } }, -#endif - { INDEX_op_brcond_i64, { R, RI } }, - -#if TCG_TARGET_HAS_ext8s_i64 - { INDEX_op_ext8s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i64 - { INDEX_op_ext16s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32s_i64 - { INDEX_op_ext32s_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i64 - { INDEX_op_ext8u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i64 - { INDEX_op_ext16u_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext32u_i64 - { INDEX_op_ext32u_i64, { R, R } }, -#endif - { INDEX_op_ext_i32_i64, { R, R } }, - { INDEX_op_extu_i32_i64, { R, R } }, -#if TCG_TARGET_HAS_bswap16_i64 - { INDEX_op_bswap16_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i64 - { INDEX_op_bswap32_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap64_i64 - { INDEX_op_bswap64_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_not_i64 - { INDEX_op_not_i64, { R, R } }, -#endif -#if TCG_TARGET_HAS_neg_i64 - { INDEX_op_neg_i64, { R, R } }, -#endif -#endif /* TCG_TARGET_REG_BITS == 64 */ - - { INDEX_op_qemu_ld_i32, { R, L } }, - { INDEX_op_qemu_ld_i64, { R64, L } }, - - { INDEX_op_qemu_st_i32, { R, S } }, - { INDEX_op_qemu_st_i64, { R64, S } }, - -#if TCG_TARGET_HAS_ext8s_i32 - { INDEX_op_ext8s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16s_i32 - { INDEX_op_ext16s_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext8u_i32 - { INDEX_op_ext8u_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_ext16u_i32 - { INDEX_op_ext16u_i32, { R, R } }, -#endif - -#if TCG_TARGET_HAS_bswap16_i32 - { INDEX_op_bswap16_i32, { R, R } }, -#endif -#if TCG_TARGET_HAS_bswap32_i32 - { INDEX_op_bswap32_i32, { R, R } }, -#endif - - { INDEX_op_mb, { } }, - { -1 }, -}; - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - int i, n = ARRAY_SIZE(tcg_target_op_defs); - - for (i = 0; i < n; ++i) { - if (tcg_target_op_defs[i].op == op) { - return &tcg_target_op_defs[i]; - } - } - return NULL; -} - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ - TCG_REG_R4, -#endif - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, -#if TCG_TARGET_NB_REGS >= 16 - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15, -#endif -}; - -#if MAX_OPC_PARAM_IARGS != 6 -# error Fix needed, number of supported input arguments changed! -#endif - -static const int tcg_target_call_iarg_regs[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, -#if 0 /* used for TCG_REG_CALL_STACK */ - TCG_REG_R4, -#endif - TCG_REG_R5, - TCG_REG_R6, -#if TCG_TARGET_REG_BITS == 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R7, -#if TCG_TARGET_NB_REGS >= 16 - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, -#else -# error Too few input registers available -#endif -#endif -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_R1 -#endif -}; - -#ifdef CONFIG_DEBUG_TCG -static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "r00", - "r01", - "r02", - "r03", - "r04", - "r05", - "r06", - "r07", -#if TCG_TARGET_NB_REGS >= 16 - "r08", - "r09", - "r10", - "r11", - "r12", - "r13", - "r14", - "r15", -#if TCG_TARGET_NB_REGS >= 32 - "r16", - "r17", - "r18", - "r19", - "r20", - "r21", - "r22", - "r23", - "r24", - "r25", - "r26", - "r27", - "r28", - "r29", - "r30", - "r31" -#endif -#endif -}; -#endif - -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - /* tcg_out_reloc always uses the same type, addend. */ - tcg_debug_assert(type == sizeof(tcg_target_long)); - tcg_debug_assert(addend == 0); - tcg_debug_assert(value != 0); - if (TCG_TARGET_REG_BITS == 32) { - tcg_patch32(code_ptr, value); - } else { - tcg_patch64(code_ptr, value); - } - return true; -} - -/* Parse target specific constraints. */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - case 'L': /* qemu_ld constraint */ - case 'S': /* qemu_st constraint */ - ct->ct |= TCG_CT_REG; - ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; - break; - default: - return NULL; - } - return ct_str; -} - -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) -/* Show current bytecode. Used by tcg interpreter. */ -void tci_disas(uint8_t opc) -{ - const TCGOpDef *def = &tcg_op_defs[opc]; - fprintf(stderr, "TCG %s %u, %u, %u\n", - def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); -} -#endif - -/* Write value (native size). */ -static void tcg_out_i(TCGContext *s, tcg_target_ulong v) -{ - if (TCG_TARGET_REG_BITS == 32) { - tcg_out32(s, v); - } else { - tcg_out64(s, v); - } -} - -/* Write opcode. */ -static void tcg_out_op_t(TCGContext *s, TCGOpcode op) -{ - tcg_out8(s, op); - tcg_out8(s, 0); -} - -/* Write register. */ -static void tcg_out_r(TCGContext *s, TCGArg t0) -{ - tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); - tcg_out8(s, t0); -} - -/* Write register or constant (native size). */ -static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out_i(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -/* Write register or constant (32 bit). */ -static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out32(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -#if TCG_TARGET_REG_BITS == 64 -/* Write register or constant (64 bit). */ -static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out64(s, arg); - } else { - tcg_out_r(s, arg); - } -} -#endif - -/* Write label. */ -static void tci_out_label(TCGContext *s, TCGLabel *label) -{ - if (label->has_value) { - tcg_out_i(s, label->u.value); - tcg_debug_assert(label->u.value); - } else { - tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); - s->code_ptr += sizeof(tcg_target_ulong); - } -} - -static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, - intptr_t arg2) -{ - uint8_t *old_code_ptr = s->code_ptr; - if (type == TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_ld_i32); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_ld_i64); - tcg_out_r(s, ret); - tcg_out_r(s, arg1); - tcg_debug_assert(arg2 == (int32_t)arg2); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -{ - uint8_t *old_code_ptr = s->code_ptr; - tcg_debug_assert(ret != arg); -#if TCG_TARGET_REG_BITS == 32 - tcg_out_op_t(s, INDEX_op_mov_i32); -#else - tcg_out_op_t(s, INDEX_op_mov_i64); -#endif - tcg_out_r(s, ret); - tcg_out_r(s, arg); - old_code_ptr[1] = s->code_ptr - old_code_ptr; - return true; -} - -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg t0, tcg_target_long arg) -{ - uint8_t *old_code_ptr = s->code_ptr; - uint32_t arg32 = arg; - if (type == TCG_TYPE_I32 || arg == arg32) { - tcg_out_op_t(s, INDEX_op_movi_i32); - tcg_out_r(s, t0); - tcg_out32(s, arg32); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_movi_i64); - tcg_out_r(s, t0); - tcg_out64(s, arg); -#else - TODO(); -#endif - } - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) -{ - uint8_t *old_code_ptr = s->code_ptr; - tcg_out_op_t(s, INDEX_op_call); - tcg_out_ri(s, 1, (uintptr_t)arg); - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, - const int *const_args) -{ - uint8_t *old_code_ptr = s->code_ptr; - - tcg_out_op_t(s, opc); - - switch (opc) { - case INDEX_op_exit_tb: - tcg_out64(s, args[0]); - break; - case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* Direct jump method. */ - /* Align for atomic patching and thread safety */ - s->code_ptr = QEMU_ALIGN_PTR_UP(s->code_ptr, 4); - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); - tcg_out32(s, 0); - } else { - /* Indirect jump method. */ - TODO(); - } - set_jmp_reset_offset(s, args[0]); - break; - case INDEX_op_br: - tci_out_label(s, arg_label(args[0])); - break; - case INDEX_op_setcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - tcg_out8(s, args[3]); /* condition */ - break; -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_setcond2_i32: - /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_ri32(s, const_args[3], args[3]); - tcg_out_ri32(s, const_args[4], args[4]); - tcg_out8(s, args[5]); /* condition */ - break; -#elif TCG_TARGET_REG_BITS == 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_ri64(s, const_args[2], args[2]); - tcg_out8(s, args[3]); /* condition */ - break; -#endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: - case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: - case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_debug_assert(args[2] == (int32_t)args[2]); - tcg_out32(s, args[2]); - break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <= UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <= UINT8_MAX); - tcg_out8(s, args[4]); - break; - -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); - tcg_out_ri64(s, const_args[2], args[2]); - break; - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <= UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <= UINT8_MAX); - tcg_out8(s, args[4]); - break; - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - TODO(); - break; - case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - TODO(); - break; - case INDEX_op_brcond_i64: - tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: -#endif /* TCG_TARGET_REG_BITS == 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - break; - case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - TODO(); - break; -#if TCG_TARGET_REG_BITS == 32 - case INDEX_op_add2_i32: - case INDEX_op_sub2_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - tcg_out_r(s, args[4]); - tcg_out_r(s, args[5]); - break; - case INDEX_op_brcond2_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - tcg_out_ri32(s, const_args[3], args[3]); - tcg_out8(s, args[4]); /* condition */ - tci_out_label(s, arg_label(args[5])); - break; - case INDEX_op_mulu2_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - break; -#endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; - case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_st_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_st_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_mb: - break; - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, - intptr_t arg2) -{ - uint8_t *old_code_ptr = s->code_ptr; - if (type == TCG_TYPE_I32) { - tcg_out_op_t(s, INDEX_op_st_i32); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); - } else { - tcg_debug_assert(type == TCG_TYPE_I64); -#if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_st_i64); - tcg_out_r(s, arg); - tcg_out_r(s, arg1); - tcg_out32(s, arg2); -#else - TODO(); -#endif - } - old_code_ptr[1] = s->code_ptr - old_code_ptr; -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - return false; -} - -/* Test if a constant matches the constraint. */ -static int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - /* No need to return 0 or 1, 0 or != 0 is good enough. */ - return arg_ct->ct & TCG_CT_CONST; -} - -static void tcg_target_init(TCGContext *s) -{ -#if defined(CONFIG_DEBUG_TCG_INTERPRETER) - const char *envval = getenv("DEBUG_TCG"); - if (envval) { - qemu_set_log(strtol(envval, NULL, 0)); - } -#endif - - /* The current code uses uint8_t for tcg operations. */ - tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX); - - /* Registers available for 32 bit operations. */ - tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; - /* Registers available for 64 bit operations. */ - tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; - /* TODO: Which registers should be set here? */ - tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; - - s->reserved_regs = 0; - tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - - /* We use negative offsets from "sp" so that we can distinguish - stores that might pretend to be call arguments. */ - tcg_set_frame(s, TCG_REG_CALL_STACK, - -CPU_TEMP_BUF_NLONGS * sizeof(long), - CPU_TEMP_BUF_NLONGS * sizeof(long)); -} - -/* Generate global QEMU prologue and epilogue code. */ -static inline void tcg_target_qemu_prologue(TCGContext *s) -{ -} diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 43ef9628c4..06ffebd6db 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -116,7 +116,7 @@ static void usage_complete(int argc, char *argv[]) } /* keep wrappers separate but do not bother defining headers for all of them */ -#include "wrap.inc.c" +#include "wrap.c.inc" static void not_implemented(void) { diff --git a/tests/fp/wrap.c.inc b/tests/fp/wrap.c.inc new file mode 100644 index 0000000000..0cbd20013e --- /dev/null +++ b/tests/fp/wrap.c.inc @@ -0,0 +1,654 @@ +/* + * In this file we wrap QEMU FP functions to look like softfloat/testfloat's, + * so that we can use the testfloat infrastructure as-is. + * + * This file must be included directly from fp-test.c. We could compile it + * separately, but it would be tedious to add declarations for all the wrappers. + */ + +static signed char sf_tininess_to_qemu(uint_fast8_t mode) +{ + switch (mode) { + case softfloat_tininess_beforeRounding: + return float_tininess_before_rounding; + case softfloat_tininess_afterRounding: + return float_tininess_after_rounding; + default: + g_assert_not_reached(); + } +} + +static signed char sf_rounding_to_qemu(uint_fast8_t mode) +{ + switch (mode) { + case softfloat_round_near_even: + return float_round_nearest_even; + case softfloat_round_minMag: + return float_round_to_zero; + case softfloat_round_min: + return float_round_down; + case softfloat_round_max: + return float_round_up; + case softfloat_round_near_maxMag: + return float_round_ties_away; + case softfloat_round_odd: + return float_round_to_odd; + default: + g_assert_not_reached(); + } +} + +static uint_fast8_t qemu_flags_to_sf(uint8_t qflags) +{ + uint_fast8_t ret = 0; + + if (qflags & float_flag_invalid) { + ret |= softfloat_flag_invalid; + } + if (qflags & float_flag_divbyzero) { + ret |= softfloat_flag_infinite; + } + if (qflags & float_flag_overflow) { + ret |= softfloat_flag_overflow; + } + if (qflags & float_flag_underflow) { + ret |= softfloat_flag_underflow; + } + if (qflags & float_flag_inexact) { + ret |= softfloat_flag_inexact; + } + return ret; +} + +/* + * floatx80 and float128 cannot be cast between qemu and softfloat, because + * in softfloat the order of the fields depends on the host's endianness. + */ +static extFloat80_t qemu_to_soft80(floatx80 a) +{ + extFloat80_t ret; + + ret.signif = a.low; + ret.signExp = a.high; + return ret; +} + +static floatx80 soft_to_qemu80(extFloat80_t a) +{ + floatx80 ret; + + ret.low = a.signif; + ret.high = a.signExp; + return ret; +} + +static float128_t qemu_to_soft128(float128 a) +{ + float128_t ret; + struct uint128 *to = (struct uint128 *)&ret; + + to->v0 = a.low; + to->v64 = a.high; + return ret; +} + +static float128 soft_to_qemu128(float128_t a) +{ + struct uint128 *from = (struct uint128 *)&a; + float128 ret; + + ret.low = from->v0; + ret.high = from->v64; + return ret; +} + +/* conversions */ +#define WRAP_SF_TO_SF_IEEE(name, func, a_type, b_type) \ + static b_type##_t name(a_type##_t a) \ + { \ + a_type *ap = (a_type *)&a; \ + b_type ret; \ + \ + ret = func(*ap, true, &qsf); \ + return *(b_type##_t *)&ret; \ + } + +WRAP_SF_TO_SF_IEEE(qemu_f16_to_f32, float16_to_float32, float16, float32) +WRAP_SF_TO_SF_IEEE(qemu_f16_to_f64, float16_to_float64, float16, float64) + +WRAP_SF_TO_SF_IEEE(qemu_f32_to_f16, float32_to_float16, float32, float16) +WRAP_SF_TO_SF_IEEE(qemu_f64_to_f16, float64_to_float16, float64, float16) +#undef WRAP_SF_TO_SF_IEEE + +#define WRAP_SF_TO_SF(name, func, a_type, b_type) \ + static b_type##_t name(a_type##_t a) \ + { \ + a_type *ap = (a_type *)&a; \ + b_type ret; \ + \ + ret = func(*ap, &qsf); \ + return *(b_type##_t *)&ret; \ + } + +WRAP_SF_TO_SF(qemu_f32_to_f64, float32_to_float64, float32, float64) +WRAP_SF_TO_SF(qemu_f64_to_f32, float64_to_float32, float64, float32) +#undef WRAP_SF_TO_SF + +#define WRAP_SF_TO_80(name, func, type) \ + static void name(type##_t a, extFloat80_t *res) \ + { \ + floatx80 ret; \ + type *ap = (type *)&a; \ + \ + ret = func(*ap, &qsf); \ + *res = qemu_to_soft80(ret); \ + } + +WRAP_SF_TO_80(qemu_f32_to_extF80M, float32_to_floatx80, float32) +WRAP_SF_TO_80(qemu_f64_to_extF80M, float64_to_floatx80, float64) +#undef WRAP_SF_TO_80 + +#define WRAP_SF_TO_128(name, func, type) \ + static void name(type##_t a, float128_t *res) \ + { \ + float128 ret; \ + type *ap = (type *)&a; \ + \ + ret = func(*ap, &qsf); \ + *res = qemu_to_soft128(ret); \ + } + +WRAP_SF_TO_128(qemu_f32_to_f128M, float32_to_float128, float32) +WRAP_SF_TO_128(qemu_f64_to_f128M, float64_to_float128, float64) +#undef WRAP_SF_TO_128 + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_SF_TO_INT(name, func, type, fast_type) \ + static fast_type name(type##_t a, uint_fast8_t round, bool exact) \ + { \ + type *ap = (type *)&a; \ + \ + qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ + return func(*ap, &qsf); \ + } + +WRAP_SF_TO_INT(qemu_f16_to_ui32, float16_to_uint32, float16, uint_fast32_t) +WRAP_SF_TO_INT(qemu_f16_to_ui64, float16_to_uint64, float16, uint_fast64_t) + +WRAP_SF_TO_INT(qemu_f32_to_ui32, float32_to_uint32, float32, uint_fast32_t) +WRAP_SF_TO_INT(qemu_f32_to_ui64, float32_to_uint64, float32, uint_fast64_t) + +WRAP_SF_TO_INT(qemu_f64_to_ui32, float64_to_uint32, float64, uint_fast32_t) +WRAP_SF_TO_INT(qemu_f64_to_ui64, float64_to_uint64, float64, uint_fast64_t) + +WRAP_SF_TO_INT(qemu_f16_to_i32, float16_to_int32, float16, int_fast32_t) +WRAP_SF_TO_INT(qemu_f16_to_i64, float16_to_int64, float16, int_fast64_t) + +WRAP_SF_TO_INT(qemu_f32_to_i32, float32_to_int32, float32, int_fast32_t) +WRAP_SF_TO_INT(qemu_f32_to_i64, float32_to_int64, float32, int_fast64_t) + +WRAP_SF_TO_INT(qemu_f64_to_i32, float64_to_int32, float64, int_fast32_t) +WRAP_SF_TO_INT(qemu_f64_to_i64, float64_to_int64, float64, int_fast64_t) +#undef WRAP_SF_TO_INT + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_SF_TO_INT_MINMAG(name, func, type, fast_type) \ + static fast_type name(type##_t a, bool exact) \ + { \ + type *ap = (type *)&a; \ + \ + return func(*ap, &qsf); \ + } + +WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui32_r_minMag, + float16_to_uint32_round_to_zero, float16, uint_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui64_r_minMag, + float16_to_uint64_round_to_zero, float16, uint_fast64_t) + +WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i32_r_minMag, + float16_to_int32_round_to_zero, float16, int_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i64_r_minMag, + float16_to_int64_round_to_zero, float16, int_fast64_t) + +WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui32_r_minMag, + float32_to_uint32_round_to_zero, float32, uint_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui64_r_minMag, + float32_to_uint64_round_to_zero, float32, uint_fast64_t) + +WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i32_r_minMag, + float32_to_int32_round_to_zero, float32, int_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i64_r_minMag, + float32_to_int64_round_to_zero, float32, int_fast64_t) + +WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui32_r_minMag, + float64_to_uint32_round_to_zero, float64, uint_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui64_r_minMag, + float64_to_uint64_round_to_zero, float64, uint_fast64_t) + +WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i32_r_minMag, + float64_to_int32_round_to_zero, float64, int_fast32_t) +WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i64_r_minMag, + float64_to_int64_round_to_zero, float64, int_fast64_t) +#undef WRAP_SF_TO_INT_MINMAG + +#define WRAP_80_TO_SF(name, func, type) \ + static type##_t name(const extFloat80_t *ap) \ + { \ + floatx80 a; \ + type ret; \ + \ + a = soft_to_qemu80(*ap); \ + ret = func(a, &qsf); \ + return *(type##_t *)&ret; \ + } + +WRAP_80_TO_SF(qemu_extF80M_to_f32, floatx80_to_float32, float32) +WRAP_80_TO_SF(qemu_extF80M_to_f64, floatx80_to_float64, float64) +#undef WRAP_80_TO_SF + +#define WRAP_128_TO_SF(name, func, type) \ + static type##_t name(const float128_t *ap) \ + { \ + float128 a; \ + type ret; \ + \ + a = soft_to_qemu128(*ap); \ + ret = func(a, &qsf); \ + return *(type##_t *)&ret; \ + } + +WRAP_128_TO_SF(qemu_f128M_to_f32, float128_to_float32, float32) +WRAP_128_TO_SF(qemu_f128M_to_f64, float128_to_float64, float64) +#undef WRAP_128_TO_SF + +static void qemu_extF80M_to_f128M(const extFloat80_t *from, float128_t *to) +{ + floatx80 qfrom; + float128 qto; + + qfrom = soft_to_qemu80(*from); + qto = floatx80_to_float128(qfrom, &qsf); + *to = qemu_to_soft128(qto); +} + +static void qemu_f128M_to_extF80M(const float128_t *from, extFloat80_t *to) +{ + float128 qfrom; + floatx80 qto; + + qfrom = soft_to_qemu128(*from); + qto = float128_to_floatx80(qfrom, &qsf); + *to = qemu_to_soft80(qto); +} + +#define WRAP_INT_TO_SF(name, func, int_type, type) \ + static type##_t name(int_type a) \ + { \ + type ret; \ + \ + ret = func(a, &qsf); \ + return *(type##_t *)&ret; \ + } + +WRAP_INT_TO_SF(qemu_ui32_to_f16, uint32_to_float16, uint32_t, float16) +WRAP_INT_TO_SF(qemu_ui32_to_f32, uint32_to_float32, uint32_t, float32) +WRAP_INT_TO_SF(qemu_ui32_to_f64, uint32_to_float64, uint32_t, float64) + +WRAP_INT_TO_SF(qemu_ui64_to_f16, uint64_to_float16, uint64_t, float16) +WRAP_INT_TO_SF(qemu_ui64_to_f32, uint64_to_float32, uint64_t, float32) +WRAP_INT_TO_SF(qemu_ui64_to_f64, uint64_to_float64, uint64_t, float64) + +WRAP_INT_TO_SF(qemu_i32_to_f16, int32_to_float16, int32_t, float16) +WRAP_INT_TO_SF(qemu_i32_to_f32, int32_to_float32, int32_t, float32) +WRAP_INT_TO_SF(qemu_i32_to_f64, int32_to_float64, int32_t, float64) + +WRAP_INT_TO_SF(qemu_i64_to_f16, int64_to_float16, int64_t, float16) +WRAP_INT_TO_SF(qemu_i64_to_f32, int64_to_float32, int64_t, float32) +WRAP_INT_TO_SF(qemu_i64_to_f64, int64_to_float64, int64_t, float64) +#undef WRAP_INT_TO_SF + +#define WRAP_INT_TO_80(name, func, int_type) \ + static void name(int_type a, extFloat80_t *res) \ + { \ + floatx80 ret; \ + \ + ret = func(a, &qsf); \ + *res = qemu_to_soft80(ret); \ + } + +WRAP_INT_TO_80(qemu_i32_to_extF80M, int32_to_floatx80, int32_t) +WRAP_INT_TO_80(qemu_i64_to_extF80M, int64_to_floatx80, int64_t) +#undef WRAP_INT_TO_80 + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_80_TO_INT(name, func, fast_type) \ + static fast_type name(const extFloat80_t *ap, uint_fast8_t round, \ + bool exact) \ + { \ + floatx80 a; \ + \ + a = soft_to_qemu80(*ap); \ + qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ + return func(a, &qsf); \ + } + +WRAP_80_TO_INT(qemu_extF80M_to_i32, floatx80_to_int32, int_fast32_t) +WRAP_80_TO_INT(qemu_extF80M_to_i64, floatx80_to_int64, int_fast64_t) +#undef WRAP_80_TO_INT + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_80_TO_INT_MINMAG(name, func, fast_type) \ + static fast_type name(const extFloat80_t *ap, bool exact) \ + { \ + floatx80 a; \ + \ + a = soft_to_qemu80(*ap); \ + return func(a, &qsf); \ + } + +WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i32_r_minMag, + floatx80_to_int32_round_to_zero, int_fast32_t) +WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag, + floatx80_to_int64_round_to_zero, int_fast64_t) +#undef WRAP_80_TO_INT_MINMAG + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_128_TO_INT(name, func, fast_type) \ + static fast_type name(const float128_t *ap, uint_fast8_t round, \ + bool exact) \ + { \ + float128 a; \ + \ + a = soft_to_qemu128(*ap); \ + qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ + return func(a, &qsf); \ + } + +WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t) +WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t) + +WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t) +WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t) +#undef WRAP_128_TO_INT + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_128_TO_INT_MINMAG(name, func, fast_type) \ + static fast_type name(const float128_t *ap, bool exact) \ + { \ + float128 a; \ + \ + a = soft_to_qemu128(*ap); \ + return func(a, &qsf); \ + } + +WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i32_r_minMag, + float128_to_int32_round_to_zero, int_fast32_t) +WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i64_r_minMag, + float128_to_int64_round_to_zero, int_fast64_t) + +WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui32_r_minMag, + float128_to_uint32_round_to_zero, uint_fast32_t) +WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui64_r_minMag, + float128_to_uint64_round_to_zero, uint_fast64_t) +#undef WRAP_128_TO_INT_MINMAG + +#define WRAP_INT_TO_128(name, func, int_type) \ + static void name(int_type a, float128_t *res) \ + { \ + float128 ret; \ + \ + ret = func(a, &qsf); \ + *res = qemu_to_soft128(ret); \ + } + +WRAP_INT_TO_128(qemu_ui64_to_f128M, uint64_to_float128, uint64_t) + +WRAP_INT_TO_128(qemu_i32_to_f128M, int32_to_float128, int32_t) +WRAP_INT_TO_128(qemu_i64_to_f128M, int64_to_float128, int64_t) +#undef WRAP_INT_TO_128 + +/* Note: exact is ignored since qemu's softfloat assumes it is set */ +#define WRAP_ROUND_TO_INT(name, func, type) \ + static type##_t name(type##_t a, uint_fast8_t round, bool exact) \ + { \ + type *ap = (type *)&a; \ + type ret; \ + \ + qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ + ret = func(*ap, &qsf); \ + return *(type##_t *)&ret; \ + } + +WRAP_ROUND_TO_INT(qemu_f16_roundToInt, float16_round_to_int, float16) +WRAP_ROUND_TO_INT(qemu_f32_roundToInt, float32_round_to_int, float32) +WRAP_ROUND_TO_INT(qemu_f64_roundToInt, float64_round_to_int, float64) +#undef WRAP_ROUND_TO_INT + +static void qemu_extF80M_roundToInt(const extFloat80_t *ap, uint_fast8_t round, + bool exact, extFloat80_t *res) +{ + floatx80 a; + floatx80 ret; + + a = soft_to_qemu80(*ap); + qsf.float_rounding_mode = sf_rounding_to_qemu(round); + ret = floatx80_round_to_int(a, &qsf); + *res = qemu_to_soft80(ret); +} + +static void qemu_f128M_roundToInt(const float128_t *ap, uint_fast8_t round, + bool exact, float128_t *res) +{ + float128 a; + float128 ret; + + a = soft_to_qemu128(*ap); + qsf.float_rounding_mode = sf_rounding_to_qemu(round); + ret = float128_round_to_int(a, &qsf); + *res = qemu_to_soft128(ret); +} + +/* operations */ +#define WRAP1(name, func, type) \ + static type##_t name(type##_t a) \ + { \ + type *ap = (type *)&a; \ + type ret; \ + \ + ret = func(*ap, &qsf); \ + return *(type##_t *)&ret; \ + } + +#define WRAP2(name, func, type) \ + static type##_t name(type##_t a, type##_t b) \ + { \ + type *ap = (type *)&a; \ + type *bp = (type *)&b; \ + type ret; \ + \ + ret = func(*ap, *bp, &qsf); \ + return *(type##_t *)&ret; \ + } + +#define WRAP_COMMON_OPS(b) \ + WRAP1(qemu_f##b##_sqrt, float##b##_sqrt, float##b) \ + WRAP2(qemu_f##b##_add, float##b##_add, float##b) \ + WRAP2(qemu_f##b##_sub, float##b##_sub, float##b) \ + WRAP2(qemu_f##b##_mul, float##b##_mul, float##b) \ + WRAP2(qemu_f##b##_div, float##b##_div, float##b) + +WRAP_COMMON_OPS(16) +WRAP_COMMON_OPS(32) +WRAP_COMMON_OPS(64) +#undef WRAP_COMMON + +WRAP2(qemu_f32_rem, float32_rem, float32) +WRAP2(qemu_f64_rem, float64_rem, float64) +#undef WRAP2 +#undef WRAP1 + +#define WRAP1_80(name, func) \ + static void name(const extFloat80_t *ap, extFloat80_t *res) \ + { \ + floatx80 a; \ + floatx80 ret; \ + \ + a = soft_to_qemu80(*ap); \ + ret = func(a, &qsf); \ + *res = qemu_to_soft80(ret); \ + } + +WRAP1_80(qemu_extF80M_sqrt, floatx80_sqrt) +#undef WRAP1_80 + +#define WRAP1_128(name, func) \ + static void name(const float128_t *ap, float128_t *res) \ + { \ + float128 a; \ + float128 ret; \ + \ + a = soft_to_qemu128(*ap); \ + ret = func(a, &qsf); \ + *res = qemu_to_soft128(ret); \ + } + +WRAP1_128(qemu_f128M_sqrt, float128_sqrt) +#undef WRAP1_128 + +#define WRAP2_80(name, func) \ + static void name(const extFloat80_t *ap, const extFloat80_t *bp, \ + extFloat80_t *res) \ + { \ + floatx80 a; \ + floatx80 b; \ + floatx80 ret; \ + \ + a = soft_to_qemu80(*ap); \ + b = soft_to_qemu80(*bp); \ + ret = func(a, b, &qsf); \ + *res = qemu_to_soft80(ret); \ + } + +WRAP2_80(qemu_extF80M_add, floatx80_add) +WRAP2_80(qemu_extF80M_sub, floatx80_sub) +WRAP2_80(qemu_extF80M_mul, floatx80_mul) +WRAP2_80(qemu_extF80M_div, floatx80_div) +WRAP2_80(qemu_extF80M_rem, floatx80_rem) +#undef WRAP2_80 + +#define WRAP2_128(name, func) \ + static void name(const float128_t *ap, const float128_t *bp, \ + float128_t *res) \ + { \ + float128 a; \ + float128 b; \ + float128 ret; \ + \ + a = soft_to_qemu128(*ap); \ + b = soft_to_qemu128(*bp); \ + ret = func(a, b, &qsf); \ + *res = qemu_to_soft128(ret); \ + } + +WRAP2_128(qemu_f128M_add, float128_add) +WRAP2_128(qemu_f128M_sub, float128_sub) +WRAP2_128(qemu_f128M_mul, float128_mul) +WRAP2_128(qemu_f128M_div, float128_div) +WRAP2_128(qemu_f128M_rem, float128_rem) +#undef WRAP2_128 + +#define WRAP_MULADD(name, func, type) \ + static type##_t name(type##_t a, type##_t b, type##_t c) \ + { \ + type *ap = (type *)&a; \ + type *bp = (type *)&b; \ + type *cp = (type *)&c; \ + type ret; \ + \ + ret = func(*ap, *bp, *cp, 0, &qsf); \ + return *(type##_t *)&ret; \ + } + +WRAP_MULADD(qemu_f16_mulAdd, float16_muladd, float16) +WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32) +WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64) +#undef WRAP_MULADD + +#define WRAP_CMP16(name, func, retcond) \ + static bool name(float16_t a, float16_t b) \ + { \ + float16 *ap = (float16 *)&a; \ + float16 *bp = (float16 *)&b; \ + int ret; \ + \ + ret = func(*ap, *bp, &qsf); \ + return retcond; \ + } + +WRAP_CMP16(qemu_f16_eq_signaling, float16_compare, ret == 0) +WRAP_CMP16(qemu_f16_eq, float16_compare_quiet, ret == 0) +WRAP_CMP16(qemu_f16_le, float16_compare, ret <= 0) +WRAP_CMP16(qemu_f16_lt, float16_compare, ret < 0) +WRAP_CMP16(qemu_f16_le_quiet, float16_compare_quiet, ret <= 0) +WRAP_CMP16(qemu_f16_lt_quiet, float16_compare_quiet, ret < 0) +#undef WRAP_CMP16 + +#define WRAP_CMP(name, func, type) \ + static bool name(type##_t a, type##_t b) \ + { \ + type *ap = (type *)&a; \ + type *bp = (type *)&b; \ + \ + return !!func(*ap, *bp, &qsf); \ + } + +#define GEN_WRAP_CMP(b) \ + WRAP_CMP(qemu_f##b##_eq_signaling, float##b##_eq, float##b) \ + WRAP_CMP(qemu_f##b##_eq, float##b##_eq_quiet, float##b) \ + WRAP_CMP(qemu_f##b##_le, float##b##_le, float##b) \ + WRAP_CMP(qemu_f##b##_lt, float##b##_lt, float##b) \ + WRAP_CMP(qemu_f##b##_le_quiet, float##b##_le_quiet, float##b) \ + WRAP_CMP(qemu_f##b##_lt_quiet, float##b##_lt_quiet, float##b) + +GEN_WRAP_CMP(32) +GEN_WRAP_CMP(64) +#undef GEN_WRAP_CMP +#undef WRAP_CMP + +#define WRAP_CMP80(name, func) \ + static bool name(const extFloat80_t *ap, const extFloat80_t *bp) \ + { \ + floatx80 a; \ + floatx80 b; \ + \ + a = soft_to_qemu80(*ap); \ + b = soft_to_qemu80(*bp); \ + return !!func(a, b, &qsf); \ + } + +WRAP_CMP80(qemu_extF80M_eq_signaling, floatx80_eq) +WRAP_CMP80(qemu_extF80M_eq, floatx80_eq_quiet) +WRAP_CMP80(qemu_extF80M_le, floatx80_le) +WRAP_CMP80(qemu_extF80M_lt, floatx80_lt) +WRAP_CMP80(qemu_extF80M_le_quiet, floatx80_le_quiet) +WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_le_quiet) +#undef WRAP_CMP80 + +#define WRAP_CMP128(name, func) \ + static bool name(const float128_t *ap, const float128_t *bp) \ + { \ + float128 a; \ + float128 b; \ + \ + a = soft_to_qemu128(*ap); \ + b = soft_to_qemu128(*bp); \ + return !!func(a, b, &qsf); \ + } + +WRAP_CMP128(qemu_f128M_eq_signaling, float128_eq) +WRAP_CMP128(qemu_f128M_eq, float128_eq_quiet) +WRAP_CMP128(qemu_f128M_le, float128_le) +WRAP_CMP128(qemu_f128M_lt, float128_lt) +WRAP_CMP128(qemu_f128M_le_quiet, float128_le_quiet) +WRAP_CMP128(qemu_f128M_lt_quiet, float128_lt_quiet) +#undef WRAP_CMP128 diff --git a/tests/fp/wrap.inc.c b/tests/fp/wrap.inc.c deleted file mode 100644 index 0cbd20013e..0000000000 --- a/tests/fp/wrap.inc.c +++ /dev/null @@ -1,654 +0,0 @@ -/* - * In this file we wrap QEMU FP functions to look like softfloat/testfloat's, - * so that we can use the testfloat infrastructure as-is. - * - * This file must be included directly from fp-test.c. We could compile it - * separately, but it would be tedious to add declarations for all the wrappers. - */ - -static signed char sf_tininess_to_qemu(uint_fast8_t mode) -{ - switch (mode) { - case softfloat_tininess_beforeRounding: - return float_tininess_before_rounding; - case softfloat_tininess_afterRounding: - return float_tininess_after_rounding; - default: - g_assert_not_reached(); - } -} - -static signed char sf_rounding_to_qemu(uint_fast8_t mode) -{ - switch (mode) { - case softfloat_round_near_even: - return float_round_nearest_even; - case softfloat_round_minMag: - return float_round_to_zero; - case softfloat_round_min: - return float_round_down; - case softfloat_round_max: - return float_round_up; - case softfloat_round_near_maxMag: - return float_round_ties_away; - case softfloat_round_odd: - return float_round_to_odd; - default: - g_assert_not_reached(); - } -} - -static uint_fast8_t qemu_flags_to_sf(uint8_t qflags) -{ - uint_fast8_t ret = 0; - - if (qflags & float_flag_invalid) { - ret |= softfloat_flag_invalid; - } - if (qflags & float_flag_divbyzero) { - ret |= softfloat_flag_infinite; - } - if (qflags & float_flag_overflow) { - ret |= softfloat_flag_overflow; - } - if (qflags & float_flag_underflow) { - ret |= softfloat_flag_underflow; - } - if (qflags & float_flag_inexact) { - ret |= softfloat_flag_inexact; - } - return ret; -} - -/* - * floatx80 and float128 cannot be cast between qemu and softfloat, because - * in softfloat the order of the fields depends on the host's endianness. - */ -static extFloat80_t qemu_to_soft80(floatx80 a) -{ - extFloat80_t ret; - - ret.signif = a.low; - ret.signExp = a.high; - return ret; -} - -static floatx80 soft_to_qemu80(extFloat80_t a) -{ - floatx80 ret; - - ret.low = a.signif; - ret.high = a.signExp; - return ret; -} - -static float128_t qemu_to_soft128(float128 a) -{ - float128_t ret; - struct uint128 *to = (struct uint128 *)&ret; - - to->v0 = a.low; - to->v64 = a.high; - return ret; -} - -static float128 soft_to_qemu128(float128_t a) -{ - struct uint128 *from = (struct uint128 *)&a; - float128 ret; - - ret.low = from->v0; - ret.high = from->v64; - return ret; -} - -/* conversions */ -#define WRAP_SF_TO_SF_IEEE(name, func, a_type, b_type) \ - static b_type##_t name(a_type##_t a) \ - { \ - a_type *ap = (a_type *)&a; \ - b_type ret; \ - \ - ret = func(*ap, true, &qsf); \ - return *(b_type##_t *)&ret; \ - } - -WRAP_SF_TO_SF_IEEE(qemu_f16_to_f32, float16_to_float32, float16, float32) -WRAP_SF_TO_SF_IEEE(qemu_f16_to_f64, float16_to_float64, float16, float64) - -WRAP_SF_TO_SF_IEEE(qemu_f32_to_f16, float32_to_float16, float32, float16) -WRAP_SF_TO_SF_IEEE(qemu_f64_to_f16, float64_to_float16, float64, float16) -#undef WRAP_SF_TO_SF_IEEE - -#define WRAP_SF_TO_SF(name, func, a_type, b_type) \ - static b_type##_t name(a_type##_t a) \ - { \ - a_type *ap = (a_type *)&a; \ - b_type ret; \ - \ - ret = func(*ap, &qsf); \ - return *(b_type##_t *)&ret; \ - } - -WRAP_SF_TO_SF(qemu_f32_to_f64, float32_to_float64, float32, float64) -WRAP_SF_TO_SF(qemu_f64_to_f32, float64_to_float32, float64, float32) -#undef WRAP_SF_TO_SF - -#define WRAP_SF_TO_80(name, func, type) \ - static void name(type##_t a, extFloat80_t *res) \ - { \ - floatx80 ret; \ - type *ap = (type *)&a; \ - \ - ret = func(*ap, &qsf); \ - *res = qemu_to_soft80(ret); \ - } - -WRAP_SF_TO_80(qemu_f32_to_extF80M, float32_to_floatx80, float32) -WRAP_SF_TO_80(qemu_f64_to_extF80M, float64_to_floatx80, float64) -#undef WRAP_SF_TO_80 - -#define WRAP_SF_TO_128(name, func, type) \ - static void name(type##_t a, float128_t *res) \ - { \ - float128 ret; \ - type *ap = (type *)&a; \ - \ - ret = func(*ap, &qsf); \ - *res = qemu_to_soft128(ret); \ - } - -WRAP_SF_TO_128(qemu_f32_to_f128M, float32_to_float128, float32) -WRAP_SF_TO_128(qemu_f64_to_f128M, float64_to_float128, float64) -#undef WRAP_SF_TO_128 - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_SF_TO_INT(name, func, type, fast_type) \ - static fast_type name(type##_t a, uint_fast8_t round, bool exact) \ - { \ - type *ap = (type *)&a; \ - \ - qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ - return func(*ap, &qsf); \ - } - -WRAP_SF_TO_INT(qemu_f16_to_ui32, float16_to_uint32, float16, uint_fast32_t) -WRAP_SF_TO_INT(qemu_f16_to_ui64, float16_to_uint64, float16, uint_fast64_t) - -WRAP_SF_TO_INT(qemu_f32_to_ui32, float32_to_uint32, float32, uint_fast32_t) -WRAP_SF_TO_INT(qemu_f32_to_ui64, float32_to_uint64, float32, uint_fast64_t) - -WRAP_SF_TO_INT(qemu_f64_to_ui32, float64_to_uint32, float64, uint_fast32_t) -WRAP_SF_TO_INT(qemu_f64_to_ui64, float64_to_uint64, float64, uint_fast64_t) - -WRAP_SF_TO_INT(qemu_f16_to_i32, float16_to_int32, float16, int_fast32_t) -WRAP_SF_TO_INT(qemu_f16_to_i64, float16_to_int64, float16, int_fast64_t) - -WRAP_SF_TO_INT(qemu_f32_to_i32, float32_to_int32, float32, int_fast32_t) -WRAP_SF_TO_INT(qemu_f32_to_i64, float32_to_int64, float32, int_fast64_t) - -WRAP_SF_TO_INT(qemu_f64_to_i32, float64_to_int32, float64, int_fast32_t) -WRAP_SF_TO_INT(qemu_f64_to_i64, float64_to_int64, float64, int_fast64_t) -#undef WRAP_SF_TO_INT - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_SF_TO_INT_MINMAG(name, func, type, fast_type) \ - static fast_type name(type##_t a, bool exact) \ - { \ - type *ap = (type *)&a; \ - \ - return func(*ap, &qsf); \ - } - -WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui32_r_minMag, - float16_to_uint32_round_to_zero, float16, uint_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f16_to_ui64_r_minMag, - float16_to_uint64_round_to_zero, float16, uint_fast64_t) - -WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i32_r_minMag, - float16_to_int32_round_to_zero, float16, int_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f16_to_i64_r_minMag, - float16_to_int64_round_to_zero, float16, int_fast64_t) - -WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui32_r_minMag, - float32_to_uint32_round_to_zero, float32, uint_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f32_to_ui64_r_minMag, - float32_to_uint64_round_to_zero, float32, uint_fast64_t) - -WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i32_r_minMag, - float32_to_int32_round_to_zero, float32, int_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f32_to_i64_r_minMag, - float32_to_int64_round_to_zero, float32, int_fast64_t) - -WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui32_r_minMag, - float64_to_uint32_round_to_zero, float64, uint_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f64_to_ui64_r_minMag, - float64_to_uint64_round_to_zero, float64, uint_fast64_t) - -WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i32_r_minMag, - float64_to_int32_round_to_zero, float64, int_fast32_t) -WRAP_SF_TO_INT_MINMAG(qemu_f64_to_i64_r_minMag, - float64_to_int64_round_to_zero, float64, int_fast64_t) -#undef WRAP_SF_TO_INT_MINMAG - -#define WRAP_80_TO_SF(name, func, type) \ - static type##_t name(const extFloat80_t *ap) \ - { \ - floatx80 a; \ - type ret; \ - \ - a = soft_to_qemu80(*ap); \ - ret = func(a, &qsf); \ - return *(type##_t *)&ret; \ - } - -WRAP_80_TO_SF(qemu_extF80M_to_f32, floatx80_to_float32, float32) -WRAP_80_TO_SF(qemu_extF80M_to_f64, floatx80_to_float64, float64) -#undef WRAP_80_TO_SF - -#define WRAP_128_TO_SF(name, func, type) \ - static type##_t name(const float128_t *ap) \ - { \ - float128 a; \ - type ret; \ - \ - a = soft_to_qemu128(*ap); \ - ret = func(a, &qsf); \ - return *(type##_t *)&ret; \ - } - -WRAP_128_TO_SF(qemu_f128M_to_f32, float128_to_float32, float32) -WRAP_128_TO_SF(qemu_f128M_to_f64, float128_to_float64, float64) -#undef WRAP_128_TO_SF - -static void qemu_extF80M_to_f128M(const extFloat80_t *from, float128_t *to) -{ - floatx80 qfrom; - float128 qto; - - qfrom = soft_to_qemu80(*from); - qto = floatx80_to_float128(qfrom, &qsf); - *to = qemu_to_soft128(qto); -} - -static void qemu_f128M_to_extF80M(const float128_t *from, extFloat80_t *to) -{ - float128 qfrom; - floatx80 qto; - - qfrom = soft_to_qemu128(*from); - qto = float128_to_floatx80(qfrom, &qsf); - *to = qemu_to_soft80(qto); -} - -#define WRAP_INT_TO_SF(name, func, int_type, type) \ - static type##_t name(int_type a) \ - { \ - type ret; \ - \ - ret = func(a, &qsf); \ - return *(type##_t *)&ret; \ - } - -WRAP_INT_TO_SF(qemu_ui32_to_f16, uint32_to_float16, uint32_t, float16) -WRAP_INT_TO_SF(qemu_ui32_to_f32, uint32_to_float32, uint32_t, float32) -WRAP_INT_TO_SF(qemu_ui32_to_f64, uint32_to_float64, uint32_t, float64) - -WRAP_INT_TO_SF(qemu_ui64_to_f16, uint64_to_float16, uint64_t, float16) -WRAP_INT_TO_SF(qemu_ui64_to_f32, uint64_to_float32, uint64_t, float32) -WRAP_INT_TO_SF(qemu_ui64_to_f64, uint64_to_float64, uint64_t, float64) - -WRAP_INT_TO_SF(qemu_i32_to_f16, int32_to_float16, int32_t, float16) -WRAP_INT_TO_SF(qemu_i32_to_f32, int32_to_float32, int32_t, float32) -WRAP_INT_TO_SF(qemu_i32_to_f64, int32_to_float64, int32_t, float64) - -WRAP_INT_TO_SF(qemu_i64_to_f16, int64_to_float16, int64_t, float16) -WRAP_INT_TO_SF(qemu_i64_to_f32, int64_to_float32, int64_t, float32) -WRAP_INT_TO_SF(qemu_i64_to_f64, int64_to_float64, int64_t, float64) -#undef WRAP_INT_TO_SF - -#define WRAP_INT_TO_80(name, func, int_type) \ - static void name(int_type a, extFloat80_t *res) \ - { \ - floatx80 ret; \ - \ - ret = func(a, &qsf); \ - *res = qemu_to_soft80(ret); \ - } - -WRAP_INT_TO_80(qemu_i32_to_extF80M, int32_to_floatx80, int32_t) -WRAP_INT_TO_80(qemu_i64_to_extF80M, int64_to_floatx80, int64_t) -#undef WRAP_INT_TO_80 - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_80_TO_INT(name, func, fast_type) \ - static fast_type name(const extFloat80_t *ap, uint_fast8_t round, \ - bool exact) \ - { \ - floatx80 a; \ - \ - a = soft_to_qemu80(*ap); \ - qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ - return func(a, &qsf); \ - } - -WRAP_80_TO_INT(qemu_extF80M_to_i32, floatx80_to_int32, int_fast32_t) -WRAP_80_TO_INT(qemu_extF80M_to_i64, floatx80_to_int64, int_fast64_t) -#undef WRAP_80_TO_INT - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_80_TO_INT_MINMAG(name, func, fast_type) \ - static fast_type name(const extFloat80_t *ap, bool exact) \ - { \ - floatx80 a; \ - \ - a = soft_to_qemu80(*ap); \ - return func(a, &qsf); \ - } - -WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i32_r_minMag, - floatx80_to_int32_round_to_zero, int_fast32_t) -WRAP_80_TO_INT_MINMAG(qemu_extF80M_to_i64_r_minMag, - floatx80_to_int64_round_to_zero, int_fast64_t) -#undef WRAP_80_TO_INT_MINMAG - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_128_TO_INT(name, func, fast_type) \ - static fast_type name(const float128_t *ap, uint_fast8_t round, \ - bool exact) \ - { \ - float128 a; \ - \ - a = soft_to_qemu128(*ap); \ - qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ - return func(a, &qsf); \ - } - -WRAP_128_TO_INT(qemu_f128M_to_i32, float128_to_int32, int_fast32_t) -WRAP_128_TO_INT(qemu_f128M_to_i64, float128_to_int64, int_fast64_t) - -WRAP_128_TO_INT(qemu_f128M_to_ui32, float128_to_uint32, uint_fast32_t) -WRAP_128_TO_INT(qemu_f128M_to_ui64, float128_to_uint64, uint_fast64_t) -#undef WRAP_128_TO_INT - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_128_TO_INT_MINMAG(name, func, fast_type) \ - static fast_type name(const float128_t *ap, bool exact) \ - { \ - float128 a; \ - \ - a = soft_to_qemu128(*ap); \ - return func(a, &qsf); \ - } - -WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i32_r_minMag, - float128_to_int32_round_to_zero, int_fast32_t) -WRAP_128_TO_INT_MINMAG(qemu_f128M_to_i64_r_minMag, - float128_to_int64_round_to_zero, int_fast64_t) - -WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui32_r_minMag, - float128_to_uint32_round_to_zero, uint_fast32_t) -WRAP_128_TO_INT_MINMAG(qemu_f128M_to_ui64_r_minMag, - float128_to_uint64_round_to_zero, uint_fast64_t) -#undef WRAP_128_TO_INT_MINMAG - -#define WRAP_INT_TO_128(name, func, int_type) \ - static void name(int_type a, float128_t *res) \ - { \ - float128 ret; \ - \ - ret = func(a, &qsf); \ - *res = qemu_to_soft128(ret); \ - } - -WRAP_INT_TO_128(qemu_ui64_to_f128M, uint64_to_float128, uint64_t) - -WRAP_INT_TO_128(qemu_i32_to_f128M, int32_to_float128, int32_t) -WRAP_INT_TO_128(qemu_i64_to_f128M, int64_to_float128, int64_t) -#undef WRAP_INT_TO_128 - -/* Note: exact is ignored since qemu's softfloat assumes it is set */ -#define WRAP_ROUND_TO_INT(name, func, type) \ - static type##_t name(type##_t a, uint_fast8_t round, bool exact) \ - { \ - type *ap = (type *)&a; \ - type ret; \ - \ - qsf.float_rounding_mode = sf_rounding_to_qemu(round); \ - ret = func(*ap, &qsf); \ - return *(type##_t *)&ret; \ - } - -WRAP_ROUND_TO_INT(qemu_f16_roundToInt, float16_round_to_int, float16) -WRAP_ROUND_TO_INT(qemu_f32_roundToInt, float32_round_to_int, float32) -WRAP_ROUND_TO_INT(qemu_f64_roundToInt, float64_round_to_int, float64) -#undef WRAP_ROUND_TO_INT - -static void qemu_extF80M_roundToInt(const extFloat80_t *ap, uint_fast8_t round, - bool exact, extFloat80_t *res) -{ - floatx80 a; - floatx80 ret; - - a = soft_to_qemu80(*ap); - qsf.float_rounding_mode = sf_rounding_to_qemu(round); - ret = floatx80_round_to_int(a, &qsf); - *res = qemu_to_soft80(ret); -} - -static void qemu_f128M_roundToInt(const float128_t *ap, uint_fast8_t round, - bool exact, float128_t *res) -{ - float128 a; - float128 ret; - - a = soft_to_qemu128(*ap); - qsf.float_rounding_mode = sf_rounding_to_qemu(round); - ret = float128_round_to_int(a, &qsf); - *res = qemu_to_soft128(ret); -} - -/* operations */ -#define WRAP1(name, func, type) \ - static type##_t name(type##_t a) \ - { \ - type *ap = (type *)&a; \ - type ret; \ - \ - ret = func(*ap, &qsf); \ - return *(type##_t *)&ret; \ - } - -#define WRAP2(name, func, type) \ - static type##_t name(type##_t a, type##_t b) \ - { \ - type *ap = (type *)&a; \ - type *bp = (type *)&b; \ - type ret; \ - \ - ret = func(*ap, *bp, &qsf); \ - return *(type##_t *)&ret; \ - } - -#define WRAP_COMMON_OPS(b) \ - WRAP1(qemu_f##b##_sqrt, float##b##_sqrt, float##b) \ - WRAP2(qemu_f##b##_add, float##b##_add, float##b) \ - WRAP2(qemu_f##b##_sub, float##b##_sub, float##b) \ - WRAP2(qemu_f##b##_mul, float##b##_mul, float##b) \ - WRAP2(qemu_f##b##_div, float##b##_div, float##b) - -WRAP_COMMON_OPS(16) -WRAP_COMMON_OPS(32) -WRAP_COMMON_OPS(64) -#undef WRAP_COMMON - -WRAP2(qemu_f32_rem, float32_rem, float32) -WRAP2(qemu_f64_rem, float64_rem, float64) -#undef WRAP2 -#undef WRAP1 - -#define WRAP1_80(name, func) \ - static void name(const extFloat80_t *ap, extFloat80_t *res) \ - { \ - floatx80 a; \ - floatx80 ret; \ - \ - a = soft_to_qemu80(*ap); \ - ret = func(a, &qsf); \ - *res = qemu_to_soft80(ret); \ - } - -WRAP1_80(qemu_extF80M_sqrt, floatx80_sqrt) -#undef WRAP1_80 - -#define WRAP1_128(name, func) \ - static void name(const float128_t *ap, float128_t *res) \ - { \ - float128 a; \ - float128 ret; \ - \ - a = soft_to_qemu128(*ap); \ - ret = func(a, &qsf); \ - *res = qemu_to_soft128(ret); \ - } - -WRAP1_128(qemu_f128M_sqrt, float128_sqrt) -#undef WRAP1_128 - -#define WRAP2_80(name, func) \ - static void name(const extFloat80_t *ap, const extFloat80_t *bp, \ - extFloat80_t *res) \ - { \ - floatx80 a; \ - floatx80 b; \ - floatx80 ret; \ - \ - a = soft_to_qemu80(*ap); \ - b = soft_to_qemu80(*bp); \ - ret = func(a, b, &qsf); \ - *res = qemu_to_soft80(ret); \ - } - -WRAP2_80(qemu_extF80M_add, floatx80_add) -WRAP2_80(qemu_extF80M_sub, floatx80_sub) -WRAP2_80(qemu_extF80M_mul, floatx80_mul) -WRAP2_80(qemu_extF80M_div, floatx80_div) -WRAP2_80(qemu_extF80M_rem, floatx80_rem) -#undef WRAP2_80 - -#define WRAP2_128(name, func) \ - static void name(const float128_t *ap, const float128_t *bp, \ - float128_t *res) \ - { \ - float128 a; \ - float128 b; \ - float128 ret; \ - \ - a = soft_to_qemu128(*ap); \ - b = soft_to_qemu128(*bp); \ - ret = func(a, b, &qsf); \ - *res = qemu_to_soft128(ret); \ - } - -WRAP2_128(qemu_f128M_add, float128_add) -WRAP2_128(qemu_f128M_sub, float128_sub) -WRAP2_128(qemu_f128M_mul, float128_mul) -WRAP2_128(qemu_f128M_div, float128_div) -WRAP2_128(qemu_f128M_rem, float128_rem) -#undef WRAP2_128 - -#define WRAP_MULADD(name, func, type) \ - static type##_t name(type##_t a, type##_t b, type##_t c) \ - { \ - type *ap = (type *)&a; \ - type *bp = (type *)&b; \ - type *cp = (type *)&c; \ - type ret; \ - \ - ret = func(*ap, *bp, *cp, 0, &qsf); \ - return *(type##_t *)&ret; \ - } - -WRAP_MULADD(qemu_f16_mulAdd, float16_muladd, float16) -WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32) -WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64) -#undef WRAP_MULADD - -#define WRAP_CMP16(name, func, retcond) \ - static bool name(float16_t a, float16_t b) \ - { \ - float16 *ap = (float16 *)&a; \ - float16 *bp = (float16 *)&b; \ - int ret; \ - \ - ret = func(*ap, *bp, &qsf); \ - return retcond; \ - } - -WRAP_CMP16(qemu_f16_eq_signaling, float16_compare, ret == 0) -WRAP_CMP16(qemu_f16_eq, float16_compare_quiet, ret == 0) -WRAP_CMP16(qemu_f16_le, float16_compare, ret <= 0) -WRAP_CMP16(qemu_f16_lt, float16_compare, ret < 0) -WRAP_CMP16(qemu_f16_le_quiet, float16_compare_quiet, ret <= 0) -WRAP_CMP16(qemu_f16_lt_quiet, float16_compare_quiet, ret < 0) -#undef WRAP_CMP16 - -#define WRAP_CMP(name, func, type) \ - static bool name(type##_t a, type##_t b) \ - { \ - type *ap = (type *)&a; \ - type *bp = (type *)&b; \ - \ - return !!func(*ap, *bp, &qsf); \ - } - -#define GEN_WRAP_CMP(b) \ - WRAP_CMP(qemu_f##b##_eq_signaling, float##b##_eq, float##b) \ - WRAP_CMP(qemu_f##b##_eq, float##b##_eq_quiet, float##b) \ - WRAP_CMP(qemu_f##b##_le, float##b##_le, float##b) \ - WRAP_CMP(qemu_f##b##_lt, float##b##_lt, float##b) \ - WRAP_CMP(qemu_f##b##_le_quiet, float##b##_le_quiet, float##b) \ - WRAP_CMP(qemu_f##b##_lt_quiet, float##b##_lt_quiet, float##b) - -GEN_WRAP_CMP(32) -GEN_WRAP_CMP(64) -#undef GEN_WRAP_CMP -#undef WRAP_CMP - -#define WRAP_CMP80(name, func) \ - static bool name(const extFloat80_t *ap, const extFloat80_t *bp) \ - { \ - floatx80 a; \ - floatx80 b; \ - \ - a = soft_to_qemu80(*ap); \ - b = soft_to_qemu80(*bp); \ - return !!func(a, b, &qsf); \ - } - -WRAP_CMP80(qemu_extF80M_eq_signaling, floatx80_eq) -WRAP_CMP80(qemu_extF80M_eq, floatx80_eq_quiet) -WRAP_CMP80(qemu_extF80M_le, floatx80_le) -WRAP_CMP80(qemu_extF80M_lt, floatx80_lt) -WRAP_CMP80(qemu_extF80M_le_quiet, floatx80_le_quiet) -WRAP_CMP80(qemu_extF80M_lt_quiet, floatx80_le_quiet) -#undef WRAP_CMP80 - -#define WRAP_CMP128(name, func) \ - static bool name(const float128_t *ap, const float128_t *bp) \ - { \ - float128 a; \ - float128 b; \ - \ - a = soft_to_qemu128(*ap); \ - b = soft_to_qemu128(*bp); \ - return !!func(a, b, &qsf); \ - } - -WRAP_CMP128(qemu_f128M_eq_signaling, float128_eq) -WRAP_CMP128(qemu_f128M_eq, float128_eq_quiet) -WRAP_CMP128(qemu_f128M_le, float128_le) -WRAP_CMP128(qemu_f128M_lt, float128_lt) -WRAP_CMP128(qemu_f128M_le_quiet, float128_le_quiet) -WRAP_CMP128(qemu_f128M_lt_quiet, float128_lt_quiet) -#undef WRAP_CMP128 diff --git a/ui/input-keymap.c b/ui/input-keymap.c index c4301851bd..1b756a6970 100644 --- a/ui/input-keymap.c +++ b/ui/input-keymap.c @@ -4,23 +4,23 @@ #include "standard-headers/linux/input.h" -#include "ui/input-keymap-atset1-to-qcode.c" -#include "ui/input-keymap-linux-to-qcode.c" -#include "ui/input-keymap-qcode-to-atset1.c" -#include "ui/input-keymap-qcode-to-atset2.c" -#include "ui/input-keymap-qcode-to-atset3.c" -#include "ui/input-keymap-qcode-to-linux.c" -#include "ui/input-keymap-qcode-to-qnum.c" -#include "ui/input-keymap-qcode-to-sun.c" -#include "ui/input-keymap-qnum-to-qcode.c" -#include "ui/input-keymap-usb-to-qcode.c" -#include "ui/input-keymap-win32-to-qcode.c" -#include "ui/input-keymap-x11-to-qcode.c" -#include "ui/input-keymap-xorgevdev-to-qcode.c" -#include "ui/input-keymap-xorgkbd-to-qcode.c" -#include "ui/input-keymap-xorgxquartz-to-qcode.c" -#include "ui/input-keymap-xorgxwin-to-qcode.c" -#include "ui/input-keymap-osx-to-qcode.c" +#include "ui/input-keymap-atset1-to-qcode.c.inc" +#include "ui/input-keymap-linux-to-qcode.c.inc" +#include "ui/input-keymap-qcode-to-atset1.c.inc" +#include "ui/input-keymap-qcode-to-atset2.c.inc" +#include "ui/input-keymap-qcode-to-atset3.c.inc" +#include "ui/input-keymap-qcode-to-linux.c.inc" +#include "ui/input-keymap-qcode-to-qnum.c.inc" +#include "ui/input-keymap-qcode-to-sun.c.inc" +#include "ui/input-keymap-qnum-to-qcode.c.inc" +#include "ui/input-keymap-usb-to-qcode.c.inc" +#include "ui/input-keymap-win32-to-qcode.c.inc" +#include "ui/input-keymap-x11-to-qcode.c.inc" +#include "ui/input-keymap-xorgevdev-to-qcode.c.inc" +#include "ui/input-keymap-xorgkbd-to-qcode.c.inc" +#include "ui/input-keymap-xorgxquartz-to-qcode.c.inc" +#include "ui/input-keymap-xorgxwin-to-qcode.c.inc" +#include "ui/input-keymap-osx-to-qcode.c.inc" int qemu_input_linux_to_qcode(unsigned int lnx) { diff --git a/ui/vnc-enc-zrle.c b/ui/vnc-enc-zrle.c index b4f71e32cf..bd33b89063 100644 --- a/ui/vnc-enc-zrle.c +++ b/ui/vnc-enc-zrle.c @@ -199,56 +199,56 @@ static void zrle_write_u8(VncState *vs, uint8_t value) #define ZRLE_BPP 8 #define ZYWRLE_ENDIAN ENDIAN_NO -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZRLE_BPP #define ZRLE_BPP 15 #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_LITTLE -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_BIG -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZRLE_BPP #define ZRLE_BPP 16 #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_LITTLE -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_BIG -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZRLE_BPP #define ZRLE_BPP 32 #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_LITTLE -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_BIG -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #define ZRLE_COMPACT_PIXEL 24a #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_LITTLE -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_BIG -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZRLE_COMPACT_PIXEL #define ZRLE_COMPACT_PIXEL 24b #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_LITTLE -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZYWRLE_ENDIAN #define ZYWRLE_ENDIAN ENDIAN_BIG -#include "vnc-enc-zrle.inc.c" +#include "vnc-enc-zrle.c.inc" #undef ZRLE_COMPACT_PIXEL #undef ZRLE_BPP diff --git a/ui/vnc-enc-zrle.c.inc b/ui/vnc-enc-zrle.c.inc new file mode 100644 index 0000000000..c107d8affc --- /dev/null +++ b/ui/vnc-enc-zrle.c.inc @@ -0,0 +1,263 @@ +/* + * QEMU VNC display driver: Zlib Run-length Encoding (ZRLE) + * + * From libvncserver/libvncserver/zrleencodetemplate.c + * Copyright (C) 2002 RealVNC Ltd. All Rights Reserved. + * Copyright (C) 2003 Sun Microsystems, Inc. + * + * Copyright (C) 2010 Corentin Chary + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +/* + * Before including this file, you must define a number of CPP macros. + * + * ZRLE_BPP should be 8, 16 or 32 depending on the bits per pixel. + * + * Note that the buf argument to ZRLE_ENCODE needs to be at least one pixel + * bigger than the largest tile of pixel data, since the ZRLE encoding + * algorithm writes to the position one past the end of the pixel data. + */ + + +#include "qemu/osdep.h" + +#undef ZRLE_ENDIAN_SUFFIX + +#if ZYWRLE_ENDIAN == ENDIAN_LITTLE +#define ZRLE_ENDIAN_SUFFIX le +#elif ZYWRLE_ENDIAN == ENDIAN_BIG +#define ZRLE_ENDIAN_SUFFIX be +#else +#define ZRLE_ENDIAN_SUFFIX ne +#endif + +#ifndef ZRLE_CONCAT +#define ZRLE_CONCAT_I(a, b) a##b +#define ZRLE_CONCAT2(a, b) ZRLE_CONCAT_I(a, b) +#define ZRLE_CONCAT3(a, b, c) ZRLE_CONCAT2(a, ZRLE_CONCAT2(b, c)) +#endif + +#ifdef ZRLE_COMPACT_PIXEL +#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_COMPACT_PIXEL,ZRLE_ENDIAN_SUFFIX) +#define ZRLE_WRITE_SUFFIX ZRLE_COMPACT_PIXEL +#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t) +#define ZRLE_BPP_OUT 24 +#elif ZRLE_BPP == 15 +#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX) +#define ZRLE_WRITE_SUFFIX 16 +#define ZRLE_PIXEL uint16_t +#define ZRLE_BPP_OUT 16 +#else +#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX) +#define ZRLE_WRITE_SUFFIX ZRLE_BPP +#define ZRLE_BPP_OUT ZRLE_BPP +#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t) +#endif + +#define ZRLE_WRITE_PIXEL ZRLE_CONCAT2(zrle_write_u, ZRLE_WRITE_SUFFIX) +#define ZRLE_ENCODE ZRLE_CONCAT2(zrle_encode_, ZRLE_ENCODE_SUFFIX) +#define ZRLE_ENCODE_TILE ZRLE_CONCAT2(zrle_encode_tile, ZRLE_ENCODE_SUFFIX) +#define ZRLE_WRITE_PALETTE ZRLE_CONCAT2(zrle_write_palette,ZRLE_ENCODE_SUFFIX) + +static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h, + int zywrle_level); + +#if ZRLE_BPP != 8 +#include "vnc-enc-zywrle-template.c" +#endif + + +static void ZRLE_ENCODE(VncState *vs, int x, int y, int w, int h, + int zywrle_level) +{ + int ty; + + for (ty = y; ty < y + h; ty += VNC_ZRLE_TILE_HEIGHT) { + + int tx, th; + + th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty); + + for (tx = x; tx < x + w; tx += VNC_ZRLE_TILE_WIDTH) { + int tw; + ZRLE_PIXEL *buf; + + tw = MIN(VNC_ZRLE_TILE_WIDTH, x + w - tx); + + buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP); + ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level); + } + } +} + +static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h, + int zywrle_level) +{ + VncPalette *palette = &vs->zrle->palette; + + int runs = 0; + int single_pixels = 0; + + bool use_rle; + bool use_palette; + + int i; + + ZRLE_PIXEL *ptr = data; + ZRLE_PIXEL *end = ptr + h * w; + *end = ~*(end-1); /* one past the end is different so the while loop ends */ + + /* Real limit is 127 but we wan't a way to know if there is more than 127 */ + palette_init(palette, 256, ZRLE_BPP); + + while (ptr < end) { + ZRLE_PIXEL pix = *ptr; + if (*++ptr != pix) { /* FIXME */ + single_pixels++; + } else { + while (*++ptr == pix) ; + runs++; + } + palette_put(palette, pix); + } + + /* Solid tile is a special case */ + + if (palette_size(palette) == 1) { + bool found; + + vnc_write_u8(vs, 1); + ZRLE_WRITE_PIXEL(vs, palette_color(palette, 0, &found)); + return; + } + + zrle_choose_palette_rle(vs, w, h, palette, ZRLE_BPP_OUT, + runs, single_pixels, zywrle_level, + &use_rle, &use_palette); + + if (!use_palette) { + vnc_write_u8(vs, (use_rle ? 128 : 0)); + } else { + uint32_t colors[VNC_PALETTE_MAX_SIZE]; + size_t size = palette_size(palette); + + vnc_write_u8(vs, (use_rle ? 128 : 0) | size); + palette_fill(palette, colors); + + for (i = 0; i < size; i++) { + ZRLE_WRITE_PIXEL(vs, colors[i]); + } + } + + if (use_rle) { + ZRLE_PIXEL *ptr = data; + ZRLE_PIXEL *end = ptr + w * h; + ZRLE_PIXEL *run_start; + ZRLE_PIXEL pix; + + while (ptr < end) { + int len; + int index = 0; + + run_start = ptr; + pix = *ptr++; + + while (*ptr == pix && ptr < end) { + ptr++; + } + + len = ptr - run_start; + + if (use_palette) + index = palette_idx(palette, pix); + + if (len <= 2 && use_palette) { + if (len == 2) { + vnc_write_u8(vs, index); + } + vnc_write_u8(vs, index); + continue; + } + if (use_palette) { + vnc_write_u8(vs, index | 128); + } else { + ZRLE_WRITE_PIXEL(vs, pix); + } + + len -= 1; + + while (len >= 255) { + vnc_write_u8(vs, 255); + len -= 255; + } + + vnc_write_u8(vs, len); + } + } else if (use_palette) { /* no RLE */ + int bppp; + ZRLE_PIXEL *ptr = data; + + /* packed pixels */ + + assert (palette_size(palette) < 17); + + bppp = bits_per_packed_pixel[palette_size(palette)-1]; + + for (i = 0; i < h; i++) { + uint8_t nbits = 0; + uint8_t byte = 0; + + ZRLE_PIXEL *eol = ptr + w; + + while (ptr < eol) { + ZRLE_PIXEL pix = *ptr++; + uint8_t index = palette_idx(palette, pix); + + byte = (byte << bppp) | index; + nbits += bppp; + if (nbits >= 8) { + vnc_write_u8(vs, byte); + nbits = 0; + } + } + if (nbits > 0) { + byte <<= 8 - nbits; + vnc_write_u8(vs, byte); + } + } + } else { + + /* raw */ + +#if ZRLE_BPP != 8 + if (zywrle_level > 0 && !(zywrle_level & 0x80)) { + ZYWRLE_ANALYZE(data, data, w, h, w, zywrle_level, vs->zywrle.buf); + ZRLE_ENCODE_TILE(vs, data, w, h, zywrle_level | 0x80); + } + else +#endif + { +#ifdef ZRLE_COMPACT_PIXEL + ZRLE_PIXEL *ptr; + + for (ptr = data; ptr < data + w * h; ptr++) { + ZRLE_WRITE_PIXEL(vs, *ptr); + } +#else + vnc_write(vs, data, w * h * (ZRLE_BPP / 8)); +#endif + } + } +} + +#undef ZRLE_PIXEL +#undef ZRLE_WRITE_PIXEL +#undef ZRLE_ENCODE +#undef ZRLE_ENCODE_TILE +#undef ZYWRLE_ENCODE_TILE +#undef ZRLE_BPP_OUT +#undef ZRLE_WRITE_SUFFIX +#undef ZRLE_ENCODE_SUFFIX diff --git a/ui/vnc-enc-zrle.inc.c b/ui/vnc-enc-zrle.inc.c deleted file mode 100644 index c107d8affc..0000000000 --- a/ui/vnc-enc-zrle.inc.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * QEMU VNC display driver: Zlib Run-length Encoding (ZRLE) - * - * From libvncserver/libvncserver/zrleencodetemplate.c - * Copyright (C) 2002 RealVNC Ltd. All Rights Reserved. - * Copyright (C) 2003 Sun Microsystems, Inc. - * - * Copyright (C) 2010 Corentin Chary - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -/* - * Before including this file, you must define a number of CPP macros. - * - * ZRLE_BPP should be 8, 16 or 32 depending on the bits per pixel. - * - * Note that the buf argument to ZRLE_ENCODE needs to be at least one pixel - * bigger than the largest tile of pixel data, since the ZRLE encoding - * algorithm writes to the position one past the end of the pixel data. - */ - - -#include "qemu/osdep.h" - -#undef ZRLE_ENDIAN_SUFFIX - -#if ZYWRLE_ENDIAN == ENDIAN_LITTLE -#define ZRLE_ENDIAN_SUFFIX le -#elif ZYWRLE_ENDIAN == ENDIAN_BIG -#define ZRLE_ENDIAN_SUFFIX be -#else -#define ZRLE_ENDIAN_SUFFIX ne -#endif - -#ifndef ZRLE_CONCAT -#define ZRLE_CONCAT_I(a, b) a##b -#define ZRLE_CONCAT2(a, b) ZRLE_CONCAT_I(a, b) -#define ZRLE_CONCAT3(a, b, c) ZRLE_CONCAT2(a, ZRLE_CONCAT2(b, c)) -#endif - -#ifdef ZRLE_COMPACT_PIXEL -#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_COMPACT_PIXEL,ZRLE_ENDIAN_SUFFIX) -#define ZRLE_WRITE_SUFFIX ZRLE_COMPACT_PIXEL -#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t) -#define ZRLE_BPP_OUT 24 -#elif ZRLE_BPP == 15 -#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX) -#define ZRLE_WRITE_SUFFIX 16 -#define ZRLE_PIXEL uint16_t -#define ZRLE_BPP_OUT 16 -#else -#define ZRLE_ENCODE_SUFFIX ZRLE_CONCAT2(ZRLE_BPP,ZRLE_ENDIAN_SUFFIX) -#define ZRLE_WRITE_SUFFIX ZRLE_BPP -#define ZRLE_BPP_OUT ZRLE_BPP -#define ZRLE_PIXEL ZRLE_CONCAT3(uint,ZRLE_BPP,_t) -#endif - -#define ZRLE_WRITE_PIXEL ZRLE_CONCAT2(zrle_write_u, ZRLE_WRITE_SUFFIX) -#define ZRLE_ENCODE ZRLE_CONCAT2(zrle_encode_, ZRLE_ENCODE_SUFFIX) -#define ZRLE_ENCODE_TILE ZRLE_CONCAT2(zrle_encode_tile, ZRLE_ENCODE_SUFFIX) -#define ZRLE_WRITE_PALETTE ZRLE_CONCAT2(zrle_write_palette,ZRLE_ENCODE_SUFFIX) - -static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h, - int zywrle_level); - -#if ZRLE_BPP != 8 -#include "vnc-enc-zywrle-template.c" -#endif - - -static void ZRLE_ENCODE(VncState *vs, int x, int y, int w, int h, - int zywrle_level) -{ - int ty; - - for (ty = y; ty < y + h; ty += VNC_ZRLE_TILE_HEIGHT) { - - int tx, th; - - th = MIN(VNC_ZRLE_TILE_HEIGHT, y + h - ty); - - for (tx = x; tx < x + w; tx += VNC_ZRLE_TILE_WIDTH) { - int tw; - ZRLE_PIXEL *buf; - - tw = MIN(VNC_ZRLE_TILE_WIDTH, x + w - tx); - - buf = zrle_convert_fb(vs, tx, ty, tw, th, ZRLE_BPP); - ZRLE_ENCODE_TILE(vs, buf, tw, th, zywrle_level); - } - } -} - -static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h, - int zywrle_level) -{ - VncPalette *palette = &vs->zrle->palette; - - int runs = 0; - int single_pixels = 0; - - bool use_rle; - bool use_palette; - - int i; - - ZRLE_PIXEL *ptr = data; - ZRLE_PIXEL *end = ptr + h * w; - *end = ~*(end-1); /* one past the end is different so the while loop ends */ - - /* Real limit is 127 but we wan't a way to know if there is more than 127 */ - palette_init(palette, 256, ZRLE_BPP); - - while (ptr < end) { - ZRLE_PIXEL pix = *ptr; - if (*++ptr != pix) { /* FIXME */ - single_pixels++; - } else { - while (*++ptr == pix) ; - runs++; - } - palette_put(palette, pix); - } - - /* Solid tile is a special case */ - - if (palette_size(palette) == 1) { - bool found; - - vnc_write_u8(vs, 1); - ZRLE_WRITE_PIXEL(vs, palette_color(palette, 0, &found)); - return; - } - - zrle_choose_palette_rle(vs, w, h, palette, ZRLE_BPP_OUT, - runs, single_pixels, zywrle_level, - &use_rle, &use_palette); - - if (!use_palette) { - vnc_write_u8(vs, (use_rle ? 128 : 0)); - } else { - uint32_t colors[VNC_PALETTE_MAX_SIZE]; - size_t size = palette_size(palette); - - vnc_write_u8(vs, (use_rle ? 128 : 0) | size); - palette_fill(palette, colors); - - for (i = 0; i < size; i++) { - ZRLE_WRITE_PIXEL(vs, colors[i]); - } - } - - if (use_rle) { - ZRLE_PIXEL *ptr = data; - ZRLE_PIXEL *end = ptr + w * h; - ZRLE_PIXEL *run_start; - ZRLE_PIXEL pix; - - while (ptr < end) { - int len; - int index = 0; - - run_start = ptr; - pix = *ptr++; - - while (*ptr == pix && ptr < end) { - ptr++; - } - - len = ptr - run_start; - - if (use_palette) - index = palette_idx(palette, pix); - - if (len <= 2 && use_palette) { - if (len == 2) { - vnc_write_u8(vs, index); - } - vnc_write_u8(vs, index); - continue; - } - if (use_palette) { - vnc_write_u8(vs, index | 128); - } else { - ZRLE_WRITE_PIXEL(vs, pix); - } - - len -= 1; - - while (len >= 255) { - vnc_write_u8(vs, 255); - len -= 255; - } - - vnc_write_u8(vs, len); - } - } else if (use_palette) { /* no RLE */ - int bppp; - ZRLE_PIXEL *ptr = data; - - /* packed pixels */ - - assert (palette_size(palette) < 17); - - bppp = bits_per_packed_pixel[palette_size(palette)-1]; - - for (i = 0; i < h; i++) { - uint8_t nbits = 0; - uint8_t byte = 0; - - ZRLE_PIXEL *eol = ptr + w; - - while (ptr < eol) { - ZRLE_PIXEL pix = *ptr++; - uint8_t index = palette_idx(palette, pix); - - byte = (byte << bppp) | index; - nbits += bppp; - if (nbits >= 8) { - vnc_write_u8(vs, byte); - nbits = 0; - } - } - if (nbits > 0) { - byte <<= 8 - nbits; - vnc_write_u8(vs, byte); - } - } - } else { - - /* raw */ - -#if ZRLE_BPP != 8 - if (zywrle_level > 0 && !(zywrle_level & 0x80)) { - ZYWRLE_ANALYZE(data, data, w, h, w, zywrle_level, vs->zywrle.buf); - ZRLE_ENCODE_TILE(vs, data, w, h, zywrle_level | 0x80); - } - else -#endif - { -#ifdef ZRLE_COMPACT_PIXEL - ZRLE_PIXEL *ptr; - - for (ptr = data; ptr < data + w * h; ptr++) { - ZRLE_WRITE_PIXEL(vs, *ptr); - } -#else - vnc_write(vs, data, w * h * (ZRLE_BPP / 8)); -#endif - } - } -} - -#undef ZRLE_PIXEL -#undef ZRLE_WRITE_PIXEL -#undef ZRLE_ENCODE -#undef ZRLE_ENCODE_TILE -#undef ZYWRLE_ENCODE_TILE -#undef ZRLE_BPP_OUT -#undef ZRLE_WRITE_SUFFIX -#undef ZRLE_ENCODE_SUFFIX -- cgit v1.2.3-55-g7522 From 0979ed017f093ead3c011513a3a79517ed75bd00 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Feb 2020 12:41:01 +0100 Subject: meson: rename .inc.h files to .h.inc Make it consistent with '.c.inc' and '.rst.inc'. Signed-off-by: Paolo Bonzini --- include/exec/cpu-all.h | 10 +- include/exec/memory.h | 12 +- include/exec/memory_ldst.h.inc | 71 +++++++ include/exec/memory_ldst.inc.h | 71 ------- include/exec/memory_ldst_cached.h.inc | 108 ++++++++++ include/exec/memory_ldst_cached.inc.h | 108 ---------- include/exec/memory_ldst_phys.h.inc | 147 ++++++++++++++ include/exec/memory_ldst_phys.inc.h | 147 -------------- target/s390x/cpu_features.c | 2 +- target/s390x/cpu_features_def.h | 2 +- target/s390x/cpu_features_def.h.inc | 371 ++++++++++++++++++++++++++++++++++ target/s390x/cpu_features_def.inc.h | 371 ---------------------------------- 12 files changed, 710 insertions(+), 710 deletions(-) create mode 100644 include/exec/memory_ldst.h.inc delete mode 100644 include/exec/memory_ldst.inc.h create mode 100644 include/exec/memory_ldst_cached.h.inc delete mode 100644 include/exec/memory_ldst_cached.inc.h create mode 100644 include/exec/memory_ldst_phys.h.inc delete mode 100644 include/exec/memory_ldst_phys.inc.h create mode 100644 target/s390x/cpu_features_def.h.inc delete mode 100644 target/s390x/cpu_features_def.inc.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index fc403d456b..f6439c4705 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -189,13 +189,13 @@ extern unsigned long reserved_va; #define ARG1 as #define ARG1_DECL AddressSpace *as #define TARGET_ENDIANNESS -#include "exec/memory_ldst.inc.h" +#include "exec/memory_ldst.h.inc" #define SUFFIX _cached_slow #define ARG1 cache #define ARG1_DECL MemoryRegionCache *cache #define TARGET_ENDIANNESS -#include "exec/memory_ldst.inc.h" +#include "exec/memory_ldst.h.inc" static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) { @@ -207,17 +207,17 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val #define ARG1 as #define ARG1_DECL AddressSpace *as #define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.inc.h" +#include "exec/memory_ldst_phys.h.inc" /* Inline fast path for direct RAM access. */ #define ENDIANNESS -#include "exec/memory_ldst_cached.inc.h" +#include "exec/memory_ldst_cached.h.inc" #define SUFFIX _cached #define ARG1 cache #define ARG1_DECL MemoryRegionCache *cache #define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.inc.h" +#include "exec/memory_ldst_phys.h.inc" #endif /* page related stuff */ diff --git a/include/exec/memory.h b/include/exec/memory.h index 307e527835..0cfe987ab4 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2133,12 +2133,12 @@ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, #define SUFFIX #define ARG1 as #define ARG1_DECL AddressSpace *as -#include "exec/memory_ldst.inc.h" +#include "exec/memory_ldst.h.inc" #define SUFFIX #define ARG1 as #define ARG1_DECL AddressSpace *as -#include "exec/memory_ldst_phys.inc.h" +#include "exec/memory_ldst_phys.h.inc" struct MemoryRegionCache { void *ptr; @@ -2179,7 +2179,7 @@ struct MemoryRegionCache { #define SUFFIX _cached_slow #define ARG1 cache #define ARG1_DECL MemoryRegionCache *cache -#include "exec/memory_ldst.inc.h" +#include "exec/memory_ldst.h.inc" /* Inline fast path for direct RAM access. */ static inline uint8_t address_space_ldub_cached(MemoryRegionCache *cache, @@ -2205,15 +2205,15 @@ static inline void address_space_stb_cached(MemoryRegionCache *cache, } #define ENDIANNESS _le -#include "exec/memory_ldst_cached.inc.h" +#include "exec/memory_ldst_cached.h.inc" #define ENDIANNESS _be -#include "exec/memory_ldst_cached.inc.h" +#include "exec/memory_ldst_cached.h.inc" #define SUFFIX _cached #define ARG1 cache #define ARG1_DECL MemoryRegionCache *cache -#include "exec/memory_ldst_phys.inc.h" +#include "exec/memory_ldst_phys.h.inc" /* address_space_cache_init: prepare for repeated access to a physical * memory region diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc new file mode 100644 index 0000000000..272c20f02e --- /dev/null +++ b/include/exec/memory_ldst.h.inc @@ -0,0 +1,71 @@ +/* + * Physical memory access templates + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2015 Linaro, Inc. + * Copyright (c) 2016 Red Hat, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifdef TARGET_ENDIANNESS +extern uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stw, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stl, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stq, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); +#else +extern uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stb, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); +extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); +#endif + +#undef ARG1_DECL +#undef ARG1 +#undef SUFFIX +#undef TARGET_ENDIANNESS diff --git a/include/exec/memory_ldst.inc.h b/include/exec/memory_ldst.inc.h deleted file mode 100644 index 272c20f02e..0000000000 --- a/include/exec/memory_ldst.inc.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Physical memory access templates - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2015 Linaro, Inc. - * Copyright (c) 2016 Red Hat, Inc. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#ifdef TARGET_ENDIANNESS -extern uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -#else -extern uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stb, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -#endif - -#undef ARG1_DECL -#undef ARG1 -#undef SUFFIX -#undef TARGET_ENDIANNESS diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ldst_cached.h.inc new file mode 100644 index 0000000000..fd4bbb40e7 --- /dev/null +++ b/include/exec/memory_ldst_cached.h.inc @@ -0,0 +1,108 @@ +/* + * Memory access templates for MemoryRegionCache + * + * Copyright (c) 2018 Red Hat, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#define ADDRESS_SPACE_LD_CACHED(size) \ + glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached)) +#define ADDRESS_SPACE_LD_CACHED_SLOW(size) \ + glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached_slow)) +#define LD_P(size) \ + glue(glue(ld, size), glue(ENDIANNESS, _p)) + +static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 4 <= cache->len - addr); + if (likely(cache->ptr)) { + return LD_P(l)(cache->ptr + addr); + } else { + return ADDRESS_SPACE_LD_CACHED_SLOW(l)(cache, addr, attrs, result); + } +} + +static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 8 <= cache->len - addr); + if (likely(cache->ptr)) { + return LD_P(q)(cache->ptr + addr); + } else { + return ADDRESS_SPACE_LD_CACHED_SLOW(q)(cache, addr, attrs, result); + } +} + +static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 2 <= cache->len - addr); + if (likely(cache->ptr)) { + return LD_P(uw)(cache->ptr + addr); + } else { + return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result); + } +} + +#undef ADDRESS_SPACE_LD_CACHED +#undef ADDRESS_SPACE_LD_CACHED_SLOW +#undef LD_P + +#define ADDRESS_SPACE_ST_CACHED(size) \ + glue(glue(address_space_st, size), glue(ENDIANNESS, _cached)) +#define ADDRESS_SPACE_ST_CACHED_SLOW(size) \ + glue(glue(address_space_st, size), glue(ENDIANNESS, _cached_slow)) +#define ST_P(size) \ + glue(glue(st, size), glue(ENDIANNESS, _p)) + +static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 4 <= cache->len - addr); + if (likely(cache->ptr)) { + ST_P(l)(cache->ptr + addr, val); + } else { + ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result); + } +} + +static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 2 <= cache->len - addr); + if (likely(cache->ptr)) { + ST_P(w)(cache->ptr + addr, val); + } else { + ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result); + } +} + +static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) +{ + assert(addr < cache->len && 8 <= cache->len - addr); + if (likely(cache->ptr)) { + ST_P(q)(cache->ptr + addr, val); + } else { + ADDRESS_SPACE_ST_CACHED_SLOW(q)(cache, addr, val, attrs, result); + } +} + +#undef ADDRESS_SPACE_ST_CACHED +#undef ADDRESS_SPACE_ST_CACHED_SLOW +#undef ST_P + +#undef ENDIANNESS diff --git a/include/exec/memory_ldst_cached.inc.h b/include/exec/memory_ldst_cached.inc.h deleted file mode 100644 index fd4bbb40e7..0000000000 --- a/include/exec/memory_ldst_cached.inc.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Memory access templates for MemoryRegionCache - * - * Copyright (c) 2018 Red Hat, Inc. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#define ADDRESS_SPACE_LD_CACHED(size) \ - glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached)) -#define ADDRESS_SPACE_LD_CACHED_SLOW(size) \ - glue(glue(address_space_ld, size), glue(ENDIANNESS, _cached_slow)) -#define LD_P(size) \ - glue(glue(ld, size), glue(ENDIANNESS, _p)) - -static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 4 <= cache->len - addr); - if (likely(cache->ptr)) { - return LD_P(l)(cache->ptr + addr); - } else { - return ADDRESS_SPACE_LD_CACHED_SLOW(l)(cache, addr, attrs, result); - } -} - -static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 8 <= cache->len - addr); - if (likely(cache->ptr)) { - return LD_P(q)(cache->ptr + addr); - } else { - return ADDRESS_SPACE_LD_CACHED_SLOW(q)(cache, addr, attrs, result); - } -} - -static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 2 <= cache->len - addr); - if (likely(cache->ptr)) { - return LD_P(uw)(cache->ptr + addr); - } else { - return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result); - } -} - -#undef ADDRESS_SPACE_LD_CACHED -#undef ADDRESS_SPACE_LD_CACHED_SLOW -#undef LD_P - -#define ADDRESS_SPACE_ST_CACHED(size) \ - glue(glue(address_space_st, size), glue(ENDIANNESS, _cached)) -#define ADDRESS_SPACE_ST_CACHED_SLOW(size) \ - glue(glue(address_space_st, size), glue(ENDIANNESS, _cached_slow)) -#define ST_P(size) \ - glue(glue(st, size), glue(ENDIANNESS, _p)) - -static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 4 <= cache->len - addr); - if (likely(cache->ptr)) { - ST_P(l)(cache->ptr + addr, val); - } else { - ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result); - } -} - -static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache, - hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 2 <= cache->len - addr); - if (likely(cache->ptr)) { - ST_P(w)(cache->ptr + addr, val); - } else { - ADDRESS_SPACE_ST_CACHED_SLOW(w)(cache, addr, val, attrs, result); - } -} - -static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache, - hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) -{ - assert(addr < cache->len && 8 <= cache->len - addr); - if (likely(cache->ptr)) { - ST_P(q)(cache->ptr + addr, val); - } else { - ADDRESS_SPACE_ST_CACHED_SLOW(q)(cache, addr, val, attrs, result); - } -} - -#undef ADDRESS_SPACE_ST_CACHED -#undef ADDRESS_SPACE_ST_CACHED_SLOW -#undef ST_P - -#undef ENDIANNESS diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc new file mode 100644 index 0000000000..91f72973cb --- /dev/null +++ b/include/exec/memory_ldst_phys.h.inc @@ -0,0 +1,147 @@ +/* + * Physical memory access templates + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2015 Linaro, Inc. + * Copyright (c) 2016 Red Hat, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifdef TARGET_ENDIANNESS +static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldl, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldq, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_lduw, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stl, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stw, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) +{ + glue(address_space_stq, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} +#else +static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldl_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldl_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldq_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldq_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_ldub, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_lduw_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) +{ + return glue(address_space_lduw_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stl_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stb, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stw_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) +{ + glue(address_space_stw_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) +{ + glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + +static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) +{ + glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} +#endif + +#undef ARG1_DECL +#undef ARG1 +#undef SUFFIX +#undef TARGET_ENDIANNESS diff --git a/include/exec/memory_ldst_phys.inc.h b/include/exec/memory_ldst_phys.inc.h deleted file mode 100644 index 91f72973cb..0000000000 --- a/include/exec/memory_ldst_phys.inc.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Physical memory access templates - * - * Copyright (c) 2003 Fabrice Bellard - * Copyright (c) 2015 Linaro, Inc. - * Copyright (c) 2016 Red Hat, Inc. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#ifdef TARGET_ENDIANNESS -static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldl, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldq, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_lduw, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stl, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stw, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) -{ - glue(address_space_stq, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} -#else -static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldl_le, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldl_be, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldq_le, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldq_be, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_ldub, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_lduw_le, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) -{ - return glue(address_space_lduw_be, SUFFIX)(ARG1, addr, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stl_be, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stb, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stw_le, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) -{ - glue(address_space_stw_be, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) -{ - glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) -{ - glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} -#endif - -#undef ARG1_DECL -#undef ARG1 -#undef SUFFIX -#undef TARGET_ENDIANNESS diff --git a/target/s390x/cpu_features.c b/target/s390x/cpu_features.c index 9f817e3cfa..31ea8df246 100644 --- a/target/s390x/cpu_features.c +++ b/target/s390x/cpu_features.c @@ -23,7 +23,7 @@ .desc = _DESC, \ }, static const S390FeatDef s390_features[S390_FEAT_MAX] = { - #include "cpu_features_def.inc.h" + #include "cpu_features_def.h.inc" }; #undef DEF_FEAT diff --git a/target/s390x/cpu_features_def.h b/target/s390x/cpu_features_def.h index 412d356feb..87df31848e 100644 --- a/target/s390x/cpu_features_def.h +++ b/target/s390x/cpu_features_def.h @@ -17,7 +17,7 @@ #define DEF_FEAT(_FEAT, ...) S390_FEAT_##_FEAT, typedef enum { - #include "cpu_features_def.inc.h" + #include "cpu_features_def.h.inc" S390_FEAT_MAX, } S390Feat; #undef DEF_FEAT diff --git a/target/s390x/cpu_features_def.h.inc b/target/s390x/cpu_features_def.h.inc new file mode 100644 index 0000000000..5942f81f16 --- /dev/null +++ b/target/s390x/cpu_features_def.h.inc @@ -0,0 +1,371 @@ +/* + * RAW s390x CPU feature definitions: + * + * DEF_FEAT(_FEAT, _NAME, _TYPE, _BIT, _DESC): + * - _FEAT: Feature (enum) name used internally (S390_FEAT_##_FEAT) + * - _NAME: Feature name exposed to the user. + * - _TYPE: Feature type (S390_FEAT_TYPE_##_TYPE). + * - _BIT: Feature bit number within feature type block (unused for MISC). + * - _DESC: Feature description, exposed to the user. + * + * Copyright IBM Corp. 2016, 2018 + * Copyright Red Hat, Inc. 2019 + * + * Author(s): Michael Mueller + * David Hildenbrand + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at + * your option) any later version. See the COPYING file in the top-level + * directory. + */ + +/* Features exposed via the STFL(E) instruction. */ +DEF_FEAT(ESAN3, "esan3", STFL, 0, "Instructions marked as n3") +DEF_FEAT(ZARCH, "zarch", STFL, 1, "z/Architecture architectural mode") +DEF_FEAT(DAT_ENH, "dateh", STFL, 3, "DAT-enhancement facility") +DEF_FEAT(IDTE_SEGMENT, "idtes", STFL, 4, "IDTE selective TLB segment-table clearing") +DEF_FEAT(IDTE_REGION, "idter", STFL, 5, "IDTE selective TLB region-table clearing") +DEF_FEAT(ASN_LX_REUSE, "asnlxr", STFL, 6, "ASN-and-LX reuse facility") +DEF_FEAT(STFLE, "stfle", STFL, 7, "Store-facility-list-extended facility") +DEF_FEAT(EDAT, "edat", STFL, 8, "Enhanced-DAT facility") +DEF_FEAT(SENSE_RUNNING_STATUS, "srs", STFL, 9, "Sense-running-status facility") +DEF_FEAT(CONDITIONAL_SSKE, "csske", STFL, 10, "Conditional-SSKE facility") +DEF_FEAT(CONFIGURATION_TOPOLOGY, "ctop", STFL, 11, "Configuration-topology facility") +DEF_FEAT(AP_QUERY_CONFIG_INFO, "apqci", STFL, 12, "Query AP Configuration Information facility") +DEF_FEAT(IPTE_RANGE, "ipter", STFL, 13, "IPTE-range facility") +DEF_FEAT(NONQ_KEY_SETTING, "nonqks", STFL, 14, "Nonquiescing key-setting facility") +DEF_FEAT(AP_FACILITIES_TEST, "apft", STFL, 15, "AP Facilities Test facility") +DEF_FEAT(EXTENDED_TRANSLATION_2, "etf2", STFL, 16, "Extended-translation facility 2") +DEF_FEAT(MSA, "msa-base", STFL, 17, "Message-security-assist facility (excluding subfunctions)") +DEF_FEAT(LONG_DISPLACEMENT, "ldisp", STFL, 18, "Long-displacement facility") +DEF_FEAT(LONG_DISPLACEMENT_FAST, "ldisphp", STFL, 19, "Long-displacement facility has high performance") +DEF_FEAT(HFP_MADDSUB, "hfpm", STFL, 20, "HFP-multiply-add/subtract facility") +DEF_FEAT(EXTENDED_IMMEDIATE, "eimm", STFL, 21, "Extended-immediate facility") +DEF_FEAT(EXTENDED_TRANSLATION_3, "etf3", STFL, 22, "Extended-translation facility 3") +DEF_FEAT(HFP_UNNORMALIZED_EXT, "hfpue", STFL, 23, "HFP-unnormalized-extension facility") +DEF_FEAT(ETF2_ENH, "etf2eh", STFL, 24, "ETF2-enhancement facility") +DEF_FEAT(STORE_CLOCK_FAST, "stckf", STFL, 25, "Store-clock-fast facility") +DEF_FEAT(PARSING_ENH, "parseh", STFL, 26, "Parsing-enhancement facility") +DEF_FEAT(MOVE_WITH_OPTIONAL_SPEC, "mvcos", STFL, 27, "Move-with-optional-specification facility") +DEF_FEAT(TOD_CLOCK_STEERING, "tods-base", STFL, 28, "TOD-clock-steering facility (excluding subfunctions)") +DEF_FEAT(ETF3_ENH, "etf3eh", STFL, 30, "ETF3-enhancement facility") +DEF_FEAT(EXTRACT_CPU_TIME, "ectg", STFL, 31, "Extract-CPU-time facility") +DEF_FEAT(COMPARE_AND_SWAP_AND_STORE, "csst", STFL, 32, "Compare-and-swap-and-store facility") +DEF_FEAT(COMPARE_AND_SWAP_AND_STORE_2, "csst2", STFL, 33, "Compare-and-swap-and-store facility 2") +DEF_FEAT(GENERAL_INSTRUCTIONS_EXT, "ginste", STFL, 34, "General-instructions-extension facility") +DEF_FEAT(EXECUTE_EXT, "exrl", STFL, 35, "Execute-extensions facility") +DEF_FEAT(ENHANCED_MONITOR, "emon", STFL, 36, "Enhanced-monitor facility") +DEF_FEAT(FLOATING_POINT_EXT, "fpe", STFL, 37, "Floating-point extension facility") +DEF_FEAT(ORDER_PRESERVING_COMPRESSION, "opc", STFL, 38, "Order Preserving Compression facility") +DEF_FEAT(SET_PROGRAM_PARAMETERS, "sprogp", STFL, 40, "Set-program-parameters facility") +DEF_FEAT(FLOATING_POINT_SUPPPORT_ENH, "fpseh", STFL, 41, "Floating-point-support-enhancement facilities") +DEF_FEAT(DFP, "dfp", STFL, 42, "DFP (decimal-floating-point) facility") +DEF_FEAT(DFP_FAST, "dfphp", STFL, 43, "DFP (decimal-floating-point) facility has high performance") +DEF_FEAT(PFPO, "pfpo", STFL, 44, "PFPO instruction") +DEF_FEAT(STFLE_45, "stfle45", STFL, 45, "Various facilities introduced with z196") +DEF_FEAT(CMPSC_ENH, "cmpsceh", STFL, 47, "CMPSC-enhancement facility") +DEF_FEAT(DFP_ZONED_CONVERSION, "dfpzc", STFL, 48, "Decimal-floating-point zoned-conversion facility") +DEF_FEAT(STFLE_49, "stfle49", STFL, 49, "Various facilities introduced with zEC12") +DEF_FEAT(CONSTRAINT_TRANSACTIONAL_EXE, "cte", STFL, 50, "Constrained transactional-execution facility") +DEF_FEAT(LOCAL_TLB_CLEARING, "ltlbc", STFL, 51, "Local-TLB-clearing facility") +DEF_FEAT(INTERLOCKED_ACCESS_2, "iacc2", STFL, 52, "Interlocked-access facility 2") +DEF_FEAT(STFLE_53, "stfle53", STFL, 53, "Various facilities introduced with z13") +DEF_FEAT(ENTROPY_ENC_COMP, "eec", STFL, 54, "Entropy encoding compression facility") +DEF_FEAT(MSA_EXT_5, "msa5-base", STFL, 57, "Message-security-assist-extension-5 facility (excluding subfunctions)") +DEF_FEAT(MISC_INSTRUCTION_EXT, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2") +DEF_FEAT(SEMAPHORE_ASSIST, "sema", STFL, 59, "Semaphore-assist facility") +DEF_FEAT(TIME_SLICE_INSTRUMENTATION, "tsi", STFL, 60, "Time-slice Instrumentation facility") +DEF_FEAT(MISC_INSTRUCTION_EXT3, "minste3", STFL, 61, "Miscellaneous-Instruction-Extensions Facility 3") +DEF_FEAT(RUNTIME_INSTRUMENTATION, "ri", STFL, 64, "CPU runtime-instrumentation facility") +DEF_FEAT(AP_QUEUE_INTERRUPT_CONTROL, "apqi", STFL, 65, "AP-Queue interruption facility") +DEF_FEAT(ZPCI, "zpci", STFL, 69, "z/PCI facility") +DEF_FEAT(ADAPTER_EVENT_NOTIFICATION, "aen", STFL, 71, "General-purpose-adapter-event-notification facility") +DEF_FEAT(ADAPTER_INT_SUPPRESSION, "ais", STFL, 72, "General-purpose-adapter-interruption-suppression facility") +DEF_FEAT(TRANSACTIONAL_EXE, "te", STFL, 73, "Transactional-execution facility") +DEF_FEAT(STORE_HYPERVISOR_INFO, "sthyi", STFL, 74, "Store-hypervisor-information facility") +DEF_FEAT(ACCESS_EXCEPTION_FS_INDICATION, "aefsi", STFL, 75, "Access-exception-fetch/store-indication facility") +DEF_FEAT(MSA_EXT_3, "msa3-base", STFL, 76, "Message-security-assist-extension-3 facility (excluding subfunctions)") +DEF_FEAT(MSA_EXT_4, "msa4-base", STFL, 77, "Message-security-assist-extension-4 facility (excluding subfunctions)") +DEF_FEAT(EDAT_2, "edat2", STFL, 78, "Enhanced-DAT facility 2") +DEF_FEAT(DFP_PACKED_CONVERSION, "dfppc", STFL, 80, "Decimal-floating-point packed-conversion facility") +DEF_FEAT(PPA15, "ppa15", STFL, 81, "PPA15 is installed") +DEF_FEAT(BPB, "bpb", STFL, 82, "Branch prediction blocking") +DEF_FEAT(VECTOR, "vx", STFL, 129, "Vector facility") +DEF_FEAT(INSTRUCTION_EXEC_PROT, "iep", STFL, 130, "Instruction-execution-protection facility") +DEF_FEAT(SIDE_EFFECT_ACCESS_ESOP2, "sea_esop2", STFL, 131, "Side-effect-access facility and Enhanced-suppression-on-protection facility 2") +DEF_FEAT(GUARDED_STORAGE, "gs", STFL, 133, "Guarded-storage facility") +DEF_FEAT(VECTOR_PACKED_DECIMAL, "vxpd", STFL, 134, "Vector packed decimal facility") +DEF_FEAT(VECTOR_ENH, "vxeh", STFL, 135, "Vector enhancements facility") +DEF_FEAT(MULTIPLE_EPOCH, "mepoch", STFL, 139, "Multiple-epoch facility") +DEF_FEAT(TEST_PENDING_EXT_INTERRUPTION, "tpei", STFL, 144, "Test-pending-external-interruption facility") +DEF_FEAT(INSERT_REFERENCE_BITS_MULT, "irbm", STFL, 145, "Insert-reference-bits-multiple facility") +DEF_FEAT(MSA_EXT_8, "msa8-base", STFL, 146, "Message-security-assist-extension-8 facility (excluding subfunctions)") +DEF_FEAT(CMM_NT, "cmmnt", STFL, 147, "CMM: ESSA-enhancement (no translate) facility") +DEF_FEAT(VECTOR_ENH2, "vxeh2", STFL, 148, "Vector Enhancements facility 2") +DEF_FEAT(ESORT_BASE, "esort-base", STFL, 150, "Enhanced-sort facility (excluding subfunctions)") +DEF_FEAT(DEFLATE_BASE, "deflate-base", STFL, 151, "Deflate-conversion facility (excluding subfunctions)") +DEF_FEAT(VECTOR_PACKED_DECIMAL_ENH, "vxpdeh", STFL, 152, "Vector-Packed-Decimal-Enhancement Facility") +DEF_FEAT(MSA_EXT_9, "msa9-base", STFL, 155, "Message-security-assist-extension-9 facility (excluding subfunctions)") +DEF_FEAT(ETOKEN, "etoken", STFL, 156, "Etoken facility") +DEF_FEAT(UNPACK, "unpack", STFL, 161, "Unpack facility") + +/* Features exposed via SCLP SCCB Byte 80 - 98 (bit numbers relative to byte-80) */ +DEF_FEAT(SIE_GSLS, "gsls", SCLP_CONF_CHAR, 40, "SIE: Guest-storage-limit-suppression facility") +DEF_FEAT(ESOP, "esop", SCLP_CONF_CHAR, 46, "Enhanced-suppression-on-protection facility") +DEF_FEAT(HPMA2, "hpma2", SCLP_CONF_CHAR, 90, "Host page management assist 2 Facility") /* 91-2 */ +DEF_FEAT(SIE_KSS, "kss", SCLP_CONF_CHAR, 151, "SIE: Keyless-subset facility") /* 98-7 */ + +/* Features exposed via SCLP SCCB Byte 116 - 119 (bit numbers relative to byte-116) */ +DEF_FEAT(SIE_64BSCAO, "64bscao", SCLP_CONF_CHAR_EXT, 0, "SIE: 64-bit-SCAO facility") +DEF_FEAT(SIE_CMMA, "cmma", SCLP_CONF_CHAR_EXT, 1, "SIE: Collaborative-memory-management assist") +DEF_FEAT(SIE_PFMFI, "pfmfi", SCLP_CONF_CHAR_EXT, 9, "SIE: PFMF interpretation facility") +DEF_FEAT(SIE_IBS, "ibs", SCLP_CONF_CHAR_EXT, 10, "SIE: Interlock-and-broadcast-suppression facility") + +/* Features exposed via SCLP CPU info. */ +DEF_FEAT(SIE_F2, "sief2", SCLP_CPU, 4, "SIE: interception format 2 (Virtual SIE)") +DEF_FEAT(SIE_SKEY, "skey", SCLP_CPU, 5, "SIE: Storage-key facility") +DEF_FEAT(SIE_GPERE, "gpereh", SCLP_CPU, 10, "SIE: Guest-PER enhancement facility") +DEF_FEAT(SIE_SIIF, "siif", SCLP_CPU, 11, "SIE: Shared IPTE-interlock facility") +DEF_FEAT(SIE_SIGPIF, "sigpif", SCLP_CPU, 12, "SIE: SIGP interpretation facility") +DEF_FEAT(SIE_IB, "ib", SCLP_CPU, 42, "SIE: Intervention bypass facility") +DEF_FEAT(SIE_CEI, "cei", SCLP_CPU, 43, "SIE: Conditional-external-interception facility") + +/* + * Features exposed via no feature bit (but e.g., instruction sensing) + * -> the feature bit number is irrelavant + */ +DEF_FEAT(DAT_ENH_2, "dateh2", MISC, 0, "DAT-enhancement facility 2") +DEF_FEAT(CMM, "cmm", MISC, 0, "Collaborative-memory-management facility") +DEF_FEAT(AP, "ap", MISC, 0, "AP instructions installed") + +/* Features exposed via the PLO instruction. */ +DEF_FEAT(PLO_CL, "plo-cl", PLO, 0, "PLO Compare and load (32 bit in general registers)") +DEF_FEAT(PLO_CLG, "plo-clg", PLO, 1, "PLO Compare and load (64 bit in parameter list)") +DEF_FEAT(PLO_CLGR, "plo-clgr", PLO, 2, "PLO Compare and load (32 bit in general registers)") +DEF_FEAT(PLO_CLX, "plo-clx", PLO, 3, "PLO Compare and load (128 bit in parameter list)") +DEF_FEAT(PLO_CS, "plo-cs", PLO, 4, "PLO Compare and swap (32 bit in general registers)") +DEF_FEAT(PLO_CSG, "plo-csg", PLO, 5, "PLO Compare and swap (64 bit in parameter list)") +DEF_FEAT(PLO_CSGR, "plo-csgr", PLO, 6, "PLO Compare and swap (32 bit in general registers)") +DEF_FEAT(PLO_CSX, "plo-csx", PLO, 7, "PLO Compare and swap (128 bit in parameter list)") +DEF_FEAT(PLO_DCS, "plo-dcs", PLO, 8, "PLO Double compare and swap (32 bit in general registers)") +DEF_FEAT(PLO_DCSG, "plo-dcsg", PLO, 9, "PLO Double compare and swap (64 bit in parameter list)") +DEF_FEAT(PLO_DCSGR, "plo-dcsgr", PLO, 10, "PLO Double compare and swap (32 bit in general registers)") +DEF_FEAT(PLO_DCSX, "plo-dcsx", PLO, 11, "PLO Double compare and swap (128 bit in parameter list)") +DEF_FEAT(PLO_CSST, "plo-csst", PLO, 12, "PLO Compare and swap and store (32 bit in general registers)") +DEF_FEAT(PLO_CSSTG, "plo-csstg", PLO, 13, "PLO Compare and swap and store (64 bit in parameter list)") +DEF_FEAT(PLO_CSSTGR, "plo-csstgr", PLO, 14, "PLO Compare and swap and store (32 bit in general registers)") +DEF_FEAT(PLO_CSSTX, "plo-csstx", PLO, 15, "PLO Compare and swap and store (128 bit in parameter list)") +DEF_FEAT(PLO_CSDST, "plo-csdst", PLO, 16, "PLO Compare and swap and double store (32 bit in general registers)") +DEF_FEAT(PLO_CSDSTG, "plo-csdstg", PLO, 17, "PLO Compare and swap and double store (64 bit in parameter list)") +DEF_FEAT(PLO_CSDSTGR, "plo-csdstgr", PLO, 18, "PLO Compare and swap and double store (32 bit in general registers)") +DEF_FEAT(PLO_CSDSTX, "plo-csdstx", PLO, 19, "PLO Compare and swap and double store (128 bit in parameter list)") +DEF_FEAT(PLO_CSTST, "plo-cstst", PLO, 20, "PLO Compare and swap and triple store (32 bit in general registers)") +DEF_FEAT(PLO_CSTSTG, "plo-cststg", PLO, 21, "PLO Compare and swap and triple store (64 bit in parameter list)") +DEF_FEAT(PLO_CSTSTGR, "plo-cststgr", PLO, 22, "PLO Compare and swap and triple store (32 bit in general registers)") +DEF_FEAT(PLO_CSTSTX, "plo-cststx", PLO, 23, "PLO Compare and swap and triple store (128 bit in parameter list)") + +/* Features exposed via the PTFF instruction. */ +DEF_FEAT(PTFF_QTO, "ptff-qto", PTFF, 1, "PTFF Query TOD Offset") +DEF_FEAT(PTFF_QSI, "ptff-qsi", PTFF, 2, "PTFF Query Steering Information") +DEF_FEAT(PTFF_QPT, "ptff-qpc", PTFF, 3, "PTFF Query Physical Clock") +DEF_FEAT(PTFF_QUI, "ptff-qui", PTFF, 4, "PTFF Query UTC Information") +DEF_FEAT(PTFF_QTOU, "ptff-qtou", PTFF, 5, "PTFF Query TOD Offset User") +DEF_FEAT(PTFF_QSIE, "ptff-qsie", PTFF, 10, "PTFF Query Steering Information Extended") +DEF_FEAT(PTFF_QTOUE, "ptff-qtoue", PTFF, 13, "PTFF Query TOD Offset User Extended") +DEF_FEAT(PTFF_STO, "ptff-sto", PTFF, 65, "PTFF Set TOD Offset") +DEF_FEAT(PTFF_STOU, "ptff-stou", PTFF, 69, "PTFF Set TOD Offset User") +DEF_FEAT(PTFF_STOE, "ptff-stoe", PTFF, 73, "PTFF Set TOD Offset Extended") +DEF_FEAT(PTFF_STOUE, "ptff-stoue", PTFF, 77, "PTFF Set TOD Offset User Extended") + +/* Features exposed via the KMAC instruction. */ +DEF_FEAT(KMAC_DEA, "kmac-dea", KMAC, 1, "KMAC DEA") +DEF_FEAT(KMAC_TDEA_128, "kmac-tdea-128", KMAC, 2, "KMAC TDEA-128") +DEF_FEAT(KMAC_TDEA_192, "kmac-tdea-192", KMAC, 3, "KMAC TDEA-192") +DEF_FEAT(KMAC_EDEA, "kmac-edea", KMAC, 9, "KMAC Encrypted-DEA") +DEF_FEAT(KMAC_ETDEA_128, "kmac-etdea-128", KMAC, 10, "KMAC Encrypted-TDEA-128") +DEF_FEAT(KMAC_ETDEA_192, "kmac-etdea-192", KMAC, 11, "KMAC Encrypted-TDEA-192") +DEF_FEAT(KMAC_AES_128, "kmac-aes-128", KMAC, 18, "KMAC AES-128") +DEF_FEAT(KMAC_AES_192, "kmac-aes-192", KMAC, 19, "KMAC AES-192") +DEF_FEAT(KMAC_AES_256, "kmac-aes-256", KMAC, 20, "KMAC AES-256") +DEF_FEAT(KMAC_EAES_128, "kmac-eaes-128", KMAC, 26, "KMAC Encrypted-AES-128") +DEF_FEAT(KMAC_EAES_192, "kmac-eaes-192", KMAC, 27, "KMAC Encrypted-AES-192") +DEF_FEAT(KMAC_EAES_256, "kmac-eaes-256", KMAC, 28, "KMAC Encrypted-AES-256") + +/* Features exposed via the KMC instruction. */ +DEF_FEAT(KMC_DEA, "kmc-dea", KMC, 1, "KMC DEA") +DEF_FEAT(KMC_TDEA_128, "kmc-tdea-128", KMC, 2, "KMC TDEA-128") +DEF_FEAT(KMC_TDEA_192, "kmc-tdea-192", KMC, 3, "KMC TDEA-192") +DEF_FEAT(KMC_EDEA, "kmc-edea", KMC, 9, "KMC Encrypted-DEA") +DEF_FEAT(KMC_ETDEA_128, "kmc-etdea-128", KMC, 10, "KMC Encrypted-TDEA-128") +DEF_FEAT(KMC_ETDEA_192, "kmc-etdea-192", KMC, 11, "KMC Encrypted-TDEA-192") +DEF_FEAT(KMC_AES_128, "kmc-aes-128", KMC, 18, "KMC AES-128") +DEF_FEAT(KMC_AES_192, "kmc-aes-192", KMC, 19, "KMC AES-192") +DEF_FEAT(KMC_AES_256, "kmc-aes-256", KMC, 20, "KMC AES-256") +DEF_FEAT(KMC_EAES_128, "kmc-eaes-128", KMC, 26, "KMC Encrypted-AES-128") +DEF_FEAT(KMC_EAES_192, "kmc-eaes-192", KMC, 27, "KMC Encrypted-AES-192") +DEF_FEAT(KMC_EAES_256, "kmc-eaes-256", KMC, 28, "KMC Encrypted-AES-256") +DEF_FEAT(KMC_PRNG, "kmc-prng", KMC, 67, "KMC PRNG") + +/* Features exposed via the KM instruction. */ +DEF_FEAT(KM_DEA, "km-dea", KM, 1, "KM DEA") +DEF_FEAT(KM_TDEA_128, "km-tdea-128", KM, 2, "KM TDEA-128") +DEF_FEAT(KM_TDEA_192, "km-tdea-192", KM, 3, "KM TDEA-192") +DEF_FEAT(KM_EDEA, "km-edea", KM, 9, "KM Encrypted-DEA") +DEF_FEAT(KM_ETDEA_128, "km-etdea-128", KM, 10, "KM Encrypted-TDEA-128") +DEF_FEAT(KM_ETDEA_192, "km-etdea-192", KM, 11, "KM Encrypted-TDEA-192") +DEF_FEAT(KM_AES_128, "km-aes-128", KM, 18, "KM AES-128") +DEF_FEAT(KM_AES_192, "km-aes-192", KM, 19, "KM AES-192") +DEF_FEAT(KM_AES_256, "km-aes-256", KM, 20, "KM AES-256") +DEF_FEAT(KM_EAES_128, "km-eaes-128", KM, 26, "KM Encrypted-AES-128") +DEF_FEAT(KM_EAES_192, "km-eaes-192", KM, 27, "KM Encrypted-AES-192") +DEF_FEAT(KM_EAES_256, "km-eaes-256", KM, 28, "KM Encrypted-AES-256") +DEF_FEAT(KM_XTS_AES_128, "km-xts-aes-128", KM, 50, "KM XTS-AES-128") +DEF_FEAT(KM_XTS_AES_256, "km-xts-aes-256", KM, 52, "KM XTS-AES-256") +DEF_FEAT(KM_XTS_EAES_128, "km-xts-eaes-128", KM, 58, "KM XTS-Encrypted-AES-128") +DEF_FEAT(KM_XTS_EAES_256, "km-xts-eaes-256", KM, 60, "KM XTS-Encrypted-AES-256") + +/* Features exposed via the KIMD instruction. */ +DEF_FEAT(KIMD_SHA_1, "kimd-sha-1", KIMD, 1, "KIMD SHA-1") +DEF_FEAT(KIMD_SHA_256, "kimd-sha-256", KIMD, 2, "KIMD SHA-256") +DEF_FEAT(KIMD_SHA_512, "kimd-sha-512", KIMD, 3, "KIMD SHA-512") +DEF_FEAT(KIMD_SHA3_224, "kimd-sha3-224", KIMD, 32, "KIMD SHA3-224") +DEF_FEAT(KIMD_SHA3_256, "kimd-sha3-256", KIMD, 33, "KIMD SHA3-256") +DEF_FEAT(KIMD_SHA3_384, "kimd-sha3-384", KIMD, 34, "KIMD SHA3-384") +DEF_FEAT(KIMD_SHA3_512, "kimd-sha3-512", KIMD, 35, "KIMD SHA3-512") +DEF_FEAT(KIMD_SHAKE_128, "kimd-shake-128", KIMD, 36, "KIMD SHAKE-128") +DEF_FEAT(KIMD_SHAKE_256, "kimd-shake-256", KIMD, 37, "KIMD SHAKE-256") +DEF_FEAT(KIMD_GHASH, "kimd-ghash", KIMD, 65, "KIMD GHASH") + +/* Features exposed via the KLMD instruction. */ +DEF_FEAT(KLMD_SHA_1, "klmd-sha-1", KLMD, 1, "KLMD SHA-1") +DEF_FEAT(KLMD_SHA_256, "klmd-sha-256", KLMD, 2, "KLMD SHA-256") +DEF_FEAT(KLMD_SHA_512, "klmd-sha-512", KLMD, 3, "KLMD SHA-512") +DEF_FEAT(KLMD_SHA3_224, "klmd-sha3-224", KLMD, 32, "KLMD SHA3-224") +DEF_FEAT(KLMD_SHA3_256, "klmd-sha3-256", KLMD, 33, "KLMD SHA3-256") +DEF_FEAT(KLMD_SHA3_384, "klmd-sha3-384", KLMD, 34, "KLMD SHA3-384") +DEF_FEAT(KLMD_SHA3_512, "klmd-sha3-512", KLMD, 35, "KLMD SHA3-512") +DEF_FEAT(KLMD_SHAKE_128, "klmd-shake-128", KLMD, 36, "KLMD SHAKE-128") +DEF_FEAT(KLMD_SHAKE_256, "klmd-shake-256", KLMD, 37, "KLMD SHAKE-256") + +/* Features exposed via the PCKMO instruction. */ +DEF_FEAT(PCKMO_EDEA, "pckmo-edea", PCKMO, 1, "PCKMO Encrypted-DEA-Key") +DEF_FEAT(PCKMO_ETDEA_128, "pckmo-etdea-128", PCKMO, 2, "PCKMO Encrypted-TDEA-128-Key") +DEF_FEAT(PCKMO_ETDEA_256, "pckmo-etdea-192", PCKMO, 3, "PCKMO Encrypted-TDEA-192-Key") +DEF_FEAT(PCKMO_AES_128, "pckmo-aes-128", PCKMO, 18, "PCKMO Encrypted-AES-128-Key") +DEF_FEAT(PCKMO_AES_192, "pckmo-aes-192", PCKMO, 19, "PCKMO Encrypted-AES-192-Key") +DEF_FEAT(PCKMO_AES_256, "pckmo-aes-256", PCKMO, 20, "PCKMO Encrypted-AES-256-Key") +DEF_FEAT(PCKMO_ECC_P256, "pckmo-ecc-p256", PCKMO, 32, "PCKMO Encrypt-ECC-P256-Key") +DEF_FEAT(PCKMO_ECC_P384, "pckmo-ecc-p384", PCKMO, 33, "PCKMO Encrypt-ECC-P384-Key") +DEF_FEAT(PCKMO_ECC_P521, "pckmo-ecc-p521", PCKMO, 34, "PCKMO Encrypt-ECC-P521-Key") +DEF_FEAT(PCKMO_ECC_ED25519, "pckmo-ecc-ed25519", PCKMO, 40 , "PCKMO Encrypt-ECC-Ed25519-Key") +DEF_FEAT(PCKMO_ECC_ED448, "pckmo-ecc-ed448", PCKMO, 41 , "PCKMO Encrypt-ECC-Ed448-Key") + +/* Features exposed via the KMCTR instruction. */ +DEF_FEAT(KMCTR_DEA, "kmctr-dea", KMCTR, 1, "KMCTR DEA") +DEF_FEAT(KMCTR_TDEA_128, "kmctr-tdea-128", KMCTR, 2, "KMCTR TDEA-128") +DEF_FEAT(KMCTR_TDEA_192, "kmctr-tdea-192", KMCTR, 3, "KMCTR TDEA-192") +DEF_FEAT(KMCTR_EDEA, "kmctr-edea", KMCTR, 9, "KMCTR Encrypted-DEA") +DEF_FEAT(KMCTR_ETDEA_128, "kmctr-etdea-128", KMCTR, 10, "KMCTR Encrypted-TDEA-128") +DEF_FEAT(KMCTR_ETDEA_192, "kmctr-etdea-192", KMCTR, 11, "KMCTR Encrypted-TDEA-192") +DEF_FEAT(KMCTR_AES_128, "kmctr-aes-128", KMCTR, 18, "KMCTR AES-128") +DEF_FEAT(KMCTR_AES_192, "kmctr-aes-192", KMCTR, 19, "KMCTR AES-192") +DEF_FEAT(KMCTR_AES_256, "kmctr-aes-256", KMCTR, 20, "KMCTR AES-256") +DEF_FEAT(KMCTR_EAES_128, "kmctr-eaes-128", KMCTR, 26, "KMCTR Encrypted-AES-128") +DEF_FEAT(KMCTR_EAES_192, "kmctr-eaes-192", KMCTR, 27, "KMCTR Encrypted-AES-192") +DEF_FEAT(KMCTR_EAES_256, "kmctr-eaes-256", KMCTR, 28, "KMCTR Encrypted-AES-256") + +/* Features exposed via the KMF instruction. */ +DEF_FEAT(KMF_DEA, "kmf-dea", KMF, 1, "KMF DEA") +DEF_FEAT(KMF_TDEA_128, "kmf-tdea-128", KMF, 2, "KMF TDEA-128") +DEF_FEAT(KMF_TDEA_192, "kmf-tdea-192", KMF, 3, "KMF TDEA-192") +DEF_FEAT(KMF_EDEA, "kmf-edea", KMF, 9, "KMF Encrypted-DEA") +DEF_FEAT(KMF_ETDEA_128, "kmf-etdea-128", KMF, 10, "KMF Encrypted-TDEA-128") +DEF_FEAT(KMF_ETDEA_192, "kmf-etdea-192", KMF, 11, "KMF Encrypted-TDEA-192") +DEF_FEAT(KMF_AES_128, "kmf-aes-128", KMF, 18, "KMF AES-128") +DEF_FEAT(KMF_AES_192, "kmf-aes-192", KMF, 19, "KMF AES-192") +DEF_FEAT(KMF_AES_256, "kmf-aes-256", KMF, 20, "KMF AES-256") +DEF_FEAT(KMF_EAES_128, "kmf-eaes-128", KMF, 26, "KMF Encrypted-AES-128") +DEF_FEAT(KMF_EAES_192, "kmf-eaes-192", KMF, 27, "KMF Encrypted-AES-192") +DEF_FEAT(KMF_EAES_256, "kmf-eaes-256", KMF, 28, "KMF Encrypted-AES-256") + +/* Features exposed via the KMO instruction. */ +DEF_FEAT(KMO_DEA, "kmo-dea", KMO, 1, "KMO DEA") +DEF_FEAT(KMO_TDEA_128, "kmo-tdea-128", KMO, 2, "KMO TDEA-128") +DEF_FEAT(KMO_TDEA_192, "kmo-tdea-192", KMO, 3, "KMO TDEA-192") +DEF_FEAT(KMO_EDEA, "kmo-edea", KMO, 9, "KMO Encrypted-DEA") +DEF_FEAT(KMO_ETDEA_128, "kmo-etdea-128", KMO, 10, "KMO Encrypted-TDEA-128") +DEF_FEAT(KMO_ETDEA_192, "kmo-etdea-192", KMO, 11, "KMO Encrypted-TDEA-192") +DEF_FEAT(KMO_AES_128, "kmo-aes-128", KMO, 18, "KMO AES-128") +DEF_FEAT(KMO_AES_192, "kmo-aes-192", KMO, 19, "KMO AES-192") +DEF_FEAT(KMO_AES_256, "kmo-aes-256", KMO, 20, "KMO AES-256") +DEF_FEAT(KMO_EAES_128, "kmo-eaes-128", KMO, 26, "KMO Encrypted-AES-128") +DEF_FEAT(KMO_EAES_192, "kmo-eaes-192", KMO, 27, "KMO Encrypted-AES-192") +DEF_FEAT(KMO_EAES_256, "kmo-eaes-256", KMO, 28, "KMO Encrypted-AES-256") + +/* Features exposed via the PCC instruction. */ +DEF_FEAT(PCC_CMAC_DEA, "pcc-cmac-dea", PCC, 1, "PCC Compute-Last-Block-CMAC-Using-DEA") +DEF_FEAT(PCC_CMAC_TDEA_128, "pcc-cmac-tdea-128", PCC, 2, "PCC Compute-Last-Block-CMAC-Using-TDEA-128") +DEF_FEAT(PCC_CMAC_TDEA_192, "pcc-cmac-tdea-192", PCC, 3, "PCC Compute-Last-Block-CMAC-Using-TDEA-192") +DEF_FEAT(PCC_CMAC_ETDEA_128, "pcc-cmac-edea", PCC, 9, "PCC Compute-Last-Block-CMAC-Using-Encrypted-DEA") +DEF_FEAT(PCC_CMAC_ETDEA_192, "pcc-cmac-etdea-128", PCC, 10, "PCC Compute-Last-Block-CMAC-Using-Encrypted-TDEA-128") +DEF_FEAT(PCC_CMAC_TDEA, "pcc-cmac-etdea-192", PCC, 11, "PCC Compute-Last-Block-CMAC-Using-EncryptedTDEA-192") +DEF_FEAT(PCC_CMAC_AES_128, "pcc-cmac-aes-128", PCC, 18, "PCC Compute-Last-Block-CMAC-Using-AES-128") +DEF_FEAT(PCC_CMAC_AES_192, "pcc-cmac-aes-192", PCC, 19, "PCC Compute-Last-Block-CMAC-Using-AES-192") +DEF_FEAT(PCC_CMAC_AES_256, "pcc-cmac-aes-256", PCC, 20, "PCC Compute-Last-Block-CMAC-Using-AES-256") +DEF_FEAT(PCC_CMAC_EAES_128, "pcc-cmac-eaes-128", PCC, 26, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-128") +DEF_FEAT(PCC_CMAC_EAES_192, "pcc-cmac-eaes-192", PCC, 27, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-192") +DEF_FEAT(PCC_CMAC_EAES_256, "pcc-cmac-eaes-256", PCC, 28, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-256") +DEF_FEAT(PCC_XTS_AES_128, "pcc-xts-aes-128", PCC, 50, "PCC Compute-XTS-Parameter-Using-AES-128") +DEF_FEAT(PCC_XTS_AES_256, "pcc-xts-aes-256", PCC, 52, "PCC Compute-XTS-Parameter-Using-AES-256") +DEF_FEAT(PCC_XTS_EAES_128, "pcc-xts-eaes-128", PCC, 58, "PCC Compute-XTS-Parameter-Using-Encrypted-AES-128") +DEF_FEAT(PCC_XTS_EAES_256, "pcc-xts-eaes-256", PCC, 60, "PCC Compute-XTS-Parameter-Using-Encrypted-AES-256") +DEF_FEAT(PCC_SCALAR_MULT_P256, "pcc-scalar-mult-p256", PCC, 64, "PCC Scalar-Multiply-P256") +DEF_FEAT(PCC_SCALAR_MULT_P384, "pcc-scalar-mult-p384", PCC, 65, "PCC Scalar-Multiply-P384") +DEF_FEAT(PCC_SCALAR_MULT_P512, "pcc-scalar-mult-p521", PCC, 66, "PCC Scalar-Multiply-P521") +DEF_FEAT(PCC_SCALAR_MULT_ED25519, "pcc-scalar-mult-ed25519", PCC, 72, "PCC Scalar-Multiply-Ed25519") +DEF_FEAT(PCC_SCALAR_MULT_ED448, "pcc-scalar-mult-ed448", PCC, 73, "PCC Scalar-Multiply-Ed448") +DEF_FEAT(PCC_SCALAR_MULT_X25519, "pcc-scalar-mult-x25519", PCC, 80, "PCC Scalar-Multiply-X25519") +DEF_FEAT(PCC_SCALAR_MULT_X448, "pcc-scalar-mult-x448", PCC, 81, "PCC Scalar-Multiply-X448") + +/* Features exposed via the PPNO/PRNO instruction. */ +DEF_FEAT(PPNO_SHA_512_DRNG, "ppno-sha-512-drng", PPNO, 3, "PPNO SHA-512-DRNG") +DEF_FEAT(PRNO_TRNG_QRTCR, "prno-trng-qrtcr", PPNO, 112, "PRNO TRNG-Query-Raw-to-Conditioned-Ratio") +DEF_FEAT(PRNO_TRNG, "prno-trng", PPNO, 114, "PRNO TRNG") + +/* Features exposed via the KMA instruction. */ +DEF_FEAT(KMA_GCM_AES_128, "kma-gcm-aes-128", KMA, 18, "KMA GCM-AES-128") +DEF_FEAT(KMA_GCM_AES_192, "kma-gcm-aes-192", KMA, 19, "KMA GCM-AES-192") +DEF_FEAT(KMA_GCM_AES_256, "kma-gcm-aes-256", KMA, 20, "KMA GCM-AES-256") +DEF_FEAT(KMA_GCM_EAES_128, "kma-gcm-eaes-128", KMA, 26, "KMA GCM-Encrypted-AES-128") +DEF_FEAT(KMA_GCM_EAES_192, "kma-gcm-eaes-192", KMA, 27, "KMA GCM-Encrypted-AES-192") +DEF_FEAT(KMA_GCM_EAES_256, "kma-gcm-eaes-256", KMA, 28, "KMA GCM-Encrypted-AES-256") + +/* Features exposed via the KDSA instruction. */ +DEF_FEAT(KDSA_ECDSA_VERIFY_P256, "kdsa-ecdsa-verify-p256", KDSA, 1, "KDSA ECDSA-Verify-P256") +DEF_FEAT(KDSA_ECDSA_VERIFY_P384, "kdsa-ecdsa-verify-p384", KDSA, 2, "KDSA ECDSA-Verify-P384") +DEF_FEAT(KDSA_ECDSA_VERIFY_P512, "kdsa-ecdsa-verify-p521", KDSA, 3, "KDSA ECDSA-Verify-P521") +DEF_FEAT(KDSA_ECDSA_SIGN_P256, "kdsa-ecdsa-sign-p256", KDSA, 9, "KDSA ECDSA-Sign-P256") +DEF_FEAT(KDSA_ECDSA_SIGN_P384, "kdsa-ecdsa-sign-p384", KDSA, 10, "KDSA ECDSA-Sign-P384") +DEF_FEAT(KDSA_ECDSA_SIGN_P512, "kdsa-ecdsa-sign-p521", KDSA, 11, "KDSA ECDSA-Sign-P521") +DEF_FEAT(KDSA_EECDSA_SIGN_P256, "kdsa-eecdsa-sign-p256", KDSA, 17, "KDSA Encrypted-ECDSA-Sign-P256") +DEF_FEAT(KDSA_EECDSA_SIGN_P384, "kdsa-eecdsa-sign-p384", KDSA, 18, "KDSA Encrypted-ECDSA-Sign-P384") +DEF_FEAT(KDSA_EECDSA_SIGN_P512, "kdsa-eecdsa-sign-p521", KDSA, 19, "KDSA Encrypted-ECDSA-Sign-P521") +DEF_FEAT(KDSA_EDDSA_VERIFY_ED25519, "kdsa-eddsa-verify-ed25519", KDSA, 32, "KDSA EdDSA-Verify-Ed25519") +DEF_FEAT(KDSA_EDDSA_VERIFY_ED448, "kdsa-eddsa-verify-ed448", KDSA, 36, "KDSA EdDSA-Verify-Ed448") +DEF_FEAT(KDSA_EDDSA_SIGN_ED25519, "kdsa-eddsa-sign-ed25519", KDSA, 40, "KDSA EdDSA-Sign-Ed25519") +DEF_FEAT(KDSA_EDDSA_SIGN_ED448, "kdsa-eddsa-sign-ed448", KDSA, 44, "KDSA EdDSA-Sign-Ed448") +DEF_FEAT(KDSA_EEDDSA_SIGN_ED25519, "kdsa-eeddsa-sign-ed25519", KDSA, 48, "KDSA Encrypted-EdDSA-Sign-Ed25519") +DEF_FEAT(KDSA_EEDDSA_SIGN_ED448, "kdsa-eeddsa-sign-ed448", KDSA, 52, "KDSA Encrypted-EdDSA-Sign-Ed448") + +/* Features exposed via the SORTL instruction. */ +DEF_FEAT(SORTL_SFLR, "sortl-sflr", SORTL, 1, "SORTL SFLR") +DEF_FEAT(SORTL_SVLR, "sortl-svlr", SORTL, 2, "SORTL SVLR") +DEF_FEAT(SORTL_32, "sortl-32", SORTL, 130, "SORTL 32 input lists") +DEF_FEAT(SORTL_128, "sortl-128", SORTL, 132, "SORTL 128 input lists") +DEF_FEAT(SORTL_F0, "sortl-f0", SORTL, 192, "SORTL format 0 parameter-block") + +/* Features exposed via the DEFLATE instruction. */ +DEF_FEAT(DEFLATE_GHDT, "dfltcc-gdht", DFLTCC, 1, "DFLTCC GDHT") +DEF_FEAT(DEFLATE_CMPR, "dfltcc-cmpr", DFLTCC, 2, "DFLTCC CMPR") +DEF_FEAT(DEFLATE_XPND, "dfltcc-xpnd", DFLTCC, 4, "DFLTCC XPND") +DEF_FEAT(DEFLATE_F0, "dfltcc-f0", DFLTCC, 192, "DFLTCC format 0 parameter-block") diff --git a/target/s390x/cpu_features_def.inc.h b/target/s390x/cpu_features_def.inc.h deleted file mode 100644 index 5942f81f16..0000000000 --- a/target/s390x/cpu_features_def.inc.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * RAW s390x CPU feature definitions: - * - * DEF_FEAT(_FEAT, _NAME, _TYPE, _BIT, _DESC): - * - _FEAT: Feature (enum) name used internally (S390_FEAT_##_FEAT) - * - _NAME: Feature name exposed to the user. - * - _TYPE: Feature type (S390_FEAT_TYPE_##_TYPE). - * - _BIT: Feature bit number within feature type block (unused for MISC). - * - _DESC: Feature description, exposed to the user. - * - * Copyright IBM Corp. 2016, 2018 - * Copyright Red Hat, Inc. 2019 - * - * Author(s): Michael Mueller - * David Hildenbrand - * - * This work is licensed under the terms of the GNU GPL, version 2 or (at - * your option) any later version. See the COPYING file in the top-level - * directory. - */ - -/* Features exposed via the STFL(E) instruction. */ -DEF_FEAT(ESAN3, "esan3", STFL, 0, "Instructions marked as n3") -DEF_FEAT(ZARCH, "zarch", STFL, 1, "z/Architecture architectural mode") -DEF_FEAT(DAT_ENH, "dateh", STFL, 3, "DAT-enhancement facility") -DEF_FEAT(IDTE_SEGMENT, "idtes", STFL, 4, "IDTE selective TLB segment-table clearing") -DEF_FEAT(IDTE_REGION, "idter", STFL, 5, "IDTE selective TLB region-table clearing") -DEF_FEAT(ASN_LX_REUSE, "asnlxr", STFL, 6, "ASN-and-LX reuse facility") -DEF_FEAT(STFLE, "stfle", STFL, 7, "Store-facility-list-extended facility") -DEF_FEAT(EDAT, "edat", STFL, 8, "Enhanced-DAT facility") -DEF_FEAT(SENSE_RUNNING_STATUS, "srs", STFL, 9, "Sense-running-status facility") -DEF_FEAT(CONDITIONAL_SSKE, "csske", STFL, 10, "Conditional-SSKE facility") -DEF_FEAT(CONFIGURATION_TOPOLOGY, "ctop", STFL, 11, "Configuration-topology facility") -DEF_FEAT(AP_QUERY_CONFIG_INFO, "apqci", STFL, 12, "Query AP Configuration Information facility") -DEF_FEAT(IPTE_RANGE, "ipter", STFL, 13, "IPTE-range facility") -DEF_FEAT(NONQ_KEY_SETTING, "nonqks", STFL, 14, "Nonquiescing key-setting facility") -DEF_FEAT(AP_FACILITIES_TEST, "apft", STFL, 15, "AP Facilities Test facility") -DEF_FEAT(EXTENDED_TRANSLATION_2, "etf2", STFL, 16, "Extended-translation facility 2") -DEF_FEAT(MSA, "msa-base", STFL, 17, "Message-security-assist facility (excluding subfunctions)") -DEF_FEAT(LONG_DISPLACEMENT, "ldisp", STFL, 18, "Long-displacement facility") -DEF_FEAT(LONG_DISPLACEMENT_FAST, "ldisphp", STFL, 19, "Long-displacement facility has high performance") -DEF_FEAT(HFP_MADDSUB, "hfpm", STFL, 20, "HFP-multiply-add/subtract facility") -DEF_FEAT(EXTENDED_IMMEDIATE, "eimm", STFL, 21, "Extended-immediate facility") -DEF_FEAT(EXTENDED_TRANSLATION_3, "etf3", STFL, 22, "Extended-translation facility 3") -DEF_FEAT(HFP_UNNORMALIZED_EXT, "hfpue", STFL, 23, "HFP-unnormalized-extension facility") -DEF_FEAT(ETF2_ENH, "etf2eh", STFL, 24, "ETF2-enhancement facility") -DEF_FEAT(STORE_CLOCK_FAST, "stckf", STFL, 25, "Store-clock-fast facility") -DEF_FEAT(PARSING_ENH, "parseh", STFL, 26, "Parsing-enhancement facility") -DEF_FEAT(MOVE_WITH_OPTIONAL_SPEC, "mvcos", STFL, 27, "Move-with-optional-specification facility") -DEF_FEAT(TOD_CLOCK_STEERING, "tods-base", STFL, 28, "TOD-clock-steering facility (excluding subfunctions)") -DEF_FEAT(ETF3_ENH, "etf3eh", STFL, 30, "ETF3-enhancement facility") -DEF_FEAT(EXTRACT_CPU_TIME, "ectg", STFL, 31, "Extract-CPU-time facility") -DEF_FEAT(COMPARE_AND_SWAP_AND_STORE, "csst", STFL, 32, "Compare-and-swap-and-store facility") -DEF_FEAT(COMPARE_AND_SWAP_AND_STORE_2, "csst2", STFL, 33, "Compare-and-swap-and-store facility 2") -DEF_FEAT(GENERAL_INSTRUCTIONS_EXT, "ginste", STFL, 34, "General-instructions-extension facility") -DEF_FEAT(EXECUTE_EXT, "exrl", STFL, 35, "Execute-extensions facility") -DEF_FEAT(ENHANCED_MONITOR, "emon", STFL, 36, "Enhanced-monitor facility") -DEF_FEAT(FLOATING_POINT_EXT, "fpe", STFL, 37, "Floating-point extension facility") -DEF_FEAT(ORDER_PRESERVING_COMPRESSION, "opc", STFL, 38, "Order Preserving Compression facility") -DEF_FEAT(SET_PROGRAM_PARAMETERS, "sprogp", STFL, 40, "Set-program-parameters facility") -DEF_FEAT(FLOATING_POINT_SUPPPORT_ENH, "fpseh", STFL, 41, "Floating-point-support-enhancement facilities") -DEF_FEAT(DFP, "dfp", STFL, 42, "DFP (decimal-floating-point) facility") -DEF_FEAT(DFP_FAST, "dfphp", STFL, 43, "DFP (decimal-floating-point) facility has high performance") -DEF_FEAT(PFPO, "pfpo", STFL, 44, "PFPO instruction") -DEF_FEAT(STFLE_45, "stfle45", STFL, 45, "Various facilities introduced with z196") -DEF_FEAT(CMPSC_ENH, "cmpsceh", STFL, 47, "CMPSC-enhancement facility") -DEF_FEAT(DFP_ZONED_CONVERSION, "dfpzc", STFL, 48, "Decimal-floating-point zoned-conversion facility") -DEF_FEAT(STFLE_49, "stfle49", STFL, 49, "Various facilities introduced with zEC12") -DEF_FEAT(CONSTRAINT_TRANSACTIONAL_EXE, "cte", STFL, 50, "Constrained transactional-execution facility") -DEF_FEAT(LOCAL_TLB_CLEARING, "ltlbc", STFL, 51, "Local-TLB-clearing facility") -DEF_FEAT(INTERLOCKED_ACCESS_2, "iacc2", STFL, 52, "Interlocked-access facility 2") -DEF_FEAT(STFLE_53, "stfle53", STFL, 53, "Various facilities introduced with z13") -DEF_FEAT(ENTROPY_ENC_COMP, "eec", STFL, 54, "Entropy encoding compression facility") -DEF_FEAT(MSA_EXT_5, "msa5-base", STFL, 57, "Message-security-assist-extension-5 facility (excluding subfunctions)") -DEF_FEAT(MISC_INSTRUCTION_EXT, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility 2") -DEF_FEAT(SEMAPHORE_ASSIST, "sema", STFL, 59, "Semaphore-assist facility") -DEF_FEAT(TIME_SLICE_INSTRUMENTATION, "tsi", STFL, 60, "Time-slice Instrumentation facility") -DEF_FEAT(MISC_INSTRUCTION_EXT3, "minste3", STFL, 61, "Miscellaneous-Instruction-Extensions Facility 3") -DEF_FEAT(RUNTIME_INSTRUMENTATION, "ri", STFL, 64, "CPU runtime-instrumentation facility") -DEF_FEAT(AP_QUEUE_INTERRUPT_CONTROL, "apqi", STFL, 65, "AP-Queue interruption facility") -DEF_FEAT(ZPCI, "zpci", STFL, 69, "z/PCI facility") -DEF_FEAT(ADAPTER_EVENT_NOTIFICATION, "aen", STFL, 71, "General-purpose-adapter-event-notification facility") -DEF_FEAT(ADAPTER_INT_SUPPRESSION, "ais", STFL, 72, "General-purpose-adapter-interruption-suppression facility") -DEF_FEAT(TRANSACTIONAL_EXE, "te", STFL, 73, "Transactional-execution facility") -DEF_FEAT(STORE_HYPERVISOR_INFO, "sthyi", STFL, 74, "Store-hypervisor-information facility") -DEF_FEAT(ACCESS_EXCEPTION_FS_INDICATION, "aefsi", STFL, 75, "Access-exception-fetch/store-indication facility") -DEF_FEAT(MSA_EXT_3, "msa3-base", STFL, 76, "Message-security-assist-extension-3 facility (excluding subfunctions)") -DEF_FEAT(MSA_EXT_4, "msa4-base", STFL, 77, "Message-security-assist-extension-4 facility (excluding subfunctions)") -DEF_FEAT(EDAT_2, "edat2", STFL, 78, "Enhanced-DAT facility 2") -DEF_FEAT(DFP_PACKED_CONVERSION, "dfppc", STFL, 80, "Decimal-floating-point packed-conversion facility") -DEF_FEAT(PPA15, "ppa15", STFL, 81, "PPA15 is installed") -DEF_FEAT(BPB, "bpb", STFL, 82, "Branch prediction blocking") -DEF_FEAT(VECTOR, "vx", STFL, 129, "Vector facility") -DEF_FEAT(INSTRUCTION_EXEC_PROT, "iep", STFL, 130, "Instruction-execution-protection facility") -DEF_FEAT(SIDE_EFFECT_ACCESS_ESOP2, "sea_esop2", STFL, 131, "Side-effect-access facility and Enhanced-suppression-on-protection facility 2") -DEF_FEAT(GUARDED_STORAGE, "gs", STFL, 133, "Guarded-storage facility") -DEF_FEAT(VECTOR_PACKED_DECIMAL, "vxpd", STFL, 134, "Vector packed decimal facility") -DEF_FEAT(VECTOR_ENH, "vxeh", STFL, 135, "Vector enhancements facility") -DEF_FEAT(MULTIPLE_EPOCH, "mepoch", STFL, 139, "Multiple-epoch facility") -DEF_FEAT(TEST_PENDING_EXT_INTERRUPTION, "tpei", STFL, 144, "Test-pending-external-interruption facility") -DEF_FEAT(INSERT_REFERENCE_BITS_MULT, "irbm", STFL, 145, "Insert-reference-bits-multiple facility") -DEF_FEAT(MSA_EXT_8, "msa8-base", STFL, 146, "Message-security-assist-extension-8 facility (excluding subfunctions)") -DEF_FEAT(CMM_NT, "cmmnt", STFL, 147, "CMM: ESSA-enhancement (no translate) facility") -DEF_FEAT(VECTOR_ENH2, "vxeh2", STFL, 148, "Vector Enhancements facility 2") -DEF_FEAT(ESORT_BASE, "esort-base", STFL, 150, "Enhanced-sort facility (excluding subfunctions)") -DEF_FEAT(DEFLATE_BASE, "deflate-base", STFL, 151, "Deflate-conversion facility (excluding subfunctions)") -DEF_FEAT(VECTOR_PACKED_DECIMAL_ENH, "vxpdeh", STFL, 152, "Vector-Packed-Decimal-Enhancement Facility") -DEF_FEAT(MSA_EXT_9, "msa9-base", STFL, 155, "Message-security-assist-extension-9 facility (excluding subfunctions)") -DEF_FEAT(ETOKEN, "etoken", STFL, 156, "Etoken facility") -DEF_FEAT(UNPACK, "unpack", STFL, 161, "Unpack facility") - -/* Features exposed via SCLP SCCB Byte 80 - 98 (bit numbers relative to byte-80) */ -DEF_FEAT(SIE_GSLS, "gsls", SCLP_CONF_CHAR, 40, "SIE: Guest-storage-limit-suppression facility") -DEF_FEAT(ESOP, "esop", SCLP_CONF_CHAR, 46, "Enhanced-suppression-on-protection facility") -DEF_FEAT(HPMA2, "hpma2", SCLP_CONF_CHAR, 90, "Host page management assist 2 Facility") /* 91-2 */ -DEF_FEAT(SIE_KSS, "kss", SCLP_CONF_CHAR, 151, "SIE: Keyless-subset facility") /* 98-7 */ - -/* Features exposed via SCLP SCCB Byte 116 - 119 (bit numbers relative to byte-116) */ -DEF_FEAT(SIE_64BSCAO, "64bscao", SCLP_CONF_CHAR_EXT, 0, "SIE: 64-bit-SCAO facility") -DEF_FEAT(SIE_CMMA, "cmma", SCLP_CONF_CHAR_EXT, 1, "SIE: Collaborative-memory-management assist") -DEF_FEAT(SIE_PFMFI, "pfmfi", SCLP_CONF_CHAR_EXT, 9, "SIE: PFMF interpretation facility") -DEF_FEAT(SIE_IBS, "ibs", SCLP_CONF_CHAR_EXT, 10, "SIE: Interlock-and-broadcast-suppression facility") - -/* Features exposed via SCLP CPU info. */ -DEF_FEAT(SIE_F2, "sief2", SCLP_CPU, 4, "SIE: interception format 2 (Virtual SIE)") -DEF_FEAT(SIE_SKEY, "skey", SCLP_CPU, 5, "SIE: Storage-key facility") -DEF_FEAT(SIE_GPERE, "gpereh", SCLP_CPU, 10, "SIE: Guest-PER enhancement facility") -DEF_FEAT(SIE_SIIF, "siif", SCLP_CPU, 11, "SIE: Shared IPTE-interlock facility") -DEF_FEAT(SIE_SIGPIF, "sigpif", SCLP_CPU, 12, "SIE: SIGP interpretation facility") -DEF_FEAT(SIE_IB, "ib", SCLP_CPU, 42, "SIE: Intervention bypass facility") -DEF_FEAT(SIE_CEI, "cei", SCLP_CPU, 43, "SIE: Conditional-external-interception facility") - -/* - * Features exposed via no feature bit (but e.g., instruction sensing) - * -> the feature bit number is irrelavant - */ -DEF_FEAT(DAT_ENH_2, "dateh2", MISC, 0, "DAT-enhancement facility 2") -DEF_FEAT(CMM, "cmm", MISC, 0, "Collaborative-memory-management facility") -DEF_FEAT(AP, "ap", MISC, 0, "AP instructions installed") - -/* Features exposed via the PLO instruction. */ -DEF_FEAT(PLO_CL, "plo-cl", PLO, 0, "PLO Compare and load (32 bit in general registers)") -DEF_FEAT(PLO_CLG, "plo-clg", PLO, 1, "PLO Compare and load (64 bit in parameter list)") -DEF_FEAT(PLO_CLGR, "plo-clgr", PLO, 2, "PLO Compare and load (32 bit in general registers)") -DEF_FEAT(PLO_CLX, "plo-clx", PLO, 3, "PLO Compare and load (128 bit in parameter list)") -DEF_FEAT(PLO_CS, "plo-cs", PLO, 4, "PLO Compare and swap (32 bit in general registers)") -DEF_FEAT(PLO_CSG, "plo-csg", PLO, 5, "PLO Compare and swap (64 bit in parameter list)") -DEF_FEAT(PLO_CSGR, "plo-csgr", PLO, 6, "PLO Compare and swap (32 bit in general registers)") -DEF_FEAT(PLO_CSX, "plo-csx", PLO, 7, "PLO Compare and swap (128 bit in parameter list)") -DEF_FEAT(PLO_DCS, "plo-dcs", PLO, 8, "PLO Double compare and swap (32 bit in general registers)") -DEF_FEAT(PLO_DCSG, "plo-dcsg", PLO, 9, "PLO Double compare and swap (64 bit in parameter list)") -DEF_FEAT(PLO_DCSGR, "plo-dcsgr", PLO, 10, "PLO Double compare and swap (32 bit in general registers)") -DEF_FEAT(PLO_DCSX, "plo-dcsx", PLO, 11, "PLO Double compare and swap (128 bit in parameter list)") -DEF_FEAT(PLO_CSST, "plo-csst", PLO, 12, "PLO Compare and swap and store (32 bit in general registers)") -DEF_FEAT(PLO_CSSTG, "plo-csstg", PLO, 13, "PLO Compare and swap and store (64 bit in parameter list)") -DEF_FEAT(PLO_CSSTGR, "plo-csstgr", PLO, 14, "PLO Compare and swap and store (32 bit in general registers)") -DEF_FEAT(PLO_CSSTX, "plo-csstx", PLO, 15, "PLO Compare and swap and store (128 bit in parameter list)") -DEF_FEAT(PLO_CSDST, "plo-csdst", PLO, 16, "PLO Compare and swap and double store (32 bit in general registers)") -DEF_FEAT(PLO_CSDSTG, "plo-csdstg", PLO, 17, "PLO Compare and swap and double store (64 bit in parameter list)") -DEF_FEAT(PLO_CSDSTGR, "plo-csdstgr", PLO, 18, "PLO Compare and swap and double store (32 bit in general registers)") -DEF_FEAT(PLO_CSDSTX, "plo-csdstx", PLO, 19, "PLO Compare and swap and double store (128 bit in parameter list)") -DEF_FEAT(PLO_CSTST, "plo-cstst", PLO, 20, "PLO Compare and swap and triple store (32 bit in general registers)") -DEF_FEAT(PLO_CSTSTG, "plo-cststg", PLO, 21, "PLO Compare and swap and triple store (64 bit in parameter list)") -DEF_FEAT(PLO_CSTSTGR, "plo-cststgr", PLO, 22, "PLO Compare and swap and triple store (32 bit in general registers)") -DEF_FEAT(PLO_CSTSTX, "plo-cststx", PLO, 23, "PLO Compare and swap and triple store (128 bit in parameter list)") - -/* Features exposed via the PTFF instruction. */ -DEF_FEAT(PTFF_QTO, "ptff-qto", PTFF, 1, "PTFF Query TOD Offset") -DEF_FEAT(PTFF_QSI, "ptff-qsi", PTFF, 2, "PTFF Query Steering Information") -DEF_FEAT(PTFF_QPT, "ptff-qpc", PTFF, 3, "PTFF Query Physical Clock") -DEF_FEAT(PTFF_QUI, "ptff-qui", PTFF, 4, "PTFF Query UTC Information") -DEF_FEAT(PTFF_QTOU, "ptff-qtou", PTFF, 5, "PTFF Query TOD Offset User") -DEF_FEAT(PTFF_QSIE, "ptff-qsie", PTFF, 10, "PTFF Query Steering Information Extended") -DEF_FEAT(PTFF_QTOUE, "ptff-qtoue", PTFF, 13, "PTFF Query TOD Offset User Extended") -DEF_FEAT(PTFF_STO, "ptff-sto", PTFF, 65, "PTFF Set TOD Offset") -DEF_FEAT(PTFF_STOU, "ptff-stou", PTFF, 69, "PTFF Set TOD Offset User") -DEF_FEAT(PTFF_STOE, "ptff-stoe", PTFF, 73, "PTFF Set TOD Offset Extended") -DEF_FEAT(PTFF_STOUE, "ptff-stoue", PTFF, 77, "PTFF Set TOD Offset User Extended") - -/* Features exposed via the KMAC instruction. */ -DEF_FEAT(KMAC_DEA, "kmac-dea", KMAC, 1, "KMAC DEA") -DEF_FEAT(KMAC_TDEA_128, "kmac-tdea-128", KMAC, 2, "KMAC TDEA-128") -DEF_FEAT(KMAC_TDEA_192, "kmac-tdea-192", KMAC, 3, "KMAC TDEA-192") -DEF_FEAT(KMAC_EDEA, "kmac-edea", KMAC, 9, "KMAC Encrypted-DEA") -DEF_FEAT(KMAC_ETDEA_128, "kmac-etdea-128", KMAC, 10, "KMAC Encrypted-TDEA-128") -DEF_FEAT(KMAC_ETDEA_192, "kmac-etdea-192", KMAC, 11, "KMAC Encrypted-TDEA-192") -DEF_FEAT(KMAC_AES_128, "kmac-aes-128", KMAC, 18, "KMAC AES-128") -DEF_FEAT(KMAC_AES_192, "kmac-aes-192", KMAC, 19, "KMAC AES-192") -DEF_FEAT(KMAC_AES_256, "kmac-aes-256", KMAC, 20, "KMAC AES-256") -DEF_FEAT(KMAC_EAES_128, "kmac-eaes-128", KMAC, 26, "KMAC Encrypted-AES-128") -DEF_FEAT(KMAC_EAES_192, "kmac-eaes-192", KMAC, 27, "KMAC Encrypted-AES-192") -DEF_FEAT(KMAC_EAES_256, "kmac-eaes-256", KMAC, 28, "KMAC Encrypted-AES-256") - -/* Features exposed via the KMC instruction. */ -DEF_FEAT(KMC_DEA, "kmc-dea", KMC, 1, "KMC DEA") -DEF_FEAT(KMC_TDEA_128, "kmc-tdea-128", KMC, 2, "KMC TDEA-128") -DEF_FEAT(KMC_TDEA_192, "kmc-tdea-192", KMC, 3, "KMC TDEA-192") -DEF_FEAT(KMC_EDEA, "kmc-edea", KMC, 9, "KMC Encrypted-DEA") -DEF_FEAT(KMC_ETDEA_128, "kmc-etdea-128", KMC, 10, "KMC Encrypted-TDEA-128") -DEF_FEAT(KMC_ETDEA_192, "kmc-etdea-192", KMC, 11, "KMC Encrypted-TDEA-192") -DEF_FEAT(KMC_AES_128, "kmc-aes-128", KMC, 18, "KMC AES-128") -DEF_FEAT(KMC_AES_192, "kmc-aes-192", KMC, 19, "KMC AES-192") -DEF_FEAT(KMC_AES_256, "kmc-aes-256", KMC, 20, "KMC AES-256") -DEF_FEAT(KMC_EAES_128, "kmc-eaes-128", KMC, 26, "KMC Encrypted-AES-128") -DEF_FEAT(KMC_EAES_192, "kmc-eaes-192", KMC, 27, "KMC Encrypted-AES-192") -DEF_FEAT(KMC_EAES_256, "kmc-eaes-256", KMC, 28, "KMC Encrypted-AES-256") -DEF_FEAT(KMC_PRNG, "kmc-prng", KMC, 67, "KMC PRNG") - -/* Features exposed via the KM instruction. */ -DEF_FEAT(KM_DEA, "km-dea", KM, 1, "KM DEA") -DEF_FEAT(KM_TDEA_128, "km-tdea-128", KM, 2, "KM TDEA-128") -DEF_FEAT(KM_TDEA_192, "km-tdea-192", KM, 3, "KM TDEA-192") -DEF_FEAT(KM_EDEA, "km-edea", KM, 9, "KM Encrypted-DEA") -DEF_FEAT(KM_ETDEA_128, "km-etdea-128", KM, 10, "KM Encrypted-TDEA-128") -DEF_FEAT(KM_ETDEA_192, "km-etdea-192", KM, 11, "KM Encrypted-TDEA-192") -DEF_FEAT(KM_AES_128, "km-aes-128", KM, 18, "KM AES-128") -DEF_FEAT(KM_AES_192, "km-aes-192", KM, 19, "KM AES-192") -DEF_FEAT(KM_AES_256, "km-aes-256", KM, 20, "KM AES-256") -DEF_FEAT(KM_EAES_128, "km-eaes-128", KM, 26, "KM Encrypted-AES-128") -DEF_FEAT(KM_EAES_192, "km-eaes-192", KM, 27, "KM Encrypted-AES-192") -DEF_FEAT(KM_EAES_256, "km-eaes-256", KM, 28, "KM Encrypted-AES-256") -DEF_FEAT(KM_XTS_AES_128, "km-xts-aes-128", KM, 50, "KM XTS-AES-128") -DEF_FEAT(KM_XTS_AES_256, "km-xts-aes-256", KM, 52, "KM XTS-AES-256") -DEF_FEAT(KM_XTS_EAES_128, "km-xts-eaes-128", KM, 58, "KM XTS-Encrypted-AES-128") -DEF_FEAT(KM_XTS_EAES_256, "km-xts-eaes-256", KM, 60, "KM XTS-Encrypted-AES-256") - -/* Features exposed via the KIMD instruction. */ -DEF_FEAT(KIMD_SHA_1, "kimd-sha-1", KIMD, 1, "KIMD SHA-1") -DEF_FEAT(KIMD_SHA_256, "kimd-sha-256", KIMD, 2, "KIMD SHA-256") -DEF_FEAT(KIMD_SHA_512, "kimd-sha-512", KIMD, 3, "KIMD SHA-512") -DEF_FEAT(KIMD_SHA3_224, "kimd-sha3-224", KIMD, 32, "KIMD SHA3-224") -DEF_FEAT(KIMD_SHA3_256, "kimd-sha3-256", KIMD, 33, "KIMD SHA3-256") -DEF_FEAT(KIMD_SHA3_384, "kimd-sha3-384", KIMD, 34, "KIMD SHA3-384") -DEF_FEAT(KIMD_SHA3_512, "kimd-sha3-512", KIMD, 35, "KIMD SHA3-512") -DEF_FEAT(KIMD_SHAKE_128, "kimd-shake-128", KIMD, 36, "KIMD SHAKE-128") -DEF_FEAT(KIMD_SHAKE_256, "kimd-shake-256", KIMD, 37, "KIMD SHAKE-256") -DEF_FEAT(KIMD_GHASH, "kimd-ghash", KIMD, 65, "KIMD GHASH") - -/* Features exposed via the KLMD instruction. */ -DEF_FEAT(KLMD_SHA_1, "klmd-sha-1", KLMD, 1, "KLMD SHA-1") -DEF_FEAT(KLMD_SHA_256, "klmd-sha-256", KLMD, 2, "KLMD SHA-256") -DEF_FEAT(KLMD_SHA_512, "klmd-sha-512", KLMD, 3, "KLMD SHA-512") -DEF_FEAT(KLMD_SHA3_224, "klmd-sha3-224", KLMD, 32, "KLMD SHA3-224") -DEF_FEAT(KLMD_SHA3_256, "klmd-sha3-256", KLMD, 33, "KLMD SHA3-256") -DEF_FEAT(KLMD_SHA3_384, "klmd-sha3-384", KLMD, 34, "KLMD SHA3-384") -DEF_FEAT(KLMD_SHA3_512, "klmd-sha3-512", KLMD, 35, "KLMD SHA3-512") -DEF_FEAT(KLMD_SHAKE_128, "klmd-shake-128", KLMD, 36, "KLMD SHAKE-128") -DEF_FEAT(KLMD_SHAKE_256, "klmd-shake-256", KLMD, 37, "KLMD SHAKE-256") - -/* Features exposed via the PCKMO instruction. */ -DEF_FEAT(PCKMO_EDEA, "pckmo-edea", PCKMO, 1, "PCKMO Encrypted-DEA-Key") -DEF_FEAT(PCKMO_ETDEA_128, "pckmo-etdea-128", PCKMO, 2, "PCKMO Encrypted-TDEA-128-Key") -DEF_FEAT(PCKMO_ETDEA_256, "pckmo-etdea-192", PCKMO, 3, "PCKMO Encrypted-TDEA-192-Key") -DEF_FEAT(PCKMO_AES_128, "pckmo-aes-128", PCKMO, 18, "PCKMO Encrypted-AES-128-Key") -DEF_FEAT(PCKMO_AES_192, "pckmo-aes-192", PCKMO, 19, "PCKMO Encrypted-AES-192-Key") -DEF_FEAT(PCKMO_AES_256, "pckmo-aes-256", PCKMO, 20, "PCKMO Encrypted-AES-256-Key") -DEF_FEAT(PCKMO_ECC_P256, "pckmo-ecc-p256", PCKMO, 32, "PCKMO Encrypt-ECC-P256-Key") -DEF_FEAT(PCKMO_ECC_P384, "pckmo-ecc-p384", PCKMO, 33, "PCKMO Encrypt-ECC-P384-Key") -DEF_FEAT(PCKMO_ECC_P521, "pckmo-ecc-p521", PCKMO, 34, "PCKMO Encrypt-ECC-P521-Key") -DEF_FEAT(PCKMO_ECC_ED25519, "pckmo-ecc-ed25519", PCKMO, 40 , "PCKMO Encrypt-ECC-Ed25519-Key") -DEF_FEAT(PCKMO_ECC_ED448, "pckmo-ecc-ed448", PCKMO, 41 , "PCKMO Encrypt-ECC-Ed448-Key") - -/* Features exposed via the KMCTR instruction. */ -DEF_FEAT(KMCTR_DEA, "kmctr-dea", KMCTR, 1, "KMCTR DEA") -DEF_FEAT(KMCTR_TDEA_128, "kmctr-tdea-128", KMCTR, 2, "KMCTR TDEA-128") -DEF_FEAT(KMCTR_TDEA_192, "kmctr-tdea-192", KMCTR, 3, "KMCTR TDEA-192") -DEF_FEAT(KMCTR_EDEA, "kmctr-edea", KMCTR, 9, "KMCTR Encrypted-DEA") -DEF_FEAT(KMCTR_ETDEA_128, "kmctr-etdea-128", KMCTR, 10, "KMCTR Encrypted-TDEA-128") -DEF_FEAT(KMCTR_ETDEA_192, "kmctr-etdea-192", KMCTR, 11, "KMCTR Encrypted-TDEA-192") -DEF_FEAT(KMCTR_AES_128, "kmctr-aes-128", KMCTR, 18, "KMCTR AES-128") -DEF_FEAT(KMCTR_AES_192, "kmctr-aes-192", KMCTR, 19, "KMCTR AES-192") -DEF_FEAT(KMCTR_AES_256, "kmctr-aes-256", KMCTR, 20, "KMCTR AES-256") -DEF_FEAT(KMCTR_EAES_128, "kmctr-eaes-128", KMCTR, 26, "KMCTR Encrypted-AES-128") -DEF_FEAT(KMCTR_EAES_192, "kmctr-eaes-192", KMCTR, 27, "KMCTR Encrypted-AES-192") -DEF_FEAT(KMCTR_EAES_256, "kmctr-eaes-256", KMCTR, 28, "KMCTR Encrypted-AES-256") - -/* Features exposed via the KMF instruction. */ -DEF_FEAT(KMF_DEA, "kmf-dea", KMF, 1, "KMF DEA") -DEF_FEAT(KMF_TDEA_128, "kmf-tdea-128", KMF, 2, "KMF TDEA-128") -DEF_FEAT(KMF_TDEA_192, "kmf-tdea-192", KMF, 3, "KMF TDEA-192") -DEF_FEAT(KMF_EDEA, "kmf-edea", KMF, 9, "KMF Encrypted-DEA") -DEF_FEAT(KMF_ETDEA_128, "kmf-etdea-128", KMF, 10, "KMF Encrypted-TDEA-128") -DEF_FEAT(KMF_ETDEA_192, "kmf-etdea-192", KMF, 11, "KMF Encrypted-TDEA-192") -DEF_FEAT(KMF_AES_128, "kmf-aes-128", KMF, 18, "KMF AES-128") -DEF_FEAT(KMF_AES_192, "kmf-aes-192", KMF, 19, "KMF AES-192") -DEF_FEAT(KMF_AES_256, "kmf-aes-256", KMF, 20, "KMF AES-256") -DEF_FEAT(KMF_EAES_128, "kmf-eaes-128", KMF, 26, "KMF Encrypted-AES-128") -DEF_FEAT(KMF_EAES_192, "kmf-eaes-192", KMF, 27, "KMF Encrypted-AES-192") -DEF_FEAT(KMF_EAES_256, "kmf-eaes-256", KMF, 28, "KMF Encrypted-AES-256") - -/* Features exposed via the KMO instruction. */ -DEF_FEAT(KMO_DEA, "kmo-dea", KMO, 1, "KMO DEA") -DEF_FEAT(KMO_TDEA_128, "kmo-tdea-128", KMO, 2, "KMO TDEA-128") -DEF_FEAT(KMO_TDEA_192, "kmo-tdea-192", KMO, 3, "KMO TDEA-192") -DEF_FEAT(KMO_EDEA, "kmo-edea", KMO, 9, "KMO Encrypted-DEA") -DEF_FEAT(KMO_ETDEA_128, "kmo-etdea-128", KMO, 10, "KMO Encrypted-TDEA-128") -DEF_FEAT(KMO_ETDEA_192, "kmo-etdea-192", KMO, 11, "KMO Encrypted-TDEA-192") -DEF_FEAT(KMO_AES_128, "kmo-aes-128", KMO, 18, "KMO AES-128") -DEF_FEAT(KMO_AES_192, "kmo-aes-192", KMO, 19, "KMO AES-192") -DEF_FEAT(KMO_AES_256, "kmo-aes-256", KMO, 20, "KMO AES-256") -DEF_FEAT(KMO_EAES_128, "kmo-eaes-128", KMO, 26, "KMO Encrypted-AES-128") -DEF_FEAT(KMO_EAES_192, "kmo-eaes-192", KMO, 27, "KMO Encrypted-AES-192") -DEF_FEAT(KMO_EAES_256, "kmo-eaes-256", KMO, 28, "KMO Encrypted-AES-256") - -/* Features exposed via the PCC instruction. */ -DEF_FEAT(PCC_CMAC_DEA, "pcc-cmac-dea", PCC, 1, "PCC Compute-Last-Block-CMAC-Using-DEA") -DEF_FEAT(PCC_CMAC_TDEA_128, "pcc-cmac-tdea-128", PCC, 2, "PCC Compute-Last-Block-CMAC-Using-TDEA-128") -DEF_FEAT(PCC_CMAC_TDEA_192, "pcc-cmac-tdea-192", PCC, 3, "PCC Compute-Last-Block-CMAC-Using-TDEA-192") -DEF_FEAT(PCC_CMAC_ETDEA_128, "pcc-cmac-edea", PCC, 9, "PCC Compute-Last-Block-CMAC-Using-Encrypted-DEA") -DEF_FEAT(PCC_CMAC_ETDEA_192, "pcc-cmac-etdea-128", PCC, 10, "PCC Compute-Last-Block-CMAC-Using-Encrypted-TDEA-128") -DEF_FEAT(PCC_CMAC_TDEA, "pcc-cmac-etdea-192", PCC, 11, "PCC Compute-Last-Block-CMAC-Using-EncryptedTDEA-192") -DEF_FEAT(PCC_CMAC_AES_128, "pcc-cmac-aes-128", PCC, 18, "PCC Compute-Last-Block-CMAC-Using-AES-128") -DEF_FEAT(PCC_CMAC_AES_192, "pcc-cmac-aes-192", PCC, 19, "PCC Compute-Last-Block-CMAC-Using-AES-192") -DEF_FEAT(PCC_CMAC_AES_256, "pcc-cmac-aes-256", PCC, 20, "PCC Compute-Last-Block-CMAC-Using-AES-256") -DEF_FEAT(PCC_CMAC_EAES_128, "pcc-cmac-eaes-128", PCC, 26, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-128") -DEF_FEAT(PCC_CMAC_EAES_192, "pcc-cmac-eaes-192", PCC, 27, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-192") -DEF_FEAT(PCC_CMAC_EAES_256, "pcc-cmac-eaes-256", PCC, 28, "PCC Compute-Last-Block-CMAC-Using-Encrypted-AES-256") -DEF_FEAT(PCC_XTS_AES_128, "pcc-xts-aes-128", PCC, 50, "PCC Compute-XTS-Parameter-Using-AES-128") -DEF_FEAT(PCC_XTS_AES_256, "pcc-xts-aes-256", PCC, 52, "PCC Compute-XTS-Parameter-Using-AES-256") -DEF_FEAT(PCC_XTS_EAES_128, "pcc-xts-eaes-128", PCC, 58, "PCC Compute-XTS-Parameter-Using-Encrypted-AES-128") -DEF_FEAT(PCC_XTS_EAES_256, "pcc-xts-eaes-256", PCC, 60, "PCC Compute-XTS-Parameter-Using-Encrypted-AES-256") -DEF_FEAT(PCC_SCALAR_MULT_P256, "pcc-scalar-mult-p256", PCC, 64, "PCC Scalar-Multiply-P256") -DEF_FEAT(PCC_SCALAR_MULT_P384, "pcc-scalar-mult-p384", PCC, 65, "PCC Scalar-Multiply-P384") -DEF_FEAT(PCC_SCALAR_MULT_P512, "pcc-scalar-mult-p521", PCC, 66, "PCC Scalar-Multiply-P521") -DEF_FEAT(PCC_SCALAR_MULT_ED25519, "pcc-scalar-mult-ed25519", PCC, 72, "PCC Scalar-Multiply-Ed25519") -DEF_FEAT(PCC_SCALAR_MULT_ED448, "pcc-scalar-mult-ed448", PCC, 73, "PCC Scalar-Multiply-Ed448") -DEF_FEAT(PCC_SCALAR_MULT_X25519, "pcc-scalar-mult-x25519", PCC, 80, "PCC Scalar-Multiply-X25519") -DEF_FEAT(PCC_SCALAR_MULT_X448, "pcc-scalar-mult-x448", PCC, 81, "PCC Scalar-Multiply-X448") - -/* Features exposed via the PPNO/PRNO instruction. */ -DEF_FEAT(PPNO_SHA_512_DRNG, "ppno-sha-512-drng", PPNO, 3, "PPNO SHA-512-DRNG") -DEF_FEAT(PRNO_TRNG_QRTCR, "prno-trng-qrtcr", PPNO, 112, "PRNO TRNG-Query-Raw-to-Conditioned-Ratio") -DEF_FEAT(PRNO_TRNG, "prno-trng", PPNO, 114, "PRNO TRNG") - -/* Features exposed via the KMA instruction. */ -DEF_FEAT(KMA_GCM_AES_128, "kma-gcm-aes-128", KMA, 18, "KMA GCM-AES-128") -DEF_FEAT(KMA_GCM_AES_192, "kma-gcm-aes-192", KMA, 19, "KMA GCM-AES-192") -DEF_FEAT(KMA_GCM_AES_256, "kma-gcm-aes-256", KMA, 20, "KMA GCM-AES-256") -DEF_FEAT(KMA_GCM_EAES_128, "kma-gcm-eaes-128", KMA, 26, "KMA GCM-Encrypted-AES-128") -DEF_FEAT(KMA_GCM_EAES_192, "kma-gcm-eaes-192", KMA, 27, "KMA GCM-Encrypted-AES-192") -DEF_FEAT(KMA_GCM_EAES_256, "kma-gcm-eaes-256", KMA, 28, "KMA GCM-Encrypted-AES-256") - -/* Features exposed via the KDSA instruction. */ -DEF_FEAT(KDSA_ECDSA_VERIFY_P256, "kdsa-ecdsa-verify-p256", KDSA, 1, "KDSA ECDSA-Verify-P256") -DEF_FEAT(KDSA_ECDSA_VERIFY_P384, "kdsa-ecdsa-verify-p384", KDSA, 2, "KDSA ECDSA-Verify-P384") -DEF_FEAT(KDSA_ECDSA_VERIFY_P512, "kdsa-ecdsa-verify-p521", KDSA, 3, "KDSA ECDSA-Verify-P521") -DEF_FEAT(KDSA_ECDSA_SIGN_P256, "kdsa-ecdsa-sign-p256", KDSA, 9, "KDSA ECDSA-Sign-P256") -DEF_FEAT(KDSA_ECDSA_SIGN_P384, "kdsa-ecdsa-sign-p384", KDSA, 10, "KDSA ECDSA-Sign-P384") -DEF_FEAT(KDSA_ECDSA_SIGN_P512, "kdsa-ecdsa-sign-p521", KDSA, 11, "KDSA ECDSA-Sign-P521") -DEF_FEAT(KDSA_EECDSA_SIGN_P256, "kdsa-eecdsa-sign-p256", KDSA, 17, "KDSA Encrypted-ECDSA-Sign-P256") -DEF_FEAT(KDSA_EECDSA_SIGN_P384, "kdsa-eecdsa-sign-p384", KDSA, 18, "KDSA Encrypted-ECDSA-Sign-P384") -DEF_FEAT(KDSA_EECDSA_SIGN_P512, "kdsa-eecdsa-sign-p521", KDSA, 19, "KDSA Encrypted-ECDSA-Sign-P521") -DEF_FEAT(KDSA_EDDSA_VERIFY_ED25519, "kdsa-eddsa-verify-ed25519", KDSA, 32, "KDSA EdDSA-Verify-Ed25519") -DEF_FEAT(KDSA_EDDSA_VERIFY_ED448, "kdsa-eddsa-verify-ed448", KDSA, 36, "KDSA EdDSA-Verify-Ed448") -DEF_FEAT(KDSA_EDDSA_SIGN_ED25519, "kdsa-eddsa-sign-ed25519", KDSA, 40, "KDSA EdDSA-Sign-Ed25519") -DEF_FEAT(KDSA_EDDSA_SIGN_ED448, "kdsa-eddsa-sign-ed448", KDSA, 44, "KDSA EdDSA-Sign-Ed448") -DEF_FEAT(KDSA_EEDDSA_SIGN_ED25519, "kdsa-eeddsa-sign-ed25519", KDSA, 48, "KDSA Encrypted-EdDSA-Sign-Ed25519") -DEF_FEAT(KDSA_EEDDSA_SIGN_ED448, "kdsa-eeddsa-sign-ed448", KDSA, 52, "KDSA Encrypted-EdDSA-Sign-Ed448") - -/* Features exposed via the SORTL instruction. */ -DEF_FEAT(SORTL_SFLR, "sortl-sflr", SORTL, 1, "SORTL SFLR") -DEF_FEAT(SORTL_SVLR, "sortl-svlr", SORTL, 2, "SORTL SVLR") -DEF_FEAT(SORTL_32, "sortl-32", SORTL, 130, "SORTL 32 input lists") -DEF_FEAT(SORTL_128, "sortl-128", SORTL, 132, "SORTL 128 input lists") -DEF_FEAT(SORTL_F0, "sortl-f0", SORTL, 192, "SORTL format 0 parameter-block") - -/* Features exposed via the DEFLATE instruction. */ -DEF_FEAT(DEFLATE_GHDT, "dfltcc-gdht", DFLTCC, 1, "DFLTCC GDHT") -DEF_FEAT(DEFLATE_CMPR, "dfltcc-cmpr", DFLTCC, 2, "DFLTCC CMPR") -DEF_FEAT(DEFLATE_XPND, "dfltcc-xpnd", DFLTCC, 4, "DFLTCC XPND") -DEF_FEAT(DEFLATE_F0, "dfltcc-f0", DFLTCC, 192, "DFLTCC format 0 parameter-block") -- cgit v1.2.3-55-g7522 From ac76f9d17cff2e5b9c002a387f711d03a404a2de Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 27 Aug 2019 21:57:39 +0400 Subject: build-sys hack: ensure target directory is there By removing some unnest-vars calls, we miss some directory creation that may be required by some/dir/object.d. This will go away once everything is converted to Meson. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- rules.mak | 1 + 1 file changed, 1 insertion(+) diff --git a/rules.mak b/rules.mak index 694865b63e..56ba540a32 100644 --- a/rules.mak +++ b/rules.mak @@ -66,6 +66,7 @@ expand-objs = $(strip $(sort $(filter %.o,$1)) \ $(filter-out %.o %.mo,$1)) %.o: %.c + @mkdir -p $(dir $@) $(call quiet-command,$(CC) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) \ -c -o $@ $<,"CC","$(TARGET_DIR)$@") -- cgit v1.2.3-55-g7522 From f5c730698a33ced107d6de26eb8c1b34486d8c2d Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Aug 2020 14:00:50 +0200 Subject: tests/vm: do not pollute configure with --efi-aarch64 Just make EFI_AARCH64 a variable in the makefile that defaults to the efi firmware included with QEMU. It can be redefined on the "make" command line. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- configure | 19 ------------------- tests/vm/Makefile.include | 2 ++ 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/configure b/configure index 2acc4d1465..1c17a0f27f 100755 --- a/configure +++ b/configure @@ -418,7 +418,6 @@ prefix="/usr/local" mandir="\${prefix}/share/man" datadir="\${prefix}/share" firmwarepath="\${prefix}/share/qemu-firmware" -efi_aarch64="" qemu_docdir="\${prefix}/share/doc/qemu" bindir="\${prefix}/bin" libdir="\${prefix}/lib" @@ -1109,8 +1108,6 @@ for opt do ;; --firmwarepath=*) firmwarepath="$optarg" ;; - --efi-aarch64=*) efi_aarch64="$optarg" - ;; --host=*|--build=*|\ --disable-dependency-tracking|\ --sbindir=*|--sharedstatedir=*|\ @@ -3650,20 +3647,6 @@ EOF fi fi -############################################ -# efi-aarch64 probe -# Check for efi files needed by aarch64 VMs. -# By default we will use the efi included with QEMU. -# Allow user to override the path for efi also. -if ! test -f "$efi_aarch64"; then - if test -f $source_path/pc-bios/edk2-aarch64-code.fd.bz2; then - # valid after build - efi_aarch64=$PWD/pc-bios/edk2-aarch64-code.fd - else - efi_aarch64="" - fi -fi - ########################################## # libcap-ng library probe if test "$cap_ng" != "no" ; then @@ -6861,7 +6844,6 @@ if test "$docs" != "no"; then echo "sphinx-build $sphinx_build" fi echo "genisoimage $genisoimage" -echo "efi_aarch64 $efi_aarch64" echo "python_yaml $python_yaml" echo "slirp support $slirp $(echo_version $slirp $slirp_version)" if test "$slirp" != "no" ; then @@ -7963,7 +7945,6 @@ echo "PYTHON=$python" >> $config_host_mak echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak echo "GENISOIMAGE=$genisoimage" >> $config_host_mak -echo "EFI_AARCH64=$efi_aarch64" >> $config_host_mak echo "PYTHON_YAML=$python_yaml" >> $config_host_mak echo "CC=$cc" >> $config_host_mak if $iasl -h > /dev/null 2>&1; then diff --git a/tests/vm/Makefile.include b/tests/vm/Makefile.include index f21948c46a..a599d1994d 100644 --- a/tests/vm/Makefile.include +++ b/tests/vm/Makefile.include @@ -2,6 +2,8 @@ .PHONY: vm-build-all vm-clean-all +EFI_AARCH64 = $(wildcard $(BUILD_DIR)/pc-bios/edk2-aarch64-code.fd) + IMAGES := freebsd netbsd openbsd centos fedora ifneq ($(GENISOIMAGE),) IMAGES += ubuntu.i386 centos -- cgit v1.2.3-55-g7522 From 00eb3db0aa2a9ff602d00e9870b52a2da36336df Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Aug 2020 14:05:50 +0200 Subject: tests/vm: check for Python YAML parser in the Makefile No need to do it in the configure file if it is only used for a help message. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- configure | 9 --------- tests/vm/Makefile.include | 6 +++++- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/configure b/configure index 1c17a0f27f..625c14c500 100755 --- a/configure +++ b/configure @@ -959,13 +959,6 @@ do fi done -# Check for existence of python3 yaml, needed to -# import yaml config files into vm-build. -python_yaml="no" -if $(python3 -c "import yaml" 2> /dev/null); then - python_yaml="yes" -fi - : ${smbd=${SMBD-/usr/sbin/smbd}} # Default objcc to clang if available, otherwise use CC @@ -6844,7 +6837,6 @@ if test "$docs" != "no"; then echo "sphinx-build $sphinx_build" fi echo "genisoimage $genisoimage" -echo "python_yaml $python_yaml" echo "slirp support $slirp $(echo_version $slirp $slirp_version)" if test "$slirp" != "no" ; then echo "smbd $smbd" @@ -7945,7 +7937,6 @@ echo "PYTHON=$python" >> $config_host_mak echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak echo "GENISOIMAGE=$genisoimage" >> $config_host_mak -echo "PYTHON_YAML=$python_yaml" >> $config_host_mak echo "CC=$cc" >> $config_host_mak if $iasl -h > /dev/null 2>&1; then echo "IASL=$iasl" >> $config_host_mak diff --git a/tests/vm/Makefile.include b/tests/vm/Makefile.include index a599d1994d..61f893ffdc 100644 --- a/tests/vm/Makefile.include +++ b/tests/vm/Makefile.include @@ -17,6 +17,10 @@ IMAGE_FILES := $(patsubst %, $(IMAGES_DIR)/%.img, $(IMAGES)) .PRECIOUS: $(IMAGE_FILES) +ifneq ($(PYTHON),) +HAVE_PYTHON_YAML = $(shell $(PYTHON) -c "import yaml" 2> /dev/null && echo yes) +endif + # 'vm-help' target was historically named 'vm-test' vm-help vm-test: @echo "vm-help: Test QEMU in preconfigured virtual machines" @@ -56,7 +60,7 @@ endif @echo " QEMU_LOCAL=1 - Use QEMU binary local to this build." @echo " QEMU=/path/to/qemu - Change path to QEMU binary" @echo " QEMU_IMG=/path/to/qemu-img - Change path to qemu-img tool" -ifeq ($(PYTHON_YAML),yes) +ifeq ($(HAVE_PYTHON_YAML),yes) @echo " QEMU_CONFIG=/path/conf.yml - Change path to VM configuration .yml file." else @echo " (install python3-yaml to enable support for yaml file to configure a VM.)" -- cgit v1.2.3-55-g7522 From b861f59593cf8f45cd2a7fd8f6122835566ad64d Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Aug 2020 16:24:29 +0200 Subject: tests/docker: add test script for static linux-user builds Signed-off-by: Paolo Bonzini --- tests/docker/test-static | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100755 tests/docker/test-static diff --git a/tests/docker/test-static b/tests/docker/test-static new file mode 100755 index 0000000000..372ef6fac7 --- /dev/null +++ b/tests/docker/test-static @@ -0,0 +1,24 @@ +#!/bin/bash -e +# +# Compile QEMU user mode emulators as static binaries on Linux. +# +# Copyright (c) 2020 Red Hat Inc. +# +# Authors: +# Paolo Bonzini +# +# This work is licensed under the terms of the GNU GPL, version 2 +# or (at your option) any later version. See the COPYING file in +# the top-level directory. + +. common.rc + +cd "$BUILD_DIR" + +build_qemu \ + --disable-system \ + --disable-tools \ + --disable-guest-agent \ + --disable-docs \ + --static +install_qemu -- cgit v1.2.3-55-g7522 From 1b00a4c476a32d1e2ffa16ce56141640358306be Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Aug 2020 15:23:28 +0200 Subject: nsis: use "make DESTDIR=" instead of "make prefix=" The next patch will prevent modifying the prefix on "make install". Adjust the creation of the installer. Signed-off-by: Paolo Bonzini --- Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 5596482dbd..ec12101a84 100644 --- a/Makefile +++ b/Makefile @@ -1188,16 +1188,16 @@ installer: $(INSTALLER) INSTDIR=/tmp/qemu-nsis -$(INSTALLER): install-doc $(SRC_PATH)/qemu.nsi - $(MAKE) install prefix=${INSTDIR} +$(INSTALLER): $(SRC_PATH)/qemu.nsi + $(MAKE) install DESTDIR=${INSTDIR} ifdef SIGNCODE - (cd ${INSTDIR}; \ + (cd ${INSTDIR}/${bindir}; \ for i in *.exe; do \ $(SIGNCODE) $${i}; \ done \ ) endif # SIGNCODE - (cd ${INSTDIR}; \ + (cd ${INSTDIR}/${bindir}; \ for i in qemu-system-*.exe; do \ arch=$${i%.exe}; \ arch=$${arch#qemu-system-}; \ @@ -1206,11 +1206,11 @@ endif # SIGNCODE echo File \"\$${BINDIR}\\$$i\"; \ echo SectionEnd; \ done \ - ) >${INSTDIR}/system-emulations.nsh + ) >${INSTDIR}/${bindir}/system-emulations.nsh makensis $(nsisflags) \ $(if $(BUILD_DOCS),-DCONFIG_DOCUMENTATION="y") \ $(if $(CONFIG_GTK),-DCONFIG_GTK="y") \ - -DBINDIR="${INSTDIR}" \ + -DBINDIR="${INSTDIR}/${bindir}" \ $(if $(DLL_PATH),-DDLLDIR="$(DLL_PATH)") \ -DSRCDIR="$(SRC_PATH)" \ -DOUTFILE="$(INSTALLER)" \ -- cgit v1.2.3-55-g7522 From 25211446ec0f02cd8516f490e078b5f81966e09c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Jun 2019 12:03:04 +0200 Subject: configure: do not include $(...) variables in config-host.mak This ensures that Meson will be able to reuse the results of the tests that are performed in the configure script. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- configure | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/configure b/configure index 625c14c500..606c327cca 100755 --- a/configure +++ b/configure @@ -610,8 +610,8 @@ QEMU_CFLAGS="-fno-strict-aliasing -fno-common -fwrapv -std=gnu99 $QEMU_CFLAGS" QEMU_CFLAGS="-Wall -Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS" QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS" QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE $QEMU_CFLAGS" -QEMU_INCLUDES="-iquote . -iquote \$(SRC_PATH) -iquote \$(SRC_PATH)/accel/tcg -iquote \$(SRC_PATH)/include" -QEMU_INCLUDES="$QEMU_INCLUDES -iquote \$(SRC_PATH)/disas/libvixl" +QEMU_INCLUDES="-iquote . -iquote ${source_path} -iquote ${source_path}/accel/tcg -iquote ${source_path}/include" +QEMU_INCLUDES="$QEMU_INCLUDES -iquote ${source_path}/disas/libvixl" if test "$debug_info" = "yes"; then CFLAGS="-g $CFLAGS" fi @@ -911,7 +911,7 @@ Linux) linux="yes" linux_user="yes" kvm="yes" - QEMU_INCLUDES="-isystem \$(SRC_PATH)/linux-headers -isystem $PWD/linux-headers $QEMU_INCLUDES" + QEMU_INCLUDES="-isystem ${source_path}/linux-headers -I$PWD/linux-headers $QEMU_INCLUDES" supported_os="yes" libudev="yes" ;; @@ -4397,8 +4397,8 @@ EOF if [ "$pwd_is_source_path" != "y" ] ; then symlink "$source_path/dtc/Makefile" "dtc/Makefile" fi - fdt_cflags="-I\$(SRC_PATH)/dtc/libfdt" - fdt_ldflags="-L\$(BUILD_DIR)/dtc/libfdt" + fdt_cflags="-I${source_path}/dtc/libfdt" + fdt_ldflags="-L$PWD/dtc/libfdt" fdt_libs="$fdt_libs" elif test "$fdt" = "yes" ; then # Not a git build & no libfdt found, prompt for system install @@ -5385,13 +5385,13 @@ case "$capstone" in git_submodules="${git_submodules} capstone" fi mkdir -p capstone - QEMU_CFLAGS="$QEMU_CFLAGS -I\$(SRC_PATH)/capstone/include" + QEMU_CFLAGS="$QEMU_CFLAGS -I${source_path}/capstone/include" if test "$mingw32" = "yes"; then LIBCAPSTONE=capstone.lib else LIBCAPSTONE=libcapstone.a fi - libs_cpu="-L\$(BUILD_DIR)/capstone -lcapstone $libs_cpu" + libs_cpu="-L$PWD/capstone -lcapstone $libs_cpu" ;; system) @@ -6414,8 +6414,8 @@ case "$slirp" in git_submodules="${git_submodules} slirp" fi mkdir -p slirp - slirp_cflags="-I\$(SRC_PATH)/slirp/src -I\$(BUILD_DIR)/slirp/src" - slirp_libs="-L\$(BUILD_DIR)/slirp -lslirp" + slirp_cflags="-I${source_path}/slirp/src -I$PWD/slirp/src" + slirp_libs="-L$PWD/slirp -lslirp" if test "$mingw32" = "yes" ; then slirp_libs="$slirp_libs -lws2_32 -liphlpapi" fi @@ -7909,19 +7909,19 @@ if test "$secret_keyring" = "yes" ; then fi if test "$tcg_interpreter" = "yes"; then - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/tci $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/tci $QEMU_INCLUDES" elif test "$ARCH" = "sparc64" ; then - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/sparc $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/sparc $QEMU_INCLUDES" elif test "$ARCH" = "s390x" ; then - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/s390 $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/s390 $QEMU_INCLUDES" elif test "$ARCH" = "x86_64" || test "$ARCH" = "x32" ; then - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/i386 $QEMU_INCLUDES" elif test "$ARCH" = "ppc64" ; then - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/ppc $QEMU_INCLUDES" elif test "$ARCH" = "riscv32" || test "$ARCH" = "riscv64" ; then - QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES" + QEMU_INCLUDES="-I${source_path}/tcg/riscv $QEMU_INCLUDES" else - QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES" + QEMU_INCLUDES="-iquote ${source_path}/tcg/${ARCH} $QEMU_INCLUDES" fi echo "HELPERS=$helpers" >> $config_host_mak -- cgit v1.2.3-55-g7522 From 22a87800e65c97c076853e87d733c36339bf02f0 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 11 Jul 2019 19:13:39 +0400 Subject: configure: expand path variables for meson configure Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- configure | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/configure b/configure index 606c327cca..373bb22287 100755 --- a/configure +++ b/configure @@ -415,16 +415,7 @@ LDFLAGS_SHARED="-shared" modules="no" module_upgrades="no" prefix="/usr/local" -mandir="\${prefix}/share/man" -datadir="\${prefix}/share" firmwarepath="\${prefix}/share/qemu-firmware" -qemu_docdir="\${prefix}/share/doc/qemu" -bindir="\${prefix}/bin" -libdir="\${prefix}/lib" -libexecdir="\${prefix}/libexec" -includedir="\${prefix}/include" -sysconfdir="\${prefix}/etc" -local_statedir="\${prefix}/var" confsuffix="/qemu" slirp="" oss_lib="" @@ -979,12 +970,6 @@ if test "$mingw32" = "yes" ; then LIBS="-liberty $LIBS" fi prefix="c:/Program Files/QEMU" - mandir="\${prefix}" - datadir="\${prefix}" - qemu_docdir="\${prefix}" - bindir="\${prefix}" - sysconfdir="\${prefix}" - local_statedir= confsuffix="" libs_qga="-lws2_32 -lwinmm -lpowrprof -lwtsapi32 -lwininet -liphlpapi -lnetapi32 $libs_qga" fi @@ -1638,6 +1623,26 @@ for opt do esac done +libdir="${libdir:-$prefix/lib}" +libexecdir="${libexecdir:-$prefix/libexec}" +includedir="${includedir:-$prefix/include}" + +if test "$mingw32" = "yes" ; then + mandir="$prefix" + datadir="$prefix" + qemu_docdir="$prefix" + bindir="$prefix" + sysconfdir="$prefix" + local_statedir= +else + mandir="${mandir:-$prefix/share/man}" + datadir="${datadir:-$prefix/share}" + qemu_docdir="${qemu_docdir:-$prefix/share/doc/qemu}" + bindir="${bindir:-$prefix/bin}" + sysconfdir="${sysconfdir:-$prefix/etc}" + local_statedir="${local_statedir:-$prefix/var}" +fi + case "$cpu" in ppc) CPU_CFLAGS="-m32" -- cgit v1.2.3-55-g7522 From 086d5f7529e598277caabd64b40cb15cc379ddf4 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Feb 2020 15:22:17 +0100 Subject: configure: prepare CFLAGS/CXXFLAGS/LDFLAGS for Meson Split between CFLAGS/QEMU_CFLAGS and CXXFLAGS/QEMU_CXXFLAGS so that we will use CFLAGS and CXXFLAGS for flags that we do not want to pass to add_project_arguments. Signed-off-by: Paolo Bonzini --- configure | 80 ++++++++++++++++++++++++--------------------------- rules.mak | 4 +-- softmmu/Makefile.objs | 2 +- 3 files changed, 41 insertions(+), 45 deletions(-) diff --git a/configure b/configure index 373bb22287..35d6492343 100755 --- a/configure +++ b/configure @@ -107,15 +107,12 @@ update_cxxflags() { # options which some versions of GCC's C++ compiler complain about # because they only make sense for C programs. QEMU_CXXFLAGS="$QEMU_CXXFLAGS -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS" - + CXXFLAGS=$(echo "$CFLAGS" | sed s/-std=gnu99/-std=gnu++11/) for arg in $QEMU_CFLAGS; do case $arg in -Wstrict-prototypes|-Wmissing-prototypes|-Wnested-externs|\ -Wold-style-declaration|-Wold-style-definition|-Wredundant-decls) ;; - -std=gnu99) - QEMU_CXXFLAGS=${QEMU_CXXFLAGS:+$QEMU_CXXFLAGS }"-std=gnu++98" - ;; *) QEMU_CXXFLAGS=${QEMU_CXXFLAGS:+$QEMU_CXXFLAGS }$arg ;; @@ -125,13 +122,13 @@ update_cxxflags() { compile_object() { local_cflags="$1" - do_cc $QEMU_CFLAGS $local_cflags -c -o $TMPO $TMPC + do_cc $CFLAGS $QEMU_CFLAGS $local_cflags -c -o $TMPO $TMPC } compile_prog() { local_cflags="$1" local_ldflags="$2" - do_cc $QEMU_CFLAGS $local_cflags -o $TMPE $TMPC $QEMU_LDFLAGS $local_ldflags + do_cc $CFLAGS $QEMU_CFLAGS $local_cflags -o $TMPE $TMPC $LDFLAGS $QEMU_LDFLAGS $local_ldflags } # symbolically link $1 to $2. Portable version of "ln -sf". @@ -597,15 +594,14 @@ ARFLAGS="${ARFLAGS-rv}" # left shift of signed integers is well defined and has the expected # 2s-complement style results. (Both clang and gcc agree that it # provides these semantics.) -QEMU_CFLAGS="-fno-strict-aliasing -fno-common -fwrapv -std=gnu99 $QEMU_CFLAGS" -QEMU_CFLAGS="-Wall -Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS" +QEMU_CFLAGS="-fno-strict-aliasing -fno-common -fwrapv $QEMU_CFLAGS" +QEMU_CFLAGS="-Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS" QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS" QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE $QEMU_CFLAGS" QEMU_INCLUDES="-iquote . -iquote ${source_path} -iquote ${source_path}/accel/tcg -iquote ${source_path}/include" QEMU_INCLUDES="$QEMU_INCLUDES -iquote ${source_path}/disas/libvixl" -if test "$debug_info" = "yes"; then - CFLAGS="-g $CFLAGS" -fi +CFLAGS="-std=gnu99 -Wall" + # running configure in the source tree? # we know that's the case if configure is there. @@ -886,7 +882,6 @@ SunOS) QEMU_CFLAGS="-D_XOPEN_SOURCE=600 $QEMU_CFLAGS" # needed for TIOCWIN* defines in termios.h QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" - QEMU_CFLAGS="-std=gnu99 $QEMU_CFLAGS" solarisnetlibs="-lsocket -lnsl -lresolv" LIBS="$solarisnetlibs $LIBS" libs_qga="$solarisnetlibs $libs_qga" @@ -963,7 +958,7 @@ if test "$mingw32" = "yes" ; then EXESUF=".exe" DSOSUF=".dll" # MinGW needs -mthreads for TLS and macro _MT. - QEMU_CFLAGS="-mthreads $QEMU_CFLAGS" + CFLAGS="-mthreads $CFLAGS" LIBS="-lwinmm -lws2_32 $LIBS" write_c_skeleton; if compile_prog "" "-liberty" ; then @@ -2109,7 +2104,7 @@ EOF for flag in $gcc_flags; do # We need to check both a compile and a link, since some compiler # setups fail only on a .c->.o compile and some only at link time - if do_cc $QEMU_CFLAGS -Werror $flag -c -o $TMPO $TMPC && + if compile_object "-Werror $flag" && compile_prog "-Werror $flag" ""; then QEMU_CFLAGS="$QEMU_CFLAGS $flag" QEMU_LDFLAGS="$QEMU_LDFLAGS $flag" @@ -2184,7 +2179,7 @@ fi if test "$static" = "yes"; then if test "$pie" != "no" && compile_prog "-Werror -fPIE -DPIE" "-static-pie"; then - QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS" + CFLAGS="-fPIE -DPIE $CFLAGS" QEMU_LDFLAGS="-static-pie $QEMU_LDFLAGS" pie="yes" elif test "$pie" = "yes"; then @@ -2194,11 +2189,11 @@ if test "$static" = "yes"; then pie="no" fi elif test "$pie" = "no"; then - QEMU_CFLAGS="$CFLAGS_NOPIE $QEMU_CFLAGS" - QEMU_LDFLAGS="$LDFLAGS_NOPIE $QEMU_LDFLAGS" + CFLAGS="$CFLAGS_NOPIE $CFLAGS" + LDFLAGS="$LDFLAGS_NOPIE $LDFLAGS" elif compile_prog "-Werror -fPIE -DPIE" "-pie"; then - QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS" - QEMU_LDFLAGS="-pie $QEMU_LDFLAGS" + CFLAGS="-fPIE -DPIE $CFLAGS" + LDFLAGS="-pie $LDFLAGS" pie="yes" elif test "$pie" = "yes"; then error_exit "PIE not available due to missing toolchain support" @@ -3981,7 +3976,7 @@ EOF if ! compile_prog "$glib_cflags -Werror" "$glib_libs" ; then if cc_has_warning_flag "-Wno-unknown-attributes"; then glib_cflags="-Wno-unknown-attributes $glib_cflags" - CFLAGS="-Wno-unknown-attributes $CFLAGS" + QEMU_CFLAGS="-Wno-unknown-attributes $CFLAGS" fi fi @@ -6506,10 +6501,28 @@ if test "$gcov" = "yes" ; then QEMU_CFLAGS="-fprofile-arcs -ftest-coverage -g $QEMU_CFLAGS" QEMU_LDFLAGS="-fprofile-arcs -ftest-coverage $QEMU_LDFLAGS" elif test "$fortify_source" = "yes" ; then - CFLAGS="-O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $CFLAGS" -elif test "$debug" = "no"; then + QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS" + debug=no +fi +if test "$debug" = "no"; then CFLAGS="-O2 $CFLAGS" fi +if test "$debug_info" = "yes"; then + CFLAGS="-g $CFLAGS" + LDFLAGS="-g $LDFLAGS" +fi + +case "$ARCH" in +alpha) + # Ensure there's only a single GP + QEMU_CFLAGS="-msmall-data $QEMU_CFLAGS" +;; +esac + +if test "$gprof" = "yes" ; then + QEMU_CFLAGS="-p $QEMU_CFLAGS" + QEMU_LDFLAGS="-p $QEMU_LDFLAGS" +fi if test "$have_asan" = "yes"; then QEMU_CFLAGS="-fsanitize=address $QEMU_CFLAGS" @@ -6782,7 +6795,7 @@ EOF update_cxxflags - if do_cxx $QEMU_CXXFLAGS -o $TMPE $TMPCXX $TMPO $QEMU_LDFLAGS; then + if do_cxx $CXXFLAGS $QEMU_CXXFLAGS -o $TMPE $TMPCXX $TMPO $QEMU_LDFLAGS; then # C++ compiler $cxx works ok with C compiler $cc : else @@ -7874,7 +7887,7 @@ if test "$fuzzing" = "yes" ; then if test "$have_fuzzer" = "yes"; then FUZZ_LDFLAGS=" -fsanitize=fuzzer" FUZZ_CFLAGS=" -fsanitize=fuzzer" - CFLAGS="$CFLAGS -fsanitize=fuzzer-no-link" + QEMU_CFLAGS="$QEMU_CFLAGS -fsanitize=fuzzer-no-link" else error_exit "Your compiler doesn't support -fsanitize=fuzzer" exit 1 @@ -7961,6 +7974,7 @@ echo "NM=$nm" >> $config_host_mak echo "PKG_CONFIG=$pkg_config_exe" >> $config_host_mak echo "WINDRES=$windres" >> $config_host_mak echo "CFLAGS=$CFLAGS" >> $config_host_mak +echo "CXXFLAGS=$CXXFLAGS" >> $config_host_mak echo "CFLAGS_NOPIE=$CFLAGS_NOPIE" >> $config_host_mak echo "QEMU_CFLAGS=$QEMU_CFLAGS" >> $config_host_mak echo "QEMU_CXXFLAGS=$QEMU_CXXFLAGS" >> $config_host_mak @@ -8430,24 +8444,6 @@ if test "$tcg_interpreter" = "yes" ; then disas_config "TCI" fi -case "$ARCH" in -alpha) - # Ensure there's only a single GP - cflags="-msmall-data $cflags" -;; -esac - -if test "$gprof" = "yes" ; then - if test "$target_linux_user" = "yes" ; then - cflags="-p $cflags" - ldflags="-p $ldflags" - fi - if test "$target_softmmu" = "yes" ; then - ldflags="-p $ldflags" - echo "GPROF_CFLAGS=-p" >> $config_target_mak - fi -fi - # Newer kernels on s390 check for an S390_PGSTE program header and # enable the pgste page table extensions in that case. This makes # the vm.allocate_pgste sysctl unnecessary. We enable this program diff --git a/rules.mak b/rules.mak index 56ba540a32..e79a4005a7 100644 --- a/rules.mak +++ b/rules.mak @@ -88,12 +88,12 @@ LINK = $(call quiet-command, $(LINKPROG) $(CFLAGS) $(QEMU_LDFLAGS) -o $@ \ %.o: %.cc $(call quiet-command,$(CXX) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ - $(QEMU_CXXFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) \ + $(QEMU_CXXFLAGS) $(QEMU_DGFLAGS) $(CXXFLAGS) $($@-cflags) \ -c -o $@ $<,"CXX","$(TARGET_DIR)$@") %.o: %.cpp $(call quiet-command,$(CXX) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ - $(QEMU_CXXFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) \ + $(QEMU_CXXFLAGS) $(QEMU_DGFLAGS) $(CXXFLAGS) $($@-cflags) \ -c -o $@ $<,"CXX","$(TARGET_DIR)$@") %.o: %.m diff --git a/softmmu/Makefile.objs b/softmmu/Makefile.objs index a414a74c50..c036887500 100644 --- a/softmmu/Makefile.objs +++ b/softmmu/Makefile.objs @@ -11,4 +11,4 @@ obj-y += memory_mapping.o obj-y += qtest.o obj-y += vl.o -vl.o-cflags := $(GPROF_CFLAGS) $(SDL_CFLAGS) +vl.o-cflags := $(SDL_CFLAGS) -- cgit v1.2.3-55-g7522 From bfea7012fe587805db7ee8b1767b3c4695a031fc Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Aug 2020 13:44:26 +0200 Subject: tests/vm: include setuptools They are a dependency of Meson, so install them. Signed-off-by: Paolo Bonzini --- tests/vm/freebsd | 1 + tests/vm/netbsd | 1 + tests/vm/openbsd | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/vm/freebsd b/tests/vm/freebsd index 29252fa4a6..b34b14fc53 100755 --- a/tests/vm/freebsd +++ b/tests/vm/freebsd @@ -33,6 +33,7 @@ class FreeBSDVM(basevm.BaseVM): "pkgconf", "bzip2", "python37", + "py37-setuptools", # gnu tools "bash", diff --git a/tests/vm/netbsd b/tests/vm/netbsd index 2e87199211..93d48b6fdd 100755 --- a/tests/vm/netbsd +++ b/tests/vm/netbsd @@ -31,6 +31,7 @@ class NetBSDVM(basevm.BaseVM): "pkgconf", "xz", "python37", + "py37-setuptools", # gnu tools "bash", diff --git a/tests/vm/openbsd b/tests/vm/openbsd index dfe633e453..7e27fda642 100755 --- a/tests/vm/openbsd +++ b/tests/vm/openbsd @@ -30,6 +30,7 @@ class OpenBSDVM(basevm.BaseVM): "git", "pkgconf", "bzip2", "xz", + "py3-setuptools", # gnu tools "bash", -- cgit v1.2.3-55-g7522 From dedad0272052f3d848d6d178b681526b2f313029 Mon Sep 17 00:00:00 2001 From: Daniel P. Berrangé Date: Fri, 21 Aug 2020 12:22:04 +0200 Subject: configure: add support for pseudo-"in source tree" builds Meson requires the build dir to be separate from the source tree. Many people are used to just running "./configure && make" though and the meson conversion breaks that. This introduces some backcompat support to make it appear as if an "in source tree" build is being done, but with the results in the "build/" directory. This allows "./configure && make" to work as it did historically, albeit with the output binaries staying under build/. Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrangé Signed-off-by: Paolo Bonzini --- .gitignore | 2 ++ configure | 52 +++++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 51 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index f8b3cd6fd5..d1e5e06242 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ +/GNUmakefile +/build/ /.doctrees /config-devices.* /config-all-devices.* diff --git a/configure b/configure index 35d6492343..f86e03981e 100755 --- a/configure +++ b/configure @@ -11,6 +11,55 @@ unset CLICOLOR_FORCE GREP_OPTIONS # Don't allow CCACHE, if present, to use cached results of compile tests! export CCACHE_RECACHE=yes +# make source path absolute +source_path=$(cd "$(dirname -- "$0")"; pwd) + +if test "$PWD" = "$source_path" +then + echo "Using './build' as the directory for build output" + + MARKER=build/auto-created-by-configure + + if test -e build + then + if test -f $MARKER + then + rm -rf build + else + echo "ERROR: ./build dir already exists and was not previously created by configure" + exit 1 + fi + fi + + mkdir build + touch $MARKER + + cat > GNUmakefile <<'EOF' +# This file is auto-generated by configure to support in-source tree +# 'make' command invocation + +ifeq ($(MAKECMDGOALS),) +recurse: all +endif + +.NOTPARALLEL: % +%: force + @echo 'changing dir to build for $(MAKE) "$(MAKECMDGOALS)"...' + @$(MAKE) -C build -f Makefile $(MAKECMDGOALS) + @if test "$(MAKECMDGOALS)" = "distclean" && \ + test -e build/auto-created-by-configure ; \ + then \ + rm -rf build GNUmakefile ; \ + fi +force: ; +.PHONY: force +GNUmakefile: ; + +EOF + cd build + exec $source_path/configure "$@" +fi + # Temporary directory used for files created while # configure runs. Since it is in the build directory # we can safely blow away any previous version of it @@ -279,9 +328,6 @@ ld_has() { $ld --help 2>/dev/null | grep ".$1" >/dev/null 2>&1 } -# make source path absolute -source_path=$(cd "$(dirname -- "$0")"; pwd) - if printf %s\\n "$source_path" "$PWD" | grep -q "[[:space:]:]"; then error_exit "main directory cannot contain spaces nor colons" -- cgit v1.2.3-55-g7522 From a56650518f5ba84ed15b9415fa1041311eeeece0 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Jun 2019 12:05:14 +0200 Subject: configure: integrate Meson in the build system The Meson build system is integrated in the existing configure/make steps by invoking Meson from the configure script and converting Meson's build.ninja rules to an included Makefile. build.ninja already provides tags/ctags/cscope rules, so they are removed. Signed-off-by: Paolo Bonzini --- Makefile | 50 ++- configure | 52 ++- meson.build | 25 ++ scripts/ninjatool.py | 1002 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1107 insertions(+), 22 deletions(-) create mode 100644 meson.build create mode 100755 scripts/ninjatool.py diff --git a/Makefile b/Makefile index ec12101a84..b726e7d8d2 100644 --- a/Makefile +++ b/Makefile @@ -49,6 +49,25 @@ git-submodule-update: endif endif +export NINJA=./ninjatool + +# Running meson regenerates both build.ninja and ninjatool, and that is +# enough to prime the rest of the build. +ninjatool: build.ninja + +# Only needed in case Makefile.ninja does not exist. +.PHONY: ninja-clean ninja-distclean clean-ctlist +clean-ctlist: +ninja-clean:: +ninja-distclean:: +build.ninja: config-host.mak + +Makefile.ninja: build.ninja ninjatool + ./ninjatool -t ninja2make --omit clean dist uninstall < $< > $@ +-include Makefile.ninja + +${ninja-targets-c_COMPILER} ${ninja-targets-cpp_COMPILER}: .var.command += -MP + .git-submodule-status: git-submodule-update config-host.mak # Check that we're not trying to do an out-of-tree build from @@ -70,7 +89,11 @@ CONFIG_ALL=y config-host.mak: $(SRC_PATH)/configure $(SRC_PATH)/pc-bios $(SRC_PATH)/VERSION @echo $@ is out-of-date, running configure - @./config.status + @if test -f meson-private/coredata.dat; then \ + ./config.status --skip-meson; \ + else \ + ./config.status; \ + fi # Force configure to re-run if the API symbols are updated ifeq ($(CONFIG_PLUGIN),y) @@ -762,7 +785,8 @@ clean-coverage: "CLEAN", "coverage files") endif -clean: recurse-clean +clean: recurse-clean ninja-clean clean-ctlist + -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h rm -f qemu-options.def @@ -799,7 +823,8 @@ rm -rf $(MANUAL_BUILDDIR)/$1/_static rm -f $(MANUAL_BUILDDIR)/$1/objects.inv $(MANUAL_BUILDDIR)/$1/searchindex.js $(MANUAL_BUILDDIR)/$1/*.html endef -distclean: clean +distclean: clean ninja-distclean + -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean -g rm -f config-host.mak config-host.h* $(DOCS) rm -f tests/tcg/config-*.mak rm -f config-all-devices.mak config-all-disas.mak config.status @@ -807,6 +832,8 @@ distclean: clean rm -f po/*.mo tests/qemu-iotests/common.env rm -f roms/seabios/config.mak roms/vgabios/config.mak rm -f qemu-plugins-ld.symbols qemu-plugins-ld64.symbols + rm -rf meson-private meson-logs meson-info compile_commands.json + rm -f Makefile.ninja ninjatool ninjatool.stamp rm -f config.log rm -f linux-headers/asm rm -f docs/version.texi @@ -933,6 +960,8 @@ ICON_SIZES=16x16 24x24 32x32 48x48 64x64 128x128 256x256 512x512 install-includedir: $(INSTALL_DIR) "$(DESTDIR)$(includedir)" +# Needed by "meson install" +export DESTDIR install: all $(if $(BUILD_DOCS),install-doc) \ install-datadir install-localstatedir install-includedir \ $(if $(INSTALL_BLOBS),$(edk2-decompressed)) \ @@ -1006,21 +1035,6 @@ endif done $(INSTALL_DATA) $(BUILD_DIR)/trace-events-all "$(DESTDIR)$(qemu_datadir)/trace-events-all" -.PHONY: ctags -ctags: - rm -f tags - find "$(SRC_PATH)" -name '*.[hc]' -exec ctags --append {} + - -.PHONY: TAGS -TAGS: - rm -f TAGS - find "$(SRC_PATH)" -name '*.[hc]' -exec etags --append {} + - -cscope: - rm -f "$(SRC_PATH)"/cscope.* - find "$(SRC_PATH)/" -name "*.[chsS]" -print | sed 's,^\./,,' > "$(SRC_PATH)/cscope.files" - cscope -b -i"$(SRC_PATH)/cscope.files" - # opengl shader programs ui/shader/%-vert.h: $(SRC_PATH)/ui/shader/%.vert $(SRC_PATH)/scripts/shaderinclude.pl @mkdir -p $(dir $@) diff --git a/configure b/configure index f86e03981e..26d571afca 100755 --- a/configure +++ b/configure @@ -552,6 +552,8 @@ fuzzing="no" rng_none="no" secret_keyring="" libdaxctl="" +meson="" +skip_meson=no supported_cpu="no" supported_os="no" @@ -1048,6 +1050,10 @@ for opt do ;; --sphinx-build=*) sphinx_build="$optarg" ;; + --skip-meson) skip_meson=yes + ;; + --meson=*) meson="$optarg" + ;; --gcov=*) gcov_tool="$optarg" ;; --smbd=*) smbd="$optarg" @@ -1813,6 +1819,7 @@ Advanced options (experts only): --install=INSTALL use specified install [$install] --python=PYTHON use specified python [$python] --sphinx-build=SPHINX use specified sphinx-build [$sphinx_build] + --meson=MESON use specified meson [$meson] --smbd=SMBD use specified smbd [$smbd] --with-git=GIT use specified git [$git] --static enable static build [$static] @@ -2020,6 +2027,16 @@ python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0] # Suppress writing compiled files python="$python -B" +if ! has "$meson" +then + error_exit "Meson not found. Use --meson=/path/to/meson" +fi +meson=$(command -v $meson) + +if ! $python -c 'import pkg_resources' > /dev/null 2>&1; then + error_exit "Python setuptools not found" +fi + # Check that the C compiler works. Doing this here before testing # the host CPU ensures that we had a valid CC to autodetect the # $cpu var (and we should bail right here if that's not the case). @@ -6550,13 +6567,13 @@ elif test "$fortify_source" = "yes" ; then QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS" debug=no fi -if test "$debug" = "no"; then - CFLAGS="-O2 $CFLAGS" -fi if test "$debug_info" = "yes"; then CFLAGS="-g $CFLAGS" LDFLAGS="-g $LDFLAGS" fi +if test "$debug" = "no"; then + CFLAGS="-O2 $CFLAGS" +fi case "$ARCH" in alpha) @@ -8001,6 +8018,7 @@ echo "PYTHON=$python" >> $config_host_mak echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak echo "GENISOIMAGE=$genisoimage" >> $config_host_mak +echo "MESON=$meson" >> $config_host_mak echo "CC=$cc" >> $config_host_mak if $iasl -h > /dev/null 2>&1; then echo "IASL=$iasl" >> $config_host_mak @@ -8611,6 +8629,30 @@ echo "# Automatically generated by configure - do not modify" > "$iotests_common echo >> "$iotests_common_env" echo "export PYTHON='$python'" >> "$iotests_common_env" +if test "$skip_meson" = no; then +rm -rf meson-private meson-info meson-logs +NINJA=$PWD/ninjatool $meson setup \ + --prefix "$prefix" \ + --libdir "$libdir" \ + --libexecdir "$libexecdir" \ + --bindir "$bindir" \ + --includedir "$includedir" \ + --datadir "$datadir" \ + --mandir "$mandir" \ + --sysconfdir "$sysconfdir" \ + --localstatedir "$local_statedir" \ + -Doptimization=$(if test "$debug" = yes; then echo 0; else echo 2; fi) \ + -Ddebug=$(if test "$debug_info" = yes; then echo true; else echo false; fi) \ + -Dwerror=$(if test "$werror" = yes; then echo true; else echo false; fi) \ + -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \ + "$PWD" "$source_path" + +if test "$?" -ne 0 ; then + error_exit "meson setup failed" +fi +touch ninjatool.stamp +fi + # Save the configure command line for later reuse. cat <config.status #!/bin/sh @@ -8659,7 +8701,9 @@ preserve_env STRIP preserve_env WINDRES printf "exec" >>config.status -printf " '%s'" "$0" "$@" >>config.status +for i in "$0" "$@"; do + test "$i" = --skip-meson || printf " '%s'" "$i" >>config.status +done echo ' "$@"' >>config.status chmod +x config.status diff --git a/meson.build b/meson.build new file mode 100644 index 0000000000..613983e464 --- /dev/null +++ b/meson.build @@ -0,0 +1,25 @@ +project('qemu', ['c'], meson_version: '>=0.55.0', + default_options: ['warning_level=1', 'c_std=gnu99', 'cpp_std=gnu++11', 'b_lundef=false'], + version: run_command('head', meson.source_root() / 'VERSION').stdout().strip()) + +not_found = dependency('', required: false) +keyval = import('unstable-keyval') +config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') + +add_project_arguments(config_host['QEMU_CFLAGS'].split(), + native: false, language: ['c', 'objc']) +add_project_arguments(config_host['QEMU_CXXFLAGS'].split(), + native: false, language: 'cpp') +add_project_link_arguments(config_host['QEMU_LDFLAGS'].split(), + native: false, language: ['c', 'cpp', 'objc']) +add_project_arguments(config_host['QEMU_INCLUDES'].split(), + language: ['c', 'cpp', 'objc']) + +add_languages('cpp', required: false, native: false) +if host_machine.system() == 'darwin' + add_languages('objc', required: false, native: false) +endif + +configure_file(input: files('scripts/ninjatool.py'), + output: 'ninjatool', + configuration: config_host) diff --git a/scripts/ninjatool.py b/scripts/ninjatool.py new file mode 100755 index 0000000000..cc77d51aa8 --- /dev/null +++ b/scripts/ninjatool.py @@ -0,0 +1,1002 @@ +#! /bin/sh + +# Python module for parsing and processing .ninja files. +# +# Author: Paolo Bonzini +# +# Copyright (C) 2019 Red Hat, Inc. + + +# We don't want to put "#! @PYTHON@" as the shebang and +# make the file executable, so instead we make this a +# Python/shell polyglot. The first line below starts a +# multiline string literal for Python, while it is just +# ":" for bash. The closing of the multiline string literal +# is never parsed by bash since it exits before. + +'''': +case "$0" in + /*) me=$0 ;; + *) me=$(command -v "$0") ;; +esac +python="@PYTHON@" +case $python in + @*) python=python3 ;; +esac +exec $python "$me" "$@" +exit 1 +''' + + +from collections import namedtuple, defaultdict +import sys +import os +import re +import json +import argparse +import shutil + + +class InvalidArgumentError(Exception): + pass + +# faster version of os.path.normpath: do nothing unless there is a double +# slash or a "." or ".." component. The filter does not have to be super +# precise, but it has to be fast. os.path.normpath is the hottest function +# for ninja2make without this optimization! +if os.path.sep == '/': + def normpath(path, _slow_re=re.compile('/[./]')): + return os.path.normpath(path) if _slow_re.search(path) or path[0] == '.' else path +else: + normpath = os.path.normpath + + +# ---- lexer and parser ---- + +PATH_RE = r"[^$\s:|]+|\$[$ :]|\$[a-zA-Z0-9_-]+|\$\{[a-zA-Z0-9_.-]+\}" + +SIMPLE_PATH_RE = re.compile(r"[^$\s:|]+") +IDENT_RE = re.compile(r"[a-zA-Z0-9_.-]+$") +STRING_RE = re.compile(r"(" + PATH_RE + r"|[\s:|])(?:\r?\n)?|.") +TOPLEVEL_RE = re.compile(r"([=:#]|\|\|?|^ +|(?:" + PATH_RE + r")+)\s*|.") +VAR_RE=re.compile(r'\$\$|\$\{([^}]*)\}') + +BUILD = 1 +POOL = 2 +RULE = 3 +DEFAULT = 4 +EQUALS = 5 +COLON = 6 +PIPE = 7 +PIPE2 = 8 +IDENT = 9 +INCLUDE = 10 +INDENT = 11 +EOL = 12 + + +class LexerError(Exception): + pass + + +class ParseError(Exception): + pass + + +class NinjaParserEvents(object): + def __init__(self, parser): + self.parser = parser + + def dollar_token(self, word, in_path=False): + return '$$' if word == '$' else word + + def variable_expansion_token(self, varname): + return '${%s}' % varname + + def variable(self, name, arg): + pass + + def begin_file(self): + pass + + def end_file(self): + pass + + def end_scope(self): + pass + + def begin_pool(self, name): + pass + + def begin_rule(self, name): + pass + + def begin_build(self, out, iout, rule, in_, iin, orderdep): + pass + + def default(self, targets): + pass + + +class NinjaParser(object): + + InputFile = namedtuple('InputFile', 'filename iter lineno') + + def __init__(self, filename, input): + self.stack = [] + self.top = None + self.iter = None + self.lineno = None + self.match_keyword = False + self.push(filename, input) + + def file_changed(self): + self.iter = self.top.iter + self.lineno = self.top.lineno + if self.top.filename is not None: + os.chdir(os.path.dirname(self.top.filename) or '.') + + def push(self, filename, input): + if self.top: + self.top.lineno = self.lineno + self.top.iter = self.iter + self.stack.append(self.top) + self.top = self.InputFile(filename=filename or 'stdin', + iter=self._tokens(input), lineno=0) + self.file_changed() + + def pop(self): + if len(self.stack): + self.top = self.stack[-1] + self.stack.pop() + self.file_changed() + else: + self.top = self.iter = None + + def next_line(self, input): + line = next(input).rstrip() + self.lineno += 1 + while len(line) and line[-1] == '$': + line = line[0:-1] + next(input).strip() + self.lineno += 1 + return line + + def print_token(self, tok): + if tok == EOL: + return "end of line" + if tok == BUILD: + return '"build"' + if tok == POOL: + return '"pool"' + if tok == RULE: + return '"rule"' + if tok == DEFAULT: + return '"default"' + if tok == EQUALS: + return '"="' + if tok == COLON: + return '":"' + if tok == PIPE: + return '"|"' + if tok == PIPE2: + return '"||"' + if tok == INCLUDE: + return '"include"' + if tok == IDENT: + return 'identifier' + return '"%s"' % tok + + def error(self, msg): + raise LexerError("%s:%d: %s" % (self.stack[-1].filename, self.lineno, msg)) + + def parse_error(self, msg): + raise ParseError("%s:%d: %s" % (self.stack[-1].filename, self.lineno, msg)) + + def expected(self, expected, tok): + msg = "found %s, expected " % (self.print_token(tok), ) + for i, exp_tok in enumerate(expected): + if i > 0: + msg = msg + (' or ' if i == len(expected) - 1 else ', ') + msg = msg + self.print_token(exp_tok) + self.parse_error(msg) + + def _variable_tokens(self, value): + for m in STRING_RE.finditer(value): + match = m.group(1) + if not match: + self.error("unexpected '%s'" % (m.group(0), )) + yield match + + def _tokens(self, input): + while True: + try: + line = self.next_line(input) + except StopIteration: + return + for m in TOPLEVEL_RE.finditer(line): + match = m.group(1) + if not match: + self.error("unexpected '%s'" % (m.group(0), )) + if match == ':': + yield COLON + continue + if match == '|': + yield PIPE + continue + if match == '||': + yield PIPE2 + continue + if match[0] == ' ': + yield INDENT + continue + if match[0] == '=': + yield EQUALS + value = line[m.start() + 1:].lstrip() + yield from self._variable_tokens(value) + break + if match[0] == '#': + break + + # identifier + if self.match_keyword: + if match == 'build': + yield BUILD + continue + if match == 'pool': + yield POOL + continue + if match == 'rule': + yield RULE + continue + if match == 'default': + yield DEFAULT + continue + if match == 'include': + filename = line[m.start() + 8:].strip() + self.push(filename, open(filename, 'r')) + break + if match == 'subninja': + self.error('subninja is not supported') + yield match + yield EOL + + def parse(self, events): + global_var = True + + def look_for(*expected): + # The last token in the token stream is always EOL. This + # is exploited to avoid catching StopIteration everywhere. + tok = next(self.iter) + if tok not in expected: + self.expected(expected, tok) + return tok + + def look_for_ident(*expected): + tok = next(self.iter) + if isinstance(tok, str): + if not IDENT_RE.match(tok): + self.parse_error('variable expansion not allowed') + elif tok not in expected: + self.expected(expected + (IDENT,), tok) + return tok + + def parse_assignment_rhs(gen, expected, in_path): + tokens = [] + for tok in gen: + if not isinstance(tok, str): + if tok in expected: + break + self.expected(expected + (IDENT,), tok) + if tok[0] != '$': + tokens.append(tok) + elif tok == '$ ' or tok == '$$' or tok == '$:': + tokens.append(events.dollar_token(tok[1], in_path)) + else: + var = tok[2:-1] if tok[1] == '{' else tok[1:] + tokens.append(events.variable_expansion_token(var)) + else: + # gen must have raised StopIteration + tok = None + + if tokens: + # Fast path avoiding str.join() + value = tokens[0] if len(tokens) == 1 else ''.join(tokens) + else: + value = None + return value, tok + + def look_for_path(*expected): + # paths in build rules are parsed one space-separated token + # at a time and expanded + token = next(self.iter) + if not isinstance(token, str): + return None, token + # Fast path if there are no dollar and variable expansion + if SIMPLE_PATH_RE.match(token): + return token, None + gen = self._variable_tokens(token) + return parse_assignment_rhs(gen, expected, True) + + def parse_assignment(tok): + name = tok + assert isinstance(name, str) + look_for(EQUALS) + value, tok = parse_assignment_rhs(self.iter, (EOL,), False) + assert tok == EOL + events.variable(name, value) + + def parse_build(): + # parse outputs + out = [] + iout = [] + while True: + value, tok = look_for_path(COLON, PIPE) + if value is None: + break + out.append(value) + if tok == PIPE: + while True: + value, tok = look_for_path(COLON) + if value is None: + break + iout.append(value) + + # parse rule + assert tok == COLON + rule = look_for_ident() + + # parse inputs and dependencies + in_ = [] + iin = [] + orderdep = [] + while True: + value, tok = look_for_path(PIPE, PIPE2, EOL) + if value is None: + break + in_.append(value) + if tok == PIPE: + while True: + value, tok = look_for_path(PIPE2, EOL) + if value is None: + break + iin.append(value) + if tok == PIPE2: + while True: + value, tok = look_for_path(EOL) + if value is None: + break + orderdep.append(value) + assert tok == EOL + events.begin_build(out, iout, rule, in_, iin, orderdep) + nonlocal global_var + global_var = False + + def parse_pool(): + # pool declarations are ignored. Just gobble all the variables + ident = look_for_ident() + look_for(EOL) + events.begin_pool(ident) + nonlocal global_var + global_var = False + + def parse_rule(): + ident = look_for_ident() + look_for(EOL) + events.begin_rule(ident) + nonlocal global_var + global_var = False + + def parse_default(): + idents = [] + while True: + ident = look_for_ident(EOL) + if ident == EOL: + break + idents.append(ident) + events.default(idents) + + def parse_declaration(tok): + if tok == EOL: + return + + nonlocal global_var + if tok == INDENT: + if global_var: + self.parse_error('indented line outside rule or edge') + tok = look_for_ident(EOL) + if tok == EOL: + return + parse_assignment(tok) + return + + if not global_var: + events.end_scope() + global_var = True + if tok == POOL: + parse_pool() + elif tok == BUILD: + parse_build() + elif tok == RULE: + parse_rule() + elif tok == DEFAULT: + parse_default() + elif isinstance(tok, str): + parse_assignment(tok) + else: + self.expected((POOL, BUILD, RULE, INCLUDE, DEFAULT, IDENT), tok) + + events.begin_file() + while self.iter: + try: + self.match_keyword = True + token = next(self.iter) + self.match_keyword = False + parse_declaration(token) + except StopIteration: + self.pop() + events.end_file() + + +# ---- variable handling ---- + +def expand(x, rule_vars=None, build_vars=None, global_vars=None): + if x is None: + return None + changed = True + have_dollar_replacement = False + while changed: + changed = False + matches = list(VAR_RE.finditer(x)) + if not matches: + break + + # Reverse the match so that expanding later matches does not + # invalidate m.start()/m.end() for earlier ones. Do not reduce $$ to $ + # until all variables are dealt with. + for m in reversed(matches): + name = m.group(1) + if not name: + have_dollar_replacement = True + continue + changed = True + if build_vars and name in build_vars: + value = build_vars[name] + elif rule_vars and name in rule_vars: + value = rule_vars[name] + elif name in global_vars: + value = global_vars[name] + else: + value = '' + x = x[:m.start()] + value + x[m.end():] + return x.replace('$$', '$') if have_dollar_replacement else x + + +class Scope(object): + def __init__(self, events): + self.events = events + + def on_left_scope(self): + pass + + def on_variable(self, key, value): + pass + + +class BuildScope(Scope): + def __init__(self, events, out, iout, rule, in_, iin, orderdep, rule_vars): + super().__init__(events) + self.rule = rule + self.out = [events.expand_and_normalize(x) for x in out] + self.in_ = [events.expand_and_normalize(x) for x in in_] + self.iin = [events.expand_and_normalize(x) for x in iin] + self.orderdep = [events.expand_and_normalize(x) for x in orderdep] + self.iout = [events.expand_and_normalize(x) for x in iout] + self.rule_vars = rule_vars + self.build_vars = dict() + self._define_variable('out', ' '.join(self.out)) + self._define_variable('in', ' '.join(self.in_)) + + def expand(self, x): + return self.events.expand(x, self.rule_vars, self.build_vars) + + def on_left_scope(self): + self.events.variable('out', self.build_vars['out']) + self.events.variable('in', self.build_vars['in']) + self.events.end_build(self, self.out, self.iout, self.rule, self.in_, + self.iin, self.orderdep) + + def _define_variable(self, key, value): + # The value has been expanded already, quote it for further + # expansion from rule variables + value = value.replace('$', '$$') + self.build_vars[key] = value + + def on_variable(self, key, value): + # in and out are at the top of the lookup order and cannot + # be overridden. Also, unlike what the manual says, build + # variables only lookup global variables. They never lookup + # rule variables, earlier build variables, or in/out. + if key not in ('in', 'in_newline', 'out'): + self._define_variable(key, self.events.expand(value)) + + +class RuleScope(Scope): + def __init__(self, events, name, vars_dict): + super().__init__(events) + self.name = name + self.vars_dict = vars_dict + self.generator = False + + def on_left_scope(self): + self.events.end_rule(self, self.name) + + def on_variable(self, key, value): + self.vars_dict[key] = value + if key == 'generator': + self.generator = True + + +class NinjaParserEventsWithVars(NinjaParserEvents): + def __init__(self, parser): + super().__init__(parser) + self.rule_vars = defaultdict(lambda: dict()) + self.global_vars = dict() + self.scope = None + + def variable(self, name, value): + if self.scope: + self.scope.on_variable(name, value) + else: + self.global_vars[name] = self.expand(value) + + def begin_build(self, out, iout, rule, in_, iin, orderdep): + if rule != 'phony' and rule not in self.rule_vars: + self.parser.parse_error("undefined rule '%s'" % rule) + + self.scope = BuildScope(self, out, iout, rule, in_, iin, orderdep, self.rule_vars[rule]) + + def begin_pool(self, name): + # pool declarations are ignored. Just gobble all the variables + self.scope = Scope(self) + + def begin_rule(self, name): + if name in self.rule_vars: + self.parser.parse_error("duplicate rule '%s'" % name) + self.scope = RuleScope(self, name, self.rule_vars[name]) + + def end_scope(self): + self.scope.on_left_scope() + self.scope = None + + # utility functions: + + def expand(self, x, rule_vars=None, build_vars=None): + return expand(x, rule_vars, build_vars, self.global_vars) + + def expand_and_normalize(self, x): + return normpath(self.expand(x)) + + # extra events not present in the superclass: + + def end_build(self, scope, out, iout, rule, in_, iin, orderdep): + pass + + def end_rule(self, scope, name): + pass + + +# ---- test client that just prints back whatever it parsed ---- + +class Writer(NinjaParserEvents): + ARGS = argparse.ArgumentParser(description='Rewrite input build.ninja to stdout.') + + def __init__(self, output, parser, args): + super().__init__(parser) + self.output = output + self.indent = '' + self.had_vars = False + + def dollar_token(self, word, in_path=False): + return '$' + word + + def print(self, *args, **kwargs): + if len(args): + self.output.write(self.indent) + print(*args, **kwargs, file=self.output) + + def variable(self, name, value): + self.print('%s = %s' % (name, value)) + self.had_vars = True + + def begin_scope(self): + self.indent = ' ' + self.had_vars = False + + def end_scope(self): + if self.had_vars: + self.print() + self.indent = '' + self.had_vars = False + + def begin_pool(self, name): + self.print('pool %s' % name) + self.begin_scope() + + def begin_rule(self, name): + self.print('rule %s' % name) + self.begin_scope() + + def begin_build(self, outputs, implicit_outputs, rule, inputs, implicit, order_only): + all_outputs = list(outputs) + all_inputs = list(inputs) + + if implicit: + all_inputs.append('|') + all_inputs.extend(implicit) + if order_only: + all_inputs.append('||') + all_inputs.extend(order_only) + if implicit_outputs: + all_outputs.append('|') + all_outputs.extend(implicit_outputs) + + self.print('build %s: %s' % (' '.join(all_outputs), + ' '.join([rule] + all_inputs))) + self.begin_scope() + + def default(self, targets): + self.print('default %s' % ' '.join(targets)) + + +# ---- emit compile_commands.json ---- + +class Compdb(NinjaParserEventsWithVars): + ARGS = argparse.ArgumentParser(description='Emit compile_commands.json.') + ARGS.add_argument('rules', nargs='*', + help='The ninja rules to emit compilation commands for.') + + def __init__(self, output, parser, args): + super().__init__(parser) + self.output = output + self.rules = args.rules + self.sep = '' + + def begin_file(self): + self.output.write('[') + self.directory = os.getcwd() + + def print_entry(self, **entry): + entry['directory'] = self.directory + self.output.write(self.sep + json.dumps(entry)) + self.sep = ',\n' + + def begin_build(self, out, iout, rule, in_, iin, orderdep): + if in_ and rule in self.rules: + super().begin_build(out, iout, rule, in_, iin, orderdep) + else: + self.scope = Scope(self) + + def end_build(self, scope, out, iout, rule, in_, iin, orderdep): + self.print_entry(command=scope.expand('${command}'), file=in_[0]) + + def end_file(self): + self.output.write(']\n') + + +# ---- clean output files ---- + +class Clean(NinjaParserEventsWithVars): + ARGS = argparse.ArgumentParser(description='Remove output build files.') + ARGS.add_argument('-g', dest='generator', action='store_true', + help='clean generated files too') + + def __init__(self, output, parser, args): + super().__init__(parser) + self.dry_run = args.dry_run + self.verbose = args.verbose or args.dry_run + self.generator = args.generator + + def begin_file(self): + print('Cleaning... ', end=(None if self.verbose else ''), flush=True) + self.cnt = 0 + + def end_file(self): + print('%d files' % self.cnt) + + def do_clean(self, *files): + for f in files: + if self.dry_run: + if os.path.exists(f): + self.cnt += 1 + print('Would remove ' + f) + continue + else: + try: + if os.path.isdir(f): + shutil.rmtree(f) + else: + os.unlink(f) + self.cnt += 1 + if self.verbose: + print('Removed ' + f) + except FileNotFoundError: + pass + + def end_build(self, scope, out, iout, rule, in_, iin, orderdep): + if rule == 'phony': + return + if self.generator: + rspfile = scope.expand('${rspfile}') + if rspfile: + self.do_clean(rspfile) + if self.generator or not scope.expand('${generator}'): + self.do_clean(*out, *iout) + depfile = scope.expand('${depfile}') + if depfile: + self.do_clean(depfile) + + +# ---- convert build.ninja to makefile ---- + +class Ninja2Make(NinjaParserEventsWithVars): + ARGS = argparse.ArgumentParser(description='Convert build.ninja to a Makefile.') + ARGS.add_argument('--clean', dest='emit_clean', action='store_true', + help='Emit clean/distclean rules.') + ARGS.add_argument('--doublecolon', action='store_true', + help='Emit double-colon rules for phony targets.') + ARGS.add_argument('--omit', metavar='TARGET', nargs='+', + help='Targets to omit.') + + def __init__(self, output, parser, args): + super().__init__(parser) + self.output = output + + self.emit_clean = args.emit_clean + self.doublecolon = args.doublecolon + self.omit = set(args.omit) + + if self.emit_clean: + self.omit.update(['clean', 'distclean']) + + # Lists of targets are kept in memory and emitted only at the + # end because appending is really inefficient in GNU make. + # We only do it when it's O(#rules) or O(#variables), but + # never when it could be O(#targets). + self.depfiles = list() + self.rspfiles = list() + self.build_vars = defaultdict(lambda: dict()) + self.rule_targets = defaultdict(lambda: list()) + self.stamp_targets = defaultdict(lambda: list()) + self.num_stamp = defaultdict(lambda: 0) + self.all_outs = set() + self.all_ins = set() + self.all_phony = set() + self.seen_default = False + + def print(self, *args, **kwargs): + print(*args, **kwargs, file=self.output) + + def dollar_token(self, word, in_path=False): + if in_path and word == ' ': + self.parser.parse_error('Make does not support spaces in filenames') + return '$$' if word == '$' else word + + def print_phony(self, outs, ins): + targets = ' '.join(outs).replace('$', '$$') + deps = ' '.join(ins).replace('$', '$$') + deps = deps.strip() + if self.doublecolon: + self.print(targets + '::' + (' ' if deps else '') + deps + ';@:') + else: + self.print(targets + ':' + (' ' if deps else '') + deps) + self.all_phony.update(outs) + + def begin_file(self): + self.print(r'# This is an automatically generated file, and it shows.') + self.print(r'ninja-default:') + self.print(r'.PHONY: ninja-default ninja-clean ninja-distclean') + if self.emit_clean: + self.print(r'ninja-clean:: ninja-clean-start; $(if $V,,@)rm -f ${ninja-depfiles}') + self.print(r'ninja-clean-start:; $(if $V,,@echo Cleaning...)') + self.print(r'ninja-distclean:: clean; $(if $V,,@)rm -f ${ninja-rspfiles}') + self.print(r'.PHONY: ninja-clean-start') + self.print_phony(['clean'], ['ninja-clean']) + self.print_phony(['distclean'], ['ninja-distclean']) + self.print(r'vpath') + self.print(r'NULL :=') + self.print(r'SPACE := ${NULL} #') + self.print(r'MAKEFLAGS += -rR') + self.print(r'define NEWLINE') + self.print(r'') + self.print(r'endef') + self.print(r'.var.in_newline = $(subst $(SPACE),$(NEWLINE),${.var.in})') + self.print(r"ninja-command = $(if $V,,$(if ${.var.description},@printf '%s\n' '$(subst ','\'',${.var.description})' && ))${.var.command}") + self.print(r"ninja-command-restat = $(if $V,,$(if ${.var.description},@printf '%s\n' '$(subst ','\'',${.var.description})' && ))${.var.command} && if test -e $(firstword ${.var.out}); then printf '%s\n' ${.var.out} > $@; fi") + + def end_file(self): + def natural_sort_key(s, _nsre=re.compile('([0-9]+)')): + return [int(text) if text.isdigit() else text.lower() + for text in _nsre.split(s)] + + self.print() + self.print('ninja-outputdirs :=') + for rule in self.rule_vars: + if rule == 'phony': + continue + self.print('ninja-targets-%s := %s' % (rule, ' '.join(self.rule_targets[rule]))) + self.print('ninja-stamp-%s := %s' % (rule, ' '.join(self.stamp_targets[rule]))) + self.print('ninja-outputdirs += $(sort $(dir ${ninja-targets-%s}))' % rule) + self.print() + self.print('dummy := $(shell mkdir -p . $(sort $(ninja-outputdirs)))') + self.print('ninja-depfiles :=' + ' '.join(self.depfiles)) + self.print('ninja-rspfiles :=' + ' '.join(self.rspfiles)) + self.print('-include ${ninja-depfiles}') + self.print() + for targets in self.build_vars: + for name, value in self.build_vars[targets].items(): + self.print('%s: private .var.%s := %s' % (targets, name, value)) + self.print() + if not self.seen_default: + default_targets = sorted(self.all_outs - self.all_ins, key=natural_sort_key) + self.print('ninja-default: ' + ' '.join(default_targets)) + + # This is a hack... Meson declares input meson.build files as + # phony, because Ninja does not have an equivalent of Make's + # "path/to/file:" declaration that ignores "path/to/file" even + # if it is absent. However, Makefile.ninja wants to depend on + # build.ninja, which in turn depends on these phony targets which + # would cause Makefile.ninja to be rebuilt in a loop. + phony_targets = sorted(self.all_phony - self.all_ins, key=natural_sort_key) + self.print('.PHONY: ' + ' '.join(phony_targets)) + + def variable(self, name, value): + super().variable(name, value) + if self.scope is None: + self.global_vars[name] = self.expand(value) + self.print('.var.%s := %s' % (name, self.global_vars[name])) + + def begin_build(self, out, iout, rule, in_, iin, orderdep): + if any(x in self.omit for x in out): + self.scope = Scope(self) + return + + super().begin_build(out, iout, rule, in_, iin, orderdep) + self.current_targets = ' '.join(self.scope.out + self.scope.iout).replace('$', '$$') + + def end_build(self, scope, out, iout, rule, in_, iin, orderdep): + self.rule_targets[rule] += self.scope.out + self.rule_targets[rule] += self.scope.iout + + self.all_outs.update(self.scope.iout) + self.all_outs.update(self.scope.out) + self.all_ins.update(self.scope.in_) + self.all_ins.update(self.scope.iin) + + targets = self.current_targets + self.current_targets = None + if rule == 'phony': + # Phony rules treat order-only dependencies as normal deps + self.print_phony(out + iout, in_ + iin + orderdep) + return + + inputs = ' '.join(in_ + iin).replace('$', '$$') + orderonly = ' '.join(orderdep).replace('$', '$$') + + rspfile = scope.expand('${rspfile}') + if rspfile: + rspfile_content = scope.expand('${rspfile_content}') + with open(rspfile, 'w') as f: + f.write(rspfile_content) + inputs += ' ' + rspfile + self.rspfiles.append(rspfile) + + restat = 'restat' in self.scope.build_vars or 'restat' in self.rule_vars[rule] + depfile = scope.expand('${depfile}') + build_vars = { + 'command': scope.expand('${command}'), + 'description': scope.expand('${description}'), + 'out': scope.expand('${out}') + } + + if restat and not depfile: + if len(out) == 1: + stamp = out[0] + '.stamp' + else: + stamp = '%s%d.stamp' %(rule, self.num_stamp[rule]) + self.num_stamp[rule] += 1 + self.print('%s: %s; @:' % (targets, stamp)) + self.print('%s: %s | %s; ${ninja-command-restat}' % (stamp, inputs, orderonly)) + self.rule_targets[rule].append(stamp) + self.stamp_targets[rule].append(stamp) + self.build_vars[stamp] = build_vars + else: + self.print('%s: %s | %s; ${ninja-command}' % (targets, inputs, orderonly)) + self.build_vars[targets] = build_vars + if depfile: + self.depfiles.append(depfile) + + def end_rule(self, scope, name): + # Note that the generator pseudo-variable could also be attached + # to a build block rather than a rule. This is not handled here + # in order to reduce the number of "rm" invocations. However, + # "ninjatool.py -t clean" does that correctly. + target = 'distclean' if scope.generator else 'clean' + self.print('ninja-%s:: ; $(if $V,,@)rm -f ${ninja-stamp-%s}' % (target, name)) + if self.emit_clean: + self.print('ninja-%s:: ; $(if $V,,@)rm -rf ${ninja-targets-%s}' % (target, name)) + + def default(self, targets): + self.print("ninja-default: " + ' '.join(targets)) + self.seen_default = True + + +# ---- command line parsing ---- + +# we cannot use subparsers because tools are chosen through the "-t" +# option. + +class ToolAction(argparse.Action): + def __init__(self, option_strings, dest, choices, metavar='TOOL', nargs=None, **kwargs): + if nargs is not None: + raise ValueError("nargs not allowed") + super().__init__(option_strings, dest, required=True, choices=choices, + metavar=metavar, **kwargs) + + def __call__(self, parser, namespace, value, option_string): + tool = self.choices[value] + setattr(namespace, self.dest, tool) + tool.ARGS.prog = '%s %s %s' % (parser.prog, option_string, value) + + +class ToolHelpAction(argparse.Action): + def __init__(self, option_strings, dest, nargs=None, **kwargs): + if nargs is not None: + raise ValueError("nargs not allowed") + super().__init__(option_strings, dest, nargs=0, **kwargs) + + def __call__(self, parser, namespace, values, option_string=None): + if namespace.tool: + namespace.tool.ARGS.print_help() + else: + parser.print_help() + parser.exit() + + +tools = { + 'test': Writer, + 'ninja2make': Ninja2Make, + 'compdb': Compdb, + 'clean': Clean, +} + +parser = argparse.ArgumentParser(description='Process and transform build.ninja files.', + add_help=False) +parser.add_argument('-C', metavar='DIR', dest='dir', default='.', + help='change to DIR before doing anything else') +parser.add_argument('-f', metavar='FILE', dest='file', default='build.ninja', + help='specify input build file [default=build.ninja]') +parser.add_argument('-n', dest='dry_run', action='store_true', + help='do not actually do anything') +parser.add_argument('-v', dest='verbose', action='store_true', + help='be more verbose') + +parser.add_argument('-t', dest='tool', choices=tools, action=ToolAction, + help='choose the tool to run') +parser.add_argument('-h', '--help', action=ToolHelpAction, + help='show this help message and exit') + +if len(sys.argv) >= 2 and sys.argv[1] == '--version': + print('1.8') + sys.exit(0) + +args, tool_args = parser.parse_known_args() +args.tool.ARGS.parse_args(tool_args, args) + +os.chdir(args.dir) +with open(args.file, 'r') as f: + parser = NinjaParser(args.file, f) + try: + events = args.tool(sys.stdout, parser, args) + except InvalidArgumentError as e: + parser.error(str(e)) + parser.parse(events) -- cgit v1.2.3-55-g7522 From fc9298928658485bf92fc8aaa782d26ca79aee6b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 13 Jul 2019 01:47:54 +0400 Subject: configure: generate Meson cross file Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- configure | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------- meson.build | 7 +++++- 2 files changed, 69 insertions(+), 10 deletions(-) diff --git a/configure b/configure index 26d571afca..958a0a4201 100755 --- a/configure +++ b/configure @@ -8630,21 +8630,75 @@ echo >> "$iotests_common_env" echo "export PYTHON='$python'" >> "$iotests_common_env" if test "$skip_meson" = no; then +cross="config-meson.cross.new" +meson_quote() { + echo "['$(echo $* | sed "s/ /','/g")']" +} + +echo "# Automatically generated by configure - do not modify" > $cross +echo "[properties]" >> $cross +test -z "$cxx" && echo "link_language = 'c'" >> $cross +echo "[binaries]" >> $cross +echo "c = $(meson_quote $cc)" >> $cross +test -n "$cxx" && echo "cpp = $(meson_quote $cxx)" >> $cross +echo "ar = $(meson_quote $ar)" >> $cross +echo "nm = $(meson_quote $nm)" >> $cross +echo "pkgconfig = $(meson_quote $pkg_config_exe)" >> $cross +echo "ranlib = $(meson_quote $ranlib)" >> $cross +echo "strip = $(meson_quote $strip)" >> $cross +echo "windres = $(meson_quote $windres)" >> $cross +if test -n "$cross_prefix"; then + cross_arg="--cross-file config-meson.cross" + # Hack: Meson expects an absolute path for the *build* machine + # for the prefix, so add a slash in front of a Windows path that + # includes a drive letter. + # + # See https://github.com/mesonbuild/meson/issues/7577. + echo "[host_machine]" >> $cross + if test "$mingw32" = "yes" ; then + echo "system = 'windows'" >> $cross + case $prefix in + ?:*) pre_prefix=/ ;; + esac + fi + case "$ARCH" in + i386|x86_64) + echo "cpu_family = 'x86'" >> $cross + ;; + ppc64le) + echo "cpu_family = 'ppc64'" >> $cross + ;; + *) + echo "cpu_family = '$ARCH'" >> $cross + ;; + esac + echo "cpu = '$cpu'" >> $cross + if test "$bigendian" = "yes" ; then + echo "endian = 'big'" >> $cross + else + echo "endian = 'little'" >> $cross + fi +else + cross_arg="--native-file config-meson.cross" +fi +mv $cross config-meson.cross + rm -rf meson-private meson-info meson-logs NINJA=$PWD/ninjatool $meson setup \ - --prefix "$prefix" \ - --libdir "$libdir" \ - --libexecdir "$libexecdir" \ - --bindir "$bindir" \ - --includedir "$includedir" \ - --datadir "$datadir" \ - --mandir "$mandir" \ - --sysconfdir "$sysconfdir" \ - --localstatedir "$local_statedir" \ + --prefix "${pre_prefix}$prefix" \ + --libdir "${pre_prefix}$libdir" \ + --libexecdir "${pre_prefix}$libexecdir" \ + --bindir "${pre_prefix}$bindir" \ + --includedir "${pre_prefix}$includedir" \ + --datadir "${pre_prefix}$datadir" \ + --mandir "${pre_prefix}$mandir" \ + --sysconfdir "${pre_prefix}$sysconfdir" \ + --localstatedir "${pre_prefix}$local_statedir" \ -Doptimization=$(if test "$debug" = yes; then echo 0; else echo 2; fi) \ -Ddebug=$(if test "$debug_info" = yes; then echo true; else echo false; fi) \ -Dwerror=$(if test "$werror" = yes; then echo true; else echo false; fi) \ -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \ + $cross_arg \ "$PWD" "$source_path" if test "$?" -ne 0 ; then diff --git a/meson.build b/meson.build index 613983e464..5ad85a7314 100644 --- a/meson.build +++ b/meson.build @@ -15,7 +15,12 @@ add_project_link_arguments(config_host['QEMU_LDFLAGS'].split(), add_project_arguments(config_host['QEMU_INCLUDES'].split(), language: ['c', 'cpp', 'objc']) -add_languages('cpp', required: false, native: false) +python = import('python').find_installation() + +link_language = meson.get_external_property('link_language', 'cpp') +if link_language == 'cpp' + add_languages('cpp', required: true, native: false) +endif if host_machine.system() == 'darwin' add_languages('objc', required: false, native: false) endif -- cgit v1.2.3-55-g7522 From 1f0a1d8a51968444b10d12a2882bc3ba16b45866 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 12:30:43 +0400 Subject: build-sys hack: link with whole .fa archives In order to link the *-obj-y files into tests, we will make static libraries of them in Meson, and then link them as whole archives into the tests. To separate regular static libraries from link-whole libraries, give them a different file extension. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- rules.mak | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/rules.mak b/rules.mak index e79a4005a7..5ab42def82 100644 --- a/rules.mak +++ b/rules.mak @@ -39,6 +39,13 @@ find-symbols = $(if $1, $(sort $(shell $(NM) -P -g $1 | $2))) defined-symbols = $(call find-symbols,$1,awk '$$2!="U"{print $$1}') undefined-symbols = $(call find-symbols,$1,awk '$$2=="U"{print $$1}') +WL := -Wl, +ifdef CONFIG_DARWIN +whole-archive = $(WL)-force_load,$1 +else +whole-archive = $(WL)--whole-archive $1 $(WL)--no-whole-archive +endif + # All the .mo objects in -m variables are also added into corresponding -y # variable in unnest-vars, but filtered out here, when LINK is called. # @@ -54,11 +61,12 @@ undefined-symbols = $(call find-symbols,$1,awk '$$2=="U"{print $$1}') # This is necessary because the exectuable itself may not use the function, in # which case the function would not be linked in. Then the DSO loading will # fail because of the missing symbol. -process-archive-undefs = $(filter-out %.a %.mo,$1) \ +process-archive-undefs = $(filter-out %.a %.fa %.mo,$1) \ $(addprefix $(WL_U), \ - $(filter $(call defined-symbols,$(filter %.a, $1)), \ + $(filter $(call defined-symbols,$(filter %.a %.fa, $1)), \ $(call undefined-symbols,$(filter %.mo,$1)))) \ - $(filter %.a,$1) + $(foreach l,$(filter %.fa,$1),$(call whole-archive,$l)) \ + $(filter %.a,$1) extract-libs = $(strip $(foreach o,$(filter-out %.mo,$1),$($o-libs))) expand-objs = $(strip $(sort $(filter %.o,$1)) \ @@ -122,7 +130,7 @@ LD_REL := $(CC) -nostdlib $(LD_REL_FLAGS) modules: %$(EXESUF): %.o - $(call LINK,$(filter %.o %.a %.mo, $^)) + $(call LINK,$(filter %.o %.a %.mo %.fa, $^)) %.a: $(call quiet-command,rm -f $@ && $(AR) rcs $@ $^,"AR","$(TARGET_DIR)$@") @@ -378,7 +386,7 @@ define unnest-vars $(error $o added in $v but $o-objs is not set))) $(shell mkdir -p ./ $(sort $(dir $($v)))) # Include all the .d files - $(eval -include $(patsubst %.o,%.d,$(patsubst %.mo,%.d,$($v)))) + $(eval -include $(patsubst %.o,%.d,$(patsubst %.mo,%.d,$(filter %.o,$($v))))) $(eval $v := $(filter-out %/,$($v)))) endef -- cgit v1.2.3-55-g7522 From 0a01d76fc12a90de870074a34040cc05fbde3765 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Wed, 21 Aug 2019 11:21:16 +0400 Subject: build-sys: add meson submodule Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- .gitmodules | 3 ++ configure | 71 ++++++++++++++++++++++++++++++++++++++++++----- meson | 1 + scripts/archive-source.sh | 3 +- 4 files changed, 70 insertions(+), 8 deletions(-) create mode 160000 meson diff --git a/.gitmodules b/.gitmodules index 9c0501a4d4..ce979398a8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -58,3 +58,6 @@ [submodule "roms/qboot"] path = roms/qboot url = https://github.com/bonzini/qboot +[submodule "meson"] + path = meson + url = https://github.com/mesonbuild/meson/ diff --git a/configure b/configure index 958a0a4201..a2c1159842 100755 --- a/configure +++ b/configure @@ -223,6 +223,25 @@ path_of() { return 1 } +version_ge () { + local_ver1=`echo $1 | tr . ' '` + local_ver2=`echo $2 | tr . ' '` + while true; do + set x $local_ver1 + local_first=${2-0} + # shift 2 does nothing if there are less than 2 arguments + shift; shift + local_ver1=$* + set x $local_ver2 + # the second argument finished, the first must be greater or equal + test $# = 1 && return 0 + test $local_first -lt $2 && return 1 + test $local_first -gt $2 && return 0 + shift; shift + local_ver2=$* + done +} + have_backend () { echo "$trace_backends" | grep "$1" >/dev/null } @@ -963,6 +982,7 @@ fi # python 2.x, but some distros have it as python 3.x, so # we check that too python= +explicit_python=no for binary in "${PYTHON-python3}" python do if has "$binary" @@ -1046,7 +1066,7 @@ for opt do ;; --install=*) install="$optarg" ;; - --python=*) python="$optarg" + --python=*) python="$optarg" ; explicit_python=yes ;; --sphinx-build=*) sphinx_build="$optarg" ;; @@ -2027,15 +2047,52 @@ python_version=$($python -c 'import sys; print("%d.%d.%d" % (sys.version_info[0] # Suppress writing compiled files python="$python -B" -if ! has "$meson" -then - error_exit "Meson not found. Use --meson=/path/to/meson" +if test -z "$meson"; then + if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.55.0; then + meson=meson + elif test -e "${source_path}/.git" && test $git_update = 'yes' ; then + meson=git + elif test -e "${source_path}/meson/meson.py" ; then + meson=internal + else + if test "$explicit_python" = yes; then + error_exit "--python requires using QEMU's embedded Meson distribution, but it was not found." + else + error_exit "Meson not found. Use --meson=/path/to/meson" + fi + fi +else + # Meson uses its own Python interpreter to invoke other Python scripts, + # but the user wants to use the one they specified with --python. + # + # We do not want to override the distro Python interpreter (and sometimes + # cannot: for example in Homebrew /usr/bin/meson is a bash script), so + # just require --meson=git|internal together with --python. + if test "$explicit_python" = yes; then + case "$meson" in + git | internal) ;; + *) error_exit "--python requires using QEMU's embedded Meson distribution." ;; + esac + fi fi -meson=$(command -v $meson) -if ! $python -c 'import pkg_resources' > /dev/null 2>&1; then - error_exit "Python setuptools not found" +if test "$meson" = git; then + git_submodules="${git_submodules} meson" fi +if test "$git_update" = yes; then + (cd "${source_path}" && GIT="$git" "./scripts/git-submodule.sh" update "$git_submodules") +fi + +case "$meson" in + git | internal) + if ! $python -c 'import pkg_resources' > /dev/null 2>&1; then + error_exit "Python setuptools not found" + fi + meson="$python ${source_path}/meson/meson.py" + ;; + *) meson=$(command -v meson) ;; +esac + # Check that the C compiler works. Doing this here before testing # the host CPU ensures that we had a valid CC to autodetect the diff --git a/meson b/meson new file mode 160000 index 0000000000..d0c68dc115 --- /dev/null +++ b/meson @@ -0,0 +1 @@ +Subproject commit d0c68dc11507a47b9b85de508e023d9590d60565 diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index fb5d6b3918..c6169db69f 100755 --- a/scripts/archive-source.sh +++ b/scripts/archive-source.sh @@ -26,7 +26,8 @@ sub_file="${sub_tdir}/submodule.tar" # independent of what the developer currently has initialized # in their checkout, because the build environment is completely # different to the host OS. -submodules="dtc slirp ui/keycodemapdb tests/fp/berkeley-softfloat-3 tests/fp/berkeley-testfloat-3" +submodules="dtc slirp meson ui/keycodemapdb" +submodules="$submodules tests/fp/berkeley-softfloat-3 tests/fp/berkeley-testfloat-3" sub_deinit="" function cleanup() { -- cgit v1.2.3-55-g7522 From f9332757898a764d85e19d339ec421236e885b68 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Feb 2020 13:28:38 +0100 Subject: meson: move summary to meson.build Signed-off-by: Paolo Bonzini --- configure | 237 ---------------------------------------------------------- meson.build | 245 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+), 237 deletions(-) diff --git a/configure b/configure index a2c1159842..f69280a273 100755 --- a/configure +++ b/configure @@ -574,8 +574,6 @@ libdaxctl="" meson="" skip_meson=no -supported_cpu="no" -supported_os="no" bogus_os="no" malloc_trim="" @@ -814,35 +812,27 @@ ARCH= # Note that this case should only have supported host CPUs, not guests. case "$cpu" in ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) - supported_cpu="yes" ;; ppc64le) ARCH="ppc64" - supported_cpu="yes" ;; i386|i486|i586|i686|i86pc|BePC) cpu="i386" - supported_cpu="yes" ;; x86_64|amd64) cpu="x86_64" - supported_cpu="yes" ;; armv*b|armv*l|arm) cpu="arm" - supported_cpu="yes" ;; aarch64) cpu="aarch64" - supported_cpu="yes" ;; mips*) cpu="mips" - supported_cpu="yes" ;; sparc|sun4[cdmuv]) cpu="sparc" - supported_cpu="yes" ;; *) # This will result in either an error or falling back to TCI later @@ -870,7 +860,6 @@ MINGW32*) audio_drv_list="" fi supported_os="yes" - pie="no" ;; GNU/kFreeBSD) bsd="yes" @@ -888,7 +877,6 @@ FreeBSD) libs_qga="-lutil $libs_qga" netmap="" # enable netmap autodetect HOST_VARIANT_DIR="freebsd" - supported_os="yes" ;; DragonFly) bsd="yes" @@ -905,7 +893,6 @@ NetBSD) audio_possible_drivers="oss sdl" oss_lib="-lossaudio" HOST_VARIANT_DIR="netbsd" - supported_os="yes" ;; OpenBSD) bsd="yes" @@ -913,7 +900,6 @@ OpenBSD) audio_drv_list="try-sdl" audio_possible_drivers="sdl" HOST_VARIANT_DIR="openbsd" - supported_os="yes" ;; Darwin) bsd="yes" @@ -934,7 +920,6 @@ Darwin) # won't work when we're compiling with gcc as a C compiler. QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" HOST_VARIANT_DIR="darwin" - supported_os="yes" ;; SunOS) solaris="yes" @@ -965,7 +950,6 @@ Linux) linux_user="yes" kvm="yes" QEMU_INCLUDES="-isystem ${source_path}/linux-headers -I$PWD/linux-headers $QEMU_INCLUDES" - supported_os="yes" libudev="yes" ;; esac @@ -5321,8 +5305,6 @@ EOF spice="yes" libs_softmmu="$libs_softmmu $spice_libs" QEMU_CFLAGS="$QEMU_CFLAGS $spice_cflags" - spice_protocol_version=$($pkg_config --modversion spice-protocol) - spice_server_version=$($pkg_config --modversion spice-server) else if test "$spice" = "yes" ; then feature_not_found "spice" \ @@ -6939,225 +6921,6 @@ QEMU_CFLAGS="$pixman_cflags $fdt_cflags $QEMU_CFLAGS" QEMU_LDFLAGS="$fdt_ldflags $QEMU_LDFLAGS" libs_softmmu="$pixman_libs $libs_softmmu" -echo "Install prefix $prefix" -echo "BIOS directory $(eval echo $qemu_datadir)" -echo "firmware path $(eval echo $firmwarepath)" -echo "binary directory $(eval echo $bindir)" -echo "library directory $(eval echo $libdir)" -echo "module directory $(eval echo $qemu_moddir)" -echo "libexec directory $(eval echo $libexecdir)" -echo "include directory $(eval echo $includedir)" -echo "config directory $(eval echo $sysconfdir)" -if test "$mingw32" = "no" ; then -echo "local state directory $(eval echo $local_statedir)" -echo "Manual directory $(eval echo $mandir)" -echo "ELF interp prefix $interp_prefix" -else -echo "local state directory queried at runtime" -echo "Windows SDK $win_sdk" -fi -echo "Build directory $(pwd)" -echo "Source path $source_path" -echo "GIT binary $git" -echo "GIT submodules $git_submodules" -echo "C compiler $cc" -echo "Host C compiler $host_cc" -echo "C++ compiler $cxx" -echo "Objective-C compiler $objcc" -echo "ARFLAGS $ARFLAGS" -echo "CFLAGS $CFLAGS" -echo "QEMU_CFLAGS $QEMU_CFLAGS" -echo "QEMU_LDFLAGS $QEMU_LDFLAGS" -echo "make $make" -echo "install $install" -echo "python $python ($python_version)" -if test "$docs" != "no"; then - echo "sphinx-build $sphinx_build" -fi -echo "genisoimage $genisoimage" -echo "slirp support $slirp $(echo_version $slirp $slirp_version)" -if test "$slirp" != "no" ; then - echo "smbd $smbd" -fi -echo "module support $modules" -echo "alt path mod load $module_upgrades" -echo "host CPU $cpu" -echo "host big endian $bigendian" -echo "target list $target_list" -echo "gprof enabled $gprof" -echo "sparse enabled $sparse" -echo "strip binaries $strip_opt" -echo "profiler $profiler" -echo "static build $static" -echo "safe stack $safe_stack" -if test "$darwin" = "yes" ; then - echo "Cocoa support $cocoa" -fi -echo "SDL support $sdl $(echo_version $sdl $sdlversion)" -echo "SDL image support $sdl_image" -echo "GTK support $gtk $(echo_version $gtk $gtk_version)" -echo "GTK GL support $gtk_gl" -echo "VTE support $vte $(echo_version $vte $vteversion)" -echo "TLS priority $tls_priority" -echo "GNUTLS support $gnutls" -echo "libgcrypt $gcrypt" -if test "$gcrypt" = "yes" -then - echo " hmac $gcrypt_hmac" - echo " XTS $gcrypt_xts" -fi -echo "nettle $nettle $(echo_version $nettle $nettle_version)" -if test "$nettle" = "yes" -then - echo " XTS $nettle_xts" -fi -echo "libtasn1 $tasn1" -echo "PAM $auth_pam" -echo "iconv support $iconv" -echo "curses support $curses" -echo "virgl support $virglrenderer $(echo_version $virglrenderer $virgl_version)" -echo "curl support $curl" -echo "mingw32 support $mingw32" -echo "Audio drivers $audio_drv_list" -echo "Block whitelist (rw) $block_drv_rw_whitelist" -echo "Block whitelist (ro) $block_drv_ro_whitelist" -echo "VirtFS support $virtfs" -echo "Multipath support $mpath" -echo "VNC support $vnc" -if test "$vnc" = "yes" ; then - echo "VNC SASL support $vnc_sasl" - echo "VNC JPEG support $vnc_jpeg" - echo "VNC PNG support $vnc_png" -fi -echo "xen support $xen" -if test "$xen" = "yes" ; then - echo "xen ctrl version $xen_ctrl_version" -fi -echo "brlapi support $brlapi" -echo "Documentation $docs" -echo "PIE $pie" -echo "vde support $vde" -echo "netmap support $netmap" -echo "Linux AIO support $linux_aio" -echo "Linux io_uring support $linux_io_uring" -echo "ATTR/XATTR support $attr" -echo "Install blobs $blobs" -echo "KVM support $kvm" -echo "HAX support $hax" -echo "HVF support $hvf" -echo "WHPX support $whpx" -echo "TCG support $tcg" -if test "$tcg" = "yes" ; then - echo "TCG debug enabled $debug_tcg" - echo "TCG interpreter $tcg_interpreter" -fi -echo "malloc trim support $malloc_trim" -echo "RDMA support $rdma" -echo "PVRDMA support $pvrdma" -echo "fdt support $fdt" -echo "membarrier $membarrier" -echo "preadv support $preadv" -echo "fdatasync $fdatasync" -echo "madvise $madvise" -echo "posix_madvise $posix_madvise" -echo "posix_memalign $posix_memalign" -echo "libcap-ng support $cap_ng" -echo "vhost-net support $vhost_net" -echo "vhost-crypto support $vhost_crypto" -echo "vhost-scsi support $vhost_scsi" -echo "vhost-vsock support $vhost_vsock" -echo "vhost-user support $vhost_user" -echo "vhost-user-fs support $vhost_user_fs" -echo "vhost-vdpa support $vhost_vdpa" -echo "Trace backends $trace_backends" -if have_backend "simple"; then -echo "Trace output file $trace_file-" -fi -echo "spice support $spice $(echo_version $spice $spice_protocol_version/$spice_server_version)" -echo "rbd support $rbd" -echo "xfsctl support $xfs" -echo "smartcard support $smartcard" -echo "libusb $libusb" -echo "usb net redir $usb_redir" -echo "OpenGL support $opengl" -echo "OpenGL dmabufs $opengl_dmabuf" -echo "libiscsi support $libiscsi" -echo "libnfs support $libnfs" -echo "build guest agent $guest_agent" -echo "QGA VSS support $guest_agent_with_vss" -echo "QGA w32 disk info $guest_agent_ntddscsi" -echo "QGA MSI support $guest_agent_msi" -echo "seccomp support $seccomp" -echo "coroutine backend $coroutine" -echo "coroutine pool $coroutine_pool" -echo "debug stack usage $debug_stack_usage" -echo "mutex debugging $debug_mutex" -echo "crypto afalg $crypto_afalg" -echo "GlusterFS support $glusterfs" -echo "gcov $gcov_tool" -echo "gcov enabled $gcov" -echo "TPM support $tpm" -echo "libssh support $libssh" -echo "QOM debugging $qom_cast_debug" -echo "Live block migration $live_block_migration" -echo "lzo support $lzo" -echo "snappy support $snappy" -echo "bzip2 support $bzip2" -echo "lzfse support $lzfse" -echo "zstd support $zstd" -echo "NUMA host support $numa" -echo "libxml2 $libxml2" -echo "tcmalloc support $tcmalloc" -echo "jemalloc support $jemalloc" -echo "avx2 optimization $avx2_opt" -echo "avx512f optimization $avx512f_opt" -echo "replication support $replication" -echo "bochs support $bochs" -echo "cloop support $cloop" -echo "dmg support $dmg" -echo "qcow v1 support $qcow1" -echo "vdi support $vdi" -echo "vvfat support $vvfat" -echo "qed support $qed" -echo "parallels support $parallels" -echo "sheepdog support $sheepdog" -echo "capstone $capstone" -echo "libpmem support $libpmem" -echo "libdaxctl support $libdaxctl" -echo "libudev $libudev" -echo "default devices $default_devices" -echo "plugin support $plugins" -echo "fuzzing support $fuzzing" -echo "gdb $gdb_bin" -echo "rng-none $rng_none" -echo "Linux keyring $secret_keyring" - -if test "$supported_cpu" = "no"; then - echo - echo "WARNING: SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES!" - echo - echo "CPU host architecture $cpu support is not currently maintained." - echo "The QEMU project intends to remove support for this host CPU in" - echo "a future release if nobody volunteers to maintain it and to" - echo "provide a build host for our continuous integration setup." - echo "configure has succeeded and you can continue to build, but" - echo "if you care about QEMU on this platform you should contact" - echo "us upstream at qemu-devel@nongnu.org." -fi - -if test "$supported_os" = "no"; then - echo - echo "WARNING: SUPPORT FOR THIS HOST OS WILL GO AWAY IN FUTURE RELEASES!" - echo - echo "Host OS $targetos support is not currently maintained." - echo "The QEMU project intends to remove support for this host OS in" - echo "a future release if nobody volunteers to maintain it and to" - echo "provide a build host for our continuous integration setup." - echo "configure has succeeded and you can continue to build, but" - echo "if you care about QEMU on this platform you should contact" - echo "us upstream at qemu-devel@nongnu.org." -fi - config_host_mak="config-host.mak" echo "# Automatically generated by configure - do not modify" >config-all-disas.mak diff --git a/meson.build b/meson.build index 5ad85a7314..c47cd74571 100644 --- a/meson.build +++ b/meson.build @@ -28,3 +28,248 @@ endif configure_file(input: files('scripts/ninjatool.py'), output: 'ninjatool', configuration: config_host) + +supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] +supported_cpus = ['ppc', 'ppc64', 's390x', 'sparc64', 'riscv32', 'riscv64', 'x86', 'x86_64', + 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] + +cpu = host_machine.cpu_family() +targetos = host_machine.system() + +summary_info = {} +summary_info += {'Install prefix': config_host['prefix']} +summary_info += {'BIOS directory': config_host['qemu_datadir']} +summary_info += {'firmware path': config_host['qemu_firmwarepath']} +summary_info += {'binary directory': config_host['bindir']} +summary_info += {'library directory': config_host['libdir']} +summary_info += {'module directory': config_host['qemu_moddir']} +summary_info += {'libexec directory': config_host['libexecdir']} +summary_info += {'include directory': config_host['includedir']} +summary_info += {'config directory': config_host['sysconfdir']} +if targetos != 'windows' + summary_info += {'local state directory': config_host['qemu_localstatedir']} + summary_info += {'Manual directory': config_host['mandir']} +else + summary_info += {'local state directory': 'queried at runtime'} +endif +summary_info += {'Build directory': meson.current_build_dir()} +summary_info += {'Source path': meson.current_source_dir()} +summary_info += {'GIT binary': config_host['GIT']} +summary_info += {'GIT submodules': config_host['GIT_SUBMODULES']} +summary_info += {'C compiler': meson.get_compiler('c').cmd_array()[0]} +summary_info += {'Host C compiler': meson.get_compiler('c', native: true).cmd_array()[0]} +if link_language == 'cpp' + summary_info += {'C++ compiler': meson.get_compiler('cpp').cmd_array()[0]} +else + summary_info += {'C++ compiler': false} +endif +if targetos == 'darwin' + summary_info += {'Objective-C compiler': meson.get_compiler('objc').cmd_array()[0]} +endif +summary_info += {'ARFLAGS': config_host['ARFLAGS']} +summary_info += {'CFLAGS': config_host['CFLAGS']} +summary_info += {'QEMU_CFLAGS': config_host['QEMU_CFLAGS']} +summary_info += {'QEMU_LDFLAGS': config_host['QEMU_LDFLAGS']} +summary_info += {'make': config_host['MAKE']} +summary_info += {'install': config_host['INSTALL']} +summary_info += {'python': '@0@ (version: @1@)'.format(python.full_path(), python.language_version())} +summary_info += {'sphinx-build': config_host['SPHINX_BUILD']} +summary_info += {'genisoimage': config_host['GENISOIMAGE']} +# TODO: add back version +summary_info += {'slirp support': config_host.has_key('CONFIG_SLIRP')} +if config_host.has_key('CONFIG_SLIRP') + summary_info += {'smbd': config_host['CONFIG_SMBD_COMMAND']} +endif +summary_info += {'module support': config_host.has_key('CONFIG_MODULES')} +if config_host.has_key('CONFIG_MODULES') + summary_info += {'alternative module path': config_host.has_key('CONFIG_MODULE_UPGRADES')} +endif +summary_info += {'host CPU': cpu} +summary_info += {'host endianness': build_machine.endian()} +summary_info += {'target list': config_host['TARGET_DIRS']} +summary_info += {'gprof enabled': config_host.has_key('CONFIG_GPROF')} +summary_info += {'sparse enabled': meson.get_compiler('c').cmd_array().contains('cgcc')} +summary_info += {'strip binaries': get_option('strip')} +summary_info += {'profiler': config_host.has_key('CONFIG_PROFILER')} +summary_info += {'static build': config_host.has_key('CONFIG_TOOLS')} +if targetos == 'darwin' + summary_info += {'Cocoa support': config_host.has_key('CONFIG_COCOA')} +endif +# TODO: add back version +summary_info += {'SDL support': config_host.has_key('CONFIG_SDL')} +summary_info += {'SDL image support': config_host.has_key('CONFIG_SDL_IMAGE')} +# TODO: add back version +summary_info += {'GTK support': config_host.has_key('CONFIG_GTK')} +summary_info += {'GTK GL support': config_host.has_key('CONFIG_GTK_GL')} +# TODO: add back version +summary_info += {'VTE support': config_host.has_key('CONFIG_VTE')} +summary_info += {'TLS priority': config_host['CONFIG_TLS_PRIORITY']} +summary_info += {'GNUTLS support': config_host.has_key('CONFIG_GNUTLS')} +# TODO: add back version +summary_info += {'libgcrypt': config_host.has_key('CONFIG_GCRYPT')} +if config_host.has_key('CONFIG_GCRYPT') + summary_info += {' hmac': config_host.has_key('CONFIG_GCRYPT_HMAC')} + summary_info += {' XTS': not config_host.has_key('CONFIG_QEMU_PRIVATE_XTS')} +endif +# TODO: add back version +summary_info += {'nettle': config_host.has_key('CONFIG_NETTLE')} +if config_host.has_key('CONFIG_NETTLE') + summary_info += {' XTS': not config_host.has_key('CONFIG_QEMU_PRIVATE_XTS')} +endif +summary_info += {'libtasn1': config_host.has_key('CONFIG_TASN1')} +summary_info += {'PAM': config_host.has_key('CONFIG_AUTH_PAM')} +summary_info += {'iconv support': config_host.has_key('CONFIG_ICONV')} +summary_info += {'curses support': config_host.has_key('CONFIG_CURSES')} +# TODO: add back version +summary_info += {'virgl support': config_host.has_key('CONFIG_VIRGL')} +summary_info += {'curl support': config_host.has_key('CONFIG_CURL')} +summary_info += {'mingw32 support': targetos == 'windows'} +summary_info += {'Audio drivers': config_host['CONFIG_AUDIO_DRIVERS']} +summary_info += {'Block whitelist (rw)': config_host['CONFIG_BDRV_RW_WHITELIST']} +summary_info += {'Block whitelist (ro)': config_host['CONFIG_BDRV_RO_WHITELIST']} +summary_info += {'VirtFS support': config_host.has_key('CONFIG_VIRTFS')} +summary_info += {'Multipath support': config_host.has_key('CONFIG_MPATH')} +summary_info += {'VNC support': config_host.has_key('CONFIG_VNC')} +if config_host.has_key('CONFIG_VNC') + summary_info += {'VNC SASL support': config_host.has_key('CONFIG_VNC_SASL')} + summary_info += {'VNC JPEG support': config_host.has_key('CONFIG_VNC_JPEG')} + summary_info += {'VNC PNG support': config_host.has_key('CONFIG_VNC_PNG')} +endif +summary_info += {'xen support': config_host.has_key('CONFIG_XEN_BACKEND')} +if config_host.has_key('CONFIG_XEN_BACKEND') + summary_info += {'xen ctrl version': config_host['CONFIG_XEN_CTRL_INTERFACE_VERSION']} +endif +summary_info += {'brlapi support': config_host.has_key('CONFIG_BRLAPI')} +summary_info += {'Documentation': config_host.has_key('BUILD_DOCS')} +summary_info += {'PIE': get_option('b_pie')} +summary_info += {'vde support': config_host.has_key('CONFIG_VDE')} +summary_info += {'netmap support': config_host.has_key('CONFIG_NETMAP')} +summary_info += {'Linux AIO support': config_host.has_key('CONFIG_LINUX_AIO')} +summary_info += {'Linux io_uring support': config_host.has_key('CONFIG_LINUX_IO_URING')} +summary_info += {'ATTR/XATTR support': config_host.has_key('CONFIG_ATTR')} +summary_info += {'Install blobs': config_host.has_key('INSTALL_BLOBS')} +# TODO: add back KVM/HAX/HVF/WHPX/TCG +#summary_info += {'KVM support': have_kvm'} +#summary_info += {'HAX support': have_hax'} +#summary_info += {'HVF support': have_hvf'} +#summary_info += {'WHPX support': have_whpx'} +#summary_info += {'TCG support': have_tcg'} +#if get_option('tcg') +# summary_info += {'TCG debug enabled': config_host.has_key('CONFIG_DEBUG_TCG')} +# summary_info += {'TCG interpreter': config_host.has_key('CONFIG_TCG_INTERPRETER')} +#endif +summary_info += {'malloc trim support': config_host.has_key('CONFIG_MALLOC_TRIM')} +summary_info += {'RDMA support': config_host.has_key('CONFIG_RDMA')} +summary_info += {'PVRDMA support': config_host.has_key('CONFIG_PVRDMA')} +summary_info += {'fdt support': config_host.has_key('CONFIG_FDT')} +summary_info += {'membarrier': config_host.has_key('CONFIG_MEMBARRIER')} +summary_info += {'preadv support': config_host.has_key('CONFIG_PREADV')} +summary_info += {'fdatasync': config_host.has_key('CONFIG_FDATASYNC')} +summary_info += {'madvise': config_host.has_key('CONFIG_MADVISE')} +summary_info += {'posix_madvise': config_host.has_key('CONFIG_POSIX_MADVISE')} +summary_info += {'posix_memalign': config_host.has_key('CONFIG_POSIX_MEMALIGN')} +summary_info += {'libcap-ng support': config_host.has_key('CONFIG_LIBCAP_NG')} +summary_info += {'vhost-net support': config_host.has_key('CONFIG_VHOST_NET')} +summary_info += {'vhost-crypto support': config_host.has_key('CONFIG_VHOST_CRYPTO')} +summary_info += {'vhost-scsi support': config_host.has_key('CONFIG_VHOST_SCSI')} +summary_info += {'vhost-vsock support': config_host.has_key('CONFIG_VHOST_VSOCK')} +summary_info += {'vhost-user support': config_host.has_key('CONFIG_VHOST_KERNEL')} +summary_info += {'vhost-user-fs support': config_host.has_key('CONFIG_VHOST_USER_FS')} +summary_info += {'vhost-vdpa support': config_host.has_key('CONFIG_VHOST_VDPA')} +summary_info += {'Trace backends': config_host['TRACE_BACKENDS']} +if config_host['TRACE_BACKENDS'].split().contains('simple') + summary_info += {'Trace output file': config_host['CONFIG_TRACE_FILE'] + '-'} +endif +# TODO: add back protocol and server version +summary_info += {'spice support': config_host.has_key('CONFIG_SPICE')} +summary_info += {'rbd support': config_host.has_key('CONFIG_RBD')} +summary_info += {'xfsctl support': config_host.has_key('CONFIG_XFS')} +summary_info += {'smartcard support': config_host.has_key('CONFIG_SMARTCARD')} +summary_info += {'libusb': config_host.has_key('CONFIG_USB_LIBUSB')} +summary_info += {'usb net redir': config_host.has_key('CONFIG_USB_REDIR')} +summary_info += {'OpenGL support': config_host.has_key('CONFIG_OPENGL')} +summary_info += {'OpenGL dmabufs': config_host.has_key('CONFIG_OPENGL_DMABUF')} +summary_info += {'libiscsi support': config_host.has_key('CONFIG_LIBISCSI')} +summary_info += {'libnfs support': config_host.has_key('CONFIG_LIBNFS')} +summary_info += {'build guest agent': config_host.has_key('CONFIG_GUEST_AGENT')} +if targetos == 'windows' + if 'WIN_SDK' in config_host + summary_info += {'Windows SDK': config_host['WIN_SDK']} + endif + summary_info += {'QGA VSS support': config_host.has_key('CONFIG_QGA_VSS')} + summary_info += {'QGA w32 disk info': config_host.has_key('CONFIG_QGA_NTDDSCSI')} + summary_info += {'QGA MSI support': config_host.has_key('CONFIG_QGA_MSI_ENABLED')} +endif +summary_info += {'seccomp support': config_host.has_key('CONFIG_SECCOMP')} +summary_info += {'coroutine backend': config_host['CONFIG_COROUTINE_BACKEND']} +summary_info += {'coroutine pool': config_host['CONFIG_COROUTINE_POOL'] == '1'} +summary_info += {'debug stack usage': config_host.has_key('CONFIG_DEBUG_STACK_USAGE')} +summary_info += {'mutex debugging': config_host.has_key('CONFIG_DEBUG_MUTEX')} +summary_info += {'crypto afalg': config_host.has_key('CONFIG_AF_ALG')} +summary_info += {'GlusterFS support': config_host.has_key('CONFIG_GLUSTERFS')} +summary_info += {'gcov': config_host.has_key('CONFIG_GCOV')} +summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')} +summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')} +summary_info += {'QOM debugging': config_host.has_key('CONFIG_QOM_CAST_DEBUG')} +summary_info += {'Live block migration': config_host.has_key('CONFIG_LIVE_BLOCK_MIGRATION')} +summary_info += {'lzo support': config_host.has_key('CONFIG_LZO')} +summary_info += {'snappy support': config_host.has_key('CONFIG_SNAPPY')} +summary_info += {'bzip2 support': config_host.has_key('CONFIG_BZIP2')} +summary_info += {'lzfse support': config_host.has_key('CONFIG_LZFSE')} +summary_info += {'zstd support': config_host.has_key('CONFIG_ZSTD')} +summary_info += {'NUMA host support': config_host.has_key('CONFIG_NUMA')} +summary_info += {'libxml2': config_host.has_key('CONFIG_LIBXML2')} +summary_info += {'tcmalloc support': config_host.has_key('CONFIG_TCMALLOC')} +summary_info += {'jemalloc support': config_host.has_key('CONFIG_JEMALLOC')} +summary_info += {'avx2 optimization': config_host.has_key('CONFIG_AVX2_OPT')} +summary_info += {'avx512f optimization': config_host.has_key('CONFIG_AVX512F_OPT')} +summary_info += {'replication support': config_host.has_key('CONFIG_REPLICATION')} +summary_info += {'bochs support': config_host.has_key('CONFIG_BOCHS')} +summary_info += {'cloop support': config_host.has_key('CONFIG_CLOOP')} +summary_info += {'dmg support': config_host.has_key('CONFIG_DMG')} +summary_info += {'qcow v1 support': config_host.has_key('CONFIG_QCOW1')} +summary_info += {'vdi support': config_host.has_key('CONFIG_VDI')} +summary_info += {'vvfat support': config_host.has_key('CONFIG_VVFAT')} +summary_info += {'qed support': config_host.has_key('CONFIG_QED')} +summary_info += {'parallels support': config_host.has_key('CONFIG_PARALLELS')} +summary_info += {'sheepdog support': config_host.has_key('CONFIG_SHEEPDOG')} +summary_info += {'capstone': config_host.has_key('CONFIG_CAPSTONE')} +summary_info += {'libpmem support': config_host.has_key('CONFIG_LIBPMEM')} +summary_info += {'libdaxctl support': config_host.has_key('CONFIG_LIBDAXCTL')} +summary_info += {'libudev': config_host.has_key('CONFIG_LIBUDEV')} +summary_info += {'default devices': config_host['CONFIG_MINIKCONF_MODE'] == '--defconfig'} +summary_info += {'plugin support': config_host.has_key('CONFIG_PLUGIN')} +summary_info += {'fuzzing support': config_host.has_key('CONFIG_FUZZ')} +if config_host.has_key('HAVE_GDB_BIN') + summary_info += {'gdb': config_host['HAVE_GDB_BIN']} +endif +summary_info += {'thread sanitizer': config_host.has_key('CONFIG_TSAN')} +summary_info += {'rng-none': config_host.has_key('CONFIG_RNG_NONE')} +summary_info += {'Linux keyring': config_host.has_key('CONFIG_SECRET_KEYRING')} +summary(summary_info, bool_yn: true) + +if not supported_cpus.contains(cpu) + message() + warning('SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES!') + message() + message('CPU host architecture ' + cpu + ' support is not currently maintained.') + message('The QEMU project intends to remove support for this host CPU in') + message('a future release if nobody volunteers to maintain it and to') + message('provide a build host for our continuous integration setup.') + message('configure has succeeded and you can continue to build, but') + message('if you care about QEMU on this platform you should contact') + message('us upstream at qemu-devel@nongnu.org.') +endif + +if not supported_oses.contains(targetos) + message() + warning('WARNING: SUPPORT FOR THIS HOST OS WILL GO AWAY IN FUTURE RELEASES!') + message() + message('Host OS ' + targetos + 'support is not currently maintained.') + message('The QEMU project intends to remove support for this host OS in') + message('a future release if nobody volunteers to maintain it and to') + message('provide a build host for our continuous integration setup.') + message('configure has succeeded and you can continue to build, but') + message('if you care about QEMU on this platform you should contact') + message('us upstream at qemu-devel@nongnu.org.') +endif -- cgit v1.2.3-55-g7522 From da6d48b969b9fe8f842434375a817db02d158973 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 17 Sep 2019 15:39:36 +0400 Subject: meson: enable pie Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- configure | 1 + 1 file changed, 1 insertion(+) diff --git a/configure b/configure index f69280a273..5eb1fb59e2 100755 --- a/configure +++ b/configure @@ -8518,6 +8518,7 @@ NINJA=$PWD/ninjatool $meson setup \ -Ddebug=$(if test "$debug_info" = yes; then echo true; else echo false; fi) \ -Dwerror=$(if test "$werror" = yes; then echo true; else echo false; fi) \ -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \ + -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \ $cross_arg \ "$PWD" "$source_path" -- cgit v1.2.3-55-g7522 From bf0e56a3ca7b6ede730ec754a95aee7f95815735 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 4 Oct 2019 17:35:16 +0400 Subject: meson: use coverage option Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 14 -------------- Makefile.target | 16 ---------------- configure | 9 ++------- docs/devel/testing.rst | 7 +++---- meson.build | 2 +- 5 files changed, 6 insertions(+), 42 deletions(-) diff --git a/Makefile b/Makefile index b726e7d8d2..ba8413d809 100644 --- a/Makefile +++ b/Makefile @@ -777,14 +777,6 @@ module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ "GEN","$@") -ifdef CONFIG_GCOV -.PHONY: clean-coverage -clean-coverage: - $(call quiet-command, \ - find . \( -name '*.gcda' -o -name '*.gcov' \) -type f -exec rm {} +, \ - "CLEAN", "coverage files") -endif - clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files @@ -1291,9 +1283,6 @@ endif echo '') @echo 'Cleaning targets:' $(call print-help,clean,Remove most generated files but keep the config) -ifdef CONFIG_GCOV - $(call print-help,clean-coverage,Remove coverage files) -endif $(call print-help,distclean,Remove all generated files) $(call print-help,dist,Build a distributable tarball) @echo '' @@ -1304,9 +1293,6 @@ endif @echo '' @echo 'Documentation targets:' $(call print-help,html info pdf txt,Build documentation in specified format) -ifdef CONFIG_GCOV - $(call print-help,coverage-report,Create code coverage report) -endif @echo '' ifdef CONFIG_WIN32 @echo 'Windows targets:' diff --git a/Makefile.target b/Makefile.target index ffa2657269..d61a6a978b 100644 --- a/Makefile.target +++ b/Makefile.target @@ -269,19 +269,3 @@ endif generated-files-y += config-target.h Makefile: $(generated-files-y) - -# Reports/Analysis -# -# The target specific coverage report only cares about target specific -# blobs and not the shared code. -# - -%/coverage-report.html: - @mkdir -p $* - $(call quiet-command,\ - gcovr -r $(SRC_PATH) --object-directory $(CURDIR) \ - -p --html --html-details -o $@, \ - "GEN", "coverage-report.html") - -.PHONY: coverage-report -coverage-report: $(CURDIR)/reports/coverage/coverage-report.html diff --git a/configure b/configure index 5eb1fb59e2..41d3b973b4 100755 --- a/configure +++ b/configure @@ -470,7 +470,6 @@ tcg_interpreter="no" bigendian="no" mingw32="no" gcov="no" -gcov_tool="gcov" EXESUF="" DSOSUF=".so" LDFLAGS_SHARED="-shared" @@ -1058,8 +1057,6 @@ for opt do ;; --meson=*) meson="$optarg" ;; - --gcov=*) gcov_tool="$optarg" - ;; --smbd=*) smbd="$optarg" ;; --extra-cflags=*) @@ -1866,7 +1863,6 @@ Advanced options (experts only): --with-coroutine=BACKEND coroutine backend. Supported options: ucontext, sigaltstack, windows --enable-gcov enable test coverage analysis with gcov - --gcov=GCOV use specified gcov [$gcov_tool] --disable-blobs disable installing provided firmware blobs --with-vss-sdk=SDK-path enable Windows VSS support in QEMU Guest Agent --with-win-sdk=SDK-path path to Windows Platform SDK (to build VSS .tlb) @@ -6600,8 +6596,7 @@ fi write_c_skeleton if test "$gcov" = "yes" ; then - QEMU_CFLAGS="-fprofile-arcs -ftest-coverage -g $QEMU_CFLAGS" - QEMU_LDFLAGS="-fprofile-arcs -ftest-coverage $QEMU_LDFLAGS" + : elif test "$fortify_source" = "yes" ; then QEMU_CFLAGS="-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $QEMU_CFLAGS" debug=no @@ -7886,7 +7881,6 @@ echo "TASN1_CFLAGS=$tasn1_cflags" >> $config_host_mak echo "POD2MAN=$POD2MAN" >> $config_host_mak if test "$gcov" = "yes" ; then echo "CONFIG_GCOV=y" >> $config_host_mak - echo "GCOV=$gcov_tool" >> $config_host_mak fi if test "$libudev" != "no"; then @@ -8519,6 +8513,7 @@ NINJA=$PWD/ninjatool $meson setup \ -Dwerror=$(if test "$werror" = yes; then echo true; else echo false; fi) \ -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \ -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \ + -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; fi) \ $cross_arg \ "$PWD" "$source_path" diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index c1ff24370b..a4264691be 100644 --- a/docs/devel/testing.rst +++ b/docs/devel/testing.rst @@ -164,13 +164,12 @@ instrumenting the tested code. To use it, configure QEMU with ``--enable-gcov`` option and build. Then run ``make check`` as usual. If you want to gather coverage information on a single test the ``make -clean-coverage`` target can be used to delete any existing coverage +clean-gcda`` target can be used to delete any existing coverage information before running a single test. You can generate a HTML coverage report by executing ``make -coverage-report`` which will create -./reports/coverage/coverage-report.html. If you want to create it -elsewhere simply execute ``make /foo/bar/baz/coverage-report.html``. +coverage-html`` which will create +``meson-logs/coveragereport/index.html``. Further analysis can be conducted by running the ``gcov`` command directly on the various .gcda output files. Please read the ``gcov`` diff --git a/meson.build b/meson.build index c47cd74571..1a56ac8b26 100644 --- a/meson.build +++ b/meson.build @@ -207,7 +207,7 @@ summary_info += {'debug stack usage': config_host.has_key('CONFIG_DEBUG_STACK_US summary_info += {'mutex debugging': config_host.has_key('CONFIG_DEBUG_MUTEX')} summary_info += {'crypto afalg': config_host.has_key('CONFIG_AF_ALG')} summary_info += {'GlusterFS support': config_host.has_key('CONFIG_GLUSTERFS')} -summary_info += {'gcov': config_host.has_key('CONFIG_GCOV')} +summary_info += {'gcov': get_option('b_coverage')} summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')} summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')} summary_info += {'QOM debugging': config_host.has_key('CONFIG_QOM_CAST_DEBUG')} -- cgit v1.2.3-55-g7522 From 968b4db38a717d334db9298fb7b6f6ba71d08806 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Feb 2020 14:45:33 +0100 Subject: meson: add sparse support Do not use cgcc; instead, extract compilation commands from compile_commands.json and invoke sparse directly. Signed-off-by: Paolo Bonzini --- Makefile | 1 + configure | 8 ++------ meson.build | 7 +++++++ scripts/check_sparse.py | 25 +++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 6 deletions(-) create mode 100644 scripts/check_sparse.py diff --git a/Makefile b/Makefile index ba8413d809..81c9642a30 100644 --- a/Makefile +++ b/Makefile @@ -1261,6 +1261,7 @@ endif $(call print-help,install,Install QEMU, documentation and tools) $(call print-help,ctags/TAGS,Generate tags file for editors) $(call print-help,cscope,Generate cscope index) + $(call print-help,sparse,Run sparse on the QEMU source) @echo '' @$(if $(TARGET_DIRS), \ echo 'Architecture specific targets:'; \ diff --git a/configure b/configure index 41d3b973b4..79bcf8a681 100755 --- a/configure +++ b/configure @@ -3058,7 +3058,7 @@ fi ########################################## # Sparse probe if test "$sparse" != "no" ; then - if has cgcc; then + if has sparse; then sparse=yes else if test "$sparse" = "yes" ; then @@ -7859,11 +7859,7 @@ echo "QEMU_CFLAGS=$QEMU_CFLAGS" >> $config_host_mak echo "QEMU_CXXFLAGS=$QEMU_CXXFLAGS" >> $config_host_mak echo "QEMU_INCLUDES=$QEMU_INCLUDES" >> $config_host_mak if test "$sparse" = "yes" ; then - echo "CC := REAL_CC=\"\$(CC)\" cgcc" >> $config_host_mak - echo "CPP := REAL_CC=\"\$(CPP)\" cgcc" >> $config_host_mak - echo "CXX := REAL_CC=\"\$(CXX)\" cgcc" >> $config_host_mak - echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak - echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak + echo "SPARSE_CFLAGS = -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak fi echo "QEMU_LDFLAGS=$QEMU_LDFLAGS" >> $config_host_mak echo "LDFLAGS_NOPIE=$LDFLAGS_NOPIE" >> $config_host_mak diff --git a/meson.build b/meson.build index 1a56ac8b26..86219e500a 100644 --- a/meson.build +++ b/meson.build @@ -25,6 +25,13 @@ if host_machine.system() == 'darwin' add_languages('objc', required: false, native: false) endif +if 'SPARSE_CFLAGS' in config_host + run_target('sparse', + command: [find_program('scripts/check_sparse.py'), + config_host['SPARSE_CFLAGS'].split(), + 'compile_commands.json']) +endif + configure_file(input: files('scripts/ninjatool.py'), output: 'ninjatool', configuration: config_host) diff --git a/scripts/check_sparse.py b/scripts/check_sparse.py new file mode 100644 index 0000000000..0de7aa55d9 --- /dev/null +++ b/scripts/check_sparse.py @@ -0,0 +1,25 @@ +#! /usr/bin/env python3 + +# Invoke sparse based on the contents of compile_commands.json + +import json +import subprocess +import sys +import shlex + +def extract_cflags(shcmd): + cflags = shlex.split(shcmd) + return [x for x in cflags + if x.startswith('-D') or x.startswith('-I') or x.startswith('-W') + or x.startswith('-std=')] + +cflags = sys.argv[1:-1] +with open(sys.argv[-1], 'r') as fd: + compile_commands = json.load(fd) + +for cmd in compile_commands: + cmd = ['sparse'] + cflags + extract_cflags(cmd['command']) + [cmd['file']] + print(' '.join((shlex.quote(x) for x in cmd))) + r = subprocess.run(cmd) + if r.returncode != 0: + sys.exit(r.returncode) -- cgit v1.2.3-55-g7522 From 245dac4a1bef719d648e20c84bbf3dcaf50de988 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 28 Jan 2020 14:48:54 +0100 Subject: meson: add testsuite Makefile generator Rules to execute tests are generated by a simple Python program that integrates into the existing "make check" mechanism. This provides familiarity for developers, and also allows piecewise conversion of the testsuite Makefiles to meson. The generated rules are based on QEMU's existing test harness Makefile and TAP parser. Signed-off-by: Paolo Bonzini --- Makefile | 10 ++++- scripts/mtest2make.py | 102 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/Makefile.include | 1 - 3 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 scripts/mtest2make.py diff --git a/Makefile b/Makefile index 81c9642a30..5f9aae6e3e 100644 --- a/Makefile +++ b/Makefile @@ -68,6 +68,14 @@ Makefile.ninja: build.ninja ninjatool ${ninja-targets-c_COMPILER} ${ninja-targets-cpp_COMPILER}: .var.command += -MP +# If MESON is empty, the rule will be re-evaluated after Makefiles are +# reread (and MESON won't be empty anymore). +ifneq ($(MESON),) +Makefile.mtest: build.ninja scripts/mtest2make.py + $(MESON) introspect --tests | $(PYTHON) scripts/mtest2make.py > $@ +-include Makefile.mtest +endif + .git-submodule-status: git-submodule-update config-host.mak # Check that we're not trying to do an out-of-tree build from @@ -825,7 +833,7 @@ distclean: clean ninja-distclean rm -f roms/seabios/config.mak roms/vgabios/config.mak rm -f qemu-plugins-ld.symbols qemu-plugins-ld64.symbols rm -rf meson-private meson-logs meson-info compile_commands.json - rm -f Makefile.ninja ninjatool ninjatool.stamp + rm -f Makefile.ninja ninjatool ninjatool.stamp Makefile.mtest rm -f config.log rm -f linux-headers/asm rm -f docs/version.texi diff --git a/scripts/mtest2make.py b/scripts/mtest2make.py new file mode 100644 index 0000000000..bdb257bbd9 --- /dev/null +++ b/scripts/mtest2make.py @@ -0,0 +1,102 @@ +#! /usr/bin/env python3 + +# Create Makefile targets to run tests, from Meson's test introspection data. +# +# Author: Paolo Bonzini + +from collections import defaultdict +import json +import os +import shlex +import sys + +class Suite(object): + def __init__(self): + self.tests = list() + self.slow_tests = list() + self.executables = set() + +print(''' +SPEED = quick + +# $1 = test command, $2 = test name +.test-human-tap = $1 < /dev/null | ./scripts/tap-driver.pl --test-name="$2" $(if $(V),,--show-failures-only) +.test-human-exitcode = $1 < /dev/null +.test-tap-tap = $1 < /dev/null | sed "s/^[a-z][a-z]* [0-9]*/& $2/" || true +.test-tap-exitcode = printf "%s\\n" 1..1 "`$1 < /dev/null > /dev/null || echo "not "`ok 1 $2" +.test.print = echo $(if $(V),'$1','Running test $2') >&3 +.test.env = MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} + +# $1 = test name, $2 = test target (human or tap) +.test.run = $(call .test.print,$(.test.cmd.$1),$(.test.name.$1)) && $(call .test-$2-$(.test.driver.$1),$(.test.cmd.$1),$(.test.name.$1)) + +define .test.human_k + @exec 3>&1; rc=0; $(foreach TEST, $1, $(call .test.run,$(TEST),human) || rc=$$?;) \\ + exit $$rc +endef +define .test.human_no_k + $(foreach TEST, $1, @exec 3>&1; $(call .test.run,$(TEST),human) +) +endef +.test.human = \\ + $(if $(findstring k, $(MAKEFLAGS)), $(.test.human_k), $(.test.human_no_k)) + +define .test.tap + @exec 3>&1; { $(foreach TEST, $1, $(call .test.run,$(TEST),tap); ) } \\ + | ./scripts/tap-merge.pl | tee "$@" \\ + | ./scripts/tap-driver.pl $(if $(V),, --show-failures-only) +endef +''') + +suites = defaultdict(Suite) +i = 0 +for test in json.load(sys.stdin): + env = ' '.join(('%s=%s' % (shlex.quote(k), shlex.quote(v)) + for k, v in test['env'].items())) + executable = os.path.relpath(test['cmd'][0]) + if test['workdir'] is not None: + test['cmd'][0] = os.path.relpath(test['cmd'][0], test['workdir']) + else: + test['cmd'][0] = executable + cmd = '$(.test.env) %s %s' % (env, ' '.join((shlex.quote(x) for x in test['cmd']))) + if test['workdir'] is not None: + cmd = '(cd %s && %s)' % (shlex.quote(test['workdir']), cmd) + driver = test['protocol'] if 'protocol' in test else 'exitcode' + + i += 1 + print('.test.name.%d := %s' % (i, test['name'])) + print('.test.driver.%d := %s' % (i, driver)) + print('.test.cmd.%d := %s' % (i, cmd)) + + test_suites = test['suite'] or ['default'] + is_slow = any(s.endswith('-slow') for s in test_suites) + for s in test_suites: + # The suite name in the introspection info is "PROJECT:SUITE" + s = s.split(':')[1] + if s.endswith('-slow'): + s = s[:-5] + if is_slow: + suites[s].slow_tests.append(i) + else: + suites[s].tests.append(i) + suites[s].executables.add(executable) + +print('.PHONY: check check-report.tap') +print('check:') +print('check-report.tap:') +print('\t@cat $^ | scripts/tap-merge.pl >$@') +for name, suite in suites.items(): + executables = ' '.join(suite.executables) + slow_test_numbers = ' '.join((str(x) for x in suite.slow_tests)) + test_numbers = ' '.join((str(x) for x in suite.tests)) + print('.test.suite-quick.%s := %s' % (name, test_numbers)) + print('.test.suite-slow.%s := $(.test.suite-quick.%s) %s' % (name, name, slow_test_numbers)) + print('check-build: %s' % executables) + print('.PHONY: check-%s' % name) + print('.PHONY: check-report-%s.tap' % name) + print('check: check-%s' % name) + print('check-%s: all %s' % (name, executables)) + print('\t$(call .test.human, $(.test.suite-$(SPEED).%s))' % (name, )) + print('check-report.tap: check-report-%s.tap' % name) + print('check-report-%s.tap: %s' % (name, executables)) + print('\t$(call .test.tap, $(.test.suite-$(SPEED).%s))' % (name, )) diff --git a/tests/Makefile.include b/tests/Makefile.include index c7e4646ded..ad54100369 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -674,7 +674,6 @@ check-report-unit.tap: $(check-unit-y) # Reports and overall runs check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap - $(call quiet-command, cat $^ | scripts/tap-merge.pl >$@,"GEN","$@") # FPU Emulation tests (aka softfloat) # -- cgit v1.2.3-55-g7522 From a81df1b68b656f2487f556240baf2af83e60ec6c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 19 Aug 2020 08:44:56 -0400 Subject: libqemuutil, qapi, trace: convert to meson This shows how to do some "computations" in meson.build using its array and dictionary data structures, and also a basic usage of the sourceset module for conditional compilation. Notice the new "if have_system" part of util/meson.build, which fixes a bug in the old build system was buggy: util/dbus.c was built even for non-softmmu builds, but the dependency on -lgio was lost when the linking was done through libqemuutil.a. Because all of its users required gio otherwise, the bug was hidden. Meson instead propagates libqemuutil's dependencies down to its users, and shows the problem. Signed-off-by: Paolo Bonzini --- Makefile | 228 ++++++------------------------------ Makefile.objs | 95 --------------- Makefile.target | 8 +- configure | 8 ++ crypto/Makefile.objs | 6 - crypto/meson.build | 11 ++ docs/devel/tracing.txt | 2 +- meson.build | 194 ++++++++++++++++++++++++++++++ qapi/Makefile.objs | 23 ---- qapi/meson.build | 121 +++++++++++++++++++ qobject/Makefile.objs | 3 - qobject/meson.build | 3 + rules.mak | 2 +- scripts/qapi-gen.py | 0 scripts/tracetool.py | 0 scripts/tracetool/backend/dtrace.py | 2 +- scripts/tracetool/backend/ust.py | 6 +- storage-daemon/Makefile.objs | 4 +- storage-daemon/meson.build | 1 + storage-daemon/qapi/Makefile.objs | 1 - storage-daemon/qapi/meson.build | 10 ++ stubs/Makefile.objs | 56 --------- stubs/meson.build | 50 ++++++++ trace/Makefile.objs | 51 -------- trace/meson.build | 76 ++++++++++++ util/Makefile.objs | 83 ------------- util/meson.build | 78 ++++++++++++ 27 files changed, 597 insertions(+), 525 deletions(-) create mode 100644 crypto/meson.build create mode 100644 qapi/meson.build delete mode 100644 qobject/Makefile.objs create mode 100644 qobject/meson.build mode change 100755 => 100644 scripts/qapi-gen.py mode change 100755 => 100644 scripts/tracetool.py create mode 100644 storage-daemon/meson.build delete mode 100644 storage-daemon/qapi/Makefile.objs create mode 100644 storage-daemon/qapi/meson.build delete mode 100644 stubs/Makefile.objs create mode 100644 stubs/meson.build create mode 100644 trace/meson.build delete mode 100644 util/Makefile.objs create mode 100644 util/meson.build diff --git a/Makefile b/Makefile index 5f9aae6e3e..e5d217d4d2 100644 --- a/Makefile +++ b/Makefile @@ -137,184 +137,60 @@ FULL_VERSION := $(if $(QEMU_PKGVERSION),$(VERSION) ($(QEMU_PKGVERSION)),$(VERSIO generated-files-y = qemu-version.h config-host.h qemu-options.def -GENERATED_QAPI_FILES = qapi/qapi-builtin-types.h qapi/qapi-builtin-types.c -GENERATED_QAPI_FILES += qapi/qapi-types.h qapi/qapi-types.c -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-types-%.h) -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-types-%.c) -GENERATED_QAPI_FILES += qapi/qapi-builtin-visit.h qapi/qapi-builtin-visit.c -GENERATED_QAPI_FILES += qapi/qapi-visit.h qapi/qapi-visit.c -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-visit-%.h) -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-visit-%.c) -GENERATED_QAPI_FILES += qapi/qapi-init-commands.h qapi/qapi-init-commands.c -GENERATED_QAPI_FILES += qapi/qapi-commands.h qapi/qapi-commands.c -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-commands-%.h) -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-commands-%.c) -GENERATED_QAPI_FILES += qapi/qapi-emit-events.h qapi/qapi-emit-events.c -GENERATED_QAPI_FILES += qapi/qapi-events.h qapi/qapi-events.c -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-events-%.h) -GENERATED_QAPI_FILES += $(QAPI_MODULES:%=qapi/qapi-events-%.c) -GENERATED_QAPI_FILES += qapi/qapi-introspect.c qapi/qapi-introspect.h -GENERATED_QAPI_FILES += qapi/qapi-doc.texi - -# The following list considers only the storage daemon main module. All other -# modules are currently shared with the main schema, so we don't actually -# generate additional files. - -GENERATED_STORAGE_DAEMON_QAPI_FILES = storage-daemon/qapi/qapi-commands.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-commands.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-emit-events.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-emit-events.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-events.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-events.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-init-commands.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-init-commands.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-introspect.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-introspect.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-types.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-types.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-visit.h -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-visit.c -GENERATED_STORAGE_DAEMON_QAPI_FILES += storage-daemon/qapi/qapi-doc.texi - -generated-files-y += $(GENERATED_QAPI_FILES) -generated-files-y += $(GENERATED_STORAGE_DAEMON_QAPI_FILES) - generated-files-y += trace/generated-tcg-tracers.h generated-files-y += trace/generated-helpers-wrappers.h generated-files-y += trace/generated-helpers.h generated-files-y += trace/generated-helpers.c -generated-files-$(CONFIG_TRACE_UST) += trace-ust-all.h -generated-files-$(CONFIG_TRACE_UST) += trace-ust-all.c - generated-files-y += module_block.h -TRACE_HEADERS = trace/trace-root.h -TRACE_SOURCES = trace/trace-root.c -TRACE_DTRACE = -ifdef CONFIG_TRACE_DTRACE -TRACE_HEADERS += trace-dtrace-root.h $(trace-events-subdirs:%=%/trace-dtrace.h) -TRACE_DTRACE += trace-dtrace-root.dtrace $(trace-events-subdirs:%=%/trace-dtrace.dtrace) -endif -ifdef CONFIG_TRACE_UST -TRACE_HEADERS += trace-ust-root.h $(trace-events-subdirs:%=%/trace-ust.h) -endif - -generated-files-y += $(BUILD_DIR)/trace-events-all generated-files-y += .git-submodule-status -trace-group-name = $(shell dirname $1 | sed -e 's/[^a-zA-Z0-9]/_/g') -trace-group-suffix = $(shell echo $1 | sed -e 's/[^a-zA-Z0-9]/_/g') - tracetool-y = $(SRC_PATH)/scripts/tracetool.py tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") -define __trace_rules -TRACE_HEADERS += trace/trace-$2.h -TRACE_SOURCES += trace/trace-$2.c -trace-obj-y += trace/trace-$2.o -trace/trace-$2.h: trace/trace-$2.h-timestamp - @cmp $$< $$@ >/dev/null 2>&1 || cp $$< $$@ -trace/trace-$2.h-timestamp: $(SRC_PATH)/$1/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak - $(call quiet-command,$(TRACETOOL) \ - --group=$2 \ - --format=h \ - --backends=$(TRACE_BACKENDS) \ - $$< > $$@,"GEN","$$(@:%-timestamp=%)") - -trace/trace-$2.c: trace/trace-$2.c-timestamp - @cmp $$< $$@ >/dev/null 2>&1 || cp $$< $$@ -trace/trace-$2.c-timestamp: $(SRC_PATH)/$1/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak - $(call quiet-command,$(TRACETOOL) \ - --group=$2 \ - --format=c \ - --backends=$(TRACE_BACKENDS) \ - $$< > $$@,"GEN","$$(@:%-timestamp=%)") -endef - -%/trace-ust.h: %/trace-ust.h-timestamp +trace/generated-helpers-wrappers.h: trace/generated-helpers-wrappers.h-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -%/trace-ust.h-timestamp: $(SRC_PATH)/%/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak - $(call quiet-command,$(TRACETOOL) \ - --group=$(call trace-group-name,$@) \ - --format=ust-events-h \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") - -%/trace-dtrace.dtrace: %/trace-dtrace.dtrace-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -%/trace-dtrace.dtrace-timestamp: $(SRC_PATH)/%/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=$(call trace-group-name,$@) \ - --format=d \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") - -%/trace-dtrace.h: %/trace-dtrace.dtrace $(tracetool-y) - $(call quiet-command,dtrace -o $@ -h -s $<, "GEN","$@") - -%/trace-dtrace.o: %/trace-dtrace.dtrace $(tracetool-y) - - -trace/trace-root.h: trace/trace-root.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/trace-root.h-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/generated-helpers-wrappers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) + @mkdir -p $(dir $@) $(call quiet-command,$(TRACETOOL) \ --group=root \ - --format=h \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") + --format=tcg-helper-wrapper-h \ + --backend=$(TRACE_BACKENDS) \ + $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") -trace/trace-root.c: trace/trace-root.c-timestamp +trace/generated-helpers.h: trace/generated-helpers.h-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/trace-root.c-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/generated-helpers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) + @mkdir -p $(dir $@) $(call quiet-command,$(TRACETOOL) \ --group=root \ - --format=c \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") + --format=tcg-helper-h \ + --backend=$(TRACE_BACKENDS) \ + $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") -trace-ust-root.h: trace-ust-root.h-timestamp +trace/generated-helpers.c: trace/generated-helpers.c-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-ust-root.h-timestamp: $(SRC_PATH)/trace-events $(tracetool-y) $(BUILD_DIR)/config-host.mak +trace/generated-helpers.c-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) + @mkdir -p $(dir $@) $(call quiet-command,$(TRACETOOL) \ --group=root \ - --format=ust-events-h \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") - -trace-ust-all.h: trace-ust-all.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-ust-all.h-timestamp: $(trace-events-files) $(tracetool-y) $(BUILD_DIR)/config-host.mak - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=ust-events-h \ - --backends=$(TRACE_BACKENDS) \ - $(trace-events-files) > $@,"GEN","$(@:%-timestamp=%)") + --format=tcg-helper-c \ + --backend=$(TRACE_BACKENDS) \ + $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") -trace-ust-all.c: trace-ust-all.c-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-ust-all.c-timestamp: $(trace-events-files) $(tracetool-y) $(BUILD_DIR)/config-host.mak - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=ust-events-c \ - --backends=$(TRACE_BACKENDS) \ - $(trace-events-files) > $@,"GEN","$(@:%-timestamp=%)") +trace/generated-helpers.o: trace/generated-helpers.c -trace-dtrace-root.dtrace: trace-dtrace-root.dtrace-timestamp +trace/generated-tcg-tracers.h: trace/generated-tcg-tracers.h-timestamp @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace-dtrace-root.dtrace-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) +trace/generated-tcg-tracers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) + @mkdir -p $(dir $@) $(call quiet-command,$(TRACETOOL) \ --group=root \ - --format=d \ - --backends=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(@:%-timestamp=%)") - -trace-dtrace-root.h: trace-dtrace-root.dtrace - $(call quiet-command,dtrace -o $@ -h -s $<, "GEN","$@") - -trace-dtrace-root.o: trace-dtrace-root.dtrace + --format=tcg-h \ + --backend=$(TRACE_BACKENDS) \ + $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv @@ -485,10 +361,8 @@ include $(SRC_PATH)/Makefile.objs endif dummy := $(call unnest-vars,, \ - stub-obj-y \ authz-obj-y \ chardev-obj-y \ - util-obj-y \ qga-obj-y \ elf2dmp-obj-y \ ivshmem-client-obj-y \ @@ -509,14 +383,7 @@ dummy := $(call unnest-vars,, \ qom-obj-y \ io-obj-y \ common-obj-y \ - common-obj-m \ - trace-obj-y) - -dummy := $(foreach DIR,$(trace-events-subdirs),$(eval $(call __trace_rules,$(DIR),$(call trace-group-suffix,$(DIR))))) - -generated-files-y += $(TRACE_HEADERS) -generated-files-y += $(TRACE_SOURCES) - + common-obj-m) include $(SRC_PATH)/tests/Makefile.include @@ -630,8 +497,7 @@ Makefile: $(version-obj-y) ###################################################################### # Build libraries -libqemuutil.a: $(util-obj-y) $(trace-obj-y) $(stub-obj-y) -libvhost-user.a: $(libvhost-user-obj-y) $(util-obj-y) $(stub-obj-y) +libvhost-user.a: $(libvhost-user-obj-y) ###################################################################### @@ -694,27 +560,6 @@ qga/qapi-generated/qapi-gen-timestamp: $(SRC_PATH)/qga/qapi-schema.json $(qapi-p "GEN","$(@:%-timestamp=%)") @>$@ -qapi-modules = $(SRC_PATH)/qapi/qapi-schema.json \ - $(QAPI_MODULES:%=$(SRC_PATH)/qapi/%.json) - -$(GENERATED_QAPI_FILES): qapi-gen-timestamp ; -qapi-gen-timestamp: $(qapi-modules) $(qapi-py) - $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ - -o "qapi" -b $<, \ - "GEN","$(@:%-timestamp=%)") - @>$@ - -qapi-modules-storage-daemon = \ - $(SRC_PATH)/storage-daemon/qapi/qapi-schema.json \ - $(QAPI_MODULES_STORAGE_DAEMON:%=$(SRC_PATH)/qapi/%.json) - -$(GENERATED_STORAGE_DAEMON_QAPI_FILES): storage-daemon/qapi/qapi-gen-timestamp ; -storage-daemon/qapi/qapi-gen-timestamp: $(qapi-modules-storage-daemon) $(qapi-py) - $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ - -o "storage-daemon/qapi" $<, \ - "GEN","$(@:%-timestamp=%)") - @>$@ - QGALIB_GEN=$(addprefix qga/qapi-generated/, qga-qapi-types.h qga-qapi-visit.h qga-qapi-commands.h qga-qapi-init-commands.h) $(qga-obj-y): $(QGALIB_GEN) @@ -752,9 +597,9 @@ ivshmem-client$(EXESUF): $(ivshmem-client-obj-y) $(COMMON_LDADDS) ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) libvhost-user.a +vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) -vhost-user-blk$(EXESUF): $(vhost-user-blk-obj-y) libvhost-user.a +vhost-user-blk$(EXESUF): $(vhost-user-blk-obj-y) libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) rdmacm-mux$(EXESUF): LIBS += "-libumad" @@ -767,12 +612,12 @@ virtiofsd$(EXESUF): $(virtiofsd-obj-y) libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) $(libvhost-user-obj-y) libqemuutil.a +vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) ifdef CONFIG_VHOST_USER_INPUT ifdef CONFIG_LINUX -vhost-user-input$(EXESUF): $(vhost-user-input-obj-y) libvhost-user.a libqemuutil.a +vhost-user-input$(EXESUF): $(vhost-user-input-obj-y) libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) # build by default, do not install @@ -801,9 +646,6 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f fsdev/*.pod scsi/*.pod rm -f qemu-img-cmds.h rm -f ui/shader/*-vert.h ui/shader/*-frag.h - @# May not be present in generated-files-y - rm -f trace/generated-tracers-dtrace.dtrace* - rm -f trace/generated-tracers-dtrace.h* rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) rm -f qapi-gen-timestamp rm -f storage-daemon/qapi/qapi-gen-timestamp @@ -1033,7 +875,9 @@ endif set -e; for x in $(KEYMAPS); do \ $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x "$(DESTDIR)$(qemu_datadir)/keymaps"; \ done - $(INSTALL_DATA) $(BUILD_DIR)/trace-events-all "$(DESTDIR)$(qemu_datadir)/trace-events-all" + for d in $(TARGET_DIRS); do \ + $(MAKE) $(SUBDIR_MAKEFLAGS) TARGET_DIR=$$d/ -C $$d $@ || exit 1 ; \ + done # opengl shader programs ui/shader/%-vert.h: $(SRC_PATH)/ui/shader/%.vert $(SRC_PATH)/scripts/shaderinclude.pl @@ -1244,10 +1088,6 @@ Makefile: $(generated-files-y) endif endif -.SECONDARY: $(TRACE_HEADERS) $(TRACE_HEADERS:%=%-timestamp) \ - $(TRACE_SOURCES) $(TRACE_SOURCES:%=%-timestamp) \ - $(TRACE_DTRACE) $(TRACE_DTRACE:%=%-timestamp) - # Include automatically generated dependency files # Dependencies in Makefile.objs files come from our recursive subdir rules -include $(wildcard *.d tests/*.d) diff --git a/Makefile.objs b/Makefile.objs index 3823463c23..e5c9077517 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -1,7 +1,5 @@ ####################################################################### # Common libraries for tools and emulators -stub-obj-y = stubs/ -util-obj-y = crypto/ util/ qobject/ qapi/ qom-obj-y = qom/ ####################################################################### @@ -94,10 +92,6 @@ common-obj-y += disas/ # Resource file for Windows executables version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o -###################################################################### -# tracing -util-obj-y += trace/ - ###################################################################### # guest agent @@ -123,92 +117,3 @@ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ virtiofsd-obj-y = tools/virtiofsd/ ###################################################################### -trace-events-subdirs = -trace-events-subdirs += accel/kvm -trace-events-subdirs += accel/tcg -trace-events-subdirs += backends -trace-events-subdirs += backends/tpm -trace-events-subdirs += crypto -trace-events-subdirs += monitor -ifeq ($(CONFIG_USER_ONLY),y) -trace-events-subdirs += linux-user -endif -ifeq ($(CONFIG_BLOCK),y) -trace-events-subdirs += authz -trace-events-subdirs += block -trace-events-subdirs += io -trace-events-subdirs += nbd -trace-events-subdirs += scsi -endif -ifeq ($(CONFIG_SOFTMMU),y) -trace-events-subdirs += audio -trace-events-subdirs += chardev -trace-events-subdirs += hw/9pfs -trace-events-subdirs += hw/acpi -trace-events-subdirs += hw/alpha -trace-events-subdirs += hw/arm -trace-events-subdirs += hw/audio -trace-events-subdirs += hw/block -trace-events-subdirs += hw/block/dataplane -trace-events-subdirs += hw/char -trace-events-subdirs += hw/dma -trace-events-subdirs += hw/hppa -trace-events-subdirs += hw/hyperv -trace-events-subdirs += hw/i2c -trace-events-subdirs += hw/i386 -trace-events-subdirs += hw/i386/xen -trace-events-subdirs += hw/ide -trace-events-subdirs += hw/input -trace-events-subdirs += hw/intc -trace-events-subdirs += hw/isa -trace-events-subdirs += hw/mem -trace-events-subdirs += hw/mips -trace-events-subdirs += hw/misc -trace-events-subdirs += hw/misc/macio -trace-events-subdirs += hw/net -trace-events-subdirs += hw/nvram -trace-events-subdirs += hw/pci -trace-events-subdirs += hw/pci-host -trace-events-subdirs += hw/ppc -trace-events-subdirs += hw/rdma -trace-events-subdirs += hw/rdma/vmw -trace-events-subdirs += hw/rtc -trace-events-subdirs += hw/s390x -trace-events-subdirs += hw/scsi -trace-events-subdirs += hw/sd -trace-events-subdirs += hw/sparc -trace-events-subdirs += hw/sparc64 -trace-events-subdirs += hw/ssi -trace-events-subdirs += hw/timer -trace-events-subdirs += hw/tpm -trace-events-subdirs += hw/usb -trace-events-subdirs += hw/vfio -trace-events-subdirs += hw/virtio -trace-events-subdirs += hw/watchdog -trace-events-subdirs += hw/xen -trace-events-subdirs += hw/gpio -trace-events-subdirs += hw/riscv -trace-events-subdirs += migration -trace-events-subdirs += net -trace-events-subdirs += ui -endif -trace-events-subdirs += hw/core -trace-events-subdirs += hw/display -trace-events-subdirs += qapi -trace-events-subdirs += qom -trace-events-subdirs += target/arm -trace-events-subdirs += target/hppa -trace-events-subdirs += target/i386 -trace-events-subdirs += target/mips -trace-events-subdirs += target/ppc -trace-events-subdirs += target/riscv -trace-events-subdirs += target/s390x -trace-events-subdirs += target/sparc -trace-events-subdirs += util - -trace-events-files = $(SRC_PATH)/trace-events $(trace-events-subdirs:%=$(SRC_PATH)/%/trace-events) - -trace-obj-y = trace-root.o -trace-obj-$(CONFIG_TRACE_UST) += trace-ust-all.o -trace-obj-$(CONFIG_TRACE_DTRACE) += trace-dtrace-root.o -trace-obj-$(CONFIG_TRACE_DTRACE) += $(trace-events-subdirs:%=%/trace-dtrace.o) diff --git a/Makefile.target b/Makefile.target index d61a6a978b..0b323641bb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -57,7 +57,7 @@ endif tracetool-y = $(SRC_PATH)/scripts/tracetool.py tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") -$(QEMU_PROG).stp-installed: $(BUILD_DIR)/trace-events-all $(tracetool-y) +$(QEMU_PROG).stp-installed: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) $(call quiet-command,$(TRACETOOL) \ --group=all \ --format=stap \ @@ -67,7 +67,7 @@ $(QEMU_PROG).stp-installed: $(BUILD_DIR)/trace-events-all $(tracetool-y) --target-type=$(TARGET_TYPE) \ $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG).stp-installed") -$(QEMU_PROG).stp: $(BUILD_DIR)/trace-events-all $(tracetool-y) +$(QEMU_PROG).stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) $(call quiet-command,$(TRACETOOL) \ --group=all \ --format=stap \ @@ -77,7 +77,7 @@ $(QEMU_PROG).stp: $(BUILD_DIR)/trace-events-all $(tracetool-y) --target-type=$(TARGET_TYPE) \ $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG).stp") -$(QEMU_PROG)-simpletrace.stp: $(BUILD_DIR)/trace-events-all $(tracetool-y) +$(QEMU_PROG)-simpletrace.stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) $(call quiet-command,$(TRACETOOL) \ --group=all \ --format=simpletrace-stap \ @@ -85,7 +85,7 @@ $(QEMU_PROG)-simpletrace.stp: $(BUILD_DIR)/trace-events-all $(tracetool-y) --probe-prefix=qemu.$(TARGET_TYPE).$(TARGET_NAME) \ $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG)-simpletrace.stp") -$(QEMU_PROG)-log.stp: $(BUILD_DIR)/trace-events-all $(tracetool-y) +$(QEMU_PROG)-log.stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) $(call quiet-command,$(TRACETOOL) \ --group=all \ --format=log-stap \ diff --git a/configure b/configure index 79bcf8a681..75ffe30d75 100755 --- a/configure +++ b/configure @@ -7247,6 +7247,8 @@ fi echo "CONFIG_TLS_PRIORITY=\"$tls_priority\"" >> $config_host_mak if test "$gnutls" = "yes" ; then echo "CONFIG_GNUTLS=y" >> $config_host_mak + echo "GNUTLS_CFLAGS=$gnutls_cflags" >> $config_host_mak + echo "GNUTLS_LIBS=$gnutls_libs" >> $config_host_mak fi if test "$gcrypt" = "yes" ; then echo "CONFIG_GCRYPT=y" >> $config_host_mak @@ -7257,6 +7259,8 @@ fi if test "$nettle" = "yes" ; then echo "CONFIG_NETTLE=y" >> $config_host_mak echo "CONFIG_NETTLE_VERSION_MAJOR=${nettle_version%%.*}" >> $config_host_mak + echo "NETTLE_CFLAGS=$nettle_cflags" >> $config_host_mak + echo "NETTLE_LIBS=$nettle_libs" >> $config_host_mak fi if test "$qemu_private_xts" = "yes" ; then echo "CONFIG_QEMU_PRIVATE_XTS=y" >> $config_host_mak @@ -7633,6 +7637,8 @@ if have_backend "log"; then fi if have_backend "ust"; then echo "CONFIG_TRACE_UST=y" >> $config_host_mak + echo "LTTNG_UST_LIBS=$lttng_ust_libs" >> $config_host_mak + echo "URCU_BP_LIBS=$urcu_bp_libs" >> $config_host_mak fi if have_backend "dtrace"; then echo "CONFIG_TRACE_DTRACE=y" >> $config_host_mak @@ -7858,6 +7864,8 @@ echo "CFLAGS_NOPIE=$CFLAGS_NOPIE" >> $config_host_mak echo "QEMU_CFLAGS=$QEMU_CFLAGS" >> $config_host_mak echo "QEMU_CXXFLAGS=$QEMU_CXXFLAGS" >> $config_host_mak echo "QEMU_INCLUDES=$QEMU_INCLUDES" >> $config_host_mak +echo "GLIB_CFLAGS=$glib_cflags" >> $config_host_mak +echo "GLIB_LIBS=$glib_libs" >> $config_host_mak if test "$sparse" = "yes" ; then echo "SPARSE_CFLAGS = -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak fi diff --git a/crypto/Makefile.objs b/crypto/Makefile.objs index f1965b1a68..a9885919f2 100644 --- a/crypto/Makefile.objs +++ b/crypto/Makefile.objs @@ -35,9 +35,3 @@ crypto-obj-$(CONFIG_QEMU_PRIVATE_XTS) += xts.o crypto-obj-y += block.o crypto-obj-y += block-qcow.o crypto-obj-y += block-luks.o - -util-obj-$(CONFIG_GCRYPT) += random-gcrypt.o -util-obj-$(if $(CONFIG_GCRYPT),n,$(CONFIG_GNUTLS)) += random-gnutls.o -util-obj-$(if $(CONFIG_GCRYPT),n,$(if $(CONFIG_GNUTLS),n,$(CONFIG_RNG_NONE))) += random-none.o -util-obj-$(if $(CONFIG_GCRYPT),n,$(if $(CONFIG_GNUTLS),n,$(if $(CONFIG_RNG_NONE),n,y))) += random-platform.o -util-obj-y += aes.o init.o diff --git a/crypto/meson.build b/crypto/meson.build new file mode 100644 index 0000000000..1b244315b9 --- /dev/null +++ b/crypto/meson.build @@ -0,0 +1,11 @@ +util_ss.add(files('aes.c')) +util_ss.add(files('init.c')) +if 'CONFIG_GCRYPT' in config_host + util_ss.add(files('random-gcrypt.c')) +elif 'CONFIG_GNUTLS' in config_host + util_ss.add(files('random-gnutls.c'), gnutls) +elif 'CONFIG_RNG_NONE' in config_host + util_ss.add(files('random-none.c')) +else + util_ss.add(files('random-platform.c')) +endif diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt index cb5f685de9..6144d9921b 100644 --- a/docs/devel/tracing.txt +++ b/docs/devel/tracing.txt @@ -60,7 +60,7 @@ general. It is strongly preferred that all events be declared directly in the sub-directory that uses them. The only exception is where there are some shared trace events defined in the top level directory trace-events file. The top level directory generates trace files with a filename prefix of -"trace-root" instead of just "trace". This is to avoid ambiguity between +"trace/trace-root" instead of just "trace". This is to avoid ambiguity between a trace.h in the current directory, vs the top level directory. === Using trace events === diff --git a/meson.build b/meson.build index 86219e500a..4e9eb5da5c 100644 --- a/meson.build +++ b/meson.build @@ -4,6 +4,9 @@ project('qemu', ['c'], meson_version: '>=0.55.0', not_found = dependency('', required: false) keyval = import('unstable-keyval') +ss = import('sourceset') + +cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') add_project_arguments(config_host['QEMU_CFLAGS'].split(), @@ -43,6 +46,197 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'sparc64', 'riscv32', 'riscv64', 'x86 cpu = host_machine.cpu_family() targetos = host_machine.system() +m = cc.find_library('m', required: false) +util = cc.find_library('util', required: false) +socket = [] +if targetos == 'windows' + socket = cc.find_library('ws2_32') +endif +glib = declare_dependency(compile_args: config_host['GLIB_CFLAGS'].split(), + link_args: config_host['GLIB_LIBS'].split()) +gio = not_found +if 'CONFIG_GIO' in config_host + gio = declare_dependency(compile_args: config_host['GIO_CFLAGS'].split(), + link_args: config_host['GIO_LIBS'].split()) +endif +lttng = not_found +if 'CONFIG_TRACE_UST' in config_host + lttng = declare_dependency(link_args: config_host['LTTNG_UST_LIBS'].split()) +endif +urcubp = not_found +if 'CONFIG_TRACE_UST' in config_host + urcubp = declare_dependency(link_args: config_host['URCU_BP_LIBS'].split()) +endif +nettle = not_found +if 'CONFIG_NETTLE' in config_host + nettle = declare_dependency(compile_args: config_host['NETTLE_CFLAGS'].split(), + link_args: config_host['NETTLE_LIBS'].split()) +endif +gnutls = not_found +if 'CONFIG_GNUTLS' in config_host + gnutls = declare_dependency(compile_args: config_host['GNUTLS_CFLAGS'].split(), + link_args: config_host['GNUTLS_LIBS'].split()) +endif + +target_dirs = config_host['TARGET_DIRS'].split() +have_user = false +have_system = false +foreach target : target_dirs + have_user = have_user or target.endswith('-user') + have_system = have_system or target.endswith('-softmmu') +endforeach +have_tools = 'CONFIG_TOOLS' in config_host +have_block = have_system or have_tools + +# Generators + +qapi_gen = find_program('scripts/qapi-gen.py') +qapi_gen_depends = [ meson.source_root() / 'scripts/qapi/__init__.py', + meson.source_root() / 'scripts/qapi/commands.py', + meson.source_root() / 'scripts/qapi/common.py', + meson.source_root() / 'scripts/qapi/doc.py', + meson.source_root() / 'scripts/qapi/error.py', + meson.source_root() / 'scripts/qapi/events.py', + meson.source_root() / 'scripts/qapi/expr.py', + meson.source_root() / 'scripts/qapi/gen.py', + meson.source_root() / 'scripts/qapi/introspect.py', + meson.source_root() / 'scripts/qapi/parser.py', + meson.source_root() / 'scripts/qapi/schema.py', + meson.source_root() / 'scripts/qapi/source.py', + meson.source_root() / 'scripts/qapi/types.py', + meson.source_root() / 'scripts/qapi/visit.py', + meson.source_root() / 'scripts/qapi/common.py', + meson.source_root() / 'scripts/qapi/doc.py', + meson.source_root() / 'scripts/qapi-gen.py' +] + +tracetool = [ + python, files('scripts/tracetool.py'), + '--backend=' + config_host['TRACE_BACKENDS'] +] + +# Collect sourcesets. + +util_ss = ss.source_set() +stub_ss = ss.source_set() +trace_ss = ss.source_set() + +############### +# Trace files # +############### + +trace_events_subdirs = [ + 'accel/kvm', + 'accel/tcg', + 'crypto', + 'monitor', +] +if have_user + trace_events_subdirs += [ 'linux-user' ] +endif +if have_block + trace_events_subdirs += [ + 'authz', + 'block', + 'io', + 'nbd', + 'scsi', + ] +endif +if have_system + trace_events_subdirs += [ + 'audio', + 'backends', + 'backends/tpm', + 'chardev', + 'hw/9pfs', + 'hw/acpi', + 'hw/alpha', + 'hw/arm', + 'hw/audio', + 'hw/block', + 'hw/block/dataplane', + 'hw/char', + 'hw/display', + 'hw/dma', + 'hw/hppa', + 'hw/hyperv', + 'hw/i2c', + 'hw/i386', + 'hw/i386/xen', + 'hw/ide', + 'hw/input', + 'hw/intc', + 'hw/isa', + 'hw/mem', + 'hw/mips', + 'hw/misc', + 'hw/misc/macio', + 'hw/net', + 'hw/nvram', + 'hw/pci', + 'hw/pci-host', + 'hw/ppc', + 'hw/rdma', + 'hw/rdma/vmw', + 'hw/rtc', + 'hw/s390x', + 'hw/scsi', + 'hw/sd', + 'hw/sparc', + 'hw/sparc64', + 'hw/ssi', + 'hw/timer', + 'hw/tpm', + 'hw/usb', + 'hw/vfio', + 'hw/virtio', + 'hw/watchdog', + 'hw/xen', + 'hw/gpio', + 'hw/riscv', + 'migration', + 'net', + 'ui', + ] +endif +trace_events_subdirs += [ + 'hw/core', + 'qapi', + 'qom', + 'target/arm', + 'target/hppa', + 'target/i386', + 'target/mips', + 'target/ppc', + 'target/riscv', + 'target/s390x', + 'target/sparc', + 'util', +] + +genh = [] + +subdir('qapi') +subdir('qobject') +subdir('stubs') +subdir('trace') +subdir('util') +subdir('crypto') +subdir('storage-daemon') + +# Build targets from sourcesets + +stub_ss = stub_ss.apply(config_host, strict: false) + +util_ss.add_all(trace_ss) +util_ss = util_ss.apply(config_host, strict: false) +libqemuutil = static_library('qemuutil', + sources: util_ss.sources() + stub_ss.sources() + genh, + dependencies: [util_ss.dependencies(), m, glib, socket]) +qemuutil = declare_dependency(link_with: libqemuutil, + sources: genh) + summary_info = {} summary_info += {'Install prefix': config_host['prefix']} summary_info += {'BIOS directory': config_host['qemu_datadir']} diff --git a/qapi/Makefile.objs b/qapi/Makefile.objs index 4673ab7490..c0a31be1a1 100644 --- a/qapi/Makefile.objs +++ b/qapi/Makefile.objs @@ -1,25 +1,4 @@ -util-obj-y = qapi-visit-core.o qapi-dealloc-visitor.o qobject-input-visitor.o -util-obj-y += qobject-output-visitor.o qmp-registry.o qmp-dispatch.o -util-obj-y += string-input-visitor.o string-output-visitor.o -util-obj-y += opts-visitor.o qapi-clone-visitor.o -util-obj-y += qmp-event.o -util-obj-y += qapi-util.o - -QAPI_COMMON_MODULES = audio authz block-core block char common control crypto -QAPI_COMMON_MODULES += dump error introspect job machine migration misc -QAPI_COMMON_MODULES += net pragma qdev qom rdma rocker run-state sockets tpm -QAPI_COMMON_MODULES += trace transaction ui QAPI_TARGET_MODULES = machine-target misc-target -QAPI_MODULES = $(QAPI_COMMON_MODULES) $(QAPI_TARGET_MODULES) - -util-obj-y += qapi-builtin-types.o -util-obj-y += $(QAPI_COMMON_MODULES:%=qapi-types-%.o) -util-obj-y += qapi-builtin-visit.o -util-obj-y += $(QAPI_COMMON_MODULES:%=qapi-visit-%.o) -util-obj-y += qapi-emit-events.o -util-obj-y += $(QAPI_COMMON_MODULES:%=qapi-events-%.o) - -common-obj-y = $(QAPI_COMMON_MODULES:%=qapi-commands-%.o) obj-y = qapi-introspect.o obj-y += $(QAPI_TARGET_MODULES:%=qapi-types-%.o) @@ -34,5 +13,3 @@ obj-y += qapi-init-commands.o QAPI_MODULES_STORAGE_DAEMON = block-core char common control crypto QAPI_MODULES_STORAGE_DAEMON += introspect job qom sockets pragma transaction - -storage-daemon-obj-y += $(QAPI_MODULES_STORAGE_DAEMON:%=qapi-commands-%.o) diff --git a/qapi/meson.build b/qapi/meson.build new file mode 100644 index 0000000000..f45b80bbfa --- /dev/null +++ b/qapi/meson.build @@ -0,0 +1,121 @@ +util_ss.add(files( + 'opts-visitor.c', + 'qapi-clone-visitor.c', + 'qapi-dealloc-visitor.c', + 'qapi-util.c', + 'qapi-visit-core.c', + 'qmp-dispatch.c', + 'qmp-event.c', + 'qmp-registry.c', + 'qobject-input-visitor.c', + 'qobject-output-visitor.c', + 'string-input-visitor.c', + 'string-output-visitor.c', +)) + +qapi_all_modules = [ + 'audio', + 'authz', + 'block-core', + 'block', + 'char', + 'common', + 'control', + 'crypto', + 'dump', + 'error', + 'introspect', + 'job', + 'machine', + 'machine-target', + 'migration', + 'misc', + 'misc-target', + 'net', + 'pragma', + 'qdev', + 'qom', + 'rdma', + 'rocker', + 'run-state', + 'sockets', + 'tpm', + 'trace', + 'transaction', + 'ui', +] + +qapi_storage_daemon_modules = [ + 'block-core', + 'char', + 'common', + 'control', + 'crypto', + 'introspect', + 'job', + 'qom', + 'sockets', + 'pragma', + 'transaction', +] + +qapi_nonmodule_outputs = [ + 'qapi-introspect.c', 'qapi-introspect.h', + 'qapi-types.c', 'qapi-types.h', + 'qapi-visit.h', 'qapi-visit.c', + 'qapi-commands.h', 'qapi-commands.c', + 'qapi-init-commands.h', 'qapi-init-commands.c', + 'qapi-events.h', 'qapi-events.c', + 'qapi-emit-events.c', 'qapi-emit-events.h', +] + +# First build all sources +qapi_util_outputs = [ + 'qapi-builtin-types.c', 'qapi-builtin-visit.c', + 'qapi-builtin-types.h', 'qapi-builtin-visit.h', +] + +qapi_inputs = [] +qapi_specific_outputs = [] +foreach module : qapi_all_modules + qapi_inputs += [ files(module + '.json') ] + qapi_module_outputs = [ + 'qapi-types-@0@.c'.format(module), + 'qapi-types-@0@.h'.format(module), + 'qapi-visit-@0@.c'.format(module), + 'qapi-visit-@0@.h'.format(module), + 'qapi-events-@0@.c'.format(module), + 'qapi-events-@0@.h'.format(module), + 'qapi-commands-@0@.c'.format(module), + 'qapi-commands-@0@.h'.format(module), + ] + if module.endswith('-target') + qapi_specific_outputs += qapi_module_outputs + else + qapi_util_outputs += qapi_module_outputs + endif +endforeach + +qapi_files = custom_target('shared QAPI source files', + output: qapi_util_outputs + qapi_specific_outputs + qapi_nonmodule_outputs + ['qapi-doc.texi'], + input: [ files('qapi-schema.json') ], + command: [ qapi_gen, '-o', 'qapi', '-b', '@INPUT0@' ], + depend_files: [ qapi_inputs, qapi_gen_depends ]) + +# Now go through all the outputs and add them to the right sourceset. +# These loops must be synchronized with the output of the above custom target. + +i = 0 +foreach output : qapi_util_outputs + if output.endswith('.h') + genh += qapi_files[i] + endif + util_ss.add(qapi_files[i]) + i = i + 1 +endforeach + +# These are still handled by the Makefile +i += qapi_nonmodule_outputs.length() +i += qapi_specific_outputs.length() + +qapi_doc_texi = qapi_files[i] diff --git a/qobject/Makefile.objs b/qobject/Makefile.objs deleted file mode 100644 index 7b12c9cacf..0000000000 --- a/qobject/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -util-obj-y = qnull.o qnum.o qstring.o qdict.o qlist.o qbool.o qlit.o -util-obj-y += qjson.o qobject.o json-lexer.o json-streamer.o json-parser.o -util-obj-y += block-qdict.o diff --git a/qobject/meson.build b/qobject/meson.build new file mode 100644 index 0000000000..bb63c06b63 --- /dev/null +++ b/qobject/meson.build @@ -0,0 +1,3 @@ +util_ss.add(files('qnull.c', 'qnum.c', 'qstring.c', 'qdict.c', 'qlist.c', 'qbool.c', + 'qlit.c', 'qjson.c', 'qobject.c', 'json-lexer.c', 'json-streamer.c', 'json-parser.c', + 'block-qdict.c')) diff --git a/rules.mak b/rules.mak index 5ab42def82..7aefd37b5d 100644 --- a/rules.mak +++ b/rules.mak @@ -32,7 +32,7 @@ QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d # dir, one absolute and the other relative to the compiler working # directory. These are the same for target-independent files, but # different for target-dependent ones. -QEMU_LOCAL_INCLUDES = -iquote $(BUILD_DIR)/$(@D) -iquote $(@D) +QEMU_LOCAL_INCLUDES = -iquote $(BUILD_DIR) -iquote $(BUILD_DIR)/$(@D) -iquote $(@D) WL_U := -Wl,-u, find-symbols = $(if $1, $(sort $(shell $(NM) -P -g $1 | $2))) diff --git a/scripts/qapi-gen.py b/scripts/qapi-gen.py old mode 100755 new mode 100644 diff --git a/scripts/tracetool.py b/scripts/tracetool.py old mode 100755 new mode 100644 diff --git a/scripts/tracetool/backend/dtrace.py b/scripts/tracetool/backend/dtrace.py index fc0c8fc52f..e17edc9b9d 100644 --- a/scripts/tracetool/backend/dtrace.py +++ b/scripts/tracetool/backend/dtrace.py @@ -38,7 +38,7 @@ def generate_h_begin(events, group): if group == "root": header = "trace-dtrace-root.h" else: - header = "trace-dtrace.h" + header = "trace-dtrace-%s.h" % group # Workaround for ust backend, which also includes and may # require SDT_USE_VARIADIC to be defined. If dtrace includes diff --git a/scripts/tracetool/backend/ust.py b/scripts/tracetool/backend/ust.py index 6c0a5f8d68..c857516f21 100644 --- a/scripts/tracetool/backend/ust.py +++ b/scripts/tracetool/backend/ust.py @@ -19,11 +19,7 @@ PUBLIC = True def generate_h_begin(events, group): - if group == "root": - header = "trace-ust-root.h" - else: - header = "trace-ust.h" - + header = 'trace-ust-' + group + '.h' out('#include ', '#include "%s"' % header, '', diff --git a/storage-daemon/Makefile.objs b/storage-daemon/Makefile.objs index cfe6beee52..41c0d02178 100644 --- a/storage-daemon/Makefile.objs +++ b/storage-daemon/Makefile.objs @@ -1 +1,3 @@ -storage-daemon-obj-y += qapi/ +storage-daemon-obj-y = qapi/libqsd-qapi.fa + +qemu-storage-daemon.o: storage-daemon/qapi/qapi-commands.h storage-daemon/qapi/qapi-init-commands.h diff --git a/storage-daemon/meson.build b/storage-daemon/meson.build new file mode 100644 index 0000000000..35f8949924 --- /dev/null +++ b/storage-daemon/meson.build @@ -0,0 +1 @@ +subdir('qapi') diff --git a/storage-daemon/qapi/Makefile.objs b/storage-daemon/qapi/Makefile.objs deleted file mode 100644 index 8a4b220c96..0000000000 --- a/storage-daemon/qapi/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -storage-daemon-obj-y += qapi-commands.o qapi-init-commands.o qapi-introspect.o diff --git a/storage-daemon/qapi/meson.build b/storage-daemon/qapi/meson.build new file mode 100644 index 0000000000..7a2b041247 --- /dev/null +++ b/storage-daemon/qapi/meson.build @@ -0,0 +1,10 @@ +qsd_qapi_files = custom_target('QAPI files for qemu-storage-daemon', + output: qapi_nonmodule_outputs + ['qapi-doc.texi'], + input: [ files('qapi-schema.json') ], + command: [ qapi_gen, '-o', 'storage-daemon/qapi', '@INPUT@' ], + depend_files: [ qapi_inputs, qapi_gen_depends ]) + +static_library('qsd-qapi', + qsd_qapi_files.to_list(), + name_suffix: 'fa', + build_by_default: false) diff --git a/stubs/Makefile.objs b/stubs/Makefile.objs deleted file mode 100644 index d42046afe4..0000000000 --- a/stubs/Makefile.objs +++ /dev/null @@ -1,56 +0,0 @@ -stub-obj-y += blk-commit-all.o -stub-obj-y += cmos.o -stub-obj-y += cpu-get-clock.o -stub-obj-y += cpu-get-icount.o -stub-obj-y += dump.o -stub-obj-y += error-printf.o -stub-obj-y += fdset.o -stub-obj-y += gdbstub.o -stub-obj-y += iothread-lock.o -stub-obj-y += is-daemonized.o -stub-obj-y += isa-bus.o -stub-obj-$(CONFIG_LINUX_AIO) += linux-aio.o -stub-obj-$(CONFIG_LINUX_IO_URING) += io_uring.o -stub-obj-y += monitor-core.o -stub-obj-y += notify-event.o -stub-obj-y += pci-bus.o -stub-obj-y += qmp_memory_device.o -stub-obj-y += qtest.o -stub-obj-y += ramfb.o -stub-obj-y += replay.o -stub-obj-y += runstate-check.o -stub-obj-$(CONFIG_SOFTMMU) += semihost.o -stub-obj-y += set-fd-handler.o -stub-obj-y += sysbus.o -stub-obj-y += tpm.o -stub-obj-y += trace-control.o -stub-obj-y += vmgenid.o -stub-obj-y += vmstate.o -stub-obj-$(CONFIG_SOFTMMU) += win32-kbd-hook.o - -####################################################################### -# code used by both qemu system emulation and qemu-img - -ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) - -stub-obj-y += arch_type.o -stub-obj-y += bdrv-next-monitor-owned.o -stub-obj-y += blockdev-close-all-bdrv-states.o -stub-obj-y += change-state-handler.o -stub-obj-y += clock-warp.o -stub-obj-y += fd-register.o -stub-obj-y += fw_cfg.o -stub-obj-y += get-vm-name.o -stub-obj-y += iothread.o -stub-obj-y += machine-init-done.o -stub-obj-y += migr-blocker.o -stub-obj-y += monitor.o -stub-obj-y += pci-host-piix.o -stub-obj-y += ram-block.o -stub-obj-y += replay-user.o -stub-obj-y += target-get-monitor-def.o -stub-obj-y += target-monitor-defs.o -stub-obj-y += uuid.o -stub-obj-y += vm-stop.o - -endif # CONFIG_SOFTMMU || CONFIG_TOOLS diff --git a/stubs/meson.build b/stubs/meson.build new file mode 100644 index 0000000000..019bd79c7a --- /dev/null +++ b/stubs/meson.build @@ -0,0 +1,50 @@ +stub_ss.add(files('arch_type.c')) +stub_ss.add(files('bdrv-next-monitor-owned.c')) +stub_ss.add(files('blk-commit-all.c')) +stub_ss.add(files('blockdev-close-all-bdrv-states.c')) +stub_ss.add(files('change-state-handler.c')) +stub_ss.add(files('clock-warp.c')) +stub_ss.add(files('cmos.c')) +stub_ss.add(files('cpu-get-clock.c')) +stub_ss.add(files('cpu-get-icount.c')) +stub_ss.add(files('dump.c')) +stub_ss.add(files('error-printf.c')) +stub_ss.add(files('fd-register.c')) +stub_ss.add(files('fdset.c')) +stub_ss.add(files('fw_cfg.c')) +stub_ss.add(files('gdbstub.c')) +stub_ss.add(files('get-vm-name.c')) +stub_ss.add(when: 'CONFIG_LINUX_IO_URING', if_true: files('io_uring.c')) +stub_ss.add(files('iothread.c')) +stub_ss.add(files('iothread-lock.c')) +stub_ss.add(files('isa-bus.c')) +stub_ss.add(files('is-daemonized.c')) +stub_ss.add(when: 'CONFIG_LINUX_AIO', if_true: files('linux-aio.c')) +stub_ss.add(files('machine-init-done.c')) +stub_ss.add(files('migr-blocker.c')) +stub_ss.add(files('monitor.c')) +stub_ss.add(files('monitor-core.c')) +stub_ss.add(files('notify-event.c')) +stub_ss.add(files('pci-bus.c')) +stub_ss.add(files('pci-host-piix.c')) +stub_ss.add(files('qmp_memory_device.c')) +stub_ss.add(files('qtest.c')) +stub_ss.add(files('ram-block.c')) +stub_ss.add(files('ramfb.c')) +stub_ss.add(files('replay.c')) +stub_ss.add(files('replay-user.c')) +stub_ss.add(files('runstate-check.c')) +stub_ss.add(files('set-fd-handler.c')) +stub_ss.add(files('sysbus.c')) +stub_ss.add(files('target-get-monitor-def.c')) +stub_ss.add(files('target-monitor-defs.c')) +stub_ss.add(files('tpm.c')) +stub_ss.add(files('trace-control.c')) +stub_ss.add(files('uuid.c')) +stub_ss.add(files('vmgenid.c')) +stub_ss.add(files('vmstate.c')) +stub_ss.add(files('vm-stop.c')) +stub_ss.add(files('win32-kbd-hook.c')) +if have_system + stub_ss.add(files('semihost.c')) +endif diff --git a/trace/Makefile.objs b/trace/Makefile.objs index c544509adf..a429474618 100644 --- a/trace/Makefile.objs +++ b/trace/Makefile.objs @@ -1,59 +1,8 @@ # -*- mode: makefile -*- -$(BUILD_DIR)/trace-events-all: $(trace-events-files) - $(call quiet-command,cat $^ > $@) - ################################################## # Translation level -$(obj)/generated-helpers-wrappers.h: $(obj)/generated-helpers-wrappers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -$(obj)/generated-helpers-wrappers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-wrapper-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -$(obj)/generated-helpers.h: $(obj)/generated-helpers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -$(obj)/generated-helpers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -$(obj)/generated-helpers.c: $(obj)/generated-helpers.c-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -$(obj)/generated-helpers.c-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-c \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -$(obj)/generated-helpers.o: $(obj)/generated-helpers.c - obj-y += generated-helpers.o - - -$(obj)/generated-tcg-tracers.h: $(obj)/generated-tcg-tracers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -$(obj)/generated-tcg-tracers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - - -###################################################################### -# Backend code - -util-obj-$(CONFIG_TRACE_SIMPLE) += simple.o -util-obj-$(CONFIG_TRACE_FTRACE) += ftrace.o -util-obj-y += control.o obj-y += control-target.o -util-obj-y += qmp.o diff --git a/trace/meson.build b/trace/meson.build new file mode 100644 index 0000000000..f0a8d1c2e2 --- /dev/null +++ b/trace/meson.build @@ -0,0 +1,76 @@ +trace_events_files = [] +foreach dir : [ '.' ] + trace_events_subdirs + trace_events_file = meson.source_root() / dir / 'trace-events' + trace_events_files += [ trace_events_file ] + group_name = dir == '.' ? 'root' : dir.underscorify() + group = '--group=' + group_name + fmt = '@0@-' + group_name + '.@1@' + + trace_h = custom_target(fmt.format('trace', 'h'), + output: fmt.format('trace', 'h'), + input: trace_events_file, + command: [ tracetool, group, '--format=h', '@INPUT@' ], + capture: true) + genh += trace_h + trace_c = custom_target(fmt.format('trace', 'c'), + output: fmt.format('trace', 'c'), + input: trace_events_file, + command: [ tracetool, group, '--format=c', '@INPUT@' ], + capture: true) + if 'CONFIG_TRACE_UST' in config_host + trace_ust_h = custom_target(fmt.format('trace-ust', 'h'), + output: fmt.format('trace-ust', 'h'), + input: trace_events_file, + command: [ tracetool, group, '--format=ust-events-h', '@INPUT@' ], + capture: true) + trace_ss.add(trace_ust_h, lttng, urcubp) + genh += trace_ust_h + endif + trace_ss.add(trace_h, trace_c) + if 'CONFIG_TRACE_DTRACE' in config_host + trace_dtrace = custom_target(fmt.format('trace-dtrace', 'dtrace'), + output: fmt.format('trace-dtrace', 'dtrace'), + input: trace_events_file, + command: [ tracetool, group, '--format=d', '@INPUT@' ], + capture: true) + trace_dtrace_h = custom_target(fmt.format('trace-dtrace', 'h'), + output: fmt.format('trace-dtrace', 'h'), + input: trace_dtrace, + command: [ 'dtrace', '-o', '@OUTPUT@', '-h', '-s', '@INPUT@' ]) + trace_dtrace_o = custom_target(fmt.format('trace-dtrace', 'o'), + output: fmt.format('trace-dtrace', 'o'), + input: trace_dtrace, + command: [ 'dtrace', '-o', '@OUTPUT@', '-G', '-s', '@INPUT@' ]) + + trace_ss.add(trace_dtrace_h, trace_dtrace_o) + genh += trace_dtrace_h + endif +endforeach + +custom_target('trace-events-all', + output: 'trace-events-all', + input: trace_events_files, + command: [ 'cat', '@INPUT@' ], + capture: true, + install: true, + install_dir: config_host['qemu_datadir']) + +if 'CONFIG_TRACE_UST' in config_host + trace_ust_all_h = custom_target('trace-ust-all.h', + output: 'trace-ust-all.h', + input: trace_events_files, + command: [ tracetool, '--group=all', '--format=ust-events-h', '@INPUT@' ], + capture: true) + trace_ust_all_c = custom_target('trace-ust-all.c', + output: 'trace-ust-all.c', + input: trace_events_files, + command: [ tracetool, '--group=all', '--format=ust-events-c', '@INPUT@' ], + capture: true) + trace_ss.add(trace_ust_all_h, trace_ust_all_c) + genh += trace_ust_all_h +endif + +trace_ss.add(when: 'CONFIG_TRACE_SIMPLE', if_true: files('simple.c')) +trace_ss.add(when: 'CONFIG_TRACE_FTRACE', if_true: files('ftrace.c')) +trace_ss.add(files('control.c')) +trace_ss.add(files('qmp.c')) diff --git a/util/Makefile.objs b/util/Makefile.objs deleted file mode 100644 index cc5e37177a..0000000000 --- a/util/Makefile.objs +++ /dev/null @@ -1,83 +0,0 @@ -util-obj-y = osdep.o cutils.o unicode.o qemu-timer-common.o -util-obj-$(call lnot,$(CONFIG_ATOMIC64)) += atomic64.o -util-obj-$(CONFIG_POSIX) += aio-posix.o -util-obj-$(CONFIG_POSIX) += fdmon-poll.o -util-obj-$(CONFIG_EPOLL_CREATE1) += fdmon-epoll.o -util-obj-$(CONFIG_LINUX_IO_URING) += fdmon-io_uring.o -util-obj-$(CONFIG_POSIX) += compatfd.o -util-obj-$(CONFIG_POSIX) += event_notifier-posix.o -util-obj-$(CONFIG_POSIX) += mmap-alloc.o -util-obj-$(CONFIG_POSIX) += oslib-posix.o -util-obj-$(CONFIG_POSIX) += qemu-openpty.o -util-obj-$(CONFIG_POSIX) += qemu-thread-posix.o -util-obj-$(CONFIG_POSIX) += memfd.o -util-obj-$(CONFIG_WIN32) += aio-win32.o -util-obj-$(CONFIG_WIN32) += event_notifier-win32.o -util-obj-$(CONFIG_WIN32) += oslib-win32.o -util-obj-$(CONFIG_WIN32) += qemu-thread-win32.o -util-obj-y += envlist.o path.o module.o -util-obj-y += host-utils.o -util-obj-y += bitmap.o bitops.o -util-obj-y += fifo8.o -util-obj-y += cacheinfo.o -util-obj-y += error.o qemu-error.o -util-obj-y += qemu-print.o -util-obj-y += id.o -util-obj-y += qemu-config.o notify.o -util-obj-y += qemu-option.o qemu-progress.o -util-obj-y += keyval.o -util-obj-y += crc32c.o -util-obj-y += uuid.o -util-obj-y += getauxval.o -util-obj-y += rcu.o -util-obj-$(CONFIG_MEMBARRIER) += sys_membarrier.o -util-obj-y += log.o -util-obj-y += pagesize.o -util-obj-y += qdist.o -util-obj-y += qht.o -util-obj-y += qsp.o -util-obj-y += range.o -util-obj-y += stats64.o -util-obj-y += systemd.o -util-obj-$(CONFIG_POSIX) += drm.o -util-obj-y += guest-random.o -util-obj-$(CONFIG_GIO) += dbus.o -dbus.o-cflags = $(GIO_CFLAGS) -dbus.o-libs = $(GIO_LIBS) -util-obj-$(CONFIG_USER_ONLY) += selfmap.o - -####################################################################### -# code used by both qemu system emulation and qemu-img - -ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) - -util-obj-y += aio-wait.o -util-obj-y += aiocb.o -util-obj-y += async.o -util-obj-y += base64.o -util-obj-y += buffer.o -util-obj-y += bufferiszero.o -util-obj-y += coroutine-$(CONFIG_COROUTINE_BACKEND).o -util-obj-y += hexdump.o -util-obj-y += lockcnt.o -util-obj-y += iov.o -util-obj-y += iova-tree.o -util-obj-y += hbitmap.o -util-obj-y += main-loop.o -util-obj-y += nvdimm-utils.o -util-obj-y += qemu-coroutine.o qemu-coroutine-lock.o qemu-coroutine-io.o -util-obj-y += qemu-coroutine-sleep.o -util-obj-y += qemu-co-shared-resource.o -util-obj-y += qemu-sockets.o -util-obj-y += qemu-timer.o -util-obj-y += thread-pool.o -util-obj-y += throttle.o -util-obj-y += timed-average.o -util-obj-y += uri.o - -util-obj-$(CONFIG_LINUX) += vfio-helpers.o -util-obj-$(CONFIG_INOTIFY1) += filemonitor-inotify.o -util-obj-$(call lnot,$(CONFIG_INOTIFY1)) += filemonitor-stub.o -util-obj-$(CONFIG_BLOCK) += readline.o - -endif # CONFIG_SOFTMMU || CONFIG_TOOLS diff --git a/util/meson.build b/util/meson.build new file mode 100644 index 0000000000..23b8ad459b --- /dev/null +++ b/util/meson.build @@ -0,0 +1,78 @@ +util_ss.add(dependency('threads')) +util_ss.add(files('osdep.c', 'cutils.c', 'unicode.c', 'qemu-timer-common.c')) +util_ss.add(when: 'CONFIG_ATOMIC64', if_false: files('atomic64.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('aio-posix.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('fdmon-poll.c')) +util_ss.add(when: 'CONFIG_EPOLL_CREATE1', if_true: files('fdmon-epoll.c')) +util_ss.add(when: 'CONFIG_LINUX_IO_URING', if_true: files('fdmon-io_uring.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('compatfd.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('event_notifier-posix.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('mmap-alloc.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('oslib-posix.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: [files('qemu-openpty.c'), util]) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('qemu-thread-posix.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('memfd.c')) +util_ss.add(when: 'CONFIG_WIN32', if_true: files('aio-win32.c')) +util_ss.add(when: 'CONFIG_WIN32', if_true: files('event_notifier-win32.c')) +util_ss.add(when: 'CONFIG_WIN32', if_true: files('oslib-win32.c')) +util_ss.add(when: 'CONFIG_WIN32', if_true: files('qemu-thread-win32.c')) +util_ss.add(when: 'CONFIG_WIN32', if_true: winmm) +util_ss.add(files('envlist.c', 'path.c', 'module.c')) +util_ss.add(files('host-utils.c')) +util_ss.add(files('bitmap.c', 'bitops.c')) +util_ss.add(files('fifo8.c')) +util_ss.add(files('cacheinfo.c')) +util_ss.add(files('error.c', 'qemu-error.c')) +util_ss.add(files('qemu-print.c')) +util_ss.add(files('id.c')) +util_ss.add(files('qemu-config.c', 'notify.c')) +util_ss.add(files('qemu-option.c', 'qemu-progress.c')) +util_ss.add(files('keyval.c')) +util_ss.add(files('crc32c.c')) +util_ss.add(files('uuid.c')) +util_ss.add(files('getauxval.c')) +util_ss.add(files('rcu.c')) +util_ss.add(when: 'CONFIG_MEMBARRIER', if_true: files('sys_membarrier.c')) +util_ss.add(files('log.c')) +util_ss.add(files('pagesize.c')) +util_ss.add(files('qdist.c')) +util_ss.add(files('qht.c')) +util_ss.add(files('qsp.c')) +util_ss.add(files('range.c')) +util_ss.add(files('stats64.c')) +util_ss.add(files('systemd.c')) +util_ss.add(when: 'CONFIG_POSIX', if_true: files('drm.c')) +util_ss.add(files('guest-random.c')) + +if have_user + util_ss.add(files('selfmap.c')) +endif + +if have_system + util_ss.add(when: 'CONFIG_GIO', if_true: [files('dbus.c'), gio]) +endif + +if have_block + util_ss.add(files('aiocb.c', 'async.c', 'aio-wait.c')) + util_ss.add(files('base64.c')) + util_ss.add(files('buffer.c')) + util_ss.add(files('bufferiszero.c')) + util_ss.add(files('coroutine-@0@.c'.format(config_host['CONFIG_COROUTINE_BACKEND']))) + util_ss.add(files('hbitmap.c')) + util_ss.add(files('hexdump.c')) + util_ss.add(files('iova-tree.c')) + util_ss.add(files('iov.c', 'qemu-sockets.c', 'uri.c')) + util_ss.add(files('lockcnt.c')) + util_ss.add(files('main-loop.c')) + util_ss.add(files('nvdimm-utils.c')) + util_ss.add(files('qemu-coroutine.c', 'qemu-coroutine-lock.c', 'qemu-coroutine-io.c')) + util_ss.add(files('qemu-coroutine-sleep.c')) + util_ss.add(files('qemu-co-shared-resource.c')) + util_ss.add(files('thread-pool.c', 'qemu-timer.c')) + util_ss.add(files('readline.c')) + util_ss.add(files('throttle.c')) + util_ss.add(files('timed-average.c')) + util_ss.add(when: 'CONFIG_INOTIFY1', if_true: files('filemonitor-inotify.c'), + if_false: files('filemonitor-stub.c')) + util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c')) +endif -- cgit v1.2.3-55-g7522 From 71c782f5cc18915e6ebf62e28df7ec371388fa71 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 18:48:06 +0400 Subject: meson: add remaining generated tcg trace helpers Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 51 --------------------------------------------------- trace/meson.build | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 51 deletions(-) diff --git a/Makefile b/Makefile index e5d217d4d2..5731d739f1 100644 --- a/Makefile +++ b/Makefile @@ -137,61 +137,10 @@ FULL_VERSION := $(if $(QEMU_PKGVERSION),$(VERSION) ($(QEMU_PKGVERSION)),$(VERSIO generated-files-y = qemu-version.h config-host.h qemu-options.def -generated-files-y += trace/generated-tcg-tracers.h - -generated-files-y += trace/generated-helpers-wrappers.h -generated-files-y += trace/generated-helpers.h -generated-files-y += trace/generated-helpers.c - generated-files-y += module_block.h generated-files-y += .git-submodule-status -tracetool-y = $(SRC_PATH)/scripts/tracetool.py -tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") - -trace/generated-helpers-wrappers.h: trace/generated-helpers-wrappers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/generated-helpers-wrappers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - @mkdir -p $(dir $@) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-wrapper-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -trace/generated-helpers.h: trace/generated-helpers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/generated-helpers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - @mkdir -p $(dir $@) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -trace/generated-helpers.c: trace/generated-helpers.c-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/generated-helpers.c-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - @mkdir -p $(dir $@) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-helper-c \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - -trace/generated-helpers.o: trace/generated-helpers.c - -trace/generated-tcg-tracers.h: trace/generated-tcg-tracers.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -trace/generated-tcg-tracers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak $(tracetool-y) - @mkdir -p $(dir $@) - $(call quiet-command,$(TRACETOOL) \ - --group=root \ - --format=tcg-h \ - --backend=$(TRACE_BACKENDS) \ - $< > $@,"GEN","$(patsubst %-timestamp,%,$@)") - KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv diff --git a/trace/meson.build b/trace/meson.build index f0a8d1c2e2..cab36a248b 100644 --- a/trace/meson.build +++ b/trace/meson.build @@ -55,6 +55,20 @@ custom_target('trace-events-all', install: true, install_dir: config_host['qemu_datadir']) +foreach d : [ + ['generated-tcg-tracers.h', 'tcg-h'], + ['generated-helpers.c', 'tcg-helper-c'], + ['generated-helpers.h', 'tcg-helper-h'], + ['generated-helpers-wrappers.h', 'tcg-helper-wrapper-h'], +] + custom_target(d[0], + output: d[0], + input: meson.source_root() / 'trace-events', + command: [ tracetool, '--group=root', '--format=@0@'.format(d[1]), '@INPUT@' ], + build_by_default: true, # to be removed when added to a target + capture: true) +endforeach + if 'CONFIG_TRACE_UST' in config_host trace_ust_all_h = custom_target('trace-ust-all.h', output: 'trace-ust-all.h', -- cgit v1.2.3-55-g7522 From 04c6f1e798fc0f0f344e49b543a8334d9972d6c2 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 18 Jul 2019 00:31:05 +0400 Subject: meson: add version.o Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- meson.build | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 4e9eb5da5c..feb3c8a30c 100644 --- a/meson.build +++ b/meson.build @@ -49,8 +49,14 @@ targetos = host_machine.system() m = cc.find_library('m', required: false) util = cc.find_library('util', required: false) socket = [] +version_res = [] if targetos == 'windows' socket = cc.find_library('ws2_32') + + win = import('windows') + version_res = win.compile_resources('version.rc', + depend_files: files('pc-bios/qemu-nsis.ico'), + include_directories: include_directories('.')) endif glib = declare_dependency(compile_args: config_host['GLIB_CFLAGS'].split(), link_args: config_host['GLIB_LIBS'].split()) @@ -235,7 +241,7 @@ libqemuutil = static_library('qemuutil', sources: util_ss.sources() + stub_ss.sources() + genh, dependencies: [util_ss.dependencies(), m, glib, socket]) qemuutil = declare_dependency(link_with: libqemuutil, - sources: genh) + sources: genh + version_res) summary_info = {} summary_info += {'Install prefix': config_host['prefix']} -- cgit v1.2.3-55-g7522 From 931049b46cb58a499a36d8a1d0ac3f7b334e0876 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 5 Feb 2020 09:44:24 +0100 Subject: contrib/libvhost-user: convert to Meson Since libqemuutil.a has been converted to Meson, the conversion is straightforward. Signed-off-by: Paolo Bonzini --- Makefile | 16 +++++----------- Makefile.objs | 1 - contrib/libvhost-user/Makefile.objs | 1 - contrib/libvhost-user/meson.build | 3 +++ meson.build | 8 ++++++++ 5 files changed, 16 insertions(+), 13 deletions(-) delete mode 100644 contrib/libvhost-user/Makefile.objs create mode 100644 contrib/libvhost-user/meson.build diff --git a/Makefile b/Makefile index 5731d739f1..78d3a78e97 100644 --- a/Makefile +++ b/Makefile @@ -318,7 +318,6 @@ dummy := $(call unnest-vars,, \ ivshmem-server-obj-y \ virtiofsd-obj-y \ rdmacm-mux-obj-y \ - libvhost-user-obj-y \ vhost-user-scsi-obj-y \ vhost-user-blk-obj-y \ vhost-user-input-obj-y \ @@ -443,11 +442,6 @@ $(BUILD_DIR)/version.o: $(SRC_PATH)/version.rc config-host.h Makefile: $(version-obj-y) -###################################################################### -# Build libraries - -libvhost-user.a: $(libvhost-user-obj-y) - ###################################################################### COMMON_LDADDS = libqemuutil.a @@ -546,9 +540,9 @@ ivshmem-client$(EXESUF): $(ivshmem-client-obj-y) $(COMMON_LDADDS) ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) libvhost-user.a $(COMMON_LDADDS) +vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) -vhost-user-blk$(EXESUF): $(vhost-user-blk-obj-y) libvhost-user.a $(COMMON_LDADDS) +vhost-user-blk$(EXESUF): $(vhost-user-blk-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) rdmacm-mux$(EXESUF): LIBS += "-libumad" @@ -557,16 +551,16 @@ rdmacm-mux$(EXESUF): $(rdmacm-mux-obj-y) $(COMMON_LDADDS) # relies on Linux-specific syscalls ifeq ($(CONFIG_LINUX)$(CONFIG_SECCOMP)$(CONFIG_LIBCAP_NG),yyy) -virtiofsd$(EXESUF): $(virtiofsd-obj-y) libvhost-user.a $(COMMON_LDADDS) +virtiofsd$(EXESUF): $(virtiofsd-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) libvhost-user.a $(COMMON_LDADDS) +vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) ifdef CONFIG_VHOST_USER_INPUT ifdef CONFIG_LINUX -vhost-user-input$(EXESUF): $(vhost-user-input-obj-y) libvhost-user.a $(COMMON_LDADDS) +vhost-user-input$(EXESUF): $(vhost-user-input-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) # build by default, do not install diff --git a/Makefile.objs b/Makefile.objs index e5c9077517..9489864967 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -106,7 +106,6 @@ qga-vss-dll-obj-y = qga/ elf2dmp-obj-y = contrib/elf2dmp/ ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ -libvhost-user-obj-y = contrib/libvhost-user/ vhost-user-scsi.o-cflags := $(LIBISCSI_CFLAGS) vhost-user-scsi.o-libs := $(LIBISCSI_LIBS) vhost-user-scsi-obj-y = contrib/vhost-user-scsi/ diff --git a/contrib/libvhost-user/Makefile.objs b/contrib/libvhost-user/Makefile.objs deleted file mode 100644 index ef3778edd4..0000000000 --- a/contrib/libvhost-user/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -libvhost-user-obj-y += libvhost-user.o libvhost-user-glib.o diff --git a/contrib/libvhost-user/meson.build b/contrib/libvhost-user/meson.build new file mode 100644 index 0000000000..e68dd1a581 --- /dev/null +++ b/contrib/libvhost-user/meson.build @@ -0,0 +1,3 @@ +libvhost_user = static_library('vhost-user', + files('libvhost-user.c', 'libvhost-user-glib.c'), + build_by_default: false) diff --git a/meson.build b/meson.build index feb3c8a30c..00f17ef36f 100644 --- a/meson.build +++ b/meson.build @@ -243,6 +243,14 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +# Other build targets + +if have_tools + if 'CONFIG_VHOST_USER' in config_host + subdir('contrib/libvhost-user') + endif +endif + summary_info = {} summary_info += {'Install prefix': config_host['prefix']} summary_info += {'BIOS directory': config_host['qemu_datadir']} -- cgit v1.2.3-55-g7522 From 3f99cf5710d77ce218116d1b6bb9682c466bbde1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 5 Feb 2020 09:45:39 +0100 Subject: tools/virtiofsd: convert to Meson Signed-off-by: Paolo Bonzini --- Makefile | 12 --- Makefile.objs | 1 - configure | 1 + meson.build | 11 +++ tools/meson.build | 10 ++ tools/virtiofsd/Makefile.objs | 12 --- tools/virtiofsd/meson.build | 19 ++++ tools/virtiofsd/passthrough_ll.c | 2 +- tools/virtiofsd/passthrough_seccomp.c | 172 ++++++++++++++++++++++++++++++++++ tools/virtiofsd/passthrough_seccomp.h | 16 ++++ tools/virtiofsd/seccomp.c | 172 ---------------------------------- tools/virtiofsd/seccomp.h | 16 ---- 12 files changed, 230 insertions(+), 214 deletions(-) create mode 100644 tools/meson.build delete mode 100644 tools/virtiofsd/Makefile.objs create mode 100644 tools/virtiofsd/meson.build create mode 100644 tools/virtiofsd/passthrough_seccomp.c create mode 100644 tools/virtiofsd/passthrough_seccomp.h delete mode 100644 tools/virtiofsd/seccomp.c delete mode 100644 tools/virtiofsd/seccomp.h diff --git a/Makefile b/Makefile index 78d3a78e97..e591d1b2b4 100644 --- a/Makefile +++ b/Makefile @@ -205,11 +205,6 @@ HELPERS-y += vhost-user-gpu$(EXESUF) vhost-user-json-y += contrib/vhost-user-gpu/50-qemu-gpu.json endif -ifeq ($(CONFIG_SOFTMMU)$(CONFIG_LINUX)$(CONFIG_SECCOMP)$(CONFIG_LIBCAP_NG),yyyy) -HELPERS-y += virtiofsd$(EXESUF) -vhost-user-json-y += tools/virtiofsd/50-qemu-virtiofsd.json -endif - # Sphinx does not allow building manuals into the same directory as # the source files, so if we're doing an in-tree QEMU build we must # build the manuals into a subdirectory (and then install them from @@ -316,7 +311,6 @@ dummy := $(call unnest-vars,, \ elf2dmp-obj-y \ ivshmem-client-obj-y \ ivshmem-server-obj-y \ - virtiofsd-obj-y \ rdmacm-mux-obj-y \ vhost-user-scsi-obj-y \ vhost-user-blk-obj-y \ @@ -549,12 +543,6 @@ rdmacm-mux$(EXESUF): LIBS += "-libumad" rdmacm-mux$(EXESUF): $(rdmacm-mux-obj-y) $(COMMON_LDADDS) $(call LINK, $^) -# relies on Linux-specific syscalls -ifeq ($(CONFIG_LINUX)$(CONFIG_SECCOMP)$(CONFIG_LIBCAP_NG),yyy) -virtiofsd$(EXESUF): $(virtiofsd-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) - $(call LINK, $^) -endif - vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) diff --git a/Makefile.objs b/Makefile.objs index 9489864967..fee0f71372 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -113,6 +113,5 @@ vhost-user-blk-obj-y = contrib/vhost-user-blk/ rdmacm-mux-obj-y = contrib/rdmacm-mux/ vhost-user-input-obj-y = contrib/vhost-user-input/ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ -virtiofsd-obj-y = tools/virtiofsd/ ###################################################################### diff --git a/configure b/configure index 75ffe30d75..4d8936ee59 100755 --- a/configure +++ b/configure @@ -7047,6 +7047,7 @@ if test "$gprof" = "yes" ; then fi if test "$cap_ng" = "yes" ; then echo "CONFIG_LIBCAP_NG=y" >> $config_host_mak + echo "LIBCAP_NG_LIBS=$cap_libs" >> $config_host_mak fi echo "CONFIG_AUDIO_DRIVERS=$audio_drv_list" >> $config_host_mak for drv in $audio_drv_list; do diff --git a/meson.build b/meson.build index 00f17ef36f..00970e6e19 100644 --- a/meson.build +++ b/meson.build @@ -83,6 +83,15 @@ if 'CONFIG_GNUTLS' in config_host gnutls = declare_dependency(compile_args: config_host['GNUTLS_CFLAGS'].split(), link_args: config_host['GNUTLS_LIBS'].split()) endif +seccomp = not_found +if 'CONFIG_SECCOMP' in config_host + seccomp = declare_dependency(compile_args: config_host['SECCOMP_CFLAGS'].split(), + link_args: config_host['SECCOMP_LIBS'].split()) +endif +libcap_ng = not_found +if 'CONFIG_LIBCAP_NG' in config_host + libcap_ng = declare_dependency(link_args: config_host['LIBCAP_NG_LIBS'].split()) +endif target_dirs = config_host['TARGET_DIRS'].split() have_user = false @@ -251,6 +260,8 @@ if have_tools endif endif +subdir('tools') + summary_info = {} summary_info += {'Install prefix': config_host['prefix']} summary_info += {'BIOS directory': config_host['qemu_datadir']} diff --git a/tools/meson.build b/tools/meson.build new file mode 100644 index 0000000000..513bd2ff4f --- /dev/null +++ b/tools/meson.build @@ -0,0 +1,10 @@ +have_virtiofsd = (have_system and + have_tools and + 'CONFIG_LINUX' in config_host and + 'CONFIG_SECCOMP' in config_host and + 'CONFIG_LIBCAP_NG' in config_host and + 'CONFIG_VHOST_USER' in config_host) + +if have_virtiofsd + subdir('virtiofsd') +endif diff --git a/tools/virtiofsd/Makefile.objs b/tools/virtiofsd/Makefile.objs deleted file mode 100644 index 076f667e46..0000000000 --- a/tools/virtiofsd/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -virtiofsd-obj-y = buffer.o \ - fuse_opt.o \ - fuse_log.o \ - fuse_lowlevel.o \ - fuse_signals.o \ - fuse_virtio.o \ - helper.o \ - passthrough_ll.o \ - seccomp.o - -seccomp.o-cflags := $(SECCOMP_CFLAGS) -seccomp.o-libs := $(SECCOMP_LIBS) diff --git a/tools/virtiofsd/meson.build b/tools/virtiofsd/meson.build new file mode 100644 index 0000000000..d1e23c5760 --- /dev/null +++ b/tools/virtiofsd/meson.build @@ -0,0 +1,19 @@ +executable('virtiofsd', files( + 'buffer.c', + 'fuse_opt.c', + 'fuse_log.c', + 'fuse_lowlevel.c', + 'fuse_signals.c', + 'fuse_virtio.c', + 'helper.c', + 'passthrough_ll.c', + 'passthrough_seccomp.c'), + link_with: libvhost_user, + dependencies: [seccomp, qemuutil, libcap_ng], + install: true, + install_dir: get_option('libexecdir')) + +configure_file(input: '50-qemu-virtiofsd.json.in', + output: '50-qemu-virtiofsd.json', + configuration: config_host, + install_dir: config_host['qemu_datadir'] / 'vhost-user') diff --git a/tools/virtiofsd/passthrough_ll.c b/tools/virtiofsd/passthrough_ll.c index 94e0de2d2b..63d1d00565 100644 --- a/tools/virtiofsd/passthrough_ll.c +++ b/tools/virtiofsd/passthrough_ll.c @@ -65,7 +65,7 @@ #include #include "passthrough_helpers.h" -#include "seccomp.h" +#include "passthrough_seccomp.h" /* Keep track of inode posix locks for each owner. */ struct lo_inode_plock { diff --git a/tools/virtiofsd/passthrough_seccomp.c b/tools/virtiofsd/passthrough_seccomp.c new file mode 100644 index 0000000000..19fee60011 --- /dev/null +++ b/tools/virtiofsd/passthrough_seccomp.c @@ -0,0 +1,172 @@ +/* + * Seccomp sandboxing for virtiofsd + * + * Copyright (C) 2019 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "passthrough_seccomp.h" +#include "fuse_i.h" +#include "fuse_log.h" +#include +#include +#include +#include + +/* Bodge for libseccomp 2.4.2 which broke ppoll */ +#if !defined(__SNR_ppoll) && defined(__SNR_brk) +#ifdef __NR_ppoll +#define __SNR_ppoll __NR_ppoll +#else +#define __SNR_ppoll __PNR_ppoll +#endif +#endif + +static const int syscall_whitelist[] = { + /* TODO ireg sem*() syscalls */ + SCMP_SYS(brk), + SCMP_SYS(capget), /* For CAP_FSETID */ + SCMP_SYS(capset), + SCMP_SYS(clock_gettime), + SCMP_SYS(clone), +#ifdef __NR_clone3 + SCMP_SYS(clone3), +#endif + SCMP_SYS(close), + SCMP_SYS(copy_file_range), + SCMP_SYS(dup), + SCMP_SYS(eventfd2), + SCMP_SYS(exit), + SCMP_SYS(exit_group), + SCMP_SYS(fallocate), + SCMP_SYS(fchdir), + SCMP_SYS(fchmod), + SCMP_SYS(fchmodat), + SCMP_SYS(fchownat), + SCMP_SYS(fcntl), + SCMP_SYS(fdatasync), + SCMP_SYS(fgetxattr), + SCMP_SYS(flistxattr), + SCMP_SYS(flock), + SCMP_SYS(fremovexattr), + SCMP_SYS(fsetxattr), + SCMP_SYS(fstat), + SCMP_SYS(fstatfs), + SCMP_SYS(fsync), + SCMP_SYS(ftruncate), + SCMP_SYS(futex), + SCMP_SYS(getdents), + SCMP_SYS(getdents64), + SCMP_SYS(getegid), + SCMP_SYS(geteuid), + SCMP_SYS(getpid), + SCMP_SYS(gettid), + SCMP_SYS(gettimeofday), + SCMP_SYS(getxattr), + SCMP_SYS(linkat), + SCMP_SYS(listxattr), + SCMP_SYS(lseek), + SCMP_SYS(madvise), + SCMP_SYS(mkdirat), + SCMP_SYS(mknodat), + SCMP_SYS(mmap), + SCMP_SYS(mprotect), + SCMP_SYS(mremap), + SCMP_SYS(munmap), + SCMP_SYS(newfstatat), + SCMP_SYS(open), + SCMP_SYS(openat), + SCMP_SYS(ppoll), + SCMP_SYS(prctl), /* TODO restrict to just PR_SET_NAME? */ + SCMP_SYS(preadv), + SCMP_SYS(pread64), + SCMP_SYS(pwritev), + SCMP_SYS(pwrite64), + SCMP_SYS(read), + SCMP_SYS(readlinkat), + SCMP_SYS(recvmsg), + SCMP_SYS(renameat), + SCMP_SYS(renameat2), + SCMP_SYS(removexattr), + SCMP_SYS(rt_sigaction), + SCMP_SYS(rt_sigprocmask), + SCMP_SYS(rt_sigreturn), + SCMP_SYS(sendmsg), + SCMP_SYS(setresgid), + SCMP_SYS(setresuid), +#ifdef __NR_setresgid32 + SCMP_SYS(setresgid32), +#endif +#ifdef __NR_setresuid32 + SCMP_SYS(setresuid32), +#endif + SCMP_SYS(set_robust_list), + SCMP_SYS(setxattr), + SCMP_SYS(symlinkat), + SCMP_SYS(time), /* Rarely needed, except on static builds */ + SCMP_SYS(tgkill), + SCMP_SYS(unlinkat), + SCMP_SYS(unshare), + SCMP_SYS(utimensat), + SCMP_SYS(write), + SCMP_SYS(writev), +}; + +/* Syscalls used when --syslog is enabled */ +static const int syscall_whitelist_syslog[] = { + SCMP_SYS(sendto), +}; + +static void add_whitelist(scmp_filter_ctx ctx, const int syscalls[], size_t len) +{ + size_t i; + + for (i = 0; i < len; i++) { + if (seccomp_rule_add(ctx, SCMP_ACT_ALLOW, syscalls[i], 0) != 0) { + fuse_log(FUSE_LOG_ERR, "seccomp_rule_add syscall %d failed\n", + syscalls[i]); + exit(1); + } + } +} + +void setup_seccomp(bool enable_syslog) +{ + scmp_filter_ctx ctx; + +#ifdef SCMP_ACT_KILL_PROCESS + ctx = seccomp_init(SCMP_ACT_KILL_PROCESS); + /* Handle a newer libseccomp but an older kernel */ + if (!ctx && errno == EOPNOTSUPP) { + ctx = seccomp_init(SCMP_ACT_TRAP); + } +#else + ctx = seccomp_init(SCMP_ACT_TRAP); +#endif + if (!ctx) { + fuse_log(FUSE_LOG_ERR, "seccomp_init() failed\n"); + exit(1); + } + + add_whitelist(ctx, syscall_whitelist, G_N_ELEMENTS(syscall_whitelist)); + if (enable_syslog) { + add_whitelist(ctx, syscall_whitelist_syslog, + G_N_ELEMENTS(syscall_whitelist_syslog)); + } + + /* libvhost-user calls this for post-copy migration, we don't need it */ + if (seccomp_rule_add(ctx, SCMP_ACT_ERRNO(ENOSYS), + SCMP_SYS(userfaultfd), 0) != 0) { + fuse_log(FUSE_LOG_ERR, "seccomp_rule_add userfaultfd failed\n"); + exit(1); + } + + if (seccomp_load(ctx) < 0) { + fuse_log(FUSE_LOG_ERR, "seccomp_load() failed\n"); + exit(1); + } + + seccomp_release(ctx); +} diff --git a/tools/virtiofsd/passthrough_seccomp.h b/tools/virtiofsd/passthrough_seccomp.h new file mode 100644 index 0000000000..d47c8eade6 --- /dev/null +++ b/tools/virtiofsd/passthrough_seccomp.h @@ -0,0 +1,16 @@ +/* + * Seccomp sandboxing for virtiofsd + * + * Copyright (C) 2019 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VIRTIOFSD_SECCOMP_H +#define VIRTIOFSD_SECCOMP_H + +#include + +void setup_seccomp(bool enable_syslog); + +#endif /* VIRTIOFSD_SECCOMP_H */ diff --git a/tools/virtiofsd/seccomp.c b/tools/virtiofsd/seccomp.c deleted file mode 100644 index 3b1522acdd..0000000000 --- a/tools/virtiofsd/seccomp.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Seccomp sandboxing for virtiofsd - * - * Copyright (C) 2019 Red Hat, Inc. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include "qemu/osdep.h" -#include "seccomp.h" -#include "fuse_i.h" -#include "fuse_log.h" -#include -#include -#include -#include - -/* Bodge for libseccomp 2.4.2 which broke ppoll */ -#if !defined(__SNR_ppoll) && defined(__SNR_brk) -#ifdef __NR_ppoll -#define __SNR_ppoll __NR_ppoll -#else -#define __SNR_ppoll __PNR_ppoll -#endif -#endif - -static const int syscall_whitelist[] = { - /* TODO ireg sem*() syscalls */ - SCMP_SYS(brk), - SCMP_SYS(capget), /* For CAP_FSETID */ - SCMP_SYS(capset), - SCMP_SYS(clock_gettime), - SCMP_SYS(clone), -#ifdef __NR_clone3 - SCMP_SYS(clone3), -#endif - SCMP_SYS(close), - SCMP_SYS(copy_file_range), - SCMP_SYS(dup), - SCMP_SYS(eventfd2), - SCMP_SYS(exit), - SCMP_SYS(exit_group), - SCMP_SYS(fallocate), - SCMP_SYS(fchdir), - SCMP_SYS(fchmod), - SCMP_SYS(fchmodat), - SCMP_SYS(fchownat), - SCMP_SYS(fcntl), - SCMP_SYS(fdatasync), - SCMP_SYS(fgetxattr), - SCMP_SYS(flistxattr), - SCMP_SYS(flock), - SCMP_SYS(fremovexattr), - SCMP_SYS(fsetxattr), - SCMP_SYS(fstat), - SCMP_SYS(fstatfs), - SCMP_SYS(fsync), - SCMP_SYS(ftruncate), - SCMP_SYS(futex), - SCMP_SYS(getdents), - SCMP_SYS(getdents64), - SCMP_SYS(getegid), - SCMP_SYS(geteuid), - SCMP_SYS(getpid), - SCMP_SYS(gettid), - SCMP_SYS(gettimeofday), - SCMP_SYS(getxattr), - SCMP_SYS(linkat), - SCMP_SYS(listxattr), - SCMP_SYS(lseek), - SCMP_SYS(madvise), - SCMP_SYS(mkdirat), - SCMP_SYS(mknodat), - SCMP_SYS(mmap), - SCMP_SYS(mprotect), - SCMP_SYS(mremap), - SCMP_SYS(munmap), - SCMP_SYS(newfstatat), - SCMP_SYS(open), - SCMP_SYS(openat), - SCMP_SYS(ppoll), - SCMP_SYS(prctl), /* TODO restrict to just PR_SET_NAME? */ - SCMP_SYS(preadv), - SCMP_SYS(pread64), - SCMP_SYS(pwritev), - SCMP_SYS(pwrite64), - SCMP_SYS(read), - SCMP_SYS(readlinkat), - SCMP_SYS(recvmsg), - SCMP_SYS(renameat), - SCMP_SYS(renameat2), - SCMP_SYS(removexattr), - SCMP_SYS(rt_sigaction), - SCMP_SYS(rt_sigprocmask), - SCMP_SYS(rt_sigreturn), - SCMP_SYS(sendmsg), - SCMP_SYS(setresgid), - SCMP_SYS(setresuid), -#ifdef __NR_setresgid32 - SCMP_SYS(setresgid32), -#endif -#ifdef __NR_setresuid32 - SCMP_SYS(setresuid32), -#endif - SCMP_SYS(set_robust_list), - SCMP_SYS(setxattr), - SCMP_SYS(symlinkat), - SCMP_SYS(time), /* Rarely needed, except on static builds */ - SCMP_SYS(tgkill), - SCMP_SYS(unlinkat), - SCMP_SYS(unshare), - SCMP_SYS(utimensat), - SCMP_SYS(write), - SCMP_SYS(writev), -}; - -/* Syscalls used when --syslog is enabled */ -static const int syscall_whitelist_syslog[] = { - SCMP_SYS(sendto), -}; - -static void add_whitelist(scmp_filter_ctx ctx, const int syscalls[], size_t len) -{ - size_t i; - - for (i = 0; i < len; i++) { - if (seccomp_rule_add(ctx, SCMP_ACT_ALLOW, syscalls[i], 0) != 0) { - fuse_log(FUSE_LOG_ERR, "seccomp_rule_add syscall %d failed\n", - syscalls[i]); - exit(1); - } - } -} - -void setup_seccomp(bool enable_syslog) -{ - scmp_filter_ctx ctx; - -#ifdef SCMP_ACT_KILL_PROCESS - ctx = seccomp_init(SCMP_ACT_KILL_PROCESS); - /* Handle a newer libseccomp but an older kernel */ - if (!ctx && errno == EOPNOTSUPP) { - ctx = seccomp_init(SCMP_ACT_TRAP); - } -#else - ctx = seccomp_init(SCMP_ACT_TRAP); -#endif - if (!ctx) { - fuse_log(FUSE_LOG_ERR, "seccomp_init() failed\n"); - exit(1); - } - - add_whitelist(ctx, syscall_whitelist, G_N_ELEMENTS(syscall_whitelist)); - if (enable_syslog) { - add_whitelist(ctx, syscall_whitelist_syslog, - G_N_ELEMENTS(syscall_whitelist_syslog)); - } - - /* libvhost-user calls this for post-copy migration, we don't need it */ - if (seccomp_rule_add(ctx, SCMP_ACT_ERRNO(ENOSYS), - SCMP_SYS(userfaultfd), 0) != 0) { - fuse_log(FUSE_LOG_ERR, "seccomp_rule_add userfaultfd failed\n"); - exit(1); - } - - if (seccomp_load(ctx) < 0) { - fuse_log(FUSE_LOG_ERR, "seccomp_load() failed\n"); - exit(1); - } - - seccomp_release(ctx); -} diff --git a/tools/virtiofsd/seccomp.h b/tools/virtiofsd/seccomp.h deleted file mode 100644 index d47c8eade6..0000000000 --- a/tools/virtiofsd/seccomp.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Seccomp sandboxing for virtiofsd - * - * Copyright (C) 2019 Red Hat, Inc. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef VIRTIOFSD_SECCOMP_H -#define VIRTIOFSD_SECCOMP_H - -#include - -void setup_seccomp(bool enable_syslog); - -#endif /* VIRTIOFSD_SECCOMP_H */ -- cgit v1.2.3-55-g7522 From 2d7ac0af9d05e80de9fe9ab20bb188482fbe4810 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Jun 2019 12:18:02 +0200 Subject: contrib/vhost-user-blk: convert to Meson The GLib pkg-config information is extracted from config-host.mak and used to link vhost-user-blk. Signed-off-by: Paolo Bonzini --- Makefile | 3 --- Makefile.objs | 1 - contrib/vhost-user-blk/Makefile.objs | 1 - contrib/vhost-user-blk/meson.build | 6 ++++++ meson.build | 1 + 5 files changed, 7 insertions(+), 5 deletions(-) delete mode 100644 contrib/vhost-user-blk/Makefile.objs create mode 100644 contrib/vhost-user-blk/meson.build diff --git a/Makefile b/Makefile index e591d1b2b4..e387b67a3b 100644 --- a/Makefile +++ b/Makefile @@ -313,7 +313,6 @@ dummy := $(call unnest-vars,, \ ivshmem-server-obj-y \ rdmacm-mux-obj-y \ vhost-user-scsi-obj-y \ - vhost-user-blk-obj-y \ vhost-user-input-obj-y \ vhost-user-gpu-obj-y \ qga-vss-dll-obj-y \ @@ -536,8 +535,6 @@ ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) endif vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) -vhost-user-blk$(EXESUF): $(vhost-user-blk-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) - $(call LINK, $^) rdmacm-mux$(EXESUF): LIBS += "-libumad" rdmacm-mux$(EXESUF): $(rdmacm-mux-obj-y) $(COMMON_LDADDS) diff --git a/Makefile.objs b/Makefile.objs index fee0f71372..f69736c10c 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -109,7 +109,6 @@ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ vhost-user-scsi.o-cflags := $(LIBISCSI_CFLAGS) vhost-user-scsi.o-libs := $(LIBISCSI_LIBS) vhost-user-scsi-obj-y = contrib/vhost-user-scsi/ -vhost-user-blk-obj-y = contrib/vhost-user-blk/ rdmacm-mux-obj-y = contrib/rdmacm-mux/ vhost-user-input-obj-y = contrib/vhost-user-input/ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ diff --git a/contrib/vhost-user-blk/Makefile.objs b/contrib/vhost-user-blk/Makefile.objs deleted file mode 100644 index 72e2cdc3ad..0000000000 --- a/contrib/vhost-user-blk/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -vhost-user-blk-obj-y = vhost-user-blk.o diff --git a/contrib/vhost-user-blk/meson.build b/contrib/vhost-user-blk/meson.build new file mode 100644 index 0000000000..5db8cc3fe2 --- /dev/null +++ b/contrib/vhost-user-blk/meson.build @@ -0,0 +1,6 @@ +# FIXME: broken on 32-bit architectures +executable('vhost-user-blk', files('vhost-user-blk.c'), + link_with: libvhost_user, + dependencies: qemuutil, + build_by_default: false, + install: false) diff --git a/meson.build b/meson.build index 00970e6e19..4343f0be6c 100644 --- a/meson.build +++ b/meson.build @@ -257,6 +257,7 @@ qemuutil = declare_dependency(link_with: libqemuutil, if have_tools if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') + subdir('contrib/vhost-user-blk') endif endif -- cgit v1.2.3-55-g7522 From 7af0dbf990afea54b6c2a186f7b6ec27c87304a8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Aug 2020 21:15:19 +0200 Subject: vhost-user-scsi: add compatibility for libiscsi 1.9.0 Signed-off-by: Paolo Bonzini --- contrib/vhost-user-scsi/vhost-user-scsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/contrib/vhost-user-scsi/vhost-user-scsi.c b/contrib/vhost-user-scsi/vhost-user-scsi.c index 7a1db164c8..3c912384e9 100644 --- a/contrib/vhost-user-scsi/vhost-user-scsi.c +++ b/contrib/vhost-user-scsi/vhost-user-scsi.c @@ -12,7 +12,9 @@ #include "qemu/osdep.h" #include +#define inline __attribute__((gnu_inline)) /* required for libiscsi v1.9.0 */ #include +#undef inline #include "contrib/libvhost-user/libvhost-user-glib.h" #include "standard-headers/linux/virtio_scsi.h" -- cgit v1.2.3-55-g7522 From 99650b628f03564d5c2ac022eb0430ddaab038da Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Jun 2019 12:21:14 +0200 Subject: contrib/vhost-user-scsi: convert to Meson The libiscsi pkg-config information is extracted from config-host.mak and used to link vhost-user-blk. Signed-off-by: Paolo Bonzini --- Makefile | 3 --- Makefile.objs | 3 --- contrib/vhost-user-scsi/Makefile.objs | 1 - contrib/vhost-user-scsi/meson.build | 7 +++++++ meson.build | 6 ++++++ 5 files changed, 13 insertions(+), 7 deletions(-) delete mode 100644 contrib/vhost-user-scsi/Makefile.objs create mode 100644 contrib/vhost-user-scsi/meson.build diff --git a/Makefile b/Makefile index e387b67a3b..1f5a710f77 100644 --- a/Makefile +++ b/Makefile @@ -312,7 +312,6 @@ dummy := $(call unnest-vars,, \ ivshmem-client-obj-y \ ivshmem-server-obj-y \ rdmacm-mux-obj-y \ - vhost-user-scsi-obj-y \ vhost-user-input-obj-y \ vhost-user-gpu-obj-y \ qga-vss-dll-obj-y \ @@ -533,8 +532,6 @@ ivshmem-client$(EXESUF): $(ivshmem-client-obj-y) $(COMMON_LDADDS) ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-scsi$(EXESUF): $(vhost-user-scsi-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) - $(call LINK, $^) rdmacm-mux$(EXESUF): LIBS += "-libumad" rdmacm-mux$(EXESUF): $(rdmacm-mux-obj-y) $(COMMON_LDADDS) diff --git a/Makefile.objs b/Makefile.objs index f69736c10c..ab798b08a7 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -106,9 +106,6 @@ qga-vss-dll-obj-y = qga/ elf2dmp-obj-y = contrib/elf2dmp/ ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ -vhost-user-scsi.o-cflags := $(LIBISCSI_CFLAGS) -vhost-user-scsi.o-libs := $(LIBISCSI_LIBS) -vhost-user-scsi-obj-y = contrib/vhost-user-scsi/ rdmacm-mux-obj-y = contrib/rdmacm-mux/ vhost-user-input-obj-y = contrib/vhost-user-input/ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ diff --git a/contrib/vhost-user-scsi/Makefile.objs b/contrib/vhost-user-scsi/Makefile.objs deleted file mode 100644 index e83a38a85b..0000000000 --- a/contrib/vhost-user-scsi/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -vhost-user-scsi-obj-y = vhost-user-scsi.o diff --git a/contrib/vhost-user-scsi/meson.build b/contrib/vhost-user-scsi/meson.build new file mode 100644 index 0000000000..257cbffc8e --- /dev/null +++ b/contrib/vhost-user-scsi/meson.build @@ -0,0 +1,7 @@ +if 'CONFIG_LIBISCSI' in config_host + executable('vhost-user-scsi', files('vhost-user-scsi.c'), + link_with: libvhost_user, + dependencies: [qemuutil, libiscsi], + build_by_default: targetos == 'linux', + install: false) +endif diff --git a/meson.build b/meson.build index 4343f0be6c..4c067d9fe6 100644 --- a/meson.build +++ b/meson.build @@ -92,6 +92,11 @@ libcap_ng = not_found if 'CONFIG_LIBCAP_NG' in config_host libcap_ng = declare_dependency(link_args: config_host['LIBCAP_NG_LIBS'].split()) endif +libiscsi = not_found +if 'CONFIG_LIBISCSI' in config_host + libiscsi = declare_dependency(compile_args: config_host['LIBISCSI_CFLAGS'].split(), + link_args: config_host['LIBISCSI_LIBS'].split()) +endif target_dirs = config_host['TARGET_DIRS'].split() have_user = false @@ -258,6 +263,7 @@ if have_tools if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') + subdir('contrib/vhost-user-scsi') endif endif -- cgit v1.2.3-55-g7522 From a9c9727c028329e18ee3dcabb75f906147936fac Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Jun 2019 12:27:52 +0200 Subject: contrib/rdmacm-mux: convert to Meson We can use config-host.mak to decide whether the tool has to be built, apart from that the conversion is straightforward. Signed-off-by: Paolo Bonzini --- Makefile | 5 ----- Makefile.objs | 1 - contrib/rdmacm-mux/Makefile.objs | 3 --- contrib/rdmacm-mux/meson.build | 9 +++++++++ meson.build | 2 ++ 5 files changed, 11 insertions(+), 9 deletions(-) delete mode 100644 contrib/rdmacm-mux/Makefile.objs create mode 100644 contrib/rdmacm-mux/meson.build diff --git a/Makefile b/Makefile index 1f5a710f77..ad3d926666 100644 --- a/Makefile +++ b/Makefile @@ -311,7 +311,6 @@ dummy := $(call unnest-vars,, \ elf2dmp-obj-y \ ivshmem-client-obj-y \ ivshmem-server-obj-y \ - rdmacm-mux-obj-y \ vhost-user-input-obj-y \ vhost-user-gpu-obj-y \ qga-vss-dll-obj-y \ @@ -533,10 +532,6 @@ ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) $(call LINK, $^) endif -rdmacm-mux$(EXESUF): LIBS += "-libumad" -rdmacm-mux$(EXESUF): $(rdmacm-mux-obj-y) $(COMMON_LDADDS) - $(call LINK, $^) - vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) diff --git a/Makefile.objs b/Makefile.objs index ab798b08a7..0f80b63554 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -106,7 +106,6 @@ qga-vss-dll-obj-y = qga/ elf2dmp-obj-y = contrib/elf2dmp/ ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ -rdmacm-mux-obj-y = contrib/rdmacm-mux/ vhost-user-input-obj-y = contrib/vhost-user-input/ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ diff --git a/contrib/rdmacm-mux/Makefile.objs b/contrib/rdmacm-mux/Makefile.objs deleted file mode 100644 index 3df744af89..0000000000 --- a/contrib/rdmacm-mux/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -ifdef CONFIG_PVRDMA -rdmacm-mux-obj-y = main.o -endif diff --git a/contrib/rdmacm-mux/meson.build b/contrib/rdmacm-mux/meson.build new file mode 100644 index 0000000000..6cc5016747 --- /dev/null +++ b/contrib/rdmacm-mux/meson.build @@ -0,0 +1,9 @@ +if 'CONFIG_PVRDMA' in config_host + # if not found, CONFIG_PVRDMA should not be set + # FIXME: broken on big endian architectures + libumad = cc.find_library('ibumad', required: true) + executable('rdmacm-mux', files('main.c'), + dependencies: [glib, libumad], + build_by_default: false, + install: false) +endif diff --git a/meson.build b/meson.build index 4c067d9fe6..c60ec5825b 100644 --- a/meson.build +++ b/meson.build @@ -260,6 +260,8 @@ qemuutil = declare_dependency(link_with: libqemuutil, # Other build targets if have_tools + subdir('contrib/rdmacm-mux') + if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') -- cgit v1.2.3-55-g7522 From 32fcc6244c729f6311d2a4c8bd54bb9b7f43786d Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 12 Jul 2019 22:11:20 +0400 Subject: contrib/vhost-user-input: convert to meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 11 ----------- Makefile.objs | 1 - contrib/vhost-user-input/Makefile.objs | 1 - contrib/vhost-user-input/meson.build | 5 +++++ meson.build | 1 + 5 files changed, 6 insertions(+), 13 deletions(-) delete mode 100644 contrib/vhost-user-input/Makefile.objs create mode 100644 contrib/vhost-user-input/meson.build diff --git a/Makefile b/Makefile index ad3d926666..c0cb10cd77 100644 --- a/Makefile +++ b/Makefile @@ -311,7 +311,6 @@ dummy := $(call unnest-vars,, \ elf2dmp-obj-y \ ivshmem-client-obj-y \ ivshmem-server-obj-y \ - vhost-user-input-obj-y \ vhost-user-gpu-obj-y \ qga-vss-dll-obj-y \ block-obj-y \ @@ -535,16 +534,6 @@ endif vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) $(call LINK, $^) -ifdef CONFIG_VHOST_USER_INPUT -ifdef CONFIG_LINUX -vhost-user-input$(EXESUF): $(vhost-user-input-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) - $(call LINK, $^) - -# build by default, do not install -all: vhost-user-input$(EXESUF) -endif -endif - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ diff --git a/Makefile.objs b/Makefile.objs index 0f80b63554..0922c3ed00 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -106,7 +106,6 @@ qga-vss-dll-obj-y = qga/ elf2dmp-obj-y = contrib/elf2dmp/ ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ -vhost-user-input-obj-y = contrib/vhost-user-input/ vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ ###################################################################### diff --git a/contrib/vhost-user-input/Makefile.objs b/contrib/vhost-user-input/Makefile.objs deleted file mode 100644 index b1fad90d51..0000000000 --- a/contrib/vhost-user-input/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -vhost-user-input-obj-y = main.o diff --git a/contrib/vhost-user-input/meson.build b/contrib/vhost-user-input/meson.build new file mode 100644 index 0000000000..1eeb1329d9 --- /dev/null +++ b/contrib/vhost-user-input/meson.build @@ -0,0 +1,5 @@ +executable('vhost-user-input', files('main.c'), + link_with: libvhost_user, + dependencies: qemuutil, + build_by_default: targetos == 'linux', + install: false) diff --git a/meson.build b/meson.build index c60ec5825b..371d571495 100644 --- a/meson.build +++ b/meson.build @@ -265,6 +265,7 @@ if have_tools if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') + subdir('contrib/vhost-user-input') subdir('contrib/vhost-user-scsi') endif endif -- cgit v1.2.3-55-g7522 From ea458960ec37856a7c50337ae3c693022154aaf7 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 12 Jul 2019 22:23:46 +0400 Subject: contrib/vhost-user-gpu: convert to meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 18 +----------------- Makefile.objs | 1 - contrib/vhost-user-gpu/Makefile.objs | 10 ---------- contrib/vhost-user-gpu/meson.build | 13 +++++++++++++ meson.build | 15 +++++++++++++++ rules.mak | 7 ------- 6 files changed, 29 insertions(+), 35 deletions(-) delete mode 100644 contrib/vhost-user-gpu/Makefile.objs create mode 100644 contrib/vhost-user-gpu/meson.build diff --git a/Makefile b/Makefile index c0cb10cd77..ed6494b771 100644 --- a/Makefile +++ b/Makefile @@ -195,16 +195,10 @@ $(call set-vpath, $(SRC_PATH)) LIBS+=-lz $(LIBS_TOOLS) -vhost-user-json-y = HELPERS-y = $(HELPERS) HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) += qemu-bridge-helper$(EXESUF) -ifeq ($(CONFIG_LINUX)$(CONFIG_VIRGL)$(CONFIG_GBM)$(CONFIG_TOOLS),yyyy) -HELPERS-y += vhost-user-gpu$(EXESUF) -vhost-user-json-y += contrib/vhost-user-gpu/50-qemu-gpu.json -endif - # Sphinx does not allow building manuals into the same directory as # the source files, so if we're doing an in-tree QEMU build we must # build the manuals into a subdirectory (and then install them from @@ -311,7 +305,6 @@ dummy := $(call unnest-vars,, \ elf2dmp-obj-y \ ivshmem-client-obj-y \ ivshmem-server-obj-y \ - vhost-user-gpu-obj-y \ qga-vss-dll-obj-y \ block-obj-y \ block-obj-m \ @@ -325,7 +318,7 @@ dummy := $(call unnest-vars,, \ include $(SRC_PATH)/tests/Makefile.include -all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all modules $(vhost-user-json-y) +all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all modules qemu-version.h: FORCE $(call quiet-command, \ @@ -531,9 +524,6 @@ ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) $(call LINK, $^) endif -vhost-user-gpu$(EXESUF): $(vhost-user-gpu-obj-y) contrib/libvhost-user/libvhost-user.a $(COMMON_LDADDS) - $(call LINK, $^) - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ @@ -731,12 +721,6 @@ endif ifneq ($(HELPERS-y),) $(call install-prog,$(HELPERS-y),$(DESTDIR)$(libexecdir)) endif -ifneq ($(vhost-user-json-y),) - $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/vhost-user/" - for x in $(vhost-user-json-y); do \ - $(INSTALL_DATA) $$x "$(DESTDIR)$(qemu_datadir)/vhost-user/"; \ - done -endif ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_PROG) "scripts/qemu-trace-stap" $(DESTDIR)$(bindir) endif diff --git a/Makefile.objs b/Makefile.objs index 0922c3ed00..2f2d4b2066 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -106,6 +106,5 @@ qga-vss-dll-obj-y = qga/ elf2dmp-obj-y = contrib/elf2dmp/ ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ -vhost-user-gpu-obj-y = contrib/vhost-user-gpu/ ###################################################################### diff --git a/contrib/vhost-user-gpu/Makefile.objs b/contrib/vhost-user-gpu/Makefile.objs deleted file mode 100644 index 09296091be..0000000000 --- a/contrib/vhost-user-gpu/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -vhost-user-gpu-obj-y = vhost-user-gpu.o virgl.o vugbm.o - -vhost-user-gpu.o-cflags := $(PIXMAN_CFLAGS) $(GBM_CFLAGS) -vhost-user-gpu.o-libs := $(PIXMAN_LIBS) - -virgl.o-cflags := $(VIRGL_CFLAGS) $(GBM_CFLAGS) -virgl.o-libs := $(VIRGL_LIBS) - -vugbm.o-cflags := $(GBM_CFLAGS) -vugbm.o-libs := $(GBM_LIBS) diff --git a/contrib/vhost-user-gpu/meson.build b/contrib/vhost-user-gpu/meson.build new file mode 100644 index 0000000000..6c1459f54a --- /dev/null +++ b/contrib/vhost-user-gpu/meson.build @@ -0,0 +1,13 @@ +if 'CONFIG_TOOLS' in config_host and 'CONFIG_VIRGL' in config_host \ + and 'CONFIG_GBM' in config_host and 'CONFIG_LINUX' in config_host + executable('vhost-user-gpu', files('vhost-user-gpu.c', 'virgl.c', 'vugbm.c'), + link_with: libvhost_user, + dependencies: [qemuutil, pixman, gbm, virgl], + install: true, + install_dir: get_option('libexecdir')) + + configure_file(input: '50-qemu-gpu.json.in', + output: '50-qemu-gpu.json', + configuration: config_host, + install_dir: config_host['qemu_datadir'] / 'vhost-user') +endif diff --git a/meson.build b/meson.build index 371d571495..71ef66e1d6 100644 --- a/meson.build +++ b/meson.build @@ -83,6 +83,8 @@ if 'CONFIG_GNUTLS' in config_host gnutls = declare_dependency(compile_args: config_host['GNUTLS_CFLAGS'].split(), link_args: config_host['GNUTLS_LIBS'].split()) endif +pixman = declare_dependency(compile_args: config_host['PIXMAN_CFLAGS'].split(), + link_args: config_host['PIXMAN_LIBS'].split()) seccomp = not_found if 'CONFIG_SECCOMP' in config_host seccomp = declare_dependency(compile_args: config_host['SECCOMP_CFLAGS'].split(), @@ -97,6 +99,16 @@ if 'CONFIG_LIBISCSI' in config_host libiscsi = declare_dependency(compile_args: config_host['LIBISCSI_CFLAGS'].split(), link_args: config_host['LIBISCSI_LIBS'].split()) endif +gbm = not_found +if 'CONFIG_GBM' in config_host + gbm = declare_dependency(compile_args: config_host['GBM_CFLAGS'].split(), + link_args: config_host['GBM_LIBS'].split()) +endif +virgl = not_found +if 'CONFIG_VIRGL' in config_host + virgl = declare_dependency(compile_args: config_host['VIRGL_CFLAGS'].split(), + link_args: config_host['VIRGL_LIBS'].split()) +endif target_dirs = config_host['TARGET_DIRS'].split() have_user = false @@ -265,6 +277,9 @@ if have_tools if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') + if 'CONFIG_LINUX' in config_host + subdir('contrib/vhost-user-gpu') + endif subdir('contrib/vhost-user-input') subdir('contrib/vhost-user-scsi') endif diff --git a/rules.mak b/rules.mak index 7aefd37b5d..1aa6394079 100644 --- a/rules.mak +++ b/rules.mak @@ -402,13 +402,6 @@ TEXI2MAN = $(call quiet-command, \ %.8: $(call TEXI2MAN) -GEN_SUBST = $(call quiet-command, \ - sed -e "s!@libexecdir@!$(libexecdir)!g" < $< > $@, \ - "GEN","$@") - -%.json: %.json.in - $(call GEN_SUBST) - # Support for building multiple output files by atomically executing # a single rule which depends on several input files (so the rule # will be executed exactly once, not once per output file, and -- cgit v1.2.3-55-g7522 From 5ee24e78f5af0e4be7c6c7192541ca5fd7b0cf96 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 12 Jul 2019 23:16:54 +0400 Subject: contrib/ivshmem: convert to meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 9 --------- Makefile.objs | 2 -- configure | 3 --- contrib/ivshmem-client/Makefile.objs | 1 - contrib/ivshmem-client/meson.build | 4 ++++ contrib/ivshmem-server/Makefile.objs | 1 - contrib/ivshmem-server/meson.build | 4 ++++ meson.build | 5 +++++ 8 files changed, 13 insertions(+), 16 deletions(-) delete mode 100644 contrib/ivshmem-client/Makefile.objs create mode 100644 contrib/ivshmem-client/meson.build delete mode 100644 contrib/ivshmem-server/Makefile.objs create mode 100644 contrib/ivshmem-server/meson.build diff --git a/Makefile b/Makefile index ed6494b771..e16cbe6191 100644 --- a/Makefile +++ b/Makefile @@ -303,8 +303,6 @@ dummy := $(call unnest-vars,, \ chardev-obj-y \ qga-obj-y \ elf2dmp-obj-y \ - ivshmem-client-obj-y \ - ivshmem-server-obj-y \ qga-vss-dll-obj-y \ block-obj-y \ block-obj-m \ @@ -517,13 +515,6 @@ endif elf2dmp$(EXESUF): $(elf2dmp-obj-y) $(call LINK, $^) -ifdef CONFIG_IVSHMEM -ivshmem-client$(EXESUF): $(ivshmem-client-obj-y) $(COMMON_LDADDS) - $(call LINK, $^) -ivshmem-server$(EXESUF): $(ivshmem-server-obj-y) $(COMMON_LDADDS) - $(call LINK, $^) -endif - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ diff --git a/Makefile.objs b/Makefile.objs index 2f2d4b2066..336a684ff3 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -104,7 +104,5 @@ qga-vss-dll-obj-y = qga/ ###################################################################### # contrib elf2dmp-obj-y = contrib/elf2dmp/ -ivshmem-client-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-client/ -ivshmem-server-obj-$(CONFIG_IVSHMEM) = contrib/ivshmem-server/ ###################################################################### diff --git a/configure b/configure index 4d8936ee59..03f4dd69a9 100755 --- a/configure +++ b/configure @@ -6729,9 +6729,6 @@ if test "$want_tools" = "yes" ; then if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then tools="qemu-nbd\$(EXESUF) qemu-storage-daemon\$(EXESUF) $tools" fi - if [ "$ivshmem" = "yes" ]; then - tools="ivshmem-client\$(EXESUF) ivshmem-server\$(EXESUF) $tools" - fi if [ "$curl" = "yes" ]; then tools="elf2dmp\$(EXESUF) $tools" fi diff --git a/contrib/ivshmem-client/Makefile.objs b/contrib/ivshmem-client/Makefile.objs deleted file mode 100644 index bfab2d20dd..0000000000 --- a/contrib/ivshmem-client/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -ivshmem-client-obj-y = ivshmem-client.o main.o diff --git a/contrib/ivshmem-client/meson.build b/contrib/ivshmem-client/meson.build new file mode 100644 index 0000000000..1b171efb4f --- /dev/null +++ b/contrib/ivshmem-client/meson.build @@ -0,0 +1,4 @@ +executable('ivshmem-client', files('ivshmem-client.c', 'main.c'), + dependencies: glib, + build_by_default: targetos == 'linux', + install: false) diff --git a/contrib/ivshmem-server/Makefile.objs b/contrib/ivshmem-server/Makefile.objs deleted file mode 100644 index c060dd3698..0000000000 --- a/contrib/ivshmem-server/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -ivshmem-server-obj-y = ivshmem-server.o main.o diff --git a/contrib/ivshmem-server/meson.build b/contrib/ivshmem-server/meson.build new file mode 100644 index 0000000000..3a53942201 --- /dev/null +++ b/contrib/ivshmem-server/meson.build @@ -0,0 +1,4 @@ +executable('ivshmem-server', files('ivshmem-server.c', 'main.c'), + dependencies: [qemuutil, rt], + build_by_default: targetos == 'linux', + install: false) diff --git a/meson.build b/meson.build index 71ef66e1d6..c1078b6759 100644 --- a/meson.build +++ b/meson.build @@ -94,6 +94,7 @@ libcap_ng = not_found if 'CONFIG_LIBCAP_NG' in config_host libcap_ng = declare_dependency(link_args: config_host['LIBCAP_NG_LIBS'].split()) endif +rt = cc.find_library('rt', required: false) libiscsi = not_found if 'CONFIG_LIBISCSI' in config_host libiscsi = declare_dependency(compile_args: config_host['LIBISCSI_CFLAGS'].split(), @@ -283,6 +284,10 @@ if have_tools subdir('contrib/vhost-user-input') subdir('contrib/vhost-user-scsi') endif + if 'CONFIG_IVSHMEM' in config_host + subdir('contrib/ivshmem-client') + subdir('contrib/ivshmem-server') + endif endif subdir('tools') -- cgit v1.2.3-55-g7522 From 1d7bb6ab2cd93d56a86b9203bfc2cac5ee36de63 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 12 Jul 2019 23:47:06 +0400 Subject: contrib/elf2dmp: convert to meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 4 ---- Makefile.objs | 6 ------ configure | 3 --- contrib/elf2dmp/Makefile.objs | 4 ---- contrib/elf2dmp/meson.build | 5 +++++ meson.build | 6 ++++++ 6 files changed, 11 insertions(+), 17 deletions(-) delete mode 100644 contrib/elf2dmp/Makefile.objs create mode 100644 contrib/elf2dmp/meson.build diff --git a/Makefile b/Makefile index e16cbe6191..91602ad51e 100644 --- a/Makefile +++ b/Makefile @@ -302,7 +302,6 @@ dummy := $(call unnest-vars,, \ authz-obj-y \ chardev-obj-y \ qga-obj-y \ - elf2dmp-obj-y \ qga-vss-dll-obj-y \ block-obj-y \ block-obj-m \ @@ -512,9 +511,6 @@ ifneq ($(EXESUF),) qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) endif -elf2dmp$(EXESUF): $(elf2dmp-obj-y) - $(call LINK, $^) - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ diff --git a/Makefile.objs b/Makefile.objs index 336a684ff3..1486254a2c 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -100,9 +100,3 @@ version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o # extracted into a QAPI schema module, or perhaps a separate schema. qga-obj-y = qga/ qga-vss-dll-obj-y = qga/ - -###################################################################### -# contrib -elf2dmp-obj-y = contrib/elf2dmp/ - -###################################################################### diff --git a/configure b/configure index 03f4dd69a9..7b01ebe065 100755 --- a/configure +++ b/configure @@ -6729,9 +6729,6 @@ if test "$want_tools" = "yes" ; then if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then tools="qemu-nbd\$(EXESUF) qemu-storage-daemon\$(EXESUF) $tools" fi - if [ "$curl" = "yes" ]; then - tools="elf2dmp\$(EXESUF) $tools" - fi fi if test "$softmmu" = yes ; then if test "$linux" = yes; then diff --git a/contrib/elf2dmp/Makefile.objs b/contrib/elf2dmp/Makefile.objs deleted file mode 100644 index 1505716916..0000000000 --- a/contrib/elf2dmp/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o - -download.o-cflags := $(CURL_CFLAGS) -download.o-libs := $(CURL_LIBS) diff --git a/contrib/elf2dmp/meson.build b/contrib/elf2dmp/meson.build new file mode 100644 index 0000000000..b3de173316 --- /dev/null +++ b/contrib/elf2dmp/meson.build @@ -0,0 +1,5 @@ +if 'CONFIG_CURL' in config_host + executable('elf2dmp', files('main.c', 'addrspace.c', 'download.c', 'pdb.c', 'qemu_elf.c'), + dependencies: [glib, curl], + install: true) +endif diff --git a/meson.build b/meson.build index c1078b6759..59ac2f05d9 100644 --- a/meson.build +++ b/meson.build @@ -110,6 +110,11 @@ if 'CONFIG_VIRGL' in config_host virgl = declare_dependency(compile_args: config_host['VIRGL_CFLAGS'].split(), link_args: config_host['VIRGL_LIBS'].split()) endif +curl = not_found +if 'CONFIG_CURL' in config_host + curl = declare_dependency(compile_args: config_host['CURL_CFLAGS'].split(), + link_args: config_host['CURL_LIBS'].split()) +endif target_dirs = config_host['TARGET_DIRS'].split() have_user = false @@ -274,6 +279,7 @@ qemuutil = declare_dependency(link_with: libqemuutil, if have_tools subdir('contrib/rdmacm-mux') + subdir('contrib/elf2dmp') if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') -- cgit v1.2.3-55-g7522 From d92989aa2e2d0a5c3de80404b33d96e9afae84d3 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 20 Aug 2019 19:48:59 +0400 Subject: meson: add macos dependencies There is no probing in configure, so no need to pass them as variables to meson. Do a regular meson dependency() instead. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- meson.build | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/meson.build b/meson.build index 59ac2f05d9..d9758629cc 100644 --- a/meson.build +++ b/meson.build @@ -50,6 +50,10 @@ m = cc.find_library('m', required: false) util = cc.find_library('util', required: false) socket = [] version_res = [] +coref = [] +iokit = [] +cocoa = [] +hvf = [] if targetos == 'windows' socket = cc.find_library('ws2_32') @@ -57,6 +61,11 @@ if targetos == 'windows' version_res = win.compile_resources('version.rc', depend_files: files('pc-bios/qemu-nsis.ico'), include_directories: include_directories('.')) +elif targetos == 'darwin' + coref = dependency('appleframeworks', modules: 'CoreFoundation') + iokit = dependency('appleframeworks', modules: 'IOKit') + cocoa = dependency('appleframeworks', modules: 'Cocoa') + hvf = dependency('appleframeworks', modules: 'Hypervisor') endif glib = declare_dependency(compile_args: config_host['GLIB_CFLAGS'].split(), link_args: config_host['GLIB_LIBS'].split()) -- cgit v1.2.3-55-g7522 From cfad62f1fa019b7c921112ae7c1e4c6fbf087929 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sun, 9 Aug 2020 23:47:45 +0200 Subject: meson: add solaris and Haiku libraries There is no probing in configure, so no need to pass them as variables to meson. Signed-off-by: Paolo Bonzini --- meson.build | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/meson.build b/meson.build index d9758629cc..8d764a9431 100644 --- a/meson.build +++ b/meson.build @@ -66,6 +66,14 @@ elif targetos == 'darwin' iokit = dependency('appleframeworks', modules: 'IOKit') cocoa = dependency('appleframeworks', modules: 'Cocoa') hvf = dependency('appleframeworks', modules: 'Hypervisor') +elif targetos == 'sunos' + socket = [cc.find_library('socket'), + cc.find_library('nsl'), + cc.find_library('resolv')] +elif targetos == 'haiku' + socket = [cc.find_library('posix_error_mapper'), + cc.find_library('network'), + cc.find_library('bsd')] endif glib = declare_dependency(compile_args: config_host['GLIB_CFLAGS'].split(), link_args: config_host['GLIB_LIBS'].split()) -- cgit v1.2.3-55-g7522 From f15bff25f7c6843d698e122dc8d1b5927360f6c1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 18 Jul 2019 13:19:02 +0200 Subject: meson: convert qemu-ga Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 53 ++++++----------------------------------------- Makefile.objs | 1 - configure | 14 ++++--------- meson.build | 8 +++++++ qga/Makefile.objs | 9 -------- qga/installer/qemu-ga.wxs | 2 +- qga/meson.build | 46 ++++++++++++++++++++++++++++++++++++++++ tests/Makefile.include | 4 ++-- tests/test-qga.c | 8 +++---- 9 files changed, 71 insertions(+), 74 deletions(-) create mode 100644 qga/meson.build diff --git a/Makefile b/Makefile index 91602ad51e..83e2c86725 100644 --- a/Makefile +++ b/Makefile @@ -301,7 +301,6 @@ endif dummy := $(call unnest-vars,, \ authz-obj-y \ chardev-obj-y \ - qga-obj-y \ qga-vss-dll-obj-y \ block-obj-y \ block-obj-m \ @@ -449,52 +448,15 @@ endif qemu-img-cmds.h: $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/scripts/hxtool $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$@") -qemu-ga$(EXESUF): LIBS = $(LIBS_QGA) -qemu-ga$(EXESUF): QEMU_CFLAGS += -I qga/qapi-generated - qemu-keymap$(EXESUF): LIBS += $(XKBCOMMON_LIBS) qemu-keymap$(EXESUF): QEMU_CFLAGS += $(XKBCOMMON_CFLAGS) -qapi-py = $(SRC_PATH)/scripts/qapi/__init__.py \ -$(SRC_PATH)/scripts/qapi/commands.py \ -$(SRC_PATH)/scripts/qapi/common.py \ -$(SRC_PATH)/scripts/qapi/doc.py \ -$(SRC_PATH)/scripts/qapi/error.py \ -$(SRC_PATH)/scripts/qapi/events.py \ -$(SRC_PATH)/scripts/qapi/expr.py \ -$(SRC_PATH)/scripts/qapi/gen.py \ -$(SRC_PATH)/scripts/qapi/introspect.py \ -$(SRC_PATH)/scripts/qapi/parser.py \ -$(SRC_PATH)/scripts/qapi/schema.py \ -$(SRC_PATH)/scripts/qapi/source.py \ -$(SRC_PATH)/scripts/qapi/types.py \ -$(SRC_PATH)/scripts/qapi/visit.py \ -$(SRC_PATH)/scripts/qapi-gen.py - -qga/qapi-generated/qga-qapi-types.c qga/qapi-generated/qga-qapi-types.h \ -qga/qapi-generated/qga-qapi-visit.c qga/qapi-generated/qga-qapi-visit.h \ -qga/qapi-generated/qga-qapi-commands.h qga/qapi-generated/qga-qapi-commands.c \ -qga/qapi-generated/qga-qapi-init-commands.h qga/qapi-generated/qga-qapi-init-commands.c \ -qga/qapi-generated/qga-qapi-doc.texi: \ -qga/qapi-generated/qapi-gen-timestamp ; -qga/qapi-generated/qapi-gen-timestamp: $(SRC_PATH)/qga/qapi-schema.json $(qapi-py) - $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ - -o qga/qapi-generated -p "qga-" $<, \ - "GEN","$(@:%-timestamp=%)") - @>$@ - -QGALIB_GEN=$(addprefix qga/qapi-generated/, qga-qapi-types.h qga-qapi-visit.h qga-qapi-commands.h qga-qapi-init-commands.h) -$(qga-obj-y): $(QGALIB_GEN) - -qemu-ga$(EXESUF): $(qga-obj-y) $(COMMON_LDADDS) - $(call LINK, $^) - ifdef QEMU_GA_MSI_ENABLED QEMU_GA_MSI=qemu-ga-$(ARCH).msi msi: $(QEMU_GA_MSI) -$(QEMU_GA_MSI): qemu-ga.exe $(QGA_VSS_PROVIDER) +$(QEMU_GA_MSI): qga/qemu-ga.exe $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI): config-host.mak @@ -507,8 +469,8 @@ msi: endif ifneq ($(EXESUF),) -.PHONY: qemu-ga -qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) +.PHONY: qga/qemu-ga +qga/qemu-ga: qga/qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) endif module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak @@ -533,9 +495,6 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f qemu-img-cmds.h rm -f ui/shader/*-vert.h ui/shader/*-frag.h rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) - rm -f qapi-gen-timestamp - rm -f storage-daemon/qapi/qapi-gen-timestamp - rm -rf qga/qapi-generated rm -f config-all-devices.mak rm -f $(SUBDIR_DEVICES_MAK) @@ -657,7 +616,7 @@ endif ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/qemu-trace-stap.1 "$(DESTDIR)$(mandir)/man1" endif -ifneq (,$(findstring qemu-ga,$(TOOLS))) +ifeq ($(CONFIG_GUEST_AGENT),y) $(INSTALL_DATA) $(MANUAL_BUILDDIR)/interop/qemu-ga.8 "$(DESTDIR)$(mandir)/man8" $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-ga-ref.html "$(DESTDIR)$(qemu_docdir)/interop" @@ -678,7 +637,7 @@ install-datadir: install-localstatedir: ifdef CONFIG_POSIX -ifneq (,$(findstring qemu-ga,$(TOOLS))) +ifeq ($(CONFIG_GUEST_AGENT),y) $(INSTALL_DIR) "$(DESTDIR)$(qemu_localstatedir)"/run endif endif @@ -870,7 +829,7 @@ $(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h docs/interop/qemu-qmp-qapi.texi: qapi/qapi-doc.texi @cp -p $< $@ -docs/interop/qemu-ga-qapi.texi: qga/qapi-generated/qga-qapi-doc.texi +docs/interop/qemu-ga-qapi.texi: qga/qga-qapi-doc.texi @cp -p $< $@ html: docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html sphinxdocs diff --git a/Makefile.objs b/Makefile.objs index 1486254a2c..259f9936ac 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -98,5 +98,4 @@ version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o # FIXME: a few definitions from qapi/qapi-types.o and # qapi/qapi-visit.o are needed by libqemuutil.a. These should be # extracted into a QAPI schema module, or perhaps a separate schema. -qga-obj-y = qga/ qga-vss-dll-obj-y = qga/ diff --git a/configure b/configure index 7b01ebe065..c7ef28782e 100755 --- a/configure +++ b/configure @@ -872,8 +872,6 @@ FreeBSD) audio_possible_drivers="oss sdl pa" # needed for kinfo_getvmmap(3) in libutil.h LIBS="-lutil $LIBS" - # needed for kinfo_getproc - libs_qga="-lutil $libs_qga" netmap="" # enable netmap autodetect HOST_VARIANT_DIR="freebsd" ;; @@ -935,7 +933,6 @@ SunOS) QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" solarisnetlibs="-lsocket -lnsl -lresolv" LIBS="$solarisnetlibs $LIBS" - libs_qga="$solarisnetlibs $libs_qga" ;; Haiku) haiku="yes" @@ -4021,7 +4018,6 @@ for i in $glib_modules; do glib_libs=$($pkg_config --libs $i) QEMU_CFLAGS="$glib_cflags $QEMU_CFLAGS" LIBS="$glib_libs $LIBS" - libs_qga="$glib_libs $libs_qga" else error_exit "glib-$glib_req_ver $i is required to compile QEMU" fi @@ -4232,7 +4228,6 @@ else done if test "$found" = "no"; then LIBS="$pthread_lib $LIBS" - libs_qga="$pthread_lib $libs_qga" fi PTHREAD_LIB="$pthread_lib" break @@ -5241,7 +5236,6 @@ if compile_prog "" "" ; then : elif compile_prog "" "-lm" ; then LIBS="-lm $LIBS" - libs_qga="-lm $libs_qga" else error_exit "libm check failed" fi @@ -5266,7 +5260,6 @@ if compile_prog "" "" ; then # we need pthread for static linking. use previous pthread test result elif compile_prog "" "$pthread_lib -lrt" ; then LIBS="$LIBS -lrt" - libs_qga="$libs_qga -lrt" fi # Check whether we need to link libutil for openpty() @@ -5645,7 +5638,6 @@ EOF fi LIBS="$lttng_ust_libs $urcu_bp_libs $LIBS" - libs_qga="$lttng_ust_libs $urcu_bp_libs $libs_qga" else error_exit "Trace backend 'ust' missing lttng-ust header files" fi @@ -6771,7 +6763,6 @@ if [ "$guest_agent" != "no" ]; then if [ "$softmmu" = no -a "$want_tools" = no ] ; then guest_agent=no elif [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" -o "$mingw32" = "yes" ] ; then - tools="qemu-ga\$(EXESUF) $tools" guest_agent=yes elif [ "$guest_agent" != yes ]; then guest_agent=no @@ -7017,6 +7008,9 @@ fi if test "$want_tools" = "yes" ; then echo "CONFIG_TOOLS=y" >> $config_host_mak fi +if test "$guest_agent" = "yes" ; then + echo "CONFIG_GUEST_AGENT=y" >> $config_host_mak +fi if test "$slirp" != "no"; then echo "CONFIG_SLIRP=y" >> $config_host_mak echo "CONFIG_SMBD_COMMAND=\"$smbd\"" >> $config_host_mak @@ -7874,7 +7868,7 @@ echo "PTHREAD_LIB=$PTHREAD_LIB" >> $config_host_mak echo "EXESUF=$EXESUF" >> $config_host_mak echo "DSOSUF=$DSOSUF" >> $config_host_mak echo "LDFLAGS_SHARED=$LDFLAGS_SHARED" >> $config_host_mak -echo "LIBS_QGA+=$libs_qga" >> $config_host_mak +echo "LIBS_QGA=$libs_qga" >> $config_host_mak echo "TASN1_LIBS=$tasn1_libs" >> $config_host_mak echo "TASN1_CFLAGS=$tasn1_cflags" >> $config_host_mak echo "POD2MAN=$POD2MAN" >> $config_host_mak diff --git a/meson.build b/meson.build index 8d764a9431..5cd8ee0298 100644 --- a/meson.build +++ b/meson.build @@ -132,6 +132,10 @@ if 'CONFIG_CURL' in config_host curl = declare_dependency(compile_args: config_host['CURL_CFLAGS'].split(), link_args: config_host['CURL_LIBS'].split()) endif +libudev = not_found +if 'CONFIG_LIBUDEV' in config_host + libudev = declare_dependency(link_args: config_host['LIBUDEV_LIBS'].split()) +endif target_dirs = config_host['TARGET_DIRS'].split() have_user = false @@ -294,6 +298,10 @@ qemuutil = declare_dependency(link_with: libqemuutil, # Other build targets +if 'CONFIG_GUEST_AGENT' in config_host + subdir('qga') +endif + if have_tools subdir('contrib/rdmacm-mux') subdir('contrib/elf2dmp') diff --git a/qga/Makefile.objs b/qga/Makefile.objs index 9c558ae51c..9ecf2496da 100644 --- a/qga/Makefile.objs +++ b/qga/Makefile.objs @@ -1,10 +1 @@ -commands-posix.o-libs := $(LIBUDEV_LIBS) -qga-obj-y = commands.o guest-agent-command-state.o main.o -qga-obj-$(CONFIG_POSIX) += commands-posix.o channel-posix.o -qga-obj-$(CONFIG_WIN32) += commands-win32.o channel-win32.o service-win32.o -qga-obj-$(CONFIG_WIN32) += vss-win32.o -qga-obj-y += qapi-generated/qga-qapi-types.o qapi-generated/qga-qapi-visit.o -qga-obj-y += qapi-generated/qga-qapi-commands.o -qga-obj-y += qapi-generated/qga-qapi-init-commands.o - qga-vss-dll-obj-$(CONFIG_QGA_VSS) += vss-win32/ diff --git a/qga/installer/qemu-ga.wxs b/qga/installer/qemu-ga.wxs index f6781752e6..9cb4c3d733 100644 --- a/qga/installer/qemu-ga.wxs +++ b/qga/installer/qemu-ga.wxs @@ -66,7 +66,7 @@ - + test_dir, "sock", NULL); cwd = g_get_current_dir(); - cmd = g_strdup_printf("%s%cqemu-ga -m unix-listen -t %s -p %s %s %s", - cwd, G_DIR_SEPARATOR, + cmd = g_strdup_printf("%s%cqga%cqemu-ga -m unix-listen -t %s -p %s %s %s", + cwd, G_DIR_SEPARATOR, G_DIR_SEPARATOR, fixture->test_dir, path, getenv("QTEST_LOG") ? "-v" : "", extra_arg ?: ""); @@ -699,8 +699,8 @@ static void test_qga_config(gconstpointer data) GKeyFile *kf; cwd = g_get_current_dir(); - cmd = g_strdup_printf("%s%cqemu-ga -D", - cwd, G_DIR_SEPARATOR); + cmd = g_strdup_printf("%s%cqga%cqemu-ga -D", + cwd, G_DIR_SEPARATOR, G_DIR_SEPARATOR); g_free(cwd); g_shell_parse_argv(cmd, NULL, &argv, &error); g_free(cmd); -- cgit v1.2.3-55-g7522 From 7272fc72682c2573c67136e2c175d33d00d8905b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 11:39:13 +0400 Subject: meson: convert vss-win32 Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 1 - Makefile.objs | 8 -------- qga/Makefile.objs | 1 - qga/meson.build | 6 ++++++ qga/vss-win32/Makefile.objs | 23 ----------------------- qga/vss-win32/meson.build | 33 +++++++++++++++++++++++++++++++++ 6 files changed, 39 insertions(+), 33 deletions(-) delete mode 100644 qga/Makefile.objs delete mode 100644 qga/vss-win32/Makefile.objs create mode 100644 qga/vss-win32/meson.build diff --git a/Makefile b/Makefile index 83e2c86725..0fa9d63bb4 100644 --- a/Makefile +++ b/Makefile @@ -301,7 +301,6 @@ endif dummy := $(call unnest-vars,, \ authz-obj-y \ chardev-obj-y \ - qga-vss-dll-obj-y \ block-obj-y \ block-obj-m \ storage-daemon-obj-y \ diff --git a/Makefile.objs b/Makefile.objs index 259f9936ac..baf15656e8 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -91,11 +91,3 @@ common-obj-y += disas/ ###################################################################### # Resource file for Windows executables version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o - -###################################################################### -# guest agent - -# FIXME: a few definitions from qapi/qapi-types.o and -# qapi/qapi-visit.o are needed by libqemuutil.a. These should be -# extracted into a QAPI schema module, or perhaps a separate schema. -qga-vss-dll-obj-y = qga/ diff --git a/qga/Makefile.objs b/qga/Makefile.objs deleted file mode 100644 index 9ecf2496da..0000000000 --- a/qga/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -qga-vss-dll-obj-$(CONFIG_QGA_VSS) += vss-win32/ diff --git a/qga/meson.build b/qga/meson.build index 3513a90f5d..9ddb260cff 100644 --- a/qga/meson.build +++ b/qga/meson.build @@ -44,3 +44,9 @@ qga = executable('qemu-ga', qga_ss.sources(), link_args: config_host['LIBS_QGA'].split(), dependencies: [qemuutil, libudev], install: true) + +if targetos == 'windows' + if 'CONFIG_QGA_VSS' in config_host + subdir('vss-win32') + endif +endif diff --git a/qga/vss-win32/Makefile.objs b/qga/vss-win32/Makefile.objs deleted file mode 100644 index c82676aeb8..0000000000 --- a/qga/vss-win32/Makefile.objs +++ /dev/null @@ -1,23 +0,0 @@ -# rules to build qga-vss.dll - -qga-vss-dll-obj-y += requester.o provider.o install.o - -obj-qga-vss-dll-obj-y = $(addprefix $(obj)/, $(qga-vss-dll-obj-y)) -$(obj-qga-vss-dll-obj-y): QEMU_CXXFLAGS := $(filter-out -fstack-protector-all -fstack-protector-strong, $(QEMU_CXXFLAGS)) -Wno-unknown-pragmas -Wno-delete-non-virtual-dtor - -QGA_VSS_LDFLAGS = -shared -Wl,--add-stdcall-alias,--enable-stdcall-fixup -lglib-2.0 -lole32 -loleaut32 -lshlwapi -luuid -lintl -lws2_32 -static -$(obj)/qga-vss.dll: $(obj-qga-vss-dll-obj-y) $(SRC_PATH)/$(obj)/qga-vss.def - $(call quiet-command,$(CXX) -o $@ $(qga-vss-dll-obj-y) $(SRC_PATH)/qga/vss-win32/qga-vss.def $(CXXFLAGS) $(QGA_VSS_LDFLAGS),"LINK","$(TARGET_DIR)$@") - - -# rules to build qga-provider.tlb -# Currently, only native build is supported because building .tlb -# (TypeLibrary) from .idl requires WindowsSDK and MIDL (and cl.exe in VC++). -MIDL=$(WIN_SDK)/Bin/midl - -$(obj)/qga-vss.tlb: $(SRC_PATH)/$(obj)/qga-vss.idl -ifeq ($(WIN_SDK),"") - $(call quiet-command,cp $(dir $<)qga-vss.tlb $@,"COPY","$(TARGET_DIR)$@") -else - $(call quiet-command,$(MIDL) -tlb $@ -I $(WIN_SDK)/Include $<,"MIDL","$(TARGET_DIR)$@") -endif diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build new file mode 100644 index 0000000000..42c8d31a3d --- /dev/null +++ b/qga/vss-win32/meson.build @@ -0,0 +1,33 @@ +if add_languages('cpp', required: false) + glib_static = dependency('glib-2.0', static: true) + link_args = cc.get_supported_link_arguments(['-fstack-protector-all', '-fstack-protector-strong', + '-Wl,--add-stdcall-alias', '-Wl,--enable-stdcall-fixup']) + shared_module('qga-vss', ['requester.cpp', 'provider.cpp', 'install.cpp'], + name_prefix: '', + cpp_args: ['-Wno-unknown-pragmas', '-Wno-delete-non-virtual-dtor', '-Wno-non-virtual-dtor'], + link_args: link_args, + vs_module_defs: 'qga-vss.def', + dependencies: [glib_static, socket, + cc.find_library('ole32'), + cc.find_library('oleaut32'), + cc.find_library('shlwapi'), + cc.find_library('uuid'), + cc.find_library('intl')]) +endif + +# rules to build qga-vss.tlb +# Currently, only native build is supported because building .tlb +# (TypeLibrary) from .idl requires WindowsSDK and MIDL (and cl.exe in VC++). +midl = find_program('midl', required: false) +if midl.found() + gen_tlb = custom_target('gen-tlb', + input: 'qga-vss.idl', + output: 'qga-vss.tlb', + command: [midl, '-tlb', '-I' + config_host['WIN_SDK'], + '@INPUT@', '@OUTPUT@']) +else + gen_tlb = custom_target('gen-tlb', + input: 'qga-vss.tlb', + output: 'qga-vss.tlb', + command: ['cp', '@INPUT@', '@OUTPUT@']) +endif -- cgit v1.2.3-55-g7522 From 328ec32d7d5b3c2aa2ecfe974e01bcbe3c5a46ac Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 13:06:20 +0400 Subject: meson: add msi generation Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 18 ------------------ qga/meson.build | 25 +++++++++++++++++++++++++ qga/vss-win32/meson.build | 3 ++- 3 files changed, 27 insertions(+), 19 deletions(-) diff --git a/Makefile b/Makefile index 0fa9d63bb4..e93ebf6299 100644 --- a/Makefile +++ b/Makefile @@ -450,23 +450,6 @@ qemu-img-cmds.h: $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/scripts/hxtool qemu-keymap$(EXESUF): LIBS += $(XKBCOMMON_LIBS) qemu-keymap$(EXESUF): QEMU_CFLAGS += $(XKBCOMMON_CFLAGS) -ifdef QEMU_GA_MSI_ENABLED -QEMU_GA_MSI=qemu-ga-$(ARCH).msi - -msi: $(QEMU_GA_MSI) - -$(QEMU_GA_MSI): qga/qemu-ga.exe $(QGA_VSS_PROVIDER) - -$(QEMU_GA_MSI): config-host.mak - -$(QEMU_GA_MSI): $(SRC_PATH)/qga/installer/qemu-ga.wxs - $(call quiet-command,QEMU_GA_VERSION="$(QEMU_GA_VERSION)" QEMU_GA_MANUFACTURER="$(QEMU_GA_MANUFACTURER)" QEMU_GA_DISTRO="$(QEMU_GA_DISTRO)" BUILD_DIR="$(BUILD_DIR)" \ - wixl -o $@ $(QEMU_GA_MSI_ARCH) $(QEMU_GA_MSI_WITH_VSS) $(QEMU_GA_MSI_MINGW_DLL_PATH) $<,"WIXL","$@") -else -msi: - @echo "MSI build not configured or dependency resolution failed (reconfigure with --enable-guest-agent-msi option)" -endif - ifneq ($(EXESUF),) .PHONY: qga/qemu-ga qga/qemu-ga: qga/qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) @@ -482,7 +465,6 @@ clean: recurse-clean ninja-clean clean-ctlist # avoid old build problems by removing potentially incorrect old files rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h rm -f qemu-options.def - rm -f *.msi find . \( -name '*.so' -o -name '*.dll' -o -name '*.mo' -o -name '*.[oda]' \) -type f \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-aarch64.a \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-arm.a \ diff --git a/qga/meson.build b/qga/meson.build index 9ddb260cff..33f6db2865 100644 --- a/qga/meson.build +++ b/qga/meson.build @@ -48,5 +48,30 @@ qga = executable('qemu-ga', qga_ss.sources(), if targetos == 'windows' if 'CONFIG_QGA_VSS' in config_host subdir('vss-win32') + else + gen_tlb = [] + endif + + wixl = find_program('wixl', required: false) + if wixl.found() + deps = [gen_tlb, qga] + if 'CONFIG_QGA_VSS' in config_host and 'QEMU_GA_MSI_WITH_VSS' in config_host + deps += qga_vss + endif + qga_msi = custom_target('QGA MSI', + input: files('installer/qemu-ga.wxs'), + output: 'qemu-ga-@0@.msi'.format(config_host['ARCH']), + depends: deps, + command: [ + 'QEMU_GA_VERSION=' + config_host['QEMU_GA_VERSION'], + 'QEMU_GA_MANUFACTURER=' + config_host['QEMU_GA_MANUFACTURER'], + 'QEMU_GA_DISTRO=' + config_host['QEMU_GA_DISTRO'], + 'BUILD_DIR=' + meson.build_root(), + wixl, '-o', '@OUTPUT0@', '@INPUT0@', + config_host['QEMU_GA_MSI_ARCH'].split(), + config_host['QEMU_GA_MSI_WITH_VSS'].split(), + config_host['QEMU_GA_MSI_MINGW_DLL_PATH'].split(), + ]) + alias_target('msi', qga_msi) endif endif diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build index 42c8d31a3d..1f39e05335 100644 --- a/qga/vss-win32/meson.build +++ b/qga/vss-win32/meson.build @@ -2,7 +2,8 @@ if add_languages('cpp', required: false) glib_static = dependency('glib-2.0', static: true) link_args = cc.get_supported_link_arguments(['-fstack-protector-all', '-fstack-protector-strong', '-Wl,--add-stdcall-alias', '-Wl,--enable-stdcall-fixup']) - shared_module('qga-vss', ['requester.cpp', 'provider.cpp', 'install.cpp'], + + qga_vss = shared_module('qga-vss', ['requester.cpp', 'provider.cpp', 'install.cpp'], name_prefix: '', cpp_args: ['-Wno-unknown-pragmas', '-Wno-delete-non-virtual-dtor', '-Wno-non-virtual-dtor'], link_args: link_args, -- cgit v1.2.3-55-g7522 From 588a19fa9d41656b2e27a20153bc75f12ddf1194 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 28 Jan 2020 15:06:16 +0100 Subject: meson: convert dummy Windows qga/qemu-ga target Signed-off-by: Paolo Bonzini --- Makefile | 5 ----- qga/meson.build | 4 ++++ qga/vss-win32/meson.build | 2 ++ 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index e93ebf6299..8d3c8d8fbd 100644 --- a/Makefile +++ b/Makefile @@ -450,11 +450,6 @@ qemu-img-cmds.h: $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/scripts/hxtool qemu-keymap$(EXESUF): LIBS += $(XKBCOMMON_LIBS) qemu-keymap$(EXESUF): QEMU_CFLAGS += $(XKBCOMMON_CFLAGS) -ifneq ($(EXESUF),) -.PHONY: qga/qemu-ga -qga/qemu-ga: qga/qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI) -endif - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ diff --git a/qga/meson.build b/qga/meson.build index 33f6db2865..2b91261427 100644 --- a/qga/meson.build +++ b/qga/meson.build @@ -44,6 +44,7 @@ qga = executable('qemu-ga', qga_ss.sources(), link_args: config_host['LIBS_QGA'].split(), dependencies: [qemuutil, libudev], install: true) +all_qga = [qga] if targetos == 'windows' if 'CONFIG_QGA_VSS' in config_host @@ -72,6 +73,9 @@ if targetos == 'windows' config_host['QEMU_GA_MSI_WITH_VSS'].split(), config_host['QEMU_GA_MSI_MINGW_DLL_PATH'].split(), ]) + all_qga += [qga_msi] alias_target('msi', qga_msi) endif endif + +alias_target('qemu-ga', all_qga) diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build index 1f39e05335..780c461432 100644 --- a/qga/vss-win32/meson.build +++ b/qga/vss-win32/meson.build @@ -14,6 +14,8 @@ if add_languages('cpp', required: false) cc.find_library('shlwapi'), cc.find_library('uuid'), cc.find_library('intl')]) + + all_qga += qga_vss endif # rules to build qga-vss.tlb -- cgit v1.2.3-55-g7522 From 8f51e01c0141659435318c41af6e37402f3eb2de Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 14:39:25 +0400 Subject: meson: add qemu-bridge-helper Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- Makefile | 4 ---- meson.build | 9 ++++++++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 8d3c8d8fbd..3addf50636 100644 --- a/Makefile +++ b/Makefile @@ -197,8 +197,6 @@ LIBS+=-lz $(LIBS_TOOLS) HELPERS-y = $(HELPERS) -HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) += qemu-bridge-helper$(EXESUF) - # Sphinx does not allow building manuals into the same directory as # the source files, so if we're doing an in-tree QEMU build we must # build the manuals into a subdirectory (and then install them from @@ -431,8 +429,6 @@ qemu-nbd$(EXESUF): qemu-nbd.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io qemu-io$(EXESUF): qemu-io.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) -qemu-bridge-helper$(EXESUF): qemu-bridge-helper.o $(COMMON_LDADDS) - qemu-keymap$(EXESUF): qemu-keymap.o ui/input-keymap.o $(COMMON_LDADDS) qemu-edid$(EXESUF): qemu-edid.o hw/display/edid-generate.o $(COMMON_LDADDS) diff --git a/meson.build b/meson.build index 5cd8ee0298..3568b4816e 100644 --- a/meson.build +++ b/meson.build @@ -297,7 +297,6 @@ qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) # Other build targets - if 'CONFIG_GUEST_AGENT' in config_host subdir('qga') endif @@ -315,6 +314,14 @@ if have_tools subdir('contrib/vhost-user-input') subdir('contrib/vhost-user-scsi') endif + + if targetos == 'linux' + executable('qemu-bridge-helper', files('qemu-bridge-helper.c'), + dependencies: [qemuutil, libcap_ng], + install: true, + install_dir: get_option('libexecdir')) + endif + if 'CONFIG_IVSHMEM' in config_host subdir('contrib/ivshmem-client') subdir('contrib/ivshmem-server') -- cgit v1.2.3-55-g7522 From ade60d4fe1b5e840080a113885af2bcca6f69bc3 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 14:48:31 +0400 Subject: meson: add qemu-keymap Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 5 ----- configure | 4 +--- meson.build | 10 ++++++++++ 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 3addf50636..b0a261bdc7 100644 --- a/Makefile +++ b/Makefile @@ -429,8 +429,6 @@ qemu-nbd$(EXESUF): qemu-nbd.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io qemu-io$(EXESUF): qemu-io.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) -qemu-keymap$(EXESUF): qemu-keymap.o ui/input-keymap.o $(COMMON_LDADDS) - qemu-edid$(EXESUF): qemu-edid.o hw/display/edid-generate.o $(COMMON_LDADDS) fsdev/virtfs-proxy-helper$(EXESUF): fsdev/virtfs-proxy-helper.o fsdev/9p-marshal.o fsdev/9p-iov-marshal.o $(COMMON_LDADDS) @@ -443,9 +441,6 @@ endif qemu-img-cmds.h: $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/scripts/hxtool $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$@") -qemu-keymap$(EXESUF): LIBS += $(XKBCOMMON_LIBS) -qemu-keymap$(EXESUF): QEMU_CFLAGS += $(XKBCOMMON_CFLAGS) - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ diff --git a/configure b/configure index c7ef28782e..88f925e707 100755 --- a/configure +++ b/configure @@ -6752,9 +6752,6 @@ if test "$softmmu" = yes ; then fi mpath=no fi - if test "$xkbcommon" = "yes"; then - tools="qemu-keymap\$(EXESUF) $tools" - fi fi # Probe for guest agent support/options @@ -7071,6 +7068,7 @@ if test "$vnc_png" = "yes" ; then echo "CONFIG_VNC_PNG=y" >> $config_host_mak fi if test "$xkbcommon" = "yes" ; then + echo "CONFIG_XKBCOMMON=y" >> $config_host_mak echo "XKBCOMMON_CFLAGS=$xkbcommon_cflags" >> $config_host_mak echo "XKBCOMMON_LIBS=$xkbcommon_libs" >> $config_host_mak fi diff --git a/meson.build b/meson.build index 3568b4816e..9ec7dd9ddc 100644 --- a/meson.build +++ b/meson.build @@ -111,6 +111,11 @@ libcap_ng = not_found if 'CONFIG_LIBCAP_NG' in config_host libcap_ng = declare_dependency(link_args: config_host['LIBCAP_NG_LIBS'].split()) endif +xkbcommon = not_found +if 'CONFIG_XKBCOMMON' in config_host + xkbcommon = declare_dependency(compile_args: config_host['XKBCOMMON_CFLAGS'].split(), + link_args: config_host['XKBCOMMON_LIBS'].split()) +endif rt = cc.find_library('rt', required: false) libiscsi = not_found if 'CONFIG_LIBISCSI' in config_host @@ -305,6 +310,11 @@ if have_tools subdir('contrib/rdmacm-mux') subdir('contrib/elf2dmp') + if 'CONFIG_XKBCOMMON' in config_host + executable('qemu-keymap', files('qemu-keymap.c', 'ui/input-keymap.c'), + dependencies: [qemuutil, xkbcommon], install: true) + endif + if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') -- cgit v1.2.3-55-g7522 From 157e7b13b93e7fc5440093486932a69ef0ecfdee Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 14:50:58 +0400 Subject: meson: add qemu-edid Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- Makefile | 2 -- configure | 2 +- meson.build | 4 ++++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index b0a261bdc7..da1e556efe 100644 --- a/Makefile +++ b/Makefile @@ -429,8 +429,6 @@ qemu-nbd$(EXESUF): qemu-nbd.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io qemu-io$(EXESUF): qemu-io.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) -qemu-edid$(EXESUF): qemu-edid.o hw/display/edid-generate.o $(COMMON_LDADDS) - fsdev/virtfs-proxy-helper$(EXESUF): fsdev/virtfs-proxy-helper.o fsdev/9p-marshal.o fsdev/9p-iov-marshal.o $(COMMON_LDADDS) scsi/qemu-pr-helper$(EXESUF): scsi/qemu-pr-helper.o scsi/utils.o $(authz-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) diff --git a/configure b/configure index 88f925e707..013ebed9ff 100755 --- a/configure +++ b/configure @@ -6717,7 +6717,7 @@ fi tools="" if test "$want_tools" = "yes" ; then - tools="qemu-img\$(EXESUF) qemu-io\$(EXESUF) qemu-edid\$(EXESUF) $tools" + tools="qemu-img\$(EXESUF) qemu-io\$(EXESUF) $tools" if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then tools="qemu-nbd\$(EXESUF) qemu-storage-daemon\$(EXESUF) $tools" fi diff --git a/meson.build b/meson.build index 9ec7dd9ddc..f49f5e08d6 100644 --- a/meson.build +++ b/meson.build @@ -315,6 +315,10 @@ if have_tools dependencies: [qemuutil, xkbcommon], install: true) endif + executable('qemu-edid', files('qemu-edid.c', 'hw/display/edid-generate.c'), + dependencies: qemuutil, + install: true) + if 'CONFIG_VHOST_USER' in config_host subdir('contrib/libvhost-user') subdir('contrib/vhost-user-blk') -- cgit v1.2.3-55-g7522 From ec0d5893da20a5f35dcbd901d98be24346bf9cc2 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 15:04:49 +0400 Subject: meson: add virtfs-proxy-helper Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 2 -- configure | 7 +++++-- fsdev/meson.build | 8 ++++++++ meson.build | 6 ++++++ 4 files changed, 19 insertions(+), 4 deletions(-) create mode 100644 fsdev/meson.build diff --git a/Makefile b/Makefile index da1e556efe..39633ec7db 100644 --- a/Makefile +++ b/Makefile @@ -429,8 +429,6 @@ qemu-nbd$(EXESUF): qemu-nbd.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io qemu-io$(EXESUF): qemu-io.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) -fsdev/virtfs-proxy-helper$(EXESUF): fsdev/virtfs-proxy-helper.o fsdev/9p-marshal.o fsdev/9p-iov-marshal.o $(COMMON_LDADDS) - scsi/qemu-pr-helper$(EXESUF): scsi/qemu-pr-helper.o scsi/utils.o $(authz-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) ifdef CONFIG_MPATH scsi/qemu-pr-helper$(EXESUF): LIBS += -ludev -lmultipath -lmpathpersist diff --git a/configure b/configure index 013ebed9ff..5e5923dfd6 100755 --- a/configure +++ b/configure @@ -4388,6 +4388,7 @@ fi ########################################## # attr probe +libattr_libs= if test "$attr" != "no" ; then cat > $TMPC < @@ -4404,7 +4405,8 @@ EOF # Older distros have , and need -lattr: elif compile_prog "-DCONFIG_LIBATTR" "-lattr" ; then attr=yes - LIBS="-lattr $LIBS" + libattr_libs="-lattr" + LIBS="$libattr_libs $LIBS" libattr=yes else if test "$attr" = "yes" ; then @@ -6716,6 +6718,7 @@ if [ "$eventfd" = "yes" ]; then fi tools="" +helpers="" if test "$want_tools" = "yes" ; then tools="qemu-img\$(EXESUF) qemu-io\$(EXESUF) $tools" if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then @@ -6726,7 +6729,6 @@ if test "$softmmu" = yes ; then if test "$linux" = yes; then if test "$virtfs" != no && test "$cap_ng" = yes && test "$attr" = yes ; then virtfs=yes - helpers="$helpers fsdev/virtfs-proxy-helper\$(EXESUF)" else if test "$virtfs" = yes; then error_exit "VirtFS requires libcap-ng devel and libattr devel" @@ -7308,6 +7310,7 @@ if test "$linux_io_uring" = "yes" ; then fi if test "$attr" = "yes" ; then echo "CONFIG_ATTR=y" >> $config_host_mak + echo "LIBATTR_LIBS=$libattr_libs" >> $config_host_mak fi if test "$libattr" = "yes" ; then echo "CONFIG_LIBATTR=y" >> $config_host_mak diff --git a/fsdev/meson.build b/fsdev/meson.build new file mode 100644 index 0000000000..30e2319960 --- /dev/null +++ b/fsdev/meson.build @@ -0,0 +1,8 @@ +have_virtfs_proxy_helper = have_tools and libattr.found() and libcap_ng.found() and 'CONFIG_VIRTFS' in config_host +if have_virtfs_proxy_helper + executable('virtfs-proxy-helper', + files('virtfs-proxy-helper.c', '9p-marshal.c', '9p-iov-marshal.c'), + dependencies: [qemuutil, libattr, libcap_ng], + install: true, + install_dir: get_option('libexecdir')) +endif diff --git a/meson.build b/meson.build index f49f5e08d6..3e9e0a9b33 100644 --- a/meson.build +++ b/meson.build @@ -102,6 +102,10 @@ if 'CONFIG_GNUTLS' in config_host endif pixman = declare_dependency(compile_args: config_host['PIXMAN_CFLAGS'].split(), link_args: config_host['PIXMAN_LIBS'].split()) +libattr = not_found +if 'CONFIG_ATTR' in config_host + libattr = declare_dependency(link_args: config_host['LIBATTR_LIBS'].split()) +endif seccomp = not_found if 'CONFIG_SECCOMP' in config_host seccomp = declare_dependency(compile_args: config_host['SECCOMP_CFLAGS'].split(), @@ -301,6 +305,8 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +subdir('fsdev') + # Other build targets if 'CONFIG_GUEST_AGENT' in config_host subdir('qga') -- cgit v1.2.3-55-g7522 From 2d78b56e7abe327fc411d4c96ce0b3cffc0d9282 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 16:00:36 +0400 Subject: meson: keymap-gen Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 38 -------------------------------------- meson.build | 1 + ui/meson.build | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 38 deletions(-) create mode 100644 ui/meson.build diff --git a/Makefile b/Makefile index 39633ec7db..c07b6bb5b8 100644 --- a/Makefile +++ b/Makefile @@ -141,44 +141,6 @@ generated-files-y += module_block.h generated-files-y += .git-submodule-status -KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen -KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv - -KEYCODEMAP_FILES = \ - ui/input-keymap-atset1-to-qcode.c.inc \ - ui/input-keymap-linux-to-qcode.c.inc \ - ui/input-keymap-qcode-to-atset1.c.inc \ - ui/input-keymap-qcode-to-atset2.c.inc \ - ui/input-keymap-qcode-to-atset3.c.inc \ - ui/input-keymap-qcode-to-linux.c.inc \ - ui/input-keymap-qcode-to-qnum.c.inc \ - ui/input-keymap-qcode-to-sun.c.inc \ - ui/input-keymap-qnum-to-qcode.c.inc \ - ui/input-keymap-usb-to-qcode.c.inc \ - ui/input-keymap-win32-to-qcode.c.inc \ - ui/input-keymap-x11-to-qcode.c.inc \ - ui/input-keymap-xorgevdev-to-qcode.c.inc \ - ui/input-keymap-xorgkbd-to-qcode.c.inc \ - ui/input-keymap-xorgxquartz-to-qcode.c.inc \ - ui/input-keymap-xorgxwin-to-qcode.c.inc \ - ui/input-keymap-osx-to-qcode.c.inc \ - $(NULL) - -generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES) - -ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs - $(call quiet-command,\ - stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \ - test -e $(KEYCODEMAP_GEN) && \ - $(PYTHON) $(KEYCODEMAP_GEN) \ - --lang glib2 \ - --varname qemu_input_map_$${src}_to_$${dst} \ - code-map $(KEYCODEMAP_CSV) $${src} $${dst} \ - > $@ || rm -f $@, "GEN", "$@") - -$(KEYCODEMAP_GEN): .git-submodule-status -$(KEYCODEMAP_CSV): .git-submodule-status - edk2-decompressed = $(basename $(wildcard pc-bios/edk2-*.fd.bz2)) pc-bios/edk2-%.fd: pc-bios/edk2-%.fd.bz2 $(call quiet-command,bzip2 -d -c $< > $@,"BUNZIP2",$<) diff --git a/meson.build b/meson.build index 3e9e0a9b33..b4a2f9db3a 100644 --- a/meson.build +++ b/meson.build @@ -292,6 +292,7 @@ subdir('trace') subdir('util') subdir('crypto') subdir('storage-daemon') +subdir('ui') # Build targets from sourcesets diff --git a/ui/meson.build b/ui/meson.build new file mode 100644 index 0000000000..a6aa7f2b36 --- /dev/null +++ b/ui/meson.build @@ -0,0 +1,34 @@ +keymaps = [ + ['atset1', 'qcode'], + ['linux', 'qcode'], + ['qcode', 'atset1'], + ['qcode', 'atset2'], + ['qcode', 'atset3'], + ['qcode', 'linux'], + ['qcode', 'qnum'], + ['qcode', 'sun'], + ['qnum', 'qcode'], + ['usb', 'qcode'], + ['win32', 'qcode'], + ['x11', 'qcode'], + ['xorgevdev', 'qcode'], + ['xorgkbd', 'qcode'], + ['xorgxquartz', 'qcode'], + ['xorgxwin', 'qcode'], + ['osx', 'qcode'], +] + +if have_system + foreach e : keymaps + output = 'input-keymap-@0@-to-@1@.c.inc'.format(e[0], e[1]) + genh += custom_target(output, + output: output, + capture: true, + build_by_default: true, # to be removed when added to a target + input: files('keycodemapdb/data/keymaps.csv'), + command: [python.full_path(), files('keycodemapdb/tools/keymap-gen'), + '--lang', 'glib2', + '--varname', 'qemu_input_map_@0@_to_@1@'.format(e[0], e[1]), + 'code-map', '@INPUT0@', e[0], e[1]]) + endforeach +endif -- cgit v1.2.3-55-g7522 From 2c273f32d3489a54010c70b4065222ff4dda3f49 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 17:10:19 +0400 Subject: meson: generate qemu-version.h Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 27 +-------------------------- meson.build | 14 ++++++++++++-- scripts/qemu-version.sh | 25 +++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 28 deletions(-) create mode 100755 scripts/qemu-version.sh diff --git a/Makefile b/Makefile index c07b6bb5b8..0b86e3a981 100644 --- a/Makefile +++ b/Makefile @@ -121,21 +121,7 @@ include $(SRC_PATH)/rules.mak # lor is defined in rules.mak CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) -# Create QEMU_PKGVERSION and FULL_VERSION strings -# If PKGVERSION is set, use that; otherwise get version and -dirty status from git -QEMU_PKGVERSION := $(if $(PKGVERSION),$(PKGVERSION),$(shell \ - cd $(SRC_PATH); \ - if test -e .git; then \ - git describe --match 'v*' 2>/dev/null | tr -d '\n'; \ - if ! git diff-index --quiet HEAD &>/dev/null; then \ - echo "-dirty"; \ - fi; \ - fi)) - -# Either "version (pkgversion)", or just "version" if pkgversion not set -FULL_VERSION := $(if $(QEMU_PKGVERSION),$(VERSION) ($(QEMU_PKGVERSION)),$(VERSION)) - -generated-files-y = qemu-version.h config-host.h qemu-options.def +generated-files-y = config-host.h qemu-options.def generated-files-y += module_block.h @@ -275,17 +261,6 @@ include $(SRC_PATH)/tests/Makefile.include all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all modules -qemu-version.h: FORCE - $(call quiet-command, \ - (printf '#define QEMU_PKGVERSION "$(QEMU_PKGVERSION)"\n'; \ - printf '#define QEMU_FULL_VERSION "$(FULL_VERSION)"\n'; \ - ) > $@.tmp) - $(call quiet-command, if ! cmp -s $@ $@.tmp; then \ - mv $@.tmp $@; \ - else \ - rm $@.tmp; \ - fi) - config-host.h: config-host.h-timestamp config-host.h-timestamp: config-host.mak qemu-options.def: $(SRC_PATH)/qemu-options.hx $(SRC_PATH)/scripts/hxtool diff --git a/meson.build b/meson.build index b4a2f9db3a..e8df2a6fb0 100644 --- a/meson.build +++ b/meson.build @@ -158,6 +158,7 @@ have_block = have_system or have_tools # Generators +genh = [] qapi_gen = find_program('scripts/qapi-gen.py') qapi_gen_depends = [ meson.source_root() / 'scripts/qapi/__init__.py', meson.source_root() / 'scripts/qapi/commands.py', @@ -183,6 +184,17 @@ tracetool = [ '--backend=' + config_host['TRACE_BACKENDS'] ] +qemu_version_cmd = [find_program('scripts/qemu-version.sh'), + meson.current_source_dir(), + config_host['PKGVERSION'], config_host['VERSION']] +qemu_version = custom_target('qemu-version.h', + output: 'qemu-version.h', + command: qemu_version_cmd, + capture: true, + build_by_default: true, + build_always_stale: true) +genh += qemu_version + # Collect sourcesets. util_ss = ss.source_set() @@ -283,8 +295,6 @@ trace_events_subdirs += [ 'util', ] -genh = [] - subdir('qapi') subdir('qobject') subdir('stubs') diff --git a/scripts/qemu-version.sh b/scripts/qemu-version.sh new file mode 100755 index 0000000000..4847385e42 --- /dev/null +++ b/scripts/qemu-version.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +set -eu + +dir="$1" +pkgversion="$2" +version="$3" + +if [ -z "$pkgversion"]; then + cd "$dir" + if [ -e .git ]; then + pkgversion=$(git describe --match 'v*' --dirty | echo "") + fi +fi + +if [ -n "$pkgversion" ]; then + fullversion="$version ($pkgversion)" +else + fullversion="$version" +fi + +cat < Signed-off-by: Paolo Bonzini --- Makefile | 19 ------------------- meson.build | 1 + ui/meson.build | 2 ++ ui/shader/meson.build | 15 +++++++++++++++ 4 files changed, 18 insertions(+), 19 deletions(-) create mode 100644 ui/shader/meson.build diff --git a/Makefile b/Makefile index 0b86e3a981..e7394e748d 100644 --- a/Makefile +++ b/Makefile @@ -393,7 +393,6 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod scsi/*.pod rm -f qemu-img-cmds.h - rm -f ui/shader/*-vert.h ui/shader/*-frag.h rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) rm -f config-all-devices.mak rm -f $(SUBDIR_DEVICES_MAK) @@ -618,24 +617,6 @@ endif $(MAKE) $(SUBDIR_MAKEFLAGS) TARGET_DIR=$$d/ -C $$d $@ || exit 1 ; \ done -# opengl shader programs -ui/shader/%-vert.h: $(SRC_PATH)/ui/shader/%.vert $(SRC_PATH)/scripts/shaderinclude.pl - @mkdir -p $(dir $@) - $(call quiet-command,\ - perl $(SRC_PATH)/scripts/shaderinclude.pl $< > $@,\ - "VERT","$@") - -ui/shader/%-frag.h: $(SRC_PATH)/ui/shader/%.frag $(SRC_PATH)/scripts/shaderinclude.pl - @mkdir -p $(dir $@) - $(call quiet-command,\ - perl $(SRC_PATH)/scripts/shaderinclude.pl $< > $@,\ - "FRAG","$@") - -ui/shader.o: $(SRC_PATH)/ui/shader.c \ - ui/shader/texture-blit-vert.h \ - ui/shader/texture-blit-flip-vert.h \ - ui/shader/texture-blit-frag.h - # documentation MAKEINFO=makeinfo MAKEINFOINCLUDES= -I docs -I $( Signed-off-by: Paolo Bonzini --- Makefile | 8 +------- Makefile.target | 6 ------ meson.build | 22 ++++++++++++++++++++++ scripts/hxtool | 2 +- 4 files changed, 24 insertions(+), 14 deletions(-) mode change 100644 => 100755 scripts/hxtool diff --git a/Makefile b/Makefile index e7394e748d..13df463e33 100644 --- a/Makefile +++ b/Makefile @@ -121,7 +121,7 @@ include $(SRC_PATH)/rules.mak # lor is defined in rules.mak CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) -generated-files-y = config-host.h qemu-options.def +generated-files-y = config-host.h generated-files-y += module_block.h @@ -263,8 +263,6 @@ all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all mo config-host.h: config-host.h-timestamp config-host.h-timestamp: config-host.mak -qemu-options.def: $(SRC_PATH)/qemu-options.hx $(SRC_PATH)/scripts/hxtool - $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$@") TARGET_DIRS_RULES := $(foreach t, all fuzz clean install, $(addsuffix /$(t), $(TARGET_DIRS))) @@ -371,9 +369,6 @@ ifdef CONFIG_MPATH scsi/qemu-pr-helper$(EXESUF): LIBS += -ludev -lmultipath -lmpathpersist endif -qemu-img-cmds.h: $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/scripts/hxtool - $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$@") - module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak $(call quiet-command,$(PYTHON) $< $@ \ $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ @@ -392,7 +387,6 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f $(edk2-decompressed) rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod scsi/*.pod - rm -f qemu-img-cmds.h rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) rm -f config-all-devices.mak rm -f $(SUBDIR_DEVICES_MAK) diff --git a/Makefile.target b/Makefile.target index 0b323641bb..257afc2723 100644 --- a/Makefile.target +++ b/Makefile.target @@ -225,12 +225,6 @@ endif gdbstub-xml.c: $(TARGET_XML_FILES) $(SRC_PATH)/scripts/feature_to_c.sh $(call quiet-command,rm -f $@ && $(SHELL) $(SRC_PATH)/scripts/feature_to_c.sh $@ $(TARGET_XML_FILES),"GEN","$(TARGET_DIR)$@") -hmp-commands.h: $(SRC_PATH)/hmp-commands.hx $(SRC_PATH)/scripts/hxtool - $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$(TARGET_DIR)$@") - -hmp-commands-info.h: $(SRC_PATH)/hmp-commands-info.hx $(SRC_PATH)/scripts/hxtool - $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -h < $< > $@,"GEN","$(TARGET_DIR)$@") - clean: clean-target rm -f *.a *~ $(PROGS) rm -f $(shell find . -name '*.[od]') diff --git a/meson.build b/meson.build index 2fb209b228..222b0d0e77 100644 --- a/meson.build +++ b/meson.build @@ -159,6 +159,7 @@ have_block = have_system or have_tools # Generators genh = [] +hxtool = find_program('scripts/hxtool') shaderinclude = find_program('scripts/shaderinclude.pl') qapi_gen = find_program('scripts/qapi-gen.py') qapi_gen_depends = [ meson.source_root() / 'scripts/qapi/__init__.py', @@ -196,6 +197,27 @@ qemu_version = custom_target('qemu-version.h', build_always_stale: true) genh += qemu_version +hxdep = [] +hx_headers = [ + ['qemu-options.hx', 'qemu-options.def'], + ['qemu-img-cmds.hx', 'qemu-img-cmds.h'], +] +if have_system + hx_headers += [ + ['hmp-commands.hx', 'hmp-commands.h'], + ['hmp-commands-info.hx', 'hmp-commands-info.h'], + ] +endif +foreach d : hx_headers + custom_target(d[1], + input: files(d[0]), + output: d[1], + capture: true, + build_by_default: true, # to be removed when added to a target + command: [hxtool, '-h', '@INPUT0@']) +endforeach +genh += hxdep + # Collect sourcesets. util_ss = ss.source_set() diff --git a/scripts/hxtool b/scripts/hxtool old mode 100644 new mode 100755 index 7b1452f3cf..80516b9437 --- a/scripts/hxtool +++ b/scripts/hxtool @@ -19,6 +19,6 @@ hxtoh() case "$1" in "-h") hxtoh ;; *) exit 1 ;; -esac +esac < "$2" exit 0 -- cgit v1.2.3-55-g7522 From bdcbea7ae5cf04733465a900a3356ff998e965e3 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 21:22:31 +0400 Subject: meson: handle edk2 bios and descriptors Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- Makefile | 29 ----------------------------- meson.build | 1 + pc-bios/descriptors/meson.build | 14 ++++++++++++++ pc-bios/meson.build | 27 +++++++++++++++++++++++++++ 4 files changed, 42 insertions(+), 29 deletions(-) create mode 100644 pc-bios/descriptors/meson.build create mode 100644 pc-bios/meson.build diff --git a/Makefile b/Makefile index 13df463e33..bc7647d37b 100644 --- a/Makefile +++ b/Makefile @@ -127,10 +127,6 @@ generated-files-y += module_block.h generated-files-y += .git-submodule-status -edk2-decompressed = $(basename $(wildcard pc-bios/edk2-*.fd.bz2)) -pc-bios/edk2-%.fd: pc-bios/edk2-%.fd.bz2 - $(call quiet-command,bzip2 -d -c $< > $@,"BUNZIP2",$<) - # Don't try to regenerate Makefile or configure # We don't generate any of them Makefile: ; @@ -274,9 +270,6 @@ $(SOFTMMU_ALL_RULES): $(chardev-obj-y) $(SOFTMMU_ALL_RULES): $(crypto-obj-y) $(SOFTMMU_ALL_RULES): $(io-obj-y) $(SOFTMMU_ALL_RULES): config-all-devices.mak -ifdef DECOMPRESS_EDK2_BLOBS -$(SOFTMMU_ALL_RULES): $(edk2-decompressed) -endif SOFTMMU_FUZZ_RULES=$(filter %-softmmu/fuzz, $(TARGET_DIRS_RULES)) $(SOFTMMU_FUZZ_RULES): $(authz-obj-y) @@ -384,7 +377,6 @@ clean: recurse-clean ninja-clean clean-ctlist ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-arm.a \ ! -path ./roms/edk2/BaseTools/Source/Python/UPT/Dll/sqlite3.dll \ -exec rm {} + - rm -f $(edk2-decompressed) rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod scsi/*.pod rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) @@ -461,13 +453,8 @@ edk2-licenses.txt \ hppa-firmware.img \ opensbi-riscv32-sifive_u-fw_jump.bin opensbi-riscv32-virt-fw_jump.bin \ opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin - - -DESCS=50-edk2-i386-secure.json 50-edk2-x86_64-secure.json \ -60-edk2-aarch64.json 60-edk2-arm.json 60-edk2-i386.json 60-edk2-x86_64.json else BLOBS= -DESCS= endif # Note that we manually filter-out the non-Sphinx documentation which @@ -544,7 +531,6 @@ install-includedir: export DESTDIR install: all $(if $(BUILD_DOCS),install-doc) \ install-datadir install-localstatedir install-includedir \ - $(if $(INSTALL_BLOBS),$(edk2-decompressed)) \ recurse-install ifneq ($(TOOLS),) $(call install-prog,$(TOOLS),$(DESTDIR)$(bindir)) @@ -567,21 +553,6 @@ ifneq ($(BLOBS),) set -e; for x in $(BLOBS); do \ $(INSTALL_DATA) $(SRC_PATH)/pc-bios/$$x "$(DESTDIR)$(qemu_datadir)"; \ done -endif -ifdef INSTALL_BLOBS - set -e; for x in $(edk2-decompressed); do \ - $(INSTALL_DATA) $$x "$(DESTDIR)$(qemu_datadir)"; \ - done -endif -ifneq ($(DESCS),) - $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/firmware" - set -e; tmpf=$$(mktemp); trap 'rm -f -- "$$tmpf"' EXIT; \ - for x in $(DESCS); do \ - sed -e 's,@DATADIR@,$(qemu_datadir),' \ - "$(SRC_PATH)/pc-bios/descriptors/$$x" > "$$tmpf"; \ - $(INSTALL_DATA) "$$tmpf" \ - "$(DESTDIR)$(qemu_datadir)/firmware/$$x"; \ - done endif for s in $(ICON_SIZES); do \ mkdir -p "$(DESTDIR)$(qemu_icondir)/hicolor/$${s}/apps"; \ diff --git a/meson.build b/meson.build index 222b0d0e77..528198b6bd 100644 --- a/meson.build +++ b/meson.build @@ -383,6 +383,7 @@ if have_tools endif subdir('tools') +subdir('pc-bios') summary_info = {} summary_info += {'Install prefix': config_host['prefix']} diff --git a/pc-bios/descriptors/meson.build b/pc-bios/descriptors/meson.build new file mode 100644 index 0000000000..7c715bace8 --- /dev/null +++ b/pc-bios/descriptors/meson.build @@ -0,0 +1,14 @@ +foreach f: [ + '50-edk2-i386-secure.json', + '50-edk2-x86_64-secure.json', + '60-edk2-aarch64.json', + '60-edk2-arm.json', + '60-edk2-i386.json', + '60-edk2-x86_64.json' +] + configure_file(input: files(f), + output: f, + configuration: {'DATADIR': config_host['qemu_datadir']}, + install: install_blobs, + install_dir: config_host['qemu_datadir'] / 'firmware') +endforeach diff --git a/pc-bios/meson.build b/pc-bios/meson.build new file mode 100644 index 0000000000..6e3bfe3ca4 --- /dev/null +++ b/pc-bios/meson.build @@ -0,0 +1,27 @@ +bzip2 = find_program('bzip2') + +install_blobs = 'INSTALL_BLOBS' in config_host +if 'DECOMPRESS_EDK2_BLOBS' in config_host + fds = [ + 'edk2-aarch64-code.fd', + 'edk2-arm-code.fd', + 'edk2-arm-vars.fd', + 'edk2-i386-code.fd', + 'edk2-i386-secure-code.fd', + 'edk2-i386-vars.fd', + 'edk2-x86_64-code.fd', + 'edk2-x86_64-secure-code.fd', + ] + + foreach f : fds + custom_target(f, + output: f, + input: '@0@.bz2'.format(f), + capture: true, + install: install_blobs, + install_dir: config_host['qemu_datadir'], + command: [ bzip2, '-dc', '@INPUT0@' ]) + endforeach +endif + +subdir('descriptors') -- cgit v1.2.3-55-g7522 From ce1c1e7a8b4719876ca28bf38234069725f3c1ef Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 28 Jan 2020 16:41:44 +0100 Subject: meson: convert check-decodetree Signed-off-by: Paolo Bonzini --- meson.build | 2 ++ tests/Makefile.include | 9 +-------- tests/meson.build | 4 ++++ 3 files changed, 7 insertions(+), 8 deletions(-) create mode 100644 tests/meson.build diff --git a/meson.build b/meson.build index 528198b6bd..6384401e9f 100644 --- a/meson.build +++ b/meson.build @@ -6,6 +6,7 @@ not_found = dependency('', required: false) keyval = import('unstable-keyval') ss = import('sourceset') +sh = find_program('sh') cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') @@ -384,6 +385,7 @@ endif subdir('tools') subdir('pc-bios') +subdir('tests') summary_info = {} summary_info += {'Install prefix': config_host['prefix']} diff --git a/tests/Makefile.include b/tests/Makefile.include index f277d238fb..12b0316a72 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -894,13 +894,6 @@ check-tests/qapi-schema/frontend: $(addprefix $(SRC_PATH)/, $(check-qapi-schema- check-tests/qapi-schema/doc-good.texi: tests/qapi-schema/doc-good.test.texi @diff -u $(SRC_PATH)/tests/qapi-schema/doc-good.texi $< -.PHONY: check-decodetree -check-decodetree: - $(call quiet-command, \ - cd $(SRC_PATH)/tests/decode && \ - ./check.sh "$(PYTHON)" "$(SRC_PATH)/scripts/decodetree.py", \ - TEST, decodetree.py) - # Python venv for running tests .PHONY: check-venv check-acceptance @@ -969,7 +962,7 @@ check-clean: rm -f tests/qtest/dbus-vmstate1-gen-timestamp rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) -check: check-block check-qapi-schema check-unit check-softfloat check-qtest check-decodetree +check: check-block check-qapi-schema check-unit check-softfloat check-qtest clean: check-clean diff --git a/tests/meson.build b/tests/meson.build new file mode 100644 index 0000000000..5c52021dc9 --- /dev/null +++ b/tests/meson.build @@ -0,0 +1,4 @@ +test('decodetree', sh, + args: [ files('decode/check.sh'), config_host['PYTHON'], files('../scripts/decodetree.py') ], + workdir: meson.current_source_dir() / 'decode', + suite: 'decodetree') -- cgit v1.2.3-55-g7522 From 3941996b131bada064d168b451202c1125d55e6b Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Aug 2020 14:08:31 +0200 Subject: meson: convert tests/fp and check-softfloat Signed-off-by: Paolo Bonzini --- configure | 2 +- tests/Makefile.include | 158 +----------- tests/fp/Makefile | 600 ---------------------------------------------- tests/fp/meson.build | 636 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/meson.build | 4 + 5 files changed, 643 insertions(+), 757 deletions(-) delete mode 100644 tests/fp/Makefile create mode 100644 tests/fp/meson.build diff --git a/configure b/configure index 5e5923dfd6..e58607a984 100755 --- a/configure +++ b/configure @@ -8378,7 +8378,7 @@ DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw" DIRS="$DIRS roms/seabios" LINKS="Makefile" LINKS="$LINKS tests/tcg/lm32/Makefile po/Makefile" -LINKS="$LINKS tests/tcg/Makefile.target tests/fp/Makefile" +LINKS="$LINKS tests/tcg/Makefile.target" LINKS="$LINKS tests/plugin/Makefile" LINKS="$LINKS pc-bios/optionrom/Makefile pc-bios/keymaps" LINKS="$LINKS pc-bios/s390-ccw/Makefile" diff --git a/tests/Makefile.include b/tests/Makefile.include index 12b0316a72..8fb6baa0a1 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -437,9 +437,6 @@ tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) tests/atomic64-bench$(EXESUF): tests/atomic64-bench.o $(test-util-obj-y) -tests/fp/%: - $(MAKE) -C $(dir $@) $(notdir $@) - tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ hw/core/bus.o \ @@ -675,157 +672,6 @@ check-report-unit.tap: $(check-unit-y) check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap -# FPU Emulation tests (aka softfloat) -# -# As we still have some places that need fixing the rules are a little -# more complex than they need to be and have to override some of the -# generic Makefile expansions. Once we are cleanly passing all -# the tests we can simplify the make syntax. - -FP_TEST_BIN=$(BUILD_DIR)/tests/fp/fp-test - -# the build dir is created by configure -$(FP_TEST_BIN): config-host.h $(test-util-obj-y) - $(call quiet-command, \ - $(MAKE) $(SUBDIR_MAKEFLAGS) -C $(dir $@) V="$(V)" $(notdir $@), \ - "BUILD", "$(notdir $@)") - -# The full test suite can take a bit of time, default to a quick run -# "-l 2 -r all" can take more than a day for some operations and is best -# run manually -FP_TL=-l 1 -r all - -# $1 = tests, $2 = description, $3 = test flags -test-softfloat = $(call quiet-command, \ - cd $(BUILD_DIR)/tests/fp && \ - ./fp-test -s $(if $3,$3,$(FP_TL)) $1 > $2.out 2>&1 || \ - (cat $2.out && exit 1;), \ - "FLOAT TEST", $2) - -# Conversion Routines: Float to Float -# FIXME: f32_to_f128 (broken), f64_to_f128 (broken) -# FIXME: f128_to_f32(broken), f128_to_f64 (broken) -# FIXME: f128_to_extF80 (broken) -check-softfloat-conv-f2f: $(FP_TEST_BIN) - $(call test-softfloat, \ - f16_to_f32 f16_to_f64 \ - f16_to_extF80 f16_to_f128 \ - f32_to_f16 f32_to_f64 \ - f32_to_extF80 \ - f64_to_f16 f64_to_f32 \ - extF80_to_f16 extF80_to_f32 \ - extF80_to_f64 extF80_to_f128 \ - f128_to_f16, \ - float-to-float) - -# Conversion Routines: Int and Uint to Float -# FIXME: i32_to_extF80 (broken), i64_to_extF80 (broken) -# ui32_to_f128 (not implemented) -check-softfloat-conv-to-float: $(FP_TEST_BIN) - $(call test-softfloat, \ - i32_to_f16 i64_to_f16 \ - i32_to_f32 i64_to_f32 \ - i32_to_f64 i64_to_f64 \ - i32_to_f128 i64_to_f128, int-to-float) - $(call test-softfloat, \ - ui32_to_f16 ui64_to_f16 \ - ui32_to_f32 ui64_to_f32 \ - ui32_to_f64 ui64_to_f64 \ - ui32_to_extF80 ui64_to_extF80 \ - ui64_to_f128, uint-to-float) - -# Conversion Routines: Float to integers -# FIXME: extF80_roundToInt (broken) -check-softfloat-conv-to-int: $(FP_TEST_BIN) - $(call test-softfloat, \ - f16_to_i32 f16_to_i32_r_minMag \ - f32_to_i32 f32_to_i32_r_minMag \ - f64_to_i32 f64_to_i32_r_minMag \ - extF80_to_i32 extF80_to_i32_r_minMag \ - f128_to_i32 f128_to_i32_r_minMag \ - f16_to_i64 f16_to_i64_r_minMag \ - f32_to_i64 f32_to_i64_r_minMag \ - f64_to_i64 f64_to_i64_r_minMag \ - extF80_to_i64 extF80_to_i64_r_minMag \ - f128_to_i64 f128_to_i64_r_minMag, \ - float-to-int) - $(call test-softfloat, \ - f16_to_ui32 f16_to_ui32_r_minMag \ - f32_to_ui32 f32_to_ui32_r_minMag \ - f64_to_ui32 f64_to_ui32_r_minMag \ - extF80_to_ui32 extF80_to_ui32_r_minMag \ - f128_to_ui32 f128_to_ui32_r_minMag \ - f16_to_ui64 f16_to_ui64_r_minMag \ - f32_to_ui64 f32_to_ui64_r_minMag \ - f64_to_ui64 f64_to_ui64_r_minMag \ - extF80_to_ui64 extF80_to_ui64_r_minMag \ - f128_to_ui64 f128_to_ui64_r_minMag, \ - float-to-uint) - $(call test-softfloat, \ - f16_roundToInt f32_roundToInt \ - f64_roundToInt f128_roundToInt, \ - round-to-integer) - -.PHONY: check-softfloat-conv -check-softfloat-conv: check-softfloat-conv-f2f -check-softfloat-conv: check-softfloat-conv-to-float -check-softfloat-conv: check-softfloat-conv-to-int - -# Generic rule for all float operations -# -# Some patterns are overridden due to broken or missing tests. -# Hopefully these can be removed over time. - -check-softfloat-%: $(FP_TEST_BIN) - $(call test-softfloat, f16_$* f32_$* f64_$* extF80_$* f128_$*, $*) - -# Float Compare routines -SF_COMPARE_OPS=eq eq_signaling le le_quiet lt_quiet -SF_COMPARE_RULES=$(patsubst %,check-softfloat-%, $(SF_COMPARE_OPS)) - -# FIXME: extF80_lt_quiet (broken) -check-softfloat-lt_quiet: $(FP_TEST_BIN) - $(call test-softfloat, \ - f16_lt_quiet f32_lt_quiet f64_lt_quiet \ - f128_lt_quiet, \ - lt_quiet) - -.PHONY: check-softfloat-compare -check-softfloat-compare: $(SF_COMPARE_RULES) - -# Math Operations - -# FIXME: extF80_mulAdd (missing) -check-softfloat-mulAdd: $(FP_TEST_BIN) - $(call test-softfloat, \ - f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd, \ - mulAdd,-l 1) - -# FIXME: extF80_rem (broken) -check-softfloat-rem: $(FP_TEST_BIN) - $(call test-softfloat, \ - f16_rem f32_rem f64_rem f128_rem, \ - rem) - -SF_MATH_OPS=add sub mul mulAdd div rem sqrt -SF_MATH_RULES=$(patsubst %,check-softfloat-%, $(SF_MATH_OPS)) - -.PHONY: check-softfloat-ops -check-softfloat-ops: $(SF_MATH_RULES) - -# Finally a generic rule to test all of softfoat. If TCG isnt't -# enabled we define a null operation which skips the tests. - -.PHONY: check-softfloat -ifeq ($(CONFIG_TCG),y) -build-softfloat: $(FP_TEST_BIN) -check-softfloat: build-softfloat check-softfloat-conv check-softfloat-compare check-softfloat-ops -else -build-softfloat check-softfloat: - $(call quiet-command, /bin/true, "FLOAT TEST", \ - "SKIPPED for non-TCG builds") -endif - # Plugins ifeq ($(CONFIG_PLUGIN),y) .PHONY: plugins @@ -953,7 +799,7 @@ check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) ifeq ($(CONFIG_TOOLS),y) check-block: $(patsubst %,check-%, $(check-block-y)) endif -check-build: build-unit build-softfloat build-qtest +check-build: build-unit build-qtest check-clean: rm -rf $(check-unit-y) tests/*.o tests/*/*.o $(QEMU_IOTESTS_HELPERS-y) @@ -962,7 +808,7 @@ check-clean: rm -f tests/qtest/dbus-vmstate1-gen-timestamp rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) -check: check-block check-qapi-schema check-unit check-softfloat check-qtest +check: check-block check-qapi-schema check-unit check-qtest clean: check-clean diff --git a/tests/fp/Makefile b/tests/fp/Makefile deleted file mode 100644 index 56768ecfd2..0000000000 --- a/tests/fp/Makefile +++ /dev/null @@ -1,600 +0,0 @@ -BUILD_DIR := $(CURDIR)/../.. - -include $(BUILD_DIR)/config-host.mak -include $(SRC_PATH)/rules.mak - -SOFTFLOAT_DIR := $(SRC_PATH)/tests/fp/berkeley-softfloat-3 -TESTFLOAT_DIR := $(SRC_PATH)/tests/fp/berkeley-testfloat-3 - -SF_SOURCE_DIR := $(SOFTFLOAT_DIR)/source -SF_INCLUDE_DIR := $(SOFTFLOAT_DIR)/source/include -# we could use any specialize here, it doesn't matter -SF_SPECIALIZE := 8086-SSE -SF_SPECIALIZE_DIR := $(SF_SOURCE_DIR)/$(SF_SPECIALIZE) - -TF_SOURCE_DIR := $(TESTFLOAT_DIR)/source - -$(call set-vpath, $(SRC_PATH)/fpu $(SRC_PATH)/tests/fp) - -LIBQEMUUTIL := $(BUILD_DIR)/libqemuutil.a - -# Use this variable to be clear when we pull in our own implementation -# We build the object with a default rule thanks to the vpath above -QEMU_SOFTFLOAT_OBJ := softfloat.o - -QEMU_INCLUDES += -I$(SRC_PATH)/tests/fp -QEMU_INCLUDES += -I$(SF_INCLUDE_DIR) -QEMU_INCLUDES += -I$(SF_SPECIALIZE_DIR) -QEMU_INCLUDES += -I$(TF_SOURCE_DIR) - -# work around TARGET_* poisoning -QEMU_CFLAGS += -DHW_POISON_H -# define a target to match testfloat's implementation-defined choices, such as -# whether to raise the invalid flag when dealing with NaNs in muladd. -QEMU_CFLAGS += -DTARGET_ARM - -# capstone has a platform.h file that clashes with softfloat's -QEMU_CFLAGS := $(filter-out %capstone, $(QEMU_CFLAGS)) - -# softfloat defines -SF_OPTS := -SF_OPTS += -DSOFTFLOAT_ROUND_ODD -SF_OPTS += -DINLINE_LEVEL=5 -SF_OPTS += -DSOFTFLOAT_FAST_DIV32TO16 -SF_OPTS += -DSOFTFLOAT_FAST_DIV64TO32 -SF_OPTS += -DSOFTFLOAT_FAST_INT64 -QEMU_CFLAGS += $(SF_OPTS) - -# silence the build of softfloat objects -SF_CFLAGS += -Wno-missing-prototypes -SF_CFLAGS += -Wno-redundant-decls -SF_CFLAGS += -Wno-return-type -SF_CFLAGS += -Wno-error - -# testfloat defines -TF_OPTS := -TF_OPTS += -DFLOAT16 -TF_OPTS += -DFLOAT64 -TF_OPTS += -DEXTFLOAT80 -TF_OPTS += -DFLOAT128 -TF_OPTS += -DFLOAT_ROUND_ODD -TF_OPTS += -DLONG_DOUBLE_IS_EXTFLOAT80 -QEMU_CFLAGS += $(TF_OPTS) - -# silence the build of testfloat objects -TF_CFLAGS := -TF_CFLAGS += -Wno-strict-prototypes -TF_CFLAGS += -Wno-unknown-pragmas -TF_CFLAGS += -Wno-uninitialized -TF_CFLAGS += -Wno-missing-prototypes -TF_CFLAGS += -Wno-return-type -TF_CFLAGS += -Wno-unused-function -TF_CFLAGS += -Wno-error - -# softfloat objects -SF_OBJS_PRIMITIVES := -SF_OBJS_PRIMITIVES += s_eq128.o -SF_OBJS_PRIMITIVES += s_le128.o -SF_OBJS_PRIMITIVES += s_lt128.o -SF_OBJS_PRIMITIVES += s_shortShiftLeft128.o -SF_OBJS_PRIMITIVES += s_shortShiftRight128.o -SF_OBJS_PRIMITIVES += s_shortShiftRightJam64.o -SF_OBJS_PRIMITIVES += s_shortShiftRightJam64Extra.o -SF_OBJS_PRIMITIVES += s_shortShiftRightJam128.o -SF_OBJS_PRIMITIVES += s_shortShiftRightJam128Extra.o -SF_OBJS_PRIMITIVES += s_shiftRightJam32.o -SF_OBJS_PRIMITIVES += s_shiftRightJam64.o -SF_OBJS_PRIMITIVES += s_shiftRightJam64Extra.o -SF_OBJS_PRIMITIVES += s_shiftRightJam128.o -SF_OBJS_PRIMITIVES += s_shiftRightJam128Extra.o -SF_OBJS_PRIMITIVES += s_shiftRightJam256M.o -SF_OBJS_PRIMITIVES += s_countLeadingZeros8.o -SF_OBJS_PRIMITIVES += s_countLeadingZeros16.o -SF_OBJS_PRIMITIVES += s_countLeadingZeros32.o -SF_OBJS_PRIMITIVES += s_countLeadingZeros64.o -SF_OBJS_PRIMITIVES += s_add128.o -SF_OBJS_PRIMITIVES += s_add256M.o -SF_OBJS_PRIMITIVES += s_sub128.o -SF_OBJS_PRIMITIVES += s_sub256M.o -SF_OBJS_PRIMITIVES += s_mul64ByShifted32To128.o -SF_OBJS_PRIMITIVES += s_mul64To128.o -SF_OBJS_PRIMITIVES += s_mul128By32.o -SF_OBJS_PRIMITIVES += s_mul128To256M.o -SF_OBJS_PRIMITIVES += s_approxRecip_1Ks.o -SF_OBJS_PRIMITIVES += s_approxRecip32_1.o -SF_OBJS_PRIMITIVES += s_approxRecipSqrt_1Ks.o -SF_OBJS_PRIMITIVES += s_approxRecipSqrt32_1.o - -SF_OBJS_SPECIALIZE := -SF_OBJS_SPECIALIZE += softfloat_raiseFlags.o -SF_OBJS_SPECIALIZE += s_f16UIToCommonNaN.o -SF_OBJS_SPECIALIZE += s_commonNaNToF16UI.o -SF_OBJS_SPECIALIZE += s_propagateNaNF16UI.o -SF_OBJS_SPECIALIZE += s_f32UIToCommonNaN.o -SF_OBJS_SPECIALIZE += s_commonNaNToF32UI.o -SF_OBJS_SPECIALIZE += s_propagateNaNF32UI.o -SF_OBJS_SPECIALIZE += s_f64UIToCommonNaN.o -SF_OBJS_SPECIALIZE += s_commonNaNToF64UI.o -SF_OBJS_SPECIALIZE += s_propagateNaNF64UI.o -SF_OBJS_SPECIALIZE += extF80M_isSignalingNaN.o -SF_OBJS_SPECIALIZE += s_extF80UIToCommonNaN.o -SF_OBJS_SPECIALIZE += s_commonNaNToExtF80UI.o -SF_OBJS_SPECIALIZE += s_propagateNaNExtF80UI.o -SF_OBJS_SPECIALIZE += f128M_isSignalingNaN.o -SF_OBJS_SPECIALIZE += s_f128UIToCommonNaN.o -SF_OBJS_SPECIALIZE += s_commonNaNToF128UI.o -SF_OBJS_SPECIALIZE += s_propagateNaNF128UI.o - -SF_OBJS_OTHERS := -SF_OBJS_OTHERS += s_roundToUI32.o -SF_OBJS_OTHERS += s_roundToUI64.o -SF_OBJS_OTHERS += s_roundToI32.o -SF_OBJS_OTHERS += s_roundToI64.o -SF_OBJS_OTHERS += s_normSubnormalF16Sig.o -SF_OBJS_OTHERS += s_roundPackToF16.o -SF_OBJS_OTHERS += s_normRoundPackToF16.o -SF_OBJS_OTHERS += s_addMagsF16.o -SF_OBJS_OTHERS += s_subMagsF16.o -SF_OBJS_OTHERS += s_mulAddF16.o -SF_OBJS_OTHERS += s_normSubnormalF32Sig.o -SF_OBJS_OTHERS += s_roundPackToF32.o -SF_OBJS_OTHERS += s_normRoundPackToF32.o -SF_OBJS_OTHERS += s_addMagsF32.o -SF_OBJS_OTHERS += s_subMagsF32.o -SF_OBJS_OTHERS += s_mulAddF32.o -SF_OBJS_OTHERS += s_normSubnormalF64Sig.o -SF_OBJS_OTHERS += s_roundPackToF64.o -SF_OBJS_OTHERS += s_normRoundPackToF64.o -SF_OBJS_OTHERS += s_addMagsF64.o -SF_OBJS_OTHERS += s_subMagsF64.o -SF_OBJS_OTHERS += s_mulAddF64.o -SF_OBJS_OTHERS += s_normSubnormalExtF80Sig.o -SF_OBJS_OTHERS += s_roundPackToExtF80.o -SF_OBJS_OTHERS += s_normRoundPackToExtF80.o -SF_OBJS_OTHERS += s_addMagsExtF80.o -SF_OBJS_OTHERS += s_subMagsExtF80.o -SF_OBJS_OTHERS += s_normSubnormalF128Sig.o -SF_OBJS_OTHERS += s_roundPackToF128.o -SF_OBJS_OTHERS += s_normRoundPackToF128.o -SF_OBJS_OTHERS += s_addMagsF128.o -SF_OBJS_OTHERS += s_subMagsF128.o -SF_OBJS_OTHERS += s_mulAddF128.o -SF_OBJS_OTHERS += softfloat_state.o -SF_OBJS_OTHERS += ui32_to_f16.o -SF_OBJS_OTHERS += ui32_to_f32.o -SF_OBJS_OTHERS += ui32_to_f64.o -SF_OBJS_OTHERS += ui32_to_extF80.o -SF_OBJS_OTHERS += ui32_to_extF80M.o -SF_OBJS_OTHERS += ui32_to_f128.o -SF_OBJS_OTHERS += ui32_to_f128M.o -SF_OBJS_OTHERS += ui64_to_f16.o -SF_OBJS_OTHERS += ui64_to_f32.o -SF_OBJS_OTHERS += ui64_to_f64.o -SF_OBJS_OTHERS += ui64_to_extF80.o -SF_OBJS_OTHERS += ui64_to_extF80M.o -SF_OBJS_OTHERS += ui64_to_f128.o -SF_OBJS_OTHERS += ui64_to_f128M.o -SF_OBJS_OTHERS += i32_to_f16.o -SF_OBJS_OTHERS += i32_to_f32.o -SF_OBJS_OTHERS += i32_to_f64.o -SF_OBJS_OTHERS += i32_to_extF80.o -SF_OBJS_OTHERS += i32_to_extF80M.o -SF_OBJS_OTHERS += i32_to_f128.o -SF_OBJS_OTHERS += i32_to_f128M.o -SF_OBJS_OTHERS += i64_to_f16.o -SF_OBJS_OTHERS += i64_to_f32.o -SF_OBJS_OTHERS += i64_to_f64.o -SF_OBJS_OTHERS += i64_to_extF80.o -SF_OBJS_OTHERS += i64_to_extF80M.o -SF_OBJS_OTHERS += i64_to_f128.o -SF_OBJS_OTHERS += i64_to_f128M.o -SF_OBJS_OTHERS += f16_to_ui32.o -SF_OBJS_OTHERS += f16_to_ui64.o -SF_OBJS_OTHERS += f16_to_i32.o -SF_OBJS_OTHERS += f16_to_i64.o -SF_OBJS_OTHERS += f16_to_ui32_r_minMag.o -SF_OBJS_OTHERS += f16_to_ui64_r_minMag.o -SF_OBJS_OTHERS += f16_to_i32_r_minMag.o -SF_OBJS_OTHERS += f16_to_i64_r_minMag.o -SF_OBJS_OTHERS += f16_to_f32.o -SF_OBJS_OTHERS += f16_to_f64.o -SF_OBJS_OTHERS += f16_to_extF80.o -SF_OBJS_OTHERS += f16_to_extF80M.o -SF_OBJS_OTHERS += f16_to_f128.o -SF_OBJS_OTHERS += f16_to_f128M.o -SF_OBJS_OTHERS += f16_roundToInt.o -SF_OBJS_OTHERS += f16_add.o -SF_OBJS_OTHERS += f16_sub.o -SF_OBJS_OTHERS += f16_mul.o -SF_OBJS_OTHERS += f16_mulAdd.o -SF_OBJS_OTHERS += f16_div.o -SF_OBJS_OTHERS += f16_rem.o -SF_OBJS_OTHERS += f16_sqrt.o -SF_OBJS_OTHERS += f16_eq.o -SF_OBJS_OTHERS += f16_le.o -SF_OBJS_OTHERS += f16_lt.o -SF_OBJS_OTHERS += f16_eq_signaling.o -SF_OBJS_OTHERS += f16_le_quiet.o -SF_OBJS_OTHERS += f16_lt_quiet.o -SF_OBJS_OTHERS += f16_isSignalingNaN.o -SF_OBJS_OTHERS += f32_to_ui32.o -SF_OBJS_OTHERS += f32_to_ui64.o -SF_OBJS_OTHERS += f32_to_i32.o -SF_OBJS_OTHERS += f32_to_i64.o -SF_OBJS_OTHERS += f32_to_ui32_r_minMag.o -SF_OBJS_OTHERS += f32_to_ui64_r_minMag.o -SF_OBJS_OTHERS += f32_to_i32_r_minMag.o -SF_OBJS_OTHERS += f32_to_i64_r_minMag.o -SF_OBJS_OTHERS += f32_to_f16.o -SF_OBJS_OTHERS += f32_to_f64.o -SF_OBJS_OTHERS += f32_to_extF80.o -SF_OBJS_OTHERS += f32_to_extF80M.o -SF_OBJS_OTHERS += f32_to_f128.o -SF_OBJS_OTHERS += f32_to_f128M.o -SF_OBJS_OTHERS += f32_roundToInt.o -SF_OBJS_OTHERS += f32_add.o -SF_OBJS_OTHERS += f32_sub.o -SF_OBJS_OTHERS += f32_mul.o -SF_OBJS_OTHERS += f32_mulAdd.o -SF_OBJS_OTHERS += f32_div.o -SF_OBJS_OTHERS += f32_rem.o -SF_OBJS_OTHERS += f32_sqrt.o -SF_OBJS_OTHERS += f32_eq.o -SF_OBJS_OTHERS += f32_le.o -SF_OBJS_OTHERS += f32_lt.o -SF_OBJS_OTHERS += f32_eq_signaling.o -SF_OBJS_OTHERS += f32_le_quiet.o -SF_OBJS_OTHERS += f32_lt_quiet.o -SF_OBJS_OTHERS += f32_isSignalingNaN.o -SF_OBJS_OTHERS += f64_to_ui32.o -SF_OBJS_OTHERS += f64_to_ui64.o -SF_OBJS_OTHERS += f64_to_i32.o -SF_OBJS_OTHERS += f64_to_i64.o -SF_OBJS_OTHERS += f64_to_ui32_r_minMag.o -SF_OBJS_OTHERS += f64_to_ui64_r_minMag.o -SF_OBJS_OTHERS += f64_to_i32_r_minMag.o -SF_OBJS_OTHERS += f64_to_i64_r_minMag.o -SF_OBJS_OTHERS += f64_to_f16.o -SF_OBJS_OTHERS += f64_to_f32.o -SF_OBJS_OTHERS += f64_to_extF80.o -SF_OBJS_OTHERS += f64_to_extF80M.o -SF_OBJS_OTHERS += f64_to_f128.o -SF_OBJS_OTHERS += f64_to_f128M.o -SF_OBJS_OTHERS += f64_roundToInt.o -SF_OBJS_OTHERS += f64_add.o -SF_OBJS_OTHERS += f64_sub.o -SF_OBJS_OTHERS += f64_mul.o -SF_OBJS_OTHERS += f64_mulAdd.o -SF_OBJS_OTHERS += f64_div.o -SF_OBJS_OTHERS += f64_rem.o -SF_OBJS_OTHERS += f64_sqrt.o -SF_OBJS_OTHERS += f64_eq.o -SF_OBJS_OTHERS += f64_le.o -SF_OBJS_OTHERS += f64_lt.o -SF_OBJS_OTHERS += f64_eq_signaling.o -SF_OBJS_OTHERS += f64_le_quiet.o -SF_OBJS_OTHERS += f64_lt_quiet.o -SF_OBJS_OTHERS += f64_isSignalingNaN.o -SF_OBJS_OTHERS += extF80_to_ui32.o -SF_OBJS_OTHERS += extF80_to_ui64.o -SF_OBJS_OTHERS += extF80_to_i32.o -SF_OBJS_OTHERS += extF80_to_i64.o -SF_OBJS_OTHERS += extF80_to_ui32_r_minMag.o -SF_OBJS_OTHERS += extF80_to_ui64_r_minMag.o -SF_OBJS_OTHERS += extF80_to_i32_r_minMag.o -SF_OBJS_OTHERS += extF80_to_i64_r_minMag.o -SF_OBJS_OTHERS += extF80_to_f16.o -SF_OBJS_OTHERS += extF80_to_f32.o -SF_OBJS_OTHERS += extF80_to_f64.o -SF_OBJS_OTHERS += extF80_to_f128.o -SF_OBJS_OTHERS += extF80_roundToInt.o -SF_OBJS_OTHERS += extF80_add.o -SF_OBJS_OTHERS += extF80_sub.o -SF_OBJS_OTHERS += extF80_mul.o -SF_OBJS_OTHERS += extF80_div.o -SF_OBJS_OTHERS += extF80_rem.o -SF_OBJS_OTHERS += extF80_sqrt.o -SF_OBJS_OTHERS += extF80_eq.o -SF_OBJS_OTHERS += extF80_le.o -SF_OBJS_OTHERS += extF80_lt.o -SF_OBJS_OTHERS += extF80_eq_signaling.o -SF_OBJS_OTHERS += extF80_le_quiet.o -SF_OBJS_OTHERS += extF80_lt_quiet.o -SF_OBJS_OTHERS += extF80_isSignalingNaN.o -SF_OBJS_OTHERS += extF80M_to_ui32.o -SF_OBJS_OTHERS += extF80M_to_ui64.o -SF_OBJS_OTHERS += extF80M_to_i32.o -SF_OBJS_OTHERS += extF80M_to_i64.o -SF_OBJS_OTHERS += extF80M_to_ui32_r_minMag.o -SF_OBJS_OTHERS += extF80M_to_ui64_r_minMag.o -SF_OBJS_OTHERS += extF80M_to_i32_r_minMag.o -SF_OBJS_OTHERS += extF80M_to_i64_r_minMag.o -SF_OBJS_OTHERS += extF80M_to_f16.o -SF_OBJS_OTHERS += extF80M_to_f32.o -SF_OBJS_OTHERS += extF80M_to_f64.o -SF_OBJS_OTHERS += extF80M_to_f128M.o -SF_OBJS_OTHERS += extF80M_roundToInt.o -SF_OBJS_OTHERS += extF80M_add.o -SF_OBJS_OTHERS += extF80M_sub.o -SF_OBJS_OTHERS += extF80M_mul.o -SF_OBJS_OTHERS += extF80M_div.o -SF_OBJS_OTHERS += extF80M_rem.o -SF_OBJS_OTHERS += extF80M_sqrt.o -SF_OBJS_OTHERS += extF80M_eq.o -SF_OBJS_OTHERS += extF80M_le.o -SF_OBJS_OTHERS += extF80M_lt.o -SF_OBJS_OTHERS += extF80M_eq_signaling.o -SF_OBJS_OTHERS += extF80M_le_quiet.o -SF_OBJS_OTHERS += extF80M_lt_quiet.o -SF_OBJS_OTHERS += f128_to_ui32.o -SF_OBJS_OTHERS += f128_to_ui64.o -SF_OBJS_OTHERS += f128_to_i32.o -SF_OBJS_OTHERS += f128_to_i64.o -SF_OBJS_OTHERS += f128_to_ui32_r_minMag.o -SF_OBJS_OTHERS += f128_to_ui64_r_minMag.o -SF_OBJS_OTHERS += f128_to_i32_r_minMag.o -SF_OBJS_OTHERS += f128_to_i64_r_minMag.o -SF_OBJS_OTHERS += f128_to_f16.o -SF_OBJS_OTHERS += f128_to_f32.o -SF_OBJS_OTHERS += f128_to_extF80.o -SF_OBJS_OTHERS += f128_to_f64.o -SF_OBJS_OTHERS += f128_roundToInt.o -SF_OBJS_OTHERS += f128_add.o -SF_OBJS_OTHERS += f128_sub.o -SF_OBJS_OTHERS += f128_mul.o -SF_OBJS_OTHERS += f128_mulAdd.o -SF_OBJS_OTHERS += f128_div.o -SF_OBJS_OTHERS += f128_rem.o -SF_OBJS_OTHERS += f128_sqrt.o -SF_OBJS_OTHERS += f128_eq.o -SF_OBJS_OTHERS += f128_le.o -SF_OBJS_OTHERS += f128_lt.o -SF_OBJS_OTHERS += f128_eq_signaling.o -SF_OBJS_OTHERS += f128_le_quiet.o -SF_OBJS_OTHERS += f128_lt_quiet.o -SF_OBJS_OTHERS += f128_isSignalingNaN.o -SF_OBJS_OTHERS += f128M_to_ui32.o -SF_OBJS_OTHERS += f128M_to_ui64.o -SF_OBJS_OTHERS += f128M_to_i32.o -SF_OBJS_OTHERS += f128M_to_i64.o -SF_OBJS_OTHERS += f128M_to_ui32_r_minMag.o -SF_OBJS_OTHERS += f128M_to_ui64_r_minMag.o -SF_OBJS_OTHERS += f128M_to_i32_r_minMag.o -SF_OBJS_OTHERS += f128M_to_i64_r_minMag.o -SF_OBJS_OTHERS += f128M_to_f16.o -SF_OBJS_OTHERS += f128M_to_f32.o -SF_OBJS_OTHERS += f128M_to_extF80M.o -SF_OBJS_OTHERS += f128M_to_f64.o -SF_OBJS_OTHERS += f128M_roundToInt.o -SF_OBJS_OTHERS += f128M_add.o -SF_OBJS_OTHERS += f128M_sub.o -SF_OBJS_OTHERS += f128M_mul.o -SF_OBJS_OTHERS += f128M_mulAdd.o -SF_OBJS_OTHERS += f128M_div.o -SF_OBJS_OTHERS += f128M_rem.o -SF_OBJS_OTHERS += f128M_sqrt.o -SF_OBJS_OTHERS += f128M_eq.o -SF_OBJS_OTHERS += f128M_le.o -SF_OBJS_OTHERS += f128M_lt.o -SF_OBJS_OTHERS += f128M_eq_signaling.o -SF_OBJS_OTHERS += f128M_le_quiet.o -SF_OBJS_OTHERS += f128M_lt_quiet.o - -SF_OBJS_ALL_NOSPEC := -SF_OBJS_ALL_NOSPEC += $(SF_OBJS_PRIMITIVES) -SF_OBJS_ALL_NOSPEC += $(SF_OBJS_OTHERS) - -SF_OBJS_ALL := -SF_OBJS_ALL += $(SF_OBJS_ALL_NOSPEC) -SF_OBJS_ALL += $(SF_OBJS_SPECIALIZE) - -# testfloat objects -TF_OBJS_GENCASES := -TF_OBJS_GENCASES += genCases_ui32.o -TF_OBJS_GENCASES += genCases_ui64.o -TF_OBJS_GENCASES += genCases_i32.o -TF_OBJS_GENCASES += genCases_i64.o -TF_OBJS_GENCASES += genCases_f16.o -TF_OBJS_GENCASES += genCases_f32.o -TF_OBJS_GENCASES += genCases_f64.o -TF_OBJS_GENCASES += genCases_extF80.o -TF_OBJS_GENCASES += genCases_f128.o - -TF_OBJS_WRITECASE := -TF_OBJS_WRITECASE += writeCase_a_ui32.o -TF_OBJS_WRITECASE += writeCase_a_ui64.o -TF_OBJS_WRITECASE += writeCase_a_f16.o -TF_OBJS_WRITECASE += writeCase_ab_f16.o -TF_OBJS_WRITECASE += writeCase_abc_f16.o -TF_OBJS_WRITECASE += writeCase_a_f32.o -TF_OBJS_WRITECASE += writeCase_ab_f32.o -TF_OBJS_WRITECASE += writeCase_abc_f32.o -TF_OBJS_WRITECASE += writeCase_a_f64.o -TF_OBJS_WRITECASE += writeCase_ab_f64.o -TF_OBJS_WRITECASE += writeCase_abc_f64.o -TF_OBJS_WRITECASE += writeCase_a_extF80M.o -TF_OBJS_WRITECASE += writeCase_ab_extF80M.o -TF_OBJS_WRITECASE += writeCase_a_f128M.o -TF_OBJS_WRITECASE += writeCase_ab_f128M.o -TF_OBJS_WRITECASE += writeCase_abc_f128M.o -TF_OBJS_WRITECASE += writeCase_z_bool.o -TF_OBJS_WRITECASE += writeCase_z_ui32.o -TF_OBJS_WRITECASE += writeCase_z_ui64.o -TF_OBJS_WRITECASE += writeCase_z_f16.o -TF_OBJS_WRITECASE += writeCase_z_f32.o -TF_OBJS_WRITECASE += writeCase_z_f64.o -TF_OBJS_WRITECASE += writeCase_z_extF80M.o -TF_OBJS_WRITECASE += writeCase_z_f128M.o - -TF_OBJS_TEST := -TF_OBJS_TEST += test_a_ui32_z_f16.o -TF_OBJS_TEST += test_a_ui32_z_f32.o -TF_OBJS_TEST += test_a_ui32_z_f64.o -TF_OBJS_TEST += test_a_ui32_z_extF80.o -TF_OBJS_TEST += test_a_ui32_z_f128.o -TF_OBJS_TEST += test_a_ui64_z_f16.o -TF_OBJS_TEST += test_a_ui64_z_f32.o -TF_OBJS_TEST += test_a_ui64_z_f64.o -TF_OBJS_TEST += test_a_ui64_z_extF80.o -TF_OBJS_TEST += test_a_ui64_z_f128.o -TF_OBJS_TEST += test_a_i32_z_f16.o -TF_OBJS_TEST += test_a_i32_z_f32.o -TF_OBJS_TEST += test_a_i32_z_f64.o -TF_OBJS_TEST += test_a_i32_z_extF80.o -TF_OBJS_TEST += test_a_i32_z_f128.o -TF_OBJS_TEST += test_a_i64_z_f16.o -TF_OBJS_TEST += test_a_i64_z_f32.o -TF_OBJS_TEST += test_a_i64_z_f64.o -TF_OBJS_TEST += test_a_i64_z_extF80.o -TF_OBJS_TEST += test_a_i64_z_f128.o -TF_OBJS_TEST += test_a_f16_z_ui32_rx.o -TF_OBJS_TEST += test_a_f16_z_ui64_rx.o -TF_OBJS_TEST += test_a_f16_z_i32_rx.o -TF_OBJS_TEST += test_a_f16_z_i64_rx.o -TF_OBJS_TEST += test_a_f16_z_ui32_x.o -TF_OBJS_TEST += test_a_f16_z_ui64_x.o -TF_OBJS_TEST += test_a_f16_z_i32_x.o -TF_OBJS_TEST += test_a_f16_z_i64_x.o -TF_OBJS_TEST += test_a_f16_z_f32.o -TF_OBJS_TEST += test_a_f16_z_f64.o -TF_OBJS_TEST += test_a_f16_z_extF80.o -TF_OBJS_TEST += test_a_f16_z_f128.o -TF_OBJS_TEST += test_az_f16.o -TF_OBJS_TEST += test_az_f16_rx.o -TF_OBJS_TEST += test_abz_f16.o -TF_OBJS_TEST += test_abcz_f16.o -TF_OBJS_TEST += test_ab_f16_z_bool.o -TF_OBJS_TEST += test_a_f32_z_ui32_rx.o -TF_OBJS_TEST += test_a_f32_z_ui64_rx.o -TF_OBJS_TEST += test_a_f32_z_i32_rx.o -TF_OBJS_TEST += test_a_f32_z_i64_rx.o -TF_OBJS_TEST += test_a_f32_z_ui32_x.o -TF_OBJS_TEST += test_a_f32_z_ui64_x.o -TF_OBJS_TEST += test_a_f32_z_i32_x.o -TF_OBJS_TEST += test_a_f32_z_i64_x.o -TF_OBJS_TEST += test_a_f32_z_f16.o -TF_OBJS_TEST += test_a_f32_z_f64.o -TF_OBJS_TEST += test_a_f32_z_extF80.o -TF_OBJS_TEST += test_a_f32_z_f128.o -TF_OBJS_TEST += test_az_f32.o -TF_OBJS_TEST += test_az_f32_rx.o -TF_OBJS_TEST += test_abz_f32.o -TF_OBJS_TEST += test_abcz_f32.o -TF_OBJS_TEST += test_ab_f32_z_bool.o -TF_OBJS_TEST += test_a_f64_z_ui32_rx.o -TF_OBJS_TEST += test_a_f64_z_ui64_rx.o -TF_OBJS_TEST += test_a_f64_z_i32_rx.o -TF_OBJS_TEST += test_a_f64_z_i64_rx.o -TF_OBJS_TEST += test_a_f64_z_ui32_x.o -TF_OBJS_TEST += test_a_f64_z_ui64_x.o -TF_OBJS_TEST += test_a_f64_z_i32_x.o -TF_OBJS_TEST += test_a_f64_z_i64_x.o -TF_OBJS_TEST += test_a_f64_z_f16.o -TF_OBJS_TEST += test_a_f64_z_f32.o -TF_OBJS_TEST += test_a_f64_z_extF80.o -TF_OBJS_TEST += test_a_f64_z_f128.o -TF_OBJS_TEST += test_az_f64.o -TF_OBJS_TEST += test_az_f64_rx.o -TF_OBJS_TEST += test_abz_f64.o -TF_OBJS_TEST += test_abcz_f64.o -TF_OBJS_TEST += test_ab_f64_z_bool.o -TF_OBJS_TEST += test_a_extF80_z_ui32_rx.o -TF_OBJS_TEST += test_a_extF80_z_ui64_rx.o -TF_OBJS_TEST += test_a_extF80_z_i32_rx.o -TF_OBJS_TEST += test_a_extF80_z_i64_rx.o -TF_OBJS_TEST += test_a_extF80_z_ui32_x.o -TF_OBJS_TEST += test_a_extF80_z_ui64_x.o -TF_OBJS_TEST += test_a_extF80_z_i32_x.o -TF_OBJS_TEST += test_a_extF80_z_i64_x.o -TF_OBJS_TEST += test_a_extF80_z_f16.o -TF_OBJS_TEST += test_a_extF80_z_f32.o -TF_OBJS_TEST += test_a_extF80_z_f64.o -TF_OBJS_TEST += test_a_extF80_z_f128.o -TF_OBJS_TEST += test_az_extF80.o -TF_OBJS_TEST += test_az_extF80_rx.o -TF_OBJS_TEST += test_abz_extF80.o -TF_OBJS_TEST += test_ab_extF80_z_bool.o -TF_OBJS_TEST += test_a_f128_z_ui32_rx.o -TF_OBJS_TEST += test_a_f128_z_ui64_rx.o -TF_OBJS_TEST += test_a_f128_z_i32_rx.o -TF_OBJS_TEST += test_a_f128_z_i64_rx.o -TF_OBJS_TEST += test_a_f128_z_ui32_x.o -TF_OBJS_TEST += test_a_f128_z_ui64_x.o -TF_OBJS_TEST += test_a_f128_z_i32_x.o -TF_OBJS_TEST += test_a_f128_z_i64_x.o -TF_OBJS_TEST += test_a_f128_z_f16.o -TF_OBJS_TEST += test_a_f128_z_f32.o -TF_OBJS_TEST += test_a_f128_z_f64.o -TF_OBJS_TEST += test_a_f128_z_extF80.o -TF_OBJS_TEST += test_az_f128.o -TF_OBJS_TEST += test_az_f128_rx.o -TF_OBJS_TEST += test_abz_f128.o -TF_OBJS_TEST += test_abcz_f128.o -TF_OBJS_TEST += test_ab_f128_z_bool.o - -TF_OBJS_LIB := -TF_OBJS_LIB += uint128_inline.o -TF_OBJS_LIB += uint128.o -TF_OBJS_LIB += fail.o -TF_OBJS_LIB += functions_common.o -TF_OBJS_LIB += functionInfos.o -TF_OBJS_LIB += standardFunctionInfos.o -TF_OBJS_LIB += random.o -TF_OBJS_LIB += genCases_common.o -TF_OBJS_LIB += $(TF_OBJS_GENCASES) -TF_OBJS_LIB += genCases_writeTestsTotal.o -TF_OBJS_LIB += verCases_inline.o -TF_OBJS_LIB += verCases_common.o -TF_OBJS_LIB += verCases_writeFunctionName.o -TF_OBJS_LIB += readHex.o -TF_OBJS_LIB += writeHex.o -TF_OBJS_LIB += $(TF_OBJS_WRITECASE) -TF_OBJS_LIB += testLoops_common.o -TF_OBJS_LIB += $(TF_OBJS_TEST) - -BINARIES := fp-test$(EXESUF) fp-bench$(EXESUF) - -# We require artefacts from the main build including config-host.h -# because platform.h includes it. Rather than re-invoking the main -# build we just error out if things aren't there. -$(LIBQEMUUTIL) $(BUILD_DIR)/config-host.h: - $(error $@ missing, re-run parent build) - -all: $(BUILD_DIR)/config-host.h $(BINARIES) - -# libtestfloat.a depends on libsoftfloat.a, so specify it first -FP_TEST_LIBS := libtestfloat.a libsoftfloat.a $(LIBQEMUUTIL) - -fp-test$(EXESUF): fp-test.o slowfloat.o $(QEMU_SOFTFLOAT_OBJ) $(FP_TEST_LIBS) - -# Custom rule to build with SF_CFLAGS -SF_BUILD = $(call quiet-command,$(CC) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ - $(QEMU_CFLAGS) $(SF_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) \ - $($@-cflags) -c -o $@ $<,"CC","$(TARGET_DIR)$@") - -$(SF_OBJS_ALL_NOSPEC): %.o: $(SF_SOURCE_DIR)/%.c - $(SF_BUILD) -$(SF_OBJS_SPECIALIZE): %.o: $(SF_SPECIALIZE_DIR)/%.c - $(SF_BUILD) - -libsoftfloat.a: $(SF_OBJS_ALL) - -# Custom rule to build with TF_CFLAGS -$(TF_OBJS_LIB) slowfloat.o: %.o: $(TF_SOURCE_DIR)/%.c - $(call quiet-command,$(CC) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ - $(QEMU_CFLAGS) $(TF_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) \ - $($@-cflags) -c -o $@ $<,"CC","$(TARGET_DIR)$@") - -libtestfloat.a: $(TF_OBJS_LIB) - -fp-bench$(EXESUF): fp-bench.o $(QEMU_SOFTFLOAT_OBJ) $(LIBQEMUUTIL) - -clean: - rm -f *.o *.d $(BINARIES) - rm -f *.gcno *.gcda *.gcov - rm -f fp-test$(EXESUF) - rm -f fp-bench$(EXESUF) - rm -f libsoftfloat.a - rm -f libtestfloat.a - --include $(wildcard *.d) diff --git a/tests/fp/meson.build b/tests/fp/meson.build new file mode 100644 index 0000000000..8779a17aab --- /dev/null +++ b/tests/fp/meson.build @@ -0,0 +1,636 @@ +# There are namespace pollution issues on Windows, due to osdep.h +# bringing in Windows headers that define a FLOAT128 type. +if targetos == 'windows' + subdir_done() +endif + +fpcflags = [ + # softfloat defines + '-DSOFTFLOAT_ROUND_ODD', + '-DINLINE_LEVEL=5', + '-DSOFTFLOAT_FAST_DIV32TO16', + '-DSOFTFLOAT_FAST_DIV64TO32', + '-DSOFTFLOAT_FAST_INT64', + # testfloat defines + '-DFLOAT16', + '-DFLOAT64', + '-DEXTFLOAT80', + '-DFLOAT128', + '-DFLOAT_ROUND_ODD', + '-DLONG_DOUBLE_IS_EXTFLOAT80', +] + +sfdir = 'berkeley-softfloat-3/source' +sfspedir = sfdir / '8086-SSE' +tfdir = 'berkeley-testfloat-3/source' + +sfinc = include_directories(sfdir / 'include', sfspedir) + +tfcflags = [ + '-Wno-strict-prototypes', + '-Wno-unknown-pragmas', + '-Wno-uninitialized', + '-Wno-missing-prototypes', + '-Wno-return-type', + '-Wno-unused-function', + '-Wno-error', +] + +tfgencases = [ + tfdir / 'genCases_ui32.c', + tfdir / 'genCases_ui64.c', + tfdir / 'genCases_i32.c', + tfdir / 'genCases_i64.c', + tfdir / 'genCases_f16.c', + tfdir / 'genCases_f32.c', + tfdir / 'genCases_f64.c', + tfdir / 'genCases_extF80.c', + tfdir / 'genCases_f128.c', +] + +tfwritecase = [ + tfdir / 'writeCase_a_ui32.c', + tfdir / 'writeCase_a_ui64.c', + tfdir / 'writeCase_a_f16.c', + tfdir / 'writeCase_ab_f16.c', + tfdir / 'writeCase_abc_f16.c', + tfdir / 'writeCase_a_f32.c', + tfdir / 'writeCase_ab_f32.c', + tfdir / 'writeCase_abc_f32.c', + tfdir / 'writeCase_a_f64.c', + tfdir / 'writeCase_ab_f64.c', + tfdir / 'writeCase_abc_f64.c', + tfdir / 'writeCase_a_extF80M.c', + tfdir / 'writeCase_ab_extF80M.c', + tfdir / 'writeCase_a_f128M.c', + tfdir / 'writeCase_ab_f128M.c', + tfdir / 'writeCase_abc_f128M.c', + tfdir / 'writeCase_z_bool.c', + tfdir / 'writeCase_z_ui32.c', + tfdir / 'writeCase_z_ui64.c', + tfdir / 'writeCase_z_f16.c', + tfdir / 'writeCase_z_f32.c', + tfdir / 'writeCase_z_f64.c', + tfdir / 'writeCase_z_extF80M.c', + tfdir / 'writeCase_z_f128M.c', +] + +tftest = [ + tfdir / 'test_a_ui32_z_f16.c', + tfdir / 'test_a_ui32_z_f32.c', + tfdir / 'test_a_ui32_z_f64.c', + tfdir / 'test_a_ui32_z_extF80.c', + tfdir / 'test_a_ui32_z_f128.c', + tfdir / 'test_a_ui64_z_f16.c', + tfdir / 'test_a_ui64_z_f32.c', + tfdir / 'test_a_ui64_z_f64.c', + tfdir / 'test_a_ui64_z_extF80.c', + tfdir / 'test_a_ui64_z_f128.c', + tfdir / 'test_a_i32_z_f16.c', + tfdir / 'test_a_i32_z_f32.c', + tfdir / 'test_a_i32_z_f64.c', + tfdir / 'test_a_i32_z_extF80.c', + tfdir / 'test_a_i32_z_f128.c', + tfdir / 'test_a_i64_z_f16.c', + tfdir / 'test_a_i64_z_f32.c', + tfdir / 'test_a_i64_z_f64.c', + tfdir / 'test_a_i64_z_extF80.c', + tfdir / 'test_a_i64_z_f128.c', + tfdir / 'test_a_f16_z_ui32_rx.c', + tfdir / 'test_a_f16_z_ui64_rx.c', + tfdir / 'test_a_f16_z_i32_rx.c', + tfdir / 'test_a_f16_z_i64_rx.c', + tfdir / 'test_a_f16_z_ui32_x.c', + tfdir / 'test_a_f16_z_ui64_x.c', + tfdir / 'test_a_f16_z_i32_x.c', + tfdir / 'test_a_f16_z_i64_x.c', + tfdir / 'test_a_f16_z_f32.c', + tfdir / 'test_a_f16_z_f64.c', + tfdir / 'test_a_f16_z_extF80.c', + tfdir / 'test_a_f16_z_f128.c', + tfdir / 'test_az_f16.c', + tfdir / 'test_az_f16_rx.c', + tfdir / 'test_abz_f16.c', + tfdir / 'test_abcz_f16.c', + tfdir / 'test_ab_f16_z_bool.c', + tfdir / 'test_a_f32_z_ui32_rx.c', + tfdir / 'test_a_f32_z_ui64_rx.c', + tfdir / 'test_a_f32_z_i32_rx.c', + tfdir / 'test_a_f32_z_i64_rx.c', + tfdir / 'test_a_f32_z_ui32_x.c', + tfdir / 'test_a_f32_z_ui64_x.c', + tfdir / 'test_a_f32_z_i32_x.c', + tfdir / 'test_a_f32_z_i64_x.c', + tfdir / 'test_a_f32_z_f16.c', + tfdir / 'test_a_f32_z_f64.c', + tfdir / 'test_a_f32_z_extF80.c', + tfdir / 'test_a_f32_z_f128.c', + tfdir / 'test_az_f32.c', + tfdir / 'test_az_f32_rx.c', + tfdir / 'test_abz_f32.c', + tfdir / 'test_abcz_f32.c', + tfdir / 'test_ab_f32_z_bool.c', + tfdir / 'test_a_f64_z_ui32_rx.c', + tfdir / 'test_a_f64_z_ui64_rx.c', + tfdir / 'test_a_f64_z_i32_rx.c', + tfdir / 'test_a_f64_z_i64_rx.c', + tfdir / 'test_a_f64_z_ui32_x.c', + tfdir / 'test_a_f64_z_ui64_x.c', + tfdir / 'test_a_f64_z_i32_x.c', + tfdir / 'test_a_f64_z_i64_x.c', + tfdir / 'test_a_f64_z_f16.c', + tfdir / 'test_a_f64_z_f32.c', + tfdir / 'test_a_f64_z_extF80.c', + tfdir / 'test_a_f64_z_f128.c', + tfdir / 'test_az_f64.c', + tfdir / 'test_az_f64_rx.c', + tfdir / 'test_abz_f64.c', + tfdir / 'test_abcz_f64.c', + tfdir / 'test_ab_f64_z_bool.c', + tfdir / 'test_a_extF80_z_ui32_rx.c', + tfdir / 'test_a_extF80_z_ui64_rx.c', + tfdir / 'test_a_extF80_z_i32_rx.c', + tfdir / 'test_a_extF80_z_i64_rx.c', + tfdir / 'test_a_extF80_z_ui32_x.c', + tfdir / 'test_a_extF80_z_ui64_x.c', + tfdir / 'test_a_extF80_z_i32_x.c', + tfdir / 'test_a_extF80_z_i64_x.c', + tfdir / 'test_a_extF80_z_f16.c', + tfdir / 'test_a_extF80_z_f32.c', + tfdir / 'test_a_extF80_z_f64.c', + tfdir / 'test_a_extF80_z_f128.c', + tfdir / 'test_az_extF80.c', + tfdir / 'test_az_extF80_rx.c', + tfdir / 'test_abz_extF80.c', + tfdir / 'test_ab_extF80_z_bool.c', + tfdir / 'test_a_f128_z_ui32_rx.c', + tfdir / 'test_a_f128_z_ui64_rx.c', + tfdir / 'test_a_f128_z_i32_rx.c', + tfdir / 'test_a_f128_z_i64_rx.c', + tfdir / 'test_a_f128_z_ui32_x.c', + tfdir / 'test_a_f128_z_ui64_x.c', + tfdir / 'test_a_f128_z_i32_x.c', + tfdir / 'test_a_f128_z_i64_x.c', + tfdir / 'test_a_f128_z_f16.c', + tfdir / 'test_a_f128_z_f32.c', + tfdir / 'test_a_f128_z_f64.c', + tfdir / 'test_a_f128_z_extF80.c', + tfdir / 'test_az_f128.c', + tfdir / 'test_az_f128_rx.c', + tfdir / 'test_abz_f128.c', + tfdir / 'test_abcz_f128.c', + tfdir / 'test_ab_f128_z_bool.c', +] + +libtestfloat = static_library( + 'testfloat', + files( + tfdir / 'uint128_inline.c', + tfdir / 'uint128.c', + tfdir / 'fail.c', + tfdir / 'functions_common.c', + tfdir / 'functionInfos.c', + tfdir / 'standardFunctionInfos.c', + tfdir / 'random.c', + tfdir / 'genCases_common.c', + tfgencases, + tfdir / 'genCases_writeTestsTotal.c', + tfdir / 'verCases_inline.c', + tfdir / 'verCases_common.c', + tfdir / 'verCases_writeFunctionName.c', + tfdir / 'readHex.c', + tfdir / 'writeHex.c', + tfwritecase, + tfdir / 'testLoops_common.c', + tftest, + ), + include_directories: sfinc, + c_args: tfcflags + fpcflags, +) + +sfcflags = [ + '-Wno-missing-prototypes', + '-Wno-redundant-decls', + '-Wno-return-type', + '-Wno-error', +] + +libsoftfloat = static_library( + 'softfloat', + files( + # primitives + sfdir / 's_eq128.c', + sfdir / 's_le128.c', + sfdir / 's_lt128.c', + sfdir / 's_shortShiftLeft128.c', + sfdir / 's_shortShiftRight128.c', + sfdir / 's_shortShiftRightJam64.c', + sfdir / 's_shortShiftRightJam64Extra.c', + sfdir / 's_shortShiftRightJam128.c', + sfdir / 's_shortShiftRightJam128Extra.c', + sfdir / 's_shiftRightJam32.c', + sfdir / 's_shiftRightJam64.c', + sfdir / 's_shiftRightJam64Extra.c', + sfdir / 's_shiftRightJam128.c', + sfdir / 's_shiftRightJam128Extra.c', + sfdir / 's_shiftRightJam256M.c', + sfdir / 's_countLeadingZeros8.c', + sfdir / 's_countLeadingZeros16.c', + sfdir / 's_countLeadingZeros32.c', + sfdir / 's_countLeadingZeros64.c', + sfdir / 's_add128.c', + sfdir / 's_add256M.c', + sfdir / 's_sub128.c', + sfdir / 's_sub256M.c', + sfdir / 's_mul64ByShifted32To128.c', + sfdir / 's_mul64To128.c', + sfdir / 's_mul128By32.c', + sfdir / 's_mul128To256M.c', + sfdir / 's_approxRecip_1Ks.c', + sfdir / 's_approxRecip32_1.c', + sfdir / 's_approxRecipSqrt_1Ks.c', + sfdir / 's_approxRecipSqrt32_1.c', + # others + sfdir / 's_roundToUI32.c', + sfdir / 's_roundToUI64.c', + sfdir / 's_roundToI32.c', + sfdir / 's_roundToI64.c', + sfdir / 's_normSubnormalF16Sig.c', + sfdir / 's_roundPackToF16.c', + sfdir / 's_normRoundPackToF16.c', + sfdir / 's_addMagsF16.c', + sfdir / 's_subMagsF16.c', + sfdir / 's_mulAddF16.c', + sfdir / 's_normSubnormalF32Sig.c', + sfdir / 's_roundPackToF32.c', + sfdir / 's_normRoundPackToF32.c', + sfdir / 's_addMagsF32.c', + sfdir / 's_subMagsF32.c', + sfdir / 's_mulAddF32.c', + sfdir / 's_normSubnormalF64Sig.c', + sfdir / 's_roundPackToF64.c', + sfdir / 's_normRoundPackToF64.c', + sfdir / 's_addMagsF64.c', + sfdir / 's_subMagsF64.c', + sfdir / 's_mulAddF64.c', + sfdir / 's_normSubnormalExtF80Sig.c', + sfdir / 's_roundPackToExtF80.c', + sfdir / 's_normRoundPackToExtF80.c', + sfdir / 's_addMagsExtF80.c', + sfdir / 's_subMagsExtF80.c', + sfdir / 's_normSubnormalF128Sig.c', + sfdir / 's_roundPackToF128.c', + sfdir / 's_normRoundPackToF128.c', + sfdir / 's_addMagsF128.c', + sfdir / 's_subMagsF128.c', + sfdir / 's_mulAddF128.c', + sfdir / 'softfloat_state.c', + sfdir / 'ui32_to_f16.c', + sfdir / 'ui32_to_f32.c', + sfdir / 'ui32_to_f64.c', + sfdir / 'ui32_to_extF80.c', + sfdir / 'ui32_to_extF80M.c', + sfdir / 'ui32_to_f128.c', + sfdir / 'ui32_to_f128M.c', + sfdir / 'ui64_to_f16.c', + sfdir / 'ui64_to_f32.c', + sfdir / 'ui64_to_f64.c', + sfdir / 'ui64_to_extF80.c', + sfdir / 'ui64_to_extF80M.c', + sfdir / 'ui64_to_f128.c', + sfdir / 'ui64_to_f128M.c', + sfdir / 'i32_to_f16.c', + sfdir / 'i32_to_f32.c', + sfdir / 'i32_to_f64.c', + sfdir / 'i32_to_extF80.c', + sfdir / 'i32_to_extF80M.c', + sfdir / 'i32_to_f128.c', + sfdir / 'i32_to_f128M.c', + sfdir / 'i64_to_f16.c', + sfdir / 'i64_to_f32.c', + sfdir / 'i64_to_f64.c', + sfdir / 'i64_to_extF80.c', + sfdir / 'i64_to_extF80M.c', + sfdir / 'i64_to_f128.c', + sfdir / 'i64_to_f128M.c', + sfdir / 'f16_to_ui32.c', + sfdir / 'f16_to_ui64.c', + sfdir / 'f16_to_i32.c', + sfdir / 'f16_to_i64.c', + sfdir / 'f16_to_ui32_r_minMag.c', + sfdir / 'f16_to_ui64_r_minMag.c', + sfdir / 'f16_to_i32_r_minMag.c', + sfdir / 'f16_to_i64_r_minMag.c', + sfdir / 'f16_to_f32.c', + sfdir / 'f16_to_f64.c', + sfdir / 'f16_to_extF80.c', + sfdir / 'f16_to_extF80M.c', + sfdir / 'f16_to_f128.c', + sfdir / 'f16_to_f128M.c', + sfdir / 'f16_roundToInt.c', + sfdir / 'f16_add.c', + sfdir / 'f16_sub.c', + sfdir / 'f16_mul.c', + sfdir / 'f16_mulAdd.c', + sfdir / 'f16_div.c', + sfdir / 'f16_rem.c', + sfdir / 'f16_sqrt.c', + sfdir / 'f16_eq.c', + sfdir / 'f16_le.c', + sfdir / 'f16_lt.c', + sfdir / 'f16_eq_signaling.c', + sfdir / 'f16_le_quiet.c', + sfdir / 'f16_lt_quiet.c', + sfdir / 'f16_isSignalingNaN.c', + sfdir / 'f32_to_ui32.c', + sfdir / 'f32_to_ui64.c', + sfdir / 'f32_to_i32.c', + sfdir / 'f32_to_i64.c', + sfdir / 'f32_to_ui32_r_minMag.c', + sfdir / 'f32_to_ui64_r_minMag.c', + sfdir / 'f32_to_i32_r_minMag.c', + sfdir / 'f32_to_i64_r_minMag.c', + sfdir / 'f32_to_f16.c', + sfdir / 'f32_to_f64.c', + sfdir / 'f32_to_extF80.c', + sfdir / 'f32_to_extF80M.c', + sfdir / 'f32_to_f128.c', + sfdir / 'f32_to_f128M.c', + sfdir / 'f32_roundToInt.c', + sfdir / 'f32_add.c', + sfdir / 'f32_sub.c', + sfdir / 'f32_mul.c', + sfdir / 'f32_mulAdd.c', + sfdir / 'f32_div.c', + sfdir / 'f32_rem.c', + sfdir / 'f32_sqrt.c', + sfdir / 'f32_eq.c', + sfdir / 'f32_le.c', + sfdir / 'f32_lt.c', + sfdir / 'f32_eq_signaling.c', + sfdir / 'f32_le_quiet.c', + sfdir / 'f32_lt_quiet.c', + sfdir / 'f32_isSignalingNaN.c', + sfdir / 'f64_to_ui32.c', + sfdir / 'f64_to_ui64.c', + sfdir / 'f64_to_i32.c', + sfdir / 'f64_to_i64.c', + sfdir / 'f64_to_ui32_r_minMag.c', + sfdir / 'f64_to_ui64_r_minMag.c', + sfdir / 'f64_to_i32_r_minMag.c', + sfdir / 'f64_to_i64_r_minMag.c', + sfdir / 'f64_to_f16.c', + sfdir / 'f64_to_f32.c', + sfdir / 'f64_to_extF80.c', + sfdir / 'f64_to_extF80M.c', + sfdir / 'f64_to_f128.c', + sfdir / 'f64_to_f128M.c', + sfdir / 'f64_roundToInt.c', + sfdir / 'f64_add.c', + sfdir / 'f64_sub.c', + sfdir / 'f64_mul.c', + sfdir / 'f64_mulAdd.c', + sfdir / 'f64_div.c', + sfdir / 'f64_rem.c', + sfdir / 'f64_sqrt.c', + sfdir / 'f64_eq.c', + sfdir / 'f64_le.c', + sfdir / 'f64_lt.c', + sfdir / 'f64_eq_signaling.c', + sfdir / 'f64_le_quiet.c', + sfdir / 'f64_lt_quiet.c', + sfdir / 'f64_isSignalingNaN.c', + sfdir / 'extF80_to_ui32.c', + sfdir / 'extF80_to_ui64.c', + sfdir / 'extF80_to_i32.c', + sfdir / 'extF80_to_i64.c', + sfdir / 'extF80_to_ui32_r_minMag.c', + sfdir / 'extF80_to_ui64_r_minMag.c', + sfdir / 'extF80_to_i32_r_minMag.c', + sfdir / 'extF80_to_i64_r_minMag.c', + sfdir / 'extF80_to_f16.c', + sfdir / 'extF80_to_f32.c', + sfdir / 'extF80_to_f64.c', + sfdir / 'extF80_to_f128.c', + sfdir / 'extF80_roundToInt.c', + sfdir / 'extF80_add.c', + sfdir / 'extF80_sub.c', + sfdir / 'extF80_mul.c', + sfdir / 'extF80_div.c', + sfdir / 'extF80_rem.c', + sfdir / 'extF80_sqrt.c', + sfdir / 'extF80_eq.c', + sfdir / 'extF80_le.c', + sfdir / 'extF80_lt.c', + sfdir / 'extF80_eq_signaling.c', + sfdir / 'extF80_le_quiet.c', + sfdir / 'extF80_lt_quiet.c', + sfdir / 'extF80_isSignalingNaN.c', + sfdir / 'extF80M_to_ui32.c', + sfdir / 'extF80M_to_ui64.c', + sfdir / 'extF80M_to_i32.c', + sfdir / 'extF80M_to_i64.c', + sfdir / 'extF80M_to_ui32_r_minMag.c', + sfdir / 'extF80M_to_ui64_r_minMag.c', + sfdir / 'extF80M_to_i32_r_minMag.c', + sfdir / 'extF80M_to_i64_r_minMag.c', + sfdir / 'extF80M_to_f16.c', + sfdir / 'extF80M_to_f32.c', + sfdir / 'extF80M_to_f64.c', + sfdir / 'extF80M_to_f128M.c', + sfdir / 'extF80M_roundToInt.c', + sfdir / 'extF80M_add.c', + sfdir / 'extF80M_sub.c', + sfdir / 'extF80M_mul.c', + sfdir / 'extF80M_div.c', + sfdir / 'extF80M_rem.c', + sfdir / 'extF80M_sqrt.c', + sfdir / 'extF80M_eq.c', + sfdir / 'extF80M_le.c', + sfdir / 'extF80M_lt.c', + sfdir / 'extF80M_eq_signaling.c', + sfdir / 'extF80M_le_quiet.c', + sfdir / 'extF80M_lt_quiet.c', + sfdir / 'f128_to_ui32.c', + sfdir / 'f128_to_ui64.c', + sfdir / 'f128_to_i32.c', + sfdir / 'f128_to_i64.c', + sfdir / 'f128_to_ui32_r_minMag.c', + sfdir / 'f128_to_ui64_r_minMag.c', + sfdir / 'f128_to_i32_r_minMag.c', + sfdir / 'f128_to_i64_r_minMag.c', + sfdir / 'f128_to_f16.c', + sfdir / 'f128_to_f32.c', + sfdir / 'f128_to_extF80.c', + sfdir / 'f128_to_f64.c', + sfdir / 'f128_roundToInt.c', + sfdir / 'f128_add.c', + sfdir / 'f128_sub.c', + sfdir / 'f128_mul.c', + sfdir / 'f128_mulAdd.c', + sfdir / 'f128_div.c', + sfdir / 'f128_rem.c', + sfdir / 'f128_sqrt.c', + sfdir / 'f128_eq.c', + sfdir / 'f128_le.c', + sfdir / 'f128_lt.c', + sfdir / 'f128_eq_signaling.c', + sfdir / 'f128_le_quiet.c', + sfdir / 'f128_lt_quiet.c', + sfdir / 'f128_isSignalingNaN.c', + sfdir / 'f128M_to_ui32.c', + sfdir / 'f128M_to_ui64.c', + sfdir / 'f128M_to_i32.c', + sfdir / 'f128M_to_i64.c', + sfdir / 'f128M_to_ui32_r_minMag.c', + sfdir / 'f128M_to_ui64_r_minMag.c', + sfdir / 'f128M_to_i32_r_minMag.c', + sfdir / 'f128M_to_i64_r_minMag.c', + sfdir / 'f128M_to_f16.c', + sfdir / 'f128M_to_f32.c', + sfdir / 'f128M_to_extF80M.c', + sfdir / 'f128M_to_f64.c', + sfdir / 'f128M_roundToInt.c', + sfdir / 'f128M_add.c', + sfdir / 'f128M_sub.c', + sfdir / 'f128M_mul.c', + sfdir / 'f128M_mulAdd.c', + sfdir / 'f128M_div.c', + sfdir / 'f128M_rem.c', + sfdir / 'f128M_sqrt.c', + sfdir / 'f128M_eq.c', + sfdir / 'f128M_le.c', + sfdir / 'f128M_lt.c', + sfdir / 'f128M_eq_signaling.c', + sfdir / 'f128M_le_quiet.c', + sfdir / 'f128M_lt_quiet.c', + # spe + sfspedir / 'softfloat_raiseFlags.c', + sfspedir / 's_f16UIToCommonNaN.c', + sfspedir / 's_commonNaNToF16UI.c', + sfspedir / 's_propagateNaNF16UI.c', + sfspedir / 's_f32UIToCommonNaN.c', + sfspedir / 's_commonNaNToF32UI.c', + sfspedir / 's_propagateNaNF32UI.c', + sfspedir / 's_f64UIToCommonNaN.c', + sfspedir / 's_commonNaNToF64UI.c', + sfspedir / 's_propagateNaNF64UI.c', + sfspedir / 'extF80M_isSignalingNaN.c', + sfspedir / 's_extF80UIToCommonNaN.c', + sfspedir / 's_commonNaNToExtF80UI.c', + sfspedir / 's_propagateNaNExtF80UI.c', + sfspedir / 'f128M_isSignalingNaN.c', + sfspedir / 's_f128UIToCommonNaN.c', + sfspedir / 's_commonNaNToF128UI.c', + sfspedir / 's_propagateNaNF128UI.c', + ), + include_directories: sfinc, + c_args: sfcflags + fpcflags, +) + +fpcflags += [ + # work around TARGET_* poisoning + '-DHW_POISON_H', + # define a target to match testfloat's implementation-defined choices, such as + # whether to raise the invalid flag when dealing with NaNs in muladd. + '-DTARGET_ARM', + # FIXME: uiZ may be used uninitialized in this function + '-Wno-uninitialized', +] + +fptest = executable( + 'fp-test', + ['fp-test.c', tfdir / 'slowfloat.c', '../../fpu/softfloat.c'], + build_by_default: false, + link_with: [libtestfloat, libsoftfloat], + dependencies: [qemuutil], + include_directories: [sfinc, include_directories(tfdir)], + c_args: fpcflags, +) +softfloat_conv_tests = { + 'float-to-float': 'f16_to_f32 f16_to_f64 f16_to_extF80 f16_to_f128 ' + + 'f32_to_f16 f32_to_f64 f32_to_extF80 ' + + 'f64_to_f16 f64_to_f32 ' + + 'extF80_to_f16 extF80_to_f32 ' + + 'extF80_to_f64 extF80_to_f128 ' + + 'f128_to_f16', + 'int-to-float': 'i32_to_f16 i64_to_f16 i32_to_f32 i64_to_f32 ' + + 'i32_to_f64 i64_to_f64 i32_to_f128 i64_to_f128', + 'uint-to-float': 'ui32_to_f16 ui64_to_f16 ui32_to_f32 ui64_to_f32 ' + + 'ui32_to_f64 ui64_to_f64 ui64_to_f128 ' + + 'ui32_to_extF80 ui64_to_extF80', + 'float-to-int': 'f16_to_i32 f16_to_i32_r_minMag ' + + 'f32_to_i32 f32_to_i32_r_minMag ' + + 'f64_to_i32 f64_to_i32_r_minMag ' + + 'extF80_to_i32 extF80_to_i32_r_minMag ' + + 'f128_to_i32 f128_to_i32_r_minMag ' + + 'f16_to_i64 f16_to_i64_r_minMag ' + + 'f32_to_i64 f32_to_i64_r_minMag ' + + 'f64_to_i64 f64_to_i64_r_minMag ' + + 'extF80_to_i64 extF80_to_i64_r_minMag ' + + 'f128_to_i64 f128_to_i64_r_minMag', + 'float-to-uint': 'f16_to_ui32 f16_to_ui32_r_minMag ' + + 'f32_to_ui32 f32_to_ui32_r_minMag ' + + 'f64_to_ui32 f64_to_ui32_r_minMag ' + + 'extF80_to_ui32 extF80_to_ui32_r_minMag ' + + 'f128_to_ui32 f128_to_ui32_r_minMag ' + + 'f16_to_ui64 f16_to_ui64_r_minMag ' + + 'f32_to_ui64 f32_to_ui64_r_minMag ' + + 'f64_to_ui64 f64_to_ui64_r_minMag ' + + 'extF80_to_ui64 extF80_to_ui64_r_minMag ' + + 'f128_to_ui64 f128_to_ui64_r_minMag', + 'round-to-integer': 'f16_roundToInt f32_roundToInt ' + + 'f64_roundToInt f128_roundToInt' +} +softfloat_tests = { + 'eq_signaling' : 'compare', + 'le' : 'compare', + 'le_quiet' : 'compare', + 'lt_quiet' : 'compare', + 'add': 'ops', + 'sub': 'ops', + 'mul': 'ops', + 'div': 'ops', + 'rem': 'ops', + 'sqrt': 'ops' +} +# The full test suite can take a bit of time, default to a quick run +# "-l 2 -r all" can take more than a day for some operations and is best +# run manually +fptest_args = ['-s', '-l', '1'] +fptest_rounding_args = ['-r', 'all'] + +# Conversion Routines: +# FIXME: i32_to_extF80 (broken), i64_to_extF80 (broken) +# extF80_roundToInt (broken) +foreach k, v : softfloat_conv_tests + test('fp-test:' + k, fptest, + args: fptest_args + fptest_rounding_args + v.split(), + suite: ['softfloat', 'softfloat-conv']) +endforeach + +# FIXME: extF80_{lt_quiet, rem} (broken), +# extF80_{mulAdd} (missing) +foreach k, v : softfloat_tests + extF80_broken = ['lt_quiet', 'rem'].contains(k) + test('fp-test:' + k, fptest, + args: fptest_args + fptest_rounding_args + + ['f16_' + k, 'f32_' + k, 'f64_' + k, 'f128_' + k] + + (extF80_broken ? [] : ['extF80_' + k]), + suite: ['softfloat', 'softfloat-' + v]) +endforeach +test('fp-test:mulAdd', fptest, + # no fptest_rounding_args + args: fptest_args + + ['f16_mulAdd', 'f32_mulAdd', 'f64_mulAdd', 'f128_mulAdd'], + suite: ['softfloat-slow', 'softfloat-ops-slow'], timeout: 60) + +fpbench = executable( + 'fp-bench', + ['fp-bench.c', '../../fpu/softfloat.c'], + build_by_default: false, + link_with: [libtestfloat, libsoftfloat], + dependencies: [qemuutil], + include_directories: [sfinc, include_directories(tfdir)], + c_args: fpcflags, +) diff --git a/tests/meson.build b/tests/meson.build index 5c52021dc9..ec26f92937 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -2,3 +2,7 @@ test('decodetree', sh, args: [ files('decode/check.sh'), config_host['PYTHON'], files('../scripts/decodetree.py') ], workdir: meson.current_source_dir() / 'decode', suite: 'decodetree') + +if 'CONFIG_TCG' in config_host + subdir('fp') +endif -- cgit v1.2.3-55-g7522 From 3afe7ab0d3f40270cb4dac58a8895ba21a646df6 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 28 Jan 2020 18:05:14 +0100 Subject: meson: convert check-qapi-schema Signed-off-by: Paolo Bonzini --- tests/Makefile.include | 218 +--------------------------------------- tests/meson.build | 2 + tests/qapi-schema/meson.build | 225 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 229 insertions(+), 216 deletions(-) create mode 100644 tests/qapi-schema/meson.build diff --git a/tests/Makefile.include b/tests/Makefile.include index 8fb6baa0a1..02d31fbe0c 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -161,201 +161,6 @@ check-unit-y += tests/test-qapi-util$(EXESUF) check-block-$(call land,$(CONFIG_POSIX),$(CONFIG_SOFTMMU)) += tests/check-block.sh -qapi-schema += alternate-any.json -qapi-schema += alternate-array.json -qapi-schema += alternate-base.json -qapi-schema += alternate-branch-if-invalid.json -qapi-schema += alternate-clash.json -qapi-schema += alternate-conflict-dict.json -qapi-schema += alternate-conflict-enum-bool.json -qapi-schema += alternate-conflict-enum-int.json -qapi-schema += alternate-conflict-string.json -qapi-schema += alternate-conflict-bool-string.json -qapi-schema += alternate-conflict-num-string.json -qapi-schema += alternate-empty.json -qapi-schema += alternate-invalid-dict.json -qapi-schema += alternate-nested.json -qapi-schema += alternate-unknown.json -qapi-schema += args-alternate.json -qapi-schema += args-any.json -qapi-schema += args-array-empty.json -qapi-schema += args-array-unknown.json -qapi-schema += args-bad-boxed.json -qapi-schema += args-boxed-anon.json -qapi-schema += args-boxed-string.json -qapi-schema += args-int.json -qapi-schema += args-invalid.json -qapi-schema += args-member-array-bad.json -qapi-schema += args-member-case.json -qapi-schema += args-member-unknown.json -qapi-schema += args-name-clash.json -qapi-schema += args-union.json -qapi-schema += args-unknown.json -qapi-schema += bad-base.json -qapi-schema += bad-data.json -qapi-schema += bad-ident.json -qapi-schema += bad-if.json -qapi-schema += bad-if-empty.json -qapi-schema += bad-if-empty-list.json -qapi-schema += bad-if-list.json -qapi-schema += bad-type-bool.json -qapi-schema += bad-type-dict.json -qapi-schema += bad-type-int.json -qapi-schema += base-cycle-direct.json -qapi-schema += base-cycle-indirect.json -qapi-schema += command-int.json -qapi-schema += comments.json -qapi-schema += doc-bad-alternate-member.json -qapi-schema += doc-bad-boxed-command-arg.json -qapi-schema += doc-bad-command-arg.json -qapi-schema += doc-bad-enum-member.json -qapi-schema += doc-bad-event-arg.json -qapi-schema += doc-bad-feature.json -qapi-schema += doc-bad-section.json -qapi-schema += doc-bad-symbol.json -qapi-schema += doc-bad-union-member.json -qapi-schema += doc-before-include.json -qapi-schema += doc-before-pragma.json -qapi-schema += doc-duplicated-arg.json -qapi-schema += doc-duplicated-return.json -qapi-schema += doc-duplicated-since.json -qapi-schema += doc-empty-arg.json -qapi-schema += doc-empty-section.json -qapi-schema += doc-empty-symbol.json -qapi-schema += doc-good.json -qapi-schema += doc-interleaved-section.json -qapi-schema += doc-invalid-end.json -qapi-schema += doc-invalid-end2.json -qapi-schema += doc-invalid-return.json -qapi-schema += doc-invalid-section.json -qapi-schema += doc-invalid-start.json -qapi-schema += doc-missing-colon.json -qapi-schema += doc-missing-expr.json -qapi-schema += doc-missing-space.json -qapi-schema += doc-missing.json -qapi-schema += doc-no-symbol.json -qapi-schema += doc-undoc-feature.json -qapi-schema += double-type.json -qapi-schema += duplicate-key.json -qapi-schema += empty.json -qapi-schema += enum-bad-member.json -qapi-schema += enum-bad-name.json -qapi-schema += enum-bad-prefix.json -qapi-schema += enum-clash-member.json -qapi-schema += enum-dict-member-unknown.json -qapi-schema += enum-if-invalid.json -qapi-schema += enum-int-member.json -qapi-schema += enum-member-case.json -qapi-schema += enum-missing-data.json -qapi-schema += enum-wrong-data.json -qapi-schema += event-boxed-empty.json -qapi-schema += event-case.json -qapi-schema += event-member-invalid-dict.json -qapi-schema += event-nest-struct.json -qapi-schema += features-bad-type.json -qapi-schema += features-deprecated-type.json -qapi-schema += features-duplicate-name.json -qapi-schema += features-if-invalid.json -qapi-schema += features-missing-name.json -qapi-schema += features-name-bad-type.json -qapi-schema += features-no-list.json -qapi-schema += features-unknown-key.json -qapi-schema += flat-union-array-branch.json -qapi-schema += flat-union-bad-base.json -qapi-schema += flat-union-bad-discriminator.json -qapi-schema += flat-union-base-any.json -qapi-schema += flat-union-base-union.json -qapi-schema += flat-union-clash-member.json -qapi-schema += flat-union-discriminator-bad-name.json -qapi-schema += flat-union-empty.json -qapi-schema += flat-union-inline.json -qapi-schema += flat-union-inline-invalid-dict.json -qapi-schema += flat-union-int-branch.json -qapi-schema += flat-union-invalid-branch-key.json -qapi-schema += flat-union-invalid-discriminator.json -qapi-schema += flat-union-invalid-if-discriminator.json -qapi-schema += flat-union-no-base.json -qapi-schema += flat-union-optional-discriminator.json -qapi-schema += flat-union-string-discriminator.json -qapi-schema += funny-char.json -qapi-schema += funny-word.json -qapi-schema += ident-with-escape.json -qapi-schema += include-before-err.json -qapi-schema += include-cycle.json -qapi-schema += include-extra-junk.json -qapi-schema += include-nested-err.json -qapi-schema += include-no-file.json -qapi-schema += include-non-file.json -qapi-schema += include-repetition.json -qapi-schema += include-self-cycle.json -qapi-schema += include-simple.json -qapi-schema += indented-expr.json -qapi-schema += leading-comma-list.json -qapi-schema += leading-comma-object.json -qapi-schema += missing-colon.json -qapi-schema += missing-comma-list.json -qapi-schema += missing-comma-object.json -qapi-schema += missing-type.json -qapi-schema += nested-struct-data.json -qapi-schema += nested-struct-data-invalid-dict.json -qapi-schema += non-objects.json -qapi-schema += oob-test.json -qapi-schema += allow-preconfig-test.json -qapi-schema += pragma-doc-required-crap.json -qapi-schema += pragma-extra-junk.json -qapi-schema += pragma-name-case-whitelist-crap.json -qapi-schema += pragma-non-dict.json -qapi-schema += pragma-unknown.json -qapi-schema += pragma-returns-whitelist-crap.json -qapi-schema += qapi-schema-test.json -qapi-schema += quoted-structural-chars.json -qapi-schema += redefined-builtin.json -qapi-schema += redefined-command.json -qapi-schema += redefined-event.json -qapi-schema += redefined-type.json -qapi-schema += reserved-command-q.json -qapi-schema += reserved-enum-q.json -qapi-schema += reserved-member-has.json -qapi-schema += reserved-member-q.json -qapi-schema += reserved-member-u.json -qapi-schema += reserved-member-underscore.json -qapi-schema += reserved-type-kind.json -qapi-schema += reserved-type-list.json -qapi-schema += returns-alternate.json -qapi-schema += returns-array-bad.json -qapi-schema += returns-dict.json -qapi-schema += returns-unknown.json -qapi-schema += returns-whitelist.json -qapi-schema += string-code-point-31.json -qapi-schema += string-code-point-127.json -qapi-schema += struct-base-clash-deep.json -qapi-schema += struct-base-clash.json -qapi-schema += struct-data-invalid.json -qapi-schema += struct-member-if-invalid.json -qapi-schema += struct-member-invalid-dict.json -qapi-schema += struct-member-invalid.json -qapi-schema += trailing-comma-list.json -qapi-schema += trailing-comma-object.json -qapi-schema += type-bypass-bad-gen.json -qapi-schema += unclosed-list.json -qapi-schema += unclosed-object.json -qapi-schema += unclosed-string.json -qapi-schema += union-base-empty.json -qapi-schema += union-base-no-discriminator.json -qapi-schema += union-branch-case.json -qapi-schema += union-branch-if-invalid.json -qapi-schema += union-branch-invalid-dict.json -qapi-schema += union-clash-branches.json -qapi-schema += union-empty.json -qapi-schema += union-invalid-base.json -qapi-schema += union-optional-branch.json -qapi-schema += union-unknown.json -qapi-schema += unknown-escape.json -qapi-schema += unknown-expr-key.json - - -check-qapi-schema-y := $(addprefix tests/qapi-schema/, $(qapi-schema)) - generated-files-y += tests/test-qapi-types.h generated-files-y += tests/include/test-qapi-types-sub-module.h generated-files-y += tests/test-qapi-types-sub-sub-module.h @@ -501,13 +306,6 @@ tests/test-qapi-gen-timestamp: \ @rm -f tests/test-qapi-doc.texi @>$@ -tests/qapi-schema/doc-good.test.texi: $(SRC_PATH)/tests/qapi-schema/doc-good.json $(qapi-py) - $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ - -o tests/qapi-schema -p "doc-good-" $<, \ - "GEN","$@") - @mv tests/qapi-schema/doc-good-qapi-doc.texi $@ - @rm -f tests/qapi-schema/doc-good-qapi-*.[ch] tests/qapi-schema/doc-good-qmp-*.[ch] - tests/qtest/dbus-vmstate1.h tests/qtest/dbus-vmstate1.c: tests/qtest/dbus-vmstate1-gen-timestamp ; tests/qtest/dbus-vmstate1-gen-timestamp: $(SRC_PATH)/tests/qtest/dbus-vmstate1.xml $(call quiet-command,$(GDBUS_CODEGEN) $< \ @@ -720,7 +518,6 @@ check-tcg: $(RUN_TCG_TARGET_RULES) .PHONY: clean-tcg clean-tcg: $(CLEAN_TCG_TARGET_RULES) -# Other tests QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu-iotests/socket_scm_helper$(EXESUF) @@ -730,16 +527,6 @@ check-tests/check-block.sh: tests/check-block.sh qemu-img$(EXESUF) \ $(patsubst %,%/all,$(filter %-softmmu,$(TARGET_DIRS))) @$< -.PHONY: check-tests/qapi-schema/frontend -check-tests/qapi-schema/frontend: $(addprefix $(SRC_PATH)/, $(check-qapi-schema-y)) - $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \ - PYTHONIOENCODING=utf-8 $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py $^, \ - TEST, check-qapi-schema) - -.PHONY: check-tests/qapi-schema/doc-good.texi -check-tests/qapi-schema/doc-good.texi: tests/qapi-schema/doc-good.test.texi - @diff -u $(SRC_PATH)/tests/qapi-schema/doc-good.texi $< - # Python venv for running tests .PHONY: check-venv check-acceptance @@ -793,8 +580,7 @@ check-acceptance: check-venv $(TESTS_RESULTS_DIR) get-vm-images # Consolidated targets -.PHONY: check-block check-qapi-schema check-qtest check-unit check check-clean get-vm-images -check-qapi-schema: check-tests/qapi-schema/frontend check-tests/qapi-schema/doc-good.texi +.PHONY: check-block check-qtest check-unit check check-clean get-vm-images check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) ifeq ($(CONFIG_TOOLS),y) check-block: $(patsubst %,check-%, $(check-block-y)) @@ -808,7 +594,7 @@ check-clean: rm -f tests/qtest/dbus-vmstate1-gen-timestamp rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) -check: check-block check-qapi-schema check-unit check-qtest +check: check-block check-unit check-qtest clean: check-clean diff --git a/tests/meson.build b/tests/meson.build index ec26f92937..8be9c2233c 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -6,3 +6,5 @@ test('decodetree', sh, if 'CONFIG_TCG' in config_host subdir('fp') endif + +subdir('qapi-schema') diff --git a/tests/qapi-schema/meson.build b/tests/qapi-schema/meson.build new file mode 100644 index 0000000000..c87d141417 --- /dev/null +++ b/tests/qapi-schema/meson.build @@ -0,0 +1,225 @@ +test_env = environment() +test_env.set('PYTHONPATH', meson.source_root() / 'scripts') +test_env.set('PYTHONIOENCODING', 'utf-8') + +schemas = [ + 'alternate-any.json', + 'alternate-array.json', + 'alternate-base.json', + 'alternate-branch-if-invalid.json', + 'alternate-clash.json', + 'alternate-conflict-dict.json', + 'alternate-conflict-enum-bool.json', + 'alternate-conflict-enum-int.json', + 'alternate-conflict-string.json', + 'alternate-conflict-bool-string.json', + 'alternate-conflict-num-string.json', + 'alternate-empty.json', + 'alternate-invalid-dict.json', + 'alternate-nested.json', + 'alternate-unknown.json', + 'args-alternate.json', + 'args-any.json', + 'args-array-empty.json', + 'args-array-unknown.json', + 'args-bad-boxed.json', + 'args-boxed-anon.json', + 'args-boxed-string.json', + 'args-int.json', + 'args-invalid.json', + 'args-member-array-bad.json', + 'args-member-case.json', + 'args-member-unknown.json', + 'args-name-clash.json', + 'args-union.json', + 'args-unknown.json', + 'bad-base.json', + 'bad-data.json', + 'bad-ident.json', + 'bad-if.json', + 'bad-if-empty.json', + 'bad-if-empty-list.json', + 'bad-if-list.json', + 'bad-type-bool.json', + 'bad-type-dict.json', + 'bad-type-int.json', + 'base-cycle-direct.json', + 'base-cycle-indirect.json', + 'command-int.json', + 'comments.json', + 'doc-bad-alternate-member.json', + 'doc-bad-boxed-command-arg.json', + 'doc-bad-command-arg.json', + 'doc-bad-enum-member.json', + 'doc-bad-event-arg.json', + 'doc-bad-feature.json', + 'doc-bad-section.json', + 'doc-bad-symbol.json', + 'doc-bad-union-member.json', + 'doc-before-include.json', + 'doc-before-pragma.json', + 'doc-duplicated-arg.json', + 'doc-duplicated-return.json', + 'doc-duplicated-since.json', + 'doc-empty-arg.json', + 'doc-empty-section.json', + 'doc-empty-symbol.json', + 'doc-good.json', + 'doc-interleaved-section.json', + 'doc-invalid-end.json', + 'doc-invalid-end2.json', + 'doc-invalid-return.json', + 'doc-invalid-section.json', + 'doc-invalid-start.json', + 'doc-missing-colon.json', + 'doc-missing-expr.json', + 'doc-missing-space.json', + 'doc-missing.json', + 'doc-no-symbol.json', + 'doc-undoc-feature.json', + 'double-type.json', + 'duplicate-key.json', + 'empty.json', + 'enum-bad-member.json', + 'enum-bad-name.json', + 'enum-bad-prefix.json', + 'enum-clash-member.json', + 'enum-dict-member-unknown.json', + 'enum-if-invalid.json', + 'enum-int-member.json', + 'enum-member-case.json', + 'enum-missing-data.json', + 'enum-wrong-data.json', + 'event-boxed-empty.json', + 'event-case.json', + 'event-member-invalid-dict.json', + 'event-nest-struct.json', + 'features-bad-type.json', + 'features-deprecated-type.json', + 'features-duplicate-name.json', + 'features-if-invalid.json', + 'features-missing-name.json', + 'features-name-bad-type.json', + 'features-no-list.json', + 'features-unknown-key.json', + 'flat-union-array-branch.json', + 'flat-union-bad-base.json', + 'flat-union-bad-discriminator.json', + 'flat-union-base-any.json', + 'flat-union-base-union.json', + 'flat-union-clash-member.json', + 'flat-union-discriminator-bad-name.json', + 'flat-union-empty.json', + 'flat-union-inline.json', + 'flat-union-inline-invalid-dict.json', + 'flat-union-int-branch.json', + 'flat-union-invalid-branch-key.json', + 'flat-union-invalid-discriminator.json', + 'flat-union-invalid-if-discriminator.json', + 'flat-union-no-base.json', + 'flat-union-optional-discriminator.json', + 'flat-union-string-discriminator.json', + 'funny-char.json', + 'funny-word.json', + 'ident-with-escape.json', + 'include-before-err.json', + 'include-cycle.json', + 'include-extra-junk.json', + 'include-nested-err.json', + 'include-no-file.json', + 'include-non-file.json', + 'include-repetition.json', + 'include-self-cycle.json', + 'include-simple.json', + 'indented-expr.json', + 'leading-comma-list.json', + 'leading-comma-object.json', + 'missing-colon.json', + 'missing-comma-list.json', + 'missing-comma-object.json', + 'missing-type.json', + 'nested-struct-data.json', + 'nested-struct-data-invalid-dict.json', + 'non-objects.json', + 'oob-test.json', + 'allow-preconfig-test.json', + 'pragma-doc-required-crap.json', + 'pragma-extra-junk.json', + 'pragma-name-case-whitelist-crap.json', + 'pragma-non-dict.json', + 'pragma-unknown.json', + 'pragma-returns-whitelist-crap.json', + 'qapi-schema-test.json', + 'quoted-structural-chars.json', + 'redefined-builtin.json', + 'redefined-command.json', + 'redefined-event.json', + 'redefined-type.json', + 'reserved-command-q.json', + 'reserved-enum-q.json', + 'reserved-member-has.json', + 'reserved-member-q.json', + 'reserved-member-u.json', + 'reserved-member-underscore.json', + 'reserved-type-kind.json', + 'reserved-type-list.json', + 'returns-alternate.json', + 'returns-array-bad.json', + 'returns-dict.json', + 'returns-unknown.json', + 'returns-whitelist.json', + 'string-code-point-31.json', + 'string-code-point-127.json', + 'struct-base-clash-deep.json', + 'struct-base-clash.json', + 'struct-data-invalid.json', + 'struct-member-if-invalid.json', + 'struct-member-invalid-dict.json', + 'struct-member-invalid.json', + 'trailing-comma-list.json', + 'trailing-comma-object.json', + 'type-bypass-bad-gen.json', + 'unclosed-list.json', + 'unclosed-object.json', + 'unclosed-string.json', + 'union-base-empty.json', + 'union-base-no-discriminator.json', + 'union-branch-case.json', + 'union-branch-if-invalid.json', + 'union-branch-invalid-dict.json', + 'union-clash-branches.json', + 'union-empty.json', + 'union-invalid-base.json', + 'union-optional-branch.json', + 'union-unknown.json', + 'unknown-escape.json', + 'unknown-expr-key.json', +] + +# Because people may want to use test-qapi.py from the command line, we +# are not using the "#! /usr/bin/env python3" trick here. See +# docs/devel/build-system.txt +test('QAPI schema regression tests', python, args: files('test-qapi.py', schemas), + env: test_env, suite: ['qapi-schema', 'qapi-frontend']) + +diff = find_program('diff') + +qapi_doc = custom_target('QAPI doc', + output: ['doc-good-qapi-doc.texi', + 'doc-good-qapi-commands.c', 'doc-good-qapi-commands.h', + 'doc-good-qapi-emit-events.c', 'doc-good-qapi-emit-events.h', + 'doc-good-qapi-events.c', 'doc-good-qapi-events.h', + 'doc-good-qapi-init-commands.c', 'doc-good-qapi-init-commands.h', + 'doc-good-qapi-introspect.c', 'doc-good-qapi-introspect.h', + 'doc-good-qapi-types.c', 'doc-good-qapi-types.h', + 'doc-good-qapi-visit.c', 'doc-good-qapi-visit.h' ], + input: files('doc-good.json'), + command: [ qapi_gen, '-o', meson.current_build_dir(), + '-p', 'doc-good-', '@INPUT0@' ], + depend_files: qapi_gen_depends) + +# "full_path()" needed here to work around +# https://github.com/mesonbuild/meson/issues/7585 +test('QAPI doc', diff, args: ['-u', files('doc-good.texi'), qapi_doc[0].full_path()], + depends: qapi_doc, + suite: ['qapi-schema', 'qapi-doc']) -- cgit v1.2.3-55-g7522 From de59dda32db56a0126047f74ec817df181f22f4a Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 19:40:16 +0400 Subject: meson: convert qom directory to Meson (tools part) Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 2 +- Makefile.objs | 2 +- Makefile.target | 3 ++- meson.build | 1 + qom/Makefile.objs | 3 --- qom/meson.build | 15 +++++++++++++++ 6 files changed, 20 insertions(+), 6 deletions(-) create mode 100644 qom/meson.build diff --git a/Makefile b/Makefile index bc7647d37b..4b152e3587 100644 --- a/Makefile +++ b/Makefile @@ -248,7 +248,6 @@ dummy := $(call unnest-vars,, \ storage-daemon-obj-y \ storage-daemon-obj-m \ crypto-obj-y \ - qom-obj-y \ io-obj-y \ common-obj-y \ common-obj-m) @@ -269,6 +268,7 @@ $(SOFTMMU_ALL_RULES): $(storage-daemon-obj-y) $(SOFTMMU_ALL_RULES): $(chardev-obj-y) $(SOFTMMU_ALL_RULES): $(crypto-obj-y) $(SOFTMMU_ALL_RULES): $(io-obj-y) +$(SOFTMMU_ALL_RULES): $(qom-obj-y) $(SOFTMMU_ALL_RULES): config-all-devices.mak SOFTMMU_FUZZ_RULES=$(filter %-softmmu/fuzz, $(TARGET_DIRS_RULES)) diff --git a/Makefile.objs b/Makefile.objs index baf15656e8..84bfa2a61a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -1,6 +1,6 @@ ####################################################################### # Common libraries for tools and emulators -qom-obj-y = qom/ +qom-obj-y = qom/libqom.fa ####################################################################### # code used by both qemu system emulation and qemu-img diff --git a/Makefile.target b/Makefile.target index 257afc2723..1e04551a8e 100644 --- a/Makefile.target +++ b/Makefile.target @@ -191,13 +191,14 @@ all-obj-y := $(obj-y) common-obj-m := include $(SRC_PATH)/Makefile.objs +dummy := $(call fix-paths,../,, \ + qom-obj-y) dummy := $(call unnest-vars,.., \ authz-obj-y \ block-obj-y \ block-obj-m \ chardev-obj-y \ crypto-obj-y \ - qom-obj-y \ io-obj-y \ common-obj-y \ common-obj-m) diff --git a/meson.build b/meson.build index 6384401e9f..658d45c4c6 100644 --- a/meson.build +++ b/meson.build @@ -340,6 +340,7 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +subdir('qom') subdir('fsdev') # Other build targets diff --git a/qom/Makefile.objs b/qom/Makefile.objs index 1b45d104ba..b9629045e6 100644 --- a/qom/Makefile.objs +++ b/qom/Makefile.objs @@ -1,5 +1,2 @@ -qom-obj-y = object.o container.o qom-qobject.o -qom-obj-y += object_interfaces.o - common-obj-$(CONFIG_SOFTMMU) += qom-hmp-cmds.o qom-qmp-cmds.o storage-daemon-obj-y += qom-qmp-cmds.o diff --git a/qom/meson.build b/qom/meson.build new file mode 100644 index 0000000000..7b2cd510f8 --- /dev/null +++ b/qom/meson.build @@ -0,0 +1,15 @@ +qom_ss = ss.source_set() +qom_ss.add(files( + 'container.c', + 'object.c', + 'object_interfaces.c', + 'qom-qobject.c', +)) + +qom_ss = qom_ss.apply(config_host, strict: false) +libqom = static_library('qom', qom_ss.sources() + genh, + dependencies: [qom_ss.dependencies()], + link_with: [libqemuutil], + name_suffix: 'fa') + +qom = declare_dependency(link_whole: libqom) -- cgit v1.2.3-55-g7522 From 5e7fbd25157342b3b983779939419fb328e00f4c Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 22:54:34 +0400 Subject: meson: convert authz directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 1 - Makefile.objs | 3 ++- Makefile.target | 2 +- authz/Makefile.objs | 7 ------- authz/meson.build | 19 +++++++++++++++++++ meson.build | 5 +++++ 6 files changed, 27 insertions(+), 10 deletions(-) delete mode 100644 authz/Makefile.objs create mode 100644 authz/meson.build diff --git a/Makefile b/Makefile index 4b152e3587..d380271765 100644 --- a/Makefile +++ b/Makefile @@ -241,7 +241,6 @@ include $(SRC_PATH)/Makefile.objs endif dummy := $(call unnest-vars,, \ - authz-obj-y \ chardev-obj-y \ block-obj-y \ block-obj-m \ diff --git a/Makefile.objs b/Makefile.objs index 84bfa2a61a..0bc361d338 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -9,7 +9,8 @@ ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) chardev-obj-y = chardev/ -authz-obj-y = authz/ +authz-obj-y = authz/libauthz.fa +authz/libauthz.fa-libs = $(if $(CONFIG_AUTH_PAM),-lpam) block-obj-y = block/ nbd/ scsi/ block-obj-y += block.o blockjob.o job.o diff --git a/Makefile.target b/Makefile.target index 1e04551a8e..79b6e02bed 100644 --- a/Makefile.target +++ b/Makefile.target @@ -192,9 +192,9 @@ common-obj-m := include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ + authz-obj-y \ qom-obj-y) dummy := $(call unnest-vars,.., \ - authz-obj-y \ block-obj-y \ block-obj-m \ chardev-obj-y \ diff --git a/authz/Makefile.objs b/authz/Makefile.objs deleted file mode 100644 index ed7b273596..0000000000 --- a/authz/Makefile.objs +++ /dev/null @@ -1,7 +0,0 @@ -authz-obj-y += base.o -authz-obj-y += simple.o -authz-obj-y += list.o -authz-obj-y += listfile.o -authz-obj-$(CONFIG_AUTH_PAM) += pamacct.o - -pamacct.o-libs = -lpam diff --git a/authz/meson.build b/authz/meson.build new file mode 100644 index 0000000000..516d71f2e2 --- /dev/null +++ b/authz/meson.build @@ -0,0 +1,19 @@ +authz_ss = ss.source_set() +authz_ss.add(genh) +authz_ss.add(files( + 'base.c', + 'list.c', + 'listfile.c', + 'simple.c', +)) + +authz_ss.add(when: ['CONFIG_AUTH_PAM', pam], if_true: files('pamacct.c')) + +authz_ss = authz_ss.apply(config_host, strict: false) +libauthz = static_library('authz', authz_ss.sources() + genh, + dependencies: [authz_ss.dependencies()], + name_suffix: 'fa', + build_by_default: false) + +authz = declare_dependency(link_whole: libauthz, + dependencies: qom) diff --git a/meson.build b/meson.build index 658d45c4c6..34363bff19 100644 --- a/meson.build +++ b/meson.build @@ -103,6 +103,10 @@ if 'CONFIG_GNUTLS' in config_host endif pixman = declare_dependency(compile_args: config_host['PIXMAN_CFLAGS'].split(), link_args: config_host['PIXMAN_LIBS'].split()) +pam = not_found +if 'CONFIG_AUTH_PAM' in config_host + pam = cc.find_library('pam') +endif libattr = not_found if 'CONFIG_ATTR' in config_host libattr = declare_dependency(link_args: config_host['LIBATTR_LIBS'].split()) @@ -341,6 +345,7 @@ qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) subdir('qom') +subdir('authz') subdir('fsdev') # Other build targets -- cgit v1.2.3-55-g7522 From 5582c58f82b2a356cac721af2e973a6fc6880fc1 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 19:28:54 +0400 Subject: meson: convert crypto directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 1 - Makefile.objs | 2 +- Makefile.target | 2 +- crypto/Makefile.objs | 37 ------------------------------------- crypto/meson.build | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ meson.build | 4 ++-- qom/meson.build | 2 +- 7 files changed, 57 insertions(+), 43 deletions(-) delete mode 100644 crypto/Makefile.objs diff --git a/Makefile b/Makefile index d380271765..c3cc71cfc0 100644 --- a/Makefile +++ b/Makefile @@ -246,7 +246,6 @@ dummy := $(call unnest-vars,, \ block-obj-m \ storage-daemon-obj-y \ storage-daemon-obj-m \ - crypto-obj-y \ io-obj-y \ common-obj-y \ common-obj-m) diff --git a/Makefile.objs b/Makefile.objs index 0bc361d338..018338d2db 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -19,7 +19,7 @@ block-obj-$(CONFIG_REPLICATION) += replication.o block-obj-m = block/ -crypto-obj-y = crypto/ +crypto-obj-y = crypto/libcrypto.fa io-obj-y = io/ diff --git a/Makefile.target b/Makefile.target index 79b6e02bed..b213955a81 100644 --- a/Makefile.target +++ b/Makefile.target @@ -193,12 +193,12 @@ common-obj-m := include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ authz-obj-y \ + crypto-obj-y \ qom-obj-y) dummy := $(call unnest-vars,.., \ block-obj-y \ block-obj-m \ chardev-obj-y \ - crypto-obj-y \ io-obj-y \ common-obj-y \ common-obj-m) diff --git a/crypto/Makefile.objs b/crypto/Makefile.objs deleted file mode 100644 index a9885919f2..0000000000 --- a/crypto/Makefile.objs +++ /dev/null @@ -1,37 +0,0 @@ -crypto-obj-y = init.o -crypto-obj-y += hash.o -crypto-obj-$(CONFIG_NETTLE) += hash-nettle.o -crypto-obj-$(if $(CONFIG_NETTLE),n,$(CONFIG_GCRYPT)) += hash-gcrypt.o -crypto-obj-$(if $(CONFIG_NETTLE),n,$(if $(CONFIG_GCRYPT),n,y)) += hash-glib.o -crypto-obj-y += hmac.o -crypto-obj-$(CONFIG_NETTLE) += hmac-nettle.o -crypto-obj-$(CONFIG_GCRYPT_HMAC) += hmac-gcrypt.o -crypto-obj-$(if $(CONFIG_NETTLE),n,$(if $(CONFIG_GCRYPT_HMAC),n,y)) += hmac-glib.o -crypto-obj-y += aes.o -crypto-obj-y += desrfb.o -crypto-obj-y += cipher.o -crypto-obj-$(CONFIG_AF_ALG) += afalg.o -crypto-obj-$(CONFIG_AF_ALG) += cipher-afalg.o -crypto-obj-$(CONFIG_AF_ALG) += hash-afalg.o -crypto-obj-$(CONFIG_GNUTLS) += tls-cipher-suites.o -crypto-obj-y += tlscreds.o -crypto-obj-y += tlscredsanon.o -crypto-obj-y += tlscredspsk.o -crypto-obj-y += tlscredsx509.o -crypto-obj-y += tlssession.o -crypto-obj-y += secret_common.o -crypto-obj-y += secret.o -crypto-obj-$(CONFIG_SECRET_KEYRING) += secret_keyring.o -crypto-obj-y += pbkdf.o -crypto-obj-$(CONFIG_NETTLE) += pbkdf-nettle.o -crypto-obj-$(if $(CONFIG_NETTLE),n,$(CONFIG_GCRYPT)) += pbkdf-gcrypt.o -crypto-obj-$(if $(CONFIG_NETTLE),n,$(if $(CONFIG_GCRYPT),n,y)) += pbkdf-stub.o -crypto-obj-y += ivgen.o -crypto-obj-y += ivgen-essiv.o -crypto-obj-y += ivgen-plain.o -crypto-obj-y += ivgen-plain64.o -crypto-obj-y += afsplit.o -crypto-obj-$(CONFIG_QEMU_PRIVATE_XTS) += xts.o -crypto-obj-y += block.o -crypto-obj-y += block-qcow.o -crypto-obj-y += block-luks.o diff --git a/crypto/meson.build b/crypto/meson.build index 1b244315b9..18da7c8541 100644 --- a/crypto/meson.build +++ b/crypto/meson.build @@ -1,3 +1,55 @@ +crypto_ss = ss.source_set() +crypto_ss.add(genh) +crypto_ss.add(files( + 'afsplit.c', + 'block-luks.c', + 'block-qcow.c', + 'block.c', + 'cipher.c', + 'desrfb.c', + 'hash.c', + 'hmac.c', + 'ivgen-essiv.c', + 'ivgen-plain.c', + 'ivgen-plain64.c', + 'ivgen.c', + 'pbkdf.c', + 'secret_common.c', + 'secret.c', + 'tlscreds.c', + 'tlscredsanon.c', + 'tlscredspsk.c', + 'tlscredsx509.c', + 'tlssession.c', +)) + +if 'CONFIG_GCRYPT' in config_host + wo_nettle = files('hash-gcrypt.c', 'pbkdf-gcrypt.c') +else + wo_nettle = files('hash-glib.c', 'pbkdf-stub.c') +endif +if 'CONFIG_GCRYPT_HMAC' not in config_host + wo_nettle += files('hmac-glib.c') +endif +crypto_ss.add(when: [nettle, 'CONFIG_NETTLE'], + if_true: files('hash-nettle.c', 'hmac-nettle.c', 'pbkdf-nettle.c'), + if_false: wo_nettle) + +crypto_ss.add(when: 'CONFIG_SECRET_KEYRING', if_true: files('secret_keyring.c')) +crypto_ss.add(when: 'CONFIG_QEMU_PRIVATE_XTS', if_true: files('xts.c')) +crypto_ss.add(when: 'CONFIG_GCRYPT_HMAC', if_true: files('hmac-gcrypt.c')) +crypto_ss.add(when: 'CONFIG_AF_ALG', if_true: files('afalg.c', 'cipher-afalg.c', 'hash-afalg.c')) +crypto_ss.add(when: 'CONFIG_GNUTLS', if_true: files('tls-cipher-suites.c')) + +crypto_ss = crypto_ss.apply(config_host, strict: false) +libcrypto = static_library('crypto', crypto_ss.sources() + genh, + dependencies: [crypto_ss.dependencies()], + name_suffix: 'fa', + build_by_default: false) + +crypto = declare_dependency(link_whole: libcrypto, + dependencies: [authz, qom]) + util_ss.add(files('aes.c')) util_ss.add(files('init.c')) if 'CONFIG_GCRYPT' in config_host diff --git a/meson.build b/meson.build index 34363bff19..9d5cd00c89 100644 --- a/meson.build +++ b/meson.build @@ -328,6 +328,8 @@ subdir('qobject') subdir('stubs') subdir('trace') subdir('util') +subdir('qom') +subdir('authz') subdir('crypto') subdir('storage-daemon') subdir('ui') @@ -344,8 +346,6 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) -subdir('qom') -subdir('authz') subdir('fsdev') # Other build targets diff --git a/qom/meson.build b/qom/meson.build index 7b2cd510f8..cbab9cdfa2 100644 --- a/qom/meson.build +++ b/qom/meson.build @@ -1,4 +1,5 @@ qom_ss = ss.source_set() +qom_ss.add(genh) qom_ss.add(files( 'container.c', 'object.c', @@ -9,7 +10,6 @@ qom_ss.add(files( qom_ss = qom_ss.apply(config_host, strict: false) libqom = static_library('qom', qom_ss.sources() + genh, dependencies: [qom_ss.dependencies()], - link_with: [libqemuutil], name_suffix: 'fa') qom = declare_dependency(link_whole: libqom) -- cgit v1.2.3-55-g7522 From 7fcfd45666c382dfadce0ea160cba7e8d3328337 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 19:33:55 +0400 Subject: meson: convert io directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 1 - Makefile.objs | 2 +- Makefile.target | 2 +- io/Makefile.objs | 12 ------------ io/meson.build | 25 +++++++++++++++++++++++++ meson.build | 1 + 6 files changed, 28 insertions(+), 15 deletions(-) delete mode 100644 io/Makefile.objs create mode 100644 io/meson.build diff --git a/Makefile b/Makefile index c3cc71cfc0..1ee3398c15 100644 --- a/Makefile +++ b/Makefile @@ -246,7 +246,6 @@ dummy := $(call unnest-vars,, \ block-obj-m \ storage-daemon-obj-y \ storage-daemon-obj-m \ - io-obj-y \ common-obj-y \ common-obj-m) diff --git a/Makefile.objs b/Makefile.objs index 018338d2db..0920cdb40c 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -21,7 +21,7 @@ block-obj-m = block/ crypto-obj-y = crypto/libcrypto.fa -io-obj-y = io/ +io-obj-y = io/libio.fa endif # CONFIG_SOFTMMU or CONFIG_TOOLS diff --git a/Makefile.target b/Makefile.target index b213955a81..f6b7a86390 100644 --- a/Makefile.target +++ b/Makefile.target @@ -194,12 +194,12 @@ include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ authz-obj-y \ crypto-obj-y \ + io-obj-y \ qom-obj-y) dummy := $(call unnest-vars,.., \ block-obj-y \ block-obj-m \ chardev-obj-y \ - io-obj-y \ common-obj-y \ common-obj-m) all-obj-y += $(common-obj-y) diff --git a/io/Makefile.objs b/io/Makefile.objs deleted file mode 100644 index 9a20fce4ed..0000000000 --- a/io/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -io-obj-y = channel.o -io-obj-y += channel-buffer.o -io-obj-y += channel-command.o -io-obj-y += channel-file.o -io-obj-y += channel-socket.o -io-obj-y += channel-tls.o -io-obj-y += channel-watch.o -io-obj-y += channel-websock.o -io-obj-y += channel-util.o -io-obj-y += dns-resolver.o -io-obj-y += net-listener.o -io-obj-y += task.o diff --git a/io/meson.build b/io/meson.build new file mode 100644 index 0000000000..768c1b5ec3 --- /dev/null +++ b/io/meson.build @@ -0,0 +1,25 @@ +io_ss = ss.source_set() +io_ss.add(genh) +io_ss.add(files( + 'channel-buffer.c', + 'channel-command.c', + 'channel-file.c', + 'channel-socket.c', + 'channel-tls.c', + 'channel-util.c', + 'channel-watch.c', + 'channel-websock.c', + 'channel.c', + 'dns-resolver.c', + 'net-listener.c', + 'task.c', +)) + +io_ss = io_ss.apply(config_host, strict: false) +libio = static_library('io', io_ss.sources() + genh, + dependencies: [io_ss.dependencies()], + link_with: libqemuutil, + name_suffix: 'fa', + build_by_default: false) + +io = declare_dependency(link_whole: libio, dependencies: [crypto, qom]) diff --git a/meson.build b/meson.build index 9d5cd00c89..ece3be725d 100644 --- a/meson.build +++ b/meson.build @@ -346,6 +346,7 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +subdir('io') subdir('fsdev') # Other build targets -- cgit v1.2.3-55-g7522 From d3b184809608f3ea948b199d779ec02169ad7085 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 14:55:32 +0400 Subject: meson: convert target/s390x/gen-features.h Needed by linux-user/s390x/cpu_loop.c; this removes the only use of HOST_CC. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 2 ++ configure | 1 - meson.build | 1 + target/meson.build | 1 + target/s390x/Makefile.objs | 20 -------------------- target/s390x/cpu_features.h | 2 +- target/s390x/cpu_models.h | 2 +- target/s390x/meson.build | 9 +++++++++ 8 files changed, 15 insertions(+), 23 deletions(-) create mode 100644 target/meson.build create mode 100644 target/s390x/meson.build diff --git a/Makefile b/Makefile index 1ee3398c15..698bbdfcd3 100644 --- a/Makefile +++ b/Makefile @@ -124,6 +124,8 @@ CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) generated-files-y = config-host.h generated-files-y += module_block.h +generated-files-y += target/s390x/gen-features.h +target/s390x/gen-features.h: Makefile.ninja generated-files-y += .git-submodule-status diff --git a/configure b/configure index e58607a984..c20436f8b2 100755 --- a/configure +++ b/configure @@ -7834,7 +7834,6 @@ echo "CC=$cc" >> $config_host_mak if $iasl -h > /dev/null 2>&1; then echo "IASL=$iasl" >> $config_host_mak fi -echo "HOST_CC=$host_cc" >> $config_host_mak echo "CXX=$cxx" >> $config_host_mak echo "OBJCC=$objcc" >> $config_host_mak echo "AR=$ar" >> $config_host_mak diff --git a/meson.build b/meson.build index ece3be725d..c892672628 100644 --- a/meson.build +++ b/meson.build @@ -348,6 +348,7 @@ qemuutil = declare_dependency(link_with: libqemuutil, subdir('io') subdir('fsdev') +subdir('target') # Other build targets if 'CONFIG_GUEST_AGENT' in config_host diff --git a/target/meson.build b/target/meson.build new file mode 100644 index 0000000000..e29dd3e01f --- /dev/null +++ b/target/meson.build @@ -0,0 +1 @@ +subdir('s390x') diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs index 3e2745594a..9b9accc5fd 100644 --- a/target/s390x/Makefile.objs +++ b/target/s390x/Makefile.objs @@ -8,23 +8,3 @@ obj-$(CONFIG_SOFTMMU) += sigp.o obj-$(CONFIG_KVM) += kvm.o obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o - -# build and run feature list generator -feat-src = $(SRC_PATH)/target/$(TARGET_BASE_ARCH)/ -feat-dst = $(BUILD_DIR)/$(TARGET_DIR) -ifneq ($(MAKECMDGOALS),clean) -generated-files-y += $(feat-dst)gen-features.h -endif - -$(feat-dst)gen-features.h: $(feat-dst)gen-features.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ -$(feat-dst)gen-features.h-timestamp: $(feat-dst)gen-features - $(call quiet-command,$< >$@,"GEN","$(TARGET_DIR)gen-features.h") - -$(feat-dst)gen-features: $(feat-src)gen-features.c - $(call quiet-command,$(HOST_CC) $(QEMU_INCLUDES) -o $@ $<,"CC","$(TARGET_DIR)gen-features") - -clean-target: - rm -f gen-features.h-timestamp - rm -f gen-features.h - rm -f gen-features diff --git a/target/s390x/cpu_features.h b/target/s390x/cpu_features.h index da695a8346..2a29475493 100644 --- a/target/s390x/cpu_features.h +++ b/target/s390x/cpu_features.h @@ -16,7 +16,7 @@ #include "qemu/bitmap.h" #include "cpu_features_def.h" -#include "gen-features.h" +#include "target/s390x/gen-features.h" /* CPU features are announced via different ways */ typedef enum { diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h index 88bd01a616..74d1f87e4f 100644 --- a/target/s390x/cpu_models.h +++ b/target/s390x/cpu_models.h @@ -14,7 +14,7 @@ #define TARGET_S390X_CPU_MODELS_H #include "cpu_features.h" -#include "gen-features.h" +#include "target/s390x/gen-features.h" #include "hw/core/cpu.h" /* static CPU definition */ diff --git a/target/s390x/meson.build b/target/s390x/meson.build new file mode 100644 index 0000000000..ddf8d20a36 --- /dev/null +++ b/target/s390x/meson.build @@ -0,0 +1,9 @@ +gen_features = executable('gen-features', 'gen-features.c', native: true, + build_by_default: false) + +gen_features_h = custom_target('gen-features.h', + output: 'gen-features.h', + capture: true, + command: gen_features) + +specific_ss.add(gen_features_h) -- cgit v1.2.3-55-g7522 From 2becc36a3e53dc9b8ed01c5288e21a2463f1f640 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Feb 2020 11:42:03 +0100 Subject: meson: infrastructure for building emulators Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 74 +++------------------- Makefile.target | 19 +++--- configure | 6 -- hw/i386/fw_cfg.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/i386/x86.c | 2 +- hw/vfio/pci-quirks.c | 2 +- hw/virtio/virtio-mem.c | 2 +- include/qemu/osdep.h | 2 +- meson.build | 166 ++++++++++++++++++++++++++++++++++++++++++++++++- rules.mak | 8 --- scripts/create_config | 2 + scripts/grepy.sh | 3 + scripts/minikconf.py | 0 softmmu/qtest.c | 2 +- 16 files changed, 192 insertions(+), 102 deletions(-) create mode 100755 scripts/grepy.sh mode change 100755 => 100644 scripts/minikconf.py diff --git a/Makefile b/Makefile index 698bbdfcd3..19f167ba5f 100644 --- a/Makefile +++ b/Makefile @@ -121,8 +121,6 @@ include $(SRC_PATH)/rules.mak # lor is defined in rules.mak CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) -generated-files-y = config-host.h - generated-files-y += module_block.h generated-files-y += target/s390x/gen-features.h target/s390x/gen-features.h: Makefile.ninja @@ -178,65 +176,6 @@ DOCS= endif SUBDIR_MAKEFLAGS=$(if $(V),,--no-print-directory --quiet) BUILD_DIR=$(BUILD_DIR) -SUBDIR_DEVICES_MAK=$(patsubst %, %/config-devices.mak, $(filter %-softmmu, $(TARGET_DIRS))) -SUBDIR_DEVICES_MAK_DEP=$(patsubst %, %.d, $(SUBDIR_DEVICES_MAK)) - -ifeq ($(SUBDIR_DEVICES_MAK),) -config-all-devices.mak: config-host.mak - $(call quiet-command,echo '# no devices' > $@,"GEN","$@") -else -config-all-devices.mak: $(SUBDIR_DEVICES_MAK) config-host.mak - $(call quiet-command, sed -n \ - 's|^\([^=]*\)=\(.*\)$$|\1:=$$(findstring y,$$(\1)\2)|p' \ - $(SUBDIR_DEVICES_MAK) | sort -u > $@, \ - "GEN","$@") -endif - --include $(SUBDIR_DEVICES_MAK_DEP) - -# This has to be kept in sync with Kconfig.host. -MINIKCONF_ARGS = \ - $(CONFIG_MINIKCONF_MODE) \ - $@ $*/config-devices.mak.d $< $(SRC_PATH)/Kconfig \ - CONFIG_TCG=$(CONFIG_TCG) \ - CONFIG_KVM=$(CONFIG_KVM) \ - CONFIG_SPICE=$(CONFIG_SPICE) \ - CONFIG_IVSHMEM=$(CONFIG_IVSHMEM) \ - CONFIG_TPM=$(CONFIG_TPM) \ - CONFIG_XEN=$(CONFIG_XEN) \ - CONFIG_OPENGL=$(CONFIG_OPENGL) \ - CONFIG_X11=$(CONFIG_X11) \ - CONFIG_VHOST_USER=$(CONFIG_VHOST_USER) \ - CONFIG_VHOST_KERNEL=$(CONFIG_VHOST_KERNEL) \ - CONFIG_VIRTFS=$(CONFIG_VIRTFS) \ - CONFIG_LINUX=$(CONFIG_LINUX) \ - CONFIG_PVRDMA=$(CONFIG_PVRDMA) - -MINIKCONF = $(PYTHON) $(SRC_PATH)/scripts/minikconf.py - -$(SUBDIR_DEVICES_MAK): %/config-devices.mak: default-configs/%.mak $(SRC_PATH)/Kconfig $(BUILD_DIR)/config-host.mak - $(call quiet-command, $(MINIKCONF) $(MINIKCONF_ARGS) \ - > $@.tmp, "GEN", "$@.tmp") - $(call quiet-command, if test -f $@; then \ - if cmp -s $@.old $@; then \ - mv $@.tmp $@; \ - cp -p $@ $@.old; \ - else \ - if test -f $@.old; then \ - echo "WARNING: $@ (user modified) out of date.";\ - else \ - echo "WARNING: $@ out of date.";\ - fi; \ - echo "Run \"$(MAKE) defconfig\" to regenerate."; \ - rm $@.tmp; \ - fi; \ - else \ - mv $@.tmp $@; \ - cp -p $@ $@.old; \ - fi,"GEN","$@"); - -defconfig: - rm -f config-all-devices.mak $(SUBDIR_DEVICES_MAK) ifneq ($(wildcard config-host.mak),) include $(SRC_PATH)/Makefile.objs @@ -279,10 +218,15 @@ $(SOFTMMU_FUZZ_RULES): $(io-obj-y) $(SOFTMMU_FUZZ_RULES): config-all-devices.mak $(SOFTMMU_FUZZ_RULES): $(edk2-decompressed) +# meson: this is sub-optimal but going away after conversion +TARGET_DEPS = $(patsubst %,%-config-target.h, $(TARGET_DIRS)) +TARGET_DEPS += $(patsubst %,%-config-devices.h, $(filter %-softmmu,$(TARGET_DIRS))) +TARGET_DEPS += $(patsubst %,libqemu-%.fa, $(TARGET_DIRS)) + .PHONY: $(TARGET_DIRS_RULES) # The $(TARGET_DIRS_RULES) are of the form SUBDIR/GOAL, so that # $(dir $@) yields the sub-directory, and $(notdir $@) yields the sub-goal -$(TARGET_DIRS_RULES): +$(TARGET_DIRS_RULES): $(TARGET_DEPS) $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $(dir $@) V="$(V)" TARGET_DIR="$(dir $@)" $(notdir $@),) # LIBFDT_lib="": avoid breaking existing trees with objects requiring -fPIC @@ -370,7 +314,6 @@ clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h - rm -f qemu-options.def find . \( -name '*.so' -o -name '*.dll' -o -name '*.mo' -o -name '*.[oda]' \) -type f \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-aarch64.a \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-arm.a \ @@ -379,8 +322,6 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod scsi/*.pod rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) - rm -f config-all-devices.mak - rm -f $(SUBDIR_DEVICES_MAK) VERSION ?= $(shell cat VERSION) @@ -398,8 +339,7 @@ distclean: clean ninja-distclean -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean -g rm -f config-host.mak config-host.h* $(DOCS) rm -f tests/tcg/config-*.mak - rm -f config-all-devices.mak config-all-disas.mak config.status - rm -f $(SUBDIR_DEVICES_MAK) + rm -f config-all-disas.mak config.status rm -f po/*.mo tests/qemu-iotests/common.env rm -f roms/seabios/config.mak roms/vgabios/config.mak rm -f qemu-plugins-ld.symbols qemu-plugins-ld64.symbols diff --git a/Makefile.target b/Makefile.target index f6b7a86390..43d2f9734f 100644 --- a/Makefile.target +++ b/Makefile.target @@ -6,8 +6,10 @@ include ../config-host.mak include config-target.mak include $(SRC_PATH)/rules.mak +FULL_TARGET_NAME=$(TARGET_NAME)-$(if $(CONFIG_SOFTMMU),softmmu,linux-user) + ifdef CONFIG_SOFTMMU -include config-devices.mak +include ../$(FULL_TARGET_NAME)-config-devices.mak endif $(call set-vpath, $(SRC_PATH):$(BUILD_DIR)) @@ -18,6 +20,9 @@ QEMU_CFLAGS += -iquote .. -iquote $(SRC_PATH)/target/$(TARGET_BASE_ARCH) -DNEED_ QEMU_CFLAGS+=-iquote $(SRC_PATH)/include +QEMU_CFLAGS += -DCONFIG_TARGET=\"../$(FULL_TARGET_NAME)-config-target.h\" +QEMU_CFLAGS += -DCONFIG_DEVICES=\"../$(FULL_TARGET_NAME)-config-devices.h\" + ifdef CONFIG_USER_ONLY # user emulator name QEMU_PROG=qemu-$(TARGET_NAME) @@ -36,15 +41,10 @@ QEMU_PROG_BUILD = $(QEMU_PROG) endif endif +LIBQEMU = ../libqemu-$(FULL_TARGET_NAME).fa PROGS=$(QEMU_PROG) $(QEMU_PROGW) STPFILES= -config-target.h: config-target.h-timestamp -config-target.h-timestamp: config-target.mak - -config-devices.h: config-devices.h-timestamp -config-devices.h-timestamp: config-devices.mak - ifdef CONFIG_TRACE_SYSTEMTAP stap: $(QEMU_PROG).stp-installed $(QEMU_PROG).stp $(QEMU_PROG)-simpletrace.stp $(QEMU_PROG)-log.stp @@ -103,6 +103,7 @@ all: $(PROGS) stap # Dummy command so that make thinks it has done something @true +obj-y += $(LIBQEMU) obj-y += trace/ ######################################################### @@ -169,7 +170,6 @@ obj-y += hw/$(TARGET_BASE_ARCH)/ endif generated-files-y += hmp-commands.h hmp-commands-info.h -generated-files-y += config-devices.h endif # CONFIG_SOFTMMU @@ -210,7 +210,7 @@ all-obj-$(CONFIG_SOFTMMU) += $(crypto-obj-y) all-obj-$(CONFIG_SOFTMMU) += $(io-obj-y) ifdef CONFIG_SOFTMMU -$(QEMU_PROG_BUILD): config-devices.mak +$(QEMU_PROG_BUILD): ../$(FULL_TARGET_NAME)-config-devices.mak endif COMMON_LDADDS = ../libqemuutil.a @@ -262,5 +262,4 @@ ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DATA) $(QEMU_PROG)-log.stp "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG)-log.stp" endif -generated-files-y += config-target.h Makefile: $(generated-files-y) diff --git a/configure b/configure index c20436f8b2..fe79cb131e 100755 --- a/configure +++ b/configure @@ -8169,18 +8169,12 @@ fi if supported_xen_target $target; then echo "CONFIG_XEN=y" >> $config_target_mak - echo "$target/config-devices.mak: CONFIG_XEN=y" >> $config_host_mak if test "$xen_pci_passthrough" = yes; then echo "CONFIG_XEN_PCI_PASSTHROUGH=y" >> "$config_target_mak" fi -else - echo "$target/config-devices.mak: CONFIG_XEN=n" >> $config_host_mak fi if supported_kvm_target $target; then echo "CONFIG_KVM=y" >> $config_target_mak - echo "$target/config-devices.mak: CONFIG_KVM=y" >> $config_host_mak -else - echo "$target/config-devices.mak: CONFIG_KVM=n" >> $config_host_mak fi if supported_hax_target $target; then echo "CONFIG_HAX=y" >> $config_target_mak diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index c55abfb01a..33441ad484 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -22,7 +22,7 @@ #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" #include "kvm_i386.h" -#include "config-devices.h" +#include CONFIG_DEVICES struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 47c5ca3e34..cc616e48f3 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -92,10 +92,10 @@ #include "hw/mem/memory-device.h" #include "sysemu/replay.h" #include "qapi/qmp/qerror.h" -#include "config-devices.h" #include "e820_memory_layout.h" #include "fw_cfg.h" #include "trace.h" +#include CONFIG_DEVICES GlobalProperty pc_compat_5_0[] = { }; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b789e83f9a..456e336934 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -23,7 +23,7 @@ */ #include "qemu/osdep.h" -#include "config-devices.h" +#include CONFIG_DEVICES #include "qemu/units.h" #include "hw/loader.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 67bee1bcb8..cf384b9743 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -49,7 +49,7 @@ #include "multiboot.h" #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" -#include "config-devices.h" +#include CONFIG_DEVICES #include "kvm_i386.h" #define BIOS_FILENAME "bios.bin" diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 3a14b7c303..57150913b7 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "config-devices.h" +#include CONFIG_DEVICES #include "exec/memop.h" #include "qemu/units.h" #include "qemu/error-report.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 7740fc613f..8fbec77ccc 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -29,7 +29,7 @@ #include "migration/misc.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "config-devices.h" +#include CONFIG_DEVICES #include "trace.h" /* diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 20872e793e..412962d91a 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -29,7 +29,7 @@ #include "config-host.h" #ifdef NEED_CPU_H -#include "config-target.h" +#include CONFIG_TARGET #else #include "exec/poison.h" #endif diff --git a/meson.build b/meson.build index c892672628..6f8024cdcf 100644 --- a/meson.build +++ b/meson.build @@ -9,6 +9,7 @@ ss = import('sourceset') sh = find_program('sh') cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') +config_all_disas = keyval.load(meson.current_build_dir() / 'config-all-disas.mak') add_project_arguments(config_host['QEMU_CFLAGS'].split(), native: false, language: ['c', 'objc']) @@ -151,16 +152,96 @@ if 'CONFIG_LIBUDEV' in config_host libudev = declare_dependency(link_args: config_host['LIBUDEV_LIBS'].split()) endif +create_config = find_program('scripts/create_config') +minikconf = find_program('scripts/minikconf.py') target_dirs = config_host['TARGET_DIRS'].split() have_user = false have_system = false +config_devices_mak_list = [] +config_devices_h = {} +config_target_mak = {} +kconfig_external_symbols = [ + 'CONFIG_KVM', + 'CONFIG_XEN', + 'CONFIG_TPM', + 'CONFIG_SPICE', + 'CONFIG_IVSHMEM', + 'CONFIG_OPENGL', + 'CONFIG_X11', + 'CONFIG_VHOST_USER', + 'CONFIG_VHOST_KERNEL', + 'CONFIG_VIRTFS', + 'CONFIG_LINUX', + 'CONFIG_PVRDMA', +] foreach target : target_dirs have_user = have_user or target.endswith('-user') - have_system = have_system or target.endswith('-softmmu') + config_target = keyval.load(meson.current_build_dir() / target / 'config-target.mak') + config_host + + if target.endswith('-softmmu') + have_system = true + + base_kconfig = [] + foreach sym : kconfig_external_symbols + if sym in config_target + base_kconfig += '@0@=y'.format(sym) + endif + endforeach + + config_devices_mak = target + '-config-devices.mak' + config_devices_mak = configure_file( + input: ['default-configs' / target + '.mak', 'Kconfig'], + output: config_devices_mak, + depfile: config_devices_mak + '.d', + capture: true, + command: [minikconf, config_host['CONFIG_MINIKCONF_MODE'], + config_devices_mak, '@DEPFILE@', '@INPUT@', + base_kconfig]) + config_devices_h += {target: custom_target( + target + '-config-devices.h', + input: config_devices_mak, + output: target + '-config-devices.h', + capture: true, + command: [create_config, '@INPUT@'])} + config_devices_mak_list += config_devices_mak + config_target += keyval.load(config_devices_mak) + endif + config_target_mak += {target: config_target} endforeach have_tools = 'CONFIG_TOOLS' in config_host have_block = have_system or have_tools +grepy = find_program('scripts/grepy.sh') +# This configuration is used to build files that are shared by +# multiple binaries, and then extracted out of the "common" +# static_library target. +# +# We do not use all_sources()/all_dependencies(), because it would +# build literally all source files, including devices only used by +# targets that are not built for this compilation. The CONFIG_ALL +# pseudo symbol replaces it. + +if have_system + config_all_devices_mak = configure_file( + output: 'config-all-devices.mak', + input: config_devices_mak_list, + capture: true, + command: [grepy, '@INPUT@'], + ) + config_all_devices = keyval.load(config_all_devices_mak) +else + config_all_devices = {} +endif +config_all = config_all_devices +config_all += config_host +config_all += config_all_disas +config_all += { + 'CONFIG_XEN': config_host.has_key('CONFIG_XEN_BACKEND'), + 'CONFIG_SOFTMMU': have_system, + 'CONFIG_USER_ONLY': have_user, + 'CONFIG_ALL': true, +} + # Generators genh = [] @@ -202,6 +283,13 @@ qemu_version = custom_target('qemu-version.h', build_always_stale: true) genh += qemu_version +config_host_h = custom_target('config-host.h', + input: meson.current_build_dir() / 'config-host.mak', + output: 'config-host.h', + capture: true, + command: [create_config, '@INPUT@']) +genh += config_host_h + hxdep = [] hx_headers = [ ['qemu-options.hx', 'qemu-options.def'], @@ -228,6 +316,16 @@ genh += hxdep util_ss = ss.source_set() stub_ss = ss.source_set() trace_ss = ss.source_set() +common_ss = ss.source_set() +softmmu_ss = ss.source_set() +user_ss = ss.source_set() +bsd_user_ss = ss.source_set() +linux_user_ss = ss.source_set() +specific_ss = ss.source_set() + +hw_arch = {} +target_arch = {} +target_softmmu_arch = {} ############### # Trace files # @@ -336,10 +434,10 @@ subdir('ui') # Build targets from sourcesets -stub_ss = stub_ss.apply(config_host, strict: false) +stub_ss = stub_ss.apply(config_all, strict: false) util_ss.add_all(trace_ss) -util_ss = util_ss.apply(config_host, strict: false) +util_ss = util_ss.apply(config_all, strict: false) libqemuutil = static_library('qemuutil', sources: util_ss.sources() + stub_ss.sources() + genh, dependencies: [util_ss.dependencies(), m, glib, socket]) @@ -350,6 +448,68 @@ subdir('io') subdir('fsdev') subdir('target') +common_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: softmmu_ss) +common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: user_ss) + +common_all = common_ss.apply(config_all, strict: false) +common_all = static_library('common', + build_by_default: false, + sources: common_all.sources() + genh, + dependencies: common_all.dependencies(), + name_suffix: 'fa') + +foreach target : target_dirs + config_target = config_target_mak[target] + target_name = config_target['TARGET_NAME'] + arch = config_target['TARGET_BASE_ARCH'] + arch_srcs = [] + + target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])] + if targetos == 'linux' + target_inc += include_directories('linux-headers', is_system: true) + endif + if target.endswith('-softmmu') + qemu_target_name = 'qemu-system-' + target_name + target_type='system' + arch_srcs += config_devices_h[target] + else + target_type='user' + qemu_target_name = 'qemu-' + target_name + if 'CONFIG_LINUX_USER' in config_target + base_dir = 'linux-user' + target_inc += include_directories('linux-user/host/' / config_host['ARCH']) + else + base_dir = 'bsd-user' + endif + target_inc += include_directories( + base_dir, + base_dir / config_target['TARGET_ABI_DIR'], + ) + endif + + target_common = common_ss.apply(config_target, strict: false) + objects = common_all.extract_objects(target_common.sources()) + + # TODO: Change to generator once obj-y goes away + config_target_h = custom_target(target + '-config-target.h', + input: meson.current_build_dir() / target / 'config-target.mak', + output: target + '-config-target.h', + capture: true, + command: [create_config, '@INPUT@']) + + target_specific = specific_ss.apply(config_target, strict: false) + arch_srcs += target_specific.sources() + + static_library('qemu-' + target, + sources: arch_srcs + [config_target_h] + genh, + objects: objects, + include_directories: target_inc, + c_args: ['-DNEED_CPU_H', + '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), + '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)], + name_suffix: 'fa') +endforeach + # Other build targets if 'CONFIG_GUEST_AGENT' in config_host subdir('qga') diff --git a/rules.mak b/rules.mak index 1aa6394079..d8d35f735a 100644 --- a/rules.mak +++ b/rules.mak @@ -203,14 +203,6 @@ notempty = $(if $1,y,n) # Generate files with tracetool TRACETOOL=$(PYTHON) $(SRC_PATH)/scripts/tracetool.py -# Generate timestamp files for .h include files - -config-%.h: config-%.h-timestamp - @cmp $< $@ >/dev/null 2>&1 || cp $< $@ - -config-%.h-timestamp: config-%.mak $(SRC_PATH)/scripts/create_config - $(call quiet-command, sh $(SRC_PATH)/scripts/create_config < $< > $@,"GEN","$(TARGET_DIR)config-$*.h") - .PHONY: clean-timestamp clean-timestamp: rm -f *.timestamp diff --git a/scripts/create_config b/scripts/create_config index 6d8f08b39d..bc82661041 100755 --- a/scripts/create_config +++ b/scripts/create_config @@ -1,5 +1,7 @@ #!/bin/sh +test $# -gt 0 && exec < $1 + echo "/* Automatically generated by create_config - do not modify */" while read line; do diff --git a/scripts/grepy.sh b/scripts/grepy.sh new file mode 100755 index 0000000000..aee46ddc8d --- /dev/null +++ b/scripts/grepy.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +grep -h '=y$' "$@" | sort -u diff --git a/scripts/minikconf.py b/scripts/minikconf.py old mode 100755 new mode 100644 diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 5672b75c35..4e439caec7 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -27,7 +27,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/cutils.h" -#include "config-devices.h" +#include CONFIG_DEVICES #ifdef CONFIG_PSERIES #include "hw/ppc/spapr_rtas.h" #endif -- cgit v1.2.3-55-g7522 From 3154fee4db6d14e72050c7efc6a6f4eb06d01d4a Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 29 Aug 2019 22:07:01 +0400 Subject: meson: add modules infrastructure Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 10 +--------- Makefile.target | 6 ++++++ meson.build | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ rules.mak | 10 +++++----- scripts/undefsym.sh | 20 ++++++++++++++++++++ 5 files changed, 83 insertions(+), 14 deletions(-) create mode 100755 scripts/undefsym.sh diff --git a/Makefile b/Makefile index 19f167ba5f..0ec50ee9b7 100644 --- a/Makefile +++ b/Makefile @@ -266,7 +266,7 @@ slirp/all: .git-submodule-status CFLAGS="$(QEMU_CFLAGS) $(CFLAGS)" LDFLAGS="$(QEMU_LDFLAGS)") $(filter %/all, $(TARGET_DIRS_RULES)): libqemuutil.a $(common-obj-y) \ - $(qom-obj-y) + $(qom-obj-y) block.syms qemu.syms $(filter %/fuzz, $(TARGET_DIRS_RULES)): libqemuutil.a $(common-obj-y) \ $(qom-obj-y) $(crypto-user-obj-$(CONFIG_USER_ONLY)) @@ -474,14 +474,6 @@ install: all $(if $(BUILD_DOCS),install-doc) \ ifneq ($(TOOLS),) $(call install-prog,$(TOOLS),$(DESTDIR)$(bindir)) endif -ifneq ($(CONFIG_MODULES),) - $(INSTALL_DIR) "$(DESTDIR)$(qemu_moddir)" - for s in $(modules-m:.mo=$(DSOSUF)); do \ - t="$(DESTDIR)$(qemu_moddir)/$$(echo $$s | tr / -)"; \ - $(INSTALL_LIB) $$s "$$t"; \ - test -z "$(STRIP)" || $(STRIP) "$$t"; \ - done -endif ifneq ($(HELPERS-y),) $(call install-prog,$(HELPERS-y),$(DESTDIR)$(libexecdir)) endif diff --git a/Makefile.target b/Makefile.target index 43d2f9734f..d1d8906b4d 100644 --- a/Makefile.target +++ b/Makefile.target @@ -162,6 +162,12 @@ obj-y += qapi/ obj-y += migration/ram.o LIBS := $(libs_softmmu) $(LIBS) +# Temporary until emulators are linked by Meson +LIBS := $(LIBS) @../block.syms @../qemu.syms +ifneq ($(CONFIG_MODULES),y) +LIBS := $(LIBS) +endif + # Hardware support ifeq ($(TARGET_NAME), sparc64) obj-y += hw/sparc64/ diff --git a/meson.build b/meson.build index 6f8024cdcf..13b83ea14b 100644 --- a/meson.build +++ b/meson.build @@ -10,6 +10,7 @@ sh = find_program('sh') cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') config_all_disas = keyval.load(meson.current_build_dir() / 'config-all-disas.mak') +enable_modules = 'CONFIG_MODULES' in config_host add_project_arguments(config_host['QEMU_CFLAGS'].split(), native: false, language: ['c', 'objc']) @@ -316,6 +317,7 @@ genh += hxdep util_ss = ss.source_set() stub_ss = ss.source_set() trace_ss = ss.source_set() +block_ss = ss.source_set() common_ss = ss.source_set() softmmu_ss = ss.source_set() user_ss = ss.source_set() @@ -323,6 +325,7 @@ bsd_user_ss = ss.source_set() linux_user_ss = ss.source_set() specific_ss = ss.source_set() +modules = {} hw_arch = {} target_arch = {} target_softmmu_arch = {} @@ -432,6 +435,12 @@ subdir('crypto') subdir('storage-daemon') subdir('ui') + +if enable_modules + libmodulecommon = static_library('module-common', files('module-common.c') + genh, pic: true, c_args: '-DBUILD_DSO') + modulecommon = declare_dependency(link_whole: libmodulecommon, compile_args: '-DBUILD_DSO') +endif + # Build targets from sourcesets stub_ss = stub_ss.apply(config_all, strict: false) @@ -448,6 +457,48 @@ subdir('io') subdir('fsdev') subdir('target') +block_mods = [] +softmmu_mods = [] +foreach d, list : modules + foreach m, module_ss : list + if enable_modules and targetos != 'windows' + module_ss = module_ss.apply(config_host, strict: false) + sl = static_library(d + '-' + m, [genh, module_ss.sources()], + dependencies: [modulecommon, module_ss.dependencies()], pic: true) + if d == 'block' + block_mods += sl + else + softmmu_mods += sl + endif + else + if d == 'block' + block_ss.add_all(module_ss) + else + softmmu_ss.add_all(module_ss) + endif + endif + endforeach +endforeach + +nm = find_program('nm') +undefsym = find_program('scripts/undefsym.sh') +block_syms = custom_target('block.syms', output: 'block.syms', + input: [libqemuutil, block_mods], + capture: true, + command: [undefsym, nm, '@INPUT@']) +qemu_syms = custom_target('qemu.syms', output: 'qemu.syms', + input: [libqemuutil, softmmu_mods], + capture: true, + command: [undefsym, nm, '@INPUT@']) + +foreach m : block_mods + softmmu_mods + shared_module(m.name(), + name_prefix: '', + link_whole: m, + install: true, + install_dir: config_host['qemu_moddir']) +endforeach + common_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: softmmu_ss) common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: user_ss) diff --git a/rules.mak b/rules.mak index d8d35f735a..9da9dcd4f6 100644 --- a/rules.mak +++ b/rules.mak @@ -61,17 +61,17 @@ endif # This is necessary because the exectuable itself may not use the function, in # which case the function would not be linked in. Then the DSO loading will # fail because of the missing symbol. -process-archive-undefs = $(filter-out %.a %.fa %.mo,$1) \ +process-archive-undefs = $(filter-out %.a %.fa %.mo %$(DSOSUF),$1) \ $(addprefix $(WL_U), \ $(filter $(call defined-symbols,$(filter %.a %.fa, $1)), \ - $(call undefined-symbols,$(filter %.mo,$1)))) \ + $(call undefined-symbols,$(filter %.mo %$(DSOSUF),$1)))) \ $(foreach l,$(filter %.fa,$1),$(call whole-archive,$l)) \ $(filter %.a,$1) -extract-libs = $(strip $(foreach o,$(filter-out %.mo,$1),$($o-libs))) +extract-libs = $(strip $(foreach o,$(filter-out %.mo %$(DSOSUF),$1),$($o-libs))) expand-objs = $(strip $(sort $(filter %.o,$1)) \ - $(foreach o,$(filter %.mo,$1),$($o-objs)) \ - $(filter-out %.o %.mo,$1)) + $(foreach o,$(filter %.mo %$(DSOSUF),$1),$($o-objs)) \ + $(filter-out %.o %.mo %$(DSOSUF),$1)) %.o: %.c @mkdir -p $(dir $@) diff --git a/scripts/undefsym.sh b/scripts/undefsym.sh new file mode 100755 index 0000000000..b9ec332e95 --- /dev/null +++ b/scripts/undefsym.sh @@ -0,0 +1,20 @@ +#! /usr/bin/env bash + +# Before a shared module's DSO is produced, a static library is built for it +# and passed to this script. The script generates -Wl,-u options to force +# the inclusion of symbol from libqemuutil.a if the shared modules need them, +# This is necessary because the modules may use functions not needed by the +# executable itself, which would cause the function to not be linked in. +# Then the DSO loading would fail because of the missing symbol. + +if test $# -le 2; then + exit 0 +fi + +NM=$1 +staticlib=$2 +shift 2 +# Find symbols defined in static libraries and undefined in shared modules +comm -12 \ + <( $NM -P -g $staticlib | awk '$2!="U"{print "-Wl,-u," $1}' | sort -u) \ + <( $NM -P -g "$@" | awk '$2=="U"{print "-Wl,-u," $1}' | sort -u) -- cgit v1.2.3-55-g7522 From 848e8ff6779e124739261d0635b21e751dfa7eca Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 15 Jul 2019 23:18:07 +0400 Subject: meson: convert chardev directory to Meson (tools part) Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- Makefile | 1 - Makefile.objs | 4 ++-- Makefile.target | 2 +- chardev/Makefile.objs | 19 ------------------- chardev/meson.build | 32 ++++++++++++++++++++++++++++++++ meson.build | 1 + 6 files changed, 36 insertions(+), 23 deletions(-) create mode 100644 chardev/meson.build diff --git a/Makefile b/Makefile index 0ec50ee9b7..597d3c128b 100644 --- a/Makefile +++ b/Makefile @@ -182,7 +182,6 @@ include $(SRC_PATH)/Makefile.objs endif dummy := $(call unnest-vars,, \ - chardev-obj-y \ block-obj-y \ block-obj-m \ storage-daemon-obj-y \ diff --git a/Makefile.objs b/Makefile.objs index 0920cdb40c..297bd5beeb 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -7,8 +7,6 @@ qom-obj-y = qom/libqom.fa ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) -chardev-obj-y = chardev/ - authz-obj-y = authz/libauthz.fa authz/libauthz.fa-libs = $(if $(CONFIG_AUTH_PAM),-lpam) @@ -19,6 +17,8 @@ block-obj-$(CONFIG_REPLICATION) += replication.o block-obj-m = block/ +chardev-obj-y = chardev/libchardev.fa + crypto-obj-y = crypto/libcrypto.fa io-obj-y = io/libio.fa diff --git a/Makefile.target b/Makefile.target index d1d8906b4d..6b9de09df5 100644 --- a/Makefile.target +++ b/Makefile.target @@ -199,13 +199,13 @@ common-obj-m := include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ authz-obj-y \ + chardev-obj-y \ crypto-obj-y \ io-obj-y \ qom-obj-y) dummy := $(call unnest-vars,.., \ block-obj-y \ block-obj-m \ - chardev-obj-y \ common-obj-y \ common-obj-m) all-obj-y += $(common-obj-y) diff --git a/chardev/Makefile.objs b/chardev/Makefile.objs index 3783dadc4c..6662d0df41 100644 --- a/chardev/Makefile.objs +++ b/chardev/Makefile.objs @@ -1,23 +1,4 @@ -chardev-obj-y += char.o chardev-obj-$(CONFIG_SOFTMMU) += chardev-sysemu.o -chardev-obj-$(CONFIG_WIN32) += char-console.o -chardev-obj-$(CONFIG_POSIX) += char-fd.o -chardev-obj-y += char-fe.o -chardev-obj-y += char-file.o -chardev-obj-y += char-io.o -chardev-obj-y += char-mux.o -chardev-obj-y += char-null.o -chardev-obj-$(CONFIG_POSIX) += char-parallel.o -chardev-obj-y += char-pipe.o -chardev-obj-$(CONFIG_POSIX) += char-pty.o -chardev-obj-y += char-ringbuf.o -chardev-obj-y += char-serial.o -chardev-obj-y += char-socket.o -chardev-obj-y += char-stdio.o -chardev-obj-y += char-udp.o -chardev-obj-$(CONFIG_WIN32) += char-win.o -chardev-obj-$(CONFIG_WIN32) += char-win-stdio.o - common-obj-$(CONFIG_SOFTMMU) += msmouse.o wctablet.o testdev.o ifeq ($(CONFIG_BRLAPI),y) diff --git a/chardev/meson.build b/chardev/meson.build new file mode 100644 index 0000000000..9d99025a14 --- /dev/null +++ b/chardev/meson.build @@ -0,0 +1,32 @@ +chardev_ss = ss.source_set() +chardev_ss.add(files( + 'char-fe.c', + 'char-file.c', + 'char-io.c', + 'char-mux.c', + 'char-null.c', + 'char-pipe.c', + 'char-ringbuf.c', + 'char-serial.c', + 'char-socket.c', + 'char-stdio.c', + 'char-udp.c', + 'char.c', +)) +chardev_ss.add(when: 'CONFIG_POSIX', if_true: files( + 'char-fd.c', + 'char-parallel.c', + 'char-pty.c', +)) +chardev_ss.add(when: 'CONFIG_WIN32', if_true: files( + 'char-console.c', + 'char-win-stdio.c', + 'char-win.c', +)) + +chardev_ss = chardev_ss.apply(config_host, strict: false) +libchardev = static_library('chardev', chardev_ss.sources() + genh, + name_suffix: 'fa', + build_by_default: false) + +chardev = declare_dependency(link_whole: libchardev) diff --git a/meson.build b/meson.build index 13b83ea14b..b78829c116 100644 --- a/meson.build +++ b/meson.build @@ -454,6 +454,7 @@ qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) subdir('io') +subdir('chardev') subdir('fsdev') subdir('target') -- cgit v1.2.3-55-g7522 From 5e5733e5999bb10e34cbbe3eda95b3cc7ad27bde Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 29 Aug 2019 22:34:43 +0400 Subject: meson: convert block Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 8 --- Makefile.objs | 32 +++++++++--- Makefile.target | 3 +- block.c | 2 +- block/Makefile.objs | 75 ----------------------------- block/meson.build | 115 ++++++++++++++++++++++++++++++++++++++++++++ block/monitor/Makefile.objs | 2 - block/monitor/meson.build | 2 + configure | 14 ++++-- meson.build | 69 ++++++++++++++++++++++++++ nbd/Makefile.objs | 1 - nbd/meson.build | 5 ++ rules.mak | 3 +- scsi/Makefile.objs | 4 -- scsi/meson.build | 4 ++ 15 files changed, 232 insertions(+), 107 deletions(-) delete mode 100644 block/Makefile.objs create mode 100644 block/meson.build delete mode 100644 block/monitor/Makefile.objs create mode 100644 block/monitor/meson.build delete mode 100644 nbd/Makefile.objs create mode 100644 nbd/meson.build delete mode 100644 scsi/Makefile.objs create mode 100644 scsi/meson.build diff --git a/Makefile b/Makefile index 597d3c128b..ff05218353 100644 --- a/Makefile +++ b/Makefile @@ -121,7 +121,6 @@ include $(SRC_PATH)/rules.mak # lor is defined in rules.mak CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) -generated-files-y += module_block.h generated-files-y += target/s390x/gen-features.h target/s390x/gen-features.h: Makefile.ninja @@ -182,8 +181,6 @@ include $(SRC_PATH)/Makefile.objs endif dummy := $(call unnest-vars,, \ - block-obj-y \ - block-obj-m \ storage-daemon-obj-y \ storage-daemon-obj-m \ common-obj-y \ @@ -304,11 +301,6 @@ ifdef CONFIG_MPATH scsi/qemu-pr-helper$(EXESUF): LIBS += -ludev -lmultipath -lmpathpersist endif -module_block.h: $(SRC_PATH)/scripts/modules/module_block.py config-host.mak - $(call quiet-command,$(PYTHON) $< $@ \ - $(addprefix $(SRC_PATH)/,$(patsubst %.mo,%.c,$(block-obj-m))), \ - "GEN","$@") - clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files diff --git a/Makefile.objs b/Makefile.objs index 297bd5beeb..eeaa0cfa82 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -10,12 +10,20 @@ ifeq ($(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)),y) authz-obj-y = authz/libauthz.fa authz/libauthz.fa-libs = $(if $(CONFIG_AUTH_PAM),-lpam) -block-obj-y = block/ nbd/ scsi/ -block-obj-y += block.o blockjob.o job.o -block-obj-y += qemu-io-cmds.o -block-obj-$(CONFIG_REPLICATION) += replication.o - -block-obj-m = block/ +block-obj-y += libblock.fa + +libblock.fa-libs = $(ZSTD_LIBS) +libblock.fa-libs += $(LIBNFS_LIBS) +libblock.fa-libs += $(LIBISCSI_LIBS) +libblock.fa-libs += $(CURL_LIBS) +libblock.fa-libs += $(RBD_LIBS) +libblock.fa-libs += $(GLUSTERFS_LIBS) +libblock.fa-libs += $(VXHS_LIBS) +libblock.fa-libs += $(LIBSSH_LIBS) +libblock.fa-libs += $(BZIP2_LIBS) +libblock.fa-libs += $(LZFSE_LIBS) +libblock.fa-libs += $(if $(CONFIG_LINUX_AIO),-laio) +libblock.fa-libs += $(LIBXML2_LIBS) chardev-obj-y = chardev/libchardev.fa @@ -40,7 +48,7 @@ storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = blockdev.o blockdev-nbd.o block/ +common-obj-y = blockdev.o blockdev-nbd.o common-obj-y += bootdevice.o iothread.o common-obj-y += dump/ common-obj-y += job-qmp.o @@ -55,6 +63,16 @@ common-obj-$(CONFIG_LINUX) += fsdev/ common-obj-y += accel/ common-obj-y += migration/ +common-obj-$(if $(CONFIG_CURL),m) += block-curl$(DSOSUF) +common-obj-$(if $(CONFIG_GLUSTERFS),m) += block-gluster$(DSOSUF) +common-obj-$(if $(CONFIG_LIBISCSI),m) += block-iscsi$(DSOSUF) +common-obj-$(if $(CONFIG_LIBNFS),m) += block-nfs$(DSOSUF) +common-obj-$(if $(CONFIG_LIBSSH),m) += block-ssh$(DSOSUF) +common-obj-$(if $(CONFIG_RBD),m) += block-rbd$(DSOSUF) + +common-obj-$(if $(CONFIG_LZFSE),m) += block-dmg-lzfse$(DSOSUF) +common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF) + common-obj-y += audio/ common-obj-m += audio/ common-obj-y += hw/ diff --git a/Makefile.target b/Makefile.target index 6b9de09df5..c0575da132 100644 --- a/Makefile.target +++ b/Makefile.target @@ -199,13 +199,12 @@ common-obj-m := include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ authz-obj-y \ + block-obj-y \ chardev-obj-y \ crypto-obj-y \ io-obj-y \ qom-obj-y) dummy := $(call unnest-vars,.., \ - block-obj-y \ - block-obj-m \ common-obj-y \ common-obj-m) all-obj-y += $(common-obj-y) diff --git a/block.c b/block.c index d9ac0e07eb..67c5028dd8 100644 --- a/block.c +++ b/block.c @@ -29,7 +29,7 @@ #include "block/nbd.h" #include "block/qdict.h" #include "qemu/error-report.h" -#include "module_block.h" +#include "block/module_block.h" #include "qemu/main-loop.h" #include "qemu/module.h" #include "qapi/error.h" diff --git a/block/Makefile.objs b/block/Makefile.objs deleted file mode 100644 index 19c6f371c9..0000000000 --- a/block/Makefile.objs +++ /dev/null @@ -1,75 +0,0 @@ -block-obj-y += raw-format.o vmdk.o vpc.o -block-obj-$(CONFIG_QCOW1) += qcow.o -block-obj-$(CONFIG_VDI) += vdi.o -block-obj-$(CONFIG_CLOOP) += cloop.o -block-obj-$(CONFIG_BOCHS) += bochs.o -block-obj-$(CONFIG_VVFAT) += vvfat.o -block-obj-$(CONFIG_DMG) += dmg.o - -block-obj-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o qcow2-cache.o qcow2-bitmap.o qcow2-threads.o -block-obj-$(CONFIG_QED) += qed.o qed-l2-cache.o qed-table.o qed-cluster.o -block-obj-$(CONFIG_QED) += qed-check.o -block-obj-y += vhdx.o vhdx-endian.o vhdx-log.o -block-obj-y += quorum.o -block-obj-y += blkdebug.o blkverify.o blkreplay.o -block-obj-$(CONFIG_PARALLELS) += parallels.o -block-obj-y += blklogwrites.o -block-obj-y += block-backend.o snapshot.o qapi.o -block-obj-$(CONFIG_WIN32) += file-win32.o win32-aio.o -block-obj-$(CONFIG_POSIX) += file-posix.o -block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o -block-obj-$(CONFIG_LINUX_IO_URING) += io_uring.o -block-obj-y += null.o mirror.o commit.o io.o create.o amend.o -block-obj-y += throttle-groups.o -block-obj-$(CONFIG_LINUX) += nvme.o - -block-obj-y += nbd.o -block-obj-$(CONFIG_SHEEPDOG) += sheepdog.o -block-obj-$(CONFIG_LIBISCSI) += iscsi.o -block-obj-$(if $(CONFIG_LIBISCSI),y,n) += iscsi-opts.o -block-obj-$(CONFIG_LIBNFS) += nfs.o -block-obj-$(CONFIG_CURL) += curl.o -block-obj-$(CONFIG_RBD) += rbd.o -block-obj-$(CONFIG_GLUSTERFS) += gluster.o -block-obj-$(CONFIG_LIBSSH) += ssh.o -block-obj-y += accounting.o dirty-bitmap.o -block-obj-y += write-threshold.o -block-obj-y += backup.o -block-obj-$(CONFIG_REPLICATION) += replication.o -block-obj-y += throttle.o copy-on-read.o -block-obj-y += block-copy.o - -block-obj-y += crypto.o - -block-obj-y += aio_task.o -block-obj-y += backup-top.o -block-obj-y += filter-compress.o -common-obj-y += monitor/ -block-obj-y += monitor/ - -block-obj-y += stream.o - -common-obj-y += qapi-sysemu.o - -nfs.o-libs := $(LIBNFS_LIBS) -iscsi.o-cflags := $(LIBISCSI_CFLAGS) -iscsi.o-libs := $(LIBISCSI_LIBS) -curl.o-cflags := $(CURL_CFLAGS) -curl.o-libs := $(CURL_LIBS) -rbd.o-cflags := $(RBD_CFLAGS) -rbd.o-libs := $(RBD_LIBS) -gluster.o-cflags := $(GLUSTERFS_CFLAGS) -gluster.o-libs := $(GLUSTERFS_LIBS) -ssh.o-cflags := $(LIBSSH_CFLAGS) -ssh.o-libs := $(LIBSSH_LIBS) -block-obj-dmg-bz2-$(CONFIG_BZIP2) += dmg-bz2.o -block-obj-$(if $(CONFIG_DMG),m,n) += $(block-obj-dmg-bz2-y) -dmg-bz2.o-libs := $(BZIP2_LIBS) -block-obj-$(if $(CONFIG_LZFSE),m,n) += dmg-lzfse.o -dmg-lzfse.o-libs := $(LZFSE_LIBS) -qcow.o-libs := -lz -linux-aio.o-libs := -laio -io_uring.o-cflags := $(LINUX_IO_URING_CFLAGS) -io_uring.o-libs := $(LINUX_IO_URING_LIBS) -parallels.o-cflags := $(LIBXML2_CFLAGS) -parallels.o-libs := $(LIBXML2_LIBS) diff --git a/block/meson.build b/block/meson.build new file mode 100644 index 0000000000..4dbbfe60b4 --- /dev/null +++ b/block/meson.build @@ -0,0 +1,115 @@ +block_ss.add(genh) +block_ss.add(files( + 'accounting.c', + 'aio_task.c', + 'amend.c', + 'backup.c', + 'backup-top.c', + 'blkdebug.c', + 'blklogwrites.c', + 'blkreplay.c', + 'blkverify.c', + 'block-backend.c', + 'block-copy.c', + 'commit.c', + 'copy-on-read.c', + 'create.c', + 'crypto.c', + 'dirty-bitmap.c', + 'filter-compress.c', + 'io.c', + 'mirror.c', + 'nbd.c', + 'null.c', + 'qapi.c', + 'qcow2-bitmap.c', + 'qcow2-cache.c', + 'qcow2-cluster.c', + 'qcow2-refcount.c', + 'qcow2-snapshot.c', + 'qcow2-threads.c', + 'qcow2.c', + 'quorum.c', + 'raw-format.c', + 'snapshot.c', + 'throttle-groups.c', + 'throttle.c', + 'vhdx-endian.c', + 'vhdx-log.c', + 'vhdx.c', + 'vmdk.c', + 'vpc.c', + 'write-threshold.c', +), zstd) + +block_ss.add(when: [zlib, 'CONFIG_QCOW1'], if_true: files('qcow.c')) +block_ss.add(when: 'CONFIG_VDI', if_true: files('vdi.c')) +block_ss.add(when: 'CONFIG_CLOOP', if_true: files('cloop.c')) +block_ss.add(when: 'CONFIG_BOCHS', if_true: files('bochs.c')) +block_ss.add(when: 'CONFIG_VVFAT', if_true: files('vvfat.c')) +block_ss.add(when: 'CONFIG_DMG', if_true: files('dmg.c')) +block_ss.add(when: 'CONFIG_QED', if_true: files( + 'qed-check.c', + 'qed-cluster.c', + 'qed-l2-cache.c', + 'qed-table.c', + 'qed.c', +)) +block_ss.add(when: [libxml2, 'CONFIG_PARALLELS'], if_true: files('parallels.c')) +block_ss.add(when: 'CONFIG_WIN32', if_true: files('file-win32.c', 'win32-aio.c')) +block_ss.add(when: 'CONFIG_POSIX', if_true: [files('file-posix.c'), coref, iokit]) +block_ss.add(when: 'CONFIG_LIBISCSI', if_true: files('iscsi-opts.c')) +block_ss.add(when: 'CONFIG_LINUX', if_true: files('nvme.c')) +block_ss.add(when: 'CONFIG_REPLICATION', if_true: files('replication.c')) +block_ss.add(when: 'CONFIG_SHEEPDOG', if_true: files('sheepdog.c')) +block_ss.add(when: ['CONFIG_LINUX_AIO', libaio], if_true: files('linux-aio.c')) +block_ss.add(when: ['CONFIG_LINUX_IO_URING', linux_io_uring], if_true: files('io_uring.c')) + +block_modules = {} + +modsrc = [] +foreach m : [ + ['CONFIG_CURL', 'curl', [curl, glib], 'curl.c'], + ['CONFIG_GLUSTERFS', 'gluster', glusterfs, 'gluster.c'], + ['CONFIG_LIBISCSI', 'iscsi', libiscsi, 'iscsi.c'], + ['CONFIG_LIBNFS', 'nfs', libnfs, 'nfs.c'], + ['CONFIG_LIBSSH', 'ssh', libssh, 'ssh.c'], + ['CONFIG_RBD', 'rbd', rbd, 'rbd.c'], +] + if config_host.has_key(m[0]) + if enable_modules + modsrc += files(m[3]) + endif + module_ss = ss.source_set() + module_ss.add(when: m[2], if_true: files(m[3])) + block_modules += {m[1] : module_ss} + endif +endforeach + +# those are not exactly regular block modules, so treat them apart +if 'CONFIG_DMG' in config_host + foreach m : [ + ['CONFIG_LZFSE', 'dmg-lzfse', liblzfse, 'dmg-lzfse.c'], + ['CONFIG_BZIP2', 'dmg-bz2', [glib, libbzip2], 'dmg-bz2.c'] + ] + if config_host.has_key(m[0]) + module_ss = ss.source_set() + module_ss.add(when: m[2], if_true: files(m[3])) + block_modules += {m[1] : module_ss} + endif + endforeach +endif + +module_block_py = find_program('../scripts/modules/module_block.py') +module_block_h = custom_target('module_block.h', + output: 'module_block.h', + input: modsrc, + command: [module_block_py, '@OUTPUT0@', modsrc]) +block_ss.add(module_block_h) + +block_ss.add(files('stream.c')) + +softmmu_ss.add(files('qapi-sysemu.c')) +subdir('monitor') + +modules += {'block': block_modules} diff --git a/block/monitor/Makefile.objs b/block/monitor/Makefile.objs deleted file mode 100644 index 39acf85022..0000000000 --- a/block/monitor/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -common-obj-y += block-hmp-cmds.o -block-obj-y += bitmap-qmp-cmds.o diff --git a/block/monitor/meson.build b/block/monitor/meson.build new file mode 100644 index 0000000000..374aac1140 --- /dev/null +++ b/block/monitor/meson.build @@ -0,0 +1,2 @@ +softmmu_ss.add(files('block-hmp-cmds.c')) +block_ss.add(files('bitmap-qmp-cmds.c')) diff --git a/configure b/configure index fe79cb131e..16cf5cb5be 100755 --- a/configure +++ b/configure @@ -2692,8 +2692,6 @@ if test "$zstd" != "no" ; then if $pkg_config --atleast-version=$libzstd_minver libzstd ; then zstd_cflags="$($pkg_config --cflags libzstd)" zstd_libs="$($pkg_config --libs libzstd)" - LIBS="$zstd_libs $LIBS" - QEMU_CFLAGS="$QEMU_CFLAGS $zstd_cflags" zstd="yes" else if test "$zstd" = "yes" ; then @@ -4111,7 +4109,8 @@ if test "$zlib" != "no" ; then int main(void) { zlibVersion(); return 0; } EOF if compile_prog "" "-lz" ; then - LIBS="$LIBS -lz" + zlib_libs=-lz + LIBS="$LIBS $zlib_libs" else error_exit "zlib check failed" \ "Make sure to have the zlib libs and headers installed." @@ -7396,7 +7395,11 @@ fi if test "$posix_memalign" = "yes" ; then echo "CONFIG_POSIX_MEMALIGN=y" >> $config_host_mak fi - +if test "$zlib" != "no" ; then + echo "CONFIG_ZLIB=y" >> $config_host_mak + echo "ZLIB_CFLAGS=$zlib_cflags" >> $config_host_mak + echo "ZLIB_LIBS=$zlib_libs" >> $config_host_mak +fi if test "$spice" = "yes" ; then echo "CONFIG_SPICE=y" >> $config_host_mak fi @@ -7466,6 +7469,8 @@ fi if test "$zstd" = "yes" ; then echo "CONFIG_ZSTD=y" >> $config_host_mak + echo "ZSTD_CFLAGS=$zstd_cflags" >> $config_host_mak + echo "ZSTD_LIBS=$zstd_libs" >> $config_host_mak fi if test "$libiscsi" = "yes" ; then @@ -7498,7 +7503,6 @@ if test "$qom_cast_debug" = "yes" ; then fi if test "$rbd" = "yes" ; then echo "CONFIG_RBD=m" >> $config_host_mak - echo "RBD_CFLAGS=$rbd_cflags" >> $config_host_mak echo "RBD_LIBS=$rbd_libs" >> $config_host_mak fi diff --git a/meson.build b/meson.build index b78829c116..1d301948b7 100644 --- a/meson.build +++ b/meson.build @@ -109,6 +109,26 @@ pam = not_found if 'CONFIG_AUTH_PAM' in config_host pam = cc.find_library('pam') endif +libaio = cc.find_library('aio', required: false) +zlib = not_found +if 'CONFIG_ZLIB' in config_host + zlib = declare_dependency(compile_args: config_host['ZLIB_CFLAGS'].split(), + link_args: config_host['ZLIB_LIBS'].split()) +endif +linux_io_uring = not_found +if 'CONFIG_LINUX_IO_URING' in config_host + linux_io_uring = declare_dependency(compile_args: config_host['LINUX_IO_URING_CFLAGS'].split(), + link_args: config_host['LINUX_IO_URING_LIBS'].split()) +endif +libxml2 = not_found +if 'CONFIG_LIBXML2' in config_host + libxml2 = declare_dependency(compile_args: config_host['LIBXML2_CFLAGS'].split(), + link_args: config_host['LIBXML2_LIBS'].split()) +endif +libnfs = not_found +if 'CONFIG_LIBNFS' in config_host + libnfs = declare_dependency(link_args: config_host['LIBNFS_LIBS'].split()) +endif libattr = not_found if 'CONFIG_ATTR' in config_host libattr = declare_dependency(link_args: config_host['LIBATTR_LIBS'].split()) @@ -133,6 +153,11 @@ if 'CONFIG_LIBISCSI' in config_host libiscsi = declare_dependency(compile_args: config_host['LIBISCSI_CFLAGS'].split(), link_args: config_host['LIBISCSI_LIBS'].split()) endif +zstd = not_found +if 'CONFIG_ZSTD' in config_host + zstd = declare_dependency(compile_args: config_host['ZSTD_CFLAGS'].split(), + link_args: config_host['ZSTD_LIBS'].split()) +endif gbm = not_found if 'CONFIG_GBM' in config_host gbm = declare_dependency(compile_args: config_host['GBM_CFLAGS'].split(), @@ -152,6 +177,28 @@ libudev = not_found if 'CONFIG_LIBUDEV' in config_host libudev = declare_dependency(link_args: config_host['LIBUDEV_LIBS'].split()) endif +rbd = not_found +if 'CONFIG_RBD' in config_host + rbd = declare_dependency(link_args: config_host['RBD_LIBS'].split()) +endif +glusterfs = not_found +if 'CONFIG_GLUSTERFS' in config_host + glusterfs = declare_dependency(compile_args: config_host['GLUSTERFS_CFLAGS'].split(), + link_args: config_host['GLUSTERFS_LIBS'].split()) +endif +libssh = not_found +if 'CONFIG_LIBSSH' in config_host + libssh = declare_dependency(compile_args: config_host['LIBSSH_CFLAGS'].split(), + link_args: config_host['LIBSSH_LIBS'].split()) +endif +libbzip2 = not_found +if 'CONFIG_BZIP2' in config_host + libbzip2 = declare_dependency(link_args: config_host['BZIP2_LIBS'].split()) +endif +liblzfse = not_found +if 'CONFIG_LZFSE' in config_host + liblzfse = declare_dependency(link_args: config_host['LZFSE_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -458,6 +505,18 @@ subdir('chardev') subdir('fsdev') subdir('target') +block_ss.add(files( + 'block.c', + 'blockjob.c', + 'job.c', + 'qemu-io-cmds.c', +)) +block_ss.add(when: 'CONFIG_REPLICATION', if_true: files('replication.c')) + +subdir('nbd') +subdir('scsi') +subdir('block') + block_mods = [] softmmu_mods = [] foreach d, list : modules @@ -492,6 +551,16 @@ qemu_syms = custom_target('qemu.syms', output: 'qemu.syms', capture: true, command: [undefsym, nm, '@INPUT@']) +block_ss = block_ss.apply(config_host, strict: false) +libblock = static_library('block', block_ss.sources() + genh, + dependencies: block_ss.dependencies(), + link_depends: block_syms, + name_suffix: 'fa', + build_by_default: false) + +block = declare_dependency(link_whole: [libblock], + link_args: '@block.syms') + foreach m : block_mods + softmmu_mods shared_module(m.name(), name_prefix: '', diff --git a/nbd/Makefile.objs b/nbd/Makefile.objs deleted file mode 100644 index eb3dd4461d..0000000000 --- a/nbd/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -block-obj-y += server.o client.o common.o diff --git a/nbd/meson.build b/nbd/meson.build new file mode 100644 index 0000000000..0c00a776d3 --- /dev/null +++ b/nbd/meson.build @@ -0,0 +1,5 @@ +block_ss.add(files( + 'client.c', + 'common.c', + 'server.c', +)) diff --git a/rules.mak b/rules.mak index 9da9dcd4f6..8285fe529a 100644 --- a/rules.mak +++ b/rules.mak @@ -374,8 +374,7 @@ define unnest-vars # Find all the .mo objects in variables and add dependency rules # according to .mo-objs. Report error if not set $(if $($o-objs), - $(eval $(o:%.mo=%$(DSOSUF)): module-common.o $($o-objs)), - $(error $o added in $v but $o-objs is not set))) + $(eval $(o:%.mo=%$(DSOSUF)): module-common.o $($o-objs)))) $(shell mkdir -p ./ $(sort $(dir $($v)))) # Include all the .d files $(eval -include $(patsubst %.o,%.d,$(patsubst %.mo,%.d,$(filter %.o,$($v))))) diff --git a/scsi/Makefile.objs b/scsi/Makefile.objs deleted file mode 100644 index bb8789cd8b..0000000000 --- a/scsi/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -block-obj-y += utils.o - -block-obj-$(CONFIG_LINUX) += pr-manager.o pr-manager-helper.o -block-obj-$(call lnot,$(CONFIG_LINUX)) += pr-manager-stub.o diff --git a/scsi/meson.build b/scsi/meson.build new file mode 100644 index 0000000000..53f3a1f716 --- /dev/null +++ b/scsi/meson.build @@ -0,0 +1,4 @@ +block_ss.add(files('utils.c')) +block_ss.add(when: 'CONFIG_LINUX', + if_true: files('pr-manager.c', 'pr-manager-helper.c'), + if_false: files('pr-manager-stub.c')) -- cgit v1.2.3-55-g7522 From b7c70bf2c521c85e2ec575705465e657a6f412c4 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 21:37:25 +0400 Subject: meson: qemu-{img,io,nbd} Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 5 ----- configure | 3 +-- meson.build | 14 ++++++++++++-- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index ff05218353..316846f6e7 100644 --- a/Makefile +++ b/Makefile @@ -289,11 +289,6 @@ Makefile: $(version-obj-y) COMMON_LDADDS = libqemuutil.a -qemu-img.o: qemu-img-cmds.h - -qemu-img$(EXESUF): qemu-img.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) -qemu-nbd$(EXESUF): qemu-nbd.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) -qemu-io$(EXESUF): qemu-io.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) scsi/qemu-pr-helper$(EXESUF): scsi/qemu-pr-helper.o scsi/utils.o $(authz-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) diff --git a/configure b/configure index 16cf5cb5be..ac0e59fa5e 100755 --- a/configure +++ b/configure @@ -6719,9 +6719,8 @@ fi tools="" helpers="" if test "$want_tools" = "yes" ; then - tools="qemu-img\$(EXESUF) qemu-io\$(EXESUF) $tools" if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then - tools="qemu-nbd\$(EXESUF) qemu-storage-daemon\$(EXESUF) $tools" + tools="qemu-storage-daemon\$(EXESUF) $tools" fi fi if test "$softmmu" = yes ; then diff --git a/meson.build b/meson.build index 1d301948b7..7f753afc6e 100644 --- a/meson.build +++ b/meson.build @@ -350,7 +350,7 @@ if have_system ] endif foreach d : hx_headers - custom_target(d[1], + hxdep += custom_target(d[1], input: files(d[0]), output: d[1], capture: true, @@ -559,7 +559,8 @@ libblock = static_library('block', block_ss.sources() + genh, build_by_default: false) block = declare_dependency(link_whole: [libblock], - link_args: '@block.syms') + link_args: '@block.syms', + dependencies: [crypto, io]) foreach m : block_mods + softmmu_mods shared_module(m.name(), @@ -637,6 +638,15 @@ if 'CONFIG_GUEST_AGENT' in config_host endif if have_tools + qemu_img = executable('qemu-img', [files('qemu-img.c'), hxdep], + dependencies: [authz, block, crypto, io, qom, qemuutil], install: true) + qemu_io = executable('qemu-io', files('qemu-io.c'), + dependencies: [block, qemuutil], install: true) + if targetos == 'linux' or targetos == 'sunos' or targetos.endswith('bsd') + qemu_nbd = executable('qemu-nbd', files('qemu-nbd.c'), + dependencies: [block, qemuutil], install: true) + endif + subdir('contrib/rdmacm-mux') subdir('contrib/elf2dmp') -- cgit v1.2.3-55-g7522 From 897b5afae57bbfa2af928a8c381465209d178e5b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 21:54:15 +0400 Subject: meson: qemu-pr-helper The executable moves back from libexecdir to bindir, when it was in 5.0 and earlier. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 7 +------ configure | 3 --- meson.build | 10 ++++++++++ 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 316846f6e7..14ad17103c 100644 --- a/Makefile +++ b/Makefile @@ -138,7 +138,7 @@ $(call set-vpath, $(SRC_PATH)) LIBS+=-lz $(LIBS_TOOLS) -HELPERS-y = $(HELPERS) +HELPERS-y = # Sphinx does not allow building manuals into the same directory as # the source files, so if we're doing an in-tree QEMU build we must @@ -291,11 +291,6 @@ COMMON_LDADDS = libqemuutil.a qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) -scsi/qemu-pr-helper$(EXESUF): scsi/qemu-pr-helper.o scsi/utils.o $(authz-obj-y) $(crypto-obj-y) $(io-obj-y) $(qom-obj-y) $(COMMON_LDADDS) -ifdef CONFIG_MPATH -scsi/qemu-pr-helper$(EXESUF): LIBS += -ludev -lmultipath -lmpathpersist -endif - clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files diff --git a/configure b/configure index ac0e59fa5e..97cdd48dc4 100755 --- a/configure +++ b/configure @@ -6717,7 +6717,6 @@ if [ "$eventfd" = "yes" ]; then fi tools="" -helpers="" if test "$want_tools" = "yes" ; then if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then tools="qemu-storage-daemon\$(EXESUF) $tools" @@ -6741,7 +6740,6 @@ if test "$softmmu" = yes ; then fi mpath=no fi - helpers="$helpers scsi/qemu-pr-helper\$(EXESUF)" else if test "$virtfs" = yes; then error_exit "VirtFS is supported only on Linux" @@ -7819,7 +7817,6 @@ else QEMU_INCLUDES="-iquote ${source_path}/tcg/${ARCH} $QEMU_INCLUDES" fi -echo "HELPERS=$helpers" >> $config_host_mak echo "TOOLS=$tools" >> $config_host_mak echo "ROMS=$roms" >> $config_host_mak echo "MAKE=$make" >> $config_host_mak diff --git a/meson.build b/meson.build index 7f753afc6e..3a8cf11edc 100644 --- a/meson.build +++ b/meson.build @@ -148,6 +148,10 @@ if 'CONFIG_XKBCOMMON' in config_host link_args: config_host['XKBCOMMON_LIBS'].split()) endif rt = cc.find_library('rt', required: false) +libmpathpersist = not_found +if config_host.has_key('CONFIG_MPATH') + libmpathpersist = cc.find_library('mpathpersist') +endif libiscsi = not_found if 'CONFIG_LIBISCSI' in config_host libiscsi = declare_dependency(compile_args: config_host['LIBISCSI_CFLAGS'].split(), @@ -633,6 +637,7 @@ foreach target : target_dirs endforeach # Other build targets + if 'CONFIG_GUEST_AGENT' in config_host subdir('qga') endif @@ -674,6 +679,11 @@ if have_tools dependencies: [qemuutil, libcap_ng], install: true, install_dir: get_option('libexecdir')) + + executable('qemu-pr-helper', files('scsi/qemu-pr-helper.c', 'scsi/utils.c'), + dependencies: [authz, crypto, io, qom, qemuutil, + libcap_ng, libudev, libmpathpersist], + install: true) endif if 'CONFIG_IVSHMEM' in config_host -- cgit v1.2.3-55-g7522 From c3a0ee847a571095fa3c81c4c5352f85f42d9fb6 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 18 Jul 2019 13:21:28 +0200 Subject: configure, Makefile; remove TOOLS and HELPERS-y variable Everything involving tools is now done by meson. Signed-off-by: Paolo Bonzini --- Makefile | 22 ++-------------------- configure | 7 ------- 2 files changed, 2 insertions(+), 27 deletions(-) diff --git a/Makefile b/Makefile index 14ad17103c..cb364f4167 100644 --- a/Makefile +++ b/Makefile @@ -138,8 +138,6 @@ $(call set-vpath, $(SRC_PATH)) LIBS+=-lz $(LIBS_TOOLS) -HELPERS-y = - # Sphinx does not allow building manuals into the same directory as # the source files, so if we're doing an in-tree QEMU build we must # build the manuals into a subdirectory (and then install them from @@ -188,7 +186,7 @@ dummy := $(call unnest-vars,, \ include $(SRC_PATH)/tests/Makefile.include -all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) $(TOOLS) $(HELPERS-y) recurse-all modules +all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) recurse-all modules config-host.h: config-host.h-timestamp config-host.h-timestamp: config-host.mak @@ -300,7 +298,7 @@ clean: recurse-clean ninja-clean clean-ctlist ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-arm.a \ ! -path ./roms/edk2/BaseTools/Source/Python/UPT/Dll/sqlite3.dll \ -exec rm {} + - rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) TAGS cscope.* *.pod *~ */*~ + rm -f TAGS cscope.* *.pod *~ */*~ rm -f fsdev/*.pod scsi/*.pod rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) @@ -452,12 +450,6 @@ export DESTDIR install: all $(if $(BUILD_DOCS),install-doc) \ install-datadir install-localstatedir install-includedir \ recurse-install -ifneq ($(TOOLS),) - $(call install-prog,$(TOOLS),$(DESTDIR)$(bindir)) -endif -ifneq ($(HELPERS-y),) - $(call install-prog,$(HELPERS-y),$(DESTDIR)$(libexecdir)) -endif ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_PROG) "scripts/qemu-trace-stap" $(DESTDIR)$(bindir) endif @@ -717,16 +709,6 @@ endif $(call print-help-run,$(t)/fuzz,Build fuzzer for $(t)); \ ))) \ echo '') - @$(if $(HELPERS-y), \ - echo 'Helper targets:'; \ - $(foreach t, $(HELPERS-y), \ - $(call print-help-run,$(t),Build $(shell basename $(t)));) \ - echo '') - @$(if $(TOOLS), \ - echo 'Tools targets:'; \ - $(foreach t, $(TOOLS), \ - $(call print-help-run,$(t),Build $(shell basename $(t)) tool);) \ - echo '') @echo 'Cleaning targets:' $(call print-help,clean,Remove most generated files but keep the config) $(call print-help,distclean,Remove all generated files) diff --git a/configure b/configure index 97cdd48dc4..a8f7c912da 100755 --- a/configure +++ b/configure @@ -6716,12 +6716,6 @@ if [ "$eventfd" = "yes" ]; then ivshmem=yes fi -tools="" -if test "$want_tools" = "yes" ; then - if [ "$linux" = "yes" -o "$bsd" = "yes" -o "$solaris" = "yes" ] ; then - tools="qemu-storage-daemon\$(EXESUF) $tools" - fi -fi if test "$softmmu" = yes ; then if test "$linux" = yes; then if test "$virtfs" != no && test "$cap_ng" = yes && test "$attr" = yes ; then @@ -7817,7 +7811,6 @@ else QEMU_INCLUDES="-iquote ${source_path}/tcg/${ARCH} $QEMU_INCLUDES" fi -echo "TOOLS=$tools" >> $config_host_mak echo "ROMS=$roms" >> $config_host_mak echo "MAKE=$make" >> $config_host_mak echo "INSTALL=$install" >> $config_host_mak -- cgit v1.2.3-55-g7522 From 2634733c6bfcb803a6b8f107a8ed1f3c598b0a47 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Jul 2019 15:40:07 +0200 Subject: meson: convert chardev directory to Meson (emulator part) Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 -- Makefile.target | 2 ++ chardev/Makefile.objs | 10 ---------- chardev/meson.build | 13 +++++++++++++ configure | 2 ++ meson.build | 14 ++++++++++++++ 6 files changed, 31 insertions(+), 12 deletions(-) delete mode 100644 chardev/Makefile.objs diff --git a/Makefile.objs b/Makefile.objs index eeaa0cfa82..e43526fe5f 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -87,8 +87,6 @@ common-obj-y += dma-helpers.o common-obj-$(CONFIG_TPM) += tpm.o common-obj-y += backends/ -common-obj-y += chardev/ -common-obj-m += chardev/ common-obj-$(CONFIG_SECCOMP) += qemu-seccomp.o qemu-seccomp.o-cflags := $(SECCOMP_CFLAGS) diff --git a/Makefile.target b/Makefile.target index c0575da132..c8c4b70162 100644 --- a/Makefile.target +++ b/Makefile.target @@ -104,6 +104,7 @@ all: $(PROGS) stap @true obj-y += $(LIBQEMU) + obj-y += trace/ ######################################################### @@ -167,6 +168,7 @@ LIBS := $(LIBS) @../block.syms @../qemu.syms ifneq ($(CONFIG_MODULES),y) LIBS := $(LIBS) endif +LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) # Hardware support ifeq ($(TARGET_NAME), sparc64) diff --git a/chardev/Makefile.objs b/chardev/Makefile.objs deleted file mode 100644 index 6662d0df41..0000000000 --- a/chardev/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -chardev-obj-$(CONFIG_SOFTMMU) += chardev-sysemu.o -common-obj-$(CONFIG_SOFTMMU) += msmouse.o wctablet.o testdev.o - -ifeq ($(CONFIG_BRLAPI),y) -common-obj-m += baum.o -baum.o-cflags := $(SDL_CFLAGS) -baum.o-libs := $(BRLAPI_LIBS) -endif - -common-obj-$(CONFIG_SPICE) += spice.o diff --git a/chardev/meson.build b/chardev/meson.build index 9d99025a14..02f914d6c0 100644 --- a/chardev/meson.build +++ b/chardev/meson.build @@ -30,3 +30,16 @@ libchardev = static_library('chardev', chardev_ss.sources() + genh, build_by_default: false) chardev = declare_dependency(link_whole: libchardev) + +softmmu_ss.add(files('chardev-sysemu.c', 'msmouse.c', 'wctablet.c', 'testdev.c')) +softmmu_ss.add(when: ['CONFIG_SPICE', spice], if_true: files('spice.c')) + +chardev_modules = {} + +if config_host.has_key('CONFIG_BRLAPI') and config_host.has_key('CONFIG_SDL') + module_ss = ss.source_set() + module_ss.add(when: [sdl, brlapi], if_true: files('baum.c')) + chardev_modules += { 'brlapi': module_ss } +endif + +modules += { 'chardev': chardev_modules } diff --git a/configure b/configure index a8f7c912da..68cf306ce8 100755 --- a/configure +++ b/configure @@ -7393,6 +7393,8 @@ if test "$zlib" != "no" ; then fi if test "$spice" = "yes" ; then echo "CONFIG_SPICE=y" >> $config_host_mak + echo "SPICE_CFLAGS=$spice_cflags" >> $config_host_mak + echo "SPICE_LIBS=$spice_libs" >> $config_host_mak fi if test "$smartcard" = "yes" ; then diff --git a/meson.build b/meson.build index 3a8cf11edc..d3b74868e2 100644 --- a/meson.build +++ b/meson.build @@ -147,6 +147,11 @@ if 'CONFIG_XKBCOMMON' in config_host xkbcommon = declare_dependency(compile_args: config_host['XKBCOMMON_CFLAGS'].split(), link_args: config_host['XKBCOMMON_LIBS'].split()) endif +spice = not_found +if 'CONFIG_SPICE' in config_host + spice = declare_dependency(compile_args: config_host['SPICE_CFLAGS'].split(), + link_args: config_host['SPICE_LIBS'].split()) +endif rt = cc.find_library('rt', required: false) libmpathpersist = not_found if config_host.has_key('CONFIG_MPATH') @@ -181,6 +186,15 @@ libudev = not_found if 'CONFIG_LIBUDEV' in config_host libudev = declare_dependency(link_args: config_host['LIBUDEV_LIBS'].split()) endif +brlapi = not_found +if 'CONFIG_BRLAPI' in config_host + brlapi = declare_dependency(link_args: config_host['BRLAPI_LIBS'].split()) +endif +sdl = not_found +if 'CONFIG_SDL' in config_host + sdl = declare_dependency(compile_args: config_host['SDL_CFLAGS'].split(), + link_args: config_host['SDL_LIBS'].split()) +endif rbd = not_found if 'CONFIG_RBD' in config_host rbd = declare_dependency(link_args: config_host['RBD_LIBS'].split()) -- cgit v1.2.3-55-g7522 From a2ce7dbd917a18408cf4bfd132578b46c2752a72 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Aug 2020 20:00:40 +0200 Subject: meson: convert tests/qtest to meson Signed-off-by: Paolo Bonzini --- meson.build | 3 + tests/Makefile.include | 47 +- tests/meson.build | 1 + tests/qtest/Makefile.include | 332 ---------- tests/qtest/ac97-test.c | 2 +- tests/qtest/acpi-utils.h | 2 +- tests/qtest/ahci-test.c | 2 +- tests/qtest/arm-cpu-features.c | 2 +- tests/qtest/boot-order-test.c | 2 +- tests/qtest/boot-sector.c | 2 +- tests/qtest/boot-sector.h | 2 +- tests/qtest/boot-serial-test.c | 2 +- tests/qtest/cdrom-test.c | 2 +- tests/qtest/dbus-vmstate-test.c | 2 +- tests/qtest/device-introspect-test.c | 2 +- tests/qtest/device-plug-test.c | 2 +- tests/qtest/drive_del-test.c | 2 +- tests/qtest/ds1338-test.c | 2 +- tests/qtest/e1000-test.c | 2 +- tests/qtest/eepro100-test.c | 2 +- tests/qtest/endianness-test.c | 2 +- tests/qtest/es1370-test.c | 2 +- tests/qtest/fuzz/fuzz.c | 2 +- tests/qtest/fuzz/fuzz.h | 2 +- tests/qtest/fuzz/i440fx_fuzz.c | 2 +- tests/qtest/fuzz/qos_fuzz.c | 2 +- tests/qtest/fuzz/virtio_net_fuzz.c | 2 +- tests/qtest/fw_cfg-test.c | 2 +- tests/qtest/hd-geo-test.c | 2 +- tests/qtest/hexloader-test.c | 2 +- tests/qtest/ide-test.c | 2 +- tests/qtest/ipoctal232-test.c | 2 +- tests/qtest/ivshmem-test.c | 2 +- tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c | 4 +- tests/qtest/libqos/ahci.c | 6 +- tests/qtest/libqos/ahci.h | 6 +- tests/qtest/libqos/arm-imx25-pdk-machine.c | 6 +- tests/qtest/libqos/arm-n800-machine.c | 6 +- tests/qtest/libqos/arm-raspi2-machine.c | 4 +- tests/qtest/libqos/arm-sabrelite-machine.c | 4 +- tests/qtest/libqos/arm-smdkc210-machine.c | 4 +- tests/qtest/libqos/arm-virt-machine.c | 6 +- tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c | 4 +- tests/qtest/libqos/e1000e.c | 6 +- tests/qtest/libqos/e1000e.h | 2 +- tests/qtest/libqos/fw_cfg.c | 2 +- tests/qtest/libqos/i2c-imx.c | 2 +- tests/qtest/libqos/i2c-omap.c | 2 +- tests/qtest/libqos/i2c.c | 2 +- tests/qtest/libqos/i2c.h | 2 +- tests/qtest/libqos/libqos-pc.c | 6 +- tests/qtest/libqos/libqos-pc.h | 2 +- tests/qtest/libqos/libqos-spapr.c | 6 +- tests/qtest/libqos/libqos-spapr.h | 2 +- tests/qtest/libqos/libqos.c | 4 +- tests/qtest/libqos/libqos.h | 4 +- tests/qtest/libqos/libqtest.h | 736 +++++++++++++++++++++++ tests/qtest/libqos/malloc-pc.c | 4 +- tests/qtest/libqos/malloc-pc.h | 2 +- tests/qtest/libqos/malloc-spapr.c | 2 +- tests/qtest/libqos/malloc-spapr.h | 2 +- tests/qtest/libqos/malloc.c | 2 +- tests/qtest/libqos/meson.build | 57 ++ tests/qtest/libqos/pci-pc.c | 2 +- tests/qtest/libqos/pci-pc.h | 6 +- tests/qtest/libqos/pci-spapr.c | 6 +- tests/qtest/libqos/pci-spapr.h | 6 +- tests/qtest/libqos/pci.c | 4 +- tests/qtest/libqos/pci.h | 2 +- tests/qtest/libqos/ppc64_pseries-machine.c | 4 +- tests/qtest/libqos/qgraph.c | 4 +- tests/qtest/libqos/qgraph.h | 6 +- tests/qtest/libqos/qgraph_internal.h | 4 +- tests/qtest/libqos/qos_external.c | 8 +- tests/qtest/libqos/qos_external.h | 4 +- tests/qtest/libqos/rtas.c | 2 +- tests/qtest/libqos/rtas.h | 2 +- tests/qtest/libqos/sdhci.c | 2 +- tests/qtest/libqos/sdhci.h | 2 +- tests/qtest/libqos/tpci200.c | 4 +- tests/qtest/libqos/usb.c | 2 +- tests/qtest/libqos/usb.h | 2 +- tests/qtest/libqos/virtio-9p.c | 4 +- tests/qtest/libqos/virtio-9p.h | 6 +- tests/qtest/libqos/virtio-balloon.c | 4 +- tests/qtest/libqos/virtio-balloon.h | 6 +- tests/qtest/libqos/virtio-blk.c | 4 +- tests/qtest/libqos/virtio-blk.h | 6 +- tests/qtest/libqos/virtio-mmio.c | 8 +- tests/qtest/libqos/virtio-mmio.h | 4 +- tests/qtest/libqos/virtio-net.c | 4 +- tests/qtest/libqos/virtio-net.h | 6 +- tests/qtest/libqos/virtio-pci.c | 14 +- tests/qtest/libqos/virtio-pci.h | 6 +- tests/qtest/libqos/virtio-rng.c | 4 +- tests/qtest/libqos/virtio-rng.h | 6 +- tests/qtest/libqos/virtio-scsi.c | 4 +- tests/qtest/libqos/virtio-scsi.h | 6 +- tests/qtest/libqos/virtio-serial.c | 4 +- tests/qtest/libqos/virtio-serial.h | 6 +- tests/qtest/libqos/virtio.c | 2 +- tests/qtest/libqos/virtio.h | 2 +- tests/qtest/libqos/x86_64_pc-machine.c | 2 +- tests/qtest/libqtest-single.h | 2 +- tests/qtest/libqtest.c | 2 +- tests/qtest/libqtest.h | 736 ----------------------- tests/qtest/m48t59-test.c | 2 +- tests/qtest/machine-none-test.c | 2 +- tests/qtest/megasas-test.c | 2 +- tests/qtest/meson.build | 257 ++++++++ tests/qtest/microbit-test.c | 2 +- tests/qtest/migration-helpers.h | 2 +- tests/qtest/migration-test.c | 4 +- tests/qtest/modules-test.c | 2 +- tests/qtest/ne2000-test.c | 2 +- tests/qtest/numa-test.c | 2 +- tests/qtest/nvme-test.c | 2 +- tests/qtest/pca9552-test.c | 2 +- tests/qtest/pci-test.c | 2 +- tests/qtest/pcnet-test.c | 2 +- tests/qtest/pflash-cfi02-test.c | 2 +- tests/qtest/pnv-xscom-test.c | 2 +- tests/qtest/prom-env-test.c | 2 +- tests/qtest/pvpanic-test.c | 2 +- tests/qtest/pxe-test.c | 2 +- tests/qtest/q35-test.c | 2 +- tests/qtest/qmp-cmd-test.c | 2 +- tests/qtest/qmp-test.c | 2 +- tests/qtest/qom-test.c | 2 +- tests/qtest/rtas-test.c | 2 +- tests/qtest/sdhci-test.c | 2 +- tests/qtest/spapr-phb-test.c | 2 +- tests/qtest/tco-test.c | 2 +- tests/qtest/test-filter-mirror.c | 2 +- tests/qtest/test-filter-redirector.c | 2 +- tests/qtest/test-hmp.c | 2 +- tests/qtest/tpm-crb-swtpm-test.c | 2 +- tests/qtest/tpm-tis-device-swtpm-test.c | 2 +- tests/qtest/tpm-tis-swtpm-test.c | 2 +- tests/qtest/tpm-util.c | 2 +- tests/qtest/tulip-test.c | 2 +- tests/qtest/virtio-rng-test.c | 2 +- tests/qtest/virtio-test.c | 2 +- tests/qtest/vmgenid-test.c | 2 +- tests/qtest/vmxnet3-test.c | 2 +- tests/qtest/wdt_ib700-test.c | 2 +- tests/test-qga.c | 2 +- tests/test-qgraph.c | 5 +- 148 files changed, 1277 insertions(+), 1325 deletions(-) delete mode 100644 tests/qtest/Makefile.include create mode 100644 tests/qtest/libqos/libqtest.h create mode 100644 tests/qtest/libqos/meson.build delete mode 100644 tests/qtest/libqtest.h create mode 100644 tests/qtest/meson.build diff --git a/meson.build b/meson.build index d3b74868e2..99daa91666 100644 --- a/meson.build +++ b/meson.build @@ -535,6 +535,9 @@ subdir('nbd') subdir('scsi') subdir('block') +# needed for fuzzing binaries +subdir('tests/qtest/libqos') + block_mods = [] softmmu_mods = [] foreach d, list : modules diff --git a/tests/Makefile.include b/tests/Makefile.include index 02d31fbe0c..99fb5132f7 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -109,6 +109,7 @@ check-unit-y += tests/test-qht$(EXESUF) check-unit-y += tests/test-qht-par$(EXESUF) check-unit-y += tests/test-bitops$(EXESUF) check-unit-y += tests/test-bitcnt$(EXESUF) +check-unit-y += tests/test-qgraph$(EXESUF) check-unit-y += tests/check-qom-interface$(EXESUF) check-unit-y += tests/check-qom-proplist$(EXESUF) check-unit-y += tests/test-qemu-opts$(EXESUF) @@ -306,19 +307,6 @@ tests/test-qapi-gen-timestamp: \ @rm -f tests/test-qapi-doc.texi @>$@ -tests/qtest/dbus-vmstate1.h tests/qtest/dbus-vmstate1.c: tests/qtest/dbus-vmstate1-gen-timestamp ; -tests/qtest/dbus-vmstate1-gen-timestamp: $(SRC_PATH)/tests/qtest/dbus-vmstate1.xml - $(call quiet-command,$(GDBUS_CODEGEN) $< \ - --interface-prefix org.qemu --generate-c-code tests/qtest/dbus-vmstate1, \ - "GEN","$(@:%-timestamp=%)") - @>$@ - -tests/qtest/dbus-vmstate-test.o-cflags := -DSRCDIR="$(SRC_PATH)" -tests/qtest/dbus-vmstate1.o-cflags := $(GIO_CFLAGS) -tests/qtest/dbus-vmstate1.o-libs := $(GIO_LIBS) - -tests/qtest/dbus-vmstate-test.o: tests/qtest/dbus-vmstate1.h - tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y) tests/test-qapi-emit-events.o tests/test-qapi-events.o @@ -333,6 +321,7 @@ tests/test-shift128$(EXESUF): tests/test-shift128.o $(test-util-obj-y) tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y) tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y) tests/test-bitcnt$(EXESUF): tests/test-bitcnt.o $(test-util-obj-y) +tests/test-qgraph$(EXESUF): tests/test-qgraph.o tests/qtest/libqos/qgraph.o $(test-util-obj-y) tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y) tests/benchmark-crypto-hash$(EXESUF): tests/benchmark-crypto-hash.o $(test-crypto-obj-y) tests/test-crypto-hmac$(EXESUF): tests/test-crypto-hmac.o $(test-crypto-obj-y) @@ -396,10 +385,8 @@ tests/migration/initrd-stress.img: tests/migration/stress$(EXESUF) rm $(INITRD_WORK_DIR)/init rmdir $(INITRD_WORK_DIR) -include $(SRC_PATH)/tests/qtest/Makefile.include - tests/test-qga$(EXESUF): qga/qemu-ga$(EXESUF) -tests/test-qga$(EXESUF): tests/test-qga.o $(qtest-obj-y) +tests/test-qga$(EXESUF): tests/test-qga.o tests/qtest/libqtest.o $(test-util-obj-y) tests/vhost-user-bridge$(EXESUF): tests/vhost-user-bridge.o $(test-util-obj-y) libvhost-user.a tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o @@ -440,14 +427,6 @@ define do_test_tap "TAP","$@") endef -.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS)) -$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: %-softmmu/all $(check-qtest-y) - $(call do_test_human,$(check-qtest-$*-y:%=tests/qtest/%$(EXESUF)) $(check-qtest-generic-y:%=tests/qtest/%$(EXESUF)), \ - QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ - QTEST_QEMU_IMG=qemu-img$(EXESUF)) - -build-qtest: $(patsubst %, %-softmmu/all, $(QTEST_TARGETS)) $(check-qtest-y) - build-unit: $(check-unit-y) check-unit: $(check-unit-y) @@ -458,18 +437,9 @@ check-speed: $(check-speed-y) # gtester tests with TAP output -$(patsubst %, check-report-qtest-%.tap, $(QTEST_TARGETS)): check-report-qtest-%.tap: %-softmmu/all $(check-qtest-y) - $(call do_test_tap, $(check-qtest-$*-y:%=tests/qtest/%$(EXESUF)) $(check-qtest-generic-y:%=tests/qtest/%$(EXESUF)), \ - QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ - QTEST_QEMU_IMG=qemu-img$(EXESUF)) - check-report-unit.tap: $(check-unit-y) $(call do_test_tap,$^) -# Reports and overall runs - -check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap - # Plugins ifeq ($(CONFIG_PLUGIN),y) .PHONY: plugins @@ -580,21 +550,18 @@ check-acceptance: check-venv $(TESTS_RESULTS_DIR) get-vm-images # Consolidated targets -.PHONY: check-block check-qtest check-unit check check-clean get-vm-images -check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) +.PHONY: check-block check-unit check check-clean get-vm-images ifeq ($(CONFIG_TOOLS),y) check-block: $(patsubst %,check-%, $(check-block-y)) endif -check-build: build-unit build-qtest +check-build: build-unit check-clean: rm -rf $(check-unit-y) tests/*.o tests/*/*.o $(QEMU_IOTESTS_HELPERS-y) - rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y:%=tests/qtest/%$(EXESUF))) $(check-qtest-generic-y:%=tests/qtest/%$(EXESUF))) rm -f tests/test-qapi-gen-timestamp - rm -f tests/qtest/dbus-vmstate1-gen-timestamp rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) -check: check-block check-unit check-qtest +check: check-block check-unit clean: check-clean @@ -603,7 +570,5 @@ clean: check-clean all: $(QEMU_IOTESTS_HELPERS-y) -include $(wildcard tests/*.d) --include $(wildcard tests/qtest/*.d) --include $(wildcard tests/qtest/libqos/*.d) endif diff --git a/tests/meson.build b/tests/meson.build index 8be9c2233c..d724402cf4 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -8,3 +8,4 @@ if 'CONFIG_TCG' in config_host endif subdir('qapi-schema') +subdir('qtest') diff --git a/tests/qtest/Makefile.include b/tests/qtest/Makefile.include deleted file mode 100644 index b0204e44f2..0000000000 --- a/tests/qtest/Makefile.include +++ /dev/null @@ -1,332 +0,0 @@ -# All QTests for now are POSIX-only, but the dependencies are -# really in libqtest, not in the testcases themselves. - -check-qtest-generic-y += cdrom-test -check-qtest-generic-y += device-introspect-test -check-qtest-generic-y += machine-none-test -check-qtest-generic-y += qmp-test -check-qtest-generic-y += qmp-cmd-test -check-qtest-generic-y += qom-test -check-qtest-generic-$(CONFIG_MODULES) += modules-test -check-qtest-generic-y += test-hmp - -check-qtest-pci-$(CONFIG_RTL8139_PCI) += rtl8139-test -check-qtest-pci-$(CONFIG_VGA) += display-vga-test -check-qtest-pci-$(CONFIG_HDA) += intel-hda-test -check-qtest-pci-$(CONFIG_IVSHMEM_DEVICE) += ivshmem-test - -DBUS_DAEMON := $(shell which dbus-daemon 2>/dev/null) -ifneq ($(GDBUS_CODEGEN),) -ifneq ($(DBUS_DAEMON),) -# Temporarily disabled due to Patchew failures: -#check-qtest-pci-$(CONFIG_GIO) += dbus-vmstate-test -endif -endif - -check-qtest-i386-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-i386-y += fdc-test -check-qtest-i386-y += ide-test -check-qtest-i386-$(CONFIG_TOOLS) += ahci-test -check-qtest-i386-y += hd-geo-test -check-qtest-i386-y += boot-order-test -check-qtest-i386-y += bios-tables-test -check-qtest-i386-$(CONFIG_SGA) += boot-serial-test -check-qtest-i386-$(CONFIG_SLIRP) += pxe-test -check-qtest-i386-y += rtc-test -check-qtest-i386-$(CONFIG_ISA_IPMI_KCS) += ipmi-kcs-test -ifdef CONFIG_LINUX -check-qtest-i386-$(CONFIG_ISA_IPMI_BT) += ipmi-bt-test -endif -check-qtest-i386-y += i440fx-test -check-qtest-i386-y += fw_cfg-test -check-qtest-i386-y += device-plug-test -check-qtest-i386-y += drive_del-test -check-qtest-i386-$(CONFIG_WDT_IB700) += wdt_ib700-test -check-qtest-i386-y += tco-test -check-qtest-i386-y += $(check-qtest-pci-y) -check-qtest-i386-$(CONFIG_PVPANIC) += pvpanic-test -check-qtest-i386-$(CONFIG_I82801B11) += i82801b11-test -check-qtest-i386-$(CONFIG_IOH3420) += ioh3420-test -check-qtest-i386-$(CONFIG_USB_UHCI) += usb-hcd-uhci-test -check-qtest-i386-$(call land,$(CONFIG_USB_EHCI),$(CONFIG_USB_UHCI)) += usb-hcd-ehci-test -check-qtest-i386-$(CONFIG_USB_XHCI_NEC) += usb-hcd-xhci-test -check-qtest-i386-y += cpu-plug-test -check-qtest-i386-y += q35-test -check-qtest-i386-y += vmgenid-test -check-qtest-i386-$(CONFIG_TPM_CRB) += tpm-crb-swtpm-test -check-qtest-i386-$(CONFIG_TPM_CRB) += tpm-crb-test -check-qtest-i386-$(CONFIG_TPM_TIS_ISA) += tpm-tis-swtpm-test -check-qtest-i386-$(CONFIG_TPM_TIS_ISA) += tpm-tis-test -check-qtest-i386-$(CONFIG_SLIRP) += test-netfilter -check-qtest-i386-$(CONFIG_POSIX) += test-filter-mirror -check-qtest-i386-$(CONFIG_RTL8139_PCI) += test-filter-redirector -check-qtest-i386-y += migration-test -check-qtest-i386-y += test-x86-cpuid-compat -check-qtest-i386-y += numa-test - -check-qtest-x86_64-y += $(check-qtest-i386-y) - -check-qtest-avr-y += boot-serial-test - -check-qtest-alpha-y += boot-serial-test -check-qtest-alpha-$(CONFIG_VGA) += display-vga-test - -check-qtest-hppa-y += boot-serial-test -check-qtest-hppa-$(CONFIG_VGA) += display-vga-test - -check-qtest-m68k-y = boot-serial-test - -check-qtest-microblaze-y += boot-serial-test - -check-qtest-mips-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-mips-$(CONFIG_VGA) += display-vga-test - -check-qtest-mips64-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-mips64-$(CONFIG_VGA) += display-vga-test - -check-qtest-mips64el-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-mips64el-$(CONFIG_VGA) += display-vga-test - -check-qtest-moxie-y += boot-serial-test - -check-qtest-ppc-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-ppc-y += boot-order-test -check-qtest-ppc-y += prom-env-test -check-qtest-ppc-y += drive_del-test -check-qtest-ppc-y += boot-serial-test -check-qtest-ppc-$(CONFIG_M48T59) += m48t59-test - -check-qtest-ppc64-y += $(check-qtest-ppc-y) -check-qtest-ppc64-$(CONFIG_PSERIES) += device-plug-test -check-qtest-ppc64-$(CONFIG_POWERNV) += pnv-xscom-test -check-qtest-ppc64-y += migration-test -check-qtest-ppc64-$(CONFIG_PSERIES) += rtas-test -check-qtest-ppc64-$(CONFIG_SLIRP) += pxe-test -check-qtest-ppc64-$(CONFIG_USB_UHCI) += usb-hcd-uhci-test -check-qtest-ppc64-$(CONFIG_USB_XHCI_NEC) += usb-hcd-xhci-test -check-qtest-ppc64-$(CONFIG_SLIRP) += test-netfilter -check-qtest-ppc64-$(CONFIG_POSIX) += test-filter-mirror -check-qtest-ppc64-$(CONFIG_RTL8139_PCI) += test-filter-redirector -check-qtest-ppc64-$(CONFIG_VGA) += display-vga-test -check-qtest-ppc64-y += numa-test -check-qtest-ppc64-$(CONFIG_IVSHMEM_DEVICE) += ivshmem-test -check-qtest-ppc64-y += cpu-plug-test - -check-qtest-sh4-$(CONFIG_ISA_TESTDEV) = endianness-test - -check-qtest-sh4eb-$(CONFIG_ISA_TESTDEV) = endianness-test - -check-qtest-sparc-y += prom-env-test -check-qtest-sparc-y += m48t59-test -check-qtest-sparc-y += boot-serial-test - -check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = endianness-test -check-qtest-sparc64-y += prom-env-test -check-qtest-sparc64-y += boot-serial-test - -check-qtest-arm-y += arm-cpu-features -check-qtest-arm-y += microbit-test -check-qtest-arm-y += m25p80-test -check-qtest-arm-y += test-arm-mptimer -check-qtest-arm-y += boot-serial-test -check-qtest-arm-y += hexloader-test -check-qtest-arm-$(CONFIG_PFLASH_CFI02) += pflash-cfi02-test - -check-qtest-aarch64-y += arm-cpu-features -check-qtest-aarch64-$(CONFIG_TPM_TIS_SYSBUS) += tpm-tis-device-test -check-qtest-aarch64-$(CONFIG_TPM_TIS_SYSBUS) += tpm-tis-device-swtpm-test -check-qtest-aarch64-y += numa-test -check-qtest-aarch64-y += boot-serial-test -check-qtest-aarch64-y += migration-test - -# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional -ifneq ($(ARCH),arm) -check-qtest-aarch64-y += bios-tables-test -endif - -check-qtest-microblazeel-y += $(check-qtest-microblaze-y) - -check-qtest-xtensaeb-y += $(check-qtest-xtensa-y) - -check-qtest-s390x-y = boot-serial-test -check-qtest-s390x-$(CONFIG_SLIRP) += pxe-test -check-qtest-s390x-$(CONFIG_SLIRP) += test-netfilter -check-qtest-s390x-$(CONFIG_POSIX) += test-filter-mirror -check-qtest-s390x-$(CONFIG_POSIX) += test-filter-redirector -check-qtest-s390x-y += drive_del-test -check-qtest-s390x-y += device-plug-test -check-qtest-s390x-y += virtio-ccw-test -check-qtest-s390x-y += cpu-plug-test -check-qtest-s390x-y += migration-test - -# libqos / qgraph : -libqgraph-obj-y = tests/qtest/libqos/qgraph.o - -libqos-core-obj-y = $(libqgraph-obj-y) tests/qtest/libqos/pci.o tests/qtest/libqos/fw_cfg.o -libqos-core-obj-y += tests/qtest/libqos/malloc.o -libqos-core-obj-y += tests/qtest/libqos/libqos.o -libqos-spapr-obj-y = $(libqos-core-obj-y) tests/qtest/libqos/malloc-spapr.o -libqos-spapr-obj-y += tests/qtest/libqos/libqos-spapr.o -libqos-spapr-obj-y += tests/qtest/libqos/rtas.o -libqos-spapr-obj-y += tests/qtest/libqos/pci-spapr.o -libqos-pc-obj-y = $(libqos-core-obj-y) tests/qtest/libqos/pci-pc.o -libqos-pc-obj-y += tests/qtest/libqos/malloc-pc.o tests/qtest/libqos/libqos-pc.o -libqos-pc-obj-y += tests/qtest/libqos/ahci.o -libqos-usb-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/qtest/libqos/usb.o - -# qos devices: -libqos-obj-y = $(libqgraph-obj-y) -libqos-obj-y += $(libqos-pc-obj-y) $(libqos-spapr-obj-y) -libqos-obj-y += tests/qtest/libqos/qos_external.o -libqos-obj-y += tests/qtest/libqos/e1000e.o -libqos-obj-y += tests/qtest/libqos/i2c.o -libqos-obj-y += tests/qtest/libqos/i2c-imx.o -libqos-obj-y += tests/qtest/libqos/i2c-omap.o -libqos-obj-y += tests/qtest/libqos/sdhci.o -libqos-obj-y += tests/qtest/libqos/tpci200.o -libqos-obj-y += tests/qtest/libqos/virtio.o -libqos-obj-$(CONFIG_VIRTFS) += tests/qtest/libqos/virtio-9p.o -libqos-obj-y += tests/qtest/libqos/virtio-balloon.o -libqos-obj-y += tests/qtest/libqos/virtio-blk.o -libqos-obj-y += tests/qtest/libqos/virtio-mmio.o -libqos-obj-y += tests/qtest/libqos/virtio-net.o -libqos-obj-y += tests/qtest/libqos/virtio-pci.o -libqos-obj-y += tests/qtest/libqos/virtio-pci-modern.o -libqos-obj-y += tests/qtest/libqos/virtio-rng.o -libqos-obj-y += tests/qtest/libqos/virtio-scsi.o -libqos-obj-y += tests/qtest/libqos/virtio-serial.o - -# qos machines: -libqos-obj-y += tests/qtest/libqos/aarch64-xlnx-zcu102-machine.o -libqos-obj-y += tests/qtest/libqos/arm-imx25-pdk-machine.o -libqos-obj-y += tests/qtest/libqos/arm-n800-machine.o -libqos-obj-y += tests/qtest/libqos/arm-raspi2-machine.o -libqos-obj-y += tests/qtest/libqos/arm-sabrelite-machine.o -libqos-obj-y += tests/qtest/libqos/arm-smdkc210-machine.o -libqos-obj-y += tests/qtest/libqos/arm-virt-machine.o -libqos-obj-y += tests/qtest/libqos/arm-xilinx-zynq-a9-machine.o -libqos-obj-y += tests/qtest/libqos/ppc64_pseries-machine.o -libqos-obj-y += tests/qtest/libqos/x86_64_pc-machine.o - -# qos tests: -qos-test-obj-y += tests/qtest/qos-test.o -qos-test-obj-y += tests/qtest/ac97-test.o -qos-test-obj-y += tests/qtest/ds1338-test.o -qos-test-obj-y += tests/qtest/e1000-test.o -qos-test-obj-y += tests/qtest/e1000e-test.o -qos-test-obj-y += tests/qtest/eepro100-test.o -qos-test-obj-y += tests/qtest/es1370-test.o -qos-test-obj-y += tests/qtest/ipoctal232-test.o -qos-test-obj-y += tests/qtest/megasas-test.o -qos-test-obj-y += tests/qtest/ne2000-test.o -qos-test-obj-y += tests/qtest/tulip-test.o -qos-test-obj-y += tests/qtest/nvme-test.o -qos-test-obj-y += tests/qtest/pca9552-test.o -qos-test-obj-y += tests/qtest/pci-test.o -qos-test-obj-y += tests/qtest/pcnet-test.o -qos-test-obj-y += tests/qtest/sdhci-test.o -qos-test-obj-y += tests/qtest/spapr-phb-test.o -qos-test-obj-y += tests/qtest/tmp105-test.o -qos-test-obj-y += tests/qtest/usb-hcd-ohci-test.o $(libqos-usb-obj-y) -qos-test-obj-$(CONFIG_VHOST_NET_USER) += tests/qtest/vhost-user-test.o $(chardev-obj-y) $(test-io-obj-y) -qos-test-obj-y += tests/qtest/virtio-test.o -qos-test-obj-$(CONFIG_VIRTFS) += tests/qtest/virtio-9p-test.o -qos-test-obj-y += tests/qtest/virtio-blk-test.o -qos-test-obj-y += tests/qtest/virtio-net-test.o -qos-test-obj-y += tests/qtest/virtio-rng-test.o -qos-test-obj-y += tests/qtest/virtio-scsi-test.o -qos-test-obj-y += tests/qtest/virtio-serial-test.o -qos-test-obj-y += tests/qtest/vmxnet3-test.o - -check-unit-y += tests/test-qgraph$(EXESUF) -tests/test-qgraph$(EXESUF): tests/test-qgraph.o $(libqgraph-obj-y) - -check-qtest-generic-y += qos-test -tests/qtest/qos-test$(EXESUF): $(qos-test-obj-y) $(libqos-obj-y) - -# QTest dependencies: -tests/qtest/qmp-test$(EXESUF): tests/qtest/qmp-test.o -tests/qtest/qmp-cmd-test$(EXESUF): tests/qtest/qmp-cmd-test.o -tests/qtest/device-introspect-test$(EXESUF): tests/qtest/device-introspect-test.o -tests/qtest/rtc-test$(EXESUF): tests/qtest/rtc-test.o -tests/qtest/m48t59-test$(EXESUF): tests/qtest/m48t59-test.o -tests/qtest/hexloader-test$(EXESUF): tests/qtest/hexloader-test.o -tests/qtest/pflash-cfi02$(EXESUF): tests/qtest/pflash-cfi02-test.o -tests/qtest/endianness-test$(EXESUF): tests/qtest/endianness-test.o -tests/qtest/prom-env-test$(EXESUF): tests/qtest/prom-env-test.o $(libqos-obj-y) -tests/qtest/rtas-test$(EXESUF): tests/qtest/rtas-test.o $(libqos-spapr-obj-y) -tests/qtest/fdc-test$(EXESUF): tests/qtest/fdc-test.o -tests/qtest/ide-test$(EXESUF): tests/qtest/ide-test.o $(libqos-pc-obj-y) -tests/qtest/ahci-test$(EXESUF): tests/qtest/ahci-test.o $(libqos-pc-obj-y) qemu-img$(EXESUF) -tests/qtest/ipmi-kcs-test$(EXESUF): tests/qtest/ipmi-kcs-test.o -tests/qtest/ipmi-bt-test$(EXESUF): tests/qtest/ipmi-bt-test.o -tests/qtest/hd-geo-test$(EXESUF): tests/qtest/hd-geo-test.o $(libqos-obj-y) -tests/qtest/boot-order-test$(EXESUF): tests/qtest/boot-order-test.o $(libqos-obj-y) -tests/qtest/boot-serial-test$(EXESUF): tests/qtest/boot-serial-test.o $(libqos-obj-y) -tests/qtest/bios-tables-test$(EXESUF): tests/qtest/bios-tables-test.o \ - tests/qtest/tpm-emu.o $(test-io-obj-y) \ - tests/qtest/boot-sector.o tests/qtest/acpi-utils.o $(libqos-obj-y) -tests/qtest/pxe-test$(EXESUF): tests/qtest/pxe-test.o tests/qtest/boot-sector.o $(libqos-obj-y) -tests/qtest/microbit-test$(EXESUF): tests/qtest/microbit-test.o -tests/qtest/m25p80-test$(EXESUF): tests/qtest/m25p80-test.o -tests/qtest/i440fx-test$(EXESUF): tests/qtest/i440fx-test.o $(libqos-pc-obj-y) -tests/qtest/q35-test$(EXESUF): tests/qtest/q35-test.o $(libqos-pc-obj-y) -tests/qtest/fw_cfg-test$(EXESUF): tests/qtest/fw_cfg-test.o $(libqos-pc-obj-y) -tests/qtest/rtl8139-test$(EXESUF): tests/qtest/rtl8139-test.o $(libqos-pc-obj-y) -tests/qtest/pnv-xscom-test$(EXESUF): tests/qtest/pnv-xscom-test.o -tests/qtest/wdt_ib700-test$(EXESUF): tests/qtest/wdt_ib700-test.o -tests/qtest/tco-test$(EXESUF): tests/qtest/tco-test.o $(libqos-pc-obj-y) -tests/qtest/virtio-ccw-test$(EXESUF): tests/qtest/virtio-ccw-test.o -tests/qtest/display-vga-test$(EXESUF): tests/qtest/display-vga-test.o -tests/qtest/qom-test$(EXESUF): tests/qtest/qom-test.o -tests/qtest/modules-test$(EXESUF): tests/qtest/modules-test.o -tests/qtest/test-hmp$(EXESUF): tests/qtest/test-hmp.o -tests/qtest/machine-none-test$(EXESUF): tests/qtest/machine-none-test.o -tests/qtest/device-plug-test$(EXESUF): tests/qtest/device-plug-test.o -tests/qtest/drive_del-test$(EXESUF): tests/qtest/drive_del-test.o -tests/qtest/pvpanic-test$(EXESUF): tests/qtest/pvpanic-test.o -tests/qtest/i82801b11-test$(EXESUF): tests/qtest/i82801b11-test.o -tests/qtest/intel-hda-test$(EXESUF): tests/qtest/intel-hda-test.o -tests/qtest/ioh3420-test$(EXESUF): tests/qtest/ioh3420-test.o -tests/qtest/usb-hcd-uhci-test$(EXESUF): tests/qtest/usb-hcd-uhci-test.o $(libqos-usb-obj-y) -tests/qtest/usb-hcd-ehci-test$(EXESUF): tests/qtest/usb-hcd-ehci-test.o $(libqos-usb-obj-y) -tests/qtest/usb-hcd-xhci-test$(EXESUF): tests/qtest/usb-hcd-xhci-test.o $(libqos-usb-obj-y) -tests/qtest/cpu-plug-test$(EXESUF): tests/qtest/cpu-plug-test.o -tests/qtest/migration-test$(EXESUF): tests/qtest/migration-test.o tests/qtest/migration-helpers.o -tests/qtest/test-netfilter$(EXESUF): tests/qtest/test-netfilter.o $(qtest-obj-y) -tests/qtest/test-filter-mirror$(EXESUF): tests/qtest/test-filter-mirror.o $(qtest-obj-y) -tests/qtest/test-filter-redirector$(EXESUF): tests/qtest/test-filter-redirector.o $(qtest-obj-y) -tests/qtest/test-x86-cpuid-compat$(EXESUF): tests/qtest/test-x86-cpuid-compat.o $(qtest-obj-y) -tests/qtest/ivshmem-test$(EXESUF): tests/qtest/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y) -tests/qtest/dbus-vmstate-test$(EXESUF): tests/qtest/dbus-vmstate-test.o tests/qtest/migration-helpers.o tests/qtest/dbus-vmstate1.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y) -tests/qtest/test-arm-mptimer$(EXESUF): tests/qtest/test-arm-mptimer.o -tests/qtest/numa-test$(EXESUF): tests/qtest/numa-test.o -tests/qtest/vmgenid-test$(EXESUF): tests/qtest/vmgenid-test.o tests/qtest/boot-sector.o tests/qtest/acpi-utils.o -tests/qtest/cdrom-test$(EXESUF): tests/qtest/cdrom-test.o tests/qtest/boot-sector.o $(libqos-obj-y) -tests/qtest/arm-cpu-features$(EXESUF): tests/qtest/arm-cpu-features.o -tests/qtest/tpm-crb-swtpm-test$(EXESUF): tests/qtest/tpm-crb-swtpm-test.o tests/qtest/tpm-emu.o \ - tests/qtest/tpm-util.o tests/qtest/tpm-tests.o $(test-io-obj-y) -tests/qtest/tpm-crb-test$(EXESUF): tests/qtest/tpm-crb-test.o tests/qtest/tpm-emu.o $(test-io-obj-y) -tests/qtest/tpm-tis-swtpm-test$(EXESUF): tests/qtest/tpm-tis-swtpm-test.o tests/qtest/tpm-emu.o \ - tests/qtest/tpm-util.o tests/qtest/tpm-tests.o $(test-io-obj-y) -tests/qtest/tpm-tis-device-swtpm-test$(EXESUF): tests/qtest/tpm-tis-device-swtpm-test.o tests/qtest/tpm-emu.o \ - tests/qtest/tpm-util.o tests/qtest/tpm-tests.o $(test-io-obj-y) -tests/qtest/tpm-tis-test$(EXESUF): tests/qtest/tpm-tis-test.o tests/qtest/tpm-tis-util.o tests/qtest/tpm-emu.o $(test-io-obj-y) -tests/qtest/tpm-tis-device-test$(EXESUF): tests/qtest/tpm-tis-device-test.o tests/qtest/tpm-tis-util.o tests/qtest/tpm-emu.o $(test-io-obj-y) - -# QTest rules - -TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) -QTEST_TARGETS = -# The qtests are not runnable (yet) under TSan due to a known issue. -# https://github.com/google/sanitizers/issues/1116 -ifndef CONFIG_TSAN -ifeq ($(CONFIG_POSIX),y) -QTEST_TARGETS = $(TARGETS) -check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y:%=tests/qtest/%$(EXESUF))) -check-qtest-y += $(check-qtest-generic-y:%=tests/qtest/%$(EXESUF)) -endif -endif - -qtest-obj-y = tests/qtest/libqtest.o $(test-util-obj-y) -$(check-qtest-y): $(qtest-obj-y) diff --git a/tests/qtest/ac97-test.c b/tests/qtest/ac97-test.c index b084e31bff..e09f2495d2 100644 --- a/tests/qtest/ac97-test.c +++ b/tests/qtest/ac97-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/acpi-utils.h b/tests/qtest/acpi-utils.h index 0c86780689..261784d251 100644 --- a/tests/qtest/acpi-utils.h +++ b/tests/qtest/acpi-utils.h @@ -13,7 +13,7 @@ #ifndef TEST_ACPI_UTILS_H #define TEST_ACPI_UTILS_H -#include "libqtest.h" +#include "libqos/libqtest.h" /* DSDT and SSDTs format */ typedef struct { diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c index c8d42ceea0..ca4294f44f 100644 --- a/tests/qtest/ahci-test.c +++ b/tests/qtest/ahci-test.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/libqos-pc.h" #include "libqos/ahci.h" #include "libqos/pci-pc.h" diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index f7e062c189..77b5e30a9c 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -10,7 +10,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qjson.h" diff --git a/tests/qtest/boot-order-test.c b/tests/qtest/boot-order-test.c index 2f1c07221c..fac580d6c4 100644 --- a/tests/qtest/boot-order-test.c +++ b/tests/qtest/boot-order-test.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "libqos/fw_cfg.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "standard-headers/linux/qemu_fw_cfg.h" diff --git a/tests/qtest/boot-sector.c b/tests/qtest/boot-sector.c index 9e66c6d013..24df5c4734 100644 --- a/tests/qtest/boot-sector.c +++ b/tests/qtest/boot-sector.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "boot-sector.h" #include "qemu-common.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #define LOW(x) ((x) & 0xff) #define HIGH(x) ((x) >> 8) diff --git a/tests/qtest/boot-sector.h b/tests/qtest/boot-sector.h index 6ee6bb4d97..b339fdee4c 100644 --- a/tests/qtest/boot-sector.h +++ b/tests/qtest/boot-sector.h @@ -14,7 +14,7 @@ #ifndef TEST_BOOT_SECTOR_H #define TEST_BOOT_SECTOR_H -#include "libqtest.h" +#include "libqos/libqtest.h" /* Create boot disk file. fname must be a suitable string for mkstemp() */ int boot_sector_init(char *fname); diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index bfe7624dc6..b6b1c23cd0 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -14,7 +14,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/libqos-spapr.h" static const uint8_t bios_avr[] = { diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 833a0508a1..e9afab693c 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "boot-sector.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/dbus-vmstate-test.c b/tests/qtest/dbus-vmstate-test.c index 2e5e47dec2..aca9b98b7a 100644 --- a/tests/qtest/dbus-vmstate-test.c +++ b/tests/qtest/dbus-vmstate-test.c @@ -1,7 +1,7 @@ #include "qemu/osdep.h" #include #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu-common.h" #include "dbus-vmstate1.h" #include "migration-helpers.h" diff --git a/tests/qtest/device-introspect-test.c b/tests/qtest/device-introspect-test.c index d68b7856a7..9f22340ee5 100644 --- a/tests/qtest/device-introspect-test.c +++ b/tests/qtest/device-introspect-test.c @@ -22,7 +22,7 @@ #include "qapi/qmp/qstring.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qlist.h" -#include "libqtest.h" +#include "libqos/libqtest.h" const char common_args[] = "-nodefaults -machine none"; diff --git a/tests/qtest/device-plug-test.c b/tests/qtest/device-plug-test.c index 318e422d51..9214892741 100644 --- a/tests/qtest/device-plug-test.c +++ b/tests/qtest/device-plug-test.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qstring.h" diff --git a/tests/qtest/drive_del-test.c b/tests/qtest/drive_del-test.c index 5f8839b232..2ab11ad225 100644 --- a/tests/qtest/drive_del-test.c +++ b/tests/qtest/drive_del-test.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/virtio.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index f6ade9a050..c5d46bcc64 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/i2c.h" #define DS1338_ADDR 0x68 diff --git a/tests/qtest/e1000-test.c b/tests/qtest/e1000-test.c index c387984ef6..ea286d1793 100644 --- a/tests/qtest/e1000-test.c +++ b/tests/qtest/e1000-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/eepro100-test.c b/tests/qtest/eepro100-test.c index 8dbffff0b8..d72ad099f1 100644 --- a/tests/qtest/eepro100-test.c +++ b/tests/qtest/eepro100-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/endianness-test.c b/tests/qtest/endianness-test.c index cc088ac01a..4e79e22c28 100644 --- a/tests/qtest/endianness-test.c +++ b/tests/qtest/endianness-test.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/bswap.h" typedef struct TestCase TestCase; diff --git a/tests/qtest/es1370-test.c b/tests/qtest/es1370-test.c index adccdac1be..2fd7fd2d3d 100644 --- a/tests/qtest/es1370-test.c +++ b/tests/qtest/es1370-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/fuzz/fuzz.c b/tests/qtest/fuzz/fuzz.c index 031594a686..1ceea84702 100644 --- a/tests/qtest/fuzz/fuzz.c +++ b/tests/qtest/fuzz/fuzz.c @@ -20,7 +20,7 @@ #include "sysemu/sysemu.h" #include "qemu/main-loop.h" #include "qemu/rcu.h" -#include "tests/qtest/libqtest.h" +#include "tests/qtest/libqos/libqtest.h" #include "tests/qtest/libqos/qgraph.h" #include "fuzz.h" diff --git a/tests/qtest/fuzz/fuzz.h b/tests/qtest/fuzz/fuzz.h index 9ca3d107c5..8eb765edc8 100644 --- a/tests/qtest/fuzz/fuzz.h +++ b/tests/qtest/fuzz/fuzz.h @@ -18,7 +18,7 @@ #include "qemu/units.h" #include "qapi/error.h" -#include "tests/qtest/libqtest.h" +#include "tests/qtest/libqos/libqtest.h" /** * A libfuzzer fuzzing target diff --git a/tests/qtest/fuzz/i440fx_fuzz.c b/tests/qtest/fuzz/i440fx_fuzz.c index bf966d478b..f45373f5d3 100644 --- a/tests/qtest/fuzz/i440fx_fuzz.c +++ b/tests/qtest/fuzz/i440fx_fuzz.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "tests/qtest/libqtest.h" +#include "tests/qtest/libqos/libqtest.h" #include "tests/qtest/libqos/pci.h" #include "tests/qtest/libqos/pci-pc.h" #include "fuzz.h" diff --git a/tests/qtest/fuzz/qos_fuzz.c b/tests/qtest/fuzz/qos_fuzz.c index d52f3ebd83..b943577b8c 100644 --- a/tests/qtest/fuzz/qos_fuzz.c +++ b/tests/qtest/fuzz/qos_fuzz.c @@ -25,7 +25,7 @@ #include "sysemu/sysemu.h" #include "qemu/main-loop.h" -#include "tests/qtest/libqtest.h" +#include "tests/qtest/libqos/libqtest.h" #include "tests/qtest/libqos/malloc.h" #include "tests/qtest/libqos/qgraph.h" #include "tests/qtest/libqos/qgraph_internal.h" diff --git a/tests/qtest/fuzz/virtio_net_fuzz.c b/tests/qtest/fuzz/virtio_net_fuzz.c index a33bd73067..277a9e2b64 100644 --- a/tests/qtest/fuzz/virtio_net_fuzz.c +++ b/tests/qtest/fuzz/virtio_net_fuzz.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "standard-headers/linux/virtio_config.h" -#include "tests/qtest/libqtest.h" +#include "tests/qtest/libqos/libqtest.h" #include "tests/qtest/libqos/virtio-net.h" #include "fuzz.h" #include "fork_fuzz.h" diff --git a/tests/qtest/fw_cfg-test.c b/tests/qtest/fw_cfg-test.c index 5dc807ba23..95b3907c18 100644 --- a/tests/qtest/fw_cfg-test.c +++ b/tests/qtest/fw_cfg-test.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "standard-headers/linux/qemu_fw_cfg.h" #include "libqos/fw_cfg.h" #include "qemu/bswap.h" diff --git a/tests/qtest/hd-geo-test.c b/tests/qtest/hd-geo-test.c index 48e8e02d6e..f7b7cfbc2d 100644 --- a/tests/qtest/hd-geo-test.c +++ b/tests/qtest/hd-geo-test.c @@ -19,7 +19,7 @@ #include "qemu-common.h" #include "qemu/bswap.h" #include "qapi/qmp/qlist.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/fw_cfg.h" #include "libqos/libqos.h" #include "standard-headers/linux/qemu_fw_cfg.h" diff --git a/tests/qtest/hexloader-test.c b/tests/qtest/hexloader-test.c index 8b7aa2d72d..561502052a 100644 --- a/tests/qtest/hexloader-test.c +++ b/tests/qtest/hexloader-test.c @@ -10,7 +10,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" /* Load 'test.hex' and verify that the in-memory contents are as expected. * 'test.hex' is a memory test pattern stored in Hexadecimal Object diff --git a/tests/qtest/ide-test.c b/tests/qtest/ide-test.c index 5cfd97f915..3f8081e77d 100644 --- a/tests/qtest/ide-test.c +++ b/tests/qtest/ide-test.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/libqos.h" #include "libqos/pci-pc.h" #include "libqos/malloc-pc.h" diff --git a/tests/qtest/ipoctal232-test.c b/tests/qtest/ipoctal232-test.c index 53a8c9b13c..65ce10b81b 100644 --- a/tests/qtest/ipoctal232-test.c +++ b/tests/qtest/ipoctal232-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" diff --git a/tests/qtest/ivshmem-test.c b/tests/qtest/ivshmem-test.c index ecda256472..d5c8b9f128 100644 --- a/tests/qtest/ivshmem-test.c +++ b/tests/qtest/ivshmem-test.c @@ -13,7 +13,7 @@ #include "contrib/ivshmem-server/ivshmem-server.h" #include "libqos/libqos-pc.h" #include "libqos/libqos-spapr.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu-common.h" #define TMPSHMSIZE (1 << 20) diff --git a/tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c b/tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c index 8f827aeb52..79631cc7a9 100644 --- a/tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c +++ b/tests/qtest/libqos/aarch64-xlnx-zcu102-machine.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "sdhci.h" typedef struct QXlnxZCU102Machine QXlnxZCU102Machine; diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index cc1b08eabe..2946abc15a 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -25,8 +25,8 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/ahci.h" -#include "libqos/pci-pc.h" +#include "ahci.h" +#include "pci-pc.h" #include "qemu-common.h" #include "qemu/host-utils.h" @@ -579,7 +579,7 @@ void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd) /* NCQ commands use exclusively 8 bit fields and needs no adjustment. * Only the count field needs to be adjusted for non-NCQ commands. * The auxiliary FIS fields are defined per-command and are not currently - * implemented in libqos/ahci.o, but may or may not need to be flipped. */ + * implemented in ahci.o, but may or may not need to be flipped. */ if (!cmd->props->ncq) { tmp.count = cpu_to_le16(tmp.count); } diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index 44ab1104b5..88835b6228 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -25,9 +25,9 @@ * THE SOFTWARE. */ -#include "libqos/libqos.h" -#include "libqos/pci.h" -#include "libqos/malloc-pc.h" +#include "libqos.h" +#include "pci.h" +#include "malloc-pc.h" /*** Supplementary PCI Config Space IDs & Masks ***/ #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922) diff --git a/tests/qtest/libqos/arm-imx25-pdk-machine.c b/tests/qtest/libqos/arm-imx25-pdk-machine.c index 0da3f19c0e..6692adfa4f 100644 --- a/tests/qtest/libqos/arm-imx25-pdk-machine.c +++ b/tests/qtest/libqos/arm-imx25-pdk-machine.c @@ -20,9 +20,9 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" -#include "libqos/i2c.h" +#include "malloc.h" +#include "qgraph.h" +#include "i2c.h" #define ARM_PAGE_SIZE 4096 #define IMX25_PDK_RAM_START 0x80000000 diff --git a/tests/qtest/libqos/arm-n800-machine.c b/tests/qtest/libqos/arm-n800-machine.c index 35f82070fa..ff2049c3a7 100644 --- a/tests/qtest/libqos/arm-n800-machine.c +++ b/tests/qtest/libqos/arm-n800-machine.c @@ -20,9 +20,9 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" -#include "libqos/i2c.h" +#include "malloc.h" +#include "qgraph.h" +#include "i2c.h" #define ARM_PAGE_SIZE 4096 #define N800_RAM_START 0x80000000 diff --git a/tests/qtest/libqos/arm-raspi2-machine.c b/tests/qtest/libqos/arm-raspi2-machine.c index 8480d80669..35bb4709a4 100644 --- a/tests/qtest/libqos/arm-raspi2-machine.c +++ b/tests/qtest/libqos/arm-raspi2-machine.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "sdhci.h" #define ARM_PAGE_SIZE 4096 diff --git a/tests/qtest/libqos/arm-sabrelite-machine.c b/tests/qtest/libqos/arm-sabrelite-machine.c index f6e403b538..72425f0ad4 100644 --- a/tests/qtest/libqos/arm-sabrelite-machine.c +++ b/tests/qtest/libqos/arm-sabrelite-machine.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "sdhci.h" #define ARM_PAGE_SIZE 4096 diff --git a/tests/qtest/libqos/arm-smdkc210-machine.c b/tests/qtest/libqos/arm-smdkc210-machine.c index eebac7feeb..321b8826d4 100644 --- a/tests/qtest/libqos/arm-smdkc210-machine.c +++ b/tests/qtest/libqos/arm-smdkc210-machine.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "sdhci.h" #define ARM_PAGE_SIZE 4096 diff --git a/tests/qtest/libqos/arm-virt-machine.c b/tests/qtest/libqos/arm-virt-machine.c index 9316598f9e..e0f5932284 100644 --- a/tests/qtest/libqos/arm-virt-machine.c +++ b/tests/qtest/libqos/arm-virt-machine.c @@ -19,9 +19,9 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-mmio.h" +#include "malloc.h" +#include "qgraph.h" +#include "virtio-mmio.h" #define ARM_PAGE_SIZE 4096 #define VIRTIO_MMIO_BASE_ADDR 0x0A003E00 diff --git a/tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c b/tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c index 473acce993..56e53c745b 100644 --- a/tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c +++ b/tests/qtest/libqos/arm-xilinx-zynq-a9-machine.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "sdhci.h" typedef struct QXilinxZynqA9Machine QXilinxZynqA9Machine; diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c index e2927ed2da..a451f6168f 100644 --- a/tests/qtest/libqos/e1000e.c +++ b/tests/qtest/libqos/e1000e.c @@ -18,13 +18,13 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/pci-pc.h" +#include "pci-pc.h" #include "qemu/sockets.h" #include "qemu/iov.h" #include "qemu/module.h" #include "qemu/bitops.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "qgraph.h" #include "e1000e.h" #define E1000E_IMS (0x00d0) diff --git a/tests/qtest/libqos/e1000e.h b/tests/qtest/libqos/e1000e.h index 35183b2875..a22f5fdbad 100644 --- a/tests/qtest/libqos/e1000e.h +++ b/tests/qtest/libqos/e1000e.h @@ -19,7 +19,7 @@ #ifndef QGRAPH_E1000E_H #define QGRAPH_E1000E_H -#include "libqos/qgraph.h" +#include "qgraph.h" #include "pci.h" #define E1000E_RX0_MSG_ID (0) diff --git a/tests/qtest/libqos/fw_cfg.c b/tests/qtest/libqos/fw_cfg.c index 1f46258f96..6b8e1babe5 100644 --- a/tests/qtest/libqos/fw_cfg.c +++ b/tests/qtest/libqos/fw_cfg.c @@ -13,7 +13,7 @@ */ #include "qemu/osdep.h" -#include "libqos/fw_cfg.h" +#include "fw_cfg.h" #include "libqtest.h" #include "qemu/bswap.h" #include "hw/nvram/fw_cfg.h" diff --git a/tests/qtest/libqos/i2c-imx.c b/tests/qtest/libqos/i2c-imx.c index f33ece55a3..8f9a7e3831 100644 --- a/tests/qtest/libqos/i2c-imx.c +++ b/tests/qtest/libqos/i2c-imx.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" -#include "libqos/i2c.h" +#include "i2c.h" #include "libqtest.h" diff --git a/tests/qtest/libqos/i2c-omap.c b/tests/qtest/libqos/i2c-omap.c index 9ae8214fa8..eb4e453485 100644 --- a/tests/qtest/libqos/i2c-omap.c +++ b/tests/qtest/libqos/i2c-omap.c @@ -7,7 +7,7 @@ * See the COPYING file in the top-level directory. */ #include "qemu/osdep.h" -#include "libqos/i2c.h" +#include "i2c.h" #include "qemu/bswap.h" diff --git a/tests/qtest/libqos/i2c.c b/tests/qtest/libqos/i2c.c index 38f800dbab..ade1bdb40e 100644 --- a/tests/qtest/libqos/i2c.c +++ b/tests/qtest/libqos/i2c.c @@ -7,7 +7,7 @@ * See the COPYING file in the top-level directory. */ #include "qemu/osdep.h" -#include "libqos/i2c.h" +#include "i2c.h" #include "libqtest.h" void qi2c_send(QI2CDevice *i2cdev, const uint8_t *buf, uint16_t len) diff --git a/tests/qtest/libqos/i2c.h b/tests/qtest/libqos/i2c.h index c65f087834..1341bac1c5 100644 --- a/tests/qtest/libqos/i2c.h +++ b/tests/qtest/libqos/i2c.h @@ -10,7 +10,7 @@ #define LIBQOS_I2C_H #include "libqtest.h" -#include "libqos/qgraph.h" +#include "qgraph.h" typedef struct I2CAdapter I2CAdapter; struct I2CAdapter { diff --git a/tests/qtest/libqos/libqos-pc.c b/tests/qtest/libqos/libqos-pc.c index d04abc548b..db420a596e 100644 --- a/tests/qtest/libqos/libqos-pc.c +++ b/tests/qtest/libqos/libqos-pc.c @@ -1,7 +1,7 @@ #include "qemu/osdep.h" -#include "libqos/libqos-pc.h" -#include "libqos/malloc-pc.h" -#include "libqos/pci-pc.h" +#include "libqos-pc.h" +#include "malloc-pc.h" +#include "pci-pc.h" static QOSOps qos_ops = { .alloc_init = pc_alloc_init, diff --git a/tests/qtest/libqos/libqos-pc.h b/tests/qtest/libqos/libqos-pc.h index a0e4c45516..1a9923ead4 100644 --- a/tests/qtest/libqos/libqos-pc.h +++ b/tests/qtest/libqos/libqos-pc.h @@ -1,7 +1,7 @@ #ifndef LIBQOS_PC_H #define LIBQOS_PC_H -#include "libqos/libqos.h" +#include "libqos.h" QOSState *qtest_pc_vboot(const char *cmdline_fmt, va_list ap); QOSState *qtest_pc_boot(const char *cmdline_fmt, ...); diff --git a/tests/qtest/libqos/libqos-spapr.c b/tests/qtest/libqos/libqos-spapr.c index 8766d543ce..db0e87ba5c 100644 --- a/tests/qtest/libqos/libqos-spapr.c +++ b/tests/qtest/libqos/libqos-spapr.c @@ -1,7 +1,7 @@ #include "qemu/osdep.h" -#include "libqos/libqos-spapr.h" -#include "libqos/malloc-spapr.h" -#include "libqos/pci-spapr.h" +#include "libqos-spapr.h" +#include "malloc-spapr.h" +#include "pci-spapr.h" static QOSOps qos_ops = { .alloc_init = spapr_alloc_init, diff --git a/tests/qtest/libqos/libqos-spapr.h b/tests/qtest/libqos/libqos-spapr.h index 49bd72d20b..c61338917a 100644 --- a/tests/qtest/libqos/libqos-spapr.h +++ b/tests/qtest/libqos/libqos-spapr.h @@ -1,7 +1,7 @@ #ifndef LIBQOS_SPAPR_H #define LIBQOS_SPAPR_H -#include "libqos/libqos.h" +#include "libqos.h" QOSState *qtest_spapr_vboot(const char *cmdline_fmt, va_list ap); QOSState *qtest_spapr_boot(const char *cmdline_fmt, ...); diff --git a/tests/qtest/libqos/libqos.c b/tests/qtest/libqos/libqos.c index f229eb2cb8..2251e864ef 100644 --- a/tests/qtest/libqos/libqos.c +++ b/tests/qtest/libqos/libqos.c @@ -2,8 +2,8 @@ #include #include "libqtest.h" -#include "libqos/libqos.h" -#include "libqos/pci.h" +#include "libqos.h" +#include "pci.h" #include "qapi/qmp/qdict.h" /*** Test Setup & Teardown ***/ diff --git a/tests/qtest/libqos/libqos.h b/tests/qtest/libqos/libqos.h index 8e971c25a3..e0b2bfe7ca 100644 --- a/tests/qtest/libqos/libqos.h +++ b/tests/qtest/libqos/libqos.h @@ -2,8 +2,8 @@ #define LIBQOS_H #include "libqtest.h" -#include "libqos/pci.h" -#include "libqos/malloc.h" +#include "pci.h" +#include "malloc.h" typedef struct QOSState QOSState; diff --git a/tests/qtest/libqos/libqtest.h b/tests/qtest/libqos/libqtest.h new file mode 100644 index 0000000000..f5cf93c386 --- /dev/null +++ b/tests/qtest/libqos/libqtest.h @@ -0,0 +1,736 @@ +/* + * QTest + * + * Copyright IBM, Corp. 2012 + * Copyright Red Hat, Inc. 2012 + * Copyright SUSE LINUX Products GmbH 2013 + * + * Authors: + * Anthony Liguori + * Paolo Bonzini + * Andreas Färber + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ +#ifndef LIBQTEST_H +#define LIBQTEST_H + +#include "qapi/qmp/qobject.h" +#include "qapi/qmp/qdict.h" + +typedef struct QTestState QTestState; + +/** + * qtest_initf: + * @fmt...: Format for creating other arguments to pass to QEMU, formatted + * like sprintf(). + * + * Convenience wrapper around qtest_init(). + * + * Returns: #QTestState instance. + */ +QTestState *qtest_initf(const char *fmt, ...) GCC_FMT_ATTR(1, 2); + +/** + * qtest_vinitf: + * @fmt: Format for creating other arguments to pass to QEMU, formatted + * like vsprintf(). + * @ap: Format arguments. + * + * Convenience wrapper around qtest_init(). + * + * Returns: #QTestState instance. + */ +QTestState *qtest_vinitf(const char *fmt, va_list ap) GCC_FMT_ATTR(1, 0); + +/** + * qtest_init: + * @extra_args: other arguments to pass to QEMU. CAUTION: these + * arguments are subject to word splitting and shell evaluation. + * + * Returns: #QTestState instance. + */ +QTestState *qtest_init(const char *extra_args); + +/** + * qtest_init_without_qmp_handshake: + * @extra_args: other arguments to pass to QEMU. CAUTION: these + * arguments are subject to word splitting and shell evaluation. + * + * Returns: #QTestState instance. + */ +QTestState *qtest_init_without_qmp_handshake(const char *extra_args); + +/** + * qtest_init_with_serial: + * @extra_args: other arguments to pass to QEMU. CAUTION: these + * arguments are subject to word splitting and shell evaluation. + * @sock_fd: pointer to store the socket file descriptor for + * connection with serial. + * + * Returns: #QTestState instance. + */ +QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd); + +/** + * qtest_quit: + * @s: #QTestState instance to operate on. + * + * Shut down the QEMU process associated to @s. + */ +void qtest_quit(QTestState *s); + +/** + * qtest_qmp_fds: + * @s: #QTestState instance to operate on. + * @fds: array of file descriptors + * @fds_num: number of elements in @fds + * @fmt...: QMP message to send to qemu, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * + * Sends a QMP message to QEMU with fds and returns the response. + */ +QDict *qtest_qmp_fds(QTestState *s, int *fds, size_t fds_num, + const char *fmt, ...) + GCC_FMT_ATTR(4, 5); + +/** + * qtest_qmp: + * @s: #QTestState instance to operate on. + * @fmt...: QMP message to send to qemu, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * + * Sends a QMP message to QEMU and returns the response. + */ +QDict *qtest_qmp(QTestState *s, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + +/** + * qtest_qmp_send: + * @s: #QTestState instance to operate on. + * @fmt...: QMP message to send to qemu, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * + * Sends a QMP message to QEMU and leaves the response in the stream. + */ +void qtest_qmp_send(QTestState *s, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + +/** + * qtest_qmp_send_raw: + * @s: #QTestState instance to operate on. + * @fmt...: text to send, formatted like sprintf() + * + * Sends text to the QMP monitor verbatim. Need not be valid JSON; + * this is useful for negative tests. + */ +void qtest_qmp_send_raw(QTestState *s, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + +/** + * qtest_vqmp_fds: + * @s: #QTestState instance to operate on. + * @fds: array of file descriptors + * @fds_num: number of elements in @fds + * @fmt: QMP message to send to QEMU, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * @ap: QMP message arguments + * + * Sends a QMP message to QEMU with fds and returns the response. + */ +QDict *qtest_vqmp_fds(QTestState *s, int *fds, size_t fds_num, + const char *fmt, va_list ap) + GCC_FMT_ATTR(4, 0); + +/** + * qtest_vqmp: + * @s: #QTestState instance to operate on. + * @fmt: QMP message to send to QEMU, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * @ap: QMP message arguments + * + * Sends a QMP message to QEMU and returns the response. + */ +QDict *qtest_vqmp(QTestState *s, const char *fmt, va_list ap) + GCC_FMT_ATTR(2, 0); + +/** + * qtest_qmp_vsend_fds: + * @s: #QTestState instance to operate on. + * @fds: array of file descriptors + * @fds_num: number of elements in @fds + * @fmt: QMP message to send to QEMU, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * @ap: QMP message arguments + * + * Sends a QMP message to QEMU and leaves the response in the stream. + */ +void qtest_qmp_vsend_fds(QTestState *s, int *fds, size_t fds_num, + const char *fmt, va_list ap) + GCC_FMT_ATTR(4, 0); + +/** + * qtest_qmp_vsend: + * @s: #QTestState instance to operate on. + * @fmt: QMP message to send to QEMU, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * @ap: QMP message arguments + * + * Sends a QMP message to QEMU and leaves the response in the stream. + */ +void qtest_qmp_vsend(QTestState *s, const char *fmt, va_list ap) + GCC_FMT_ATTR(2, 0); + +/** + * qtest_receive: + * @s: #QTestState instance to operate on. + * + * Reads a QMP message from QEMU and returns the response. + */ +QDict *qtest_qmp_receive(QTestState *s); + +/** + * qtest_qmp_eventwait: + * @s: #QTestState instance to operate on. + * @s: #event event to wait for. + * + * Continuously polls for QMP responses until it receives the desired event. + */ +void qtest_qmp_eventwait(QTestState *s, const char *event); + +/** + * qtest_qmp_eventwait_ref: + * @s: #QTestState instance to operate on. + * @s: #event event to wait for. + * + * Continuously polls for QMP responses until it receives the desired event. + * Returns a copy of the event for further investigation. + */ +QDict *qtest_qmp_eventwait_ref(QTestState *s, const char *event); + +/** + * qtest_qmp_receive_success: + * @s: #QTestState instance to operate on + * @event_cb: Event callback + * @opaque: Argument for @event_cb + * + * Poll QMP messages until a command success response is received. + * If @event_cb, call it for each event received, passing @opaque, + * the event's name and data. + * Return the success response's "return" member. + */ +QDict *qtest_qmp_receive_success(QTestState *s, + void (*event_cb)(void *opaque, + const char *name, + QDict *data), + void *opaque); + +/** + * qtest_hmp: + * @s: #QTestState instance to operate on. + * @fmt...: HMP command to send to QEMU, formats arguments like sprintf(). + * + * Send HMP command to QEMU via QMP's human-monitor-command. + * QMP events are discarded. + * + * Returns: the command's output. The caller should g_free() it. + */ +char *qtest_hmp(QTestState *s, const char *fmt, ...) GCC_FMT_ATTR(2, 3); + +/** + * qtest_hmpv: + * @s: #QTestState instance to operate on. + * @fmt: HMP command to send to QEMU, formats arguments like vsprintf(). + * @ap: HMP command arguments + * + * Send HMP command to QEMU via QMP's human-monitor-command. + * QMP events are discarded. + * + * Returns: the command's output. The caller should g_free() it. + */ +char *qtest_vhmp(QTestState *s, const char *fmt, va_list ap) + GCC_FMT_ATTR(2, 0); + +void qtest_module_load(QTestState *s, const char *prefix, const char *libname); + +/** + * qtest_get_irq: + * @s: #QTestState instance to operate on. + * @num: Interrupt to observe. + * + * Returns: The level of the @num interrupt. + */ +bool qtest_get_irq(QTestState *s, int num); + +/** + * qtest_irq_intercept_in: + * @s: #QTestState instance to operate on. + * @string: QOM path of a device. + * + * Associate qtest irqs with the GPIO-in pins of the device + * whose path is specified by @string. + */ +void qtest_irq_intercept_in(QTestState *s, const char *string); + +/** + * qtest_irq_intercept_out: + * @s: #QTestState instance to operate on. + * @string: QOM path of a device. + * + * Associate qtest irqs with the GPIO-out pins of the device + * whose path is specified by @string. + */ +void qtest_irq_intercept_out(QTestState *s, const char *string); + +/** + * qtest_set_irq_in: + * @s: QTestState instance to operate on. + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/irq GPIO-in pin to the given level. + */ +void qtest_set_irq_in(QTestState *s, const char *string, const char *name, + int irq, int level); + +/** + * qtest_outb: + * @s: #QTestState instance to operate on. + * @addr: I/O port to write to. + * @value: Value being written. + * + * Write an 8-bit value to an I/O port. + */ +void qtest_outb(QTestState *s, uint16_t addr, uint8_t value); + +/** + * qtest_outw: + * @s: #QTestState instance to operate on. + * @addr: I/O port to write to. + * @value: Value being written. + * + * Write a 16-bit value to an I/O port. + */ +void qtest_outw(QTestState *s, uint16_t addr, uint16_t value); + +/** + * qtest_outl: + * @s: #QTestState instance to operate on. + * @addr: I/O port to write to. + * @value: Value being written. + * + * Write a 32-bit value to an I/O port. + */ +void qtest_outl(QTestState *s, uint16_t addr, uint32_t value); + +/** + * qtest_inb: + * @s: #QTestState instance to operate on. + * @addr: I/O port to read from. + * + * Returns an 8-bit value from an I/O port. + */ +uint8_t qtest_inb(QTestState *s, uint16_t addr); + +/** + * qtest_inw: + * @s: #QTestState instance to operate on. + * @addr: I/O port to read from. + * + * Returns a 16-bit value from an I/O port. + */ +uint16_t qtest_inw(QTestState *s, uint16_t addr); + +/** + * qtest_inl: + * @s: #QTestState instance to operate on. + * @addr: I/O port to read from. + * + * Returns a 32-bit value from an I/O port. + */ +uint32_t qtest_inl(QTestState *s, uint16_t addr); + +/** + * qtest_writeb: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * + * Writes an 8-bit value to memory. + */ +void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value); + +/** + * qtest_writew: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * + * Writes a 16-bit value to memory. + */ +void qtest_writew(QTestState *s, uint64_t addr, uint16_t value); + +/** + * qtest_writel: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * + * Writes a 32-bit value to memory. + */ +void qtest_writel(QTestState *s, uint64_t addr, uint32_t value); + +/** + * qtest_writeq: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * + * Writes a 64-bit value to memory. + */ +void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value); + +/** + * qtest_readb: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * + * Reads an 8-bit value from memory. + * + * Returns: Value read. + */ +uint8_t qtest_readb(QTestState *s, uint64_t addr); + +/** + * qtest_readw: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * + * Reads a 16-bit value from memory. + * + * Returns: Value read. + */ +uint16_t qtest_readw(QTestState *s, uint64_t addr); + +/** + * qtest_readl: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * + * Reads a 32-bit value from memory. + * + * Returns: Value read. + */ +uint32_t qtest_readl(QTestState *s, uint64_t addr); + +/** + * qtest_readq: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * + * Reads a 64-bit value from memory. + * + * Returns: Value read. + */ +uint64_t qtest_readq(QTestState *s, uint64_t addr); + +/** + * qtest_memread: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * + * Read guest memory into a buffer. + */ +void qtest_memread(QTestState *s, uint64_t addr, void *data, size_t size); + +/** + * qtest_rtas_call: + * @s: #QTestState instance to operate on. + * @name: name of the command to call. + * @nargs: Number of args. + * @args: Guest address to read args from. + * @nret: Number of return value. + * @ret: Guest address to write return values to. + * + * Call an RTAS function + */ +uint64_t qtest_rtas_call(QTestState *s, const char *name, + uint32_t nargs, uint64_t args, + uint32_t nret, uint64_t ret); + +/** + * qtest_bufread: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * + * Read guest memory into a buffer and receive using a base64 encoding. + */ +void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size); + +/** + * qtest_memwrite: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * + * Write a buffer to guest memory. + */ +void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t size); + +/** + * qtest_bufwrite: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * + * Write a buffer to guest memory and transmit using a base64 encoding. + */ +void qtest_bufwrite(QTestState *s, uint64_t addr, + const void *data, size_t size); + +/** + * qtest_memset: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @patt: Byte pattern to fill the guest memory region with. + * @size: Number of bytes to write. + * + * Write a pattern to guest memory. + */ +void qtest_memset(QTestState *s, uint64_t addr, uint8_t patt, size_t size); + +/** + * qtest_clock_step_next: + * @s: #QTestState instance to operate on. + * + * Advance the QEMU_CLOCK_VIRTUAL to the next deadline. + * + * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. + */ +int64_t qtest_clock_step_next(QTestState *s); + +/** + * qtest_clock_step: + * @s: QTestState instance to operate on. + * @step: Number of nanoseconds to advance the clock by. + * + * Advance the QEMU_CLOCK_VIRTUAL by @step nanoseconds. + * + * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. + */ +int64_t qtest_clock_step(QTestState *s, int64_t step); + +/** + * qtest_clock_set: + * @s: QTestState instance to operate on. + * @val: Nanoseconds value to advance the clock to. + * + * Advance the QEMU_CLOCK_VIRTUAL to @val nanoseconds since the VM was launched. + * + * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. + */ +int64_t qtest_clock_set(QTestState *s, int64_t val); + +/** + * qtest_big_endian: + * @s: QTestState instance to operate on. + * + * Returns: True if the architecture under test has a big endian configuration. + */ +bool qtest_big_endian(QTestState *s); + +/** + * qtest_get_arch: + * + * Returns: The architecture for the QEMU executable under test. + */ +const char *qtest_get_arch(void); + +/** + * qtest_add_func: + * @str: Test case path. + * @fn: Test case function + * + * Add a GTester testcase with the given name and function. + * The path is prefixed with the architecture under test, as + * returned by qtest_get_arch(). + */ +void qtest_add_func(const char *str, void (*fn)(void)); + +/** + * qtest_add_data_func: + * @str: Test case path. + * @data: Test case data + * @fn: Test case function + * + * Add a GTester testcase with the given name, data and function. + * The path is prefixed with the architecture under test, as + * returned by qtest_get_arch(). + */ +void qtest_add_data_func(const char *str, const void *data, + void (*fn)(const void *)); + +/** + * qtest_add_data_func_full: + * @str: Test case path. + * @data: Test case data + * @fn: Test case function + * @data_free_func: GDestroyNotify for data + * + * Add a GTester testcase with the given name, data and function. + * The path is prefixed with the architecture under test, as + * returned by qtest_get_arch(). + * + * @data is passed to @data_free_func() on test completion. + */ +void qtest_add_data_func_full(const char *str, void *data, + void (*fn)(const void *), + GDestroyNotify data_free_func); + +/** + * qtest_add: + * @testpath: Test case path + * @Fixture: Fixture type + * @tdata: Test case data + * @fsetup: Test case setup function + * @ftest: Test case function + * @fteardown: Test case teardown function + * + * Add a GTester testcase with the given name, data and functions. + * The path is prefixed with the architecture under test, as + * returned by qtest_get_arch(). + */ +#define qtest_add(testpath, Fixture, tdata, fsetup, ftest, fteardown) \ + do { \ + char *path = g_strdup_printf("/%s/%s", qtest_get_arch(), testpath); \ + g_test_add(path, Fixture, tdata, fsetup, ftest, fteardown); \ + g_free(path); \ + } while (0) + +void qtest_add_abrt_handler(GHookFunc fn, const void *data); + +/** + * qtest_qmp_assert_success: + * @qts: QTestState instance to operate on + * @fmt...: QMP message to send to qemu, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * + * Sends a QMP message to QEMU and asserts that a 'return' key is present in + * the response. + */ +void qtest_qmp_assert_success(QTestState *qts, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + +QDict *qmp_fd_receive(int fd); +void qmp_fd_vsend_fds(int fd, int *fds, size_t fds_num, + const char *fmt, va_list ap) GCC_FMT_ATTR(4, 0); +void qmp_fd_vsend(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); +void qmp_fd_send(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); +void qmp_fd_send_raw(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); +void qmp_fd_vsend_raw(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); +QDict *qmp_fdv(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); +QDict *qmp_fd(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); + +/** + * qtest_cb_for_every_machine: + * @cb: Pointer to the callback function + * @skip_old_versioned: true if versioned old machine types should be skipped + * + * Call a callback function for every name of all available machines. + */ +void qtest_cb_for_every_machine(void (*cb)(const char *machine), + bool skip_old_versioned); + +/** + * qtest_qmp_device_add_qdict: + * @qts: QTestState instance to operate on + * @drv: Name of the device that should be added + * @arguments: QDict with properties for the device to intialize + * + * Generic hot-plugging test via the device_add QMP command with properties + * supplied in form of QDict. Use NULL for empty properties list. + */ +void qtest_qmp_device_add_qdict(QTestState *qts, const char *drv, + const QDict *arguments); + +/** + * qtest_qmp_device_add: + * @qts: QTestState instance to operate on + * @driver: Name of the device that should be added + * @id: Identification string + * @fmt...: QMP message to send to qemu, formatted like + * qobject_from_jsonf_nofail(). See parse_escape() for what's + * supported after '%'. + * + * Generic hot-plugging test via the device_add QMP command. + */ +void qtest_qmp_device_add(QTestState *qts, const char *driver, const char *id, + const char *fmt, ...) GCC_FMT_ATTR(4, 5); + +/** + * qtest_qmp_device_del: + * @qts: QTestState instance to operate on + * @id: Identification string + * + * Generic hot-unplugging test via the device_del QMP command. + */ +void qtest_qmp_device_del(QTestState *qts, const char *id); + +/** + * qmp_rsp_is_err: + * @rsp: QMP response to check for error + * + * Test @rsp for error and discard @rsp. + * Returns 'true' if there is error in @rsp and 'false' otherwise. + */ +bool qmp_rsp_is_err(QDict *rsp); + +/** + * qmp_assert_error_class: + * @rsp: QMP response to check for error + * @class: an error class + * + * Assert the response has the given error class and discard @rsp. + */ +void qmp_assert_error_class(QDict *rsp, const char *class); + +/** + * qtest_probe_child: + * @s: QTestState instance to operate on. + * + * Returns: true if the child is still alive. + */ +bool qtest_probe_child(QTestState *s); + +/** + * qtest_set_expected_status: + * @s: QTestState instance to operate on. + * @status: an expected exit status. + * + * Set expected exit status of the child. + */ +void qtest_set_expected_status(QTestState *s, int status); + +QTestState *qtest_inproc_init(QTestState **s, bool log, const char* arch, + void (*send)(void*, const char*)); + +void qtest_client_inproc_recv(void *opaque, const char *str); +#endif diff --git a/tests/qtest/libqos/malloc-pc.c b/tests/qtest/libqos/malloc-pc.c index 6f92ce4135..16ff9609cc 100644 --- a/tests/qtest/libqos/malloc-pc.c +++ b/tests/qtest/libqos/malloc-pc.c @@ -11,8 +11,8 @@ */ #include "qemu/osdep.h" -#include "libqos/malloc-pc.h" -#include "libqos/fw_cfg.h" +#include "malloc-pc.h" +#include "fw_cfg.h" #include "standard-headers/linux/qemu_fw_cfg.h" diff --git a/tests/qtest/libqos/malloc-pc.h b/tests/qtest/libqos/malloc-pc.h index 21e75ae004..d8d79853c8 100644 --- a/tests/qtest/libqos/malloc-pc.h +++ b/tests/qtest/libqos/malloc-pc.h @@ -13,7 +13,7 @@ #ifndef LIBQOS_MALLOC_PC_H #define LIBQOS_MALLOC_PC_H -#include "libqos/malloc.h" +#include "malloc.h" void pc_alloc_init(QGuestAllocator *s, QTestState *qts, QAllocOpts flags); diff --git a/tests/qtest/libqos/malloc-spapr.c b/tests/qtest/libqos/malloc-spapr.c index 2a6b7e3776..84862e4876 100644 --- a/tests/qtest/libqos/malloc-spapr.c +++ b/tests/qtest/libqos/malloc-spapr.c @@ -6,7 +6,7 @@ */ #include "qemu/osdep.h" -#include "libqos/malloc-spapr.h" +#include "malloc-spapr.h" #include "qemu-common.h" diff --git a/tests/qtest/libqos/malloc-spapr.h b/tests/qtest/libqos/malloc-spapr.h index e5fe9bfc4b..f99572fd71 100644 --- a/tests/qtest/libqos/malloc-spapr.h +++ b/tests/qtest/libqos/malloc-spapr.h @@ -8,7 +8,7 @@ #ifndef LIBQOS_MALLOC_SPAPR_H #define LIBQOS_MALLOC_SPAPR_H -#include "libqos/malloc.h" +#include "malloc.h" void spapr_alloc_init(QGuestAllocator *s, QTestState *qts, QAllocOpts flags); diff --git a/tests/qtest/libqos/malloc.c b/tests/qtest/libqos/malloc.c index 615422a5c4..f708b01432 100644 --- a/tests/qtest/libqos/malloc.c +++ b/tests/qtest/libqos/malloc.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqos/malloc.h" +#include "malloc.h" #include "qemu-common.h" #include "qemu/host-utils.h" diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build new file mode 100644 index 0000000000..19931b9248 --- /dev/null +++ b/tests/qtest/libqos/meson.build @@ -0,0 +1,57 @@ +libqos = static_library('qos', + files('../libqtest.c', + 'qgraph.c', + 'qos_external.c', + 'pci.c', + 'fw_cfg.c', + 'malloc.c', + 'libqos.c', + + # spapr + 'malloc-spapr.c', + 'libqos-spapr.c', + 'rtas.c', + 'pci-spapr.c', + + # pc + 'pci-pc.c', + 'malloc-pc.c', + 'libqos-pc.c', + 'ahci.c', + + # usb + 'usb.c', + + # qgraph devices: + 'e1000e.c', + 'i2c.c', + 'i2c-imx.c', + 'i2c-omap.c', + 'sdhci.c', + 'tpci200.c', + 'virtio.c', + 'virtio-9p.c', + 'virtio-balloon.c', + 'virtio-blk.c', + 'virtio-mmio.c', + 'virtio-net.c', + 'virtio-pci.c', + 'virtio-pci-modern.c', + 'virtio-rng.c', + 'virtio-scsi.c', + 'virtio-serial.c', + + # qgraph machines: + 'aarch64-xlnx-zcu102-machine.c', + 'arm-imx25-pdk-machine.c', + 'arm-n800-machine.c', + 'arm-raspi2-machine.c', + 'arm-sabrelite-machine.c', + 'arm-smdkc210-machine.c', + 'arm-virt-machine.c', + 'arm-xilinx-zynq-a9-machine.c', + 'ppc64_pseries-machine.c', + 'x86_64_pc-machine.c', +), build_by_default: false) + +qos = declare_dependency(link_whole: libqos) diff --git a/tests/qtest/libqos/pci-pc.c b/tests/qtest/libqos/pci-pc.c index 3bb2eb3ba8..f97844289f 100644 --- a/tests/qtest/libqos/pci-pc.c +++ b/tests/qtest/libqos/pci-pc.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/pci-pc.h" +#include "pci-pc.h" #include "qapi/qmp/qdict.h" #include "hw/pci/pci_regs.h" diff --git a/tests/qtest/libqos/pci-pc.h b/tests/qtest/libqos/pci-pc.h index 4690005232..49ec9507f2 100644 --- a/tests/qtest/libqos/pci-pc.h +++ b/tests/qtest/libqos/pci-pc.h @@ -13,9 +13,9 @@ #ifndef LIBQOS_PCI_PC_H #define LIBQOS_PCI_PC_H -#include "libqos/pci.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "pci.h" +#include "malloc.h" +#include "qgraph.h" typedef struct QPCIBusPC { QOSGraphObject obj; diff --git a/tests/qtest/libqos/pci-spapr.c b/tests/qtest/libqos/pci-spapr.c index d6f8c01cb7..262226985f 100644 --- a/tests/qtest/libqos/pci-spapr.c +++ b/tests/qtest/libqos/pci-spapr.c @@ -7,9 +7,9 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/pci-spapr.h" -#include "libqos/rtas.h" -#include "libqos/qgraph.h" +#include "pci-spapr.h" +#include "rtas.h" +#include "qgraph.h" #include "hw/pci/pci_regs.h" diff --git a/tests/qtest/libqos/pci-spapr.h b/tests/qtest/libqos/pci-spapr.h index d9e25631c6..20a43718b7 100644 --- a/tests/qtest/libqos/pci-spapr.h +++ b/tests/qtest/libqos/pci-spapr.h @@ -8,9 +8,9 @@ #ifndef LIBQOS_PCI_SPAPR_H #define LIBQOS_PCI_SPAPR_H -#include "libqos/malloc.h" -#include "libqos/pci.h" -#include "libqos/qgraph.h" +#include "malloc.h" +#include "pci.h" +#include "qgraph.h" /* From include/hw/pci-host/spapr.h */ diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index 2309a724e4..e1e96189c8 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -11,11 +11,11 @@ */ #include "qemu/osdep.h" -#include "libqos/pci.h" +#include "pci.h" #include "hw/pci/pci_regs.h" #include "qemu/host-utils.h" -#include "libqos/qgraph.h" +#include "qgraph.h" void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, void (*func)(QPCIDevice *dev, int devfn, void *data), diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 590c175190..ee64fdecbd 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -14,7 +14,7 @@ #define LIBQOS_PCI_H #include "libqtest.h" -#include "libqos/qgraph.h" +#include "qgraph.h" #define QPCI_PIO_LIMIT 0x10000 diff --git a/tests/qtest/libqos/ppc64_pseries-machine.c b/tests/qtest/libqos/ppc64_pseries-machine.c index 5d7bd88f2f..24ca179976 100644 --- a/tests/qtest/libqos/ppc64_pseries-machine.c +++ b/tests/qtest/libqos/ppc64_pseries-machine.c @@ -18,10 +18,10 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/qgraph.h" +#include "qgraph.h" #include "pci-spapr.h" #include "qemu/module.h" -#include "libqos/malloc-spapr.h" +#include "malloc-spapr.h" typedef struct QSPAPR_pci_host QSPAPR_pci_host; typedef struct Qppc64_pseriesMachine Qppc64_pseriesMachine; diff --git a/tests/qtest/libqos/qgraph.c b/tests/qtest/libqos/qgraph.c index eb0af8ab4a..fc49cfa879 100644 --- a/tests/qtest/libqos/qgraph.c +++ b/tests/qtest/libqos/qgraph.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/queue.h" -#include "libqos/qgraph_internal.h" -#include "libqos/qgraph.h" +#include "qgraph_internal.h" +#include "qgraph.h" #define QGRAPH_PRINT_DEBUG 0 #define QOS_ROOT "" diff --git a/tests/qtest/libqos/qgraph.h b/tests/qtest/libqos/qgraph.h index db1244eb59..10543269ce 100644 --- a/tests/qtest/libqos/qgraph.h +++ b/tests/qtest/libqos/qgraph.h @@ -106,7 +106,7 @@ typedef void *(*QOSBeforeTest) (GString *cmd_line, void *arg); * * Creating new driver an its interface * - #include "libqos/qgraph.h" + #include "qgraph.h" struct My_driver { QOSGraphObject obj; @@ -190,7 +190,7 @@ typedef void *(*QOSBeforeTest) (GString *cmd_line, void *arg); * * Creating new test * - * #include "libqos/qgraph.h" + * #include "qgraph.h" * * static void my_test_function(void *obj, void *data) * { @@ -230,7 +230,7 @@ typedef void *(*QOSBeforeTest) (GString *cmd_line, void *arg); * a valid test path will be: * "/x86_64/pc/other_node/my_driver/my_interface/my_test". * - * Additional examples are also in libqos/test-qgraph.c + * Additional examples are also in test-qgraph.c * * Command line: * Command line is built by using node names and optional arguments diff --git a/tests/qtest/libqos/qgraph_internal.h b/tests/qtest/libqos/qgraph_internal.h index aa3123f0f2..968fa69450 100644 --- a/tests/qtest/libqos/qgraph_internal.h +++ b/tests/qtest/libqos/qgraph_internal.h @@ -20,11 +20,11 @@ #define QGRAPH_INTERNAL_H /* This header is declaring additional helper functions defined in - * libqos/qgraph.c + * qgraph.c * It should not be included in tests */ -#include "libqos/qgraph.h" +#include "qgraph.h" typedef struct QOSGraphMachine QOSGraphMachine; typedef enum QOSEdgeType QOSEdgeType; diff --git a/tests/qtest/libqos/qos_external.c b/tests/qtest/libqos/qos_external.c index 0dfc05cfb6..10ee0f75b2 100644 --- a/tests/qtest/libqos/qos_external.c +++ b/tests/qtest/libqos/qos_external.c @@ -24,10 +24,10 @@ #include "qapi/qmp/qstring.h" #include "qemu/module.h" #include "qapi/qmp/qlist.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" -#include "libqos/qgraph_internal.h" -#include "libqos/qos_external.h" +#include "malloc.h" +#include "qgraph.h" +#include "qgraph_internal.h" +#include "qos_external.h" static void machine_apply_to_node(const char *name) { diff --git a/tests/qtest/libqos/qos_external.h b/tests/qtest/libqos/qos_external.h index 56a2f37fde..8446e3df0b 100644 --- a/tests/qtest/libqos/qos_external.h +++ b/tests/qtest/libqos/qos_external.h @@ -19,7 +19,9 @@ #ifndef QOS_EXTERNAL_H #define QOS_EXTERNAL_H -#include "libqos/malloc.h" +#include "qgraph.h" + +#include "malloc.h" #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-qom.h" diff --git a/tests/qtest/libqos/rtas.c b/tests/qtest/libqos/rtas.c index d81ff4274d..db29d5554d 100644 --- a/tests/qtest/libqos/rtas.c +++ b/tests/qtest/libqos/rtas.c @@ -5,7 +5,7 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/rtas.h" +#include "rtas.h" static void qrtas_copy_args(QTestState *qts, uint64_t target_args, uint32_t nargs, uint32_t *args) diff --git a/tests/qtest/libqos/rtas.h b/tests/qtest/libqos/rtas.h index 459e23aaf4..f38f99dfab 100644 --- a/tests/qtest/libqos/rtas.h +++ b/tests/qtest/libqos/rtas.h @@ -5,7 +5,7 @@ #ifndef LIBQOS_RTAS_H #define LIBQOS_RTAS_H -#include "libqos/malloc.h" +#include "malloc.h" int qrtas_get_time_of_day(QTestState *qts, QGuestAllocator *alloc, struct tm *tm, uint32_t *ns); diff --git a/tests/qtest/libqos/sdhci.c b/tests/qtest/libqos/sdhci.c index fbf2e36aec..65f0d07fc5 100644 --- a/tests/qtest/libqos/sdhci.c +++ b/tests/qtest/libqos/sdhci.c @@ -18,7 +18,7 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/qgraph.h" +#include "qgraph.h" #include "pci.h" #include "qemu/module.h" #include "sdhci.h" diff --git a/tests/qtest/libqos/sdhci.h b/tests/qtest/libqos/sdhci.h index 1acd3096e2..22d647b1fd 100644 --- a/tests/qtest/libqos/sdhci.h +++ b/tests/qtest/libqos/sdhci.h @@ -19,7 +19,7 @@ #ifndef QGRAPH_QSDHCI_H #define QGRAPH_QSDHCI_H -#include "libqos/qgraph.h" +#include "qgraph.h" #include "pci.h" typedef struct QSDHCI QSDHCI; diff --git a/tests/qtest/libqos/tpci200.c b/tests/qtest/libqos/tpci200.c index ae590a456e..1787b1f188 100644 --- a/tests/qtest/libqos/tpci200.c +++ b/tests/qtest/libqos/tpci200.c @@ -10,8 +10,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/qgraph.h" -#include "libqos/pci.h" +#include "qgraph.h" +#include "pci.h" typedef struct QTpci200 QTpci200; typedef struct QIpack QIpack; diff --git a/tests/qtest/libqos/usb.c b/tests/qtest/libqos/usb.c index d7a9cb3c72..8b45b02984 100644 --- a/tests/qtest/libqos/usb.c +++ b/tests/qtest/libqos/usb.c @@ -14,7 +14,7 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "hw/usb/uhci-regs.h" -#include "libqos/usb.h" +#include "usb.h" void qusb_pci_init_one(QPCIBus *pcibus, struct qhc *hc, uint32_t devfn, int bar) { diff --git a/tests/qtest/libqos/usb.h b/tests/qtest/libqos/usb.h index eeced39a2f..50030d7fb1 100644 --- a/tests/qtest/libqos/usb.h +++ b/tests/qtest/libqos/usb.h @@ -1,7 +1,7 @@ #ifndef LIBQOS_USB_H #define LIBQOS_USB_H -#include "libqos/pci-pc.h" +#include "pci-pc.h" struct qhc { QPCIDevice *dev; diff --git a/tests/qtest/libqos/virtio-9p.c b/tests/qtest/libqos/virtio-9p.c index c87b56132a..2e300063e3 100644 --- a/tests/qtest/libqos/virtio-9p.c +++ b/tests/qtest/libqos/virtio-9p.c @@ -20,8 +20,8 @@ #include "libqtest.h" #include "qemu/module.h" #include "standard-headers/linux/virtio_ids.h" -#include "libqos/virtio-9p.h" -#include "libqos/qgraph.h" +#include "virtio-9p.h" +#include "qgraph.h" static QGuestAllocator *alloc; diff --git a/tests/qtest/libqos/virtio-9p.h b/tests/qtest/libqos/virtio-9p.h index be9621a5e3..b1e6badc4a 100644 --- a/tests/qtest/libqos/virtio-9p.h +++ b/tests/qtest/libqos/virtio-9p.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_9P_H #define TESTS_LIBQOS_VIRTIO_9P_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtio9P QVirtio9P; typedef struct QVirtio9PPCI QVirtio9PPCI; diff --git a/tests/qtest/libqos/virtio-balloon.c b/tests/qtest/libqos/virtio-balloon.c index 9745f4a83c..a3da5c234d 100644 --- a/tests/qtest/libqos/virtio-balloon.c +++ b/tests/qtest/libqos/virtio-balloon.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-balloon.h" +#include "qgraph.h" +#include "virtio-balloon.h" /* virtio-balloon-device */ static void *qvirtio_balloon_get_driver(QVirtioBalloon *v_balloon, diff --git a/tests/qtest/libqos/virtio-balloon.h b/tests/qtest/libqos/virtio-balloon.h index 5b919303a6..309894c338 100644 --- a/tests/qtest/libqos/virtio-balloon.h +++ b/tests/qtest/libqos/virtio-balloon.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_BALLOON_H #define TESTS_LIBQOS_VIRTIO_BALLOON_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioBalloon QVirtioBalloon; typedef struct QVirtioBalloonPCI QVirtioBalloonPCI; diff --git a/tests/qtest/libqos/virtio-blk.c b/tests/qtest/libqos/virtio-blk.c index 5fc69401be..5da02591bc 100644 --- a/tests/qtest/libqos/virtio-blk.c +++ b/tests/qtest/libqos/virtio-blk.c @@ -20,8 +20,8 @@ #include "libqtest.h" #include "qemu/module.h" #include "standard-headers/linux/virtio_blk.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-blk.h" +#include "qgraph.h" +#include "virtio-blk.h" #define PCI_SLOT 0x04 #define PCI_FN 0x00 diff --git a/tests/qtest/libqos/virtio-blk.h b/tests/qtest/libqos/virtio-blk.h index 5170f13cfe..dcef38851e 100644 --- a/tests/qtest/libqos/virtio-blk.h +++ b/tests/qtest/libqos/virtio-blk.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_BLK_H #define TESTS_LIBQOS_VIRTIO_BLK_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioBlk QVirtioBlk; typedef struct QVirtioBlkPCI QVirtioBlkPCI; diff --git a/tests/qtest/libqos/virtio-mmio.c b/tests/qtest/libqos/virtio-mmio.c index e0a2bd7bc6..75efda3029 100644 --- a/tests/qtest/libqos/virtio-mmio.c +++ b/tests/qtest/libqos/virtio-mmio.c @@ -10,10 +10,10 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/virtio.h" -#include "libqos/virtio-mmio.h" -#include "libqos/malloc.h" -#include "libqos/qgraph.h" +#include "virtio.h" +#include "virtio-mmio.h" +#include "malloc.h" +#include "qgraph.h" #include "standard-headers/linux/virtio_ring.h" static uint8_t qvirtio_mmio_config_readb(QVirtioDevice *d, uint64_t off) diff --git a/tests/qtest/libqos/virtio-mmio.h b/tests/qtest/libqos/virtio-mmio.h index 0e45778b07..30803bc91c 100644 --- a/tests/qtest/libqos/virtio-mmio.h +++ b/tests/qtest/libqos/virtio-mmio.h @@ -10,8 +10,8 @@ #ifndef LIBQOS_VIRTIO_MMIO_H #define LIBQOS_VIRTIO_MMIO_H -#include "libqos/virtio.h" -#include "libqos/qgraph.h" +#include "virtio.h" +#include "qgraph.h" #define QVIRTIO_MMIO_MAGIC_VALUE 0x000 #define QVIRTIO_MMIO_VERSION 0x004 diff --git a/tests/qtest/libqos/virtio-net.c b/tests/qtest/libqos/virtio-net.c index a9e253afe4..1cae07f60d 100644 --- a/tests/qtest/libqos/virtio-net.c +++ b/tests/qtest/libqos/virtio-net.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-net.h" +#include "qgraph.h" +#include "virtio-net.h" #include "hw/virtio/virtio-net.h" diff --git a/tests/qtest/libqos/virtio-net.h b/tests/qtest/libqos/virtio-net.h index b8cbec04af..5ba2161de2 100644 --- a/tests/qtest/libqos/virtio-net.h +++ b/tests/qtest/libqos/virtio-net.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_NET_H #define TESTS_LIBQOS_VIRTIO_NET_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioNet QVirtioNet; typedef struct QVirtioNetPCI QVirtioNetPCI; diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c index 62851c29bb..cd3c0f5bf3 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -9,13 +9,13 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" -#include "libqos/pci.h" -#include "libqos/pci-pc.h" -#include "libqos/malloc.h" -#include "libqos/malloc-pc.h" -#include "libqos/qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" +#include "pci.h" +#include "pci-pc.h" +#include "malloc.h" +#include "malloc-pc.h" +#include "qgraph.h" #include "standard-headers/linux/virtio_ring.h" #include "standard-headers/linux/virtio_pci.h" diff --git a/tests/qtest/libqos/virtio-pci.h b/tests/qtest/libqos/virtio-pci.h index 294d5567ee..f5115cacba 100644 --- a/tests/qtest/libqos/virtio-pci.h +++ b/tests/qtest/libqos/virtio-pci.h @@ -10,9 +10,9 @@ #ifndef LIBQOS_VIRTIO_PCI_H #define LIBQOS_VIRTIO_PCI_H -#include "libqos/virtio.h" -#include "libqos/pci.h" -#include "libqos/qgraph.h" +#include "virtio.h" +#include "pci.h" +#include "qgraph.h" typedef struct QVirtioPCIMSIXOps QVirtioPCIMSIXOps; diff --git a/tests/qtest/libqos/virtio-rng.c b/tests/qtest/libqos/virtio-rng.c index 46f8d95b1f..2e09dd7c48 100644 --- a/tests/qtest/libqos/virtio-rng.c +++ b/tests/qtest/libqos/virtio-rng.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-rng.h" +#include "qgraph.h" +#include "virtio-rng.h" /* virtio-rng-device */ static void *qvirtio_rng_get_driver(QVirtioRng *v_rng, diff --git a/tests/qtest/libqos/virtio-rng.h b/tests/qtest/libqos/virtio-rng.h index 9342372efa..9ca102b599 100644 --- a/tests/qtest/libqos/virtio-rng.h +++ b/tests/qtest/libqos/virtio-rng.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_RNG_H #define TESTS_LIBQOS_VIRTIO_RNG_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioRng QVirtioRng; typedef struct QVirtioRngPCI QVirtioRngPCI; diff --git a/tests/qtest/libqos/virtio-scsi.c b/tests/qtest/libqos/virtio-scsi.c index c8c3598428..5644e32fc3 100644 --- a/tests/qtest/libqos/virtio-scsi.c +++ b/tests/qtest/libqos/virtio-scsi.c @@ -20,8 +20,8 @@ #include "libqtest.h" #include "qemu/module.h" #include "standard-headers/linux/virtio_ids.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-scsi.h" +#include "qgraph.h" +#include "virtio-scsi.h" /* virtio-scsi-device */ static void *qvirtio_scsi_get_driver(QVirtioSCSI *v_scsi, diff --git a/tests/qtest/libqos/virtio-scsi.h b/tests/qtest/libqos/virtio-scsi.h index 9e3774d99a..531315e6ad 100644 --- a/tests/qtest/libqos/virtio-scsi.h +++ b/tests/qtest/libqos/virtio-scsi.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_SCSI_H #define TESTS_LIBQOS_VIRTIO_SCSI_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioSCSI QVirtioSCSI; typedef struct QVirtioSCSIPCI QVirtioSCSIPCI; diff --git a/tests/qtest/libqos/virtio-serial.c b/tests/qtest/libqos/virtio-serial.c index b95654085d..ee34afd95a 100644 --- a/tests/qtest/libqos/virtio-serial.c +++ b/tests/qtest/libqos/virtio-serial.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "qemu/module.h" -#include "libqos/qgraph.h" -#include "libqos/virtio-serial.h" +#include "qgraph.h" +#include "virtio-serial.h" static void *qvirtio_serial_get_driver(QVirtioSerial *v_serial, const char *interface) diff --git a/tests/qtest/libqos/virtio-serial.h b/tests/qtest/libqos/virtio-serial.h index 3328c6cf19..3db43b2bb8 100644 --- a/tests/qtest/libqos/virtio-serial.h +++ b/tests/qtest/libqos/virtio-serial.h @@ -19,9 +19,9 @@ #ifndef TESTS_LIBQOS_VIRTIO_SERIAL_H #define TESTS_LIBQOS_VIRTIO_SERIAL_H -#include "libqos/qgraph.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" typedef struct QVirtioSerial QVirtioSerial; typedef struct QVirtioSerialPCI QVirtioSerialPCI; diff --git a/tests/qtest/libqos/virtio.c b/tests/qtest/libqos/virtio.c index 9aa360620c..6fe7bf9555 100644 --- a/tests/qtest/libqos/virtio.c +++ b/tests/qtest/libqos/virtio.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "qemu/bswap.h" #include "libqtest.h" -#include "libqos/virtio.h" +#include "virtio.h" #include "standard-headers/linux/virtio_config.h" #include "standard-headers/linux/virtio_ring.h" diff --git a/tests/qtest/libqos/virtio.h b/tests/qtest/libqos/virtio.h index 529ef7555a..b8bd06e1b8 100644 --- a/tests/qtest/libqos/virtio.h +++ b/tests/qtest/libqos/virtio.h @@ -10,7 +10,7 @@ #ifndef LIBQOS_VIRTIO_H #define LIBQOS_VIRTIO_H -#include "libqos/malloc.h" +#include "malloc.h" #include "standard-headers/linux/virtio_ring.h" #define QVIRTIO_F_BAD_FEATURE 0x40000000ull diff --git a/tests/qtest/libqos/x86_64_pc-machine.c b/tests/qtest/libqos/x86_64_pc-machine.c index 0edb1c9144..ad96742a92 100644 --- a/tests/qtest/libqos/x86_64_pc-machine.c +++ b/tests/qtest/libqos/x86_64_pc-machine.c @@ -18,7 +18,7 @@ #include "qemu/osdep.h" #include "libqtest.h" -#include "libqos/qgraph.h" +#include "qgraph.h" #include "pci-pc.h" #include "qemu/module.h" #include "malloc-pc.h" diff --git a/tests/qtest/libqtest-single.h b/tests/qtest/libqtest-single.h index 6f1bb1331c..176979a2ce 100644 --- a/tests/qtest/libqtest-single.h +++ b/tests/qtest/libqtest-single.h @@ -11,7 +11,7 @@ #ifndef LIBQTEST_SINGLE_H #define LIBQTEST_SINGLE_H -#include "libqtest.h" +#include "libqos/libqtest.h" QTestState *global_qtest __attribute__((common, weak)); diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index fd4680590d..26f1223642 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -20,7 +20,7 @@ #include #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu-common.h" #include "qemu/ctype.h" #include "qemu/cutils.h" diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h deleted file mode 100644 index f5cf93c386..0000000000 --- a/tests/qtest/libqtest.h +++ /dev/null @@ -1,736 +0,0 @@ -/* - * QTest - * - * Copyright IBM, Corp. 2012 - * Copyright Red Hat, Inc. 2012 - * Copyright SUSE LINUX Products GmbH 2013 - * - * Authors: - * Anthony Liguori - * Paolo Bonzini - * Andreas Färber - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ -#ifndef LIBQTEST_H -#define LIBQTEST_H - -#include "qapi/qmp/qobject.h" -#include "qapi/qmp/qdict.h" - -typedef struct QTestState QTestState; - -/** - * qtest_initf: - * @fmt...: Format for creating other arguments to pass to QEMU, formatted - * like sprintf(). - * - * Convenience wrapper around qtest_init(). - * - * Returns: #QTestState instance. - */ -QTestState *qtest_initf(const char *fmt, ...) GCC_FMT_ATTR(1, 2); - -/** - * qtest_vinitf: - * @fmt: Format for creating other arguments to pass to QEMU, formatted - * like vsprintf(). - * @ap: Format arguments. - * - * Convenience wrapper around qtest_init(). - * - * Returns: #QTestState instance. - */ -QTestState *qtest_vinitf(const char *fmt, va_list ap) GCC_FMT_ATTR(1, 0); - -/** - * qtest_init: - * @extra_args: other arguments to pass to QEMU. CAUTION: these - * arguments are subject to word splitting and shell evaluation. - * - * Returns: #QTestState instance. - */ -QTestState *qtest_init(const char *extra_args); - -/** - * qtest_init_without_qmp_handshake: - * @extra_args: other arguments to pass to QEMU. CAUTION: these - * arguments are subject to word splitting and shell evaluation. - * - * Returns: #QTestState instance. - */ -QTestState *qtest_init_without_qmp_handshake(const char *extra_args); - -/** - * qtest_init_with_serial: - * @extra_args: other arguments to pass to QEMU. CAUTION: these - * arguments are subject to word splitting and shell evaluation. - * @sock_fd: pointer to store the socket file descriptor for - * connection with serial. - * - * Returns: #QTestState instance. - */ -QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd); - -/** - * qtest_quit: - * @s: #QTestState instance to operate on. - * - * Shut down the QEMU process associated to @s. - */ -void qtest_quit(QTestState *s); - -/** - * qtest_qmp_fds: - * @s: #QTestState instance to operate on. - * @fds: array of file descriptors - * @fds_num: number of elements in @fds - * @fmt...: QMP message to send to qemu, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * - * Sends a QMP message to QEMU with fds and returns the response. - */ -QDict *qtest_qmp_fds(QTestState *s, int *fds, size_t fds_num, - const char *fmt, ...) - GCC_FMT_ATTR(4, 5); - -/** - * qtest_qmp: - * @s: #QTestState instance to operate on. - * @fmt...: QMP message to send to qemu, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * - * Sends a QMP message to QEMU and returns the response. - */ -QDict *qtest_qmp(QTestState *s, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - -/** - * qtest_qmp_send: - * @s: #QTestState instance to operate on. - * @fmt...: QMP message to send to qemu, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * - * Sends a QMP message to QEMU and leaves the response in the stream. - */ -void qtest_qmp_send(QTestState *s, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - -/** - * qtest_qmp_send_raw: - * @s: #QTestState instance to operate on. - * @fmt...: text to send, formatted like sprintf() - * - * Sends text to the QMP monitor verbatim. Need not be valid JSON; - * this is useful for negative tests. - */ -void qtest_qmp_send_raw(QTestState *s, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - -/** - * qtest_vqmp_fds: - * @s: #QTestState instance to operate on. - * @fds: array of file descriptors - * @fds_num: number of elements in @fds - * @fmt: QMP message to send to QEMU, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * @ap: QMP message arguments - * - * Sends a QMP message to QEMU with fds and returns the response. - */ -QDict *qtest_vqmp_fds(QTestState *s, int *fds, size_t fds_num, - const char *fmt, va_list ap) - GCC_FMT_ATTR(4, 0); - -/** - * qtest_vqmp: - * @s: #QTestState instance to operate on. - * @fmt: QMP message to send to QEMU, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * @ap: QMP message arguments - * - * Sends a QMP message to QEMU and returns the response. - */ -QDict *qtest_vqmp(QTestState *s, const char *fmt, va_list ap) - GCC_FMT_ATTR(2, 0); - -/** - * qtest_qmp_vsend_fds: - * @s: #QTestState instance to operate on. - * @fds: array of file descriptors - * @fds_num: number of elements in @fds - * @fmt: QMP message to send to QEMU, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * @ap: QMP message arguments - * - * Sends a QMP message to QEMU and leaves the response in the stream. - */ -void qtest_qmp_vsend_fds(QTestState *s, int *fds, size_t fds_num, - const char *fmt, va_list ap) - GCC_FMT_ATTR(4, 0); - -/** - * qtest_qmp_vsend: - * @s: #QTestState instance to operate on. - * @fmt: QMP message to send to QEMU, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * @ap: QMP message arguments - * - * Sends a QMP message to QEMU and leaves the response in the stream. - */ -void qtest_qmp_vsend(QTestState *s, const char *fmt, va_list ap) - GCC_FMT_ATTR(2, 0); - -/** - * qtest_receive: - * @s: #QTestState instance to operate on. - * - * Reads a QMP message from QEMU and returns the response. - */ -QDict *qtest_qmp_receive(QTestState *s); - -/** - * qtest_qmp_eventwait: - * @s: #QTestState instance to operate on. - * @s: #event event to wait for. - * - * Continuously polls for QMP responses until it receives the desired event. - */ -void qtest_qmp_eventwait(QTestState *s, const char *event); - -/** - * qtest_qmp_eventwait_ref: - * @s: #QTestState instance to operate on. - * @s: #event event to wait for. - * - * Continuously polls for QMP responses until it receives the desired event. - * Returns a copy of the event for further investigation. - */ -QDict *qtest_qmp_eventwait_ref(QTestState *s, const char *event); - -/** - * qtest_qmp_receive_success: - * @s: #QTestState instance to operate on - * @event_cb: Event callback - * @opaque: Argument for @event_cb - * - * Poll QMP messages until a command success response is received. - * If @event_cb, call it for each event received, passing @opaque, - * the event's name and data. - * Return the success response's "return" member. - */ -QDict *qtest_qmp_receive_success(QTestState *s, - void (*event_cb)(void *opaque, - const char *name, - QDict *data), - void *opaque); - -/** - * qtest_hmp: - * @s: #QTestState instance to operate on. - * @fmt...: HMP command to send to QEMU, formats arguments like sprintf(). - * - * Send HMP command to QEMU via QMP's human-monitor-command. - * QMP events are discarded. - * - * Returns: the command's output. The caller should g_free() it. - */ -char *qtest_hmp(QTestState *s, const char *fmt, ...) GCC_FMT_ATTR(2, 3); - -/** - * qtest_hmpv: - * @s: #QTestState instance to operate on. - * @fmt: HMP command to send to QEMU, formats arguments like vsprintf(). - * @ap: HMP command arguments - * - * Send HMP command to QEMU via QMP's human-monitor-command. - * QMP events are discarded. - * - * Returns: the command's output. The caller should g_free() it. - */ -char *qtest_vhmp(QTestState *s, const char *fmt, va_list ap) - GCC_FMT_ATTR(2, 0); - -void qtest_module_load(QTestState *s, const char *prefix, const char *libname); - -/** - * qtest_get_irq: - * @s: #QTestState instance to operate on. - * @num: Interrupt to observe. - * - * Returns: The level of the @num interrupt. - */ -bool qtest_get_irq(QTestState *s, int num); - -/** - * qtest_irq_intercept_in: - * @s: #QTestState instance to operate on. - * @string: QOM path of a device. - * - * Associate qtest irqs with the GPIO-in pins of the device - * whose path is specified by @string. - */ -void qtest_irq_intercept_in(QTestState *s, const char *string); - -/** - * qtest_irq_intercept_out: - * @s: #QTestState instance to operate on. - * @string: QOM path of a device. - * - * Associate qtest irqs with the GPIO-out pins of the device - * whose path is specified by @string. - */ -void qtest_irq_intercept_out(QTestState *s, const char *string); - -/** - * qtest_set_irq_in: - * @s: QTestState instance to operate on. - * @string: QOM path of a device - * @name: IRQ name - * @irq: IRQ number - * @level: IRQ level - * - * Force given device/irq GPIO-in pin to the given level. - */ -void qtest_set_irq_in(QTestState *s, const char *string, const char *name, - int irq, int level); - -/** - * qtest_outb: - * @s: #QTestState instance to operate on. - * @addr: I/O port to write to. - * @value: Value being written. - * - * Write an 8-bit value to an I/O port. - */ -void qtest_outb(QTestState *s, uint16_t addr, uint8_t value); - -/** - * qtest_outw: - * @s: #QTestState instance to operate on. - * @addr: I/O port to write to. - * @value: Value being written. - * - * Write a 16-bit value to an I/O port. - */ -void qtest_outw(QTestState *s, uint16_t addr, uint16_t value); - -/** - * qtest_outl: - * @s: #QTestState instance to operate on. - * @addr: I/O port to write to. - * @value: Value being written. - * - * Write a 32-bit value to an I/O port. - */ -void qtest_outl(QTestState *s, uint16_t addr, uint32_t value); - -/** - * qtest_inb: - * @s: #QTestState instance to operate on. - * @addr: I/O port to read from. - * - * Returns an 8-bit value from an I/O port. - */ -uint8_t qtest_inb(QTestState *s, uint16_t addr); - -/** - * qtest_inw: - * @s: #QTestState instance to operate on. - * @addr: I/O port to read from. - * - * Returns a 16-bit value from an I/O port. - */ -uint16_t qtest_inw(QTestState *s, uint16_t addr); - -/** - * qtest_inl: - * @s: #QTestState instance to operate on. - * @addr: I/O port to read from. - * - * Returns a 32-bit value from an I/O port. - */ -uint32_t qtest_inl(QTestState *s, uint16_t addr); - -/** - * qtest_writeb: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @value: Value being written. - * - * Writes an 8-bit value to memory. - */ -void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value); - -/** - * qtest_writew: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @value: Value being written. - * - * Writes a 16-bit value to memory. - */ -void qtest_writew(QTestState *s, uint64_t addr, uint16_t value); - -/** - * qtest_writel: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @value: Value being written. - * - * Writes a 32-bit value to memory. - */ -void qtest_writel(QTestState *s, uint64_t addr, uint32_t value); - -/** - * qtest_writeq: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @value: Value being written. - * - * Writes a 64-bit value to memory. - */ -void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value); - -/** - * qtest_readb: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * - * Reads an 8-bit value from memory. - * - * Returns: Value read. - */ -uint8_t qtest_readb(QTestState *s, uint64_t addr); - -/** - * qtest_readw: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * - * Reads a 16-bit value from memory. - * - * Returns: Value read. - */ -uint16_t qtest_readw(QTestState *s, uint64_t addr); - -/** - * qtest_readl: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * - * Reads a 32-bit value from memory. - * - * Returns: Value read. - */ -uint32_t qtest_readl(QTestState *s, uint64_t addr); - -/** - * qtest_readq: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * - * Reads a 64-bit value from memory. - * - * Returns: Value read. - */ -uint64_t qtest_readq(QTestState *s, uint64_t addr); - -/** - * qtest_memread: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * @data: Pointer to where memory contents will be stored. - * @size: Number of bytes to read. - * - * Read guest memory into a buffer. - */ -void qtest_memread(QTestState *s, uint64_t addr, void *data, size_t size); - -/** - * qtest_rtas_call: - * @s: #QTestState instance to operate on. - * @name: name of the command to call. - * @nargs: Number of args. - * @args: Guest address to read args from. - * @nret: Number of return value. - * @ret: Guest address to write return values to. - * - * Call an RTAS function - */ -uint64_t qtest_rtas_call(QTestState *s, const char *name, - uint32_t nargs, uint64_t args, - uint32_t nret, uint64_t ret); - -/** - * qtest_bufread: - * @s: #QTestState instance to operate on. - * @addr: Guest address to read from. - * @data: Pointer to where memory contents will be stored. - * @size: Number of bytes to read. - * - * Read guest memory into a buffer and receive using a base64 encoding. - */ -void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size); - -/** - * qtest_memwrite: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @data: Pointer to the bytes that will be written to guest memory. - * @size: Number of bytes to write. - * - * Write a buffer to guest memory. - */ -void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t size); - -/** - * qtest_bufwrite: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @data: Pointer to the bytes that will be written to guest memory. - * @size: Number of bytes to write. - * - * Write a buffer to guest memory and transmit using a base64 encoding. - */ -void qtest_bufwrite(QTestState *s, uint64_t addr, - const void *data, size_t size); - -/** - * qtest_memset: - * @s: #QTestState instance to operate on. - * @addr: Guest address to write to. - * @patt: Byte pattern to fill the guest memory region with. - * @size: Number of bytes to write. - * - * Write a pattern to guest memory. - */ -void qtest_memset(QTestState *s, uint64_t addr, uint8_t patt, size_t size); - -/** - * qtest_clock_step_next: - * @s: #QTestState instance to operate on. - * - * Advance the QEMU_CLOCK_VIRTUAL to the next deadline. - * - * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. - */ -int64_t qtest_clock_step_next(QTestState *s); - -/** - * qtest_clock_step: - * @s: QTestState instance to operate on. - * @step: Number of nanoseconds to advance the clock by. - * - * Advance the QEMU_CLOCK_VIRTUAL by @step nanoseconds. - * - * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. - */ -int64_t qtest_clock_step(QTestState *s, int64_t step); - -/** - * qtest_clock_set: - * @s: QTestState instance to operate on. - * @val: Nanoseconds value to advance the clock to. - * - * Advance the QEMU_CLOCK_VIRTUAL to @val nanoseconds since the VM was launched. - * - * Returns: The current value of the QEMU_CLOCK_VIRTUAL in nanoseconds. - */ -int64_t qtest_clock_set(QTestState *s, int64_t val); - -/** - * qtest_big_endian: - * @s: QTestState instance to operate on. - * - * Returns: True if the architecture under test has a big endian configuration. - */ -bool qtest_big_endian(QTestState *s); - -/** - * qtest_get_arch: - * - * Returns: The architecture for the QEMU executable under test. - */ -const char *qtest_get_arch(void); - -/** - * qtest_add_func: - * @str: Test case path. - * @fn: Test case function - * - * Add a GTester testcase with the given name and function. - * The path is prefixed with the architecture under test, as - * returned by qtest_get_arch(). - */ -void qtest_add_func(const char *str, void (*fn)(void)); - -/** - * qtest_add_data_func: - * @str: Test case path. - * @data: Test case data - * @fn: Test case function - * - * Add a GTester testcase with the given name, data and function. - * The path is prefixed with the architecture under test, as - * returned by qtest_get_arch(). - */ -void qtest_add_data_func(const char *str, const void *data, - void (*fn)(const void *)); - -/** - * qtest_add_data_func_full: - * @str: Test case path. - * @data: Test case data - * @fn: Test case function - * @data_free_func: GDestroyNotify for data - * - * Add a GTester testcase with the given name, data and function. - * The path is prefixed with the architecture under test, as - * returned by qtest_get_arch(). - * - * @data is passed to @data_free_func() on test completion. - */ -void qtest_add_data_func_full(const char *str, void *data, - void (*fn)(const void *), - GDestroyNotify data_free_func); - -/** - * qtest_add: - * @testpath: Test case path - * @Fixture: Fixture type - * @tdata: Test case data - * @fsetup: Test case setup function - * @ftest: Test case function - * @fteardown: Test case teardown function - * - * Add a GTester testcase with the given name, data and functions. - * The path is prefixed with the architecture under test, as - * returned by qtest_get_arch(). - */ -#define qtest_add(testpath, Fixture, tdata, fsetup, ftest, fteardown) \ - do { \ - char *path = g_strdup_printf("/%s/%s", qtest_get_arch(), testpath); \ - g_test_add(path, Fixture, tdata, fsetup, ftest, fteardown); \ - g_free(path); \ - } while (0) - -void qtest_add_abrt_handler(GHookFunc fn, const void *data); - -/** - * qtest_qmp_assert_success: - * @qts: QTestState instance to operate on - * @fmt...: QMP message to send to qemu, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * - * Sends a QMP message to QEMU and asserts that a 'return' key is present in - * the response. - */ -void qtest_qmp_assert_success(QTestState *qts, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - -QDict *qmp_fd_receive(int fd); -void qmp_fd_vsend_fds(int fd, int *fds, size_t fds_num, - const char *fmt, va_list ap) GCC_FMT_ATTR(4, 0); -void qmp_fd_vsend(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); -void qmp_fd_send(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); -void qmp_fd_send_raw(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); -void qmp_fd_vsend_raw(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); -QDict *qmp_fdv(int fd, const char *fmt, va_list ap) GCC_FMT_ATTR(2, 0); -QDict *qmp_fd(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); - -/** - * qtest_cb_for_every_machine: - * @cb: Pointer to the callback function - * @skip_old_versioned: true if versioned old machine types should be skipped - * - * Call a callback function for every name of all available machines. - */ -void qtest_cb_for_every_machine(void (*cb)(const char *machine), - bool skip_old_versioned); - -/** - * qtest_qmp_device_add_qdict: - * @qts: QTestState instance to operate on - * @drv: Name of the device that should be added - * @arguments: QDict with properties for the device to intialize - * - * Generic hot-plugging test via the device_add QMP command with properties - * supplied in form of QDict. Use NULL for empty properties list. - */ -void qtest_qmp_device_add_qdict(QTestState *qts, const char *drv, - const QDict *arguments); - -/** - * qtest_qmp_device_add: - * @qts: QTestState instance to operate on - * @driver: Name of the device that should be added - * @id: Identification string - * @fmt...: QMP message to send to qemu, formatted like - * qobject_from_jsonf_nofail(). See parse_escape() for what's - * supported after '%'. - * - * Generic hot-plugging test via the device_add QMP command. - */ -void qtest_qmp_device_add(QTestState *qts, const char *driver, const char *id, - const char *fmt, ...) GCC_FMT_ATTR(4, 5); - -/** - * qtest_qmp_device_del: - * @qts: QTestState instance to operate on - * @id: Identification string - * - * Generic hot-unplugging test via the device_del QMP command. - */ -void qtest_qmp_device_del(QTestState *qts, const char *id); - -/** - * qmp_rsp_is_err: - * @rsp: QMP response to check for error - * - * Test @rsp for error and discard @rsp. - * Returns 'true' if there is error in @rsp and 'false' otherwise. - */ -bool qmp_rsp_is_err(QDict *rsp); - -/** - * qmp_assert_error_class: - * @rsp: QMP response to check for error - * @class: an error class - * - * Assert the response has the given error class and discard @rsp. - */ -void qmp_assert_error_class(QDict *rsp, const char *class); - -/** - * qtest_probe_child: - * @s: QTestState instance to operate on. - * - * Returns: true if the child is still alive. - */ -bool qtest_probe_child(QTestState *s); - -/** - * qtest_set_expected_status: - * @s: QTestState instance to operate on. - * @status: an expected exit status. - * - * Set expected exit status of the child. - */ -void qtest_set_expected_status(QTestState *s, int status); - -QTestState *qtest_inproc_init(QTestState **s, bool log, const char* arch, - void (*send)(void*, const char*)); - -void qtest_client_inproc_recv(void *opaque, const char *str); -#endif diff --git a/tests/qtest/m48t59-test.c b/tests/qtest/m48t59-test.c index b94a1230f7..6db3234100 100644 --- a/tests/qtest/m48t59-test.c +++ b/tests/qtest/m48t59-test.c @@ -14,7 +14,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #define RTC_SECONDS 0x9 #define RTC_MINUTES 0xa diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c index 57107f1aec..aab06b9fc2 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -14,7 +14,7 @@ #include "qemu-common.h" #include "qemu/cutils.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/megasas-test.c b/tests/qtest/megasas-test.c index d6796b9bd7..eae70ff95f 100644 --- a/tests/qtest/megasas-test.c +++ b/tests/qtest/megasas-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/bswap.h" #include "qemu/module.h" #include "libqos/qgraph.h" diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build new file mode 100644 index 0000000000..30cb88d919 --- /dev/null +++ b/tests/qtest/meson.build @@ -0,0 +1,257 @@ +# All QTests for now are POSIX-only, but the dependencies are +# really in libqtest, not in the testcases themselves. +if not config_host.has_key('CONFIG_POSIX') + subdir_done() +endif + +qtests_generic = [ + 'cdrom-test', + 'device-introspect-test', + 'machine-none-test', + 'qmp-test', + 'qmp-cmd-test', + 'qom-test', + 'test-hmp', + 'qos-test', +] +if config_host.has_key('CONFIG_MODULES') + qtests_generic += [ 'modules-test' ] +endif + +qtests_pci = \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + \ + (config_all_devices.has_key('CONFIG_IVSHMEM_DEVICE') ? ['ivshmem-test'] : []) + +qtests_i386 = \ + (config_host.has_key('CONFIG_SLIRP') ? ['pxe-test', 'test-netfilter'] : []) + \ + (config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) + \ + (have_tools ? ['ahci-test'] : []) + \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_SGA') ? ['boot-serial-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['test-filter-redirector'] : []) + \ + (config_all_devices.has_key('CONFIG_ISA_IPMI_KCS') ? ['ipmi-kcs-test'] : []) + \ + (config_host.has_key('CONFIG_LINUX') and \ + config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \ + (config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \ + (config_all_devices.has_key('CONFIG_PVPANIC') ? ['pvpanic-test'] : []) + \ + (config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \ + (config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \ + (config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \ + (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : []) + \ + (config_all_devices.has_key('CONFIG_USB_UHCI') and \ + config_all_devices.has_key('CONFIG_USB_EHCI') ? ['usb-hcd-ehci-test'] : []) + \ + (config_all_devices.has_key('CONFIG_USB_XHCI_NEC') ? ['usb-hcd-xhci-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_CRB') ? ['tpm-crb-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_CRB') ? ['tpm-crb-swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : []) + \ + qtests_pci + \ + ['fdc-test', + 'ide-test', + 'ahci-test', + 'hd-geo-test', + 'boot-order-test', + 'bios-tables-test', + 'rtc-test', + 'i440fx-test', + 'fw_cfg-test', + 'device-plug-test', + 'drive_del-test', + 'tco-test', + 'cpu-plug-test', + 'q35-test', + 'vmgenid-test', + 'migration-test', + 'test-x86-cpuid-compat', + 'numa-test'] + +dbus_daemon = find_program('dbus-daemon', required: false) +if dbus_daemon.found() and config_host.has_key('GDBUS_CODEGEN') + # Temporarily disabled due to Patchew failures: + #qtests_i386 += ['dbus-vmstate-test'] + dbus_vmstate1 = custom_target('dbus-vmstate description', + output: ['dbus-vmstate1.h', 'dbus-vmstate1.c'], + input: files('dbus-vmstate1.xml'), + command: [config_host['GDBUS_CODEGEN'], + '@INPUT@', + '--interface-prefix', 'org.qemu', + '--generate-c-code', '@BASENAME@']).to_list() +else + dbus_vmstate1 = [] +endif + +qtests_x86_64 = qtests_i386 + +qtests_alpha = [ 'boot-serial-test' ] + \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + +qtests_avr = [ 'boot-serial-test' ] + +qtests_hppa = [ 'boot-serial-test' ] + \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + +qtests_m68k = [ 'boot-serial-test' ] +qtests_microblaze = [ 'boot-serial-test' ] +qtests_microblazeel = qtests_microblaze + +qtests_mips = \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + +qtests_mips64 = \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + +qtests_mips64el = \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + +qtests_moxie = [ 'boot-serial-test' ] + +qtests_ppc = \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + (config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \ + ['boot-order-test', 'prom-env-test', 'drive_del-test', 'boot-serial-test'] \ + +qtests_ppc64 = \ + (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ + (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + \ + (config_host.has_key('CONFIG_SLIRP') ? ['pxe-test', 'test-netfilter'] : []) + \ + (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : []) + \ + (config_all_devices.has_key('CONFIG_USB_XHCI_NEC') ? ['usb-hcd-xhci-test'] : []) + \ + (config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) + \ + qtests_pci + ['migration-test', 'numa-test', 'cpu-plug-test'] + +qtests_sh4 = (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) +qtests_sh4eb = (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + +qtests_sparc = ['prom-env-test', 'm48t59-test', 'boot-serial-test'] + +qtests_sparc64 = \ + (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ + ['prom-env-test', 'boot-serial-test'] + +qtests_arm = \ + (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ + ['arm-cpu-features', + 'microbit-test', + 'm25p80-test', + 'test-arm-mptimer', + 'boot-serial-test', + 'hexloader-test'] + +# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional +qtests_aarch64 = \ + (cpu != 'arm' ? ['bios-tables-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ + (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ + ['numa-test', + 'boot-serial-test', + 'migration-test'] + +qtests_s390x = \ + (config_host.has_key('CONFIG_SLIRP') ? ['pxe-test', 'test-netfilter'] : []) + \ + (config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) + \ + (config_host.has_key('CONFIG_POSIX') ? ['test-filter-redirector'] : []) + \ + ['boot-serial-test', + 'drive_del-test', + 'device-plug-test', + 'virtio-ccw-test', + 'cpu-plug-test', + 'migration-test'] + +qos_test_ss = ss.source_set() +qos_test_ss.add( + 'ac97-test.c', + 'ds1338-test.c', + 'e1000-test.c', + 'e1000e-test.c', + 'eepro100-test.c', + 'es1370-test.c', + 'ipoctal232-test.c', + 'megasas-test.c', + 'ne2000-test.c', + 'tulip-test.c', + 'nvme-test.c', + 'pca9552-test.c', + 'pci-test.c', + 'pcnet-test.c', + 'sdhci-test.c', + 'spapr-phb-test.c', + 'tmp105-test.c', + 'usb-hcd-ohci-test.c', + 'virtio-test.c', + 'virtio-blk-test.c', + 'virtio-net-test.c', + 'virtio-rng-test.c', + 'virtio-scsi-test.c', + 'virtio-serial-test.c', + 'vmxnet3-test.c', +) +qos_test_ss.add(when: 'CONFIG_VIRTFS', if_true: files('virtio-9p-test.c')) +qos_test_ss.add(when: 'CONFIG_VHOST_USER', if_true: files('vhost-user-test.c')) + +extra_qtest_deps = { + 'bios-tables-test': [io], + 'ivshmem-test': [rt], + 'qos-test': [chardev, io], + 'tpm-crb-swtpm-test': [io], + 'tpm-crb-test': [io], + 'tpm-tis-swtpm-test': [io], + 'tpm-tis-test': [io], + 'tpm-tis-device-swtpm-test': [io], + 'tpm-tis-device-test': [io], +} +extra_qtest_srcs = { + 'bios-tables-test': files('boot-sector.c', 'acpi-utils.c', 'tpm-emu.c'), + 'pxe-test': files('boot-sector.c'), + 'cdrom-test': files('boot-sector.c'), + 'migration-test': files('migration-helpers.c'), + 'ivshmem-test': files('../../contrib/ivshmem-server/ivshmem-server.c'), + 'dbus-vmstate-test': files('migration-helpers.c') + dbus_vmstate1, + 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'), + 'tpm-crb-swtpm-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tests.c'), + 'tpm-crb-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tests.c'), + 'tpm-tis-device-swtpm-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tis-util.c', 'tpm-tests.c'), + 'tpm-tis-device-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tis-util.c', 'tpm-tests.c'), + 'tpm-tis-swtpm-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tis-util.c', 'tpm-tests.c'), + 'tpm-tis-test': files('tpm-emu.c', 'tpm-util.c', 'tpm-tis-util.c', 'tpm-tests.c'), + 'qos-test': qos_test_ss.apply(config_host, strict: false).sources() +} + + +qtest_executables = {} +foreach dir : target_dirs + if not dir.endswith('-softmmu') + continue + endif + + target_base = dir.split('-')[0] + qtests = get_variable('qtests_' + target_base, []) + qtests_generic + + qtest_env = environment() + qtest_env.set('QTEST_QEMU_IMG', './qemu-img') + qtest_env.set('G_TEST_DBUS_DAEMON', meson.source_root() / 'tests/dbus-vmstate-daemon.sh') + qtest_env.set('QTEST_QEMU_BINARY', '@0@-softmmu/qemu-system-@0@'.format(target_base)) + + foreach test : qtests + # Executables are shared across targets, declare them only the first time we + # encounter them + if not qtest_executables.has_key(test) + qtest_executables += { + test: executable(test, + files(test + '.c') + extra_qtest_srcs.get(test, []), + dependencies: [qemuutil, qos] + extra_qtest_deps.get(test, [])) + } + endif + # FIXME: missing dependency on the emulator binary and qemu-img + test('qtest-@0@: @1@'.format(target_base, test), + qtest_executables[test], + env: qtest_env, + args: ['--tap', '-k'], + protocol: 'tap', + suite: ['qtest', 'qtest-' + target_base]) + endforeach +endforeach diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c index 04e199ec33..2b255579df 100644 --- a/tests/qtest/microbit-test.c +++ b/tests/qtest/microbit-test.c @@ -16,7 +16,7 @@ #include "qemu/osdep.h" #include "exec/hwaddr.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "hw/arm/nrf51.h" #include "hw/char/nrf51_uart.h" diff --git a/tests/qtest/migration-helpers.h b/tests/qtest/migration-helpers.h index a11808b3b7..d63bba9630 100644 --- a/tests/qtest/migration-helpers.h +++ b/tests/qtest/migration-helpers.h @@ -12,7 +12,7 @@ #ifndef MIGRATION_HELPERS_H_ #define MIGRATION_HELPERS_H_ -#include "libqtest.h" +#include "libqos/libqtest.h" extern bool got_stop; diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index 21ea5ba1d2..00a233cd8c 100644 --- a/tests/qtest/migration-test.c +++ b/tests/qtest/migration-test.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" #include "qemu/module.h" @@ -25,7 +25,7 @@ #include "qapi/qobject-output-visitor.h" #include "migration-helpers.h" -#include "migration/migration-test.h" +#include "tests/migration/migration-test.h" /* TODO actually test the results and get rid of this */ #define qtest_qmp_discard_response(...) qobject_unref(qtest_qmp(__VA_ARGS__)) diff --git a/tests/qtest/modules-test.c b/tests/qtest/modules-test.c index 88217686e1..c238b3f422 100644 --- a/tests/qtest/modules-test.c +++ b/tests/qtest/modules-test.c @@ -1,5 +1,5 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" const char common_args[] = "-nodefaults -machine none"; diff --git a/tests/qtest/ne2000-test.c b/tests/qtest/ne2000-test.c index 3fc0e555d5..43cfc4535a 100644 --- a/tests/qtest/ne2000-test.c +++ b/tests/qtest/ne2000-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index e1ed6d4322..b25ebf97d8 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -10,7 +10,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qlist.h" diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c index ff0442150c..d32c953a38 100644 --- a/tests/qtest/nvme-test.c +++ b/tests/qtest/nvme-test.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qemu/units.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/pca9552-test.c b/tests/qtest/pca9552-test.c index d80ed93cd3..42a1312665 100644 --- a/tests/qtest/pca9552-test.c +++ b/tests/qtest/pca9552-test.c @@ -9,7 +9,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/qgraph.h" #include "libqos/i2c.h" #include "hw/misc/pca9552_regs.h" diff --git a/tests/qtest/pci-test.c b/tests/qtest/pci-test.c index 4b2092b949..e15d4d94d1 100644 --- a/tests/qtest/pci-test.c +++ b/tests/qtest/pci-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/pcnet-test.c b/tests/qtest/pcnet-test.c index 900944fa7e..7583aeb3c3 100644 --- a/tests/qtest/pcnet-test.c +++ b/tests/qtest/pcnet-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/pflash-cfi02-test.c b/tests/qtest/pflash-cfi02-test.c index 17aa669b2e..afb702b565 100644 --- a/tests/qtest/pflash-cfi02-test.c +++ b/tests/qtest/pflash-cfi02-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" /* * To test the pflash_cfi02 device, we run QEMU with the musicpal machine with diff --git a/tests/qtest/pnv-xscom-test.c b/tests/qtest/pnv-xscom-test.c index 2c46d5cf6d..c8d4043362 100644 --- a/tests/qtest/pnv-xscom-test.c +++ b/tests/qtest/pnv-xscom-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" typedef enum PnvChipType { PNV_CHIP_POWER8E, /* AKA Murano (default) */ diff --git a/tests/qtest/prom-env-test.c b/tests/qtest/prom-env-test.c index 60e6ec3153..f41d80154a 100644 --- a/tests/qtest/prom-env-test.c +++ b/tests/qtest/prom-env-test.c @@ -20,7 +20,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/libqos-spapr.h" #define MAGIC 0xcafec0de diff --git a/tests/qtest/pvpanic-test.c b/tests/qtest/pvpanic-test.c index ff9176adf3..e57639481e 100644 --- a/tests/qtest/pvpanic-test.c +++ b/tests/qtest/pvpanic-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" static void test_panic(void) diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c index 1161a773a4..32bbae33c5 100644 --- a/tests/qtest/pxe-test.c +++ b/tests/qtest/pxe-test.c @@ -15,7 +15,7 @@ #include "qemu/osdep.h" #include #include "qemu-common.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "boot-sector.h" #include "libqos/libqos-spapr.h" diff --git a/tests/qtest/q35-test.c b/tests/qtest/q35-test.c index c922d81bc0..b7cf144990 100644 --- a/tests/qtest/q35-test.c +++ b/tests/qtest/q35-test.c @@ -10,7 +10,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/pci.h" #include "libqos/pci-pc.h" #include "hw/pci-host/q35.h" diff --git a/tests/qtest/qmp-cmd-test.c b/tests/qtest/qmp-cmd-test.c index f7b1aa7fdc..f34e68858a 100644 --- a/tests/qtest/qmp-cmd-test.c +++ b/tests/qtest/qmp-cmd-test.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/error.h" #include "qapi/qapi-visit-introspect.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/qmp-test.c b/tests/qtest/qmp-test.c index 1a8876b6ca..5950c3ebbb 100644 --- a/tests/qtest/qmp-test.c +++ b/tests/qtest/qmp-test.c @@ -11,7 +11,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/error.h" #include "qapi/qapi-visit-control.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c index 1acf0d7369..eb34af843b 100644 --- a/tests/qtest/qom-test.c +++ b/tests/qtest/qom-test.c @@ -13,7 +13,7 @@ #include "qapi/qmp/qdict.h" #include "qapi/qmp/qlist.h" #include "qemu/cutils.h" -#include "libqtest.h" +#include "libqos/libqtest.h" static void test_properties(QTestState *qts, const char *path, bool recurse) { diff --git a/tests/qtest/rtas-test.c b/tests/qtest/rtas-test.c index 167b42db38..a7e83e7d40 100644 --- a/tests/qtest/rtas-test.c +++ b/tests/qtest/rtas-test.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/libqos-spapr.h" #include "libqos/rtas.h" diff --git a/tests/qtest/sdhci-test.c b/tests/qtest/sdhci-test.c index 6275e7626c..a110cfe321 100644 --- a/tests/qtest/sdhci-test.c +++ b/tests/qtest/sdhci-test.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "hw/registerfields.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/pci-pc.h" #include "hw/pci/pci.h" diff --git a/tests/qtest/spapr-phb-test.c b/tests/qtest/spapr-phb-test.c index 093dc22f2f..ea8d596507 100644 --- a/tests/qtest/spapr-phb-test.c +++ b/tests/qtest/spapr-phb-test.c @@ -9,7 +9,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" diff --git a/tests/qtest/tco-test.c b/tests/qtest/tco-test.c index 254f735370..47bc7ad301 100644 --- a/tests/qtest/tco-test.c +++ b/tests/qtest/tco-test.c @@ -9,7 +9,7 @@ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "libqos/pci.h" #include "libqos/pci-pc.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/test-filter-mirror.c b/tests/qtest/test-filter-mirror.c index 1e3ced84a9..bc0dee64dd 100644 --- a/tests/qtest/test-filter-mirror.c +++ b/tests/qtest/test-filter-mirror.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qemu/iov.h" #include "qemu/sockets.h" diff --git a/tests/qtest/test-filter-redirector.c b/tests/qtest/test-filter-redirector.c index e4d53220fd..829db8c2ea 100644 --- a/tests/qtest/test-filter-redirector.c +++ b/tests/qtest/test-filter-redirector.c @@ -52,7 +52,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qemu/iov.h" #include "qemu/sockets.h" diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c index d5e7ebd176..aea1384bac 100644 --- a/tests/qtest/test-hmp.c +++ b/tests/qtest/test-hmp.c @@ -15,7 +15,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" static int verbose; diff --git a/tests/qtest/tpm-crb-swtpm-test.c b/tests/qtest/tpm-crb-swtpm-test.c index 55fdb5657d..1d82a48c04 100644 --- a/tests/qtest/tpm-crb-swtpm-test.c +++ b/tests/qtest/tpm-crb-swtpm-test.c @@ -15,7 +15,7 @@ #include "qemu/osdep.h" #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "tpm-tests.h" #include "hw/acpi/tpm.h" diff --git a/tests/qtest/tpm-tis-device-swtpm-test.c b/tests/qtest/tpm-tis-device-swtpm-test.c index 7b20035142..f7126eff9e 100644 --- a/tests/qtest/tpm-tis-device-swtpm-test.c +++ b/tests/qtest/tpm-tis-device-swtpm-test.c @@ -16,7 +16,7 @@ #include "qemu/osdep.h" #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "tpm-tests.h" #include "hw/acpi/tpm.h" diff --git a/tests/qtest/tpm-tis-swtpm-test.c b/tests/qtest/tpm-tis-swtpm-test.c index 90131cb3c4..fa590e68f1 100644 --- a/tests/qtest/tpm-tis-swtpm-test.c +++ b/tests/qtest/tpm-tis-swtpm-test.c @@ -15,7 +15,7 @@ #include "qemu/osdep.h" #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "tpm-tests.h" #include "hw/acpi/tpm.h" diff --git a/tests/qtest/tpm-util.c b/tests/qtest/tpm-util.c index 58a9593745..e2b29ef0f8 100644 --- a/tests/qtest/tpm-util.c +++ b/tests/qtest/tpm-util.c @@ -15,7 +15,7 @@ #include "qemu/osdep.h" #include "hw/acpi/tpm.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "tpm-util.h" #include "qapi/qmp/qdict.h" diff --git a/tests/qtest/tulip-test.c b/tests/qtest/tulip-test.c index 2fb6c4d5a7..da16cbfafc 100644 --- a/tests/qtest/tulip-test.c +++ b/tests/qtest/tulip-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/virtio-rng-test.c b/tests/qtest/virtio-rng-test.c index 092ba13068..e6b8cd8e0c 100644 --- a/tests/qtest/virtio-rng-test.c +++ b/tests/qtest/virtio-rng-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/virtio-rng.h" diff --git a/tests/qtest/virtio-test.c b/tests/qtest/virtio-test.c index f7c6afdcf1..6313417630 100644 --- a/tests/qtest/virtio-test.c +++ b/tests/qtest/virtio-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c index efba76e716..6781a51447 100644 --- a/tests/qtest/vmgenid-test.c +++ b/tests/qtest/vmgenid-test.c @@ -14,7 +14,7 @@ #include "hw/acpi/acpi-defs.h" #include "boot-sector.h" #include "acpi-utils.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #define VGID_GUID "324e6eaf-d1d1-4bf6-bf41-b9bb6c91fb87" diff --git a/tests/qtest/vmxnet3-test.c b/tests/qtest/vmxnet3-test.c index a81025252c..97c23fd3a8 100644 --- a/tests/qtest/vmxnet3-test.c +++ b/tests/qtest/vmxnet3-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qemu/module.h" #include "libqos/qgraph.h" #include "libqos/pci.h" diff --git a/tests/qtest/wdt_ib700-test.c b/tests/qtest/wdt_ib700-test.c index 797288d939..6c36e43fb8 100644 --- a/tests/qtest/wdt_ib700-test.c +++ b/tests/qtest/wdt_ib700-test.c @@ -8,7 +8,7 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qemu/timer.h" diff --git a/tests/test-qga.c b/tests/test-qga.c index d1b4c3e8ce..4ac4c22109 100644 --- a/tests/test-qga.c +++ b/tests/test-qga.c @@ -4,7 +4,7 @@ #include #include -#include "libqtest.h" +#include "libqos/libqtest.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qlist.h" diff --git a/tests/test-qgraph.c b/tests/test-qgraph.c index 5c7e457075..267291c6ed 100644 --- a/tests/test-qgraph.c +++ b/tests/test-qgraph.c @@ -17,9 +17,8 @@ */ #include "qemu/osdep.h" -#include "libqtest.h" -#include "libqos/qgraph.h" -#include "libqos/qgraph_internal.h" +#include "qtest/libqos/qgraph.h" +#include "qtest/libqos/qgraph_internal.h" #define MACHINE_PC "x86_64/pc" #define MACHINE_RASPI2 "arm/raspi2" -- cgit v1.2.3-55-g7522 From 478e943f515bffb712ff65a85b5db36c90a2f5e7 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 17 Aug 2020 12:47:55 +0200 Subject: meson: convert audio directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 7 +++++-- Makefile.target | 3 ++- audio/Makefile.objs | 35 ----------------------------------- audio/meson.build | 30 ++++++++++++++++++++++++++++++ configure | 16 ++++++++++++++++ meson.build | 27 +++++++++++++++++++++++++++ 6 files changed, 80 insertions(+), 38 deletions(-) delete mode 100644 audio/Makefile.objs create mode 100644 audio/meson.build diff --git a/Makefile.objs b/Makefile.objs index e43526fe5f..ec7627a4c6 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -63,6 +63,11 @@ common-obj-$(CONFIG_LINUX) += fsdev/ common-obj-y += accel/ common-obj-y += migration/ +common-obj-$(CONFIG_AUDIO_ALSA) += audio-alsa$(DSOSUF) +common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) +common-obj-$(CONFIG_AUDIO_PA) += audio-pa$(DSOSUF) +common-obj-$(CONFIG_AUDIO_SDL) += audio-sdl$(DSOSUF) + common-obj-$(if $(CONFIG_CURL),m) += block-curl$(DSOSUF) common-obj-$(if $(CONFIG_GLUSTERFS),m) += block-gluster$(DSOSUF) common-obj-$(if $(CONFIG_LIBISCSI),m) += block-iscsi$(DSOSUF) @@ -73,8 +78,6 @@ common-obj-$(if $(CONFIG_RBD),m) += block-rbd$(DSOSUF) common-obj-$(if $(CONFIG_LZFSE),m) += block-dmg-lzfse$(DSOSUF) common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF) -common-obj-y += audio/ -common-obj-m += audio/ common-obj-y += hw/ common-obj-m += hw/ diff --git a/Makefile.target b/Makefile.target index c8c4b70162..ff0e1b2d10 100644 --- a/Makefile.target +++ b/Makefile.target @@ -166,9 +166,10 @@ LIBS := $(libs_softmmu) $(LIBS) # Temporary until emulators are linked by Meson LIBS := $(LIBS) @../block.syms @../qemu.syms ifneq ($(CONFIG_MODULES),y) -LIBS := $(LIBS) +LIBS := $(LIBS) $(ALSA_LIBS) $(OSS_LIBS) $(PULSE_LIBS) $(SDL_LIBS) endif LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) +LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) # Hardware support ifeq ($(TARGET_NAME), sparc64) diff --git a/audio/Makefile.objs b/audio/Makefile.objs deleted file mode 100644 index b4a4c11f31..0000000000 --- a/audio/Makefile.objs +++ /dev/null @@ -1,35 +0,0 @@ -common-obj-y = audio.o audio_legacy.o noaudio.o wavaudio.o mixeng.o -common-obj-$(CONFIG_SPICE) += spiceaudio.o -common-obj-$(CONFIG_AUDIO_COREAUDIO) += coreaudio.o -common-obj-$(CONFIG_AUDIO_DSOUND) += dsoundaudio.o -common-obj-$(CONFIG_AUDIO_WIN_INT) += audio_win_int.o -common-obj-y += wavcapture.o - -coreaudio.o-libs := $(COREAUDIO_LIBS) -dsoundaudio.o-libs := $(DSOUND_LIBS) - -# alsa module -common-obj-$(CONFIG_AUDIO_ALSA) += alsa.mo -alsa.mo-objs = alsaaudio.o -alsa.mo-libs := $(ALSA_LIBS) - -# oss module -common-obj-$(CONFIG_AUDIO_OSS) += oss.mo -oss.mo-objs = ossaudio.o -oss.mo-libs := $(OSS_LIBS) - -# pulseaudio module -common-obj-$(CONFIG_AUDIO_PA) += pa.mo -pa.mo-objs = paaudio.o -pa.mo-libs := $(PULSE_LIBS) - -# sdl module -common-obj-$(CONFIG_AUDIO_SDL) += sdl.mo -sdl.mo-objs = sdlaudio.o -sdl.mo-cflags := $(SDL_CFLAGS) -sdl.mo-libs := $(SDL_LIBS) - -# jack module -common-obj-$(CONFIG_AUDIO_JACK) += jack.mo -jack.mo-objs = jackaudio.o -jack.mo-libs := $(JACK_LIBS) diff --git a/audio/meson.build b/audio/meson.build new file mode 100644 index 0000000000..15c06ba045 --- /dev/null +++ b/audio/meson.build @@ -0,0 +1,30 @@ +softmmu_ss.add(files( + 'audio.c', + 'audio_legacy.c', + 'mixeng.c', + 'noaudio.c', + 'wavaudio.c', + 'wavcapture.c', +)) + +softmmu_ss.add(when: [spice, 'CONFIG_SPICE'], if_true: files('spiceaudio.c')) +softmmu_ss.add(when: [coreaudio, 'CONFIG_AUDIO_COREAUDIO'], if_true: files('coreaudio.c')) +softmmu_ss.add(when: [dsound, 'CONFIG_AUDIO_DSOUND'], if_true: files('dsoundaudio.c')) +softmmu_ss.add(when: ['CONFIG_AUDIO_WIN_INT'], if_true: files('audio_win_int.c')) + +audio_modules = {} +foreach m : [ + ['CONFIG_AUDIO_ALSA', 'alsa', alsa, 'alsaaudio.c'], + ['CONFIG_AUDIO_OSS', 'oss', oss, 'ossaudio.c'], + ['CONFIG_AUDIO_PA', 'pa', pulse, 'paaudio.c'], + ['CONFIG_AUDIO_SDL', 'sdl', sdl, 'sdlaudio.c'], + ['CONFIG_AUDIO_JACK', 'jack', jack, 'jackaudio.c'] +] + if config_host.has_key(m[0]) + module_ss = ss.source_set() + module_ss.add(when: m[2], if_true: files(m[3])) + audio_modules += {m[1] : module_ss} + endif +endforeach + +modules += {'audio': audio_modules} diff --git a/configure b/configure index 68cf306ce8..cd6ad9cd7b 100755 --- a/configure +++ b/configure @@ -3767,6 +3767,8 @@ for drv in $audio_drv_list; do alsa | try-alsa) if $pkg_config alsa --exists; then alsa_libs=$($pkg_config alsa --libs) + alsa_cflags=$($pkg_config alsa --cflags) + alsa=yes if test "$drv" = "try-alsa"; then audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-alsa/alsa/') fi @@ -3782,7 +3784,9 @@ for drv in $audio_drv_list; do pa | try-pa) if $pkg_config libpulse --exists; then + libpulse=yes pulse_libs=$($pkg_config libpulse --libs) + pulse_cflags=$($pkg_config libpulse --cflags) if test "$drv" = "try-pa"; then audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-pa/pa/') fi @@ -3825,6 +3829,7 @@ for drv in $audio_drv_list; do jack | try-jack) if $pkg_config jack --exists; then + libjack=yes jack_libs=$($pkg_config jack --libs) if test "$drv" = "try-jack"; then audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-jack/jack/') @@ -7036,11 +7041,22 @@ for drv in $audio_drv_list; do echo "$def=y" >> $config_host_mak ;; esac done +if test "$alsa" = "yes" ; then + echo "CONFIG_ALSA=y" >> $config_host_mak +fi echo "ALSA_LIBS=$alsa_libs" >> $config_host_mak +echo "ALSA_CFLAGS=$alsa_cflags" >> $config_host_mak +if test "$libpulse" = "yes" ; then + echo "CONFIG_LIBPULSE=y" >> $config_host_mak +fi echo "PULSE_LIBS=$pulse_libs" >> $config_host_mak +echo "PULSE_CFLAGS=$pulse_cflags" >> $config_host_mak echo "COREAUDIO_LIBS=$coreaudio_libs" >> $config_host_mak echo "DSOUND_LIBS=$dsound_libs" >> $config_host_mak echo "OSS_LIBS=$oss_libs" >> $config_host_mak +if test "$libjack" = "yes" ; then + echo "CONFIG_LIBJACK=y" >> $config_host_mak +fi echo "JACK_LIBS=$jack_libs" >> $config_host_mak if test "$audio_win_int" = "yes" ; then echo "CONFIG_AUDIO_WIN_INT=y" >> $config_host_mak diff --git a/meson.build b/meson.build index 99daa91666..e1e70d4b48 100644 --- a/meson.build +++ b/meson.build @@ -147,6 +147,20 @@ if 'CONFIG_XKBCOMMON' in config_host xkbcommon = declare_dependency(compile_args: config_host['XKBCOMMON_CFLAGS'].split(), link_args: config_host['XKBCOMMON_LIBS'].split()) endif +pulse = not_found +if 'CONFIG_LIBPULSE' in config_host + pulse = declare_dependency(compile_args: config_host['PULSE_CFLAGS'].split(), + link_args: config_host['PULSE_LIBS'].split()) +endif +alsa = not_found +if 'CONFIG_ALSA' in config_host + alsa = declare_dependency(compile_args: config_host['ALSA_CFLAGS'].split(), + link_args: config_host['ALSA_LIBS'].split()) +endif +jack = not_found +if 'CONFIG_LIBJACK' in config_host + jack = declare_dependency(link_args: config_host['JACK_LIBS'].split()) +endif spice = not_found if 'CONFIG_SPICE' in config_host spice = declare_dependency(compile_args: config_host['SPICE_CFLAGS'].split(), @@ -217,6 +231,18 @@ liblzfse = not_found if 'CONFIG_LZFSE' in config_host liblzfse = declare_dependency(link_args: config_host['LZFSE_LIBS'].split()) endif +oss = not_found +if 'CONFIG_AUDIO_OSS' in config_host + oss = declare_dependency(link_args: config_host['OSS_LIBS'].split()) +endif +dsound = not_found +if 'CONFIG_AUDIO_DSOUND' in config_host + dsound = declare_dependency(link_args: config_host['DSOUND_LIBS'].split()) +endif +coreaudio = not_found +if 'CONFIG_AUDIO_COREAUDIO' in config_host + coreaudio = declare_dependency(link_args: config_host['COREAUDIO_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -518,6 +544,7 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +subdir('audio') subdir('io') subdir('chardev') subdir('fsdev') -- cgit v1.2.3-55-g7522 From 2b1ccdf44146424032e384749efa993855f3bda6 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 16 Jul 2019 23:21:02 +0400 Subject: meson: convert ui directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 8 +++--- Makefile.target | 8 +++--- configure | 6 +++++ meson.build | 50 ++++++++++++++++++++++++++++++++++ ui/Makefile.objs | 73 ------------------------------------------------- ui/meson.build | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- ui/shader.c | 6 ++--- 7 files changed, 149 insertions(+), 84 deletions(-) delete mode 100644 ui/Makefile.objs diff --git a/Makefile.objs b/Makefile.objs index ec7627a4c6..72e935023d 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -68,6 +68,11 @@ common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) common-obj-$(CONFIG_AUDIO_PA) += audio-pa$(DSOSUF) common-obj-$(CONFIG_AUDIO_SDL) += audio-sdl$(DSOSUF) +common-obj-$(if $(CONFIG_CURSES),m) += ui-curses$(DSOSUF) +common-obj-$(if $(CONFIG_GTK),m) += ui-gtk$(DSOSUF) +common-obj-$(if $(CONFIG_SDL),m) += ui-sdl$(DSOSUF) +common-obj-$(if $(CONFIG_SPICE),m) += ui-spice-app$(DSOSUF) + common-obj-$(if $(CONFIG_CURL),m) += block-curl$(DSOSUF) common-obj-$(if $(CONFIG_GLUSTERFS),m) += block-gluster$(DSOSUF) common-obj-$(if $(CONFIG_LIBISCSI),m) += block-iscsi$(DSOSUF) @@ -83,9 +88,6 @@ common-obj-m += hw/ common-obj-y += replay/ -common-obj-y += ui/ -common-obj-m += ui/ - common-obj-y += dma-helpers.o common-obj-$(CONFIG_TPM) += tpm.o diff --git a/Makefile.target b/Makefile.target index ff0e1b2d10..16f1e781e9 100644 --- a/Makefile.target +++ b/Makefile.target @@ -167,8 +167,9 @@ LIBS := $(libs_softmmu) $(LIBS) LIBS := $(LIBS) @../block.syms @../qemu.syms ifneq ($(CONFIG_MODULES),y) LIBS := $(LIBS) $(ALSA_LIBS) $(OSS_LIBS) $(PULSE_LIBS) $(SDL_LIBS) +LIBS := $(LIBS) $(GTK_LIBS) $(VTE_LIBS) $(X11_LIBS) $(CURSES_LIBS) $(ICONV_LIBS) $(GIO_LIBS) endif -LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) +LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) # Hardware support @@ -207,9 +208,8 @@ dummy := $(call fix-paths,../,, \ crypto-obj-y \ io-obj-y \ qom-obj-y) -dummy := $(call unnest-vars,.., \ - common-obj-y \ - common-obj-m) +dummy := $(call unnest-vars,..,common-obj-y) + all-obj-y += $(common-obj-y) all-obj-y += $(qom-obj-y) all-obj-$(CONFIG_SOFTMMU) += $(authz-obj-y) diff --git a/configure b/configure index cd6ad9cd7b..6133feed16 100755 --- a/configure +++ b/configure @@ -7069,12 +7069,18 @@ fi if test "$vnc_sasl" = "yes" ; then echo "CONFIG_VNC_SASL=y" >> $config_host_mak fi +echo "SASL_CFLAGS=$vnc_sasl_cflags" >> $config_host_mak +echo "SASL_LIBS=$vnc_sasl_libs" >> $config_host_mak if test "$vnc_jpeg" = "yes" ; then echo "CONFIG_VNC_JPEG=y" >> $config_host_mak fi +echo "JPEG_CFLAGS=$vnc_jpeg_cflags" >> $config_host_mak +echo "JPEG_LIBS=$vnc_jpeg_libs" >> $config_host_mak if test "$vnc_png" = "yes" ; then echo "CONFIG_VNC_PNG=y" >> $config_host_mak fi +echo "PNG_CFLAGS=$vnc_png_cflags" >> $config_host_mak +echo "PNG_LIBS=$vnc_png_libs" >> $config_host_mak if test "$xkbcommon" = "yes" ; then echo "CONFIG_XKBCOMMON=y" >> $config_host_mak echo "XKBCOMMON_CFLAGS=$xkbcommon_cflags" >> $config_host_mak diff --git a/meson.build b/meson.build index e1e70d4b48..ca1e6906b7 100644 --- a/meson.build +++ b/meson.build @@ -243,6 +243,56 @@ coreaudio = not_found if 'CONFIG_AUDIO_COREAUDIO' in config_host coreaudio = declare_dependency(link_args: config_host['COREAUDIO_LIBS'].split()) endif +opengl = not_found +if 'CONFIG_OPENGL' in config_host + opengl = declare_dependency(link_args: config_host['OPENGL_LIBS'].split()) +else +endif +gtk = not_found +if 'CONFIG_GTK' in config_host + gtk = declare_dependency(compile_args: config_host['GTK_CFLAGS'].split(), + link_args: config_host['GTK_LIBS'].split()) +endif +vte = not_found +if 'CONFIG_VTE' in config_host + vte = declare_dependency(compile_args: config_host['VTE_CFLAGS'].split(), + link_args: config_host['VTE_LIBS'].split()) +endif +x11 = not_found +if 'CONFIG_X11' in config_host + x11 = declare_dependency(compile_args: config_host['X11_CFLAGS'].split(), + link_args: config_host['X11_LIBS'].split()) +endif +curses = not_found +if 'CONFIG_CURSES' in config_host + curses = declare_dependency(compile_args: config_host['CURSES_CFLAGS'].split(), + link_args: config_host['CURSES_LIBS'].split()) +endif +iconv = not_found +if 'CONFIG_ICONV' in config_host + iconv = declare_dependency(compile_args: config_host['ICONV_CFLAGS'].split(), + link_args: config_host['ICONV_LIBS'].split()) +endif +gio = not_found +if 'CONFIG_GIO' in config_host + gio = declare_dependency(compile_args: config_host['GIO_CFLAGS'].split(), + link_args: config_host['GIO_LIBS'].split()) +endif +png = not_found +if 'CONFIG_VNC_PNG' in config_host + png = declare_dependency(compile_args: config_host['PNG_CFLAGS'].split(), + link_args: config_host['PNG_LIBS'].split()) +endif +jpeg = not_found +if 'CONFIG_VNC_JPEG' in config_host + jpeg = declare_dependency(compile_args: config_host['JPEG_CFLAGS'].split(), + link_args: config_host['JPEG_LIBS'].split()) +endif +sasl = not_found +if 'CONFIG_VNC_SASL' in config_host + sasl = declare_dependency(compile_args: config_host['SASL_CFLAGS'].split(), + link_args: config_host['SASL_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') diff --git a/ui/Makefile.objs b/ui/Makefile.objs deleted file mode 100644 index 504b196479..0000000000 --- a/ui/Makefile.objs +++ /dev/null @@ -1,73 +0,0 @@ -vnc-obj-y += vnc.o -vnc-obj-y += vnc-enc-zlib.o vnc-enc-hextile.o -vnc-obj-y += vnc-enc-tight.o vnc-palette.o -vnc-obj-y += vnc-enc-zrle.o -vnc-obj-y += vnc-auth-vencrypt.o -vnc-obj-$(CONFIG_VNC_SASL) += vnc-auth-sasl.o -vnc-obj-y += vnc-ws.o -vnc-obj-y += vnc-jobs.o - -common-obj-y += keymaps.o console.o cursor.o qemu-pixman.o -common-obj-y += input.o input-keymap.o input-legacy.o kbd-state.o -common-obj-y += input-barrier.o -common-obj-$(CONFIG_LINUX) += input-linux.o -common-obj-$(CONFIG_SPICE) += spice-core.o spice-input.o spice-display.o -common-obj-$(CONFIG_COCOA) += cocoa.o -common-obj-$(CONFIG_VNC) += $(vnc-obj-y) -common-obj-$(call lnot,$(CONFIG_VNC)) += vnc-stubs.o -ifneq (,$(findstring m,$(CONFIG_SDL)$(CONFIG_GTK))) -common-obj-$(CONFIG_WIN32) += win32-kbd-hook.o -endif - -# ui-sdl module -common-obj-$(CONFIG_SDL) += sdl.mo -sdl.mo-objs := sdl2.o sdl2-input.o sdl2-2d.o -ifeq ($(CONFIG_OPENGL),y) -sdl.mo-objs += sdl2-gl.o -endif -sdl.mo-cflags := $(SDL_CFLAGS) -sdl.mo-libs := $(SDL_LIBS) - -# ui-gtk module -common-obj-$(CONFIG_GTK) += gtk.mo -gtk.mo-objs := gtk.o -gtk.mo-cflags := $(GTK_CFLAGS) $(VTE_CFLAGS) -gtk.mo-libs := $(GTK_LIBS) $(VTE_LIBS) -ifeq ($(CONFIG_OPENGL),y) -gtk.mo-objs += gtk-egl.o -gtk.mo-libs += $(OPENGL_LIBS) -ifeq ($(CONFIG_GTK_GL),y) -gtk.mo-objs += gtk-gl-area.o -endif -endif - -ifeq ($(CONFIG_X11),y) -sdl.mo-objs += x_keymap.o -gtk.mo-objs += x_keymap.o -x_keymap.o-cflags := $(X11_CFLAGS) -x_keymap.o-libs := $(X11_LIBS) -endif - -common-obj-$(CONFIG_CURSES) += curses.mo -curses.mo-objs := curses.o -curses.mo-cflags := $(CURSES_CFLAGS) $(ICONV_CFLAGS) -curses.mo-libs := $(CURSES_LIBS) $(ICONV_LIBS) - -ifeq ($(CONFIG_GIO)$(CONFIG_SPICE),yy) -common-obj-$(if $(CONFIG_MODULES),m,y) += spice-app.mo -endif -spice-app.mo-objs := spice-app.o -spice-app.mo-cflags := $(GIO_CFLAGS) -spice-app.mo-libs := $(GIO_LIBS) - -common-obj-$(CONFIG_OPENGL) += shader.o -common-obj-$(CONFIG_OPENGL) += console-gl.o -common-obj-$(CONFIG_OPENGL) += egl-helpers.o -common-obj-$(CONFIG_OPENGL) += egl-context.o -common-obj-$(CONFIG_OPENGL_DMABUF) += egl-headless.o - -shader.o-libs += $(OPENGL_LIBS) -console-gl.o-libs += $(OPENGL_LIBS) -egl-helpers.o-libs += $(OPENGL_LIBS) -egl-context.o-libs += $(OPENGL_LIBS) -egl-headless.o-libs += $(OPENGL_LIBS) diff --git a/ui/meson.build b/ui/meson.build index 35da0d8d26..66282c398d 100644 --- a/ui/meson.build +++ b/ui/meson.build @@ -1,3 +1,82 @@ +softmmu_ss.add(files( + 'console.c', + 'cursor.c', + 'input-keymap.c', + 'input-legacy.c', + 'input-barrier.c', + 'input.c', + 'kbd-state.c', + 'keymaps.c', + 'qemu-pixman.c', +)) +softmmu_ss.add(pixman) + +softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('input-linux.c')) +softmmu_ss.add(when: 'CONFIG_SPICE', if_true: files('spice-core.c', 'spice-input.c', 'spice-display.c')) +softmmu_ss.add(when: [cocoa, 'CONFIG_COCOA'], if_true: files('cocoa.m')) + +vnc_ss = ss.source_set() +vnc_ss.add(files( + 'vnc.c', + 'vnc-enc-zlib.c', + 'vnc-enc-hextile.c', + 'vnc-enc-tight.c', + 'vnc-palette.c', + 'vnc-enc-zrle.c', + 'vnc-auth-vencrypt.c', + 'vnc-ws.c', + 'vnc-jobs.c', +)) +vnc_ss.add(zlib) +vnc_ss.add(when: 'CONFIG_VNC_SASL', if_true: [files('vnc-auth-sasl.c'), sasl]) +softmmu_ss.add_all(when: 'CONFIG_VNC', if_true: vnc_ss) +softmmu_ss.add(when: 'CONFIG_VNC', if_false: files('vnc-stubs.c')) +softmmu_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true: files('shader.c', 'console-gl.c', 'egl-helpers.c', 'egl-context.c')) +softmmu_ss.add(when: [opengl, 'CONFIG_OPENGL_DMABUF'], if_true: files('egl-headless.c')) +softmmu_ss.add(when: 'CONFIG_VNC_PNG', if_true: png) +softmmu_ss.add(when: 'CONFIG_VNC_JPEG', if_true: jpeg) + +ui_modules = {} + +if config_host.has_key('CONFIG_CURSES') + curses_ss = ss.source_set() + curses_ss.add(when: [curses, iconv], if_true: files('curses.c')) + ui_modules += {'curses' : curses_ss} +endif + +if config_host.has_key('CONFIG_GTK') and config_host.has_key('CONFIG_VTE') + softmmu_ss.add(when: 'CONFIG_WIN32', if_true: files('win32-kbd-hook.c')) + + gtk_ss = ss.source_set() + gtk_ss.add(gtk, vte, files('gtk.c')) + gtk_ss.add(when: [x11, 'CONFIG_X11'], if_true: files('x_keymap.c')) + gtk_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true: files('gtk-egl.c')) + gtk_ss.add(when: [opengl, 'CONFIG_GTK_GL'], if_true: files('gtk-gl-area.c')) + ui_modules += {'gtk' : gtk_ss} +endif + +if config_host.has_key('CONFIG_SDL') + softmmu_ss.add(when: 'CONFIG_WIN32', if_true: files('win32-kbd-hook.c')) + + sdl_ss = ss.source_set() + sdl_ss.add(pixman, glib, files( + 'sdl2-2d.c', + 'sdl2-input.c', + 'sdl2.c', + )) + sdl_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true: files('sdl2-gl.c')) + sdl_ss.add(when: [x11, 'CONFIG_X11'], if_true: files('x_keymap.c')) + ui_modules += {'sdl' : sdl_ss} +endif + +if config_host.has_key('CONFIG_SPICE') and config_host.has_key('CONFIG_GIO') + spice_ss = ss.source_set() + spice_ss.add(spice, gio, files('spice-app.c')) + ui_modules += {'spice-app': spice_ss} +endif + +keymap_gen = find_program('keycodemapdb/tools/keymap-gen') + keymaps = [ ['atset1', 'qcode'], ['linux', 'qcode'], @@ -24,7 +103,6 @@ if have_system genh += custom_target(output, output: output, capture: true, - build_by_default: true, # to be removed when added to a target input: files('keycodemapdb/data/keymaps.csv'), command: [python.full_path(), files('keycodemapdb/tools/keymap-gen'), '--lang', 'glib2', @@ -34,3 +112,5 @@ if have_system endif subdir('shader') + +modules += {'ui': ui_modules} diff --git a/ui/shader.c b/ui/shader.c index d78829f43b..e8b8d321b7 100644 --- a/ui/shader.c +++ b/ui/shader.c @@ -27,9 +27,9 @@ #include "qemu/osdep.h" #include "ui/shader.h" -#include "shader/texture-blit-vert.h" -#include "shader/texture-blit-flip-vert.h" -#include "shader/texture-blit-frag.h" +#include "ui/shader/texture-blit-vert.h" +#include "ui/shader/texture-blit-flip-vert.h" +#include "ui/shader/texture-blit-frag.h" struct QemuGLShader { GLint texture_blit_prog; -- cgit v1.2.3-55-g7522 From 4a96337dfa714f4d15cf9769b6a932a25be48421 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Aug 2020 16:22:28 +0200 Subject: meson: convert root directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 21 ++------------------- Makefile.target | 2 +- configure | 2 ++ meson.build | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 20 deletions(-) diff --git a/Makefile.objs b/Makefile.objs index 72e935023d..ec15ebc4b4 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -48,16 +48,9 @@ storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = blockdev.o blockdev-nbd.o -common-obj-y += bootdevice.o iothread.o -common-obj-y += dump/ -common-obj-y += job-qmp.o +common-obj-y = dump/ common-obj-y += monitor/ common-obj-y += net/ -common-obj-y += qdev-monitor.o -common-obj-$(CONFIG_WIN32) += os-win32.o -common-obj-$(CONFIG_POSIX) += os-posix.o - common-obj-$(CONFIG_LINUX) += fsdev/ common-obj-y += accel/ @@ -87,25 +80,15 @@ common-obj-y += hw/ common-obj-m += hw/ common-obj-y += replay/ - -common-obj-y += dma-helpers.o -common-obj-$(CONFIG_TPM) += tpm.o - common-obj-y += backends/ -common-obj-$(CONFIG_SECCOMP) += qemu-seccomp.o -qemu-seccomp.o-cflags := $(SECCOMP_CFLAGS) -qemu-seccomp.o-libs := $(SECCOMP_LIBS) - -common-obj-$(CONFIG_FDT) += device_tree.o - common-obj-y += qapi/ endif # CONFIG_SOFTMMU ####################################################################### # Target-independent parts used in system and user emulation -common-obj-y += cpus-common.o + common-obj-y += hw/ common-obj-y += qom/ common-obj-y += disas/ diff --git a/Makefile.target b/Makefile.target index 16f1e781e9..5f926e5bfa 100644 --- a/Makefile.target +++ b/Makefile.target @@ -169,7 +169,7 @@ ifneq ($(CONFIG_MODULES),y) LIBS := $(LIBS) $(ALSA_LIBS) $(OSS_LIBS) $(PULSE_LIBS) $(SDL_LIBS) LIBS := $(LIBS) $(GTK_LIBS) $(VTE_LIBS) $(X11_LIBS) $(CURSES_LIBS) $(ICONV_LIBS) $(GIO_LIBS) endif -LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) +LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOMP_LIBS) LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) # Hardware support diff --git a/configure b/configure index 6133feed16..711c252034 100755 --- a/configure +++ b/configure @@ -7380,6 +7380,8 @@ if test "$preadv" = "yes" ; then fi if test "$fdt" != "no" ; then echo "CONFIG_FDT=y" >> $config_host_mak + echo "FDT_CFLAGS=$fdt_cflags" >> $config_host_mak + echo "FDT_LIBS=$fdt_ldflags $fdt_libs" >> $config_host_mak fi if test "$membarrier" = "yes" ; then echo "CONFIG_MEMBARRIER=y" >> $config_host_mak diff --git a/meson.build b/meson.build index ca1e6906b7..ff200900ed 100644 --- a/meson.build +++ b/meson.build @@ -51,6 +51,7 @@ targetos = host_machine.system() m = cc.find_library('m', required: false) util = cc.find_library('util', required: false) +winmm = [] socket = [] version_res = [] coref = [] @@ -59,6 +60,7 @@ cocoa = [] hvf = [] if targetos == 'windows' socket = cc.find_library('ws2_32') + winmm = cc.find_library('winmm') win = import('windows') version_res = win.compile_resources('version.rc', @@ -293,6 +295,11 @@ if 'CONFIG_VNC_SASL' in config_host sasl = declare_dependency(compile_args: config_host['SASL_CFLAGS'].split(), link_args: config_host['SASL_LIBS'].split()) endif +fdt = not_found +if 'CONFIG_FDT' in config_host + fdt = declare_dependency(compile_args: config_host['FDT_CFLAGS'].split(), + link_args: config_host['FDT_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -459,6 +466,7 @@ util_ss = ss.source_set() stub_ss = ss.source_set() trace_ss = ss.source_set() block_ss = ss.source_set() +blockdev_ss = ss.source_set() common_ss = ss.source_set() softmmu_ss = ss.source_set() user_ss = ss.source_set() @@ -612,6 +620,31 @@ subdir('nbd') subdir('scsi') subdir('block') +blockdev_ss.add(files( + 'blockdev.c', + 'blockdev-nbd.c', + 'iothread.c', + 'job-qmp.c', +)) + +# os-posix.c contains POSIX-specific functions used by qemu-storage-daemon, +# os-win32.c does not +blockdev_ss.add(when: 'CONFIG_POSIX', if_true: files('os-posix.c')) +softmmu_ss.add(when: 'CONFIG_WIN32', if_true: [files('os-win32.c')]) + +softmmu_ss.add_all(blockdev_ss) +softmmu_ss.add(files( + 'bootdevice.c', + 'dma-helpers.c', + 'qdev-monitor.c', +), sdl) + +softmmu_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) +softmmu_ss.add(when: 'CONFIG_SECCOMP', if_true: [files('qemu-seccomp.c'), seccomp]) +softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) + +common_ss.add(files('cpus-common.c')) + # needed for fuzzing binaries subdir('tests/qtest/libqos') -- cgit v1.2.3-55-g7522 From 5d3ea0e17db463362578f47a47b5f0c4348516a2 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Aug 2020 13:40:26 +0200 Subject: meson: convert most of softmmu/ Leave out main.c, it's special due to fuzzing. Signed-off-by: Paolo Bonzini --- meson.build | 2 ++ softmmu/Makefile.objs | 14 +------------- softmmu/meson.build | 10 ++++++++++ 3 files changed, 13 insertions(+), 13 deletions(-) create mode 100644 softmmu/meson.build diff --git a/meson.build b/meson.build index ff200900ed..442855daef 100644 --- a/meson.build +++ b/meson.build @@ -645,6 +645,8 @@ softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) common_ss.add(files('cpus-common.c')) +subdir('softmmu') + # needed for fuzzing binaries subdir('tests/qtest/libqos') diff --git a/softmmu/Makefile.objs b/softmmu/Makefile.objs index c036887500..ec74d8a9fa 100644 --- a/softmmu/Makefile.objs +++ b/softmmu/Makefile.objs @@ -1,14 +1,2 @@ softmmu-main-y = softmmu/main.o - -obj-y += arch_init.o -obj-y += cpus.o -obj-y += cpu-throttle.o -obj-y += balloon.o -obj-y += ioport.o -obj-y += memory.o -obj-y += memory_mapping.o - -obj-y += qtest.o - -obj-y += vl.o -vl.o-cflags := $(SDL_CFLAGS) +main.o-cflags := $(SDL_CFLAGS) diff --git a/softmmu/meson.build b/softmmu/meson.build new file mode 100644 index 0000000000..95d38df259 --- /dev/null +++ b/softmmu/meson.build @@ -0,0 +1,10 @@ +specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files( + 'arch_init.c', + 'balloon.c', + 'cpus.c', + 'cpu-throttle.c', + 'ioport.c', + 'memory.c', + 'memory_mapping.c', + 'qtest.c', + 'vl.c')) -- cgit v1.2.3-55-g7522 From 0e1309d0c56fcfce14bd314aa73e35f65c2856b5 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 3 Sep 2019 16:47:00 +0400 Subject: meson: convert trace/ Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- trace/Makefile.objs | 8 -------- trace/meson.build | 5 ++++- 2 files changed, 4 insertions(+), 9 deletions(-) delete mode 100644 trace/Makefile.objs diff --git a/trace/Makefile.objs b/trace/Makefile.objs deleted file mode 100644 index a429474618..0000000000 --- a/trace/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -# -*- mode: makefile -*- - - -################################################## -# Translation level - -obj-y += generated-helpers.o -obj-y += control-target.o diff --git a/trace/meson.build b/trace/meson.build index cab36a248b..9c3c128164 100644 --- a/trace/meson.build +++ b/trace/meson.build @@ -1,3 +1,5 @@ +specific_ss.add(files('control-target.c')) + trace_events_files = [] foreach dir : [ '.' ] + trace_events_subdirs trace_events_file = meson.source_root() / dir / 'trace-events' @@ -61,12 +63,13 @@ foreach d : [ ['generated-helpers.h', 'tcg-helper-h'], ['generated-helpers-wrappers.h', 'tcg-helper-wrapper-h'], ] - custom_target(d[0], + gen = custom_target(d[0], output: d[0], input: meson.source_root() / 'trace-events', command: [ tracetool, '--group=root', '--format=@0@'.format(d[1]), '@INPUT@' ], build_by_default: true, # to be removed when added to a target capture: true) + specific_ss.add(gen) endforeach if 'CONFIG_TRACE_UST' in config_host -- cgit v1.2.3-55-g7522 From 708eab42dc75304473f23ea1ead06d579dcb7566 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 3 Sep 2019 16:59:33 +0400 Subject: meson: convert dump/ Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 3 +-- Makefile.target | 1 - configure | 4 ++++ dump/Makefile.objs | 3 --- dump/meson.build | 4 ++++ meson.build | 9 +++++++++ 6 files changed, 18 insertions(+), 6 deletions(-) delete mode 100644 dump/Makefile.objs create mode 100644 dump/meson.build diff --git a/Makefile.objs b/Makefile.objs index ec15ebc4b4..6657a6cce3 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -48,8 +48,7 @@ storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = dump/ -common-obj-y += monitor/ +common-obj-y = monitor/ common-obj-y += net/ common-obj-$(CONFIG_LINUX) += fsdev/ diff --git a/Makefile.target b/Makefile.target index 5f926e5bfa..c8f7a6c04b 100644 --- a/Makefile.target +++ b/Makefile.target @@ -156,7 +156,6 @@ endif #CONFIG_BSD_USER ifdef CONFIG_SOFTMMU obj-y += softmmu/ obj-y += gdbstub.o -obj-y += dump/ obj-y += hw/ obj-y += monitor/ obj-y += qapi/ diff --git a/configure b/configure index 711c252034..a56de5621a 100755 --- a/configure +++ b/configure @@ -2620,6 +2620,7 @@ int main(void) { lzo_version(); return 0; } EOF if compile_prog "" "-llzo2" ; then libs_softmmu="$libs_softmmu -llzo2" + lzo_libs="-llzo2" lzo="yes" else if test "$lzo" = "yes"; then @@ -2639,6 +2640,7 @@ int main(void) { snappy_max_compressed_length(4096); return 0; } EOF if compile_prog "" "-lsnappy" ; then libs_softmmu="$libs_softmmu -lsnappy" + snappy_libs='-lsnappy' snappy="yes" else if test "$snappy" = "yes"; then @@ -7468,10 +7470,12 @@ fi if test "$lzo" = "yes" ; then echo "CONFIG_LZO=y" >> $config_host_mak + echo "LZO_LIBS=$lzo_libs" >> $config_host_mak fi if test "$snappy" = "yes" ; then echo "CONFIG_SNAPPY=y" >> $config_host_mak + echo "SNAPPY_LIBS=$snappy_libs" >> $config_host_mak fi if test "$bzip2" = "yes" ; then diff --git a/dump/Makefile.objs b/dump/Makefile.objs deleted file mode 100644 index d2a5db3b81..0000000000 --- a/dump/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += dump.o -common-obj-y += dump-hmp-cmds.o -obj-$(TARGET_X86_64) += win_dump.o diff --git a/dump/meson.build b/dump/meson.build new file mode 100644 index 0000000000..2eff29c3ea --- /dev/null +++ b/dump/meson.build @@ -0,0 +1,4 @@ +softmmu_ss.add(files('dump-hmp-cmds.c')) + +specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files('dump.c'), snappy, lzo]) +specific_ss.add(when: ['CONFIG_SOFTMMU', 'TARGET_X86_64'], if_true: files('win_dump.c')) diff --git a/meson.build b/meson.build index 442855daef..6d5eb31dcf 100644 --- a/meson.build +++ b/meson.build @@ -300,6 +300,14 @@ if 'CONFIG_FDT' in config_host fdt = declare_dependency(compile_args: config_host['FDT_CFLAGS'].split(), link_args: config_host['FDT_LIBS'].split()) endif +snappy = not_found +if 'CONFIG_SNAPPY' in config_host + snappy = declare_dependency(link_args: config_host['SNAPPY_LIBS'].split()) +endif +lzo = not_found +if 'CONFIG_LZO' in config_host + lzo = declare_dependency(link_args: config_host['LZO_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -607,6 +615,7 @@ subdir('io') subdir('chardev') subdir('fsdev') subdir('target') +subdir('dump') block_ss.add(files( 'block.c', -- cgit v1.2.3-55-g7522 From ff219dca9ffa4c3417f8a00ef7ce3e9a15196eb0 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Aug 2020 21:14:26 +0200 Subject: meson: convert common QMP bits for qemu and qemu-storage-daemon Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 8 +++++--- Makefile.target | 1 - meson.build | 10 ++++++++++ monitor/Makefile.objs | 6 ------ monitor/meson.build | 9 +++++++++ qom/Makefile.objs | 2 -- qom/meson.build | 3 +++ 7 files changed, 27 insertions(+), 12 deletions(-) delete mode 100644 monitor/Makefile.objs create mode 100644 monitor/meson.build delete mode 100644 qom/Makefile.objs diff --git a/Makefile.objs b/Makefile.objs index 6657a6cce3..d7826c1e5c 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -37,10 +37,11 @@ endif # CONFIG_SOFTMMU or CONFIG_TOOLS # storage-daemon-obj-y is code used by qemu-storage-daemon (these objects are # used for system emulation, too, but specified separately there) -storage-daemon-obj-y = block/ monitor/ qapi/ qom/ storage-daemon/ +storage-daemon-obj-y = block/ qapi/ qom/ storage-daemon/ storage-daemon-obj-y += blockdev.o blockdev-nbd.o iothread.o job-qmp.o storage-daemon-obj-$(CONFIG_WIN32) += os-win32.o storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o +storage-daemon-obj-y += libqmp.fa ###################################################################### # Target independent part of system emulation. The long term path is to @@ -48,8 +49,7 @@ storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = monitor/ -common-obj-y += net/ +common-obj-y = net/ common-obj-$(CONFIG_LINUX) += fsdev/ common-obj-y += accel/ @@ -83,6 +83,8 @@ common-obj-y += backends/ common-obj-y += qapi/ +common-obj-y += libqmp.fa + endif # CONFIG_SOFTMMU ####################################################################### diff --git a/Makefile.target b/Makefile.target index c8f7a6c04b..54a9ef1330 100644 --- a/Makefile.target +++ b/Makefile.target @@ -157,7 +157,6 @@ ifdef CONFIG_SOFTMMU obj-y += softmmu/ obj-y += gdbstub.o obj-y += hw/ -obj-y += monitor/ obj-y += qapi/ obj-y += migration/ram.o LIBS := $(libs_softmmu) $(LIBS) diff --git a/meson.build b/meson.build index 6d5eb31dcf..9d1a530271 100644 --- a/meson.build +++ b/meson.build @@ -475,6 +475,7 @@ stub_ss = ss.source_set() trace_ss = ss.source_set() block_ss = ss.source_set() blockdev_ss = ss.source_set() +qmp_ss = ss.source_set() common_ss = ss.source_set() softmmu_ss = ss.source_set() user_ss = ss.source_set() @@ -655,6 +656,7 @@ softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) common_ss.add(files('cpus-common.c')) subdir('softmmu') +subdir('monitor') # needed for fuzzing binaries subdir('tests/qtest/libqos') @@ -704,6 +706,14 @@ block = declare_dependency(link_whole: [libblock], link_args: '@block.syms', dependencies: [crypto, io]) +qmp_ss = qmp_ss.apply(config_host, strict: false) +libqmp = static_library('qmp', qmp_ss.sources() + genh, + dependencies: qmp_ss.dependencies(), + name_suffix: 'fa', + build_by_default: false) + +qmp = declare_dependency(link_whole: [libqmp]) + foreach m : block_mods + softmmu_mods shared_module(m.name(), name_prefix: '', diff --git a/monitor/Makefile.objs b/monitor/Makefile.objs deleted file mode 100644 index a8533c9dd7..0000000000 --- a/monitor/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -obj-y += misc.o -common-obj-y += monitor.o qmp.o hmp.o -common-obj-y += qmp-cmds.o qmp-cmds-control.o -common-obj-y += hmp-cmds.o - -storage-daemon-obj-y += monitor.o qmp.o qmp-cmds-control.o diff --git a/monitor/meson.build b/monitor/meson.build new file mode 100644 index 0000000000..0484a64341 --- /dev/null +++ b/monitor/meson.build @@ -0,0 +1,9 @@ +qmp_ss.add(files('monitor.c', 'qmp.c', 'qmp-cmds-control.c')) + +softmmu_ss.add(files( + 'hmp-cmds.c', + 'hmp.c', + 'qmp-cmds.c', +)) + +specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files('misc.c')) diff --git a/qom/Makefile.objs b/qom/Makefile.objs deleted file mode 100644 index b9629045e6..0000000000 --- a/qom/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -common-obj-$(CONFIG_SOFTMMU) += qom-hmp-cmds.o qom-qmp-cmds.o -storage-daemon-obj-y += qom-qmp-cmds.o diff --git a/qom/meson.build b/qom/meson.build index cbab9cdfa2..a1cd03c82c 100644 --- a/qom/meson.build +++ b/qom/meson.build @@ -7,6 +7,9 @@ qom_ss.add(files( 'qom-qobject.c', )) +qmp_ss.add(files('qom-qmp-cmds.c')) +softmmu_ss.add(files('qom-hmp-cmds.c')) + qom_ss = qom_ss.apply(config_host, strict: false) libqom = static_library('qom', qom_ss.sources() + genh, dependencies: [qom_ss.dependencies()], -- cgit v1.2.3-55-g7522 From 7c58bb769dce4764b413ae4a9e13c4c54d537b87 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Aug 2020 20:18:36 +0200 Subject: meson: convert qemu-storage-daemon Signed-off-by: Paolo Bonzini --- Makefile | 5 - Makefile.objs | 10 - meson.build | 2 +- qemu-storage-daemon.c | 343 ----------------------------------- storage-daemon/Makefile.objs | 3 - storage-daemon/meson.build | 13 ++ storage-daemon/qapi/meson.build | 5 +- storage-daemon/qemu-storage-daemon.c | 343 +++++++++++++++++++++++++++++++++++ 8 files changed, 358 insertions(+), 366 deletions(-) delete mode 100644 qemu-storage-daemon.c delete mode 100644 storage-daemon/Makefile.objs create mode 100644 storage-daemon/qemu-storage-daemon.c diff --git a/Makefile b/Makefile index cb364f4167..0b06b9cacd 100644 --- a/Makefile +++ b/Makefile @@ -179,8 +179,6 @@ include $(SRC_PATH)/Makefile.objs endif dummy := $(call unnest-vars,, \ - storage-daemon-obj-y \ - storage-daemon-obj-m \ common-obj-y \ common-obj-m) @@ -196,7 +194,6 @@ TARGET_DIRS_RULES := $(foreach t, all fuzz clean install, $(addsuffix /$(t), $(T SOFTMMU_ALL_RULES=$(filter %-softmmu/all, $(TARGET_DIRS_RULES)) $(SOFTMMU_ALL_RULES): $(authz-obj-y) $(SOFTMMU_ALL_RULES): $(block-obj-y) -$(SOFTMMU_ALL_RULES): $(storage-daemon-obj-y) $(SOFTMMU_ALL_RULES): $(chardev-obj-y) $(SOFTMMU_ALL_RULES): $(crypto-obj-y) $(SOFTMMU_ALL_RULES): $(io-obj-y) @@ -287,8 +284,6 @@ Makefile: $(version-obj-y) COMMON_LDADDS = libqemuutil.a -qemu-storage-daemon$(EXESUF): qemu-storage-daemon.o $(authz-obj-y) $(block-obj-y) $(crypto-obj-y) $(chardev-obj-y) $(io-obj-y) $(qom-obj-y) $(storage-daemon-obj-y) $(COMMON_LDADDS) - clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files diff --git a/Makefile.objs b/Makefile.objs index d7826c1e5c..e304d92954 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -33,16 +33,6 @@ io-obj-y = io/libio.fa endif # CONFIG_SOFTMMU or CONFIG_TOOLS -####################################################################### -# storage-daemon-obj-y is code used by qemu-storage-daemon (these objects are -# used for system emulation, too, but specified separately there) - -storage-daemon-obj-y = block/ qapi/ qom/ storage-daemon/ -storage-daemon-obj-y += blockdev.o blockdev-nbd.o iothread.o job-qmp.o -storage-daemon-obj-$(CONFIG_WIN32) += os-win32.o -storage-daemon-obj-$(CONFIG_POSIX) += os-posix.o -storage-daemon-obj-y += libqmp.fa - ###################################################################### # Target independent part of system emulation. The long term path is to # suppress *all* target specific code in case of system emulation, i.e. a diff --git a/meson.build b/meson.build index 9d1a530271..4ff3f7bccb 100644 --- a/meson.build +++ b/meson.build @@ -590,7 +590,6 @@ subdir('util') subdir('qom') subdir('authz') subdir('crypto') -subdir('storage-daemon') subdir('ui') @@ -800,6 +799,7 @@ if have_tools dependencies: [block, qemuutil], install: true) endif + subdir('storage-daemon') subdir('contrib/rdmacm-mux') subdir('contrib/elf2dmp') diff --git a/qemu-storage-daemon.c b/qemu-storage-daemon.c deleted file mode 100644 index 7e9b0e0d3f..0000000000 --- a/qemu-storage-daemon.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * QEMU storage daemon - * - * Copyright (c) 2003-2008 Fabrice Bellard - * Copyright (c) 2019 Kevin Wolf - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" - -#include - -#include "block/block.h" -#include "block/nbd.h" -#include "chardev/char.h" -#include "crypto/init.h" -#include "monitor/monitor.h" -#include "monitor/monitor-internal.h" - -#include "qapi/error.h" -#include "qapi/qapi-visit-block.h" -#include "qapi/qapi-visit-block-core.h" -#include "qapi/qapi-visit-control.h" -#include "qapi/qmp/qdict.h" -#include "qapi/qmp/qstring.h" -#include "qapi/qobject-input-visitor.h" - -#include "qemu-common.h" -#include "qemu-version.h" -#include "qemu/config-file.h" -#include "qemu/error-report.h" -#include "qemu/help_option.h" -#include "qemu/log.h" -#include "qemu/main-loop.h" -#include "qemu/module.h" -#include "qemu/option.h" -#include "qom/object_interfaces.h" - -#include "storage-daemon/qapi/qapi-commands.h" -#include "storage-daemon/qapi/qapi-init-commands.h" - -#include "sysemu/runstate.h" -#include "trace/control.h" - -static volatile bool exit_requested = false; - -void qemu_system_killed(int signal, pid_t pid) -{ - exit_requested = true; -} - -void qmp_quit(Error **errp) -{ - exit_requested = true; -} - -static void help(void) -{ - printf( -"Usage: %s [options]\n" -"QEMU storage daemon\n" -"\n" -" -h, --help display this help and exit\n" -" -T, --trace [[enable=]][,events=][,file=]\n" -" specify tracing options\n" -" -V, --version output version information and exit\n" -"\n" -" --blockdev [driver=][,node-name=][,discard=ignore|unmap]\n" -" [,cache.direct=on|off][,cache.no-flush=on|off]\n" -" [,read-only=on|off][,auto-read-only=on|off]\n" -" [,force-share=on|off][,detect-zeroes=on|off|unmap]\n" -" [,driver specific parameters...]\n" -" configure a block backend\n" -"\n" -" --chardev configure a character device backend\n" -" (see the qemu(1) man page for possible options)\n" -"\n" -" --export [type=]nbd,device=[,name=]\n" -" [,writable=on|off][,bitmap=]\n" -" export the specified block node over NBD\n" -" (requires --nbd-server)\n" -"\n" -" --monitor [chardev=]name[,mode=control][,pretty[=on|off]]\n" -" configure a QMP monitor\n" -"\n" -" --nbd-server addr.type=inet,addr.host=,addr.port=\n" -" [,tls-creds=][,tls-authz=]\n" -" --nbd-server addr.type=unix,addr.path=\n" -" [,tls-creds=][,tls-authz=]\n" -" start an NBD server for exporting block nodes\n" -"\n" -" --object help list object types that can be added\n" -" --object ,help list properties for the given object type\n" -" --object [,=...]\n" -" create a new object of type , setting\n" -" properties in the order they are specified. Note\n" -" that the 'id' property must be set.\n" -" See the qemu(1) man page for documentation of the\n" -" objects that can be added.\n" -"\n" -QEMU_HELP_BOTTOM "\n", - error_get_progname()); -} - -enum { - OPTION_BLOCKDEV = 256, - OPTION_CHARDEV, - OPTION_EXPORT, - OPTION_MONITOR, - OPTION_NBD_SERVER, - OPTION_OBJECT, -}; - -extern QemuOptsList qemu_chardev_opts; - -static QemuOptsList qemu_object_opts = { - .name = "object", - .implied_opt_name = "qom-type", - .head = QTAILQ_HEAD_INITIALIZER(qemu_object_opts.head), - .desc = { - { } - }, -}; - -static void init_qmp_commands(void) -{ - qmp_init_marshal(&qmp_commands); - qmp_register_command(&qmp_commands, "query-qmp-schema", - qmp_query_qmp_schema, QCO_ALLOW_PRECONFIG); - - QTAILQ_INIT(&qmp_cap_negotiation_commands); - qmp_register_command(&qmp_cap_negotiation_commands, "qmp_capabilities", - qmp_marshal_qmp_capabilities, QCO_ALLOW_PRECONFIG); -} - -static void init_export(BlockExport *export, Error **errp) -{ - switch (export->type) { - case BLOCK_EXPORT_TYPE_NBD: - qmp_nbd_server_add(&export->u.nbd, errp); - break; - default: - g_assert_not_reached(); - } -} - -static void process_options(int argc, char *argv[]) -{ - int c; - - static const struct option long_options[] = { - {"blockdev", required_argument, NULL, OPTION_BLOCKDEV}, - {"chardev", required_argument, NULL, OPTION_CHARDEV}, - {"export", required_argument, NULL, OPTION_EXPORT}, - {"help", no_argument, NULL, 'h'}, - {"monitor", required_argument, NULL, OPTION_MONITOR}, - {"nbd-server", required_argument, NULL, OPTION_NBD_SERVER}, - {"object", required_argument, NULL, OPTION_OBJECT}, - {"trace", required_argument, NULL, 'T'}, - {"version", no_argument, NULL, 'V'}, - {0, 0, 0, 0} - }; - - /* - * In contrast to the system emulator, options are processed in the order - * they are given on the command lines. This means that things must be - * defined first before they can be referenced in another option. - */ - while ((c = getopt_long(argc, argv, "hT:V", long_options, NULL)) != -1) { - switch (c) { - case '?': - exit(EXIT_FAILURE); - case 'h': - help(); - exit(EXIT_SUCCESS); - case 'T': - { - char *trace_file = trace_opt_parse(optarg); - trace_init_file(trace_file); - g_free(trace_file); - break; - } - case 'V': - printf("qemu-storage-daemon version " - QEMU_FULL_VERSION "\n" QEMU_COPYRIGHT "\n"); - exit(EXIT_SUCCESS); - case OPTION_BLOCKDEV: - { - Visitor *v; - BlockdevOptions *options; - - v = qobject_input_visitor_new_str(optarg, "driver", - &error_fatal); - - visit_type_BlockdevOptions(v, NULL, &options, &error_fatal); - visit_free(v); - - qmp_blockdev_add(options, &error_fatal); - qapi_free_BlockdevOptions(options); - break; - } - case OPTION_CHARDEV: - { - /* TODO This interface is not stable until we QAPIfy it */ - QemuOpts *opts = qemu_opts_parse_noisily(&qemu_chardev_opts, - optarg, true); - if (opts == NULL) { - exit(EXIT_FAILURE); - } - - if (!qemu_chr_new_from_opts(opts, NULL, &error_fatal)) { - /* No error, but NULL returned means help was printed */ - exit(EXIT_SUCCESS); - } - qemu_opts_del(opts); - break; - } - case OPTION_EXPORT: - { - Visitor *v; - BlockExport *export; - - v = qobject_input_visitor_new_str(optarg, "type", &error_fatal); - visit_type_BlockExport(v, NULL, &export, &error_fatal); - visit_free(v); - - init_export(export, &error_fatal); - qapi_free_BlockExport(export); - break; - } - case OPTION_MONITOR: - { - Visitor *v; - MonitorOptions *monitor; - - v = qobject_input_visitor_new_str(optarg, "chardev", - &error_fatal); - visit_type_MonitorOptions(v, NULL, &monitor, &error_fatal); - visit_free(v); - - /* TODO Catch duplicate monitor IDs */ - monitor_init(monitor, false, &error_fatal); - qapi_free_MonitorOptions(monitor); - break; - } - case OPTION_NBD_SERVER: - { - Visitor *v; - NbdServerOptions *options; - - v = qobject_input_visitor_new_str(optarg, NULL, &error_fatal); - visit_type_NbdServerOptions(v, NULL, &options, &error_fatal); - visit_free(v); - - nbd_server_start_options(options, &error_fatal); - qapi_free_NbdServerOptions(options); - break; - } - case OPTION_OBJECT: - { - QemuOpts *opts; - const char *type; - QDict *args; - - /* FIXME The keyval parser rejects 'help' arguments, so we must - * unconditionall try QemuOpts first. */ - opts = qemu_opts_parse(&qemu_object_opts, - optarg, true, &error_fatal); - type = qemu_opt_get(opts, "qom-type"); - if (type && user_creatable_print_help(type, opts)) { - exit(EXIT_SUCCESS); - } - qemu_opts_del(opts); - - args = keyval_parse(optarg, "qom-type", &error_fatal); - user_creatable_add_dict(args, true, &error_fatal); - qobject_unref(args); - break; - } - default: - g_assert_not_reached(); - } - } - if (optind != argc) { - error_report("Unexpected argument: %s", argv[optind]); - exit(EXIT_FAILURE); - } -} - -int main(int argc, char *argv[]) -{ -#ifdef CONFIG_POSIX - signal(SIGPIPE, SIG_IGN); -#endif - - error_init(argv[0]); - qemu_init_exec_dir(argv[0]); - os_setup_signal_handling(); - - module_call_init(MODULE_INIT_QOM); - module_call_init(MODULE_INIT_TRACE); - qemu_add_opts(&qemu_object_opts); - qemu_add_opts(&qemu_trace_opts); - qcrypto_init(&error_fatal); - bdrv_init(); - monitor_init_globals_core(); - init_qmp_commands(); - - if (!trace_init_backends()) { - return EXIT_FAILURE; - } - qemu_set_log(LOG_TRACE); - - qemu_init_main_loop(&error_fatal); - process_options(argc, argv); - - while (!exit_requested) { - main_loop_wait(false); - } - - monitor_cleanup(); - qemu_chr_cleanup(); - user_creatable_cleanup(); - - return EXIT_SUCCESS; -} diff --git a/storage-daemon/Makefile.objs b/storage-daemon/Makefile.objs deleted file mode 100644 index 41c0d02178..0000000000 --- a/storage-daemon/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -storage-daemon-obj-y = qapi/libqsd-qapi.fa - -qemu-storage-daemon.o: storage-daemon/qapi/qapi-commands.h storage-daemon/qapi/qapi-init-commands.h diff --git a/storage-daemon/meson.build b/storage-daemon/meson.build index 35f8949924..0409acc3f5 100644 --- a/storage-daemon/meson.build +++ b/storage-daemon/meson.build @@ -1 +1,14 @@ +qsd_ss = ss.source_set() +qsd_ss.add(files('qemu-storage-daemon.c')) +qsd_ss.add(block, chardev, qmp, qom, qemuutil) +qsd_ss.add_all(blockdev_ss) + subdir('qapi') + +if have_tools + qsd_ss = qsd_ss.apply(config_host, strict: false) + executable('qemu-storage-daemon', + qsd_ss.sources(), + dependencies: qsd_ss.dependencies(), + install: true) +endif diff --git a/storage-daemon/qapi/meson.build b/storage-daemon/qapi/meson.build index 7a2b041247..cea618bec0 100644 --- a/storage-daemon/qapi/meson.build +++ b/storage-daemon/qapi/meson.build @@ -4,7 +4,4 @@ qsd_qapi_files = custom_target('QAPI files for qemu-storage-daemon', command: [ qapi_gen, '-o', 'storage-daemon/qapi', '@INPUT@' ], depend_files: [ qapi_inputs, qapi_gen_depends ]) -static_library('qsd-qapi', - qsd_qapi_files.to_list(), - name_suffix: 'fa', - build_by_default: false) +qsd_ss.add(qsd_qapi_files.to_list()) diff --git a/storage-daemon/qemu-storage-daemon.c b/storage-daemon/qemu-storage-daemon.c new file mode 100644 index 0000000000..7e9b0e0d3f --- /dev/null +++ b/storage-daemon/qemu-storage-daemon.c @@ -0,0 +1,343 @@ +/* + * QEMU storage daemon + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2019 Kevin Wolf + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include + +#include "block/block.h" +#include "block/nbd.h" +#include "chardev/char.h" +#include "crypto/init.h" +#include "monitor/monitor.h" +#include "monitor/monitor-internal.h" + +#include "qapi/error.h" +#include "qapi/qapi-visit-block.h" +#include "qapi/qapi-visit-block-core.h" +#include "qapi/qapi-visit-control.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qstring.h" +#include "qapi/qobject-input-visitor.h" + +#include "qemu-common.h" +#include "qemu-version.h" +#include "qemu/config-file.h" +#include "qemu/error-report.h" +#include "qemu/help_option.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/module.h" +#include "qemu/option.h" +#include "qom/object_interfaces.h" + +#include "storage-daemon/qapi/qapi-commands.h" +#include "storage-daemon/qapi/qapi-init-commands.h" + +#include "sysemu/runstate.h" +#include "trace/control.h" + +static volatile bool exit_requested = false; + +void qemu_system_killed(int signal, pid_t pid) +{ + exit_requested = true; +} + +void qmp_quit(Error **errp) +{ + exit_requested = true; +} + +static void help(void) +{ + printf( +"Usage: %s [options]\n" +"QEMU storage daemon\n" +"\n" +" -h, --help display this help and exit\n" +" -T, --trace [[enable=]][,events=][,file=]\n" +" specify tracing options\n" +" -V, --version output version information and exit\n" +"\n" +" --blockdev [driver=][,node-name=][,discard=ignore|unmap]\n" +" [,cache.direct=on|off][,cache.no-flush=on|off]\n" +" [,read-only=on|off][,auto-read-only=on|off]\n" +" [,force-share=on|off][,detect-zeroes=on|off|unmap]\n" +" [,driver specific parameters...]\n" +" configure a block backend\n" +"\n" +" --chardev configure a character device backend\n" +" (see the qemu(1) man page for possible options)\n" +"\n" +" --export [type=]nbd,device=[,name=]\n" +" [,writable=on|off][,bitmap=]\n" +" export the specified block node over NBD\n" +" (requires --nbd-server)\n" +"\n" +" --monitor [chardev=]name[,mode=control][,pretty[=on|off]]\n" +" configure a QMP monitor\n" +"\n" +" --nbd-server addr.type=inet,addr.host=,addr.port=\n" +" [,tls-creds=][,tls-authz=]\n" +" --nbd-server addr.type=unix,addr.path=\n" +" [,tls-creds=][,tls-authz=]\n" +" start an NBD server for exporting block nodes\n" +"\n" +" --object help list object types that can be added\n" +" --object ,help list properties for the given object type\n" +" --object [,=...]\n" +" create a new object of type , setting\n" +" properties in the order they are specified. Note\n" +" that the 'id' property must be set.\n" +" See the qemu(1) man page for documentation of the\n" +" objects that can be added.\n" +"\n" +QEMU_HELP_BOTTOM "\n", + error_get_progname()); +} + +enum { + OPTION_BLOCKDEV = 256, + OPTION_CHARDEV, + OPTION_EXPORT, + OPTION_MONITOR, + OPTION_NBD_SERVER, + OPTION_OBJECT, +}; + +extern QemuOptsList qemu_chardev_opts; + +static QemuOptsList qemu_object_opts = { + .name = "object", + .implied_opt_name = "qom-type", + .head = QTAILQ_HEAD_INITIALIZER(qemu_object_opts.head), + .desc = { + { } + }, +}; + +static void init_qmp_commands(void) +{ + qmp_init_marshal(&qmp_commands); + qmp_register_command(&qmp_commands, "query-qmp-schema", + qmp_query_qmp_schema, QCO_ALLOW_PRECONFIG); + + QTAILQ_INIT(&qmp_cap_negotiation_commands); + qmp_register_command(&qmp_cap_negotiation_commands, "qmp_capabilities", + qmp_marshal_qmp_capabilities, QCO_ALLOW_PRECONFIG); +} + +static void init_export(BlockExport *export, Error **errp) +{ + switch (export->type) { + case BLOCK_EXPORT_TYPE_NBD: + qmp_nbd_server_add(&export->u.nbd, errp); + break; + default: + g_assert_not_reached(); + } +} + +static void process_options(int argc, char *argv[]) +{ + int c; + + static const struct option long_options[] = { + {"blockdev", required_argument, NULL, OPTION_BLOCKDEV}, + {"chardev", required_argument, NULL, OPTION_CHARDEV}, + {"export", required_argument, NULL, OPTION_EXPORT}, + {"help", no_argument, NULL, 'h'}, + {"monitor", required_argument, NULL, OPTION_MONITOR}, + {"nbd-server", required_argument, NULL, OPTION_NBD_SERVER}, + {"object", required_argument, NULL, OPTION_OBJECT}, + {"trace", required_argument, NULL, 'T'}, + {"version", no_argument, NULL, 'V'}, + {0, 0, 0, 0} + }; + + /* + * In contrast to the system emulator, options are processed in the order + * they are given on the command lines. This means that things must be + * defined first before they can be referenced in another option. + */ + while ((c = getopt_long(argc, argv, "hT:V", long_options, NULL)) != -1) { + switch (c) { + case '?': + exit(EXIT_FAILURE); + case 'h': + help(); + exit(EXIT_SUCCESS); + case 'T': + { + char *trace_file = trace_opt_parse(optarg); + trace_init_file(trace_file); + g_free(trace_file); + break; + } + case 'V': + printf("qemu-storage-daemon version " + QEMU_FULL_VERSION "\n" QEMU_COPYRIGHT "\n"); + exit(EXIT_SUCCESS); + case OPTION_BLOCKDEV: + { + Visitor *v; + BlockdevOptions *options; + + v = qobject_input_visitor_new_str(optarg, "driver", + &error_fatal); + + visit_type_BlockdevOptions(v, NULL, &options, &error_fatal); + visit_free(v); + + qmp_blockdev_add(options, &error_fatal); + qapi_free_BlockdevOptions(options); + break; + } + case OPTION_CHARDEV: + { + /* TODO This interface is not stable until we QAPIfy it */ + QemuOpts *opts = qemu_opts_parse_noisily(&qemu_chardev_opts, + optarg, true); + if (opts == NULL) { + exit(EXIT_FAILURE); + } + + if (!qemu_chr_new_from_opts(opts, NULL, &error_fatal)) { + /* No error, but NULL returned means help was printed */ + exit(EXIT_SUCCESS); + } + qemu_opts_del(opts); + break; + } + case OPTION_EXPORT: + { + Visitor *v; + BlockExport *export; + + v = qobject_input_visitor_new_str(optarg, "type", &error_fatal); + visit_type_BlockExport(v, NULL, &export, &error_fatal); + visit_free(v); + + init_export(export, &error_fatal); + qapi_free_BlockExport(export); + break; + } + case OPTION_MONITOR: + { + Visitor *v; + MonitorOptions *monitor; + + v = qobject_input_visitor_new_str(optarg, "chardev", + &error_fatal); + visit_type_MonitorOptions(v, NULL, &monitor, &error_fatal); + visit_free(v); + + /* TODO Catch duplicate monitor IDs */ + monitor_init(monitor, false, &error_fatal); + qapi_free_MonitorOptions(monitor); + break; + } + case OPTION_NBD_SERVER: + { + Visitor *v; + NbdServerOptions *options; + + v = qobject_input_visitor_new_str(optarg, NULL, &error_fatal); + visit_type_NbdServerOptions(v, NULL, &options, &error_fatal); + visit_free(v); + + nbd_server_start_options(options, &error_fatal); + qapi_free_NbdServerOptions(options); + break; + } + case OPTION_OBJECT: + { + QemuOpts *opts; + const char *type; + QDict *args; + + /* FIXME The keyval parser rejects 'help' arguments, so we must + * unconditionall try QemuOpts first. */ + opts = qemu_opts_parse(&qemu_object_opts, + optarg, true, &error_fatal); + type = qemu_opt_get(opts, "qom-type"); + if (type && user_creatable_print_help(type, opts)) { + exit(EXIT_SUCCESS); + } + qemu_opts_del(opts); + + args = keyval_parse(optarg, "qom-type", &error_fatal); + user_creatable_add_dict(args, true, &error_fatal); + qobject_unref(args); + break; + } + default: + g_assert_not_reached(); + } + } + if (optind != argc) { + error_report("Unexpected argument: %s", argv[optind]); + exit(EXIT_FAILURE); + } +} + +int main(int argc, char *argv[]) +{ +#ifdef CONFIG_POSIX + signal(SIGPIPE, SIG_IGN); +#endif + + error_init(argv[0]); + qemu_init_exec_dir(argv[0]); + os_setup_signal_handling(); + + module_call_init(MODULE_INIT_QOM); + module_call_init(MODULE_INIT_TRACE); + qemu_add_opts(&qemu_object_opts); + qemu_add_opts(&qemu_trace_opts); + qcrypto_init(&error_fatal); + bdrv_init(); + monitor_init_globals_core(); + init_qmp_commands(); + + if (!trace_init_backends()) { + return EXIT_FAILURE; + } + qemu_set_log(LOG_TRACE); + + qemu_init_main_loop(&error_fatal); + process_options(argc, argv); + + while (!exit_requested) { + main_loop_wait(false); + } + + monitor_cleanup(); + qemu_chr_cleanup(); + user_creatable_cleanup(); + + return EXIT_SUCCESS; +} -- cgit v1.2.3-55-g7522 From 17ef2af6b67f29bb5c5c687f07216544830f167a Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 22 Jul 2019 23:40:45 +0400 Subject: meson: convert replay directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 1 - meson.build | 1 + replay/Makefile.objs | 10 ---------- replay/meson.build | 12 ++++++++++++ 4 files changed, 13 insertions(+), 11 deletions(-) delete mode 100644 replay/Makefile.objs create mode 100644 replay/meson.build diff --git a/Makefile.objs b/Makefile.objs index e304d92954..cfb2cf2b49 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -68,7 +68,6 @@ common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF common-obj-y += hw/ common-obj-m += hw/ -common-obj-y += replay/ common-obj-y += backends/ common-obj-y += qapi/ diff --git a/meson.build b/meson.build index 4ff3f7bccb..60313b2eae 100644 --- a/meson.build +++ b/meson.build @@ -656,6 +656,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') subdir('monitor') +subdir('replay') # needed for fuzzing binaries subdir('tests/qtest/libqos') diff --git a/replay/Makefile.objs b/replay/Makefile.objs deleted file mode 100644 index 939be964a9..0000000000 --- a/replay/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -common-obj-y += replay.o -common-obj-y += replay-internal.o -common-obj-y += replay-events.o -common-obj-y += replay-time.o -common-obj-y += replay-input.o -common-obj-y += replay-char.o -common-obj-y += replay-snapshot.o -common-obj-y += replay-net.o -common-obj-y += replay-audio.o -common-obj-y += replay-random.o diff --git a/replay/meson.build b/replay/meson.build new file mode 100644 index 0000000000..8783aea7c8 --- /dev/null +++ b/replay/meson.build @@ -0,0 +1,12 @@ +softmmu_ss.add(files( + 'replay.c', + 'replay-internal.c', + 'replay-events.c', + 'replay-time.c', + 'replay-input.c', + 'replay-char.c', + 'replay-snapshot.c', + 'replay-net.c', + 'replay-audio.c', + 'replay-random.c', +)) -- cgit v1.2.3-55-g7522 From 5516623020db6a4f3ebee42b2fd6a5c517f939a9 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Wed, 24 Jul 2019 19:16:22 +0400 Subject: meson: convert migration directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 1 - Makefile.target | 1 - meson.build | 5 +++++ migration/Makefile.objs | 18 ------------------ migration/meson.build | 40 ++++++++++++++++++++++++++++++++++++++++ tests/Makefile.include | 7 +++---- 6 files changed, 48 insertions(+), 24 deletions(-) delete mode 100644 migration/Makefile.objs create mode 100644 migration/meson.build diff --git a/Makefile.objs b/Makefile.objs index cfb2cf2b49..9d0a82d82a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -43,7 +43,6 @@ common-obj-y = net/ common-obj-$(CONFIG_LINUX) += fsdev/ common-obj-y += accel/ -common-obj-y += migration/ common-obj-$(CONFIG_AUDIO_ALSA) += audio-alsa$(DSOSUF) common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) diff --git a/Makefile.target b/Makefile.target index 54a9ef1330..4d912df3a3 100644 --- a/Makefile.target +++ b/Makefile.target @@ -158,7 +158,6 @@ obj-y += softmmu/ obj-y += gdbstub.o obj-y += hw/ obj-y += qapi/ -obj-y += migration/ram.o LIBS := $(libs_softmmu) $(LIBS) # Temporary until emulators are linked by Meson diff --git a/meson.build b/meson.build index 60313b2eae..9bc1a2ac0d 100644 --- a/meson.build +++ b/meson.build @@ -308,6 +308,10 @@ lzo = not_found if 'CONFIG_LZO' in config_host lzo = declare_dependency(link_args: config_host['LZO_LIBS'].split()) endif +rdma = not_found +if 'CONFIG_RDMA' in config_host + rdma = declare_dependency(link_args: config_host['RDMA_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -655,6 +659,7 @@ softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) common_ss.add(files('cpus-common.c')) subdir('softmmu') +subdir('migration') subdir('monitor') subdir('replay') diff --git a/migration/Makefile.objs b/migration/Makefile.objs deleted file mode 100644 index 0fc619e380..0000000000 --- a/migration/Makefile.objs +++ /dev/null @@ -1,18 +0,0 @@ -common-obj-y += migration.o socket.o fd.o exec.o -common-obj-y += tls.o channel.o savevm.o -common-obj-y += colo.o colo-failover.o -common-obj-y += vmstate.o vmstate-types.o page_cache.o -common-obj-y += qemu-file.o global_state.o -common-obj-y += qemu-file-channel.o -common-obj-y += xbzrle.o postcopy-ram.o -common-obj-y += qjson.o -common-obj-y += block-dirty-bitmap.o -common-obj-y += multifd.o -common-obj-y += multifd-zlib.o -common-obj-$(CONFIG_ZSTD) += multifd-zstd.o - -common-obj-$(CONFIG_RDMA) += rdma.o - -common-obj-$(CONFIG_LIVE_BLOCK_MIGRATION) += block.o - -rdma.o-libs := $(RDMA_LIBS) diff --git a/migration/meson.build b/migration/meson.build new file mode 100644 index 0000000000..ac8ff1419f --- /dev/null +++ b/migration/meson.build @@ -0,0 +1,40 @@ +# Files needed by unit tests +migration_files = files( + 'page_cache.c', + 'xbzrle.c', + 'vmstate-types.c', + 'vmstate.c', + 'qemu-file-channel.c', + 'qemu-file.c', + 'qjson.c', +) + +libmigration = static_library('migration', sources: migration_files + genh, + name_suffix: 'fa', + build_by_default: false) +migration = declare_dependency(link_with: libmigration, + dependencies: [zlib, qom, io]) +softmmu_ss.add(migration) + +softmmu_ss.add(files( + 'block-dirty-bitmap.c', + 'channel.c', + 'colo-failover.c', + 'colo.c', + 'exec.c', + 'fd.c', + 'global_state.c', + 'migration.c', + 'multifd.c', + 'multifd-zlib.c', + 'postcopy-ram.c', + 'savevm.c', + 'socket.c', + 'tls.c', +)) + +softmmu_ss.add(when: ['CONFIG_RDMA', rdma], if_true: files('rdma.c')) +softmmu_ss.add(when: 'CONFIG_LIVE_BLOCK_MIGRATION', if_true: files('block.c')) +softmmu_ss.add(when: 'CONFIG_ZSTD', if_true: [files('multifd-zstd.c'), zstd]) + +specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files('ram.c')) diff --git a/tests/Makefile.include b/tests/Makefile.include index 99fb5132f7..8ac9c68f04 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -227,7 +227,8 @@ tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y) tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) $(test-crypto-obj-y) tests/test-bitmap$(EXESUF): tests/test-bitmap.o $(test-util-obj-y) tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o -tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o migration/page_cache.o $(test-util-obj-y) +tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/libmigration.fa $(test-util-obj-y) \ + $(test-io-obj-y) tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o $(test-util-obj-y) tests/test-int128$(EXESUF): tests/test-int128.o tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y) @@ -253,9 +254,7 @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/vmstate-if.o \ hw/core/clock.o hw/core/qdev-clock.o \ $(test-qapi-obj-y) -tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ - migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ - migration/qemu-file-channel.o migration/qjson.o \ +tests/test-vmstate$(EXESUF): tests/test-vmstate.o migration/libmigration.fa \ $(test-io-obj-y) tests/test-timed-average$(EXESUF): tests/test-timed-average.o $(test-util-obj-y) tests/test-base64$(EXESUF): tests/test-base64.o $(test-util-obj-y) -- cgit v1.2.3-55-g7522 From cdaf07228cf42d708fe24371a68cec022841e018 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 22 Jul 2019 23:47:50 +0400 Subject: meson: convert net directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 3 +-- Makefile.target | 1 + meson.build | 10 ++++++++++ net/Makefile.objs | 32 -------------------------------- net/can/Makefile.objs | 2 -- net/can/meson.build | 5 +++++ net/meson.build | 40 ++++++++++++++++++++++++++++++++++++++++ 7 files changed, 57 insertions(+), 36 deletions(-) delete mode 100644 net/Makefile.objs delete mode 100644 net/can/Makefile.objs create mode 100644 net/can/meson.build create mode 100644 net/meson.build diff --git a/Makefile.objs b/Makefile.objs index 9d0a82d82a..f2700442a4 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -39,8 +39,7 @@ endif # CONFIG_SOFTMMU or CONFIG_TOOLS # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = net/ -common-obj-$(CONFIG_LINUX) += fsdev/ +common-obj-$(CONFIG_LINUX) = fsdev/ common-obj-y += accel/ diff --git a/Makefile.target b/Makefile.target index 4d912df3a3..bf3fda92c1 100644 --- a/Makefile.target +++ b/Makefile.target @@ -168,6 +168,7 @@ LIBS := $(LIBS) $(GTK_LIBS) $(VTE_LIBS) $(X11_LIBS) $(CURSES_LIBS) $(ICONV_LIBS) endif LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOMP_LIBS) LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) +LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) # Hardware support ifeq ($(TARGET_NAME), sparc64) diff --git a/meson.build b/meson.build index 9bc1a2ac0d..ead9420844 100644 --- a/meson.build +++ b/meson.build @@ -149,6 +149,15 @@ if 'CONFIG_XKBCOMMON' in config_host xkbcommon = declare_dependency(compile_args: config_host['XKBCOMMON_CFLAGS'].split(), link_args: config_host['XKBCOMMON_LIBS'].split()) endif +slirp = not_found +if config_host.has_key('CONFIG_SLIRP') + slirp = declare_dependency(compile_args: config_host['SLIRP_CFLAGS'].split(), + link_args: config_host['SLIRP_LIBS'].split()) +endif +vde = not_found +if config_host.has_key('CONFIG_VDE') + vde = declare_dependency(link_args: config_host['VDE_LIBS'].split()) +endif pulse = not_found if 'CONFIG_LIBPULSE' in config_host pulse = declare_dependency(compile_args: config_host['PULSE_CFLAGS'].split(), @@ -661,6 +670,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') subdir('migration') subdir('monitor') +subdir('net') subdir('replay') # needed for fuzzing binaries diff --git a/net/Makefile.objs b/net/Makefile.objs deleted file mode 100644 index 5ab45545db..0000000000 --- a/net/Makefile.objs +++ /dev/null @@ -1,32 +0,0 @@ -common-obj-y = net.o queue.o checksum.o util.o hub.o -common-obj-y += socket.o -common-obj-y += dump.o -common-obj-y += eth.o -common-obj-y += announce.o -common-obj-$(CONFIG_L2TPV3) += l2tpv3.o -common-obj-$(call land,$(CONFIG_VIRTIO_NET),$(CONFIG_VHOST_NET_USER)) += vhost-user.o -common-obj-$(call land,$(call lnot,$(CONFIG_VIRTIO_NET)),$(CONFIG_VHOST_NET_USER)) += vhost-user-stub.o -common-obj-$(CONFIG_ALL) += vhost-user-stub.o -common-obj-$(CONFIG_SLIRP) += slirp.o -slirp.o-cflags := $(SLIRP_CFLAGS) -slirp.o-libs := $(SLIRP_LIBS) -common-obj-$(CONFIG_VDE) += vde.o -common-obj-$(CONFIG_NETMAP) += netmap.o -common-obj-y += filter.o -common-obj-y += filter-buffer.o -common-obj-y += filter-mirror.o -common-obj-y += colo-compare.o -common-obj-y += colo.o -common-obj-y += filter-rewriter.o -common-obj-y += filter-replay.o - -tap-obj-$(CONFIG_LINUX) = tap-linux.o -tap-obj-$(CONFIG_BSD) = tap-bsd.o -tap-obj-$(CONFIG_SOLARIS) = tap-solaris.o -tap-obj-y ?= tap-stub.o -common-obj-$(CONFIG_POSIX) += tap.o $(tap-obj-y) -common-obj-$(CONFIG_WIN32) += tap-win32.o -common-obj-$(CONFIG_VHOST_NET_VDPA) += vhost-vdpa.o -vde.o-libs = $(VDE_LIBS) - -common-obj-$(CONFIG_CAN_BUS) += can/ diff --git a/net/can/Makefile.objs b/net/can/Makefile.objs deleted file mode 100644 index 9f35dc5c87..0000000000 --- a/net/can/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -common-obj-y += can_core.o can_host.o -common-obj-$(CONFIG_LINUX) += can_socketcan.o diff --git a/net/can/meson.build b/net/can/meson.build new file mode 100644 index 0000000000..f53d9ec54f --- /dev/null +++ b/net/can/meson.build @@ -0,0 +1,5 @@ +can_ss = ss.source_set() +can_ss.add(files('can_core.c', 'can_host.c')) +can_ss.add(when: 'CONFIG_LINUX', if_true: files('can_socketcan.c')) + +softmmu_ss.add_all(when: 'CONFIG_CAN_BUS', if_true: can_ss) diff --git a/net/meson.build b/net/meson.build new file mode 100644 index 0000000000..6c2ec47dd5 --- /dev/null +++ b/net/meson.build @@ -0,0 +1,40 @@ +softmmu_ss.add(files( + 'announce.c', + 'checksum.c', + 'colo-compare.c', + 'colo.c', + 'dump.c', + 'eth.c', + 'filter-buffer.c', + 'filter-mirror.c', + 'filter-replay.c', + 'filter-rewriter.c', + 'filter.c', + 'hub.c', + 'net.c', + 'queue.c', + 'socket.c', + 'util.c', +)) + +softmmu_ss.add(when: 'CONFIG_L2TPV3', if_true: files('l2tpv3.c')) +softmmu_ss.add(when: ['CONFIG_SLIRP', slirp], if_true: files('slirp.c')) +softmmu_ss.add(when: ['CONFIG_VDE', vde], if_true: files('vde.c')) +softmmu_ss.add(when: 'CONFIG_NETMAP', if_true: files('netmap.c')) +vhost_user_ss = ss.source_set() +vhost_user_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('vhost-user.c'), if_false: files('vhost-user-stub.c')) +softmmu_ss.add_all(when: 'CONFIG_VHOST_NET_USER', if_true: vhost_user_ss) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('vhost-user-stub.c')) + +softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('tap-linux.c')) +softmmu_ss.add(when: 'CONFIG_BSD', if_true: files('tap-bsd.c')) +softmmu_ss.add(when: 'CONFIG_SOLARIS', if_true: files('tap-solaris.c')) +tap_posix = ['tap.c'] +if not config_host.has_key('CONFIG_LINUX') and not config_host.has_key('CONFIG_BSD') and not config_host.has_key('CONFIG_SOLARIS') + tap_posix += 'tap-stub.c' +endif +softmmu_ss.add(when: 'CONFIG_POSIX', if_true: files(tap_posix)) +softmmu_ss.add(when: 'CONFIG_WIN32', if_true: files('tap-win32.c')) +softmmu_ss.add(when: 'CONFIG_VHOST_NET_VDPA', if_true: files('vhost-vdpa.c')) + +subdir('can') -- cgit v1.2.3-55-g7522 From ab3180515c6a5f080623cde07c9b89ece77abb19 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Wed, 24 Jul 2019 19:23:16 +0400 Subject: meson: convert backends directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 -- backends/Makefile.objs | 23 ----------------------- backends/meson.build | 19 +++++++++++++++++++ backends/tpm/Makefile.objs | 4 ---- backends/tpm/meson.build | 8 ++++++++ configure | 2 ++ meson.build | 5 +++++ 7 files changed, 34 insertions(+), 29 deletions(-) delete mode 100644 backends/Makefile.objs create mode 100644 backends/meson.build delete mode 100644 backends/tpm/Makefile.objs create mode 100644 backends/tpm/meson.build diff --git a/Makefile.objs b/Makefile.objs index f2700442a4..c00851a0cd 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -66,8 +66,6 @@ common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF common-obj-y += hw/ common-obj-m += hw/ -common-obj-y += backends/ - common-obj-y += qapi/ common-obj-y += libqmp.fa diff --git a/backends/Makefile.objs b/backends/Makefile.objs deleted file mode 100644 index 22d204cb48..0000000000 --- a/backends/Makefile.objs +++ /dev/null @@ -1,23 +0,0 @@ -common-obj-y += rng.o rng-egd.o rng-builtin.o -common-obj-$(CONFIG_POSIX) += rng-random.o - -common-obj-$(CONFIG_TPM) += tpm/ - -common-obj-y += hostmem.o hostmem-ram.o -common-obj-$(CONFIG_POSIX) += hostmem-file.o - -common-obj-y += cryptodev.o -common-obj-y += cryptodev-builtin.o - -ifeq ($(CONFIG_VIRTIO_CRYPTO),y) -common-obj-y += cryptodev-vhost.o -common-obj-$(CONFIG_VHOST_CRYPTO) += cryptodev-vhost-user.o -endif - -common-obj-$(call land,$(CONFIG_VHOST_USER),$(CONFIG_VIRTIO)) += vhost-user.o - -common-obj-$(CONFIG_LINUX) += hostmem-memfd.o - -common-obj-$(CONFIG_GIO) += dbus-vmstate.o -dbus-vmstate.o-cflags = $(GIO_CFLAGS) -dbus-vmstate.o-libs = $(GIO_LIBS) diff --git a/backends/meson.build b/backends/meson.build new file mode 100644 index 0000000000..484456ece7 --- /dev/null +++ b/backends/meson.build @@ -0,0 +1,19 @@ +softmmu_ss.add([files( + 'cryptodev-builtin.c', + 'cryptodev.c', + 'hostmem-ram.c', + 'hostmem.c', + 'rng-builtin.c', + 'rng-egd.c', + 'rng.c', +), numa]) + +softmmu_ss.add(when: 'CONFIG_POSIX', if_true: files('rng-random.c')) +softmmu_ss.add(when: 'CONFIG_POSIX', if_true: files('hostmem-file.c')) +softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('hostmem-memfd.c')) +softmmu_ss.add(when: ['CONFIG_VHOST_USER', 'CONFIG_VIRTIO'], if_true: files('vhost-user.c')) +softmmu_ss.add(when: 'CONFIG_VIRTIO_CRYPTO', if_true: files('cryptodev-vhost.c')) +softmmu_ss.add(when: ['CONFIG_VIRTIO_CRYPTO', 'CONFIG_VHOST_CRYPTO'], if_true: files('cryptodev-vhost-user.c')) +softmmu_ss.add(when: 'CONFIG_GIO', if_true: [files('dbus-vmstate.c'), gio]) + +subdir('tpm') diff --git a/backends/tpm/Makefile.objs b/backends/tpm/Makefile.objs deleted file mode 100644 index db2731f634..0000000000 --- a/backends/tpm/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -common-obj-y += tpm_backend.o -common-obj-y += tpm_util.o -common-obj-$(CONFIG_TPM_PASSTHROUGH) += tpm_passthrough.o -common-obj-$(CONFIG_TPM_EMULATOR) += tpm_emulator.o diff --git a/backends/tpm/meson.build b/backends/tpm/meson.build new file mode 100644 index 0000000000..857929082e --- /dev/null +++ b/backends/tpm/meson.build @@ -0,0 +1,8 @@ +tpm_ss = ss.source_set() + +tpm_ss.add(files('tpm_backend.c')) +tpm_ss.add(files('tpm_util.c')) +tpm_ss.add(when: 'CONFIG_TPM_PASSTHROUGH', if_true: files('tpm_passthrough.c')) +tpm_ss.add(when: 'CONFIG_TPM_EMULATOR', if_true: files('tpm_emulator.c')) + +softmmu_ss.add_all(when: 'CONFIG_TPM', if_true: tpm_ss) diff --git a/configure b/configure index a56de5621a..06a6e93c09 100755 --- a/configure +++ b/configure @@ -4741,6 +4741,7 @@ EOF if compile_prog "" "-lnuma" ; then numa=yes libs_softmmu="-lnuma $libs_softmmu" + numa_libs="-lnuma" else if test "$numa" = "yes" ; then feature_not_found "numa" "install numactl devel" @@ -8367,6 +8368,7 @@ fi if test "$numa" = "yes"; then echo "CONFIG_NUMA=y" >> $config_host_mak + echo "NUMA_LIBS=$numa_libs" >> $config_host_mak fi if test "$ccache_cpp2" = "yes"; then diff --git a/meson.build b/meson.build index ead9420844..06755f34b3 100644 --- a/meson.build +++ b/meson.build @@ -321,6 +321,10 @@ rdma = not_found if 'CONFIG_RDMA' in config_host rdma = declare_dependency(link_args: config_host['RDMA_LIBS'].split()) endif +numa = not_found +if 'CONFIG_NUMA' in config_host + numa = declare_dependency(link_args: config_host['NUMA_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -668,6 +672,7 @@ softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) common_ss.add(files('cpus-common.c')) subdir('softmmu') +subdir('backends') subdir('migration') subdir('monitor') subdir('net') -- cgit v1.2.3-55-g7522 From 5eead72bd3282decd055b60977f45046fdf7e4c2 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 25 Jul 2019 14:22:34 +0400 Subject: meson: convert fsdev/ Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 4 +--- configure | 1 - fsdev/Makefile.objs | 12 ------------ fsdev/meson.build | 10 ++++++++++ 4 files changed, 11 insertions(+), 16 deletions(-) delete mode 100644 fsdev/Makefile.objs diff --git a/Makefile.objs b/Makefile.objs index c00851a0cd..7158031c0c 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -39,9 +39,7 @@ endif # CONFIG_SOFTMMU or CONFIG_TOOLS # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-$(CONFIG_LINUX) = fsdev/ - -common-obj-y += accel/ +common-obj-y = accel/ common-obj-$(CONFIG_AUDIO_ALSA) += audio-alsa$(DSOSUF) common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) diff --git a/configure b/configure index 06a6e93c09..09e1ffc1a0 100755 --- a/configure +++ b/configure @@ -3751,7 +3751,6 @@ int main(void) EOF if compile_prog "" "$cap_libs" ; then cap_ng=yes - libs_tools="$cap_libs $libs_tools" else if test "$cap_ng" = "yes" ; then feature_not_found "cap_ng" "Install libcap-ng devel" diff --git a/fsdev/Makefile.objs b/fsdev/Makefile.objs deleted file mode 100644 index 42cd70c367..0000000000 --- a/fsdev/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -# Lots of the fsdev/9pcode is pulled in by vl.c via qemu_fsdev_add. -# only pull in the actual 9p backend if we also enabled virtio or xen. -ifeq ($(CONFIG_FSDEV_9P),y) -common-obj-y = qemu-fsdev.o 9p-marshal.o 9p-iov-marshal.o -else -common-obj-y = qemu-fsdev-dummy.o -endif -common-obj-y += qemu-fsdev-opts.o qemu-fsdev-throttle.o - -# Toplevel always builds this; targets without virtio will put it in -# common-obj-y -common-obj-$(CONFIG_ALL) += qemu-fsdev-dummy.o diff --git a/fsdev/meson.build b/fsdev/meson.build index 30e2319960..7dd1cc9bfb 100644 --- a/fsdev/meson.build +++ b/fsdev/meson.build @@ -1,3 +1,13 @@ +fsdev_ss = ss.source_set() +fsdev_ss.add(files('qemu-fsdev-opts.c', 'qemu-fsdev-throttle.c')) +fsdev_ss.add(when: 'CONFIG_ALL', if_true: files('qemu-fsdev-dummy.c')) +fsdev_ss.add(when: ['CONFIG_FSDEV_9P'], if_true: files( + '9p-iov-marshal.c', + '9p-marshal.c', + 'qemu-fsdev.c', +), if_false: files('qemu-fsdev-dummy.c')) +softmmu_ss.add_all(when: 'CONFIG_LINUX', if_true: fsdev_ss) + have_virtfs_proxy_helper = have_tools and libattr.found() and libcap_ng.found() and 'CONFIG_VIRTFS' in config_host if have_virtfs_proxy_helper executable('virtfs-proxy-helper', -- cgit v1.2.3-55-g7522 From c574e161120aa0b8c76ee90d21d43c6e53e7f1ba Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 26 Jul 2019 12:02:31 +0400 Subject: meson: convert disas directory to Meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 -- disas/Makefile.objs | 30 ------------------------------ disas/libvixl/Makefile.objs | 5 ----- disas/libvixl/meson.build | 7 +++++++ disas/meson.build | 27 +++++++++++++++++++++++++++ meson.build | 1 + 6 files changed, 35 insertions(+), 37 deletions(-) delete mode 100644 disas/Makefile.objs delete mode 100644 disas/libvixl/Makefile.objs create mode 100644 disas/libvixl/meson.build create mode 100644 disas/meson.build diff --git a/Makefile.objs b/Makefile.objs index 7158031c0c..3b32a4c9bb 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -74,8 +74,6 @@ endif # CONFIG_SOFTMMU # Target-independent parts used in system and user emulation common-obj-y += hw/ -common-obj-y += qom/ -common-obj-y += disas/ ###################################################################### # Resource file for Windows executables diff --git a/disas/Makefile.objs b/disas/Makefile.objs deleted file mode 100644 index 3c1cdce026..0000000000 --- a/disas/Makefile.objs +++ /dev/null @@ -1,30 +0,0 @@ - -common-obj-$(CONFIG_ALPHA_DIS) += alpha.o -common-obj-$(CONFIG_ARM_DIS) += arm.o -common-obj-$(CONFIG_ARM_A64_DIS) += arm-a64.o -common-obj-$(CONFIG_ARM_A64_DIS) += libvixl/ -libvixldir = $(SRC_PATH)/disas/libvixl -# The -Wno-sign-compare is needed only for gcc 4.6, which complains about -# some signed-unsigned equality comparisons in libvixl which later gcc -# versions do not. -arm-a64.o-cflags := -I$(libvixldir) -Wno-sign-compare -common-obj-$(CONFIG_CRIS_DIS) += cris.o -common-obj-$(CONFIG_HPPA_DIS) += hppa.o -common-obj-$(CONFIG_I386_DIS) += i386.o -common-obj-$(CONFIG_M68K_DIS) += m68k.o -common-obj-$(CONFIG_MICROBLAZE_DIS) += microblaze.o -common-obj-$(CONFIG_MIPS_DIS) += mips.o -common-obj-$(CONFIG_NANOMIPS_DIS) += nanomips.o -common-obj-$(CONFIG_NIOS2_DIS) += nios2.o -common-obj-$(CONFIG_MOXIE_DIS) += moxie.o -common-obj-$(CONFIG_PPC_DIS) += ppc.o -common-obj-$(CONFIG_RISCV_DIS) += riscv.o -common-obj-$(CONFIG_S390_DIS) += s390.o -common-obj-$(CONFIG_SH4_DIS) += sh4.o -common-obj-$(CONFIG_SPARC_DIS) += sparc.o -common-obj-$(CONFIG_LM32_DIS) += lm32.o -common-obj-$(CONFIG_XTENSA_DIS) += xtensa.o - -# TODO: As long as the TCG interpreter and its generated code depend -# on the QEMU target, we cannot compile the disassembler here. -#common-obj-$(CONFIG_TCI_DIS) += tci.o diff --git a/disas/libvixl/Makefile.objs b/disas/libvixl/Makefile.objs deleted file mode 100644 index 99a637f6a0..0000000000 --- a/disas/libvixl/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -common-obj-$(CONFIG_ARM_A64_DIS) = vixl/utils.o \ - vixl/compiler-intrinsics.o \ - vixl/a64/instructions-a64.o \ - vixl/a64/decoder-a64.o \ - vixl/a64/disasm-a64.o diff --git a/disas/libvixl/meson.build b/disas/libvixl/meson.build new file mode 100644 index 0000000000..5e2eb33e8e --- /dev/null +++ b/disas/libvixl/meson.build @@ -0,0 +1,7 @@ +libvixl_ss.add(files( + 'vixl/a64/decoder-a64.cc', + 'vixl/a64/disasm-a64.cc', + 'vixl/a64/instructions-a64.cc', + 'vixl/compiler-intrinsics.cc', + 'vixl/utils.cc', +)) diff --git a/disas/meson.build b/disas/meson.build new file mode 100644 index 0000000000..0527d69128 --- /dev/null +++ b/disas/meson.build @@ -0,0 +1,27 @@ +libvixl_ss = ss.source_set() +subdir('libvixl') + +common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c')) +common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc')) +common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss) +common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c')) +common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c')) +common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c')) +common_ss.add(when: 'CONFIG_I386_DIS', if_true: files('i386.c')) +common_ss.add(when: 'CONFIG_LM32_DIS', if_true: files('lm32.c')) +common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c')) +common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c')) +common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c')) +common_ss.add(when: 'CONFIG_MOXIE_DIS', if_true: files('moxie.c')) +common_ss.add(when: 'CONFIG_NANOMIPS_DIS', if_true: files('nanomips.cpp')) +common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c')) +common_ss.add(when: 'CONFIG_PPC_DIS', if_true: files('ppc.c')) +common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('riscv.c')) +common_ss.add(when: 'CONFIG_S390_DIS', if_true: files('s390.c')) +common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) +common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) +common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c')) + +# TODO: As long as the TCG interpreter and its generated code depend +# on the QEMU target, we cannot compile the disassembler here. +#common_ss.add(when: 'CONFIG_TCI_DIS', if_true: files('tci.c')) diff --git a/meson.build b/meson.build index 06755f34b3..edb635347c 100644 --- a/meson.build +++ b/meson.build @@ -673,6 +673,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') subdir('backends') +subdir('disas') subdir('migration') subdir('monitor') subdir('net') -- cgit v1.2.3-55-g7522 From 5242523b5f35813c8e088bc8eae2fb4d4aa50dd6 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 12:01:26 +0400 Subject: meson: convert qapi-specific to meson Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 -- Makefile.target | 1 - qapi/Makefile.objs | 15 --------------- qapi/meson.build | 10 +++++++--- 4 files changed, 7 insertions(+), 21 deletions(-) delete mode 100644 qapi/Makefile.objs diff --git a/Makefile.objs b/Makefile.objs index 3b32a4c9bb..c332323b81 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -64,8 +64,6 @@ common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF common-obj-y += hw/ common-obj-m += hw/ -common-obj-y += qapi/ - common-obj-y += libqmp.fa endif # CONFIG_SOFTMMU diff --git a/Makefile.target b/Makefile.target index bf3fda92c1..386378b9c8 100644 --- a/Makefile.target +++ b/Makefile.target @@ -157,7 +157,6 @@ ifdef CONFIG_SOFTMMU obj-y += softmmu/ obj-y += gdbstub.o obj-y += hw/ -obj-y += qapi/ LIBS := $(libs_softmmu) $(LIBS) # Temporary until emulators are linked by Meson diff --git a/qapi/Makefile.objs b/qapi/Makefile.objs deleted file mode 100644 index c0a31be1a1..0000000000 --- a/qapi/Makefile.objs +++ /dev/null @@ -1,15 +0,0 @@ -QAPI_TARGET_MODULES = machine-target misc-target - -obj-y = qapi-introspect.o -obj-y += $(QAPI_TARGET_MODULES:%=qapi-types-%.o) -obj-y += qapi-types.o -obj-y += $(QAPI_TARGET_MODULES:%=qapi-visit-%.o) -obj-y += qapi-visit.o -obj-y += $(QAPI_TARGET_MODULES:%=qapi-events-%.o) -obj-y += qapi-events.o -obj-y += $(QAPI_TARGET_MODULES:%=qapi-commands-%.o) -obj-y += qapi-commands.o -obj-y += qapi-init-commands.o - -QAPI_MODULES_STORAGE_DAEMON = block-core char common control crypto -QAPI_MODULES_STORAGE_DAEMON += introspect job qom sockets pragma transaction diff --git a/qapi/meson.build b/qapi/meson.build index f45b80bbfa..2b2872a41d 100644 --- a/qapi/meson.build +++ b/qapi/meson.build @@ -114,8 +114,12 @@ foreach output : qapi_util_outputs i = i + 1 endforeach -# These are still handled by the Makefile -i += qapi_nonmodule_outputs.length() -i += qapi_specific_outputs.length() +foreach output : qapi_specific_outputs + qapi_nonmodule_outputs + if output.endswith('.h') + genh += qapi_files[i] + endif + specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: qapi_files[i]) + i = i + 1 +endforeach qapi_doc_texi = qapi_files[i] -- cgit v1.2.3-55-g7522 From 582ea95f5f9389677734637bdc021588c393bc3b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 15:15:32 +0400 Subject: meson: convert hw/xen Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- configure | 7 +++++-- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/xen/Makefile.objs | 7 ------- hw/xen/meson.build | 20 ++++++++++++++++++++ meson.build | 6 ++++++ 6 files changed, 32 insertions(+), 10 deletions(-) create mode 100644 hw/meson.build delete mode 100644 hw/xen/Makefile.objs create mode 100644 hw/xen/meson.build diff --git a/configure b/configure index 09e1ffc1a0..ddbe1f4569 100755 --- a/configure +++ b/configure @@ -2740,6 +2740,8 @@ if test "$xen" != "no" ; then fi QEMU_CFLAGS="$QEMU_CFLAGS $($pkg_config --cflags $xen_pc)" libs_softmmu="$($pkg_config --libs $xen_pc) $libs_softmmu" + xen_cflags="$($pkg_config --cflags $xen_pc)" + xen_libs="$($pkg_config --libs $xen_pc)" else xen_libs="-lxenstore -lxenctrl -lxenguest" @@ -3020,9 +3022,8 @@ EOF if test "$xen" = yes; then if test $xen_ctrl_version -ge 40701 ; then - libs_softmmu="$xen_stable_libs $libs_softmmu" + xen_libs="$xen_libs $xen_stable_libs " fi - libs_softmmu="$xen_libs $libs_softmmu" fi fi fi @@ -7313,6 +7314,8 @@ fi if test "$xen" = "yes" ; then echo "CONFIG_XEN_BACKEND=y" >> $config_host_mak echo "CONFIG_XEN_CTRL_INTERFACE_VERSION=$xen_ctrl_version" >> $config_host_mak + echo "XEN_CFLAGS=$xen_cflags" >> $config_host_mak + echo "XEN_LIBS=$xen_libs" >> $config_host_mak fi if test "$linux_aio" = "yes" ; then echo "CONFIG_LINUX_AIO=y" >> $config_host_mak diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 14b7ea4eb6..d204a906af 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -35,7 +35,6 @@ devices-dirs-y += usb/ devices-dirs-$(CONFIG_VFIO) += vfio/ devices-dirs-y += virtio/ devices-dirs-y += watchdog/ -devices-dirs-$(CONFIG_XEN) += xen/ devices-dirs-$(CONFIG_MEM_DEVICE) += mem/ devices-dirs-$(CONFIG_NUBUS) += nubus/ devices-dirs-y += semihosting/ diff --git a/hw/meson.build b/hw/meson.build new file mode 100644 index 0000000000..08112a5e4b --- /dev/null +++ b/hw/meson.build @@ -0,0 +1 @@ +subdir('xen') diff --git a/hw/xen/Makefile.objs b/hw/xen/Makefile.objs deleted file mode 100644 index 502b32d877..0000000000 --- a/hw/xen/Makefile.objs +++ /dev/null @@ -1,7 +0,0 @@ -# xen backend driver support -common-obj-y += xen-legacy-backend.o xen_devconfig.o xen_pvdev.o xen-bus.o xen-bus-helper.o xen-backend.o - -obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o -obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_graphics.o xen_pt_msi.o -obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt_load_rom.o -obj-$(call lnot,$(CONFIG_XEN_PCI_PASSTHROUGH)) += xen_pt_stub.o diff --git a/hw/xen/meson.build b/hw/xen/meson.build new file mode 100644 index 0000000000..076954b89c --- /dev/null +++ b/hw/xen/meson.build @@ -0,0 +1,20 @@ +softmmu_ss.add(when: ['CONFIG_XEN', xen], if_true: files( + 'xen-backend.c', + 'xen-bus-helper.c', + 'xen-bus.c', + 'xen-legacy-backend.c', + 'xen_devconfig.c', + 'xen_pvdev.c', +)) + +xen_specific_ss = ss.source_set() +xen_specific_ss.add(when: 'CONFIG_XEN_PCI_PASSTHROUGH', if_true: files( + 'xen-host-pci-device.c', + 'xen_pt.c', + 'xen_pt_config_init.c', + 'xen_pt_graphics.c', + 'xen_pt_load_rom.c', + 'xen_pt_msi.c', +), if_false: files('xen_pt_stub.c')) + +specific_ss.add_all(when: ['CONFIG_XEN', xen], if_true: xen_specific_ss) diff --git a/meson.build b/meson.build index edb635347c..aa715e5428 100644 --- a/meson.build +++ b/meson.build @@ -325,6 +325,11 @@ numa = not_found if 'CONFIG_NUMA' in config_host numa = declare_dependency(link_args: config_host['NUMA_LIBS'].split()) endif +xen = not_found +if 'CONFIG_XEN_BACKEND' in config_host + xen = declare_dependency(compile_args: config_host['XEN_CFLAGS'].split(), + link_args: config_host['XEN_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -678,6 +683,7 @@ subdir('migration') subdir('monitor') subdir('net') subdir('replay') +subdir('hw') # needed for fuzzing binaries subdir('tests/qtest/libqos') -- cgit v1.2.3-55-g7522 From c92a30977737f501e04c51210acceb0ec25291d3 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 15:24:58 +0400 Subject: meson: convert hw/core Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/core/Makefile.objs | 34 ---------------------------------- hw/core/meson.build | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/meson.build | 1 + tests/Makefile.include | 10 +--------- 5 files changed, 51 insertions(+), 44 deletions(-) delete mode 100644 hw/core/Makefile.objs create mode 100644 hw/core/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index d204a906af..bdf8bdf256 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -1,4 +1,3 @@ -devices-dirs-y = core/ ifeq ($(CONFIG_SOFTMMU), y) devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFIG_XEN))) += 9pfs/ devices-dirs-y += acpi/ diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs deleted file mode 100644 index d8fee8effe..0000000000 --- a/hw/core/Makefile.objs +++ /dev/null @@ -1,34 +0,0 @@ -# core qdev-related obj files, also used by *-user: -common-obj-y += qdev.o qdev-properties.o -common-obj-y += bus.o -common-obj-y += cpu.o -common-obj-y += resettable.o -common-obj-y += hotplug.o -common-obj-y += vmstate-if.o -# irq.o needed for qdev GPIO handling: -common-obj-y += irq.o -common-obj-y += clock.o qdev-clock.o - -common-obj-$(CONFIG_SOFTMMU) += reset.o -common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o -common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o -common-obj-$(CONFIG_SOFTMMU) += nmi.o -common-obj-$(CONFIG_SOFTMMU) += vm-change-state-handler.o -common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o -common-obj-$(CONFIG_SOFTMMU) += sysbus.o -common-obj-$(CONFIG_SOFTMMU) += machine.o -common-obj-$(CONFIG_SOFTMMU) += null-machine.o -common-obj-$(CONFIG_SOFTMMU) += loader.o -common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o -common-obj-$(CONFIG_SOFTMMU) += numa.o -common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o -obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o - -common-obj-$(CONFIG_XILINX_AXI) += stream.o -common-obj-$(CONFIG_PTIMER) += ptimer.o -common-obj-$(CONFIG_FITLOADER) += loader-fit.o -common-obj-$(CONFIG_REGISTER) += register.o -common-obj-$(CONFIG_OR_IRQ) += or-irq.o -common-obj-$(CONFIG_SPLIT_IRQ) += split-irq.o -common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o -common-obj-$(CONFIG_GENERIC_LOADER) += generic-loader.o diff --git a/hw/core/meson.build b/hw/core/meson.build new file mode 100644 index 0000000000..fc91f98075 --- /dev/null +++ b/hw/core/meson.build @@ -0,0 +1,49 @@ +# core qdev-related obj files, also used by *-user and unit tests +hwcore_files = files( + 'bus.c', + 'fw-path-provider.c', + 'hotplug.c', + 'qdev-properties.c', + 'qdev.c', + 'reset.c', + 'resettable.c', + 'vmstate-if.c', + # irq.c needed for qdev GPIO handling: + 'irq.c', + 'clock.c', + 'qdev-clock.c', +) + +libhwcore = static_library('hwcore', sources: hwcore_files + genh, + name_suffix: 'fa', + build_by_default: false) +hwcore = declare_dependency(link_whole: libhwcore) +common_ss.add(hwcore) + +common_ss.add(files('cpu.c')) +common_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) +common_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c')) +common_ss.add(when: 'CONFIG_OR_IRQ', if_true: files('or-irq.c')) +common_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('platform-bus.c')) +common_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c')) +common_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c')) +common_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c')) +common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c')) + +softmmu_ss.add(files( + 'loader.c', + 'machine-hmp-cmds.c', + 'machine.c', + 'nmi.c', + 'null-machine.c', + 'qdev-fw.c', + 'qdev-properties-system.c', + 'sysbus.c', + 'vm-change-state-handler.c', + 'clock-vmstate.c', +)) + +specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files( + 'machine-qmp-cmds.c', + 'numa.c', +)) diff --git a/hw/meson.build b/hw/meson.build index 08112a5e4b..fe7c466460 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1 +1,2 @@ +subdir('core') subdir('xen') diff --git a/tests/Makefile.include b/tests/Makefile.include index 8ac9c68f04..609a40c6e5 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -244,15 +244,7 @@ tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) tests/atomic64-bench$(EXESUF): tests/atomic64-bench.o $(test-util-obj-y) -tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ - hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ - hw/core/bus.o \ - hw/core/resettable.o \ - hw/core/irq.o \ - hw/core/fw-path-provider.o \ - hw/core/reset.o \ - hw/core/vmstate-if.o \ - hw/core/clock.o hw/core/qdev-clock.o \ +tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o hw/core/libhwcore.fa \ $(test-qapi-obj-y) tests/test-vmstate$(EXESUF): tests/test-vmstate.o migration/libmigration.fa \ $(test-io-obj-y) -- cgit v1.2.3-55-g7522 From 56d996c50ae5df3e8aa52d1abbb00eec9c00e786 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Jan 2020 12:49:17 +0100 Subject: meson: convert hw/semihosting Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/semihosting/Makefile.objs | 2 -- hw/semihosting/meson.build | 4 ++++ 4 files changed, 5 insertions(+), 3 deletions(-) delete mode 100644 hw/semihosting/Makefile.objs create mode 100644 hw/semihosting/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index bdf8bdf256..6a7ca0fcfe 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -36,7 +36,6 @@ devices-dirs-y += virtio/ devices-dirs-y += watchdog/ devices-dirs-$(CONFIG_MEM_DEVICE) += mem/ devices-dirs-$(CONFIG_NUBUS) += nubus/ -devices-dirs-y += semihosting/ devices-dirs-y += smbios/ endif diff --git a/hw/meson.build b/hw/meson.build index fe7c466460..66a2f6cddd 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,2 +1,3 @@ subdir('core') +subdir('semihosting') subdir('xen') diff --git a/hw/semihosting/Makefile.objs b/hw/semihosting/Makefile.objs deleted file mode 100644 index 4ad47c05c0..0000000000 --- a/hw/semihosting/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_SEMIHOSTING) += config.o -obj-$(CONFIG_SEMIHOSTING) += console.o diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build new file mode 100644 index 0000000000..f40ac574c4 --- /dev/null +++ b/hw/semihosting/meson.build @@ -0,0 +1,4 @@ +specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( + 'config.c', + 'console.c', +)) -- cgit v1.2.3-55-g7522 From b908c370f73192d95f13145148c4bafe39d1171c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Jan 2020 12:50:57 +0100 Subject: meson: convert hw/nubus Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/nubus/Makefile.objs | 4 ---- hw/nubus/meson.build | 7 +++++++ 4 files changed, 8 insertions(+), 5 deletions(-) delete mode 100644 hw/nubus/Makefile.objs create mode 100644 hw/nubus/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 6a7ca0fcfe..86bc201a55 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -35,7 +35,6 @@ devices-dirs-$(CONFIG_VFIO) += vfio/ devices-dirs-y += virtio/ devices-dirs-y += watchdog/ devices-dirs-$(CONFIG_MEM_DEVICE) += mem/ -devices-dirs-$(CONFIG_NUBUS) += nubus/ devices-dirs-y += smbios/ endif diff --git a/hw/meson.build b/hw/meson.build index 66a2f6cddd..03ef30212e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ subdir('core') +subdir('nubus') subdir('semihosting') subdir('xen') diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs deleted file mode 100644 index 135ba7878d..0000000000 --- a/hw/nubus/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -common-obj-y += nubus-device.o -common-obj-y += nubus-bus.o -common-obj-y += nubus-bridge.o -common-obj-$(CONFIG_Q800) += mac-nubus-bridge.o diff --git a/hw/nubus/meson.build b/hw/nubus/meson.build new file mode 100644 index 0000000000..9287c633aa --- /dev/null +++ b/hw/nubus/meson.build @@ -0,0 +1,7 @@ +nubus_ss = ss.source_set() +nubus_ss.add(files('nubus-device.c')) +nubus_ss.add(files('nubus-bus.c')) +nubus_ss.add(files('nubus-bridge.c')) +nubus_ss.add(when: 'CONFIG_Q800', if_true: files('mac-nubus-bridge.c')) + +softmmu_ss.add_all(when: 'CONFIG_NUBUS', if_true: nubus_ss) -- cgit v1.2.3-55-g7522 From d6c9b1f00365abe9bfde8cd67d49db3146f681a1 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 15:39:54 +0400 Subject: meson: convert hw/smbios Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/smbios/Makefile.objs | 10 ---------- hw/smbios/meson.build | 13 +++++++++++++ 4 files changed, 14 insertions(+), 11 deletions(-) delete mode 100644 hw/smbios/Makefile.objs create mode 100644 hw/smbios/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 86bc201a55..73c49ddd3b 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -35,7 +35,6 @@ devices-dirs-$(CONFIG_VFIO) += vfio/ devices-dirs-y += virtio/ devices-dirs-y += watchdog/ devices-dirs-$(CONFIG_MEM_DEVICE) += mem/ -devices-dirs-y += smbios/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 03ef30212e..dccc2d19a6 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') subdir('nubus') subdir('semihosting') +subdir('smbios') subdir('xen') diff --git a/hw/smbios/Makefile.objs b/hw/smbios/Makefile.objs deleted file mode 100644 index 23bb2bac07..0000000000 --- a/hw/smbios/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -ifeq ($(CONFIG_SMBIOS),y) -common-obj-y += smbios.o -common-obj-$(CONFIG_IPMI) += smbios_type_38.o -common-obj-$(call lnot,$(CONFIG_IPMI)) += smbios_type_38-stub.o -else -common-obj-y += smbios-stub.o -endif - -common-obj-$(CONFIG_ALL) += smbios-stub.o -common-obj-$(CONFIG_ALL) += smbios_type_38-stub.o diff --git a/hw/smbios/meson.build b/hw/smbios/meson.build new file mode 100644 index 0000000000..9e762c7108 --- /dev/null +++ b/hw/smbios/meson.build @@ -0,0 +1,13 @@ +smbios_ss = ss.source_set() +smbios_ss.add(files('smbios.c')) +smbios_ss.add(when: 'CONFIG_IPMI', + if_true: files('smbios_type_38.c'), + if_false: files('smbios_type_38-stub.c')) + +softmmu_ss.add_all(when: 'CONFIG_SMBIOS', if_true: smbios_ss) +softmmu_ss.add(when: 'CONFIG_SMBIOS', if_false: files('smbios-stub.c')) + +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files( + 'smbios-stub.c', + 'smbios_type_38-stub.c', +)) -- cgit v1.2.3-55-g7522 From 97813b940d56712d456d8a1260ecd5320b10761c Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 15:45:58 +0400 Subject: meson: convert hw/mem Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/mem/Kconfig | 1 + hw/mem/Makefile.objs | 3 --- hw/mem/meson.build | 6 ++++++ hw/meson.build | 1 + 5 files changed, 8 insertions(+), 4 deletions(-) delete mode 100644 hw/mem/Makefile.objs create mode 100644 hw/mem/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 73c49ddd3b..df72b25a64 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -34,7 +34,6 @@ devices-dirs-y += usb/ devices-dirs-$(CONFIG_VFIO) += vfio/ devices-dirs-y += virtio/ devices-dirs-y += watchdog/ -devices-dirs-$(CONFIG_MEM_DEVICE) += mem/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/mem/Kconfig b/hw/mem/Kconfig index c27844900d..a0ef2cf648 100644 --- a/hw/mem/Kconfig +++ b/hw/mem/Kconfig @@ -9,3 +9,4 @@ config NVDIMM bool default y depends on (PC || PSERIES || ARM_VIRT) + select MEM_DEVICE diff --git a/hw/mem/Makefile.objs b/hw/mem/Makefile.objs deleted file mode 100644 index 56345befd0..0000000000 --- a/hw/mem/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -common-obj-$(CONFIG_DIMM) += pc-dimm.o -common-obj-y += memory-device.o -common-obj-$(CONFIG_NVDIMM) += nvdimm.o diff --git a/hw/mem/meson.build b/hw/mem/meson.build new file mode 100644 index 0000000000..ba424622bb --- /dev/null +++ b/hw/mem/meson.build @@ -0,0 +1,6 @@ +mem_ss = ss.source_set() +mem_ss.add(files('memory-device.c')) +mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c')) +mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c')) + +softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss) diff --git a/hw/meson.build b/hw/meson.build index dccc2d19a6..542d675618 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') -- cgit v1.2.3-55-g7522 From e4fea7db5ea8b0b3482a9f1510f28be1e9715e42 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 15:50:11 +0400 Subject: meson: convert hw/watchdog Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/watchdog/Makefile.objs | 7 ------- hw/watchdog/meson.build | 7 +++++++ 4 files changed, 8 insertions(+), 8 deletions(-) delete mode 100644 hw/watchdog/Makefile.objs create mode 100644 hw/watchdog/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index df72b25a64..9ebd13d7cd 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -33,7 +33,6 @@ devices-dirs-$(CONFIG_TPM) += tpm/ devices-dirs-y += usb/ devices-dirs-$(CONFIG_VFIO) += vfio/ devices-dirs-y += virtio/ -devices-dirs-y += watchdog/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 542d675618..f2209d900c 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,4 +3,5 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('watchdog') subdir('xen') diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs deleted file mode 100644 index 631b711d86..0000000000 --- a/hw/watchdog/Makefile.objs +++ /dev/null @@ -1,7 +0,0 @@ -common-obj-y += watchdog.o -common-obj-$(CONFIG_CMSDK_APB_WATCHDOG) += cmsdk-apb-watchdog.o -common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o -common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o -common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o -common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o -common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build new file mode 100644 index 0000000000..9b8725e642 --- /dev/null +++ b/hw/watchdog/meson.build @@ -0,0 +1,7 @@ +softmmu_ss.add(files('watchdog.c')) +softmmu_ss.add(when: 'CONFIG_CMSDK_APB_WATCHDOG', if_true: files('cmsdk-apb-watchdog.c')) +softmmu_ss.add(when: 'CONFIG_WDT_IB6300ESB', if_true: files('wdt_i6300esb.c')) +softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wdt_ib700.c')) +softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c')) +softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c')) -- cgit v1.2.3-55-g7522 From be786d2f4aa3f9f53141ddabb50247176c004506 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 17:23:36 +0400 Subject: meson: convert hw/virtio Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/virtio/Makefile.objs | 48 ---------------------------------------------- hw/virtio/meson.build | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 52 insertions(+), 49 deletions(-) delete mode 100644 hw/virtio/Makefile.objs create mode 100644 hw/virtio/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 9ebd13d7cd..a1cfb99334 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -32,7 +32,6 @@ devices-dirs-y += timer/ devices-dirs-$(CONFIG_TPM) += tpm/ devices-dirs-y += usb/ devices-dirs-$(CONFIG_VFIO) += vfio/ -devices-dirs-y += virtio/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index f2209d900c..8338fc4408 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,5 +3,6 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('virtio') subdir('watchdog') subdir('xen') diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs deleted file mode 100644 index fc91719b4a..0000000000 --- a/hw/virtio/Makefile.objs +++ /dev/null @@ -1,48 +0,0 @@ -ifeq ($(CONFIG_VIRTIO),y) -common-obj-y += virtio-bus.o -obj-y += virtio.o - -obj-$(CONFIG_VHOST) += vhost.o vhost-backend.o -common-obj-$(call lnot,$(CONFIG_VHOST)) += vhost-stub.o -obj-$(CONFIG_VHOST_USER) += vhost-user.o -obj-$(CONFIG_VHOST_VDPA) += vhost-vdpa.o - -common-obj-$(CONFIG_VIRTIO_RNG) += virtio-rng.o -common-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o -common-obj-$(CONFIG_VIRTIO_MMIO) += virtio-mmio.o -obj-$(CONFIG_VIRTIO_BALLOON) += virtio-balloon.o -obj-$(CONFIG_VIRTIO_CRYPTO) += virtio-crypto.o -obj-$(CONFIG_VHOST_USER_FS) += vhost-user-fs.o -obj-$(call land,$(CONFIG_VIRTIO_CRYPTO),$(CONFIG_VIRTIO_PCI)) += virtio-crypto-pci.o -obj-$(CONFIG_VIRTIO_PMEM) += virtio-pmem.o -common-obj-$(call land,$(CONFIG_VIRTIO_PMEM),$(CONFIG_VIRTIO_PCI)) += virtio-pmem-pci.o -obj-$(call land,$(CONFIG_VHOST_USER_FS),$(CONFIG_VIRTIO_PCI)) += vhost-user-fs-pci.o -obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu.o -obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock-common.o vhost-vsock.o -obj-$(CONFIG_VHOST_USER_VSOCK) += vhost-vsock-common.o vhost-user-vsock.o -obj-$(CONFIG_VIRTIO_MEM) += virtio-mem.o -common-obj-$(call land,$(CONFIG_VIRTIO_MEM),$(CONFIG_VIRTIO_PCI)) += virtio-mem-pci.o - -ifeq ($(CONFIG_VIRTIO_PCI),y) -obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock-pci.o -obj-$(CONFIG_VHOST_USER_VSOCK) += vhost-user-vsock-pci.o -obj-$(CONFIG_VHOST_USER_BLK) += vhost-user-blk-pci.o -obj-$(CONFIG_VHOST_USER_INPUT) += vhost-user-input-pci.o -obj-$(CONFIG_VHOST_USER_SCSI) += vhost-user-scsi-pci.o -obj-$(CONFIG_VHOST_SCSI) += vhost-scsi-pci.o -obj-$(CONFIG_VIRTIO_INPUT_HOST) += virtio-input-host-pci.o -obj-$(CONFIG_VIRTIO_INPUT) += virtio-input-pci.o -obj-$(CONFIG_VIRTIO_RNG) += virtio-rng-pci.o -obj-$(CONFIG_VIRTIO_BALLOON) += virtio-balloon-pci.o -obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu-pci.o -obj-$(CONFIG_VIRTIO_9P) += virtio-9p-pci.o -obj-$(CONFIG_VIRTIO_SCSI) += virtio-scsi-pci.o -obj-$(CONFIG_VIRTIO_BLK) += virtio-blk-pci.o -obj-$(CONFIG_VIRTIO_NET) += virtio-net-pci.o -obj-$(CONFIG_VIRTIO_SERIAL) += virtio-serial-pci.o -endif -else -common-obj-y += vhost-stub.o -endif - -common-obj-$(CONFIG_ALL) += vhost-stub.o diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build new file mode 100644 index 0000000000..fbff9bc9d4 --- /dev/null +++ b/hw/virtio/meson.build @@ -0,0 +1,51 @@ +softmmu_virtio_ss = ss.source_set() +softmmu_virtio_ss.add(files('virtio-bus.c')) +softmmu_virtio_ss.add(when: 'CONFIG_VIRTIO_PCI', if_true: files('virtio-pci.c')) +softmmu_virtio_ss.add(when: 'CONFIG_VIRTIO_MMIO', if_true: files('virtio-mmio.c')) +softmmu_virtio_ss.add(when: 'CONFIG_VHOST', if_false: files('vhost-stub.c')) + +softmmu_ss.add_all(when: 'CONFIG_VIRTIO', if_true: softmmu_virtio_ss) +softmmu_ss.add(when: 'CONFIG_VIRTIO', if_false: files('vhost-stub.c')) + +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('vhost-stub.c')) + +virtio_ss = ss.source_set() +virtio_ss.add(files('virtio.c')) +virtio_ss.add(when: 'CONFIG_VHOST', if_true: files('vhost.c', 'vhost-backend.c')) +virtio_ss.add(when: 'CONFIG_VHOST_USER', if_true: files('vhost-user.c')) +virtio_ss.add(when: 'CONFIG_VHOST_VDPA', if_true: files('vhost-vdpa.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_BALLOON', if_true: files('virtio-balloon.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_CRYPTO', if_true: files('virtio-crypto.c')) +virtio_ss.add(when: ['CONFIG_VIRTIO_CRYPTO', 'CONFIG_VIRTIO_PCI'], if_true: files('virtio-crypto-pci.c')) +virtio_ss.add(when: 'CONFIG_VHOST_USER_FS', if_true: files('vhost-user-fs.c')) +virtio_ss.add(when: ['CONFIG_VHOST_USER_FS', 'CONFIG_VIRTIO_PCI'], if_true: files('vhost-user-fs-pci.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_PMEM', if_true: files('virtio-pmem.c')) +virtio_ss.add(when: 'CONFIG_VHOST_VSOCK', if_true: files('vhost-vsock.c', 'vhost-vsock-common.c')) +virtio_ss.add(when: 'CONFIG_VHOST_USER_VSOCK', if_true: files('vhost-user-vsock.c', 'vhost-vsock-common.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_RNG', if_true: files('virtio-rng.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_IOMMU', if_true: files('virtio-iommu.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_MEM', if_true: files('virtio-mem.c')) + +virtio_pci_ss = ss.source_set() +virtio_pci_ss.add(when: 'CONFIG_VHOST_VSOCK', if_true: files('vhost-vsock-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VHOST_USER_VSOCK', if_true: files('vhost-user-vsock-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VHOST_USER_INPUT', if_true: files('vhost-user-input-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VHOST_USER_SCSI', if_true: files('vhost-user-scsi-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VHOST_SCSI', if_true: files('vhost-scsi-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_INPUT_HOST', if_true: files('virtio-input-host-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_INPUT', if_true: files('virtio-input-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_RNG', if_true: files('virtio-rng-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_BALLOON', if_true: files('virtio-balloon-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_9P', if_true: files('virtio-9p-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_SCSI', if_true: files('virtio-scsi-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('virtio-net-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-serial-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_PMEM', if_true: files('virtio-pmem-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_IOMMU', if_true: files('virtio-iommu-pci.c')) +virtio_pci_ss.add(when: 'CONFIG_VIRTIO_MEM', if_true: files('virtio-mem-pci.c')) + +virtio_ss.add_all(when: 'CONFIG_VIRTIO_PCI', if_true: virtio_pci_ss) + +specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: virtio_ss) -- cgit v1.2.3-55-g7522 From 4f780d5629e965e2c479f36adeed11dc6902306c Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 15 Aug 2019 17:31:07 +0400 Subject: meson: convert hw/vfio Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/vfio/Makefile.objs | 8 -------- hw/vfio/meson.build | 18 ++++++++++++++++++ 4 files changed, 19 insertions(+), 9 deletions(-) delete mode 100644 hw/vfio/Makefile.objs create mode 100644 hw/vfio/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index a1cfb99334..f6e08f6660 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -31,7 +31,6 @@ devices-dirs-y += ssi/ devices-dirs-y += timer/ devices-dirs-$(CONFIG_TPM) += tpm/ devices-dirs-y += usb/ -devices-dirs-$(CONFIG_VFIO) += vfio/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 8338fc4408..4dafc8a08e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('vfio') subdir('virtio') subdir('watchdog') subdir('xen') diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs deleted file mode 100644 index 9bb1c09e84..0000000000 --- a/hw/vfio/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -obj-y += common.o spapr.o -obj-$(CONFIG_VFIO_PCI) += pci.o pci-quirks.o display.o -obj-$(CONFIG_VFIO_CCW) += ccw.o -obj-$(CONFIG_VFIO_PLATFORM) += platform.o -obj-$(CONFIG_VFIO_XGMAC) += calxeda-xgmac.o -obj-$(CONFIG_VFIO_AMD_XGBE) += amd-xgbe.o -obj-$(CONFIG_VFIO_AP) += ap.o -obj-$(CONFIG_VFIO_IGD) += igd.o diff --git a/hw/vfio/meson.build b/hw/vfio/meson.build new file mode 100644 index 0000000000..37efa74018 --- /dev/null +++ b/hw/vfio/meson.build @@ -0,0 +1,18 @@ +vfio_ss = ss.source_set() +vfio_ss.add(files( + 'common.c', + 'spapr.c', +)) +vfio_ss.add(when: 'CONFIG_VFIO_PCI', if_true: files( + 'display.c', + 'pci-quirks.c', + 'pci.c', +)) +vfio_ss.add(when: 'CONFIG_VFIO_CCW', if_true: files('ccw.c')) +vfio_ss.add(when: 'CONFIG_VFIO_PLATFORM', if_true: files('platform.c')) +vfio_ss.add(when: 'CONFIG_VFIO_XGMAC', if_true: files('calxeda-xgmac.c')) +vfio_ss.add(when: 'CONFIG_VFIO_AMD_XGBE', if_true: files('amd-xgbe.c')) +vfio_ss.add(when: 'CONFIG_VFIO_AP', if_true: files('ap.c')) +vfio_ss.add(when: 'CONFIG_VFIO_IGD', if_true: files('igd.c')) + +specific_ss.add_all(when: 'CONFIG_VFIO', if_true: vfio_ss) -- cgit v1.2.3-55-g7522 From 06677ce161c1ed0efc2851a592695cea0d24055a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Aug 2020 13:07:39 +0200 Subject: meson: convert hw/usb Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 1 + hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/usb/Makefile.objs | 71 ---------------------------------------------------- hw/usb/meson.build | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++ meson.build | 15 +++++++++++ 6 files changed, 86 insertions(+), 72 deletions(-) delete mode 100644 hw/usb/Makefile.objs create mode 100644 hw/usb/meson.build diff --git a/Makefile.target b/Makefile.target index 386378b9c8..3d5a2af4af 100644 --- a/Makefile.target +++ b/Makefile.target @@ -168,6 +168,7 @@ endif LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOMP_LIBS) LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) +LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) # Hardware support ifeq ($(TARGET_NAME), sparc64) diff --git a/hw/Makefile.objs b/hw/Makefile.objs index f6e08f6660..c2619bbb50 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -30,7 +30,6 @@ devices-dirs-y += sd/ devices-dirs-y += ssi/ devices-dirs-y += timer/ devices-dirs-$(CONFIG_TPM) += tpm/ -devices-dirs-y += usb/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 4dafc8a08e..89bd6adb70 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('usb') subdir('vfio') subdir('virtio') subdir('watchdog') diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs deleted file mode 100644 index e342ff59fa..0000000000 --- a/hw/usb/Makefile.objs +++ /dev/null @@ -1,71 +0,0 @@ -# usb subsystem core -common-obj-y += core.o combined-packet.o bus.o libhw.o -common-obj-$(CONFIG_USB) += desc.o desc-msos.o - -# usb host adapters -common-obj-$(CONFIG_USB_UHCI) += hcd-uhci.o -common-obj-$(CONFIG_USB_OHCI) += hcd-ohci.o -common-obj-$(CONFIG_USB_OHCI_PCI) += hcd-ohci-pci.o -common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o -common-obj-$(CONFIG_USB_EHCI_PCI) += hcd-ehci-pci.o -common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o -common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o -common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o -common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o -common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o - -common-obj-$(CONFIG_TUSB6010) += tusb6010.o -common-obj-$(CONFIG_IMX) += chipidea.o - -# emulated usb devices -common-obj-$(CONFIG_USB) += dev-hub.o -common-obj-$(CONFIG_USB) += dev-hid.o -common-obj-$(CONFIG_USB_TABLET_WACOM) += dev-wacom.o -common-obj-$(CONFIG_USB_STORAGE_BOT) += dev-storage.o -common-obj-$(CONFIG_USB_STORAGE_UAS) += dev-uas.o -common-obj-$(CONFIG_USB_AUDIO) += dev-audio.o -common-obj-$(CONFIG_USB_SERIAL) += dev-serial.o -common-obj-$(CONFIG_USB_NETWORK) += dev-network.o - -ifeq ($(CONFIG_USB_SMARTCARD),y) -common-obj-y += dev-smartcard-reader.o -ifeq ($(CONFIG_SMARTCARD),y) -common-obj-m += smartcard.mo -smartcard.mo-objs := ccid-card-passthru.o ccid-card-emulated.o -smartcard.mo-cflags := $(SMARTCARD_CFLAGS) -smartcard.mo-libs := $(SMARTCARD_LIBS) -endif -endif - -ifeq ($(CONFIG_POSIX),y) -common-obj-$(CONFIG_USB_STORAGE_MTP) += dev-mtp.o -endif - -# usb redirection -ifeq ($(CONFIG_USB),y) -ifeq ($(CONFIG_USB_REDIR),y) -common-obj-m += redirect.mo -redirect.mo-objs = redirect.o quirks.o -redirect.mo-cflags = $(USB_REDIR_CFLAGS) -redirect.mo-libs = $(USB_REDIR_LIBS) -endif -endif - -# usb pass-through -ifeq ($(CONFIG_USB_LIBUSB)$(CONFIG_USB),yy) -common-obj-y += host-libusb.o -else -common-obj-y += host-stub.o -endif -common-obj-$(CONFIG_ALL) += host-stub.o - -host-libusb.o-cflags := $(LIBUSB_CFLAGS) -host-libusb.o-libs := $(LIBUSB_LIBS) - -ifeq ($(CONFIG_USB_LIBUSB),y) -common-obj-$(CONFIG_XEN) += xen-usb.o -xen-usb.o-cflags := $(LIBUSB_CFLAGS) -xen-usb.o-libs := $(LIBUSB_LIBS) -endif - -common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o diff --git a/hw/usb/meson.build b/hw/usb/meson.build new file mode 100644 index 0000000000..3c44a1b069 --- /dev/null +++ b/hw/usb/meson.build @@ -0,0 +1,69 @@ +hw_usb_modules = {} + +# usb subsystem core +softmmu_ss.add(files( + 'bus.c', + 'combined-packet.c', + 'core.c', + 'libhw.c' +)) + +softmmu_ss.add(when: 'CONFIG_USB', if_true: files( + 'desc.c', + 'desc-msos.c', +)) + +# usb host adapters +softmmu_ss.add(when: 'CONFIG_USB_UHCI', if_true: files('hcd-uhci.c')) +softmmu_ss.add(when: 'CONFIG_USB_OHCI', if_true: files('hcd-ohci.c')) +softmmu_ss.add(when: 'CONFIG_USB_OHCI_PCI', if_true: files('hcd-ohci-pci.c')) +softmmu_ss.add(when: 'CONFIG_USB_EHCI', if_true: files('hcd-ehci.c')) +softmmu_ss.add(when: 'CONFIG_USB_EHCI_PCI', if_true: files('hcd-ehci-pci.c')) +softmmu_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci.c', 'hcd-ehci-sysbus.c')) +softmmu_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hcd-xhci.c')) +softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c')) +softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c')) +softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) + +softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) +softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c')) + +# emulated usb devices +softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c')) +softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hid.c')) +softmmu_ss.add(when: 'CONFIG_USB_TABLET_WACOM', if_true: files('dev-wacom.c')) +softmmu_ss.add(when: 'CONFIG_USB_STORAGE_BOT', if_true: files('dev-storage.c')) +softmmu_ss.add(when: 'CONFIG_USB_STORAGE_UAS', if_true: files('dev-uas.c')) +softmmu_ss.add(when: 'CONFIG_USB_AUDIO', if_true: files('dev-audio.c')) +softmmu_ss.add(when: 'CONFIG_USB_SERIAL', if_true: files('dev-serial.c')) +softmmu_ss.add(when: 'CONFIG_USB_NETWORK', if_true: files('dev-network.c')) +softmmu_ss.add(when: ['CONFIG_POSIX', 'CONFIG_USB_STORAGE_MTP'], if_true: files('dev-mtp.c')) + +# smartcard +softmmu_ss.add(when: 'CONFIG_USB_SMARTCARD', if_true: files('dev-smartcard-reader.c')) + +if config_host.has_key('CONFIG_SMARTCARD') + usbsmartcard_ss = ss.source_set() + usbsmartcard_ss.add(when: 'CONFIG_USB_SMARTCARD', + if_true: [cacard, files('ccid-card-emulated.c', 'ccid-card-passthru.c')]) + hw_usb_modules += {'smartcard': usbsmartcard_ss} +endif + +# usb redirect +if config_host.has_key('CONFIG_USB_REDIR') + usbredir_ss = ss.source_set() + usbredir_ss.add(when: 'CONFIG_USB', + if_true: [usbredir, files('redirect.c', 'quirks.c')]) + hw_usb_modules += {'redirect': usbredir_ss} +endif + +# usb pass-through +softmmu_ss.add(when: ['CONFIG_USB', 'CONFIG_USB_LIBUSB', libusb], + if_true: files('host-libusb.c'), + if_false: files('host-stub.c')) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('host-stub.c')) + +softmmu_ss.add(when: ['CONFIG_USB', 'CONFIG_XEN', libusb], if_true: files('xen-usb.c')) + +modules += { 'hw-usb': hw_usb_modules } diff --git a/meson.build b/meson.build index aa715e5428..ec958ba2af 100644 --- a/meson.build +++ b/meson.build @@ -330,6 +330,21 @@ if 'CONFIG_XEN_BACKEND' in config_host xen = declare_dependency(compile_args: config_host['XEN_CFLAGS'].split(), link_args: config_host['XEN_LIBS'].split()) endif +cacard = not_found +if 'CONFIG_SMARTCARD' in config_host + cacard = declare_dependency(compile_args: config_host['SMARTCARD_CFLAGS'].split(), + link_args: config_host['SMARTCARD_LIBS'].split()) +endif +usbredir = not_found +if 'CONFIG_USB_REDIR' in config_host + usbredir = declare_dependency(compile_args: config_host['USB_REDIR_CFLAGS'].split(), + link_args: config_host['USB_REDIR_LIBS'].split()) +endif +libusb = not_found +if 'CONFIG_USB_LIBUSB' in config_host + libusb = declare_dependency(compile_args: config_host['LIBUSB_CFLAGS'].split(), + link_args: config_host['LIBUSB_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') -- cgit v1.2.3-55-g7522 From 70c2cfedd3ad6a9ac433c194740c657075001ecc Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Aug 2020 14:03:59 +0200 Subject: meson: convert hw/tpm Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/tpm/Makefile.objs | 6 ------ hw/tpm/meson.build | 8 ++++++++ 4 files changed, 9 insertions(+), 7 deletions(-) delete mode 100644 hw/tpm/Makefile.objs create mode 100644 hw/tpm/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index c2619bbb50..f0e5728d13 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -29,7 +29,6 @@ devices-dirs-$(CONFIG_SCSI) += scsi/ devices-dirs-y += sd/ devices-dirs-y += ssi/ devices-dirs-y += timer/ -devices-dirs-$(CONFIG_TPM) += tpm/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 89bd6adb70..2ddf6bad33 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('tpm') subdir('usb') subdir('vfio') subdir('virtio') diff --git a/hw/tpm/Makefile.objs b/hw/tpm/Makefile.objs deleted file mode 100644 index 6fc05be67c..0000000000 --- a/hw/tpm/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -obj-$(call lor,$(CONFIG_TPM_TIS),$(CONFIG_TPM_CRB)) += tpm_ppi.o -common-obj-$(CONFIG_TPM_TIS_ISA) += tpm_tis_isa.o -common-obj-$(CONFIG_TPM_TIS_SYSBUS) += tpm_tis_sysbus.o -common-obj-$(CONFIG_TPM_TIS) += tpm_tis_common.o -common-obj-$(CONFIG_TPM_CRB) += tpm_crb.o -obj-$(CONFIG_TPM_SPAPR) += tpm_spapr.o diff --git a/hw/tpm/meson.build b/hw/tpm/meson.build new file mode 100644 index 0000000000..1c68d81d6a --- /dev/null +++ b/hw/tpm/meson.build @@ -0,0 +1,8 @@ +softmmu_ss.add(when: 'CONFIG_TPM_TIS', if_true: files('tpm_tis_common.c')) +softmmu_ss.add(when: 'CONFIG_TPM_TIS_ISA', if_true: files('tpm_tis_isa.c')) +softmmu_ss.add(when: 'CONFIG_TPM_TIS_SYSBUS', if_true: files('tpm_tis_sysbus.c')) +softmmu_ss.add(when: 'CONFIG_TPM_CRB', if_true: files('tpm_crb.c')) + +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TPM_TIS'], if_true: files('tpm_ppi.c')) +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TPM_CRB'], if_true: files('tpm_ppi.c')) +specific_ss.add(when: 'CONFIG_TPM_SPAPR', if_true: files('tpm_spapr.c')) -- cgit v1.2.3-55-g7522 From beeb0566d7e831347b5d7e412b3830a72557168b Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Jan 2020 12:35:13 +0100 Subject: meson: convert hw/timer Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/timer/Makefile.objs | 41 ----------------------------------------- hw/timer/meson.build | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 42 deletions(-) delete mode 100644 hw/timer/Makefile.objs create mode 100644 hw/timer/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index f0e5728d13..70ecaa8135 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -28,7 +28,6 @@ devices-dirs-y += rtc/ devices-dirs-$(CONFIG_SCSI) += scsi/ devices-dirs-y += sd/ devices-dirs-y += ssi/ -devices-dirs-y += timer/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 2ddf6bad33..50b26db852 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('mem') subdir('nubus') subdir('semihosting') subdir('smbios') +subdir('timer') subdir('tpm') subdir('usb') subdir('vfio') diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs deleted file mode 100644 index 1303b13e0d..0000000000 --- a/hw/timer/Makefile.objs +++ /dev/null @@ -1,41 +0,0 @@ -common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o -common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o -common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o -common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o -common-obj-$(CONFIG_CADENCE) += cadence_ttc.o -common-obj-$(CONFIG_HPET) += hpet.o -common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o -common-obj-$(CONFIG_PUV3) += puv3_ost.o -common-obj-$(CONFIG_XILINX) += xilinx_timer.o -common-obj-$(CONFIG_SLAVIO) += slavio_timer.o -common-obj-$(CONFIG_ETRAXFS) += etraxfs_timer.o -common-obj-$(CONFIG_GRLIB) += grlib_gptimer.o -common-obj-$(CONFIG_IMX) += imx_epit.o -common-obj-$(CONFIG_IMX) += imx_gpt.o -common-obj-$(CONFIG_LM32) += lm32_timer.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o -common-obj-$(CONFIG_NRF51_SOC) += nrf51_timer.o - -common-obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o -common-obj-$(CONFIG_OMAP) += omap_gptimer.o -common-obj-$(CONFIG_OMAP) += omap_synctimer.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o -common-obj-$(CONFIG_SH4) += sh_timer.o -common-obj-$(CONFIG_RENESAS_TMR) += renesas_tmr.o -common-obj-$(CONFIG_RENESAS_CMT) += renesas_cmt.o -common-obj-$(CONFIG_DIGIC) += digic-timer.o -common-obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o - -common-obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o - -common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o - -common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o -common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o -common-obj-$(CONFIG_MSF2) += mss-timer.o -common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o - -obj-$(CONFIG_AVR_TIMER16) += avr_timer16.o diff --git a/hw/timer/meson.build b/hw/timer/meson.build new file mode 100644 index 0000000000..9f0a267c83 --- /dev/null +++ b/hw/timer/meson.build @@ -0,0 +1,37 @@ +softmmu_ss.add(when: 'CONFIG_A9_GTIMER', if_true: files('a9gtimer.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_PIT', if_true: files('allwinner-a10-pit.c')) +softmmu_ss.add(when: 'CONFIG_ALTERA_TIMER', if_true: files('altera_timer.c')) +softmmu_ss.add(when: 'CONFIG_ARM_MPTIMER', if_true: files('arm_mptimer.c')) +softmmu_ss.add(when: 'CONFIG_ARM_TIMER', if_true: files('arm_timer.c')) +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_systick.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_timer.c')) +softmmu_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_ttc.c')) +softmmu_ss.add(when: 'CONFIG_CMSDK_APB_DUALTIMER', if_true: files('cmsdk-apb-dualtimer.c')) +softmmu_ss.add(when: 'CONFIG_CMSDK_APB_TIMER', if_true: files('cmsdk-apb-timer.c')) +softmmu_ss.add(when: 'CONFIG_RENESAS_TMR', if_true: files('renesas_tmr.c')) +softmmu_ss.add(when: 'CONFIG_RENESAS_CMT', if_true: files('renesas_cmt.c')) +softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic-timer.c')) +softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_timer.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_mct.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pwm.c')) +softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_gptimer.c')) +softmmu_ss.add(when: 'CONFIG_HPET', if_true: files('hpet.c')) +softmmu_ss.add(when: 'CONFIG_I8254', if_true: files('i8254_common.c', 'i8254.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_epit.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpt.c')) +softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_timer.c')) +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-sysctl.c')) +softmmu_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gictimer.c')) +softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-timer.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_timer.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gptimer.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_synctimer.c')) +softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_ost.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_timer.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_systmr.c')) +softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_timer.c')) +softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c')) +softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c')) +softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) + +specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c')) -- cgit v1.2.3-55-g7522 From ee80237e380df36562e545c63d9b058d7b39f8b9 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Jan 2020 12:35:13 +0100 Subject: meson: convert hw/rtc Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/rtc/Makefile.objs | 15 --------------- hw/rtc/meson.build | 16 ++++++++++++++++ 4 files changed, 17 insertions(+), 16 deletions(-) delete mode 100644 hw/rtc/Makefile.objs create mode 100644 hw/rtc/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 70ecaa8135..f60fd019ac 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -24,7 +24,6 @@ devices-dirs-y += nvram/ devices-dirs-y += pci/ devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ devices-dirs-y += pcmcia/ -devices-dirs-y += rtc/ devices-dirs-$(CONFIG_SCSI) += scsi/ devices-dirs-y += sd/ devices-dirs-y += ssi/ diff --git a/hw/meson.build b/hw/meson.build index 50b26db852..1fb1687e1e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('rtc') subdir('semihosting') subdir('smbios') subdir('timer') diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs deleted file mode 100644 index e4c1b8617c..0000000000 --- a/hw/rtc/Makefile.objs +++ /dev/null @@ -1,15 +0,0 @@ -common-obj-$(CONFIG_DS1338) += ds1338.o -common-obj-$(CONFIG_M41T80) += m41t80.o -common-obj-$(CONFIG_M48T59) += m48t59.o -ifeq ($(CONFIG_ISA_BUS),y) -common-obj-$(CONFIG_M48T59) += m48t59-isa.o -endif -common-obj-$(CONFIG_PL031) += pl031.o -common-obj-$(CONFIG_TWL92230) += twl92230.o -common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o -obj-$(CONFIG_MC146818RTC) += mc146818rtc.o -common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_rtc.o -common-obj-$(CONFIG_GOLDFISH_RTC) += goldfish_rtc.o -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-rtc.o diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build new file mode 100644 index 0000000000..7cecdee5dd --- /dev/null +++ b/hw/rtc/meson.build @@ -0,0 +1,16 @@ + +softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c')) +softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c')) +softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c')) +softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c')) +softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c')) +softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c')) + +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_rtc.c')) +softmmu_ss.add(when: 'CONFIG_SUN4V_RTC', if_true: files('sun4v-rtc.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_rtc.c')) +softmmu_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true: files('goldfish_rtc.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c')) + +specific_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c')) -- cgit v1.2.3-55-g7522 From b1bc817d686cd6b8c00965c626403222d60acf82 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:02:22 +0400 Subject: meson: convert hw/ssi Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/ssi/Makefile.objs | 10 ---------- hw/ssi/meson.build | 9 +++++++++ 4 files changed, 10 insertions(+), 11 deletions(-) delete mode 100644 hw/ssi/Makefile.objs create mode 100644 hw/ssi/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index f60fd019ac..e50eb04635 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -26,7 +26,6 @@ devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ devices-dirs-y += pcmcia/ devices-dirs-$(CONFIG_SCSI) += scsi/ devices-dirs-y += sd/ -devices-dirs-y += ssi/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 1fb1687e1e..75644266f2 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -4,6 +4,7 @@ subdir('nubus') subdir('rtc') subdir('semihosting') subdir('smbios') +subdir('ssi') subdir('timer') subdir('tpm') subdir('usb') diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs deleted file mode 100644 index 07a85f1967..0000000000 --- a/hw/ssi/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -common-obj-$(CONFIG_PL022) += pl022.o -common-obj-$(CONFIG_SSI) += ssi.o -common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o -common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o -common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o -common-obj-$(CONFIG_MSF2) += mss-spi.o - -common-obj-$(CONFIG_OMAP) += omap_spi.o -common-obj-$(CONFIG_IMX) += imx_spi.o diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build new file mode 100644 index 0000000000..f1f5c287d0 --- /dev/null +++ b/hw/ssi/meson.build @@ -0,0 +1,9 @@ +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) +softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) +softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) +softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) +softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi.c')) +softmmu_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c')) +softmmu_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: files('xilinx_spips.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c')) -- cgit v1.2.3-55-g7522 From 092795f8588e466e67d043b8780d8f8c2659e100 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:04:35 +0400 Subject: meson: convert hw/sd Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/sd/Makefile.objs | 12 ------------ hw/sd/meson.build | 12 ++++++++++++ 4 files changed, 13 insertions(+), 13 deletions(-) delete mode 100644 hw/sd/Makefile.objs create mode 100644 hw/sd/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index e50eb04635..6f9c0b7983 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -25,7 +25,6 @@ devices-dirs-y += pci/ devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ devices-dirs-y += pcmcia/ devices-dirs-$(CONFIG_SCSI) += scsi/ -devices-dirs-y += sd/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 75644266f2..a73f4aebde 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -2,6 +2,7 @@ subdir('core') subdir('mem') subdir('nubus') subdir('rtc') +subdir('sd') subdir('semihosting') subdir('smbios') subdir('ssi') diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs deleted file mode 100644 index 0d1df1721c..0000000000 --- a/hw/sd/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -common-obj-$(CONFIG_PL181) += pl181.o -common-obj-$(CONFIG_SSI_SD) += ssi-sd.o -common-obj-$(CONFIG_SD) += sd.o core.o sdmmc-internal.o -common-obj-$(CONFIG_SDHCI) += sdhci.o -common-obj-$(CONFIG_SDHCI_PCI) += sdhci-pci.o - -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sdhost.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-memcard.o -common-obj-$(CONFIG_OMAP) += omap_mmc.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o -common-obj-$(CONFIG_RASPI) += bcm2835_sdhost.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o diff --git a/hw/sd/meson.build b/hw/sd/meson.build new file mode 100644 index 0000000000..b43e59bd00 --- /dev/null +++ b/hw/sd/meson.build @@ -0,0 +1,12 @@ +softmmu_ss.add(when: 'CONFIG_PL181', if_true: files('pl181.c')) +softmmu_ss.add(when: 'CONFIG_SD', if_true: files('sd.c', 'core.c', 'sdmmc-internal.c')) +softmmu_ss.add(when: 'CONFIG_SDHCI', if_true: files('sdhci.c')) +softmmu_ss.add(when: 'CONFIG_SDHCI_PCI', if_true: files('sdhci-pci.c')) +softmmu_ss.add(when: 'CONFIG_SSI_SD', if_true: files('ssi-sd.c')) + +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-memcard.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_mmc.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c')) -- cgit v1.2.3-55-g7522 From 7633d844367fd341be1ee0a5af785ccdd4ad55d9 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:16:48 +0400 Subject: meson: convert hw/scsi Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/scsi/Makefile.objs | 15 --------------- hw/scsi/meson.build | 26 ++++++++++++++++++++++++++ 4 files changed, 27 insertions(+), 16 deletions(-) delete mode 100644 hw/scsi/Makefile.objs create mode 100644 hw/scsi/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 6f9c0b7983..b6461c2f5e 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -24,7 +24,6 @@ devices-dirs-y += nvram/ devices-dirs-y += pci/ devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ devices-dirs-y += pcmcia/ -devices-dirs-$(CONFIG_SCSI) += scsi/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index a73f4aebde..d4abb67715 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -2,6 +2,7 @@ subdir('core') subdir('mem') subdir('nubus') subdir('rtc') +subdir('scsi') subdir('sd') subdir('semihosting') subdir('smbios') diff --git a/hw/scsi/Makefile.objs b/hw/scsi/Makefile.objs deleted file mode 100644 index 54b36ed8b1..0000000000 --- a/hw/scsi/Makefile.objs +++ /dev/null @@ -1,15 +0,0 @@ -common-obj-y += scsi-disk.o emulation.o -common-obj-y += scsi-generic.o scsi-bus.o -common-obj-$(CONFIG_LSI_SCSI_PCI) += lsi53c895a.o -common-obj-$(CONFIG_MPTSAS_SCSI_PCI) += mptsas.o mptconfig.o mptendian.o -common-obj-$(CONFIG_MEGASAS_SCSI_PCI) += megasas.o -common-obj-$(CONFIG_VMW_PVSCSI_SCSI_PCI) += vmw_pvscsi.o -common-obj-$(CONFIG_ESP) += esp.o -common-obj-$(CONFIG_ESP_PCI) += esp-pci.o -obj-$(CONFIG_SPAPR_VSCSI) += spapr_vscsi.o - -ifeq ($(CONFIG_VIRTIO_SCSI),y) -obj-y += virtio-scsi.o virtio-scsi-dataplane.o -obj-$(CONFIG_VHOST_SCSI) += vhost-scsi-common.o vhost-scsi.o -obj-$(CONFIG_VHOST_USER_SCSI) += vhost-scsi-common.o vhost-user-scsi.o -endif diff --git a/hw/scsi/meson.build b/hw/scsi/meson.build new file mode 100644 index 0000000000..923a34f344 --- /dev/null +++ b/hw/scsi/meson.build @@ -0,0 +1,26 @@ +scsi_ss = ss.source_set() +scsi_ss.add(files( + 'emulation.c', + 'scsi-bus.c', + 'scsi-disk.c', + 'scsi-generic.c', +)) +scsi_ss.add(when: 'CONFIG_ESP', if_true: files('esp.c')) +scsi_ss.add(when: 'CONFIG_ESP_PCI', if_true: files('esp-pci.c')) +scsi_ss.add(when: 'CONFIG_LSI_SCSI_PCI', if_true: files('lsi53c895a.c')) +scsi_ss.add(when: 'CONFIG_MEGASAS_SCSI_PCI', if_true: files('megasas.c')) +scsi_ss.add(when: 'CONFIG_MPTSAS_SCSI_PCI', if_true: files('mptsas.c', 'mptconfig.c', 'mptendian.c')) +scsi_ss.add(when: 'CONFIG_VMW_PVSCSI_SCSI_PCI', if_true: files('vmw_pvscsi.c')) +softmmu_ss.add_all(when: 'CONFIG_SCSI', if_true: scsi_ss) + +specific_scsi_ss = ss.source_set() + +virtio_scsi_ss = ss.source_set() +virtio_scsi_ss.add(files('virtio-scsi.c', 'virtio-scsi-dataplane.c')) +virtio_scsi_ss.add(when: 'CONFIG_VHOST_SCSI', if_true: files('vhost-scsi-common.c', 'vhost-scsi.c')) +virtio_scsi_ss.add(when: 'CONFIG_VHOST_USER_SCSI', if_true: files('vhost-scsi-common.c', 'vhost-user-scsi.c')) +specific_scsi_ss.add_all(when: 'CONFIG_VIRTIO_SCSI', if_true: virtio_scsi_ss) + +specific_scsi_ss.add(when: 'CONFIG_SPAPR_VSCSI', if_true: files('spapr_vscsi.c')) + +specific_ss.add_all(when: 'CONFIG_SCSI', if_true: specific_scsi_ss) -- cgit v1.2.3-55-g7522 From 00953fa550f4868c39a340001c9839cc9bb534f0 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:19:34 +0400 Subject: meson: convert hw/pcmcia Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/pcmcia/Makefile.objs | 2 -- hw/pcmcia/meson.build | 2 ++ 4 files changed, 3 insertions(+), 3 deletions(-) delete mode 100644 hw/pcmcia/Makefile.objs create mode 100644 hw/pcmcia/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index b6461c2f5e..f28da5869d 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -23,7 +23,6 @@ devices-dirs-y += rdma/ devices-dirs-y += nvram/ devices-dirs-y += pci/ devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ -devices-dirs-y += pcmcia/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index d4abb67715..ed25644237 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('pcmcia') subdir('rtc') subdir('scsi') subdir('sd') diff --git a/hw/pcmcia/Makefile.objs b/hw/pcmcia/Makefile.objs deleted file mode 100644 index 02cd986a2c..0000000000 --- a/hw/pcmcia/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -common-obj-y += pcmcia.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx.o diff --git a/hw/pcmcia/meson.build b/hw/pcmcia/meson.build new file mode 100644 index 0000000000..ab50bd325d --- /dev/null +++ b/hw/pcmcia/meson.build @@ -0,0 +1,2 @@ +softmmu_ss.add(files('pcmcia.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c')) -- cgit v1.2.3-55-g7522 From 9235a82d0ff80e04218134b6a2c48e3e31c261de Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:23:03 +0400 Subject: meson: convert hw/pci-host Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 2 +- hw/meson.build | 1 + hw/pci-host/Makefile.objs | 24 ------------------------ hw/pci-host/meson.build | 31 +++++++++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 25 deletions(-) delete mode 100644 hw/pci-host/Makefile.objs create mode 100644 hw/pci-host/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index f28da5869d..0038cf89d9 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -22,7 +22,7 @@ devices-dirs-y += net/ devices-dirs-y += rdma/ devices-dirs-y += nvram/ devices-dirs-y += pci/ -devices-dirs-$(CONFIG_PCI) += pci-bridge/ pci-host/ +devices-dirs-$(CONFIG_PCI) += pci-bridge/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index ed25644237..ca36e486e7 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('pci-host') subdir('pcmcia') subdir('rtc') subdir('scsi') diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs deleted file mode 100644 index e422e0aca0..0000000000 --- a/hw/pci-host/Makefile.objs +++ /dev/null @@ -1,24 +0,0 @@ -common-obj-$(CONFIG_PAM) += pam.o - -# PPC devices -common-obj-$(CONFIG_PREP_PCI) += prep.o -common-obj-$(CONFIG_GRACKLE_PCI) += grackle.o -# NewWorld PowerMac -common-obj-$(CONFIG_UNIN_PCI) += uninorth.o -# PowerPC E500 boards -common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o - -# ARM devices -common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o - -common-obj-$(CONFIG_PCI_SABRE) += sabre.o -common-obj-$(CONFIG_PCI_BONITO) += bonito.o -common-obj-$(CONFIG_PCI_I440FX) += i440fx.o -common-obj-$(CONFIG_XEN_IGD_PASSTHROUGH) += xen_igd_pt.o -common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o -common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o -common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o - -common-obj-$(CONFIG_PCI_EXPRESS_DESIGNWARE) += designware.o -obj-$(CONFIG_POWERNV) += pnv_phb4.o pnv_phb4_pec.o -obj-$(CONFIG_POWERNV) += pnv_phb3.o pnv_phb3_msi.o pnv_phb3_pbcq.o diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build new file mode 100644 index 0000000000..cd52f6ff1c --- /dev/null +++ b/hw/pci-host/meson.build @@ -0,0 +1,31 @@ +pci_ss = ss.source_set() +pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c')) +pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c')) +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c')) +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c')) +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_Q35', if_true: files('q35.c')) +pci_ss.add(when: 'CONFIG_PCI_EXPRESS_XILINX', if_true: files('xilinx-pcie.c')) +pci_ss.add(when: 'CONFIG_PCI_I440FX', if_true: files('i440fx.c')) +pci_ss.add(when: 'CONFIG_PCI_SABRE', if_true: files('sabre.c')) +pci_ss.add(when: 'CONFIG_XEN_IGD_PASSTHROUGH', if_true: files('xen_igd_pt.c')) + +# PPC devices +pci_ss.add(when: 'CONFIG_PREP_PCI', if_true: files('prep.c')) +pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c')) +# NewWorld PowerMac +pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c')) +# PowerPC E500 boards +pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c')) + +# ARM devices +pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c')) + +softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) + +specific_ss.add(when: 'CONFIG_POWERNV', if_true: files( + 'pnv_phb3.c', + 'pnv_phb3_msi.c', + 'pnv_phb3_pbcq.c', + 'pnv_phb4.c', + 'pnv_phb4_pec.c' +)) -- cgit v1.2.3-55-g7522 From ea7e9b5730dbcce6fa1bc150342caf43920f2db9 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:26:17 +0400 Subject: meson: convert hw/pci-bridge Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/pci-bridge/Makefile.objs | 10 ---------- hw/pci-bridge/meson.build | 14 ++++++++++++++ 4 files changed, 15 insertions(+), 11 deletions(-) delete mode 100644 hw/pci-bridge/Makefile.objs create mode 100644 hw/pci-bridge/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 0038cf89d9..3513040d4a 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -22,7 +22,6 @@ devices-dirs-y += net/ devices-dirs-y += rdma/ devices-dirs-y += nvram/ devices-dirs-y += pci/ -devices-dirs-$(CONFIG_PCI) += pci-bridge/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index ca36e486e7..a7301f21e8 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('pci-bridge') subdir('pci-host') subdir('pcmcia') subdir('rtc') diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs deleted file mode 100644 index 47065f87d9..0000000000 --- a/hw/pci-bridge/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -common-obj-y += pci_bridge_dev.o -common-obj-$(CONFIG_PCIE_PORT) += pcie_root_port.o gen_pcie_root_port.o pcie_pci_bridge.o -common-obj-$(CONFIG_PXB) += pci_expander_bridge.o -common-obj-$(CONFIG_XIO3130) += xio3130_upstream.o xio3130_downstream.o -common-obj-$(CONFIG_IOH3420) += ioh3420.o -common-obj-$(CONFIG_I82801B11) += i82801b11.o -# NewWorld PowerMac -common-obj-$(CONFIG_DEC_PCI) += dec.o -# Sun4u -common-obj-$(CONFIG_SIMBA) += simba.o diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build new file mode 100644 index 0000000000..daab8acf2a --- /dev/null +++ b/hw/pci-bridge/meson.build @@ -0,0 +1,14 @@ +pci_ss = ss.source_set() +pci_ss.add(files('pci_bridge_dev.c')) +pci_ss.add(when: 'CONFIG_I82801B11', if_true: files('i82801b11.c')) +pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c')) +pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pcie_root_port.c', 'pcie_pci_bridge.c')) +pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c')) +pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c')) + +# NewWorld PowerMac +pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c')) +# Sun4u +pci_ss.add(when: 'CONFIG_SIMBA', if_true: files('simba.c')) + +softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) -- cgit v1.2.3-55-g7522 From 4a328444333dd917ae17241f433085a64ee17d8e Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:32:24 +0400 Subject: meson: convert hw/pci Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/pci/Makefile.objs | 14 -------------- hw/pci/meson.build | 19 +++++++++++++++++++ 4 files changed, 20 insertions(+), 15 deletions(-) delete mode 100644 hw/pci/Makefile.objs create mode 100644 hw/pci/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 3513040d4a..20832841d2 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -21,7 +21,6 @@ devices-dirs-y += misc/ devices-dirs-y += net/ devices-dirs-y += rdma/ devices-dirs-y += nvram/ -devices-dirs-y += pci/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index a7301f21e8..53c347c395 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('pci') subdir('pci-bridge') subdir('pci-host') subdir('pcmcia') diff --git a/hw/pci/Makefile.objs b/hw/pci/Makefile.objs deleted file mode 100644 index c78f2fb24b..0000000000 --- a/hw/pci/Makefile.objs +++ /dev/null @@ -1,14 +0,0 @@ -common-obj-$(CONFIG_PCI) += pci.o pci_bridge.o -common-obj-$(CONFIG_PCI) += msix.o msi.o -common-obj-$(CONFIG_PCI) += shpc.o -common-obj-$(CONFIG_PCI) += slotid_cap.o -common-obj-$(CONFIG_PCI) += pci_host.o - -# The functions in these modules can be used by devices too. Since we -# allow plugging PCIe devices into PCI buses, include them even if -# CONFIG_PCI_EXPRESS=n. -common-obj-$(CONFIG_PCI) += pcie.o pcie_aer.o -common-obj-$(CONFIG_PCI_EXPRESS) += pcie_port.o pcie_host.o - -common-obj-$(call lnot,$(CONFIG_PCI)) += pci-stub.o -common-obj-$(CONFIG_ALL) += pci-stub.o diff --git a/hw/pci/meson.build b/hw/pci/meson.build new file mode 100644 index 0000000000..5c4bbac817 --- /dev/null +++ b/hw/pci/meson.build @@ -0,0 +1,19 @@ +pci_ss = ss.source_set() +pci_ss.add(files( + 'msi.c', + 'msix.c', + 'pci.c', + 'pci_bridge.c', + 'pci_host.c', + 'shpc.c', + 'slotid_cap.c' +)) +# The functions in these modules can be used by devices too. Since we +# allow plugging PCIe devices into PCI buses, include them even if +# CONFIG_PCI_EXPRESS=n. +pci_ss.add(files('pcie.c', 'pcie_aer.c')) +softmmu_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'pcie_host.c')) +softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) + +softmmu_ss.add(when: 'CONFIG_PCI', if_false: files('pci-stub.c')) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('pci-stub.c')) -- cgit v1.2.3-55-g7522 From 9f6ede2f1a936b61b24d0b1f387e8e785108eb41 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:35:29 +0400 Subject: meson: convert hw/nvram Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/nvram/Makefile.objs | 8 -------- hw/nvram/meson.build | 9 +++++++++ 4 files changed, 10 insertions(+), 9 deletions(-) delete mode 100644 hw/nvram/Makefile.objs create mode 100644 hw/nvram/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 20832841d2..78860ae9c7 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -20,7 +20,6 @@ devices-dirs-y += isa/ devices-dirs-y += misc/ devices-dirs-y += net/ devices-dirs-y += rdma/ -devices-dirs-y += nvram/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 53c347c395..0bdd6a2613 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,6 +1,7 @@ subdir('core') subdir('mem') subdir('nubus') +subdir('nvram') subdir('pci') subdir('pci-bridge') subdir('pci-host') diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs deleted file mode 100644 index f3ad921382..0000000000 --- a/hw/nvram/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -common-obj-$(CONFIG_DS1225Y) += ds1225y.o -common-obj-$(CONFIG_NMC93XX_EEPROM) += eeprom93xx.o -common-obj-$(CONFIG_AT24C) += eeprom_at24c.o -common-obj-y += fw_cfg.o -common-obj-$(CONFIG_CHRP_NVRAM) += chrp_nvram.o -common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o -common-obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o -obj-$(CONFIG_PSERIES) += spapr_nvram.o diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build new file mode 100644 index 0000000000..ba214558ac --- /dev/null +++ b/hw/nvram/meson.build @@ -0,0 +1,9 @@ +softmmu_ss.add(files('fw_cfg.c')) +softmmu_ss.add(when: 'CONFIG_CHRP_NVRAM', if_true: files('chrp_nvram.c')) +softmmu_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c')) +softmmu_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c')) +softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c')) +softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c')) + +specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) -- cgit v1.2.3-55-g7522 From 19233c978a50a13b05cc9a33b9574aa83a28193f Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:47:43 +0400 Subject: meson: convert hw/rdma Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/rdma/Makefile.objs | 3 --- hw/rdma/meson.build | 10 ++++++++++ 4 files changed, 11 insertions(+), 4 deletions(-) delete mode 100644 hw/rdma/Makefile.objs create mode 100644 hw/rdma/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 78860ae9c7..748a718b0f 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -19,7 +19,6 @@ devices-dirs-$(CONFIG_IPMI) += ipmi/ devices-dirs-y += isa/ devices-dirs-y += misc/ devices-dirs-y += net/ -devices-dirs-y += rdma/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 0bdd6a2613..f704e51361 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -6,6 +6,7 @@ subdir('pci') subdir('pci-bridge') subdir('pci-host') subdir('pcmcia') +subdir('rdma') subdir('rtc') subdir('scsi') subdir('sd') diff --git a/hw/rdma/Makefile.objs b/hw/rdma/Makefile.objs deleted file mode 100644 index 819bb12a35..0000000000 --- a/hw/rdma/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-$(CONFIG_VMW_PVRDMA) += rdma_utils.o rdma_backend.o rdma_rm.o rdma.o -obj-$(CONFIG_VMW_PVRDMA) += vmw/pvrdma_dev_ring.o vmw/pvrdma_cmd.o \ - vmw/pvrdma_qp_ops.o vmw/pvrdma_main.o diff --git a/hw/rdma/meson.build b/hw/rdma/meson.build new file mode 100644 index 0000000000..7325f40c32 --- /dev/null +++ b/hw/rdma/meson.build @@ -0,0 +1,10 @@ +specific_ss.add(when: 'CONFIG_VMW_PVRDMA', if_true: files( + 'rdma.c', + 'rdma_backend.c', + 'rdma_rm.c', + 'rdma_utils.c', + 'vmw/pvrdma_cmd.c', + 'vmw/pvrdma_dev_ring.c', + 'vmw/pvrdma_main.c', + 'vmw/pvrdma_qp_ops.c', +)) -- cgit v1.2.3-55-g7522 From b1419fa665584e493257475af2618443bd834e47 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 17:48:00 +0400 Subject: meson: convert hw/net Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/net/Makefile.objs | 59 ------------------------------------------ hw/net/can/Makefile.objs | 4 --- hw/net/can/meson.build | 4 +++ hw/net/meson.build | 67 ++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 72 insertions(+), 64 deletions(-) delete mode 100644 hw/net/Makefile.objs delete mode 100644 hw/net/can/Makefile.objs create mode 100644 hw/net/can/meson.build create mode 100644 hw/net/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 748a718b0f..d0d7816118 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -18,7 +18,6 @@ devices-dirs-$(CONFIG_IPACK) += ipack/ devices-dirs-$(CONFIG_IPMI) += ipmi/ devices-dirs-y += isa/ devices-dirs-y += misc/ -devices-dirs-y += net/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index f704e51361..1f7b2c4fb9 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,5 +1,6 @@ subdir('core') subdir('mem') +subdir('net') subdir('nubus') subdir('nvram') subdir('pci') diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs deleted file mode 100644 index 7ccbf72ea7..0000000000 --- a/hw/net/Makefile.objs +++ /dev/null @@ -1,59 +0,0 @@ -common-obj-$(CONFIG_DP8393X) += dp8393x.o -common-obj-$(CONFIG_XEN) += xen_nic.o -common-obj-$(CONFIG_NE2000_COMMON) += ne2000.o - -# PCI network cards -common-obj-$(CONFIG_NE2000_PCI) += ne2000-pci.o -common-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o -common-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o -common-obj-$(CONFIG_PCNET_COMMON) += pcnet.o -common-obj-$(CONFIG_E1000_PCI) += e1000.o e1000x_common.o -common-obj-$(CONFIG_E1000E_PCI_EXPRESS) += net_tx_pkt.o net_rx_pkt.o -common-obj-$(CONFIG_E1000E_PCI_EXPRESS) += e1000e.o e1000e_core.o e1000x_common.o -common-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o -common-obj-$(CONFIG_VMXNET3_PCI) += net_tx_pkt.o net_rx_pkt.o -common-obj-$(CONFIG_VMXNET3_PCI) += vmxnet3.o -common-obj-$(CONFIG_TULIP) += tulip.o - -common-obj-$(CONFIG_SMC91C111) += smc91c111.o -common-obj-$(CONFIG_LAN9118) += lan9118.o -common-obj-$(CONFIG_NE2000_ISA) += ne2000-isa.o -common-obj-$(CONFIG_OPENCORES_ETH) += opencores_eth.o -common-obj-$(CONFIG_XGMAC) += xgmac.o -common-obj-$(CONFIG_MIPSNET) += mipsnet.o -common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o -common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o -common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) += allwinner-sun8i-emac.o -common-obj-$(CONFIG_IMX_FEC) += imx_fec.o - -common-obj-$(CONFIG_CADENCE) += cadence_gem.o -common-obj-$(CONFIG_STELLARIS_ENET) += stellaris_enet.o -common-obj-$(CONFIG_LANCE) += lance.o -common-obj-$(CONFIG_LASI_82596) += lasi_i82596.o -common-obj-$(CONFIG_I82596_COMMON) += i82596.o -common-obj-$(CONFIG_SUNHME) += sunhme.o -common-obj-$(CONFIG_FTGMAC100) += ftgmac100.o -common-obj-$(CONFIG_SUNGEM) += sungem.o - -common-obj-$(CONFIG_ETRAXFS) += etraxfs_eth.o -common-obj-$(CONFIG_COLDFIRE) += mcf_fec.o -obj-$(CONFIG_MILKYMIST) += milkymist-minimac2.o -obj-$(CONFIG_PSERIES) += spapr_llan.o -obj-$(CONFIG_XILINX_ETHLITE) += xilinx_ethlite.o - -common-obj-$(CONFIG_VIRTIO_NET) += net_rx_pkt.o -obj-$(CONFIG_VIRTIO_NET) += virtio-net.o -common-obj-$(call land,$(CONFIG_VIRTIO_NET),$(CONFIG_VHOST_NET)) += vhost_net.o -common-obj-$(call lnot,$(call land,$(CONFIG_VIRTIO_NET),$(CONFIG_VHOST_NET))) += vhost_net-stub.o -common-obj-$(CONFIG_ALL) += vhost_net-stub.o - -common-obj-$(CONFIG_ETSEC) += fsl_etsec/etsec.o fsl_etsec/registers.o \ - fsl_etsec/rings.o fsl_etsec/miim.o - -common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \ - rocker/rocker_desc.o rocker/rocker_world.o \ - rocker/rocker_of_dpa.o -obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o - -common-obj-$(CONFIG_CAN_BUS) += can/ -common-obj-$(CONFIG_MSF2) += msf2-emac.o diff --git a/hw/net/can/Makefile.objs b/hw/net/can/Makefile.objs deleted file mode 100644 index 9f0c4ee332..0000000000 --- a/hw/net/can/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -common-obj-$(CONFIG_CAN_SJA1000) += can_sja1000.o -common-obj-$(CONFIG_CAN_PCI) += can_kvaser_pci.o -common-obj-$(CONFIG_CAN_PCI) += can_pcm3680_pci.o -common-obj-$(CONFIG_CAN_PCI) += can_mioe3680_pci.o diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build new file mode 100644 index 0000000000..c9cfeb7954 --- /dev/null +++ b/hw/net/can/meson.build @@ -0,0 +1,4 @@ +softmmu_ss.add(when: 'CONFIG_CAN_SJA1000', if_true: files('can_sja1000.c')) +softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_kvaser_pci.c')) +softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c')) +softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c')) diff --git a/hw/net/meson.build b/hw/net/meson.build new file mode 100644 index 0000000000..4a7051b54a --- /dev/null +++ b/hw/net/meson.build @@ -0,0 +1,67 @@ +softmmu_ss.add(when: 'CONFIG_DP8393X', if_true: files('dp8393x.c')) +softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_nic.c')) +softmmu_ss.add(when: 'CONFIG_NE2000_COMMON', if_true: files('ne2000.c')) + +# PCI network cards +softmmu_ss.add(when: 'CONFIG_NE2000_PCI', if_true: files('ne2000-pci.c')) +softmmu_ss.add(when: 'CONFIG_EEPRO100_PCI', if_true: files('eepro100.c')) +softmmu_ss.add(when: 'CONFIG_PCNET_PCI', if_true: files('pcnet-pci.c')) +softmmu_ss.add(when: 'CONFIG_PCNET_COMMON', if_true: files('pcnet.c')) +softmmu_ss.add(when: 'CONFIG_E1000_PCI', if_true: files('e1000.c', 'e1000x_common.c')) +softmmu_ss.add(when: 'CONFIG_E1000E_PCI_EXPRESS', if_true: files('net_tx_pkt.c', 'net_rx_pkt.c')) +softmmu_ss.add(when: 'CONFIG_E1000E_PCI_EXPRESS', if_true: files('e1000e.c', 'e1000e_core.c', 'e1000x_common.c')) +softmmu_ss.add(when: 'CONFIG_RTL8139_PCI', if_true: files('rtl8139.c')) +softmmu_ss.add(when: 'CONFIG_TULIP', if_true: files('tulip.c')) +softmmu_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('net_tx_pkt.c', 'net_rx_pkt.c')) +softmmu_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) + +softmmu_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) +softmmu_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) +softmmu_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) +softmmu_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) +softmmu_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) +softmmu_ss.add(when: 'CONFIG_MIPSNET', if_true: files('mipsnet.c')) +softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('xilinx_axienet.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_EMAC', if_true: files('allwinner_emac.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_SUN8I_EMAC', if_true: files('allwinner-sun8i-emac.c')) +softmmu_ss.add(when: 'CONFIG_IMX_FEC', if_true: files('imx_fec.c')) +softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-emac.c')) + +softmmu_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_gem.c')) +softmmu_ss.add(when: 'CONFIG_STELLARIS_ENET', if_true: files('stellaris_enet.c')) +softmmu_ss.add(when: 'CONFIG_LANCE', if_true: files('lance.c')) +softmmu_ss.add(when: 'CONFIG_LASI_I82596', if_true: files('lasi_i82596.c')) +softmmu_ss.add(when: 'CONFIG_I82596_COMMON', if_true: files('i82596.c')) +softmmu_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) +softmmu_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) +softmmu_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) + +softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) +softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) +specific_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-minimac2.c')) +specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_llan.c')) +specific_ss.add(when: 'CONFIG_XILINX_ETHLITE', if_true: files('xilinx_ethlite.c')) + +softmmu_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('net_rx_pkt.c')) +specific_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('virtio-net.c')) + +softmmu_ss.add(when: ['CONFIG_VIRTIO_NET', 'CONFIG_VHOST_NET'], if_true: files('vhost_net.c'), if_false: files('vhost_net-stub.c')) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('vhost_net-stub.c')) + +softmmu_ss.add(when: 'CONFIG_ETSEC', if_true: files( + 'fsl_etsec/etsec.c', + 'fsl_etsec/miim.c', + 'fsl_etsec/registers.c', + 'fsl_etsec/rings.c', +)) + +softmmu_ss.add(when: 'CONFIG_ROCKER', if_true: files( + 'rocker/rocker.c', + 'rocker/rocker_desc.c', + 'rocker/rocker_fp.c', + 'rocker/rocker_of_dpa.c', + 'rocker/rocker_world.c', +), if_false: files('rocker/qmp-norocker.c')) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('rocker/qmp-norocker.c')) + +subdir('can') -- cgit v1.2.3-55-g7522 From 721cdcae73071d12415b64971ece3f87b2971bc2 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:15:00 +0400 Subject: meson: convert hw/misc Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/meson.build | 1 + hw/misc/Makefile.objs | 95 ------------------------------------------- hw/misc/macio/Makefile.objs | 5 --- hw/misc/macio/meson.build | 8 ++++ hw/misc/meson.build | 99 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 108 insertions(+), 101 deletions(-) delete mode 100644 hw/misc/Makefile.objs delete mode 100644 hw/misc/macio/Makefile.objs create mode 100644 hw/misc/macio/meson.build create mode 100644 hw/misc/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index d0d7816118..ac8278edf7 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -17,7 +17,6 @@ devices-dirs-y += intc/ devices-dirs-$(CONFIG_IPACK) += ipack/ devices-dirs-$(CONFIG_IPMI) += ipmi/ devices-dirs-y += isa/ -devices-dirs-y += misc/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 1f7b2c4fb9..6ca82b0375 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,5 +1,6 @@ subdir('core') subdir('mem') +subdir('misc') subdir('net') subdir('nubus') subdir('nvram') diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs deleted file mode 100644 index 6be3d255ab..0000000000 --- a/hw/misc/Makefile.objs +++ /dev/null @@ -1,95 +0,0 @@ -common-obj-$(CONFIG_APPLESMC) += applesmc.o -common-obj-$(CONFIG_MAX111X) += max111x.o -common-obj-$(CONFIG_TMP105) += tmp105.o -common-obj-$(CONFIG_TMP421) += tmp421.o -common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o -common-obj-$(CONFIG_SGA) += sga.o -common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o -common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o -common-obj-$(CONFIG_EDU) += edu.o -common-obj-$(CONFIG_PCA9552) += pca9552.o - -common-obj-$(CONFIG_UNIMP) += unimp.o -common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o -common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o - -# ARM devices -common-obj-$(CONFIG_PL310) += arm_l2x0.o -common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o -common-obj-$(CONFIG_A9SCU) += a9scu.o -common-obj-$(CONFIG_ARM11SCU) += arm11scu.o - -# Mac devices -common-obj-$(CONFIG_MOS6522) += mos6522.o - -# PKUnity SoC devices -common-obj-$(CONFIG_PUV3) += puv3_pm.o - -common-obj-$(CONFIG_MACIO) += macio/ - -common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o - -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-cpucfg.o -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-dramc.o -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o -common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-sid.o -common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o -common-obj-$(CONFIG_NSERIES) += cbus.o -common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o -common-obj-$(CONFIG_IMX) += imx_ccm.o -common-obj-$(CONFIG_IMX) += imx31_ccm.o -common-obj-$(CONFIG_IMX) += imx25_ccm.o -common-obj-$(CONFIG_IMX) += imx6_ccm.o -common-obj-$(CONFIG_IMX) += imx6ul_ccm.o -obj-$(CONFIG_IMX) += imx6_src.o -common-obj-$(CONFIG_IMX) += imx7_ccm.o -common-obj-$(CONFIG_IMX) += imx7_snvs.o -common-obj-$(CONFIG_IMX) += imx7_gpr.o -common-obj-$(CONFIG_IMX) += imx_rngc.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o -common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o -common-obj-$(CONFIG_OMAP) += omap_clk.o -common-obj-$(CONFIG_OMAP) += omap_gpmc.o -common-obj-$(CONFIG_OMAP) += omap_l4.o -common-obj-$(CONFIG_OMAP) += omap_sdrc.o -common-obj-$(CONFIG_OMAP) += omap_tap.o -common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o -common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o -common-obj-$(CONFIG_RASPI) += bcm2835_property.o -common-obj-$(CONFIG_RASPI) += bcm2835_rng.o -common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o -common-obj-$(CONFIG_SLAVIO) += slavio_misc.o -common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o -common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o -common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o -common-obj-$(CONFIG_STM32F4XX_SYSCFG) += stm32f4xx_syscfg.o -common-obj-$(CONFIG_STM32F4XX_EXTI) += stm32f4xx_exti.o -obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o -obj-$(CONFIG_MIPS_CPS) += mips_cpc.o -obj-$(CONFIG_MIPS_ITU) += mips_itu.o -common-obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o -common-obj-$(CONFIG_MPS2_SCC) += mps2-scc.o - -common-obj-$(CONFIG_TZ_MPC) += tz-mpc.o -common-obj-$(CONFIG_TZ_MSC) += tz-msc.o -common-obj-$(CONFIG_TZ_PPC) += tz-ppc.o -common-obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o -obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o -common-obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o -common-obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o -common-obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o - -common-obj-$(CONFIG_PVPANIC) += pvpanic.o -common-obj-$(CONFIG_AUX) += auxbus.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o -common-obj-$(CONFIG_MSF2) += msf2-sysreg.o -common-obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o -obj-$(CONFIG_MAC_VIA) += mac_via.o - -common-obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o - -obj-$(CONFIG_AVR_POWER) += avr_power.o diff --git a/hw/misc/macio/Makefile.objs b/hw/misc/macio/Makefile.objs deleted file mode 100644 index 07fdb320d4..0000000000 --- a/hw/misc/macio/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -common-obj-y += macio.o -common-obj-$(CONFIG_CUDA) += cuda.o -common-obj-$(CONFIG_MAC_PMU) += pmu.o -common-obj-$(CONFIG_MAC_DBDMA) += mac_dbdma.o -common-obj-$(CONFIG_MACIO_GPIO) += gpio.o diff --git a/hw/misc/macio/meson.build b/hw/misc/macio/meson.build new file mode 100644 index 0000000000..17282da20a --- /dev/null +++ b/hw/misc/macio/meson.build @@ -0,0 +1,8 @@ +macio_ss = ss.source_set() +macio_ss.add(files('macio.c')) +macio_ss.add(when: 'CONFIG_CUDA', if_true: files('cuda.c')) +macio_ss.add(when: 'CONFIG_MACIO_GPIO', if_true: files('gpio.c')) +macio_ss.add(when: 'CONFIG_MAC_DBDMA', if_true: files('mac_dbdma.c')) +macio_ss.add(when: 'CONFIG_MAC_PMU', if_true: files('pmu.c')) + +softmmu_ss.add_all(when: 'CONFIG_MACIO', if_true: macio_ss) diff --git a/hw/misc/meson.build b/hw/misc/meson.build new file mode 100644 index 0000000000..84fed0494d --- /dev/null +++ b/hw/misc/meson.build @@ -0,0 +1,99 @@ +softmmu_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c')) +softmmu_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c')) +softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c')) +softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c')) +softmmu_ss.add(when: 'CONFIG_ISA_TESTDEV', if_true: files('pc-testdev.c')) +softmmu_ss.add(when: 'CONFIG_MAX111X', if_true: files('max111x.c')) +softmmu_ss.add(when: 'CONFIG_PCA9552', if_true: files('pca9552.c')) +softmmu_ss.add(when: 'CONFIG_PCI_TESTDEV', if_true: files('pci-testdev.c')) +softmmu_ss.add(when: 'CONFIG_SGA', if_true: files('sga.c')) +softmmu_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) +softmmu_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) +softmmu_ss.add(when: 'CONFIG_UNIMP', if_true: files('unimp.c')) +softmmu_ss.add(when: 'CONFIG_EMPTY_SLOT', if_true: files('empty_slot.c')) + +# ARM devices +softmmu_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l2x0.c')) +softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_debug.c')) +softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) +softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) + +# Mac devices +softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) + +# PKUnity SoC devices +softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c')) + +subdir('macio') + +softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c')) + +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c')) +specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c')) +softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c')) +softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c')) +softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_pmu.c', 'exynos4210_clk.c', 'exynos4210_rng.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files( + 'imx25_ccm.c', + 'imx31_ccm.c', + 'imx6_ccm.c', + 'imx6ul_ccm.c', + 'imx7_ccm.c', + 'imx7_gpr.c', + 'imx7_snvs.c', + 'imx_ccm.c', + 'imx_rngc.c', +)) +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-hpdmc.c', 'milkymist-pfpu.c')) +softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files( + 'omap_clk.c', + 'omap_gpmc.c', + 'omap_l4.c', + 'omap_sdrc.c', + 'omap_tap.c', +)) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( + 'bcm2835_mbox.c', + 'bcm2835_mphi.c', + 'bcm2835_property.c', + 'bcm2835_rng.c', + 'bcm2835_thermal.c', +)) +softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) +softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) +softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c')) +softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c')) +softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c')) +softmmu_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c')) +softmmu_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c')) + +softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c')) +softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c')) +softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c')) +softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c')) +softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c')) +softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c')) +softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c')) + +softmmu_ss.add(when: 'CONFIG_PVPANIC', if_true: files('pvpanic.c')) +softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c')) +softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c')) + +softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c')) + +specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c')) + +specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c')) +specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c')) + +specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c')) + +specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c')) +specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) -- cgit v1.2.3-55-g7522 From a74fb3984adfcdbb27c47a2585933962fd1b96e9 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:20:39 +0400 Subject: meson: convert hw/isa Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/isa/Makefile.objs | 11 ----------- hw/isa/meson.build | 11 +++++++++++ hw/meson.build | 1 + 4 files changed, 12 insertions(+), 12 deletions(-) delete mode 100644 hw/isa/Makefile.objs create mode 100644 hw/isa/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index ac8278edf7..a28e211e78 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -16,7 +16,6 @@ devices-dirs-y += input/ devices-dirs-y += intc/ devices-dirs-$(CONFIG_IPACK) += ipack/ devices-dirs-$(CONFIG_IPMI) += ipmi/ -devices-dirs-y += isa/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs deleted file mode 100644 index 8e73960a75..0000000000 --- a/hw/isa/Makefile.objs +++ /dev/null @@ -1,11 +0,0 @@ -common-obj-$(CONFIG_ISA_BUS) += isa-bus.o -common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o -common-obj-$(CONFIG_APM) += apm.o -common-obj-$(CONFIG_I82378) += i82378.o -common-obj-$(CONFIG_PC87312) += pc87312.o -common-obj-$(CONFIG_PIIX3) += piix3.o -common-obj-$(CONFIG_PIIX4) += piix4.o -common-obj-$(CONFIG_VT82C686) += vt82c686.o -common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o - -obj-$(CONFIG_LPC_ICH9) += lpc_ich9.o diff --git a/hw/isa/meson.build b/hw/isa/meson.build new file mode 100644 index 0000000000..8bf678ca0a --- /dev/null +++ b/hw/isa/meson.build @@ -0,0 +1,11 @@ +softmmu_ss.add(when: 'CONFIG_APM', if_true: files('apm.c')) +softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c')) +softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) +softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) +softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) +softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) +softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c')) +softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) + +specific_ss.add(when: 'CONFIG_LPC_ICH9', if_true: files('lpc_ich9.c')) diff --git a/hw/meson.build b/hw/meson.build index 6ca82b0375..86598544e6 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('isa') subdir('mem') subdir('misc') subdir('net') -- cgit v1.2.3-55-g7522 From a7b9b7d1d709ba2c5e089f9d69f00df7404c43f7 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:22:36 +0400 Subject: meson: convert hw/ipmi Signed-off-by: Marc-André Lureau Reviewed-by: Corey Minyard Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/ipmi/Makefile.objs | 8 -------- hw/ipmi/meson.build | 11 +++++++++++ hw/meson.build | 1 + 4 files changed, 12 insertions(+), 9 deletions(-) delete mode 100644 hw/ipmi/Makefile.objs create mode 100644 hw/ipmi/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index a28e211e78..f136377866 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -15,7 +15,6 @@ devices-dirs-y += ide/ devices-dirs-y += input/ devices-dirs-y += intc/ devices-dirs-$(CONFIG_IPACK) += ipack/ -devices-dirs-$(CONFIG_IPMI) += ipmi/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs deleted file mode 100644 index 3cca10bc50..0000000000 --- a/hw/ipmi/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -common-obj-$(CONFIG_IPMI) += ipmi.o ipmi_kcs.o ipmi_bt.o -common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_bmc_sim.o -common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_bmc_extern.o -common-obj-$(CONFIG_ISA_IPMI_KCS) += isa_ipmi_kcs.o -common-obj-$(CONFIG_PCI_IPMI_KCS) += pci_ipmi_kcs.o -common-obj-$(CONFIG_ISA_IPMI_BT) += isa_ipmi_bt.o -common-obj-$(CONFIG_PCI_IPMI_BT) += pci_ipmi_bt.o -common-obj-$(CONFIG_IPMI_SSIF) += smbus_ipmi.o diff --git a/hw/ipmi/meson.build b/hw/ipmi/meson.build new file mode 100644 index 0000000000..9622ea2a2c --- /dev/null +++ b/hw/ipmi/meson.build @@ -0,0 +1,11 @@ +ipmi_ss = ss.source_set() +ipmi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c', 'ipmi_kcs.c', 'ipmi_bt.c')) +ipmi_ss.add(when: 'CONFIG_IPMI_LOCAL', if_true: files('ipmi_bmc_sim.c')) +ipmi_ss.add(when: 'CONFIG_IPMI_EXTERN', if_true: files('ipmi_bmc_extern.c')) +ipmi_ss.add(when: 'CONFIG_ISA_IPMI_KCS', if_true: files('isa_ipmi_kcs.c')) +ipmi_ss.add(when: 'CONFIG_PCI_IPMI_KCS', if_true: files('pci_ipmi_kcs.c')) +ipmi_ss.add(when: 'CONFIG_ISA_IPMI_BT', if_true: files('isa_ipmi_bt.c')) +ipmi_ss.add(when: 'CONFIG_PCI_IPMI_BT', if_true: files('pci_ipmi_bt.c')) +ipmi_ss.add(when: 'CONFIG_IPMI_SSIF', if_true: files('smbus_ipmi.c')) + +softmmu_ss.add_all(when: 'CONFIG_IPMI', if_true: ipmi_ss) diff --git a/hw/meson.build b/hw/meson.build index 86598544e6..9796f95e5c 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('ipmi') subdir('isa') subdir('mem') subdir('misc') -- cgit v1.2.3-55-g7522 From ae36d233d37ab80245ac23f1ce04e97b0df6805d Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:23:55 +0400 Subject: meson: convert hw/ipack Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/ipack/Makefile.objs | 2 -- hw/ipack/meson.build | 1 + hw/meson.build | 1 + 4 files changed, 2 insertions(+), 3 deletions(-) delete mode 100644 hw/ipack/Makefile.objs create mode 100644 hw/ipack/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index f136377866..76d9305959 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -14,7 +14,6 @@ devices-dirs-$(CONFIG_I2C) += i2c/ devices-dirs-y += ide/ devices-dirs-y += input/ devices-dirs-y += intc/ -devices-dirs-$(CONFIG_IPACK) += ipack/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/ipack/Makefile.objs b/hw/ipack/Makefile.objs deleted file mode 100644 index 8b9bdcb549..0000000000 --- a/hw/ipack/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -common-obj-$(CONFIG_IPACK) += ipack.o -common-obj-$(CONFIG_IPACK) += tpci200.o diff --git a/hw/ipack/meson.build b/hw/ipack/meson.build new file mode 100644 index 0000000000..3f8138b6f2 --- /dev/null +++ b/hw/ipack/meson.build @@ -0,0 +1 @@ +softmmu_ss.add(when: 'CONFIG_IPACK', if_true: files('ipack.c', 'tpci200.c')) diff --git a/hw/meson.build b/hw/meson.build index 9796f95e5c..ec4bb48a0f 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('ipack') subdir('ipmi') subdir('isa') subdir('mem') -- cgit v1.2.3-55-g7522 From bff065adcdbd81ef699711d7caee1cf41c620a1b Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:36:51 +0400 Subject: meson: convert hw/intc Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/intc/Makefile.objs | 54 -------------------------------------------------- hw/intc/meson.build | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ hw/meson.build | 1 + 4 files changed, 56 insertions(+), 55 deletions(-) delete mode 100644 hw/intc/Makefile.objs create mode 100644 hw/intc/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 76d9305959..80b104168a 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -13,7 +13,6 @@ devices-dirs-$(CONFIG_HYPERV) += hyperv/ devices-dirs-$(CONFIG_I2C) += i2c/ devices-dirs-y += ide/ devices-dirs-y += input/ -devices-dirs-y += intc/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs deleted file mode 100644 index 3ac2b40fbb..0000000000 --- a/hw/intc/Makefile.objs +++ /dev/null @@ -1,54 +0,0 @@ -common-obj-$(CONFIG_HEATHROW_PIC) += heathrow_pic.o -common-obj-$(CONFIG_I8259) += i8259_common.o i8259.o -common-obj-$(CONFIG_PL190) += pl190.o -common-obj-$(CONFIG_PUV3) += puv3_intc.o -common-obj-$(CONFIG_XILINX) += xilinx_intc.o -common-obj-$(CONFIG_XLNX_ZYNQMP_PMU) += xlnx-pmu-iomod-intc.o -common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o -common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o -common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o -common-obj-$(CONFIG_LM32) += lm32_pic.o -common-obj-$(CONFIG_REALVIEW) += realview_gic.o -common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o -common-obj-$(CONFIG_IOAPIC) += ioapic_common.o -common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o -common-obj-$(CONFIG_ARM_GIC) += arm_gic.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv2m.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o -common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o -common-obj-$(CONFIG_OPENPIC) += openpic.o -common-obj-$(CONFIG_RX_ICU) += rx_icu.o -common-obj-y += intc.o - -obj-$(CONFIG_APIC) += apic.o apic_common.o -obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o -obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o -obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o -obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o -obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o -obj-$(CONFIG_GRLIB) += grlib_irqmp.o -obj-$(CONFIG_IOAPIC) += ioapic.o -obj-$(CONFIG_OMAP) += omap_intc.o -obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o -obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o -obj-$(CONFIG_SH4) += sh_intc.o -obj-$(CONFIG_XICS) += xics.o -obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o -obj-$(CONFIG_XICS_KVM) += xics_kvm.o -obj-$(CONFIG_XIVE) += xive.o -obj-$(CONFIG_XIVE_SPAPR) += spapr_xive.o -obj-$(CONFIG_XIVE_KVM) += spapr_xive_kvm.o -obj-$(CONFIG_POWERNV) += xics_pnv.o pnv_xive.o -obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o -obj-$(CONFIG_S390_FLIC) += s390_flic.o -obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o -obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o -obj-$(CONFIG_MIPS_CPS) += mips_gic.o -obj-$(CONFIG_NIOS2) += nios2_iic.o -obj-$(CONFIG_OMPIC) += ompic.o -obj-$(CONFIG_IBEX) += ibex_plic.o -obj-$(CONFIG_LOONGSON_LIOINTC) += loongson_liointc.o diff --git a/hw/intc/meson.build b/hw/intc/meson.build new file mode 100644 index 0000000000..c16f7f036e --- /dev/null +++ b/hw/intc/meson.build @@ -0,0 +1,55 @@ +softmmu_ss.add(files('intc.c')) +softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( + 'arm_gic.c', + 'arm_gic_common.c', + 'arm_gicv2m.c', + 'arm_gicv3.c', + 'arm_gicv3_common.c', + 'arm_gicv3_dist.c', + 'arm_gicv3_its_common.c', + 'arm_gicv3_redist.c', +)) +softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) +softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) +softmmu_ss.add(when: 'CONFIG_I8259', if_true: files('i8259_common.c', 'i8259.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_avic.c', 'imx_gpcv2.c')) +softmmu_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic_common.c')) +softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_pic.c')) +softmmu_ss.add(when: 'CONFIG_OPENPIC', if_true: files('openpic.c')) +softmmu_ss.add(when: 'CONFIG_PL190', if_true: files('pl190.c')) +softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_intc.c')) +softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_gic.c')) +softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_intctl.c')) +softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_intc.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-ipi.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-intc.c')) + +specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) +specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) +specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) +specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c')) +specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c')) +specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) +specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c')) +specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c')) +specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) +specific_ss.add(when: 'CONFIG_NIOS2', if_true: files('nios2_iic.c')) +specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) +specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) +specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c')) +specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c')) +specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c')) +specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c')) +specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) +specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c')) +specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) +specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) +specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c')) +specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c')) +specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) +specific_ss.add(when: 'CONFIG_XIVE_KVM', if_true: files('spapr_xive_kvm.c')) +specific_ss.add(when: 'CONFIG_XIVE_SPAPR', if_true: files('spapr_xive.c')) diff --git a/hw/meson.build b/hw/meson.build index ec4bb48a0f..986e710287 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('intc') subdir('ipack') subdir('ipmi') subdir('isa') -- cgit v1.2.3-55-g7522 From 6a18fd05907f8a1a116f91c6145eee9e5b4f3930 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:39:54 +0400 Subject: meson: convert hw/input Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/input/Makefile.objs | 18 ------------------ hw/input/meson.build | 18 ++++++++++++++++++ hw/meson.build | 1 + 4 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 hw/input/Makefile.objs create mode 100644 hw/input/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 80b104168a..3feccd83d7 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -12,7 +12,6 @@ devices-dirs-y += gpio/ devices-dirs-$(CONFIG_HYPERV) += hyperv/ devices-dirs-$(CONFIG_I2C) += i2c/ devices-dirs-y += ide/ -devices-dirs-y += input/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs deleted file mode 100644 index abc1ff03c0..0000000000 --- a/hw/input/Makefile.objs +++ /dev/null @@ -1,18 +0,0 @@ -common-obj-$(CONFIG_ADB) += adb.o adb-mouse.o adb-kbd.o -common-obj-y += hid.o -common-obj-$(CONFIG_LM832X) += lm832x.o -common-obj-$(CONFIG_PCKBD) += pckbd.o -common-obj-$(CONFIG_PL050) += pl050.o -common-obj-$(CONFIG_PS2) += ps2.o -common-obj-$(CONFIG_STELLARIS_INPUT) += stellaris_input.o -common-obj-$(CONFIG_TSC2005) += tsc2005.o - -common-obj-$(CONFIG_VIRTIO_INPUT) += virtio-input.o -common-obj-$(CONFIG_VIRTIO_INPUT) += virtio-input-hid.o -common-obj-$(CONFIG_VIRTIO_INPUT_HOST) += virtio-input-host.o -common-obj-$(CONFIG_VHOST_USER_INPUT) += vhost-user-input.o - -common-obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o -common-obj-$(CONFIG_TSC210X) += tsc210x.o -common-obj-$(CONFIG_LASIPS2) += lasips2.o diff --git a/hw/input/meson.build b/hw/input/meson.build new file mode 100644 index 0000000000..e7285b15ae --- /dev/null +++ b/hw/input/meson.build @@ -0,0 +1,18 @@ +softmmu_ss.add(files('hid.c')) +softmmu_ss.add(when: 'CONFIG_ADB', if_true: files('adb.c', 'adb-mouse.c', 'adb-kbd.c')) +softmmu_ss.add(when: 'CONFIG_LM832X', if_true: files('lm832x.c')) +softmmu_ss.add(when: 'CONFIG_PCKBD', if_true: files('pckbd.c')) +softmmu_ss.add(when: 'CONFIG_PL050', if_true: files('pl050.c')) +softmmu_ss.add(when: 'CONFIG_PS2', if_true: files('ps2.c')) +softmmu_ss.add(when: 'CONFIG_STELLARIS_INPUT', if_true: files('stellaris_input.c')) +softmmu_ss.add(when: 'CONFIG_TSC2005', if_true: files('tsc2005.c')) + +softmmu_ss.add(when: 'CONFIG_VIRTIO_INPUT', if_true: files('virtio-input.c')) +softmmu_ss.add(when: 'CONFIG_VIRTIO_INPUT', if_true: files('virtio-input-hid.c')) +softmmu_ss.add(when: 'CONFIG_VIRTIO_INPUT_HOST', if_true: files('virtio-input-host.c')) +softmmu_ss.add(when: 'CONFIG_VHOST_USER_INPUT', if_true: files('vhost-user-input.c')) + +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-softusb.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_keypad.c')) +softmmu_ss.add(when: 'CONFIG_TSC210X', if_true: files('tsc210x.c')) +softmmu_ss.add(when: 'CONFIG_LASIPS2', if_true: files('lasips2.c')) diff --git a/hw/meson.build b/hw/meson.build index 986e710287..b15c8d0970 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('input') subdir('intc') subdir('ipack') subdir('ipmi') -- cgit v1.2.3-55-g7522 From 5b8c4d2d9b2348d03a756f9624bc89d595fa8c00 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 18:56:47 +0400 Subject: meson: convert hw/ide Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/ide/Makefile.objs | 14 -------------- hw/ide/meson.build | 14 ++++++++++++++ hw/meson.build | 1 + 4 files changed, 15 insertions(+), 15 deletions(-) delete mode 100644 hw/ide/Makefile.objs create mode 100644 hw/ide/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 3feccd83d7..02c5c0d94e 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -11,7 +11,6 @@ devices-dirs-y += dma/ devices-dirs-y += gpio/ devices-dirs-$(CONFIG_HYPERV) += hyperv/ devices-dirs-$(CONFIG_I2C) += i2c/ -devices-dirs-y += ide/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/ide/Makefile.objs b/hw/ide/Makefile.objs deleted file mode 100644 index faf04e0209..0000000000 --- a/hw/ide/Makefile.objs +++ /dev/null @@ -1,14 +0,0 @@ -common-obj-$(CONFIG_IDE_CORE) += core.o atapi.o -common-obj-$(CONFIG_IDE_QDEV) += qdev.o -common-obj-$(CONFIG_IDE_PCI) += pci.o -common-obj-$(CONFIG_IDE_ISA) += isa.o ioport.o -common-obj-$(CONFIG_IDE_PIIX) += piix.o ioport.o -common-obj-$(CONFIG_IDE_CMD646) += cmd646.o -common-obj-$(CONFIG_IDE_MACIO) += macio.o -common-obj-$(CONFIG_IDE_MMIO) += mmio.o -common-obj-$(CONFIG_IDE_VIA) += via.o -common-obj-$(CONFIG_MICRODRIVE) += microdrive.o -common-obj-$(CONFIG_AHCI) += ahci.o -common-obj-$(CONFIG_AHCI_ICH9) += ich.o -common-obj-$(CONFIG_ALLWINNER_A10) += ahci-allwinner.o -common-obj-$(CONFIG_IDE_SII3112) += sii3112.o diff --git a/hw/ide/meson.build b/hw/ide/meson.build new file mode 100644 index 0000000000..ddcb3b28d2 --- /dev/null +++ b/hw/ide/meson.build @@ -0,0 +1,14 @@ +softmmu_ss.add(when: 'CONFIG_AHCI', if_true: files('ahci.c')) +softmmu_ss.add(when: 'CONFIG_AHCI_ICH9', if_true: files('ich.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('ahci-allwinner.c')) +softmmu_ss.add(when: 'CONFIG_IDE_CMD646', if_true: files('cmd646.c')) +softmmu_ss.add(when: 'CONFIG_IDE_CORE', if_true: files('core.c', 'atapi.c')) +softmmu_ss.add(when: 'CONFIG_IDE_ISA', if_true: files('isa.c', 'ioport.c')) +softmmu_ss.add(when: 'CONFIG_IDE_MACIO', if_true: files('macio.c')) +softmmu_ss.add(when: 'CONFIG_IDE_MMIO', if_true: files('mmio.c')) +softmmu_ss.add(when: 'CONFIG_IDE_PCI', if_true: files('pci.c')) +softmmu_ss.add(when: 'CONFIG_IDE_PIIX', if_true: files('piix.c', 'ioport.c')) +softmmu_ss.add(when: 'CONFIG_IDE_QDEV', if_true: files('qdev.c')) +softmmu_ss.add(when: 'CONFIG_IDE_SII3112', if_true: files('sii3112.c')) +softmmu_ss.add(when: 'CONFIG_IDE_VIA', if_true: files('via.c')) +softmmu_ss.add(when: 'CONFIG_MICRODRIVE', if_true: files('microdrive.c')) diff --git a/hw/meson.build b/hw/meson.build index b15c8d0970..4d7c31c652 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('ide') subdir('input') subdir('intc') subdir('ipack') -- cgit v1.2.3-55-g7522 From c8d9333f1fa7f7ae336369957aa6d85b95ea7120 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 19:00:37 +0400 Subject: meson: convert hw/i2c Signed-off-by: Marc-André Lureau Reviewed-by: Corey Minyard Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/i2c/Makefile.objs | 14 -------------- hw/i2c/meson.build | 16 ++++++++++++++++ hw/meson.build | 1 + 4 files changed, 17 insertions(+), 15 deletions(-) delete mode 100644 hw/i2c/Makefile.objs create mode 100644 hw/i2c/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 02c5c0d94e..22eb804730 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -10,7 +10,6 @@ devices-dirs-y += display/ devices-dirs-y += dma/ devices-dirs-y += gpio/ devices-dirs-$(CONFIG_HYPERV) += hyperv/ -devices-dirs-$(CONFIG_I2C) += i2c/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs deleted file mode 100644 index f2c61eaa8b..0000000000 --- a/hw/i2c/Makefile.objs +++ /dev/null @@ -1,14 +0,0 @@ -common-obj-$(CONFIG_I2C) += core.o -common-obj-$(CONFIG_SMBUS) += smbus_slave.o smbus_master.o -common-obj-$(CONFIG_SMBUS_EEPROM) += smbus_eeprom.o -common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o -common-obj-$(CONFIG_ACPI_X86_ICH) += smbus_ich9.o -common-obj-$(CONFIG_ACPI_SMBUS) += pm_smbus.o -common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o -common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_i2c.o -common-obj-$(CONFIG_NRF51_SOC) += microbit_i2c.o -common-obj-$(CONFIG_MPC_I2C) += mpc_i2c.o -common-obj-$(CONFIG_OMAP) += omap_i2c.o -common-obj-$(CONFIG_PPC4XX) += ppc4xx_i2c.o diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build new file mode 100644 index 0000000000..3a511539ad --- /dev/null +++ b/hw/i2c/meson.build @@ -0,0 +1,16 @@ +i2c_ss = ss.source_set() +i2c_ss.add(when: 'CONFIG_I2C', if_true: files('core.c')) +i2c_ss.add(when: 'CONFIG_SMBUS', if_true: files('smbus_slave.c', 'smbus_master.c')) +i2c_ss.add(when: 'CONFIG_ACPI_SMBUS', if_true: files('pm_smbus.c')) +i2c_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('smbus_ich9.c')) +i2c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i2c.c')) +i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c')) +i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c')) +i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) +i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) +i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) +i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) +i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c')) +i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c')) +i2c_ss.add(when: 'CONFIG_PPC4XX', if_true: files('ppc4xx_i2c.c')) +softmmu_ss.add_all(when: 'CONFIG_I2C', if_true: i2c_ss) diff --git a/hw/meson.build b/hw/meson.build index 4d7c31c652..983edc1d47 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('i2c') subdir('ide') subdir('input') subdir('intc') -- cgit v1.2.3-55-g7522 From cc4d76a3ed2937900038ea0223fc182b945103bc Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 19:02:41 +0400 Subject: meson: convert hw/hyperv Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/hyperv/Makefile.objs | 3 --- hw/hyperv/meson.build | 3 +++ hw/meson.build | 1 + 4 files changed, 4 insertions(+), 4 deletions(-) delete mode 100644 hw/hyperv/Makefile.objs create mode 100644 hw/hyperv/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 22eb804730..a2c2f6d1de 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -9,7 +9,6 @@ devices-dirs-y += cpu/ devices-dirs-y += display/ devices-dirs-y += dma/ devices-dirs-y += gpio/ -devices-dirs-$(CONFIG_HYPERV) += hyperv/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/hyperv/Makefile.objs b/hw/hyperv/Makefile.objs deleted file mode 100644 index 5b614e040c..0000000000 --- a/hw/hyperv/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += hyperv.o -obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o -obj-$(CONFIG_VMBUS) += vmbus.o diff --git a/hw/hyperv/meson.build b/hw/hyperv/meson.build new file mode 100644 index 0000000000..1367e2994f --- /dev/null +++ b/hw/hyperv/meson.build @@ -0,0 +1,3 @@ +specific_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c')) +specific_ss.add(when: 'CONFIG_HYPERV_TESTDEV', if_true: files('hyperv_testdev.c')) +specific_ss.add(when: 'CONFIG_VMBUS', if_true: files('vmbus.c')) diff --git a/hw/meson.build b/hw/meson.build index 983edc1d47..f9e5adfb48 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('hyperv') subdir('i2c') subdir('ide') subdir('input') -- cgit v1.2.3-55-g7522 From a7b057d1d0fd163c74503de1cf5978495ebdfc6f Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 19:03:55 +0400 Subject: meson: convert hw/gpio Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/gpio/Makefile.objs | 12 ------------ hw/gpio/meson.build | 12 ++++++++++++ hw/meson.build | 1 + 4 files changed, 13 insertions(+), 13 deletions(-) delete mode 100644 hw/gpio/Makefile.objs create mode 100644 hw/gpio/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index a2c2f6d1de..c04dfe589c 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -8,7 +8,6 @@ devices-dirs-y += char/ devices-dirs-y += cpu/ devices-dirs-y += display/ devices-dirs-y += dma/ -devices-dirs-y += gpio/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs deleted file mode 100644 index 3cfc261f9b..0000000000 --- a/hw/gpio/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -common-obj-$(CONFIG_MAX7310) += max7310.o -common-obj-$(CONFIG_PL061) += pl061.o -common-obj-$(CONFIG_PUV3) += puv3_gpio.o -common-obj-$(CONFIG_ZAURUS) += zaurus.o -common-obj-$(CONFIG_E500) += mpc8xxx.o -common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o - -common-obj-$(CONFIG_OMAP) += omap_gpio.o -common-obj-$(CONFIG_IMX) += imx_gpio.o -common-obj-$(CONFIG_RASPI) += bcm2835_gpio.o -common-obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o -common-obj-$(CONFIG_ASPEED_SOC) += aspeed_gpio.o diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build new file mode 100644 index 0000000000..6bcdfa6b1d --- /dev/null +++ b/hw/gpio/meson.build @@ -0,0 +1,12 @@ +softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c')) +softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c')) +softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c')) +softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) +softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c')) +softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c')) + +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')) +softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) diff --git a/hw/meson.build b/hw/meson.build index f9e5adfb48..52577c3205 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('gpio') subdir('hyperv') subdir('i2c') subdir('ide') -- cgit v1.2.3-55-g7522 From 7d744257a8b3586efcc8c997ed6219cb338f22fe Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Fri, 16 Aug 2019 19:06:19 +0400 Subject: meson: convert hw/dma Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/dma/Makefile.objs | 16 ---------------- hw/dma/meson.build | 15 +++++++++++++++ hw/meson.build | 1 + 4 files changed, 16 insertions(+), 17 deletions(-) delete mode 100644 hw/dma/Makefile.objs create mode 100644 hw/dma/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index c04dfe589c..26917a4e1b 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -7,7 +7,6 @@ devices-dirs-y += block/ devices-dirs-y += char/ devices-dirs-y += cpu/ devices-dirs-y += display/ -devices-dirs-y += dma/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs deleted file mode 100644 index f4b1cfe26d..0000000000 --- a/hw/dma/Makefile.objs +++ /dev/null @@ -1,16 +0,0 @@ -common-obj-$(CONFIG_PUV3) += puv3_dma.o -common-obj-$(CONFIG_RC4030) += rc4030.o -common-obj-$(CONFIG_PL080) += pl080.o -common-obj-$(CONFIG_PL330) += pl330.o -common-obj-$(CONFIG_I82374) += i82374.o -common-obj-$(CONFIG_I8257) += i8257.o -common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o -common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o -common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o -common-obj-$(CONFIG_STP2000) += sparc32_dma.o -common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dpdma.o -common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zdma.o - -common-obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o -common-obj-$(CONFIG_RASPI) += bcm2835_dma.o diff --git a/hw/dma/meson.build b/hw/dma/meson.build new file mode 100644 index 0000000000..ff5bb3748f --- /dev/null +++ b/hw/dma/meson.build @@ -0,0 +1,15 @@ +softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_dma.c')) +softmmu_ss.add(when: 'CONFIG_RC4030', if_true: files('rc4030.c')) +softmmu_ss.add(when: 'CONFIG_PL080', if_true: files('pl080.c')) +softmmu_ss.add(when: 'CONFIG_PL330', if_true: files('pl330.c')) +softmmu_ss.add(when: 'CONFIG_I82374', if_true: files('i82374.c')) +softmmu_ss.add(when: 'CONFIG_I8257', if_true: files('i8257.c')) +softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('xilinx_axidma.c')) +softmmu_ss.add(when: 'CONFIG_ZYNQ_DEVCFG', if_true: files('xlnx-zynq-devcfg.c')) +softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_dma.c')) +softmmu_ss.add(when: 'CONFIG_STP2000', if_true: files('sparc32_dma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dpdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) diff --git a/hw/meson.build b/hw/meson.build index 52577c3205..96da0bba7e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('dma') subdir('gpio') subdir('hyperv') subdir('i2c') -- cgit v1.2.3-55-g7522 From b4c8eece5735b5b30bc48f600745c587f8f1170a Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:03:19 +0400 Subject: meson: convert hw/display Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 1 + hw/Makefile.objs | 1 - hw/display/Makefile.objs | 65 ------------------------------------- hw/display/meson.build | 84 ++++++++++++++++++++++++++++++++++++++++++++++++ hw/meson.build | 1 + 5 files changed, 86 insertions(+), 66 deletions(-) delete mode 100644 hw/display/Makefile.objs create mode 100644 hw/display/meson.build diff --git a/Makefile.target b/Makefile.target index 3d5a2af4af..3534ece38a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -169,6 +169,7 @@ LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOM LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) +LIBS := $(LIBS) $(VIRGL_LIBS) # Hardware support ifeq ($(TARGET_NAME), sparc64) diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 26917a4e1b..6fce6a1473 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -6,7 +6,6 @@ devices-dirs-y += audio/ devices-dirs-y += block/ devices-dirs-y += char/ devices-dirs-y += cpu/ -devices-dirs-y += display/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs deleted file mode 100644 index d619594ad4..0000000000 --- a/hw/display/Makefile.objs +++ /dev/null @@ -1,65 +0,0 @@ -common-obj-$(CONFIG_DDC) += i2c-ddc.o -common-obj-$(CONFIG_EDID) += edid-generate.o edid-region.o - -common-obj-$(CONFIG_FW_CFG_DMA) += ramfb.o -common-obj-$(CONFIG_FW_CFG_DMA) += ramfb-standalone.o - -common-obj-$(CONFIG_ADS7846) += ads7846.o -common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o -common-obj-$(call land,$(CONFIG_VGA_CIRRUS),$(CONFIG_VGA_ISA))+=cirrus_vga_isa.o -common-obj-$(CONFIG_G364FB) += g364fb.o -common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o -common-obj-$(CONFIG_PL110) += pl110.o -common-obj-$(CONFIG_SII9022) += sii9022.o -common-obj-$(CONFIG_SSD0303) += ssd0303.o -common-obj-$(CONFIG_SSD0323) += ssd0323.o -common-obj-$(CONFIG_XEN) += xenfb.o - -common-obj-$(CONFIG_VGA_PCI) += vga-pci.o -common-obj-$(CONFIG_VGA_ISA) += vga-isa.o -common-obj-$(CONFIG_VGA_ISA_MM) += vga-isa-mm.o -common-obj-$(CONFIG_VMWARE_VGA) += vmware_vga.o -common-obj-$(CONFIG_BOCHS_DISPLAY) += bochs-display.o - -common-obj-$(CONFIG_BLIZZARD) += blizzard.o -common-obj-$(CONFIG_EXYNOS4) += exynos4210_fimd.o -common-obj-$(CONFIG_FRAMEBUFFER) += framebuffer.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-vgafb.o -common-obj-$(CONFIG_ZAURUS) += tc6393xb.o -common-obj-$(CONFIG_MACFB) += macfb.o - -obj-$(CONFIG_MILKYMIST_TMU2) += milkymist-tmu2.o -milkymist-tmu2.o-cflags := $(X11_CFLAGS) $(OPENGL_CFLAGS) -milkymist-tmu2.o-libs := $(X11_LIBS) $(OPENGL_LIBS) - -common-obj-$(CONFIG_OMAP) += omap_dss.o -obj-$(CONFIG_OMAP) += omap_lcdc.o -common-obj-$(CONFIG_PXA2XX) += pxa2xx_lcd.o -common-obj-$(CONFIG_RASPI) += bcm2835_fb.o -common-obj-$(CONFIG_SM501) += sm501.o -common-obj-$(CONFIG_TCX) += tcx.o -common-obj-$(CONFIG_CG3) += cg3.o -common-obj-$(CONFIG_NEXTCUBE) += next-fb.o -common-obj-$(CONFIG_ARTIST) += artist.o - -obj-$(CONFIG_VGA) += vga.o - -ifeq ($(CONFIG_QXL),y) -common-obj-m += qxl.mo -qxl.mo-objs = qxl.o qxl-logger.o qxl-render.o -endif - -common-obj-$(CONFIG_VIRTIO_GPU) += virtio-gpu-base.o virtio-gpu.o virtio-gpu-3d.o -common-obj-$(CONFIG_VHOST_USER_GPU) += vhost-user-gpu.o -common-obj-$(call land,$(CONFIG_VIRTIO_GPU),$(CONFIG_VIRTIO_PCI)) += virtio-gpu-pci.o -common-obj-$(call land,$(CONFIG_VHOST_USER_GPU),$(CONFIG_VIRTIO_PCI)) += vhost-user-gpu-pci.o -common-obj-$(CONFIG_VIRTIO_VGA) += virtio-vga.o -common-obj-$(CONFIG_VHOST_USER_VGA) += vhost-user-vga.o -virtio-gpu.o-cflags := $(VIRGL_CFLAGS) -virtio-gpu.o-libs += $(VIRGL_LIBS) -virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS) -virtio-gpu-3d.o-libs += $(VIRGL_LIBS) -common-obj-$(CONFIG_DPCD) += dpcd.o -common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dp.o - -common-obj-$(CONFIG_ATI_VGA) += ati.o ati_2d.o ati_dbg.o diff --git a/hw/display/meson.build b/hw/display/meson.build new file mode 100644 index 0000000000..78adaf9db4 --- /dev/null +++ b/hw/display/meson.build @@ -0,0 +1,84 @@ +hw_display_modules = {} + +softmmu_ss.add(when: 'CONFIG_DDC', if_true: files('i2c-ddc.c')) +softmmu_ss.add(when: 'CONFIG_EDID', if_true: files('edid-generate.c', 'edid-region.c')) + +softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('ramfb.c')) +softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('ramfb-standalone.c')) + +softmmu_ss.add(when: 'CONFIG_ADS7846', if_true: files('ads7846.c')) +softmmu_ss.add(when: 'CONFIG_VGA_CIRRUS', if_true: files('cirrus_vga.c')) +softmmu_ss.add(when: ['CONFIG_VGA_CIRRUS', 'CONFIG_VGA_ISA'], if_true: files('cirrus_vga_isa.c')) +softmmu_ss.add(when: 'CONFIG_G364FB', if_true: files('g364fb.c')) +softmmu_ss.add(when: 'CONFIG_JAZZ_LED', if_true: files('jazz_led.c')) +softmmu_ss.add(when: 'CONFIG_PL110', if_true: files('pl110.c')) +softmmu_ss.add(when: 'CONFIG_SII9022', if_true: files('sii9022.c')) +softmmu_ss.add(when: 'CONFIG_SSD0303', if_true: files('ssd0303.c')) +softmmu_ss.add(when: 'CONFIG_SSD0323', if_true: files('ssd0323.c')) +softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xenfb.c')) + +softmmu_ss.add(when: 'CONFIG_VGA_PCI', if_true: files('vga-pci.c')) +softmmu_ss.add(when: 'CONFIG_VGA_ISA', if_true: files('vga-isa.c')) +softmmu_ss.add(when: 'CONFIG_VGA_ISA_MM', if_true: files('vga-isa-mm.c')) +softmmu_ss.add(when: 'CONFIG_VMWARE_VGA', if_true: files('vmware_vga.c')) +softmmu_ss.add(when: 'CONFIG_BOCHS_DISPLAY', if_true: files('bochs-display.c')) + +softmmu_ss.add(when: 'CONFIG_BLIZZARD', if_true: files('blizzard.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_fimd.c')) +softmmu_ss.add(when: 'CONFIG_FRAMEBUFFER', if_true: files('framebuffer.c')) +softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('tc6393xb.c')) + +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dss.c')) +softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_lcd.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_fb.c')) +softmmu_ss.add(when: 'CONFIG_SM501', if_true: files('sm501.c')) +softmmu_ss.add(when: 'CONFIG_TCX', if_true: files('tcx.c')) +softmmu_ss.add(when: 'CONFIG_CG3', if_true: files('cg3.c')) +softmmu_ss.add(when: 'CONFIG_MACFB', if_true: files('macfb.c')) +softmmu_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c')) + +specific_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) + +if config_all_devices.has_key('CONFIG_QXL') + qxl_ss = ss.source_set() + qxl_ss.add(when: 'CONFIG_QXL', if_true: files('qxl.c', 'qxl-logger.c', 'qxl-render.c')) + hw_display_modules += {'qxl': qxl_ss} +endif + +softmmu_ss.add(when: 'CONFIG_QXL', if_true: files('qxl.c', 'qxl-logger.c', 'qxl-render.c')) + +softmmu_ss.add(when: 'CONFIG_DPCD', if_true: files('dpcd.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dp.c')) + +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-vgafb.c')) +softmmu_ss.add(when: 'CONFIG_ARTIST', if_true: files('artist.c')) + +softmmu_ss.add(when: [pixman, 'CONFIG_ATI_VGA'], if_true: files('ati.c', 'ati_2d.c', 'ati_dbg.c')) + +if config_all_devices.has_key('CONFIG_VIRTIO_GPU') + virtio_gpu_ss = ss.source_set() + virtio_gpu_ss.add(when: 'CONFIG_VIRTIO_GPU', + if_true: [files('virtio-gpu-base.c', 'virtio-gpu.c', 'virtio-gpu-3d.c'), pixman, virgl]) + virtio_gpu_ss.add(when: 'CONFIG_VHOST_USER_GPU', if_true: files('vhost-user-gpu.c')) + virtio_gpu_ss.add(when: ['CONFIG_VIRTIO_GPU', 'CONFIG_VIRTIO_PCI'], if_true: files('virtio-gpu-pci.c')) + virtio_gpu_ss.add(when: ['CONFIG_VHOST_USER_GPU', 'CONFIG_VIRTIO_PCI'], if_true: files('vhost-user-gpu-pci.c')) + virtio_gpu_ss.add(when: 'CONFIG_VIRTIO_VGA', if_true: files('virtio-vga.c')) + virtio_gpu_ss.add(when: 'CONFIG_VHOST_USER_VGA', if_true: files('vhost-user-vga.c')) + + # FIXME: this was attempted in the Makefile build system; it was then reverted + # as it would try to load all devices when the module is loaded, even if + # config_devices for this target only has some of them. Since virtio-gpu-pci + # and virtio-vga both instantiate a virtio-gpu-device, fixing it probably does + # not even require a dependency system, just splitting the module in three + # for CONFIG_VIRTIO_GPU/CONFIG_VHOST_USER_GPU, CONFIG_VIRTIO_PCI and + # CONFIG_VIRTIO_VGA/CONFIG_VHOST_USER_VGA. + # Sourcesets are a dime a dozen, so keep it and just disable module builds. + + #hw_display_modules += {'virtio-gpu': virtio_gpu_ss} + softmmu_ss.add_all(virtio_gpu_ss) +endif + +specific_ss.add(when: [x11, opengl, 'CONFIG_MILKYMIST_TMU2'], if_true: files('milkymist-tmu2.c')) +specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_lcdc.c')) + +modules += { 'hw-display': hw_display_modules } diff --git a/hw/meson.build b/hw/meson.build index 96da0bba7e..dacd26c561 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('display') subdir('dma') subdir('gpio') subdir('hyperv') -- cgit v1.2.3-55-g7522 From cff3c5d2b4029f375b9ed077d99577b3d64e7e24 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:21:13 +0400 Subject: meson: convert hw/cpu Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/cpu/Makefile.objs | 5 ----- hw/cpu/meson.build | 6 ++++++ hw/meson.build | 1 + 4 files changed, 7 insertions(+), 6 deletions(-) delete mode 100644 hw/cpu/Makefile.objs create mode 100644 hw/cpu/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 6fce6a1473..97ad30295e 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -5,7 +5,6 @@ devices-dirs-y += adc/ devices-dirs-y += audio/ devices-dirs-y += block/ devices-dirs-y += char/ -devices-dirs-y += cpu/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs deleted file mode 100644 index 8db9e8a7b3..0000000000 --- a/hw/cpu/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o -obj-$(CONFIG_REALVIEW) += realview_mpcore.o -obj-$(CONFIG_A9MPCORE) += a9mpcore.o -obj-$(CONFIG_A15MPCORE) += a15mpcore.o -common-obj-y += core.o cluster.o diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build new file mode 100644 index 0000000000..9e52fee9e7 --- /dev/null +++ b/hw/cpu/meson.build @@ -0,0 +1,6 @@ +softmmu_ss.add(files('core.c', 'cluster.c')) + +specific_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c')) +specific_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c')) +specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) +specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c')) diff --git a/hw/meson.build b/hw/meson.build index dacd26c561..103da4840b 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,4 +1,5 @@ subdir('core') +subdir('cpu') subdir('display') subdir('dma') subdir('gpio') -- cgit v1.2.3-55-g7522 From a518e03cdba86079891d7faf57c928e01b323250 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:25:08 +0400 Subject: meson: convert hw/char Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/char/Makefile.objs | 39 --------------------------------------- hw/char/meson.build | 38 ++++++++++++++++++++++++++++++++++++++ hw/meson.build | 1 + 4 files changed, 39 insertions(+), 40 deletions(-) delete mode 100644 hw/char/Makefile.objs create mode 100644 hw/char/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 97ad30295e..04cfb6ca6d 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -4,7 +4,6 @@ devices-dirs-y += acpi/ devices-dirs-y += adc/ devices-dirs-y += audio/ devices-dirs-y += block/ -devices-dirs-y += char/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs deleted file mode 100644 index bf177ac41d..0000000000 --- a/hw/char/Makefile.objs +++ /dev/null @@ -1,39 +0,0 @@ -common-obj-$(CONFIG_IPACK) += ipoctal232.o -common-obj-$(CONFIG_ESCC) += escc.o -common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o -common-obj-$(CONFIG_PARALLEL) += parallel.o -common-obj-$(CONFIG_ISA_BUS) += parallel-isa.o -common-obj-$(CONFIG_PL011) += pl011.o -common-obj-$(CONFIG_SERIAL) += serial.o -common-obj-$(CONFIG_SERIAL_ISA) += serial-isa.o -common-obj-$(CONFIG_SERIAL_PCI) += serial-pci.o -common-obj-$(CONFIG_SERIAL_PCI_MULTI) += serial-pci-multi.o -common-obj-$(CONFIG_VIRTIO_SERIAL) += virtio-console.o -common-obj-$(CONFIG_XILINX) += xilinx_uartlite.o -common-obj-$(CONFIG_XEN) += xen_console.o -common-obj-$(CONFIG_CADENCE) += cadence_uart.o -common-obj-$(CONFIG_IBEX) += ibex_uart.o - -common-obj-$(CONFIG_EXYNOS4) += exynos4210_uart.o -common-obj-$(CONFIG_COLDFIRE) += mcf_uart.o -common-obj-$(CONFIG_OMAP) += omap_uart.o -common-obj-$(CONFIG_SH4) += sh_serial.o -common-obj-$(CONFIG_DIGIC) += digic-uart.o -common-obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o -common-obj-$(CONFIG_RASPI) += bcm2835_aux.o -common-obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o -common-obj-$(CONFIG_AVR_USART) += avr_usart.o - -common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o -common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o -common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o -common-obj-$(CONFIG_GRLIB) += grlib_apbuart.o -common-obj-$(CONFIG_IMX) += imx_serial.o -common-obj-$(CONFIG_LM32) += lm32_juart.o -common-obj-$(CONFIG_LM32) += lm32_uart.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o -common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o - -obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o -obj-$(CONFIG_PSERIES) += spapr_vty.o -obj-$(CONFIG_TERMINAL3270) += terminal3270.o diff --git a/hw/char/meson.build b/hw/char/meson.build new file mode 100644 index 0000000000..e888215145 --- /dev/null +++ b/hw/char/meson.build @@ -0,0 +1,38 @@ +softmmu_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_uart.c')) +softmmu_ss.add(when: 'CONFIG_CMSDK_APB_UART', if_true: files('cmsdk-apb-uart.c')) +softmmu_ss.add(when: 'CONFIG_ESCC', if_true: files('escc.c')) +softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_ser.c')) +softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_apbuart.c')) +softmmu_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_uart.c')) +softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_serial.c')) +softmmu_ss.add(when: 'CONFIG_IPACK', if_true: files('ipoctal232.c')) +softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('parallel-isa.c')) +softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugcon.c')) +softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_juart.c')) +softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_uart.c')) +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-uart.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_uart.c')) +softmmu_ss.add(when: 'CONFIG_PARALLEL', if_true: files('parallel.c')) +softmmu_ss.add(when: 'CONFIG_PL011', if_true: files('pl011.c')) +softmmu_ss.add(when: 'CONFIG_SCLPCONSOLE', if_true: files('sclpconsole.c', 'sclpconsole-lm.c')) +softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c')) +softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c')) +softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c')) +softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c')) +softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c')) +softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c')) +softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) + +softmmu_ss.add(when: 'CONFIG_AVR_USART', if_true: files('avr_usart.c')) +softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c')) +softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic-uart.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c')) +softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) +softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) +softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) +softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) + +specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c')) +specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c')) +specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) diff --git a/hw/meson.build b/hw/meson.build index 103da4840b..dd0c77ec2b 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('char') subdir('core') subdir('cpu') subdir('display') -- cgit v1.2.3-55-g7522 From 6bcb5d96654ecbf74feaa418412487a743051dcb Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:30:59 +0400 Subject: meson: convert hw/block Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/block/Makefile.objs | 18 ------------------ hw/block/dataplane/Makefile.objs | 2 -- hw/block/dataplane/meson.build | 2 ++ hw/block/meson.build | 21 +++++++++++++++++++++ hw/meson.build | 1 + 6 files changed, 24 insertions(+), 21 deletions(-) delete mode 100644 hw/block/Makefile.objs delete mode 100644 hw/block/dataplane/Makefile.objs create mode 100644 hw/block/dataplane/meson.build create mode 100644 hw/block/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 04cfb6ca6d..9068859ef0 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -3,7 +3,6 @@ devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFI devices-dirs-y += acpi/ devices-dirs-y += adc/ devices-dirs-y += audio/ -devices-dirs-y += block/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs deleted file mode 100644 index 8855c22656..0000000000 --- a/hw/block/Makefile.objs +++ /dev/null @@ -1,18 +0,0 @@ -common-obj-y += block.o cdrom.o hd-geometry.o -common-obj-$(CONFIG_FDC) += fdc.o -common-obj-$(CONFIG_SSI_M25P80) += m25p80.o -common-obj-$(CONFIG_NAND) += nand.o -common-obj-$(CONFIG_PFLASH_CFI01) += pflash_cfi01.o -common-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o -common-obj-$(CONFIG_XEN) += xen-block.o -common-obj-$(CONFIG_ECC) += ecc.o -common-obj-$(CONFIG_ONENAND) += onenand.o -common-obj-$(CONFIG_SWIM) += swim.o - -common-obj-$(CONFIG_SH4) += tc58128.o - -obj-$(CONFIG_VIRTIO_BLK) += virtio-blk.o -obj-$(CONFIG_VHOST_USER_BLK) += vhost-user-blk.o -common-obj-$(CONFIG_NVME_PCI) += nvme.o - -obj-y += dataplane/ diff --git a/hw/block/dataplane/Makefile.objs b/hw/block/dataplane/Makefile.objs deleted file mode 100644 index 0c5270268e..0000000000 --- a/hw/block/dataplane/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_VIRTIO_BLK) += virtio-blk.o -obj-$(CONFIG_XEN) += xen-block.o diff --git a/hw/block/dataplane/meson.build b/hw/block/dataplane/meson.build new file mode 100644 index 0000000000..12c6a264f1 --- /dev/null +++ b/hw/block/dataplane/meson.build @@ -0,0 +1,2 @@ +specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c')) +specific_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c')) diff --git a/hw/block/meson.build b/hw/block/meson.build new file mode 100644 index 0000000000..78cad8f7cb --- /dev/null +++ b/hw/block/meson.build @@ -0,0 +1,21 @@ +softmmu_ss.add(files( + 'block.c', + 'cdrom.c', + 'hd-geometry.c' +)) +softmmu_ss.add(when: 'CONFIG_ECC', if_true: files('ecc.c')) +softmmu_ss.add(when: 'CONFIG_FDC', if_true: files('fdc.c')) +softmmu_ss.add(when: 'CONFIG_NAND', if_true: files('nand.c')) +softmmu_ss.add(when: 'CONFIG_ONENAND', if_true: files('onenand.c')) +softmmu_ss.add(when: 'CONFIG_PFLASH_CFI01', if_true: files('pflash_cfi01.c')) +softmmu_ss.add(when: 'CONFIG_PFLASH_CFI02', if_true: files('pflash_cfi02.c')) +softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c')) +softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c')) +softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c')) +softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('tc58128.c')) +softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c')) + +specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c')) +specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk.c')) + +subdir('dataplane') diff --git a/hw/meson.build b/hw/meson.build index dd0c77ec2b..f968aa8374 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('block') subdir('char') subdir('core') subdir('cpu') -- cgit v1.2.3-55-g7522 From a9d4825542510e6d9483e29fb8e3761397eaada1 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:33:44 +0400 Subject: meson: convert hw/audio Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/audio/Makefile.objs | 18 ------------------ hw/audio/meson.build | 14 ++++++++++++++ hw/meson.build | 1 + 4 files changed, 15 insertions(+), 19 deletions(-) delete mode 100644 hw/audio/Makefile.objs create mode 100644 hw/audio/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 9068859ef0..c0cbc0f132 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOFTMMU), y) devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFIG_XEN))) += 9pfs/ devices-dirs-y += acpi/ devices-dirs-y += adc/ -devices-dirs-y += audio/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs deleted file mode 100644 index 63db383709..0000000000 --- a/hw/audio/Makefile.objs +++ /dev/null @@ -1,18 +0,0 @@ -# Sound -common-obj-$(CONFIG_SB16) += sb16.o -common-obj-$(CONFIG_ES1370) += es1370.o -common-obj-$(CONFIG_AC97) += ac97.o -common-obj-$(CONFIG_ADLIB) += fmopl.o adlib.o -common-obj-$(CONFIG_GUS) += gus.o gusemu_hal.o gusemu_mixer.o -common-obj-$(CONFIG_CS4231A) += cs4231a.o -common-obj-$(CONFIG_HDA) += intel-hda.o hda-codec.o - -common-obj-$(CONFIG_PCSPK) += pcspk.o -common-obj-$(CONFIG_WM8750) += wm8750.o -common-obj-$(CONFIG_PL041) += pl041.o lm4549.o - -common-obj-$(CONFIG_CS4231) += cs4231.o -common-obj-$(CONFIG_MARVELL_88W8618) += marvell_88w8618.o -common-obj-$(CONFIG_MILKYMIST) += milkymist-ac97.o - -common-obj-y += soundhw.o diff --git a/hw/audio/meson.build b/hw/audio/meson.build new file mode 100644 index 0000000000..549e9a0396 --- /dev/null +++ b/hw/audio/meson.build @@ -0,0 +1,14 @@ +softmmu_ss.add(files('soundhw.c')) +softmmu_ss.add(when: 'CONFIG_AC97', if_true: files('ac97.c')) +softmmu_ss.add(when: 'CONFIG_ADLIB', if_true: files('fmopl.c', 'adlib.c')) +softmmu_ss.add(when: 'CONFIG_CS4231', if_true: files('cs4231.c')) +softmmu_ss.add(when: 'CONFIG_CS4231A', if_true: files('cs4231a.c')) +softmmu_ss.add(when: 'CONFIG_ES1370', if_true: files('es1370.c')) +softmmu_ss.add(when: 'CONFIG_GUS', if_true: files('gus.c', 'gusemu_hal.c', 'gusemu_mixer.c')) +softmmu_ss.add(when: 'CONFIG_HDA', if_true: files('intel-hda.c', 'hda-codec.c')) +softmmu_ss.add(when: 'CONFIG_MARVELL_88W8618', if_true: files('marvell_88w8618.c')) +softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-ac97.c')) +softmmu_ss.add(when: 'CONFIG_PCSPK', if_true: files('pcspk.c')) +softmmu_ss.add(when: 'CONFIG_PL041', if_true: files('pl041.c', 'lm4549.c')) +softmmu_ss.add(when: 'CONFIG_SB16', if_true: files('sb16.c')) +softmmu_ss.add(when: 'CONFIG_WM8750', if_true: files('wm8750.c')) diff --git a/hw/meson.build b/hw/meson.build index f968aa8374..624335be90 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('audio') subdir('block') subdir('char') subdir('core') -- cgit v1.2.3-55-g7522 From b53d555f6907434afc93d78cf316f10598b2853c Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:34:47 +0400 Subject: meson: convert hw/adc Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/adc/Makefile.objs | 1 - hw/adc/meson.build | 1 + hw/meson.build | 1 + 4 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 hw/adc/Makefile.objs create mode 100644 hw/adc/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index c0cbc0f132..4bdb674ef0 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOFTMMU), y) devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFIG_XEN))) += 9pfs/ devices-dirs-y += acpi/ -devices-dirs-y += adc/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs deleted file mode 100644 index 2b9dc36c7f..0000000000 --- a/hw/adc/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -common-obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o diff --git a/hw/adc/meson.build b/hw/adc/meson.build new file mode 100644 index 0000000000..0d62ae96ae --- /dev/null +++ b/hw/adc/meson.build @@ -0,0 +1 @@ +softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c')) diff --git a/hw/meson.build b/hw/meson.build index 624335be90..ffa3f06dc0 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('adc') subdir('audio') subdir('block') subdir('char') -- cgit v1.2.3-55-g7522 From 36b34c359fc0c38c4221358671712bbdffa1a2d9 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 11:40:51 +0400 Subject: meson: convert hw/acpi Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- hw/Makefile.objs | 1 - hw/acpi/Makefile.objs | 26 -------------------------- hw/acpi/meson.build | 25 +++++++++++++++++++++++++ hw/meson.build | 1 + 4 files changed, 26 insertions(+), 27 deletions(-) delete mode 100644 hw/acpi/Makefile.objs create mode 100644 hw/acpi/meson.build diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 4bdb674ef0..ebae00af6e 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOFTMMU), y) devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFIG_XEN))) += 9pfs/ -devices-dirs-y += acpi/ endif common-obj-y += $(devices-dirs-y) diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs deleted file mode 100644 index 72886c7965..0000000000 --- a/hw/acpi/Makefile.objs +++ /dev/null @@ -1,26 +0,0 @@ -ifeq ($(CONFIG_ACPI),y) -common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o -common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o -common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o -common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o -common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o -common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o -common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o -common-obj-$(CONFIG_ACPI_HW_REDUCED) += generic_event_device.o -common-obj-$(CONFIG_ACPI_HMAT) += hmat.o -common-obj-$(CONFIG_ACPI_APEI) += ghes.o -common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o -common-obj-$(call lnot,$(CONFIG_PC)) += acpi-x86-stub.o - -common-obj-y += acpi_interface.o -common-obj-y += bios-linker-loader.o -common-obj-y += aml-build.o utils.o -common-obj-$(CONFIG_ACPI_PCI) += pci.o -common-obj-$(CONFIG_TPM) += tpm.o - -common-obj-$(CONFIG_IPMI) += ipmi.o -common-obj-$(call lnot,$(CONFIG_IPMI)) += ipmi-stub.o -else -common-obj-y += acpi-stub.o aml-build-stub.o -endif -common-obj-$(CONFIG_ALL) += acpi-stub.o aml-build-stub.o acpi-x86-stub.o ipmi-stub.o diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build new file mode 100644 index 0000000000..dd69577212 --- /dev/null +++ b/hw/acpi/meson.build @@ -0,0 +1,25 @@ +acpi_ss = ss.source_set() +acpi_ss.add(files( + 'acpi_interface.c', + 'aml-build.c', + 'bios-linker-loader.c', + 'utils.c', +)) +acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu.c')) +acpi_ss.add(when: 'CONFIG_ACPI_CPU_HOTPLUG', if_true: files('cpu_hotplug.c')) +acpi_ss.add(when: 'CONFIG_ACPI_MEMORY_HOTPLUG', if_true: files('memory_hotplug.c')) +acpi_ss.add(when: 'CONFIG_ACPI_NVDIMM', if_true: files('nvdimm.c')) +acpi_ss.add(when: 'CONFIG_ACPI_PCI', if_true: files('pci.c')) +acpi_ss.add(when: 'CONFIG_ACPI_VMGENID', if_true: files('vmgenid.c')) +acpi_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: files('generic_event_device.c')) +acpi_ss.add(when: 'CONFIG_ACPI_HMAT', if_true: files('hmat.c')) +acpi_ss.add(when: 'CONFIG_ACPI_APEI', if_true: files('ghes.c')) +acpi_ss.add(when: 'CONFIG_ACPI_X86', if_true: files('core.c', 'piix4.c', 'pcihp.c'), if_false: files('acpi-stub.c')) +acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c')) +acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files('ipmi-stub.c')) +acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c')) +acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) +softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-build-stub.c')) +softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss) +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 'aml-build-stub.c', + 'acpi-x86-stub.c', 'ipmi-stub.c')) diff --git a/hw/meson.build b/hw/meson.build index ffa3f06dc0..55ca2b2b61 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('acpi') subdir('adc') subdir('audio') subdir('block') -- cgit v1.2.3-55-g7522 From b2c00bce54cce0dbb8c7fd3dd397cfdaca4c28ef Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 12:04:43 +0400 Subject: meson: convert hw/9pfs, cleanup hw/Makefile.objs is gone so there is more code that can be removed. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 4 ---- Makefile.objs | 8 -------- Makefile.target | 15 --------------- hw/9pfs/Kconfig | 4 ++++ hw/9pfs/Makefile.objs | 9 --------- hw/9pfs/meson.build | 20 ++++++++++++++++++++ hw/Makefile.objs | 8 -------- hw/meson.build | 1 + 8 files changed, 25 insertions(+), 44 deletions(-) delete mode 100644 hw/9pfs/Makefile.objs create mode 100644 hw/9pfs/meson.build delete mode 100644 hw/Makefile.objs diff --git a/Makefile b/Makefile index 0b06b9cacd..ca51abfd8c 100644 --- a/Makefile +++ b/Makefile @@ -178,10 +178,6 @@ ifneq ($(wildcard config-host.mak),) include $(SRC_PATH)/Makefile.objs endif -dummy := $(call unnest-vars,, \ - common-obj-y \ - common-obj-m) - include $(SRC_PATH)/tests/Makefile.include all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) recurse-all modules diff --git a/Makefile.objs b/Makefile.objs index c332323b81..c9720a92df 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -61,18 +61,10 @@ common-obj-$(if $(CONFIG_RBD),m) += block-rbd$(DSOSUF) common-obj-$(if $(CONFIG_LZFSE),m) += block-dmg-lzfse$(DSOSUF) common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF) -common-obj-y += hw/ -common-obj-m += hw/ - common-obj-y += libqmp.fa endif # CONFIG_SOFTMMU -####################################################################### -# Target-independent parts used in system and user emulation - -common-obj-y += hw/ - ###################################################################### # Resource file for Windows executables version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o diff --git a/Makefile.target b/Makefile.target index 3534ece38a..c95e0deb79 100644 --- a/Makefile.target +++ b/Makefile.target @@ -156,7 +156,6 @@ endif #CONFIG_BSD_USER ifdef CONFIG_SOFTMMU obj-y += softmmu/ obj-y += gdbstub.o -obj-y += hw/ LIBS := $(libs_softmmu) $(LIBS) # Temporary until emulators are linked by Meson @@ -185,20 +184,6 @@ endif # CONFIG_SOFTMMU dummy := $(call unnest-vars,,obj-y) all-obj-y := $(obj-y) -# -# common-obj-m has some crap here, probably as side effect from -# unnest-vars recursing into target directories to fill obj-y and not -# properly handling the -m case. -# -# Clear common-obj-m as workaround. Fixes suspious dependency errors -# when building devices as modules. A bit hackish, but should be ok -# as long as we do not have any target-specific modules. -# -# The meson-based build system currently in development doesn't need -# unnest-vars and will obsolete this workaround. -# -common-obj-m := - include $(SRC_PATH)/Makefile.objs dummy := $(call fix-paths,../,, \ authz-obj-y \ diff --git a/hw/9pfs/Kconfig b/hw/9pfs/Kconfig index 3ae5749661..d3ebd73730 100644 --- a/hw/9pfs/Kconfig +++ b/hw/9pfs/Kconfig @@ -2,8 +2,12 @@ config FSDEV_9P bool depends on VIRTFS +config 9PFS + bool + config VIRTIO_9P bool default y depends on VIRTFS && VIRTIO select FSDEV_9P + select 9PFS diff --git a/hw/9pfs/Makefile.objs b/hw/9pfs/Makefile.objs deleted file mode 100644 index 70ded6fd8f..0000000000 --- a/hw/9pfs/Makefile.objs +++ /dev/null @@ -1,9 +0,0 @@ -common-obj-y = 9p.o 9p-util.o -common-obj-y += 9p-local.o 9p-xattr.o -common-obj-y += 9p-xattr-user.o 9p-posix-acl.o -common-obj-y += coth.o cofs.o codir.o cofile.o -common-obj-y += coxattr.o 9p-synth.o -common-obj-y += 9p-proxy.o - -common-obj-$(CONFIG_XEN) += xen-9p-backend.o -obj-$(CONFIG_VIRTIO_9P) += virtio-9p-device.o diff --git a/hw/9pfs/meson.build b/hw/9pfs/meson.build new file mode 100644 index 0000000000..cc09426212 --- /dev/null +++ b/hw/9pfs/meson.build @@ -0,0 +1,20 @@ +fs_ss = ss.source_set() +fs_ss.add(files( + '9p-local.c', + '9p-posix-acl.c', + '9p-proxy.c', + '9p-synth.c', + '9p-util.c', + '9p-xattr-user.c', + '9p-xattr.c', + '9p.c', + 'codir.c', + 'cofile.c', + 'cofs.c', + 'coth.c', + 'coxattr.c', +)) +fs_ss.add(when: 'CONFIG_XEN', if_true: files('xen-9p-backend.c')) +softmmu_ss.add_all(when: 'CONFIG_9PFS', if_true: fs_ss) + +specific_ss.add(when: 'CONFIG_VIRTIO_9P', if_true: files('virtio-9p-device.c')) diff --git a/hw/Makefile.objs b/hw/Makefile.objs deleted file mode 100644 index ebae00af6e..0000000000 --- a/hw/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -ifeq ($(CONFIG_SOFTMMU), y) -devices-dirs-$(call lor,$(CONFIG_VIRTIO_9P),$(call land,$(CONFIG_VIRTFS),$(CONFIG_XEN))) += 9pfs/ -endif - -common-obj-y += $(devices-dirs-y) -common-obj-m += display/ -common-obj-m += usb/ -obj-y += $(devices-dirs-y) diff --git a/hw/meson.build b/hw/meson.build index 55ca2b2b61..ba8763cad8 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -1,3 +1,4 @@ +subdir('9pfs') subdir('acpi') subdir('adc') subdir('audio') -- cgit v1.2.3-55-g7522 From 2c44220d055d12142f27cf513848f17d6007ae35 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sat, 17 Aug 2019 13:55:58 +0400 Subject: meson: convert hw/arch* Each architecture's sourceset is placed in an hw_arch dictionary, and picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 7 ---- hw/alpha/Makefile.objs | 1 - hw/alpha/meson.build | 8 +++++ hw/arm/Makefile.objs | 56 ------------------------------- hw/arm/meson.build | 59 +++++++++++++++++++++++++++++++++ hw/avr/Makefile.objs | 3 -- hw/avr/meson.build | 6 ++++ hw/cris/Makefile.objs | 2 -- hw/cris/meson.build | 5 +++ hw/hppa/Makefile.objs | 1 - hw/hppa/meson.build | 4 +++ hw/i386/Makefile.objs | 20 ------------ hw/i386/kvm/Makefile.objs | 5 --- hw/i386/kvm/meson.build | 8 +++++ hw/i386/meson.build | 32 ++++++++++++++++++ hw/i386/xen/Makefile.objs | 1 - hw/i386/xen/meson.build | 7 ++++ hw/lm32/Makefile.objs | 3 -- hw/lm32/meson.build | 6 ++++ hw/m68k/Makefile.objs | 4 --- hw/m68k/meson.build | 7 ++++ hw/meson.build | 25 ++++++++++++++ hw/microblaze/Makefile.objs | 4 --- hw/microblaze/meson.build | 7 ++++ hw/mips/Makefile.objs | 8 ----- hw/mips/meson.build | 11 +++++++ hw/moxie/Makefile.objs | 2 -- hw/moxie/meson.build | 4 +++ hw/nios2/Makefile.objs | 3 -- hw/nios2/meson.build | 6 ++++ hw/openrisc/Makefile.objs | 2 -- hw/openrisc/meson.build | 5 +++ hw/ppc/Makefile.objs | 35 -------------------- hw/ppc/meson.build | 80 +++++++++++++++++++++++++++++++++++++++++++++ hw/riscv/Makefile.objs | 16 --------- hw/riscv/meson.build | 19 +++++++++++ hw/rx/Makefile.objs | 2 -- hw/rx/meson.build | 5 +++ hw/s390x/Makefile.objs | 37 --------------------- hw/s390x/meson.build | 46 ++++++++++++++++++++++++++ hw/sh4/Makefile.objs | 4 --- hw/sh4/meson.build | 10 ++++++ hw/sparc/Makefile.objs | 3 -- hw/sparc/meson.build | 6 ++++ hw/sparc64/Makefile.objs | 4 --- hw/sparc64/meson.build | 6 ++++ hw/tricore/Makefile.objs | 1 - hw/tricore/meson.build | 4 +++ hw/unicore32/Makefile.objs | 4 --- hw/unicore32/meson.build | 5 +++ hw/xenpv/Makefile.objs | 2 -- hw/xenpv/meson.build | 3 ++ hw/xtensa/Makefile.objs | 6 ---- hw/xtensa/meson.build | 11 +++++++ meson.build | 4 +++ 55 files changed, 399 insertions(+), 236 deletions(-) delete mode 100644 hw/alpha/Makefile.objs create mode 100644 hw/alpha/meson.build delete mode 100644 hw/arm/Makefile.objs create mode 100644 hw/arm/meson.build delete mode 100644 hw/avr/Makefile.objs create mode 100644 hw/avr/meson.build delete mode 100644 hw/cris/Makefile.objs create mode 100644 hw/cris/meson.build delete mode 100644 hw/hppa/Makefile.objs create mode 100644 hw/hppa/meson.build delete mode 100644 hw/i386/Makefile.objs delete mode 100644 hw/i386/kvm/Makefile.objs create mode 100644 hw/i386/kvm/meson.build create mode 100644 hw/i386/meson.build delete mode 100644 hw/i386/xen/Makefile.objs create mode 100644 hw/i386/xen/meson.build delete mode 100644 hw/lm32/Makefile.objs create mode 100644 hw/lm32/meson.build delete mode 100644 hw/m68k/Makefile.objs create mode 100644 hw/m68k/meson.build delete mode 100644 hw/microblaze/Makefile.objs create mode 100644 hw/microblaze/meson.build delete mode 100644 hw/mips/Makefile.objs create mode 100644 hw/mips/meson.build delete mode 100644 hw/moxie/Makefile.objs create mode 100644 hw/moxie/meson.build delete mode 100644 hw/nios2/Makefile.objs create mode 100644 hw/nios2/meson.build delete mode 100644 hw/openrisc/Makefile.objs create mode 100644 hw/openrisc/meson.build delete mode 100644 hw/ppc/Makefile.objs create mode 100644 hw/ppc/meson.build delete mode 100644 hw/riscv/Makefile.objs create mode 100644 hw/riscv/meson.build delete mode 100644 hw/rx/Makefile.objs create mode 100644 hw/rx/meson.build delete mode 100644 hw/s390x/Makefile.objs create mode 100644 hw/s390x/meson.build delete mode 100644 hw/sh4/Makefile.objs create mode 100644 hw/sh4/meson.build delete mode 100644 hw/sparc/Makefile.objs create mode 100644 hw/sparc/meson.build delete mode 100644 hw/sparc64/Makefile.objs create mode 100644 hw/sparc64/meson.build delete mode 100644 hw/tricore/Makefile.objs create mode 100644 hw/tricore/meson.build delete mode 100644 hw/unicore32/Makefile.objs create mode 100644 hw/unicore32/meson.build delete mode 100644 hw/xenpv/Makefile.objs create mode 100644 hw/xenpv/meson.build delete mode 100644 hw/xtensa/Makefile.objs create mode 100644 hw/xtensa/meson.build diff --git a/Makefile.target b/Makefile.target index c95e0deb79..28cefba1de 100644 --- a/Makefile.target +++ b/Makefile.target @@ -170,13 +170,6 @@ LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) LIBS := $(LIBS) $(VIRGL_LIBS) -# Hardware support -ifeq ($(TARGET_NAME), sparc64) -obj-y += hw/sparc64/ -else -obj-y += hw/$(TARGET_BASE_ARCH)/ -endif - generated-files-y += hmp-commands.h hmp-commands-info.h endif # CONFIG_SOFTMMU diff --git a/hw/alpha/Makefile.objs b/hw/alpha/Makefile.objs deleted file mode 100644 index 62fdf3edec..0000000000 --- a/hw/alpha/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_DP264) += dp264.o pci.o typhoon.o diff --git a/hw/alpha/meson.build b/hw/alpha/meson.build new file mode 100644 index 0000000000..81ca215777 --- /dev/null +++ b/hw/alpha/meson.build @@ -0,0 +1,8 @@ +alpha_ss = ss.source_set() +alpha_ss.add(when: 'CONFIG_DP264', if_true: files( + 'dp264.c', + 'pci.c', + 'typhoon.c', +)) + +hw_arch += {'alpha': alpha_ss} diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs deleted file mode 100644 index 534a6a119e..0000000000 --- a/hw/arm/Makefile.objs +++ /dev/null @@ -1,56 +0,0 @@ -obj-y += boot.o -obj-$(CONFIG_PLATFORM_BUS) += sysbus-fdt.o -obj-$(CONFIG_ARM_VIRT) += virt.o -obj-$(CONFIG_ACPI) += virt-acpi-build.o -obj-$(CONFIG_DIGIC) += digic_boards.o -obj-$(CONFIG_EXYNOS4) += exynos4_boards.o -obj-$(CONFIG_EMCRAFT_SF2) += msf2-som.o -obj-$(CONFIG_HIGHBANK) += highbank.o -obj-$(CONFIG_INTEGRATOR) += integratorcp.o -obj-$(CONFIG_MAINSTONE) += mainstone.o -obj-$(CONFIG_MICROBIT) += microbit.o -obj-$(CONFIG_MUSICPAL) += musicpal.o -obj-$(CONFIG_NETDUINO2) += netduino2.o -obj-$(CONFIG_NETDUINOPLUS2) += netduinoplus2.o -obj-$(CONFIG_NSERIES) += nseries.o -obj-$(CONFIG_SX1) += omap_sx1.o -obj-$(CONFIG_CHEETAH) += palm.o -obj-$(CONFIG_GUMSTIX) += gumstix.o -obj-$(CONFIG_SPITZ) += spitz.o -obj-$(CONFIG_TOSA) += tosa.o -obj-$(CONFIG_Z2) += z2.o -obj-$(CONFIG_REALVIEW) += realview.o -obj-$(CONFIG_SBSA_REF) += sbsa-ref.o -obj-$(CONFIG_STELLARIS) += stellaris.o -obj-$(CONFIG_COLLIE) += collie.o -obj-$(CONFIG_VERSATILE) += versatilepb.o -obj-$(CONFIG_VEXPRESS) += vexpress.o -obj-$(CONFIG_ZYNQ) += xilinx_zynq.o -obj-$(CONFIG_SABRELITE) += sabrelite.o - -obj-$(CONFIG_ARM_V7M) += armv7m.o -obj-$(CONFIG_EXYNOS4) += exynos4210.o -obj-$(CONFIG_PXA2XX) += pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o -obj-$(CONFIG_DIGIC) += digic.o -obj-$(CONFIG_OMAP) += omap1.o omap2.o -obj-$(CONFIG_STRONGARM) += strongarm.o -obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o -obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3.o orangepi.o -obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o -obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o -obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o -obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o -obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o -obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o -obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o -obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o aspeed_ast2600.o -obj-$(CONFIG_MPS2) += mps2.o -obj-$(CONFIG_MPS2) += mps2-tz.o -obj-$(CONFIG_MSF2) += msf2-soc.o -obj-$(CONFIG_MUSCA) += musca.o -obj-$(CONFIG_ARMSSE) += armsse.o -obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o -obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o -obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o -obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o diff --git a/hw/arm/meson.build b/hw/arm/meson.build new file mode 100644 index 0000000000..1ae5e17eeb --- /dev/null +++ b/hw/arm/meson.build @@ -0,0 +1,59 @@ +arm_ss = ss.source_set() +arm_ss.add(files('boot.c')) +arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c')) +arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) +arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) +arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) +arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) +arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) +arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) +arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) +arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) +arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) +arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) +arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) +arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) +arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) +arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) +arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) +arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) +arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) +arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) +arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) +arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) +arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) +arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) +arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) +arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) +arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) +arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) + +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) +arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) +arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) +arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) +arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) +arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) +arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) +arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) +arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) +arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) +arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) +arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) +arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c')) +arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) +arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) +arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) +arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) +arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c', 'smmuv3.c')) +arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) +arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) + +hw_arch += {'arm': arm_ss} diff --git a/hw/avr/Makefile.objs b/hw/avr/Makefile.objs deleted file mode 100644 index 4dca064bfc..0000000000 --- a/hw/avr/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += boot.o -obj-$(CONFIG_AVR_ATMEGA_MCU) += atmega.o -obj-$(CONFIG_ARDUINO) += arduino.o diff --git a/hw/avr/meson.build b/hw/avr/meson.build new file mode 100644 index 0000000000..46d53fb17e --- /dev/null +++ b/hw/avr/meson.build @@ -0,0 +1,6 @@ +avr_ss = ss.source_set() +avr_ss.add(files('boot.c')) +avr_ss.add(when: 'CONFIG_AVR_ATMEGA_MCU', if_true: files('atmega.c')) +avr_ss.add(when: 'CONFIG_ARDUINO', if_true: files('arduino.c')) + +hw_arch += {'avr': avr_ss} diff --git a/hw/cris/Makefile.objs b/hw/cris/Makefile.objs deleted file mode 100644 index a4a27b3a13..0000000000 --- a/hw/cris/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += boot.o -obj-$(CONFIG_AXIS) += axis_dev88.o diff --git a/hw/cris/meson.build b/hw/cris/meson.build new file mode 100644 index 0000000000..dc808a4e0f --- /dev/null +++ b/hw/cris/meson.build @@ -0,0 +1,5 @@ +cris_ss = ss.source_set() +cris_ss.add(files('boot.c')) +cris_ss.add(when: 'CONFIG_AXIS', if_true: files('axis_dev88.c')) + +hw_arch += {'cris': cris_ss} diff --git a/hw/hppa/Makefile.objs b/hw/hppa/Makefile.objs deleted file mode 100644 index eac3467d8a..0000000000 --- a/hw/hppa/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_DINO) += pci.o machine.o dino.o lasi.o diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build new file mode 100644 index 0000000000..1deae83aee --- /dev/null +++ b/hw/hppa/meson.build @@ -0,0 +1,4 @@ +hppa_ss = ss.source_set() +hppa_ss.add(when: 'CONFIG_DINO', if_true: files('pci.c', 'machine.c', 'dino.c', 'lasi.c')) + +hw_arch += {'hppa': hppa_ss} diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs deleted file mode 100644 index 6abc74551a..0000000000 --- a/hw/i386/Makefile.objs +++ /dev/null @@ -1,20 +0,0 @@ -obj-$(CONFIG_KVM) += kvm/ -obj-y += e820_memory_layout.o multiboot.o -obj-y += x86.o -obj-$(CONFIG_PC) += pc.o pc_sysfw.o -obj-$(CONFIG_I440FX) += pc_piix.o -obj-$(CONFIG_Q35) += pc_q35.o -obj-$(CONFIG_MICROVM) += microvm.o -obj-y += fw_cfg.o -obj-$(CONFIG_X86_IOMMU) += x86-iommu.o -obj-$(call lnot,$(CONFIG_X86_IOMMU)) += x86-iommu-stub.o -obj-$(CONFIG_VTD) += intel_iommu.o -obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o -obj-$(CONFIG_XEN) += ../xenpv/ xen/ -obj-$(CONFIG_VMPORT) += vmport.o -obj-$(CONFIG_VMMOUSE) += vmmouse.o -obj-$(CONFIG_PC) += port92.o - -obj-y += kvmvapic.o -obj-$(CONFIG_ACPI) += acpi-common.o -obj-$(CONFIG_PC) += acpi-build.o diff --git a/hw/i386/kvm/Makefile.objs b/hw/i386/kvm/Makefile.objs deleted file mode 100644 index 0c8d5f2dee..0000000000 --- a/hw/i386/kvm/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += clock.o -obj-$(CONFIG_APIC) += apic.o -obj-$(CONFIG_IOAPIC) += ioapic.o -obj-$(CONFIG_I8254) += i8254.o -obj-$(CONFIG_I8259) += i8259.o diff --git a/hw/i386/kvm/meson.build b/hw/i386/kvm/meson.build new file mode 100644 index 0000000000..95467f1ded --- /dev/null +++ b/hw/i386/kvm/meson.build @@ -0,0 +1,8 @@ +i386_kvm_ss = ss.source_set() +i386_kvm_ss.add(files('clock.c')) +i386_kvm_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c')) +i386_kvm_ss.add(when: 'CONFIG_I8254', if_true: files('i8254.c')) +i386_kvm_ss.add(when: 'CONFIG_I8259', if_true: files('i8259.c')) +i386_kvm_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) + +i386_ss.add_all(when: 'CONFIG_KVM', if_true: i386_kvm_ss) diff --git a/hw/i386/meson.build b/hw/i386/meson.build new file mode 100644 index 0000000000..63918fbe22 --- /dev/null +++ b/hw/i386/meson.build @@ -0,0 +1,32 @@ +i386_ss = ss.source_set() +i386_ss.add(files( + 'fw_cfg.c', + 'kvmvapic.c', + 'e820_memory_layout.c', + 'multiboot.c', + 'x86.c', +)) + +i386_ss.add(when: 'CONFIG_X86_IOMMU', if_true: files('x86-iommu.c'), + if_false: files('x86-iommu-stub.c')) +i386_ss.add(when: 'CONFIG_AMD_IOMMU', if_true: files('amd_iommu.c')) +i386_ss.add(when: 'CONFIG_I440FX', if_true: files('pc_piix.c')) +i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('microvm.c')) +i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c')) +i386_ss.add(when: 'CONFIG_VMMOUSE', if_true: files('vmmouse.c')) +i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) +i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) + +i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) +i386_ss.add(when: 'CONFIG_PC', if_true: files( + 'pc.c', + 'pc_sysfw.c', + 'acpi-build.c', + 'port92.c')) + +subdir('kvm') +subdir('xen') + +i386_ss.add_all(xenpv_ss) + +hw_arch += {'i386': i386_ss} diff --git a/hw/i386/xen/Makefile.objs b/hw/i386/xen/Makefile.objs deleted file mode 100644 index be9d10cf2a..0000000000 --- a/hw/i386/xen/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-y += xen_platform.o xen_apic.o xen_pvdevice.o xen-hvm.o xen-mapcache.o diff --git a/hw/i386/xen/meson.build b/hw/i386/xen/meson.build new file mode 100644 index 0000000000..be84130300 --- /dev/null +++ b/hw/i386/xen/meson.build @@ -0,0 +1,7 @@ +i386_ss.add(when: 'CONFIG_XEN', if_true: files( + 'xen-hvm.c', + 'xen-mapcache.c', + 'xen_apic.c', + 'xen_platform.c', + 'xen_pvdevice.c', +)) diff --git a/hw/lm32/Makefile.objs b/hw/lm32/Makefile.objs deleted file mode 100644 index c3941866c7..0000000000 --- a/hw/lm32/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -# LM32 boards -obj-$(CONFIG_LM32) += lm32_boards.o -obj-$(CONFIG_MILKYMIST) += milkymist.o diff --git a/hw/lm32/meson.build b/hw/lm32/meson.build new file mode 100644 index 0000000000..8caf0a727f --- /dev/null +++ b/hw/lm32/meson.build @@ -0,0 +1,6 @@ +lm32_ss = ss.source_set() +# LM32 boards +lm32_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_boards.c')) +lm32_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist.c')) + +hw_arch += {'lm32': lm32_ss} diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs deleted file mode 100644 index b2c9e5ab12..0000000000 --- a/hw/m68k/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_AN5206) += an5206.o mcf5206.o -obj-$(CONFIG_MCF5208) += mcf5208.o mcf_intc.o -obj-$(CONFIG_NEXTCUBE) += next-kbd.o next-cube.o -obj-$(CONFIG_Q800) += q800.o diff --git a/hw/m68k/meson.build b/hw/m68k/meson.build new file mode 100644 index 0000000000..ca0044c652 --- /dev/null +++ b/hw/m68k/meson.build @@ -0,0 +1,7 @@ +m68k_ss = ss.source_set() +m68k_ss.add(when: 'CONFIG_AN5206', if_true: files('an5206.c', 'mcf5206.c')) +m68k_ss.add(when: 'CONFIG_MCF5208', if_true: files('mcf5208.c', 'mcf_intc.c')) +m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cube.c')) +m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c')) + +hw_arch += {'m68k': m68k_ss} diff --git a/hw/meson.build b/hw/meson.build index ba8763cad8..010de7219c 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -40,3 +40,28 @@ subdir('vfio') subdir('virtio') subdir('watchdog') subdir('xen') +subdir('xenpv') + +subdir('alpha') +subdir('arm') +subdir('avr') +subdir('cris') +subdir('hppa') +subdir('i386') +subdir('lm32') +subdir('m68k') +subdir('microblaze') +subdir('mips') +subdir('moxie') +subdir('nios2') +subdir('openrisc') +subdir('ppc') +subdir('riscv') +subdir('rx') +subdir('s390x') +subdir('sh4') +subdir('sparc') +subdir('sparc64') +subdir('tricore') +subdir('unicore32') +subdir('xtensa') diff --git a/hw/microblaze/Makefile.objs b/hw/microblaze/Makefile.objs deleted file mode 100644 index 8595a62f6c..0000000000 --- a/hw/microblaze/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_PETALOGIX_S3ADSP1800) += petalogix_s3adsp1800_mmu.o -obj-$(CONFIG_PETALOGIX_ML605) += petalogix_ml605_mmu.o -obj-$(CONFIG_XLNX_ZYNQMP_PMU) += xlnx-zynqmp-pmu.o -obj-y += boot.o diff --git a/hw/microblaze/meson.build b/hw/microblaze/meson.build new file mode 100644 index 0000000000..bb9e4eb8f4 --- /dev/null +++ b/hw/microblaze/meson.build @@ -0,0 +1,7 @@ +microblaze_ss = ss.source_set() +microblaze_ss.add(files('boot.c')) +microblaze_ss.add(when: 'CONFIG_PETALOGIX_S3ADSP1800', if_true: files('petalogix_s3adsp1800_mmu.c')) +microblaze_ss.add(when: 'CONFIG_PETALOGIX_ML605', if_true: files('petalogix_ml605_mmu.c')) +microblaze_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-zynqmp-pmu.c')) + +hw_arch += {'microblaze': microblaze_ss} diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs deleted file mode 100644 index 739e2b7b40..0000000000 --- a/hw/mips/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -obj-y += addr.o mips_int.o -obj-$(CONFIG_R4K) += r4k.o -obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o -obj-$(CONFIG_MIPSSIM) += mipssim.o -obj-$(CONFIG_JAZZ) += jazz.o -obj-$(CONFIG_FULOONG) += fuloong2e.o -obj-$(CONFIG_MIPS_CPS) += cps.o -obj-$(CONFIG_MIPS_BOSTON) += boston.o diff --git a/hw/mips/meson.build b/hw/mips/meson.build new file mode 100644 index 0000000000..6ac9dc4cff --- /dev/null +++ b/hw/mips/meson.build @@ -0,0 +1,11 @@ +mips_ss = ss.source_set() +mips_ss.add(files('addr.c', 'mips_int.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) +mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) +mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: files('boston.c')) +mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) +mips_ss.add(when: 'CONFIG_R4K', if_true: files('r4k.c')) + +hw_arch += {'mips': mips_ss} diff --git a/hw/moxie/Makefile.objs b/hw/moxie/Makefile.objs deleted file mode 100644 index ddbf300f54..0000000000 --- a/hw/moxie/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -# moxie boards -obj-$(CONFIG_MOXIESIM) += moxiesim.o diff --git a/hw/moxie/meson.build b/hw/moxie/meson.build new file mode 100644 index 0000000000..05a7c2e00f --- /dev/null +++ b/hw/moxie/meson.build @@ -0,0 +1,4 @@ +moxie_ss = ss.source_set() +moxie_ss.add(when: 'CONFIG_MOXIESIM', if_true: files('moxiesim.c')) + +hw_arch += {'moxie': moxie_ss} diff --git a/hw/nios2/Makefile.objs b/hw/nios2/Makefile.objs deleted file mode 100644 index 3e017981ba..0000000000 --- a/hw/nios2/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y = boot.o cpu_pic.o -obj-$(CONFIG_NIOS2_10M50) += 10m50_devboard.o -obj-$(CONFIG_NIOS2_GENERIC_NOMMU) += generic_nommu.o diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build new file mode 100644 index 0000000000..dd66ebb32f --- /dev/null +++ b/hw/nios2/meson.build @@ -0,0 +1,6 @@ +nios2_ss = ss.source_set() +nios2_ss.add(files('boot.c', 'cpu_pic.c')) +nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c')) +nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_nommu.c')) + +hw_arch += {'nios2': nios2_ss} diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs deleted file mode 100644 index aa04de7f5a..0000000000 --- a/hw/openrisc/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y = pic_cpu.o cputimer.o -obj-$(CONFIG_OR1K_SIM) += openrisc_sim.o diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build new file mode 100644 index 0000000000..57c42558e1 --- /dev/null +++ b/hw/openrisc/meson.build @@ -0,0 +1,5 @@ +openrisc_ss = ss.source_set() +openrisc_ss.add(files('pic_cpu.c', 'cputimer.c')) +openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c')) + +hw_arch += {'openrisc': openrisc_ss} diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs deleted file mode 100644 index c3d3cc56eb..0000000000 --- a/hw/ppc/Makefile.objs +++ /dev/null @@ -1,35 +0,0 @@ -# shared objects -obj-y += ppc.o ppc_booke.o -obj-$(CONFIG_FDT_PPC) += fdt.o -obj-$(CONFIG_FW_CFG_PPC) += fw_cfg.o -# IBM pSeries (sPAPR) -obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o -obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o -obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o -obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o -obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o spapr_nvdimm.o -obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o -obj-$(call land,$(CONFIG_PSERIES),$(CONFIG_LINUX)) += spapr_pci_vfio.o spapr_pci_nvlink2.o -# IBM PowerNV -obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o -obj-$(CONFIG_POWERNV) += pnv_homer.o pnv_pnor.o - -obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o -# PowerPC 4xx boards -obj-$(CONFIG_PPC405) += ppc405_boards.o ppc405_uc.o -obj-$(CONFIG_PPC440) += ppc440_bamboo.o ppc440_pcix.o ppc440_uc.o -obj-$(CONFIG_PPC4XX) += ppc4xx_pci.o ppc4xx_devs.o -obj-$(CONFIG_SAM460EX) += sam460ex.o -# PReP -obj-$(CONFIG_PREP) += prep.o -obj-$(CONFIG_PREP) += prep_systemio.o -obj-${CONFIG_RS6000_MC} += rs6000_mc.o -# OldWorld PowerMac -obj-$(CONFIG_MAC_OLDWORLD) += mac_oldworld.o -# NewWorld PowerMac -obj-$(CONFIG_MAC_NEWWORLD) += mac_newworld.o -# e500 -obj-$(CONFIG_E500) += e500.o mpc8544ds.o e500plat.o -obj-$(CONFIG_E500) += mpc8544_guts.o ppce500_spin.o -# PowerPC 440 Xilinx ML507 reference board. -obj-$(CONFIG_VIRTEX) += virtex_ml507.o diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build new file mode 100644 index 0000000000..918969b320 --- /dev/null +++ b/hw/ppc/meson.build @@ -0,0 +1,80 @@ +ppc_ss = ss.source_set() +ppc_ss.add(files( + 'ppc.c', + 'ppc_booke.c', +)) +ppc_ss.add(when: 'CONFIG_FDT_PPC', if_true: [files( + 'fdt.c', +), fdt]) +ppc_ss.add(when: 'CONFIG_FW_CFG_PPC', if_true: files('fw_cfg.c')) + +# IBM pSeries (sPAPR) +ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files( + 'spapr.c', + 'spapr_caps.c', + 'spapr_vio.c', + 'spapr_events.c', + 'spapr_hcall.c', + 'spapr_iommu.c', + 'spapr_rtas.c', + 'spapr_pci.c', + 'spapr_rtc.c', + 'spapr_drc.c', + 'spapr_cpu_core.c', + 'spapr_ovec.c', + 'spapr_irq.c', + 'spapr_tpm_proxy.c', + 'spapr_nvdimm.c', + 'spapr_rtas_ddw.c' +)) +ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c')) +ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_LINUX'], if_true: files( + 'spapr_pci_vfio.c', + 'spapr_pci_nvlink2.c' +)) + +# IBM PowerNV +ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( + 'pnv.c', + 'pnv_xscom.c', + 'pnv_core.c', + 'pnv_lpc.c', + 'pnv_psi.c', + 'pnv_occ.c', + 'pnv_bmc.c', + 'pnv_homer.c', + 'pnv_pnor.c', +)) +# PowerPC 4xx boards +ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( + 'ppc405_boards.c', + 'ppc405_uc.c')) +ppc_ss.add(when: 'CONFIG_PPC440', if_true: files( + 'ppc440_bamboo.c', + 'ppc440_pcix.c', 'ppc440_uc.c')) +ppc_ss.add(when: 'CONFIG_PPC4XX', if_true: files( + 'ppc4xx_pci.c', + 'ppc4xx_devs.c')) +ppc_ss.add(when: 'CONFIG_SAM460EX', if_true: files('sam460ex.c')) +# PReP +ppc_ss.add(when: 'CONFIG_PREP', if_true: files('prep.c')) +ppc_ss.add(when: 'CONFIG_PREP', if_true: files('prep_systemio.c')) +ppc_ss.add(when: 'CONFIG_RS6000_MC', if_true: files('rs6000_mc.c')) +# OldWorld PowerMac +ppc_ss.add(when: 'CONFIG_MAC_OLDWORLD', if_true: files('mac_oldworld.c')) +# NewWorld PowerMac +ppc_ss.add(when: 'CONFIG_MAC_NEWWORLD', if_true: files('mac_newworld.c')) +# e500 +ppc_ss.add(when: 'CONFIG_E500', if_true: files( + 'e500.c', + 'mpc8544ds.c', + 'e500plat.c' +)) +ppc_ss.add(when: 'CONFIG_E500', if_true: files( + 'mpc8544_guts.c', + 'ppce500_spin.c' +)) +# PowerPC 440 Xilinx ML507 reference board. +ppc_ss.add(when: 'CONFIG_VIRTEX', if_true: files('virtex_ml507.c')) + +hw_arch += {'ppc': ppc_ss} diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs deleted file mode 100644 index 57cc708f5d..0000000000 --- a/hw/riscv/Makefile.objs +++ /dev/null @@ -1,16 +0,0 @@ -obj-y += boot.o -obj-$(CONFIG_SPIKE) += riscv_htif.o -obj-$(CONFIG_HART) += riscv_hart.o -obj-$(CONFIG_OPENTITAN) += opentitan.o -obj-$(CONFIG_SIFIVE_E) += sifive_e.o -obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o -obj-$(CONFIG_SIFIVE) += sifive_clint.o -obj-$(CONFIG_SIFIVE) += sifive_gpio.o -obj-$(CONFIG_SIFIVE) += sifive_plic.o -obj-$(CONFIG_SIFIVE) += sifive_test.o -obj-$(CONFIG_SIFIVE_U) += sifive_u.o -obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o -obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o -obj-$(CONFIG_SIFIVE) += sifive_uart.o -obj-$(CONFIG_SPIKE) += spike.o -obj-$(CONFIG_RISCV_VIRT) += virt.o diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build new file mode 100644 index 0000000000..2de8e5a2fe --- /dev/null +++ b/hw/riscv/meson.build @@ -0,0 +1,19 @@ +riscv_ss = ss.source_set() +riscv_ss.add(files('boot.c')) +riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) +riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) +riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) + +hw_arch += {'riscv': riscv_ss} diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs deleted file mode 100644 index 4ef6b9e5b1..0000000000 --- a/hw/rx/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_RX62N_MCU) += rx62n.o -obj-$(CONFIG_RX_GDBSIM) += rx-gdbsim.o diff --git a/hw/rx/meson.build b/hw/rx/meson.build new file mode 100644 index 0000000000..d223512a78 --- /dev/null +++ b/hw/rx/meson.build @@ -0,0 +1,5 @@ +rx_ss = ss.source_set() +rx_ss.add(when: 'CONFIG_RX_GDBSIM', if_true: files('rx-gdbsim.c')) +rx_ss.add(when: 'CONFIG_RX62N_MCU', if_true: files('rx62n.c')) + +hw_arch += {'rx': rx_ss} diff --git a/hw/s390x/Makefile.objs b/hw/s390x/Makefile.objs deleted file mode 100644 index a46a1c7894..0000000000 --- a/hw/s390x/Makefile.objs +++ /dev/null @@ -1,37 +0,0 @@ -obj-y += s390-virtio-hcall.o -obj-y += sclp.o -obj-y += event-facility.o -obj-y += sclpquiesce.o -obj-y += sclpcpu.o -obj-y += ipl.o -obj-y += css.o -obj-$(CONFIG_S390_CCW_VIRTIO) += s390-virtio-ccw.o -obj-$(CONFIG_TERMINAL3270) += 3270-ccw.o -ifeq ($(CONFIG_VIRTIO_CCW),y) -obj-y += virtio-ccw.o -obj-$(CONFIG_VIRTIO_SERIAL) += virtio-ccw-serial.o -obj-$(CONFIG_VIRTIO_BALLOON) += virtio-ccw-balloon.o -obj-$(CONFIG_VIRTIO_SCSI) += virtio-ccw-scsi.o -obj-$(CONFIG_VIRTIO_RNG) += virtio-ccw-rng.o -obj-$(CONFIG_VIRTIO_CRYPTO) += virtio-ccw-crypto.o -obj-$(CONFIG_VIRTIO_GPU) += virtio-ccw-gpu.o -obj-$(CONFIG_VIRTIO_INPUT) += virtio-ccw-input.o -obj-$(CONFIG_VIRTIO_NET) += virtio-ccw-net.o -obj-$(CONFIG_VIRTIO_BLK) += virtio-ccw-blk.o -obj-$(call land,$(CONFIG_VIRTIO_9P),$(CONFIG_VIRTFS)) += virtio-ccw-9p.o -obj-$(CONFIG_VHOST_VSOCK) += vhost-vsock-ccw.o -endif -obj-y += css-bridge.o -obj-y += ccw-device.o -obj-y += s390-pci-bus.o s390-pci-inst.o -obj-y += s390-skeys.o -obj-y += s390-stattrib.o -obj-y += tod.o -obj-y += tod-qemu.o -obj-$(CONFIG_KVM) += tod-kvm.o -obj-$(CONFIG_KVM) += s390-skeys-kvm.o -obj-$(CONFIG_KVM) += s390-stattrib-kvm.o -obj-$(CONFIG_KVM) += pv.o -obj-y += s390-ccw.o -obj-y += ap-device.o -obj-y += ap-bridge.o diff --git a/hw/s390x/meson.build b/hw/s390x/meson.build new file mode 100644 index 0000000000..b63782d87a --- /dev/null +++ b/hw/s390x/meson.build @@ -0,0 +1,46 @@ +s390x_ss = ss.source_set() +s390x_ss.add(files( + 'ap-bridge.c', + 'ap-device.c', + 'ccw-device.c', + 'css-bridge.c', + 'css.c', + 'event-facility.c', + 'ipl.c', + 's390-ccw.c', + 's390-pci-bus.c', + 's390-pci-inst.c', + 's390-skeys.c', + 's390-stattrib.c', + 's390-virtio-hcall.c', + 'sclp.c', + 'sclpcpu.c', + 'sclpquiesce.c', + 'tod-qemu.c', + 'tod.c', +)) +s390x_ss.add(when: 'CONFIG_KVM', if_true: files( + 'tod-kvm.c', + 's390-skeys-kvm.c', + 's390-stattrib-kvm.c', + 'pv.c', +)) +s390x_ss.add(when: 'CONFIG_S390_CCW_VIRTIO', if_true: files('s390-virtio-ccw.c')) +s390x_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('3270-ccw.c')) + +virtio_ss = ss.source_set() +virtio_ss.add(files('virtio-ccw.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_BALLOON', if_true: files('virtio-ccw-balloon.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-ccw-blk.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_CRYPTO', if_true: files('virtio-ccw-crypto.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_GPU', if_true: files('virtio-ccw-gpu.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_INPUT', if_true: files('virtio-ccw-input.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('virtio-ccw-net.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_RNG', if_true: files('virtio-ccw-rng.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_SCSI', if_true: files('virtio-ccw-scsi.c')) +virtio_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-ccw-serial.c')) +virtio_ss.add(when: ['CONFIG_VIRTIO_9P', 'CONFIG_VIRTFS'], if_true: files('virtio-ccw-blk.c')) +virtio_ss.add(when: 'CONFIG_VHOST_VSOCK', if_true: files('vhost-vsock-ccw.c')) +s390x_ss.add_all(when: 'CONFIG_VIRTIO_CCW', if_true: virtio_ss) + +hw_arch += {'s390x': s390x_ss} diff --git a/hw/sh4/Makefile.objs b/hw/sh4/Makefile.objs deleted file mode 100644 index 2a707f9473..0000000000 --- a/hw/sh4/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += sh7750.o sh7750_regnames.o -obj-y += sh_pci.o -obj-$(CONFIG_R2D) += r2d.o -obj-$(CONFIG_SHIX) += shix.o diff --git a/hw/sh4/meson.build b/hw/sh4/meson.build new file mode 100644 index 0000000000..303c0f4287 --- /dev/null +++ b/hw/sh4/meson.build @@ -0,0 +1,10 @@ +sh4_ss = ss.source_set() +sh4_ss.add(files( + 'sh7750.c', + 'sh7750_regnames.c', + 'sh_pci.c' +)) +sh4_ss.add(when: 'CONFIG_R2D', if_true: files('r2d.c')) +sh4_ss.add(when: 'CONFIG_SHIX', if_true: files('shix.c')) + +hw_arch += {'sh4': sh4_ss} diff --git a/hw/sparc/Makefile.objs b/hw/sparc/Makefile.objs deleted file mode 100644 index d57e33f83e..0000000000 --- a/hw/sparc/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-$(CONFIG_SUN4M) += sun4m_iommu.o -obj-$(CONFIG_SUN4M) += sun4m.o -obj-$(CONFIG_LEON3) += leon3.o diff --git a/hw/sparc/meson.build b/hw/sparc/meson.build new file mode 100644 index 0000000000..19c442c90d --- /dev/null +++ b/hw/sparc/meson.build @@ -0,0 +1,6 @@ +sparc_ss = ss.source_set() +sparc_ss.add(when: 'CONFIG_LEON3', if_true: files('leon3.c')) +sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m.c')) +sparc_ss.add(when: 'CONFIG_SUN4M', if_true: files('sun4m_iommu.c')) + +hw_arch += {'sparc': sparc_ss} diff --git a/hw/sparc64/Makefile.objs b/hw/sparc64/Makefile.objs deleted file mode 100644 index af0525c1a2..0000000000 --- a/hw/sparc64/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += sparc64.o -obj-$(CONFIG_SUN4U) += sun4u_iommu.o -obj-$(CONFIG_SUN4U) += sun4u.o -obj-$(CONFIG_NIAGARA) += niagara.o diff --git a/hw/sparc64/meson.build b/hw/sparc64/meson.build new file mode 100644 index 0000000000..58b5504651 --- /dev/null +++ b/hw/sparc64/meson.build @@ -0,0 +1,6 @@ +sparc64_ss = ss.source_set() +sparc64_ss.add(files('sparc64.c')) +sparc64_ss.add(when: 'CONFIG_NIAGARA', if_true: files('niagara.c')) +sparc64_ss.add(when: 'CONFIG_SUN4U', if_true: files('sun4u.c', 'sun4u_iommu.c')) + +hw_arch += {'sparc64': sparc64_ss} diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs deleted file mode 100644 index 5501f6c1a8..0000000000 --- a/hw/tricore/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_TRICORE) += tricore_testboard.o diff --git a/hw/tricore/meson.build b/hw/tricore/meson.build new file mode 100644 index 0000000000..579aa13c78 --- /dev/null +++ b/hw/tricore/meson.build @@ -0,0 +1,4 @@ +tricore_ss = ss.source_set() +tricore_ss.add(when: 'CONFIG_TRICORE', if_true: files('tricore_testboard.c')) + +hw_arch += {'tricore': tricore_ss} diff --git a/hw/unicore32/Makefile.objs b/hw/unicore32/Makefile.objs deleted file mode 100644 index e0fd628523..0000000000 --- a/hw/unicore32/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -# For UniCore32 machines and boards - -# PKUnity-v3 SoC and board information -obj-${CONFIG_PUV3} += puv3.o diff --git a/hw/unicore32/meson.build b/hw/unicore32/meson.build new file mode 100644 index 0000000000..fc26d6bcab --- /dev/null +++ b/hw/unicore32/meson.build @@ -0,0 +1,5 @@ +unicore32_ss = ss.source_set() +# PKUnity-v3 SoC and board information +unicore32_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3.c')) + +hw_arch += {'unicore32': unicore32_ss} diff --git a/hw/xenpv/Makefile.objs b/hw/xenpv/Makefile.objs deleted file mode 100644 index 8bfa4586ab..0000000000 --- a/hw/xenpv/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -# Xen PV machine support -obj-$(CONFIG_XEN) += xen_machine_pv.o diff --git a/hw/xenpv/meson.build b/hw/xenpv/meson.build new file mode 100644 index 0000000000..40f911ac15 --- /dev/null +++ b/hw/xenpv/meson.build @@ -0,0 +1,3 @@ +xenpv_ss = ss.source_set() + +xenpv_ss.add(when: 'CONFIG_XEN', if_true: files('xen_machine_pv.c')) diff --git a/hw/xtensa/Makefile.objs b/hw/xtensa/Makefile.objs deleted file mode 100644 index 2b40e1b60a..0000000000 --- a/hw/xtensa/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -obj-y += mx_pic.o -obj-y += pic_cpu.o -obj-y += xtensa_memory.o -obj-$(CONFIG_XTENSA_SIM) += sim.o -obj-$(CONFIG_XTENSA_VIRT) += virt.o -obj-$(CONFIG_XTENSA_XTFPGA) += xtfpga.o diff --git a/hw/xtensa/meson.build b/hw/xtensa/meson.build new file mode 100644 index 0000000000..1d5835df4b --- /dev/null +++ b/hw/xtensa/meson.build @@ -0,0 +1,11 @@ +xtensa_ss = ss.source_set() +xtensa_ss.add(files( + 'mx_pic.c', + 'pic_cpu.c', + 'xtensa_memory.c', +)) +xtensa_ss.add(when: 'CONFIG_XTENSA_SIM', if_true: files('sim.c')) +xtensa_ss.add(when: 'CONFIG_XTENSA_VIRT', if_true: files('virt.c')) +xtensa_ss.add(when: 'CONFIG_XTENSA_XTFPGA', if_true: files('xtfpga.c')) + +hw_arch += {'xtensa': xtensa_ss} diff --git a/meson.build b/meson.build index ec958ba2af..5c9f66d2a7 100644 --- a/meson.build +++ b/meson.build @@ -787,6 +787,10 @@ foreach target : target_dirs if target.endswith('-softmmu') qemu_target_name = 'qemu-system-' + target_name target_type='system' + hw_dir = target_name == 'sparc64' ? 'sparc64' : arch + hw = hw_arch[hw_dir].apply(config_target, strict: false) + arch_srcs += hw.sources() + arch_srcs += config_devices_h[target] else target_type='user' -- cgit v1.2.3-55-g7522 From abff1abfe8113a989215ed33c48839a827e531f1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 7 Aug 2020 12:10:23 +0200 Subject: meson: target Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 3 +- libdecnumber/Makefile.objs | 5 --- libdecnumber/meson.build | 7 ++++ meson.build | 11 +++++ scripts/decodetree.py | 2 +- target/alpha/Makefile.objs | 4 -- target/alpha/meson.build | 18 +++++++++ target/arm/Makefile.objs | 89 ----------------------------------------- target/arm/meson.build | 62 ++++++++++++++++++++++++++++ target/avr/Makefile.objs | 34 ---------------- target/avr/disas.c | 2 +- target/avr/meson.build | 20 +++++++++ target/avr/translate.c | 2 +- target/cris/Makefile.objs | 3 -- target/cris/meson.build | 14 +++++++ target/hppa/Makefile.objs | 11 ----- target/hppa/meson.build | 19 +++++++++ target/hppa/translate.c | 2 +- target/i386/Makefile.objs | 23 ----------- target/i386/hvf/Makefile.objs | 2 - target/i386/hvf/meson.build | 12 ++++++ target/i386/meson.build | 40 ++++++++++++++++++ target/lm32/Makefile.objs | 4 -- target/lm32/meson.build | 15 +++++++ target/m68k/Makefile.objs | 5 --- target/m68k/meson.build | 17 ++++++++ target/meson.build | 22 ++++++++++ target/microblaze/Makefile.objs | 3 -- target/microblaze/meson.build | 14 +++++++ target/mips/Makefile.objs | 6 --- target/mips/meson.build | 24 +++++++++++ target/moxie/Makefile.objs | 2 - target/moxie/meson.build | 14 +++++++ target/nios2/Makefile.objs | 4 -- target/nios2/meson.build | 15 +++++++ target/openrisc/Makefile.objs | 15 ------- target/openrisc/disas.c | 2 +- target/openrisc/meson.build | 23 +++++++++++ target/openrisc/translate.c | 2 +- target/ppc/Makefile.objs | 20 --------- target/ppc/meson.build | 37 +++++++++++++++++ target/riscv/Makefile.objs | 28 ------------- target/riscv/meson.build | 34 ++++++++++++++++ target/riscv/translate.c | 4 +- target/rx/Makefile.objs | 11 ----- target/rx/disas.c | 2 +- target/rx/meson.build | 16 ++++++++ target/rx/translate.c | 2 +- target/s390x/Makefile.objs | 10 ----- target/s390x/meson.build | 42 ++++++++++++++++++- target/sh4/Makefile.objs | 3 -- target/sh4/meson.build | 14 +++++++ target/sparc/Makefile.objs | 7 ---- target/sparc/meson.build | 23 +++++++++++ target/tilegx/Makefile.objs | 1 - target/tilegx/meson.build | 13 ++++++ target/tricore/Makefile.objs | 1 - target/tricore/meson.build | 15 +++++++ target/unicore32/Makefile.objs | 8 ---- target/unicore32/meson.build | 14 +++++++ target/xtensa/Makefile.objs | 16 -------- target/xtensa/meson.build | 30 ++++++++++++++ 62 files changed, 595 insertions(+), 328 deletions(-) delete mode 100644 libdecnumber/Makefile.objs create mode 100644 libdecnumber/meson.build mode change 100755 => 100644 scripts/decodetree.py delete mode 100644 target/alpha/Makefile.objs create mode 100644 target/alpha/meson.build delete mode 100644 target/arm/Makefile.objs create mode 100644 target/arm/meson.build delete mode 100644 target/avr/Makefile.objs create mode 100644 target/avr/meson.build delete mode 100644 target/cris/Makefile.objs create mode 100644 target/cris/meson.build delete mode 100644 target/hppa/Makefile.objs create mode 100644 target/hppa/meson.build delete mode 100644 target/i386/Makefile.objs delete mode 100644 target/i386/hvf/Makefile.objs create mode 100644 target/i386/hvf/meson.build create mode 100644 target/i386/meson.build delete mode 100644 target/lm32/Makefile.objs create mode 100644 target/lm32/meson.build delete mode 100644 target/m68k/Makefile.objs create mode 100644 target/m68k/meson.build delete mode 100644 target/microblaze/Makefile.objs create mode 100644 target/microblaze/meson.build delete mode 100644 target/mips/Makefile.objs create mode 100644 target/mips/meson.build delete mode 100644 target/moxie/Makefile.objs create mode 100644 target/moxie/meson.build delete mode 100644 target/nios2/Makefile.objs create mode 100644 target/nios2/meson.build delete mode 100644 target/openrisc/Makefile.objs create mode 100644 target/openrisc/meson.build delete mode 100644 target/ppc/Makefile.objs create mode 100644 target/ppc/meson.build delete mode 100644 target/riscv/Makefile.objs create mode 100644 target/riscv/meson.build delete mode 100644 target/rx/Makefile.objs create mode 100644 target/rx/meson.build delete mode 100644 target/s390x/Makefile.objs delete mode 100644 target/sh4/Makefile.objs create mode 100644 target/sh4/meson.build delete mode 100644 target/sparc/Makefile.objs create mode 100644 target/sparc/meson.build delete mode 100644 target/tilegx/Makefile.objs create mode 100644 target/tilegx/meson.build delete mode 100644 target/tricore/Makefile.objs create mode 100644 target/tricore/meson.build delete mode 100644 target/unicore32/Makefile.objs create mode 100644 target/unicore32/meson.build delete mode 100644 target/xtensa/Makefile.objs create mode 100644 target/xtensa/meson.build diff --git a/Makefile.target b/Makefile.target index 28cefba1de..1ab8773402 100644 --- a/Makefile.target +++ b/Makefile.target @@ -116,7 +116,6 @@ obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o obj-$(CONFIG_TCG) += fpu/softfloat.o -obj-y += target/$(TARGET_BASE_ARCH)/ obj-y += disas.o obj-$(call notempty,$(TARGET_XML_FILES)) += gdbstub-xml.o LIBS := $(libs_cpu) $(LIBS) @@ -168,7 +167,7 @@ LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOM LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) -LIBS := $(LIBS) $(VIRGL_LIBS) +LIBS := $(LIBS) $(VIRGL_LIBS) $(CURSES_LIBS) generated-files-y += hmp-commands.h hmp-commands-info.h diff --git a/libdecnumber/Makefile.objs b/libdecnumber/Makefile.objs deleted file mode 100644 index d81db0443a..0000000000 --- a/libdecnumber/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += decContext.o -obj-y += decNumber.o -obj-y += dpd/decimal32.o -obj-y += dpd/decimal64.o -obj-y += dpd/decimal128.o diff --git a/libdecnumber/meson.build b/libdecnumber/meson.build new file mode 100644 index 0000000000..4d04139af4 --- /dev/null +++ b/libdecnumber/meson.build @@ -0,0 +1,7 @@ +libdecnumber = files( + 'decContext.c', + 'decNumber.c', + 'dpd/decimal128.c', + 'dpd/decimal32.c', + 'dpd/decimal64.c', +) diff --git a/meson.build b/meson.build index 5c9f66d2a7..ac59ccc935 100644 --- a/meson.build +++ b/meson.build @@ -647,10 +647,15 @@ libqemuutil = static_library('qemuutil', qemuutil = declare_dependency(link_with: libqemuutil, sources: genh + version_res) +decodetree = generator(find_program('scripts/decodetree.py'), + output: 'decode-@BASENAME@.c.inc', + arguments: ['@INPUT@', '@EXTRA_ARGS@', '-o', '@OUTPUT@']) + subdir('audio') subdir('io') subdir('chardev') subdir('fsdev') +subdir('libdecnumber') subdir('target') subdir('dump') @@ -787,6 +792,9 @@ foreach target : target_dirs if target.endswith('-softmmu') qemu_target_name = 'qemu-system-' + target_name target_type='system' + t = target_softmmu_arch[arch].apply(config_target, strict: false) + arch_srcs += t.sources() + hw_dir = target_name == 'sparc64' ? 'sparc64' : arch hw = hw_arch[hw_dir].apply(config_target, strict: false) arch_srcs += hw.sources() @@ -807,6 +815,9 @@ foreach target : target_dirs ) endif + t = target_arch[arch].apply(config_target, strict: false) + arch_srcs += t.sources() + target_common = common_ss.apply(config_target, strict: false) objects = common_all.extract_objects(target_common.sources()) diff --git a/scripts/decodetree.py b/scripts/decodetree.py old mode 100755 new mode 100644 index 694757b6c2..4cd1e10904 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -1257,7 +1257,7 @@ def main(): long_opts = ['decode=', 'translate=', 'output=', 'insnwidth=', 'static-decode=', 'varinsnwidth='] try: - (opts, args) = getopt.getopt(sys.argv[1:], 'o:vw:', long_opts) + (opts, args) = getopt.gnu_getopt(sys.argv[1:], 'o:vw:', long_opts) except getopt.GetoptError as err: error(0, err) for o, a in opts: diff --git a/target/alpha/Makefile.objs b/target/alpha/Makefile.objs deleted file mode 100644 index 63664629f6..0000000000 --- a/target/alpha/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_SOFTMMU) += machine.o -obj-y += translate.o helper.o cpu.o -obj-y += int_helper.o fpu_helper.o vax_helper.o sys_helper.o mem_helper.o -obj-y += gdbstub.o diff --git a/target/alpha/meson.build b/target/alpha/meson.build new file mode 100644 index 0000000000..1aec55abb4 --- /dev/null +++ b/target/alpha/meson.build @@ -0,0 +1,18 @@ +alpha_ss = ss.source_set() +alpha_ss.add(files( + 'cpu.c', + 'fpu_helper.c', + 'gdbstub.c', + 'helper.c', + 'int_helper.c', + 'mem_helper.c', + 'sys_helper.c', + 'translate.c', + 'vax_helper.c', +)) + +alpha_softmmu_ss = ss.source_set() +alpha_softmmu_ss.add(files('machine.c')) + +target_arch += {'alpha': alpha_ss} +target_softmmu_arch += {'alpha': alpha_softmmu_ss} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs deleted file mode 100644 index 317eed993f..0000000000 --- a/target/arm/Makefile.objs +++ /dev/null @@ -1,89 +0,0 @@ -obj-$(CONFIG_TCG) += arm-semi.o -obj-y += helper.o vfp_helper.o -obj-y += cpu.o gdbstub.o -obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o - -obj-$(CONFIG_SOFTMMU) += machine.o arch_dump.o monitor.o -obj-$(CONFIG_SOFTMMU) += arm-powerctl.o - -obj-$(CONFIG_KVM) += kvm.o -obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o -obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o -obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py - -target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ - "GEN", $(TARGET_DIR)$@) - -target/arm/translate-sve.o: target/arm/decode-sve.c.inc -target/arm/translate.o: target/arm/decode-neon-shared.c.inc -target/arm/translate.o: target/arm/decode-neon-dp.c.inc -target/arm/translate.o: target/arm/decode-neon-ls.c.inc -target/arm/translate.o: target/arm/decode-vfp.c.inc -target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc -target/arm/translate.o: target/arm/decode-a32.c.inc -target/arm/translate.o: target/arm/decode-a32-uncond.c.inc -target/arm/translate.o: target/arm/decode-t32.c.inc -target/arm/translate.o: target/arm/decode-t16.c.inc - -obj-y += tlb_helper.o debug_helper.o -obj-y += translate.o op_helper.o -obj-y += crypto_helper.o -obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o -obj-y += m_helper.o -obj-y += cpu_tcg.o - -obj-$(CONFIG_SOFTMMU) += psci.o - -obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o -obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o -obj-$(TARGET_AARCH64) += pauth_helper.o -obj-$(TARGET_AARCH64) += mte_helper.o diff --git a/target/arm/meson.build b/target/arm/meson.build new file mode 100644 index 0000000000..bd46cdb523 --- /dev/null +++ b/target/arm/meson.build @@ -0,0 +1,62 @@ +gen = [ + decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), + decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), + decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), + decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), + decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), + decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), + decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), + decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), + decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), + decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), +] + +arm_ss = ss.source_set() +arm_ss.add(gen) +arm_ss.add(files( + 'cpu.c', + 'crypto_helper.c', + 'debug_helper.c', + 'gdbstub.c', + 'helper.c', + 'iwmmxt_helper.c', + 'm_helper.c', + 'neon_helper.c', + 'op_helper.c', + 'tlb_helper.c', + 'translate.c', + 'vec_helper.c', + 'vfp_helper.c', + 'cpu_tcg.c', +)) +arm_ss.add(zlib) + +arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) + +kvm_ss = ss.source_set() +kvm_ss.add(when: 'TARGET_AARCH64', if_true: files('kvm64.c'), if_false: files('kvm32.c')) +arm_ss.add_all(when: 'CONFIG_KVM', if_true: kvm_ss) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) + +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c', + 'helper-a64.c', + 'mte_helper.c', + 'pauth_helper.c', + 'sve_helper.c', + 'translate-a64.c', + 'translate-sve.c', +)) + +arm_softmmu_ss = ss.source_set() +arm_softmmu_ss.add(files( + 'arch_dump.c', + 'arm-powerctl.c', + 'machine.c', + 'monitor.c', + 'psci.c', +)) + +target_arch += {'arm': arm_ss} +target_softmmu_arch += {'arm': arm_softmmu_ss} diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs deleted file mode 100644 index fb94a0b069..0000000000 --- a/target/avr/Makefile.objs +++ /dev/null @@ -1,34 +0,0 @@ -# -# QEMU AVR -# -# Copyright (c) 2016-2020 Michael Rolnik -# -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, see -# -# - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py -decode-y = $(SRC_PATH)/target/avr/insn.decode - -target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE) - $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \ - "GEN", $(TARGET_DIR)$@) - -target/avr/translate.o: target/avr/decode_insn.c.inc - -obj-y += translate.o cpu.o helper.o -obj-y += gdbstub.o -obj-y += disas.o -obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target/avr/disas.c b/target/avr/disas.c index f15dc7911a..b7689e8d7c 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x) /* Include the auto-generated decoder. */ static bool decode_insn(DisasContext *ctx, uint16_t insn); -#include "decode_insn.c.inc" +#include "decode-insn.c.inc" #define output(mnemonic, format, ...) \ (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \ diff --git a/target/avr/meson.build b/target/avr/meson.build new file mode 100644 index 0000000000..7e8e29c59d --- /dev/null +++ b/target/avr/meson.build @@ -0,0 +1,20 @@ +gen = [ + decodetree.process('insn.decode', extra_args: [ '--decode', 'decode_insn', + '--insnwidth', '16' ]) +] + +avr_ss = ss.source_set() +avr_softmmu_ss = ss.source_set() + +avr_ss.add(gen) +avr_ss.add(files( + 'translate.c', + 'helper.c', + 'cpu.c', + 'gdbstub.c', + 'disas.c')) + +avr_softmmu_ss.add(files('machine.c')) + +target_arch += {'avr': avr_ss} +target_softmmu_arch += {'avr': avr_softmmu_ss} diff --git a/target/avr/translate.c b/target/avr/translate.c index 9eb14f63f0..850c5941d9 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -198,7 +198,7 @@ static bool avr_have_feature(DisasContext *ctx, int feature) } static bool decode_insn(DisasContext *ctx, uint16_t insn); -#include "decode_insn.c.inc" +#include "decode-insn.c.inc" /* * Arithmetic Instructions diff --git a/target/cris/Makefile.objs b/target/cris/Makefile.objs deleted file mode 100644 index 7779227fc4..0000000000 --- a/target/cris/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += gdbstub.o -obj-$(CONFIG_SOFTMMU) += mmu.o machine.o diff --git a/target/cris/meson.build b/target/cris/meson.build new file mode 100644 index 0000000000..67c3793c85 --- /dev/null +++ b/target/cris/meson.build @@ -0,0 +1,14 @@ +cris_ss = ss.source_set() +cris_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'op_helper.c', + 'translate.c', +)) + +cris_softmmu_ss = ss.source_set() +cris_softmmu_ss.add(files('mmu.c', 'machine.c')) + +target_arch += {'cris': cris_ss} +target_softmmu_arch += {'cris': cris_softmmu_ss} diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs deleted file mode 100644 index 190cbff197..0000000000 --- a/target/hppa/Makefile.objs +++ /dev/null @@ -1,11 +0,0 @@ -obj-y += translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o -obj-y += int_helper.o -obj-$(CONFIG_SOFTMMU) += machine.o - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py - -target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) - -target/hppa/translate.o: target/hppa/decode.c.inc diff --git a/target/hppa/meson.build b/target/hppa/meson.build new file mode 100644 index 0000000000..8a7ff82efc --- /dev/null +++ b/target/hppa/meson.build @@ -0,0 +1,19 @@ +gen = decodetree.process('insns.decode') + +hppa_ss = ss.source_set() +hppa_ss.add(gen) +hppa_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'int_helper.c', + 'mem_helper.c', + 'op_helper.c', + 'translate.c', +)) + +hppa_softmmu_ss = ss.source_set() +hppa_softmmu_ss.add(files('machine.c')) + +target_arch += {'hppa': hppa_ss} +target_softmmu_arch += {'hppa': hppa_softmmu_ss} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 316f58562e..f5765ef688 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -334,7 +334,7 @@ static int expand_shl11(DisasContext *ctx, int val) /* Include the auto-generated decoder. */ -#include "decode.c.inc" +#include "decode-insns.c.inc" /* We are not using a goto_tb (for whatever reason), but have updated the iaq (for whatever reason), so don't do it again on exit. */ diff --git a/target/i386/Makefile.objs b/target/i386/Makefile.objs deleted file mode 100644 index 0b93143e27..0000000000 --- a/target/i386/Makefile.objs +++ /dev/null @@ -1,23 +0,0 @@ -obj-y += helper.o cpu.o gdbstub.o xsave_helper.o -obj-$(CONFIG_TCG) += translate.o -obj-$(CONFIG_TCG) += bpt_helper.o cc_helper.o excp_helper.o fpu_helper.o -obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o mpx_helper.o -obj-$(CONFIG_TCG) += seg_helper.o smm_helper.o svm_helper.o -obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o -obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o -ifeq ($(CONFIG_SOFTMMU),y) -obj-y += machine.o arch_memory_mapping.o arch_dump.o monitor.o -obj-$(CONFIG_KVM) += kvm.o -obj-$(CONFIG_HYPERV) += hyperv.o -obj-$(call lnot,$(CONFIG_HYPERV)) += hyperv-stub.o -ifeq ($(CONFIG_WIN32),y) -obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-windows.o -endif -ifeq ($(CONFIG_POSIX),y) -obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-posix.o -endif -obj-$(CONFIG_HVF) += hvf/ -obj-$(CONFIG_WHPX) += whpx-all.o -endif -obj-$(CONFIG_SEV) += sev.o -obj-$(call lnot,$(CONFIG_SEV)) += sev-stub.o diff --git a/target/i386/hvf/Makefile.objs b/target/i386/hvf/Makefile.objs deleted file mode 100644 index 927b86bc67..0000000000 --- a/target/i386/hvf/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += hvf.o -obj-y += x86.o x86_cpuid.o x86_decode.o x86_descr.o x86_emu.o x86_flags.o x86_mmu.o x86hvf.o x86_task.o diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build new file mode 100644 index 0000000000..c8a43717ee --- /dev/null +++ b/target/i386/hvf/meson.build @@ -0,0 +1,12 @@ +i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( + 'hvf.c', + 'x86.c', + 'x86_cpuid.c', + 'x86_decode.c', + 'x86_descr.c', + 'x86_emu.c', + 'x86_flags.c', + 'x86_mmu.c', + 'x86_task.c', + 'x86hvf.c', +)) diff --git a/target/i386/meson.build b/target/i386/meson.build new file mode 100644 index 0000000000..e0b71ade56 --- /dev/null +++ b/target/i386/meson.build @@ -0,0 +1,40 @@ +i386_ss = ss.source_set() +i386_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'xsave_helper.c', +)) +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c')) + +i386_softmmu_ss = ss.source_set() +i386_softmmu_ss.add(files( + 'arch_dump.c', + 'arch_memory_mapping.c', + 'machine.c', + 'monitor.c', +)) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files('whpx-all.c')) +i386_softmmu_ss.add(when: ['CONFIG_POSIX', 'CONFIG_HAX'], if_true: files('hax-all.c', 'hax-mem.c', 'hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_WIN32', 'CONFIG_HAX'], if_true: files('hax-all.c', 'hax-mem.c', 'hax-windows.c')) + +subdir('hvf') + +target_arch += {'i386': i386_ss} +target_softmmu_arch += {'i386': i386_softmmu_ss} diff --git a/target/lm32/Makefile.objs b/target/lm32/Makefile.objs deleted file mode 100644 index c3e1bd6bd6..0000000000 --- a/target/lm32/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += gdbstub.o -obj-y += lm32-semi.o -obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target/lm32/meson.build b/target/lm32/meson.build new file mode 100644 index 0000000000..ef0eef07f1 --- /dev/null +++ b/target/lm32/meson.build @@ -0,0 +1,15 @@ +lm32_ss = ss.source_set() +lm32_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'lm32-semi.c', + 'op_helper.c', + 'translate.c', +)) + +lm32_softmmu_ss = ss.source_set() +lm32_softmmu_ss.add(files('machine.c')) + +target_arch += {'lm32': lm32_ss} +target_softmmu_arch += {'lm32': lm32_softmmu_ss} diff --git a/target/m68k/Makefile.objs b/target/m68k/Makefile.objs deleted file mode 100644 index ac61948676..0000000000 --- a/target/m68k/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += m68k-semi.o -obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += fpu_helper.o softfloat.o -obj-y += gdbstub.o -obj-$(CONFIG_SOFTMMU) += monitor.o diff --git a/target/m68k/meson.build b/target/m68k/meson.build new file mode 100644 index 0000000000..05cd9fbd1e --- /dev/null +++ b/target/m68k/meson.build @@ -0,0 +1,17 @@ +m68k_ss = ss.source_set() +m68k_ss.add(files( + 'cpu.c', + 'fpu_helper.c', + 'gdbstub.c', + 'helper.c', + 'm68k-semi.c', + 'op_helper.c', + 'softfloat.c', + 'translate.c', +)) + +m68k_softmmu_ss = ss.source_set() +m68k_softmmu_ss.add(files('monitor.c')) + +target_arch += {'m68k': m68k_ss} +target_softmmu_arch += {'m68k': m68k_softmmu_ss} diff --git a/target/meson.build b/target/meson.build index e29dd3e01f..9f0ae93b75 100644 --- a/target/meson.build +++ b/target/meson.build @@ -1 +1,23 @@ +subdir('alpha') +subdir('arm') +subdir('avr') +subdir('cris') +subdir('hppa') +subdir('i386') +subdir('lm32') +subdir('m68k') +subdir('microblaze') +subdir('mips') +subdir('moxie') +subdir('nios2') +subdir('openrisc') +subdir('ppc') +subdir('riscv') +subdir('rx') subdir('s390x') +subdir('sh4') +subdir('sparc') +subdir('tilegx') +subdir('tricore') +subdir('unicore32') +subdir('xtensa') diff --git a/target/microblaze/Makefile.objs b/target/microblaze/Makefile.objs deleted file mode 100644 index f3d7b44c89..0000000000 --- a/target/microblaze/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += gdbstub.o -obj-$(CONFIG_SOFTMMU) += mmu.o diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build new file mode 100644 index 0000000000..b8fe4afe61 --- /dev/null +++ b/target/microblaze/meson.build @@ -0,0 +1,14 @@ +microblaze_ss = ss.source_set() +microblaze_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'op_helper.c', + 'translate.c', +)) + +microblaze_softmmu_ss = ss.source_set() +microblaze_softmmu_ss.add(files('mmu.c')) + +target_arch += {'microblaze': microblaze_ss} +target_softmmu_arch += {'microblaze': microblaze_softmmu_ss} diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs deleted file mode 100644 index b820b3b7bc..0000000000 --- a/target/mips/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -obj-y += translate.o cpu.o gdbstub.o helper.o -obj-y += op_helper.o cp0_helper.o fpu_helper.o -obj-y += dsp_helper.o lmmi_helper.o msa_helper.o -obj-$(CONFIG_SOFTMMU) += mips-semi.o -obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o -obj-$(CONFIG_KVM) += kvm.o diff --git a/target/mips/meson.build b/target/mips/meson.build new file mode 100644 index 0000000000..fa1f024e78 --- /dev/null +++ b/target/mips/meson.build @@ -0,0 +1,24 @@ +mips_ss = ss.source_set() +mips_ss.add(files( + 'cp0_helper.c', + 'cpu.c', + 'dsp_helper.c', + 'fpu_helper.c', + 'gdbstub.c', + 'helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'op_helper.c', + 'translate.c', +)) +mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) + +mips_softmmu_ss = ss.source_set() +mips_softmmu_ss.add(files( + 'cp0_timer.c', + 'machine.c', + 'mips-semi.c', +)) + +target_arch += {'mips': mips_ss} +target_softmmu_arch += {'mips': mips_softmmu_ss} diff --git a/target/moxie/Makefile.objs b/target/moxie/Makefile.objs deleted file mode 100644 index 6381d4d636..0000000000 --- a/target/moxie/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += translate.o helper.o machine.o cpu.o machine.o -obj-$(CONFIG_SOFTMMU) += mmu.o diff --git a/target/moxie/meson.build b/target/moxie/meson.build new file mode 100644 index 0000000000..b4beb528cc --- /dev/null +++ b/target/moxie/meson.build @@ -0,0 +1,14 @@ +moxie_ss = ss.source_set() +moxie_ss.add(files( + 'cpu.c', + 'helper.c', + 'machine.c', + 'machine.c', + 'translate.c', +)) + +moxie_softmmu_ss = ss.source_set() +moxie_softmmu_ss.add(files('mmu.c')) + +target_arch += {'moxie': moxie_ss} +target_softmmu_arch += {'moxie': moxie_softmmu_ss} diff --git a/target/nios2/Makefile.objs b/target/nios2/Makefile.objs deleted file mode 100644 index 010de0e7a6..0000000000 --- a/target/nios2/Makefile.objs +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o mmu.o nios2-semi.o -obj-$(CONFIG_SOFTMMU) += monitor.o - -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) diff --git a/target/nios2/meson.build b/target/nios2/meson.build new file mode 100644 index 0000000000..e643917db1 --- /dev/null +++ b/target/nios2/meson.build @@ -0,0 +1,15 @@ +nios2_ss = ss.source_set() +nios2_ss.add(files( + 'cpu.c', + 'helper.c', + 'mmu.c', + 'nios2-semi.c', + 'op_helper.c', + 'translate.c', +)) + +nios2_softmmu_ss = ss.source_set() +nios2_softmmu_ss.add(files('monitor.c')) + +target_arch += {'nios2': nios2_ss} +target_softmmu_arch += {'nios2': nios2_softmmu_ss} diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs deleted file mode 100644 index 423d64512e..0000000000 --- a/target/openrisc/Makefile.objs +++ /dev/null @@ -1,15 +0,0 @@ -obj-$(CONFIG_SOFTMMU) += machine.o -obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o -obj-y += exception_helper.o fpu_helper.o \ - interrupt_helper.o sys_helper.o -obj-y += gdbstub.o - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py - -target/openrisc/decode.c.inc: \ - $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) - -target/openrisc/translate.o: target/openrisc/decode.c.inc -target/openrisc/disas.o: target/openrisc/decode.c.inc diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index cc91775344..dc025bd64d 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -25,7 +25,7 @@ typedef disassemble_info DisasContext; /* Include the auto-generated decoder. */ -#include "decode.c.inc" +#include "decode-insns.c.inc" #define output(mnemonic, format, ...) \ (info->fprintf_func(info->stream, "%-9s " format, \ diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build new file mode 100644 index 0000000000..9774a58306 --- /dev/null +++ b/target/openrisc/meson.build @@ -0,0 +1,23 @@ +gen = decodetree.process('insns.decode') + +openrisc_ss = ss.source_set() +openrisc_ss.add(gen) +openrisc_ss.add(files( + 'cpu.c', + 'disas.c', + 'exception.c', + 'exception_helper.c', + 'fpu_helper.c', + 'gdbstub.c', + 'interrupt.c', + 'interrupt_helper.c', + 'mmu.c', + 'sys_helper.c', + 'translate.c', +)) + +openrisc_softmmu_ss = ss.source_set() +openrisc_softmmu_ss.add(files('machine.c')) + +target_arch += {'openrisc': openrisc_ss} +target_softmmu_arch += {'openrisc': openrisc_softmmu_ss} diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 573428b8ea..c6dce879f1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -65,7 +65,7 @@ static inline bool is_user(DisasContext *dc) } /* Include the auto-generated decoder. */ -#include "decode.c.inc" +#include "decode-insns.c.inc" static TCGv cpu_sr; static TCGv cpu_regs[32]; diff --git a/target/ppc/Makefile.objs b/target/ppc/Makefile.objs deleted file mode 100644 index e8fa18ce13..0000000000 --- a/target/ppc/Makefile.objs +++ /dev/null @@ -1,20 +0,0 @@ -obj-y += cpu-models.o -obj-y += cpu.o -obj-y += translate.o -ifeq ($(CONFIG_SOFTMMU),y) -obj-y += machine.o mmu_helper.o mmu-hash32.o monitor.o arch_dump.o -obj-$(TARGET_PPC64) += mmu-hash64.o mmu-book3s-v3.o compat.o -obj-$(TARGET_PPC64) += mmu-radix64.o -endif -obj-$(CONFIG_KVM) += kvm.o -obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o -obj-y += dfp_helper.o -obj-y += excp_helper.o -obj-y += fpu_helper.o -obj-y += int_helper.o -obj-y += timebase_helper.o -obj-y += misc_helper.o -obj-y += mem_helper.o -obj-y += ../../libdecnumber/ -obj-$(CONFIG_USER_ONLY) += user_only_helper.o -obj-y += gdbstub.o diff --git a/target/ppc/meson.build b/target/ppc/meson.build new file mode 100644 index 0000000000..bbfef90e08 --- /dev/null +++ b/target/ppc/meson.build @@ -0,0 +1,37 @@ +ppc_ss = ss.source_set() +ppc_ss.add(files( + 'cpu-models.c', + 'cpu.c', + 'dfp_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'gdbstub.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'timebase_helper.c', + 'translate.c', +)) + +ppc_ss.add(libdecnumber) + +ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) +ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) + +ppc_softmmu_ss = ss.source_set() +ppc_softmmu_ss.add(files( + 'arch_dump.c', + 'machine.c', + 'mmu-hash32.c', + 'mmu_helper.c', + 'monitor.c', +)) +ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( + 'compat.c', + 'mmu-book3s-v3.c', + 'mmu-hash64.c', + 'mmu-radix64.c', +)) + +target_arch += {'ppc': ppc_ss} +target_softmmu_arch += {'ppc': ppc_softmmu_ss} diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs deleted file mode 100644 index 1cd4c58005..0000000000 --- a/target/riscv/Makefile.objs +++ /dev/null @@ -1,28 +0,0 @@ -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o vector_helper.o gdbstub.o -obj-$(CONFIG_SOFTMMU) += pmp.o - -ifeq ($(CONFIG_SOFTMMU),y) -obj-y += monitor.o -endif - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py - -decode32-y = $(SRC_PATH)/target/riscv/insn32.decode -decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode - -decode16-y = $(SRC_PATH)/target/riscv/insn16.decode -decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode -decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode - -target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE) - $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ - $(decode32-y), "GEN", $(TARGET_DIR)$@) - -target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE) - $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ - --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) - -target/riscv/translate.o: target/riscv/decode_insn32.c.inc \ - target/riscv/decode_insn16.c.inc diff --git a/target/riscv/meson.build b/target/riscv/meson.build new file mode 100644 index 0000000000..abd647fea1 --- /dev/null +++ b/target/riscv/meson.build @@ -0,0 +1,34 @@ +# FIXME extra_args should accept files() +dir = meson.current_source_dir() +gen32 = [ + decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']), + decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), +] + +gen64 = [ + decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']), + decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']), +] + +riscv_ss = ss.source_set() +riscv_ss.add(when: 'TARGET_RISCV32', if_true: gen32) +riscv_ss.add(when: 'TARGET_RISCV64', if_true: gen64) +riscv_ss.add(files( + 'cpu.c', + 'cpu_helper.c', + 'csr.c', + 'fpu_helper.c', + 'gdbstub.c', + 'op_helper.c', + 'vector_helper.c', + 'translate.c', +)) + +riscv_softmmu_ss = ss.source_set() +riscv_softmmu_ss.add(files( + 'pmp.c', + 'monitor.c' +)) + +target_arch += {'riscv': riscv_ss} +target_softmmu_arch += {'riscv': riscv_softmmu_ss} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5ef5613909..d0485c0750 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) } /* Include the auto-generated decoder for 32 bit insn */ -#include "decode_insn32.c.inc" +#include "decode-insn32.c.inc" static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, void (*func)(TCGv, TCGv, target_long)) @@ -728,7 +728,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */ -#include "decode_insn16.c.inc" +#include "decode-insn16.c.inc" static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs deleted file mode 100644 index cc3c4204a1..0000000000 --- a/target/rx/Makefile.objs +++ /dev/null @@ -1,11 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o - -DECODETREE = $(SRC_PATH)/scripts/decodetree.py - -target/rx/decode.c.inc: \ - $(SRC_PATH)/target/rx/insns.decode $(DECODETREE) - $(call quiet-command,\ - $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@) - -target/rx/translate.o: target/rx/decode.c.inc -target/rx/disas.o: target/rx/decode.c.inc diff --git a/target/rx/disas.c b/target/rx/disas.c index 60eff6f55f..67b9328829 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -100,7 +100,7 @@ static int bdsp_s(DisasContext *ctx, int d) } /* Include the auto-generated decoder. */ -#include "decode.c.inc" +#include "decode-insns.c.inc" static void dump_bytes(DisasContext *ctx) { diff --git a/target/rx/meson.build b/target/rx/meson.build new file mode 100644 index 0000000000..8de0ad49b9 --- /dev/null +++ b/target/rx/meson.build @@ -0,0 +1,16 @@ +gen = [ + decodetree.process('insns.decode', extra_args: [ '--varinsnwidth', '32' ]) +] + +rx_ss = ss.source_set() +rx_ss.add(gen) +rx_ss.add(files( + 'translate.c', + 'op_helper.c', + 'helper.c', + 'cpu.c', + 'gdbstub.c', + 'disas.c')) + +target_arch += {'rx': rx_ss} +target_softmmu_arch += {'rx': ss.source_set()} diff --git a/target/rx/translate.c b/target/rx/translate.c index bc49614cbb..da9713d362 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -124,7 +124,7 @@ static int bdsp_s(DisasContext *ctx, int d) } /* Include the auto-generated decoder. */ -#include "decode.c.inc" +#include "decode-insns.c.inc" void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs deleted file mode 100644 index 9b9accc5fd..0000000000 --- a/target/s390x/Makefile.objs +++ /dev/null @@ -1,10 +0,0 @@ -obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o -obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o -obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o -obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o vec_string_helper.o -obj-$(CONFIG_TCG) += vec_fpu_helper.o -obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o -obj-$(CONFIG_SOFTMMU) += sigp.o -obj-$(CONFIG_KVM) += kvm.o -obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o -obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o diff --git a/target/s390x/meson.build b/target/s390x/meson.build index ddf8d20a36..27d248ef6e 100644 --- a/target/s390x/meson.build +++ b/target/s390x/meson.build @@ -1,3 +1,30 @@ +s390x_ss = ss.source_set() +s390x_ss.add(files( + 'cpu.c', + 'cpu_features.c', + 'cpu_models.c', + 'gdbstub.c', + 'helper.c', + 'interrupt.c', +)) + +s390x_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cc_helper.c', + 'crypto_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'translate.c', + 'vec_fpu_helper.c', + 'vec_helper.c', + 'vec_int_helper.c', + 'vec_string_helper.c', +), if_false: 'tcg-stub.c') + +s390x_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) + gen_features = executable('gen-features', 'gen-features.c', native: true, build_by_default: false) @@ -6,4 +33,17 @@ gen_features_h = custom_target('gen-features.h', capture: true, command: gen_features) -specific_ss.add(gen_features_h) +s390x_ss.add(gen_features_h) + +s390x_softmmu_ss = ss.source_set() +s390x_softmmu_ss.add(files( + 'arch_dump.c', + 'diag.c', + 'ioinst.c', + 'machine.c', + 'mmu_helper.c', + 'sigp.c', +)) + +target_arch += {'s390x': s390x_ss} +target_softmmu_arch += {'s390x': s390x_softmmu_ss} diff --git a/target/sh4/Makefile.objs b/target/sh4/Makefile.objs deleted file mode 100644 index 2c25d96e65..0000000000 --- a/target/sh4/Makefile.objs +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o -obj-$(CONFIG_SOFTMMU) += monitor.o -obj-y += gdbstub.o diff --git a/target/sh4/meson.build b/target/sh4/meson.build new file mode 100644 index 0000000000..56a57576da --- /dev/null +++ b/target/sh4/meson.build @@ -0,0 +1,14 @@ +sh4_ss = ss.source_set() +sh4_ss.add(files( + 'cpu.c', + 'gdbstub.c', + 'helper.c', + 'op_helper.c', + 'translate.c', +)) + +sh4_softmmu_ss = ss.source_set() +sh4_softmmu_ss.add(files('monitor.c')) + +target_arch += {'sh4': sh4_ss} +target_softmmu_arch += {'sh4': sh4_softmmu_ss} diff --git a/target/sparc/Makefile.objs b/target/sparc/Makefile.objs deleted file mode 100644 index ec905698c5..0000000000 --- a/target/sparc/Makefile.objs +++ /dev/null @@ -1,7 +0,0 @@ -obj-$(CONFIG_SOFTMMU) += machine.o monitor.o -obj-y += translate.o helper.o cpu.o -obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o -obj-$(TARGET_SPARC) += int32_helper.o -obj-$(TARGET_SPARC64) += int64_helper.o -obj-$(TARGET_SPARC64) += vis_helper.o -obj-y += gdbstub.o diff --git a/target/sparc/meson.build b/target/sparc/meson.build new file mode 100644 index 0000000000..a3638b9503 --- /dev/null +++ b/target/sparc/meson.build @@ -0,0 +1,23 @@ +sparc_ss = ss.source_set() +sparc_ss.add(files( + 'cc_helper.c', + 'cpu.c', + 'fop_helper.c', + 'gdbstub.c', + 'helper.c', + 'ldst_helper.c', + 'mmu_helper.c', + 'translate.c', + 'win_helper.c', +)) +sparc_ss.add(when: 'TARGET_SPARC', if_true: files('int32_helper.c')) +sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helper.c')) + +sparc_softmmu_ss = ss.source_set() +sparc_softmmu_ss.add(files( + 'machine.c', + 'monitor.c', +)) + +target_arch += {'sparc': sparc_ss} +target_softmmu_arch += {'sparc': sparc_softmmu_ss} diff --git a/target/tilegx/Makefile.objs b/target/tilegx/Makefile.objs deleted file mode 100644 index 0db778f407..0000000000 --- a/target/tilegx/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-y += cpu.o translate.o helper.o simd_helper.o diff --git a/target/tilegx/meson.build b/target/tilegx/meson.build new file mode 100644 index 0000000000..678590439c --- /dev/null +++ b/target/tilegx/meson.build @@ -0,0 +1,13 @@ +tilegx_ss = ss.source_set() +tilegx_ss.add(files( + 'cpu.c', + 'helper.c', + 'simd_helper.c', + 'translate.c', +)) +tilegx_ss.add(zlib) + +tilegx_softmmu_ss = ss.source_set() + +target_arch += {'tilegx': tilegx_ss} +target_softmmu_arch += {'tilegx': tilegx_softmmu_ss} diff --git a/target/tricore/Makefile.objs b/target/tricore/Makefile.objs deleted file mode 100644 index 281b55f08d..0000000000 --- a/target/tricore/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o gdbstub.o diff --git a/target/tricore/meson.build b/target/tricore/meson.build new file mode 100644 index 0000000000..0ccc829517 --- /dev/null +++ b/target/tricore/meson.build @@ -0,0 +1,15 @@ +tricore_ss = ss.source_set() +tricore_ss.add(files( + 'cpu.c', + 'fpu_helper.c', + 'helper.c', + 'op_helper.c', + 'translate.c', + 'gdbstub.c', +)) +tricore_ss.add(zlib) + +tricore_softmmu_ss = ss.source_set() + +target_arch += {'tricore': tricore_ss} +target_softmmu_arch += {'tricore': tricore_softmmu_ss} diff --git a/target/unicore32/Makefile.objs b/target/unicore32/Makefile.objs deleted file mode 100644 index 35d8bf530d..0000000000 --- a/target/unicore32/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o -obj-y += ucf64_helper.o - -obj-$(CONFIG_SOFTMMU) += softmmu.o - -# Huh? Uses curses directly instead of using ui/console.h interfaces ... -helper.o-cflags := $(CURSES_CFLAGS) -helper.o-libs := $(CURSES_LIBS) diff --git a/target/unicore32/meson.build b/target/unicore32/meson.build new file mode 100644 index 0000000000..0fa78772eb --- /dev/null +++ b/target/unicore32/meson.build @@ -0,0 +1,14 @@ +unicore32_ss = ss.source_set() +unicore32_ss.add(files( + 'cpu.c', + 'helper.c', + 'op_helper.c', + 'translate.c', + 'ucf64_helper.c', +), curses) + +unicore32_softmmu_ss = ss.source_set() +unicore32_softmmu_ss.add(files('softmmu.c')) + +target_arch += {'unicore32': unicore32_ss} +target_softmmu_arch += {'unicore32': unicore32_softmmu_ss} diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs deleted file mode 100644 index c7e7fe6063..0000000000 --- a/target/xtensa/Makefile.objs +++ /dev/null @@ -1,16 +0,0 @@ -obj-y += core-dc232b.o -obj-y += core-dc233c.o -obj-y += core-de212.o -obj-y += core-fsf.o -obj-y += core-sample_controller.o -obj-y += core-test_kc705_be.o -obj-y += core-test_mmuhifi_c3.o -obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o -obj-y += xtensa-isa.o -obj-y += translate.o op_helper.o helper.o cpu.o -obj-$(CONFIG_SOFTMMU) += dbg_helper.o -obj-y += exc_helper.o -obj-y += fpu_helper.o -obj-y += gdbstub.o -obj-$(CONFIG_SOFTMMU) += mmu_helper.o -obj-y += win_helper.o diff --git a/target/xtensa/meson.build b/target/xtensa/meson.build new file mode 100644 index 0000000000..27e453e1d1 --- /dev/null +++ b/target/xtensa/meson.build @@ -0,0 +1,30 @@ +xtensa_ss = ss.source_set() +xtensa_ss.add(files( + 'core-dc232b.c', + 'core-dc233c.c', + 'core-de212.c', + 'core-fsf.c', + 'core-sample_controller.c', + 'core-test_kc705_be.c', + 'core-test_mmuhifi_c3.c', + 'cpu.c', + 'exc_helper.c', + 'fpu_helper.c', + 'gdbstub.c', + 'helper.c', + 'op_helper.c', + 'translate.c', + 'win_helper.c', + 'xtensa-isa.c', +)) + +xtensa_softmmu_ss = ss.source_set() +xtensa_softmmu_ss.add(files( + 'dbg_helper.c', + 'mmu_helper.c', + 'monitor.c', + 'xtensa-semi.c', +)) + +target_arch += {'xtensa': xtensa_ss} +target_softmmu_arch += {'xtensa': xtensa_softmmu_ss} -- cgit v1.2.3-55-g7522 From 1a82878a0840ec963119fdf40895d87861884f40 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sun, 18 Aug 2019 16:13:08 +0400 Subject: meson: accel Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 +- Makefile.target | 1 - accel/Makefile.objs | 6 ------ accel/kvm/Makefile.objs | 2 -- accel/kvm/meson.build | 5 +++++ accel/meson.build | 7 +++++++ accel/stubs/Makefile.objs | 6 ------ accel/stubs/meson.build | 6 ++++++ accel/tcg/Makefile.objs | 9 --------- accel/tcg/meson.build | 15 +++++++++++++++ accel/xen/Makefile.objs | 1 - accel/xen/meson.build | 1 + meson.build | 1 + 13 files changed, 36 insertions(+), 26 deletions(-) delete mode 100644 accel/Makefile.objs delete mode 100644 accel/kvm/Makefile.objs create mode 100644 accel/kvm/meson.build create mode 100644 accel/meson.build delete mode 100644 accel/stubs/Makefile.objs create mode 100644 accel/stubs/meson.build delete mode 100644 accel/tcg/Makefile.objs create mode 100644 accel/tcg/meson.build delete mode 100644 accel/xen/Makefile.objs create mode 100644 accel/xen/meson.build diff --git a/Makefile.objs b/Makefile.objs index c9720a92df..83622c58a5 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -39,7 +39,7 @@ endif # CONFIG_SOFTMMU or CONFIG_TOOLS # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = accel/ +common-obj-y = common-obj-$(CONFIG_AUDIO_ALSA) += audio-alsa$(DSOSUF) common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) diff --git a/Makefile.target b/Makefile.target index 1ab8773402..8633e2b9fe 100644 --- a/Makefile.target +++ b/Makefile.target @@ -110,7 +110,6 @@ obj-y += trace/ ######################################################### # cpu emulator library obj-y += exec.o exec-vary.o -obj-y += accel/ obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o diff --git a/accel/Makefile.objs b/accel/Makefile.objs deleted file mode 100644 index ff72f0d030..0000000000 --- a/accel/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -common-obj-$(CONFIG_SOFTMMU) += accel.o -obj-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_POSIX)) += qtest.o -obj-$(CONFIG_KVM) += kvm/ -obj-$(CONFIG_TCG) += tcg/ -obj-$(CONFIG_XEN) += xen/ -obj-y += stubs/ diff --git a/accel/kvm/Makefile.objs b/accel/kvm/Makefile.objs deleted file mode 100644 index fdfa481578..0000000000 --- a/accel/kvm/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += kvm-all.o -obj-$(call lnot,$(CONFIG_SEV)) += sev-stub.o diff --git a/accel/kvm/meson.build b/accel/kvm/meson.build new file mode 100644 index 0000000000..4db2388e2f --- /dev/null +++ b/accel/kvm/meson.build @@ -0,0 +1,5 @@ +kvm_ss = ss.source_set() +kvm_ss.add(files('kvm-all.c')) +kvm_ss.add(when: 'CONFIG_SEV', if_false: files('sev-stub.c')) + +specific_ss.add_all(when: 'CONFIG_KVM', if_true: kvm_ss) diff --git a/accel/meson.build b/accel/meson.build new file mode 100644 index 0000000000..26c503e480 --- /dev/null +++ b/accel/meson.build @@ -0,0 +1,7 @@ +softmmu_ss.add(files('accel.c')) +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_POSIX'], if_true: files('qtest.c')) + +subdir('kvm') +subdir('tcg') +subdir('xen') +subdir('stubs') diff --git a/accel/stubs/Makefile.objs b/accel/stubs/Makefile.objs deleted file mode 100644 index bbd14e71fb..0000000000 --- a/accel/stubs/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -obj-$(call lnot,$(CONFIG_HAX)) += hax-stub.o -obj-$(call lnot,$(CONFIG_HVF)) += hvf-stub.o -obj-$(call lnot,$(CONFIG_WHPX)) += whpx-stub.o -obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o -obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o -obj-$(call lnot,$(CONFIG_XEN)) += xen-stub.o diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build new file mode 100644 index 0000000000..314e3cfff4 --- /dev/null +++ b/accel/stubs/meson.build @@ -0,0 +1,6 @@ +specific_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c')) +specific_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c')) +specific_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) +specific_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +specific_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c')) +specific_ss.add(when: 'CONFIG_WHPX', if_false: files('whpx-stub.c')) diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs deleted file mode 100644 index a92f2c454b..0000000000 --- a/accel/tcg/Makefile.objs +++ /dev/null @@ -1,9 +0,0 @@ -obj-$(CONFIG_SOFTMMU) += tcg-all.o -obj-$(CONFIG_SOFTMMU) += cputlb.o -obj-y += tcg-runtime.o tcg-runtime-gvec.o -obj-y += cpu-exec.o cpu-exec-common.o translate-all.o -obj-y += translator.o - -obj-$(CONFIG_USER_ONLY) += user-exec.o -obj-$(call lnot,$(CONFIG_SOFTMMU)) += user-exec-stub.o -obj-$(CONFIG_PLUGIN) += plugin-gen.o diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build new file mode 100644 index 0000000000..2a335b50f2 --- /dev/null +++ b/accel/tcg/meson.build @@ -0,0 +1,15 @@ +tcg_ss = ss.source_set() +tcg_ss.add(files( + 'cpu-exec-common.c', + 'cpu-exec.c', + 'tcg-runtime-gvec.c', + 'tcg-runtime.c', + 'translate-all.c', + 'translator.c', +)) +tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) +tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c')) +tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: files('plugin-gen.c')) +specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) + +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tcg-all.c', 'cputlb.c')) diff --git a/accel/xen/Makefile.objs b/accel/xen/Makefile.objs deleted file mode 100644 index 7482cfb436..0000000000 --- a/accel/xen/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-y += xen-all.o diff --git a/accel/xen/meson.build b/accel/xen/meson.build new file mode 100644 index 0000000000..002bdb03c6 --- /dev/null +++ b/accel/xen/meson.build @@ -0,0 +1 @@ +specific_ss.add(when: 'CONFIG_XEN', if_true: files('xen-all.c')) diff --git a/meson.build b/meson.build index ac59ccc935..baf9b69e99 100644 --- a/meson.build +++ b/meson.build @@ -704,6 +704,7 @@ subdir('monitor') subdir('net') subdir('replay') subdir('hw') +subdir('accel') # needed for fuzzing binaries subdir('tests/qtest/libqos') -- cgit v1.2.3-55-g7522 From 3a30446aed8497b5928576c6d1aedba557363934 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sun, 18 Aug 2019 16:13:08 +0400 Subject: meson: linux-user The most interesting or most complicated part here is the syscall_nr.h generators. In order to keep the generation logic all in meson.build, I am adding to config_target the name of the .tbl file, and making the generated file syscall_nr.h for input file syscall.tbl. For architectures where the input file is not named syscall_nr.tbl, syscall_nr.h has to be a source file; it's just a forwarder for x86 (i386/x86_64), while for MIPS64 it chooses between N32 and N64 ABIs. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 3 --- configure | 27 ++++++++++++--------------- linux-user/Makefile.objs | 25 ------------------------- linux-user/alpha/Makefile.objs | 5 ----- linux-user/alpha/meson.build | 5 +++++ linux-user/arm/Makefile.objs | 8 -------- linux-user/arm/meson.build | 10 ++++++++++ linux-user/arm/nwfpe/Makefile.objs | 2 -- linux-user/arm/nwfpe/meson.build | 10 ++++++++++ linux-user/hppa/Makefile.objs | 5 ----- linux-user/hppa/meson.build | 5 +++++ linux-user/i386/Makefile.objs | 5 ----- linux-user/i386/meson.build | 5 +++++ linux-user/i386/syscall_nr.h | 1 + linux-user/m68k/Makefile.objs | 5 ----- linux-user/m68k/meson.build | 5 +++++ linux-user/meson.build | 37 +++++++++++++++++++++++++++++++++++++ linux-user/microblaze/Makefile.objs | 5 ----- linux-user/microblaze/meson.build | 5 +++++ linux-user/mips/Makefile.objs | 5 ----- linux-user/mips/meson.build | 6 ++++++ linux-user/mips/syscall_nr.h | 1 + linux-user/mips64/Makefile.objs | 12 ------------ linux-user/mips64/meson.build | 6 ++++++ linux-user/mips64/syscall_nr.h | 7 +++++++ linux-user/ppc/Makefile.objs | 6 ------ linux-user/ppc/meson.build | 5 +++++ linux-user/s390x/Makefile.objs | 5 ----- linux-user/s390x/meson.build | 5 +++++ linux-user/sh4/Makefile.objs | 5 ----- linux-user/sh4/meson.build | 5 +++++ linux-user/sparc/Makefile.objs | 5 ----- linux-user/sparc/meson.build | 5 +++++ linux-user/sparc64/Makefile.objs | 5 ----- linux-user/sparc64/meson.build | 5 +++++ linux-user/x86_64/Makefile.objs | 5 ----- linux-user/x86_64/meson.build | 5 +++++ linux-user/x86_64/syscall_nr.h | 1 + linux-user/xtensa/Makefile.objs | 5 ----- linux-user/xtensa/meson.build | 5 +++++ meson.build | 16 +++++++++++++++- 41 files changed, 166 insertions(+), 132 deletions(-) delete mode 100644 linux-user/Makefile.objs delete mode 100644 linux-user/alpha/Makefile.objs create mode 100644 linux-user/alpha/meson.build delete mode 100644 linux-user/arm/Makefile.objs create mode 100644 linux-user/arm/meson.build delete mode 100644 linux-user/arm/nwfpe/Makefile.objs create mode 100644 linux-user/arm/nwfpe/meson.build delete mode 100644 linux-user/hppa/Makefile.objs create mode 100644 linux-user/hppa/meson.build delete mode 100644 linux-user/i386/Makefile.objs create mode 100644 linux-user/i386/meson.build create mode 100644 linux-user/i386/syscall_nr.h delete mode 100644 linux-user/m68k/Makefile.objs create mode 100644 linux-user/m68k/meson.build create mode 100644 linux-user/meson.build delete mode 100644 linux-user/microblaze/Makefile.objs create mode 100644 linux-user/microblaze/meson.build delete mode 100644 linux-user/mips/Makefile.objs create mode 100644 linux-user/mips/meson.build create mode 100644 linux-user/mips/syscall_nr.h delete mode 100644 linux-user/mips64/Makefile.objs create mode 100644 linux-user/mips64/meson.build create mode 100644 linux-user/mips64/syscall_nr.h delete mode 100644 linux-user/ppc/Makefile.objs create mode 100644 linux-user/ppc/meson.build delete mode 100644 linux-user/s390x/Makefile.objs create mode 100644 linux-user/s390x/meson.build delete mode 100644 linux-user/sh4/Makefile.objs create mode 100644 linux-user/sh4/meson.build delete mode 100644 linux-user/sparc/Makefile.objs create mode 100644 linux-user/sparc/meson.build delete mode 100644 linux-user/sparc64/Makefile.objs create mode 100644 linux-user/sparc64/meson.build delete mode 100644 linux-user/x86_64/Makefile.objs create mode 100644 linux-user/x86_64/meson.build create mode 100644 linux-user/x86_64/syscall_nr.h delete mode 100644 linux-user/xtensa/Makefile.objs create mode 100644 linux-user/xtensa/meson.build diff --git a/Makefile.target b/Makefile.target index 8633e2b9fe..a68859d7c2 100644 --- a/Makefile.target +++ b/Makefile.target @@ -131,9 +131,6 @@ QEMU_CFLAGS+=-I$(SRC_PATH)/linux-user/$(TARGET_ABI_DIR) \ -I$(SRC_PATH)/linux-user \ -Ilinux-user/$(TARGET_ABI_DIR) -obj-y += linux-user/ -obj-y += gdbstub.o thunk.o - endif #CONFIG_LINUX_USER ######################################################### diff --git a/configure b/configure index ddbe1f4569..0c73c5f877 100755 --- a/configure +++ b/configure @@ -1992,20 +1992,6 @@ fi # Remove old dependency files to make sure that they get properly regenerated rm -f */config-devices.mak.d -# Remove syscall_nr.h to be sure they will be regenerated in the build -# directory, not in the source directory -for arch in alpha hppa m68k xtensa sh4 microblaze arm ppc s390x sparc sparc64 \ - i386 x86_64 mips mips64 ; do - # remove the file if it has been generated in the source directory - rm -f "${source_path}/linux-user/${arch}/syscall_nr.h" - # remove the dependency files - for target in ${arch}*-linux-user ; do - test -d "${target}" && find "${target}" -type f -name "*.d" \ - -exec grep -q "${source_path}/linux-user/${arch}/syscall_nr.h" {} \; \ - -print | while read file ; do rm "${file}" "${file%.d}.o" ; done - done -done - if test -z "$python" then error_exit "Python not found. Use --python=/path/to/python" @@ -7999,18 +7985,22 @@ gdb_xml_files="" TARGET_ARCH="$target_name" TARGET_BASE_ARCH="" TARGET_ABI_DIR="" +TARGET_SYSTBL_ABI="" +TARGET_SYSTBL="" case "$target_name" in i386) mttcg="yes" gdb_xml_files="i386-32bit.xml" TARGET_SYSTBL_ABI=i386 + TARGET_SYSTBL=syscall_32.tbl ;; x86_64) TARGET_BASE_ARCH=i386 TARGET_SYSTBL_ABI=common,64 + TARGET_SYSTBL=syscall_64.tbl mttcg="yes" - gdb_xml_files="i386-64bit.xml" + gdb_xml_files="i386-64bit.xml" ;; alpha) mttcg="yes" @@ -8058,6 +8048,7 @@ case "$target_name" in TARGET_ARCH=mips echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak TARGET_SYSTBL_ABI=o32 + TARGET_SYSTBL=syscall_o32.tbl ;; mipsn32|mipsn32el) mttcg="yes" @@ -8066,6 +8057,7 @@ case "$target_name" in echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak echo "TARGET_ABI32=y" >> $config_target_mak TARGET_SYSTBL_ABI=n32 + TARGET_SYSTBL=syscall_n32.tbl ;; mips64|mips64el) mttcg="no" @@ -8073,6 +8065,7 @@ case "$target_name" in TARGET_BASE_ARCH=mips echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak TARGET_SYSTBL_ABI=n64 + TARGET_SYSTBL=syscall_n64.tbl ;; moxie) ;; @@ -8171,6 +8164,9 @@ esac if [ "$TARGET_BASE_ARCH" = "" ]; then TARGET_BASE_ARCH=$TARGET_ARCH fi +if [ "$TARGET_SYSTBL_ABI" != "" ] && [ "$TARGET_SYSTBL" = "" ]; then + TARGET_SYSTBL=syscall.tbl +fi symlink "$source_path/Makefile.target" "$target_dir/Makefile" @@ -8191,6 +8187,7 @@ if [ "$HOST_VARIANT_DIR" != "" ]; then fi if [ "$TARGET_SYSTBL_ABI" != "" ]; then echo "TARGET_SYSTBL_ABI=$TARGET_SYSTBL_ABI" >> $config_target_mak + echo "TARGET_SYSTBL=$TARGET_SYSTBL" >> $config_target_mak fi if supported_xen_target $target; then diff --git a/linux-user/Makefile.objs b/linux-user/Makefile.objs deleted file mode 100644 index 1940910a73..0000000000 --- a/linux-user/Makefile.objs +++ /dev/null @@ -1,25 +0,0 @@ -obj-y = main.o syscall.o strace.o mmap.o signal.o \ - elfload.o linuxload.o uaccess.o uname.o \ - safe-syscall.o $(TARGET_ABI_DIR)/signal.o \ - $(TARGET_ABI_DIR)/cpu_loop.o exit.o fd-trans.o - -obj-$(TARGET_HAS_BFLT) += flatload.o -obj-$(TARGET_I386) += vm86.o -obj-$(TARGET_AARCH64) += arm/semihost.o - -obj-$(TARGET_ALPHA) += alpha/ -obj-$(TARGET_ARM) += arm/ -obj-$(TARGET_HPPA) += hppa/ -obj-$(TARGET_I386) += i386/ -obj-$(TARGET_M68K) += m68k/ -obj-$(TARGET_MICROBLAZE) += microblaze/ -obj-$(TARGET_MIPS) += mips/ -obj-$(TARGET_MIPS64) += mips64/ -obj-$(TARGET_PPC) += ppc/ -obj-$(TARGET_PPC64) += ppc/ -obj-$(TARGET_S390X) += s390x/ -obj-$(TARGET_SH4) += sh4/ -obj-$(TARGET_SPARC) += sparc/ -obj-$(TARGET_SPARC64) += $(TARGET_ABI_DIR)/ -obj-$(TARGET_X86_64) += x86_64/ -obj-$(TARGET_XTENSA) += xtensa/ diff --git a/linux-user/alpha/Makefile.objs b/linux-user/alpha/Makefile.objs deleted file mode 100644 index d6397a70ab..0000000000 --- a/linux-user/alpha/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/alpha/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/alpha/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/alpha/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/alpha/meson.build b/linux-user/alpha/meson.build new file mode 100644 index 0000000000..a3cd22d2c4 --- /dev/null +++ b/linux-user/alpha/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'alpha': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/arm/Makefile.objs b/linux-user/arm/Makefile.objs deleted file mode 100644 index c7eb94dcba..0000000000 --- a/linux-user/arm/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -obj-$(TARGET_ARM) += nwfpe/ -obj-$(TARGET_ARM) += semihost.o - -generated-files-y += linux-user/arm/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/arm/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/arm/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build new file mode 100644 index 0000000000..432984b58e --- /dev/null +++ b/linux-user/arm/meson.build @@ -0,0 +1,10 @@ +linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) +linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) + +subdir('nwfpe') + +syscall_nr_generators += { + 'arm': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/arm/nwfpe/Makefile.objs b/linux-user/arm/nwfpe/Makefile.objs deleted file mode 100644 index 51b0c32c2a..0000000000 --- a/linux-user/arm/nwfpe/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y = fpa11.o fpa11_cpdo.o fpa11_cpdt.o fpa11_cprt.o fpopcode.o -obj-y += single_cpdo.o double_cpdo.o extended_cpdo.o diff --git a/linux-user/arm/nwfpe/meson.build b/linux-user/arm/nwfpe/meson.build new file mode 100644 index 0000000000..1c27e55f2a --- /dev/null +++ b/linux-user/arm/nwfpe/meson.build @@ -0,0 +1,10 @@ +linux_user_ss.add(when: 'TARGET_ARM', if_true: files( + 'double_cpdo.c', + 'extended_cpdo.c', + 'fpa11.c', + 'fpa11_cpdo.c', + 'fpa11_cpdt.c', + 'fpa11_cprt.c', + 'fpopcode.c', + 'single_cpdo.c', +)) diff --git a/linux-user/hppa/Makefile.objs b/linux-user/hppa/Makefile.objs deleted file mode 100644 index f8368be6f3..0000000000 --- a/linux-user/hppa/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/hppa/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/hppa/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/hppa/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/hppa/meson.build b/linux-user/hppa/meson.build new file mode 100644 index 0000000000..4709508a09 --- /dev/null +++ b/linux-user/hppa/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'hppa': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/i386/Makefile.objs b/linux-user/i386/Makefile.objs deleted file mode 100644 index c25cf17bfb..0000000000 --- a/linux-user/i386/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/i386/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/i386/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/i386/syscall_32.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/i386/meson.build b/linux-user/i386/meson.build new file mode 100644 index 0000000000..ee523019a5 --- /dev/null +++ b/linux-user/i386/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'i386': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/i386/syscall_nr.h b/linux-user/i386/syscall_nr.h new file mode 100644 index 0000000000..976caab67f --- /dev/null +++ b/linux-user/i386/syscall_nr.h @@ -0,0 +1 @@ +#include "syscall_32_nr.h" diff --git a/linux-user/m68k/Makefile.objs b/linux-user/m68k/Makefile.objs deleted file mode 100644 index 961bd05c23..0000000000 --- a/linux-user/m68k/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/m68k/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/m68k/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/m68k/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/m68k/meson.build b/linux-user/m68k/meson.build new file mode 100644 index 0000000000..c0f436fe50 --- /dev/null +++ b/linux-user/m68k/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'm68k': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/meson.build b/linux-user/meson.build new file mode 100644 index 0000000000..2b94e4ba24 --- /dev/null +++ b/linux-user/meson.build @@ -0,0 +1,37 @@ +linux_user_ss.add(files( + 'elfload.c', + 'exit.c', + 'fd-trans.c', + 'linuxload.c', + 'main.c', + 'mmap.c', + 'safe-syscall.S', + 'signal.c', + 'strace.c', + 'syscall.c', + 'uaccess.c', + 'uname.c', +)) +linux_user_ss.add(rt) + +linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) +linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) + + +syscall_nr_generators = {} + +subdir('alpha') +subdir('arm') +subdir('hppa') +subdir('i386') +subdir('m68k') +subdir('microblaze') +subdir('mips64') +subdir('mips') +subdir('ppc') +subdir('s390x') +subdir('sh4') +subdir('sparc64') +subdir('sparc') +subdir('x86_64') +subdir('xtensa') diff --git a/linux-user/microblaze/Makefile.objs b/linux-user/microblaze/Makefile.objs deleted file mode 100644 index bb8b318dda..0000000000 --- a/linux-user/microblaze/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/microblaze/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/microblaze/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/microblaze/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/microblaze/meson.build b/linux-user/microblaze/meson.build new file mode 100644 index 0000000000..f749d89418 --- /dev/null +++ b/linux-user/microblaze/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'microblaze': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/mips/Makefile.objs b/linux-user/mips/Makefile.objs deleted file mode 100644 index 9be4de07d9..0000000000 --- a/linux-user/mips/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/mips/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/mips/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/mips/syscall_o32.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI) "" 4000,"GEN","$@") diff --git a/linux-user/mips/meson.build b/linux-user/mips/meson.build new file mode 100644 index 0000000000..262a35703b --- /dev/null +++ b/linux-user/mips/meson.build @@ -0,0 +1,6 @@ +syscall_nr_generators += { + 'mips': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@', + '', '4000' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/mips/syscall_nr.h b/linux-user/mips/syscall_nr.h new file mode 100644 index 0000000000..45d133c6f9 --- /dev/null +++ b/linux-user/mips/syscall_nr.h @@ -0,0 +1 @@ +#include "syscall_o32_nr.h" diff --git a/linux-user/mips64/Makefile.objs b/linux-user/mips64/Makefile.objs deleted file mode 100644 index 573448f956..0000000000 --- a/linux-user/mips64/Makefile.objs +++ /dev/null @@ -1,12 +0,0 @@ -generated-files-y += linux-user/$(TARGET_ABI_DIR)/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)/syscallhdr.sh - -ifeq ($(TARGET_SYSTBL_ABI),n32) -%/syscall_nr.h: $(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)/syscall_n32.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ n32 "" 6000,"GEN","$@") -endif -ifeq ($(TARGET_SYSTBL_ABI),n64) -%/syscall_nr.h: $(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)/syscall_n64.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ n64 "" 5000,"GEN","$@") -endif diff --git a/linux-user/mips64/meson.build b/linux-user/mips64/meson.build new file mode 100644 index 0000000000..0caab5fabd --- /dev/null +++ b/linux-user/mips64/meson.build @@ -0,0 +1,6 @@ +syscall_nr_generators += { + 'mips64': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@', + '', 'TARGET_SYSCALL_OFFSET' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/syscall_nr.h new file mode 100644 index 0000000000..672f2fa51c --- /dev/null +++ b/linux-user/mips64/syscall_nr.h @@ -0,0 +1,7 @@ +#ifdef TARGET_ABI_MIPSN32 +#define TARGET_SYSCALL_OFFSET 6000 +#include "syscall_n32_nr.h" +#else +#define TARGET_SYSCALL_OFFSET 5000 +#include "syscall_n64_nr.h" +#endif diff --git a/linux-user/ppc/Makefile.objs b/linux-user/ppc/Makefile.objs deleted file mode 100644 index be92e67eb1..0000000000 --- a/linux-user/ppc/Makefile.objs +++ /dev/null @@ -1,6 +0,0 @@ -generated-files-y += linux-user/$(TARGET_ABI_DIR)/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)/syscallhdr.sh - -%/syscall_nr.h: $(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/ppc/meson.build b/linux-user/ppc/meson.build new file mode 100644 index 0000000000..19fead7bc8 --- /dev/null +++ b/linux-user/ppc/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'ppc': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/s390x/Makefile.objs b/linux-user/s390x/Makefile.objs deleted file mode 100644 index f30f1625cc..0000000000 --- a/linux-user/s390x/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/s390x/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/s390x/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/s390x/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/s390x/meson.build b/linux-user/s390x/meson.build new file mode 100644 index 0000000000..0781ccea1d --- /dev/null +++ b/linux-user/s390x/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 's390x': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/sh4/Makefile.objs b/linux-user/sh4/Makefile.objs deleted file mode 100644 index 83fc939570..0000000000 --- a/linux-user/sh4/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/sh4/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/sh4/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/sh4/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/sh4/meson.build b/linux-user/sh4/meson.build new file mode 100644 index 0000000000..3bc3a6924a --- /dev/null +++ b/linux-user/sh4/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'sh4': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/sparc/Makefile.objs b/linux-user/sparc/Makefile.objs deleted file mode 100644 index 29d3f066cb..0000000000 --- a/linux-user/sparc/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/sparc/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/sparc/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/sparc/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/sparc/meson.build b/linux-user/sparc/meson.build new file mode 100644 index 0000000000..51a9c7795c --- /dev/null +++ b/linux-user/sparc/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'sparc': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/sparc64/Makefile.objs b/linux-user/sparc64/Makefile.objs deleted file mode 100644 index afcd535bc4..0000000000 --- a/linux-user/sparc64/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/sparc64/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/sparc64/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/sparc/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/sparc64/meson.build b/linux-user/sparc64/meson.build new file mode 100644 index 0000000000..9527a40ed4 --- /dev/null +++ b/linux-user/sparc64/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'sparc64': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/x86_64/Makefile.objs b/linux-user/x86_64/Makefile.objs deleted file mode 100644 index 2cef1d48be..0000000000 --- a/linux-user/x86_64/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/x86_64/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/x86_64/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/x86_64/syscall_64.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/x86_64/meson.build b/linux-user/x86_64/meson.build new file mode 100644 index 0000000000..203af9a60c --- /dev/null +++ b/linux-user/x86_64/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'x86_64': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/linux-user/x86_64/syscall_nr.h b/linux-user/x86_64/syscall_nr.h new file mode 100644 index 0000000000..760302cb3e --- /dev/null +++ b/linux-user/x86_64/syscall_nr.h @@ -0,0 +1 @@ +#include "syscall_64_nr.h" diff --git a/linux-user/xtensa/Makefile.objs b/linux-user/xtensa/Makefile.objs deleted file mode 100644 index d4be1b7455..0000000000 --- a/linux-user/xtensa/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -generated-files-y += linux-user/xtensa/syscall_nr.h - -syshdr := $(SRC_PATH)/linux-user/xtensa/syscallhdr.sh -%/syscall_nr.h: $(SRC_PATH)/linux-user/xtensa/syscall.tbl $(syshdr) - $(call quiet-command, sh $(syshdr) $< $@ $(TARGET_SYSTBL_ABI),"GEN","$@") diff --git a/linux-user/xtensa/meson.build b/linux-user/xtensa/meson.build new file mode 100644 index 0000000000..de77f3b66a --- /dev/null +++ b/linux-user/xtensa/meson.build @@ -0,0 +1,5 @@ +syscall_nr_generators += { + 'xtensa': generator(sh, + arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], + output: '@BASENAME@_nr.h') +} diff --git a/meson.build b/meson.build index baf9b69e99..490f3d9c75 100644 --- a/meson.build +++ b/meson.build @@ -705,6 +705,10 @@ subdir('net') subdir('replay') subdir('hw') subdir('accel') +subdir('linux-user') + +linux_user_ss.add(files('gdbstub.c', 'thunk.c')) +specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) # needed for fuzzing binaries subdir('tests/qtest/libqos') @@ -802,6 +806,7 @@ foreach target : target_dirs arch_srcs += config_devices_h[target] else + abi = config_target['TARGET_ABI_DIR'] target_type='user' qemu_target_name = 'qemu-' + target_name if 'CONFIG_LINUX_USER' in config_target @@ -812,8 +817,17 @@ foreach target : target_dirs endif target_inc += include_directories( base_dir, - base_dir / config_target['TARGET_ABI_DIR'], + base_dir / abi, ) + if 'CONFIG_LINUX_USER' in config_target + dir = base_dir / abi + arch_srcs += files(dir / 'signal.c', dir / 'cpu_loop.c') + if config_target.has_key('TARGET_SYSTBL_ABI') + arch_srcs += \ + syscall_nr_generators[abi].process(base_dir / abi / config_target['TARGET_SYSTBL'], + extra_args : config_target['TARGET_SYSTBL_ABI']) + endif + endif endif t = target_arch[arch].apply(config_target, strict: false) -- cgit v1.2.3-55-g7522 From b309c321256fc48cd7164c55582eaa37bc77b6ab Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sun, 18 Aug 2019 19:20:37 +0400 Subject: meson: bsd-user Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 3 --- bsd-user/Makefile.objs | 2 -- bsd-user/meson.build | 10 ++++++++++ meson.build | 4 ++++ 4 files changed, 14 insertions(+), 5 deletions(-) delete mode 100644 bsd-user/Makefile.objs create mode 100644 bsd-user/meson.build diff --git a/Makefile.target b/Makefile.target index a68859d7c2..5c099fa79f 100644 --- a/Makefile.target +++ b/Makefile.target @@ -141,9 +141,6 @@ ifdef CONFIG_BSD_USER QEMU_CFLAGS+=-I$(SRC_PATH)/bsd-user -I$(SRC_PATH)/bsd-user/$(TARGET_ABI_DIR) \ -I$(SRC_PATH)/bsd-user/$(HOST_VARIANT_DIR) -obj-y += bsd-user/ -obj-y += gdbstub.o - endif #CONFIG_BSD_USER ######################################################### diff --git a/bsd-user/Makefile.objs b/bsd-user/Makefile.objs deleted file mode 100644 index 5e77f57782..0000000000 --- a/bsd-user/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -obj-y = main.o bsdload.o elfload.o mmap.o signal.o strace.o syscall.o \ - uaccess.o diff --git a/bsd-user/meson.build b/bsd-user/meson.build new file mode 100644 index 0000000000..0369549340 --- /dev/null +++ b/bsd-user/meson.build @@ -0,0 +1,10 @@ +bsd_user_ss.add(files( + 'bsdload.c', + 'elfload.c', + 'main.c', + 'mmap.c', + 'signal.c', + 'strace.c', + 'syscall.c', + 'uaccess.c', +)) diff --git a/meson.build b/meson.build index 490f3d9c75..df63f15ee7 100644 --- a/meson.build +++ b/meson.build @@ -705,8 +705,12 @@ subdir('net') subdir('replay') subdir('hw') subdir('accel') +subdir('bsd-user') subdir('linux-user') +bsd_user_ss.add(files('gdbstub.c')) +specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) + linux_user_ss.add(files('gdbstub.c', 'thunk.c')) specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) -- cgit v1.2.3-55-g7522 From c9322ab5bfe17e9db099646978f43a745816073e Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Sun, 18 Aug 2019 19:51:17 +0400 Subject: meson: cpu-emu Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 12 ------------ configure | 10 +++++++++- meson.build | 37 +++++++++++++++++++++++++++++++++++++ scripts/feature_to_c.sh | 24 ++++++++---------------- 4 files changed, 54 insertions(+), 29 deletions(-) diff --git a/Makefile.target b/Makefile.target index 5c099fa79f..c180b4cb38 100644 --- a/Makefile.target +++ b/Makefile.target @@ -108,15 +108,6 @@ obj-y += $(LIBQEMU) obj-y += trace/ ######################################################### -# cpu emulator library -obj-y += exec.o exec-vary.o -obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o -obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o -obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o -obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o -obj-$(CONFIG_TCG) += fpu/softfloat.o -obj-y += disas.o -obj-$(call notempty,$(TARGET_XML_FILES)) += gdbstub-xml.o LIBS := $(libs_cpu) $(LIBS) obj-$(CONFIG_PLUGIN) += plugins/ @@ -200,9 +191,6 @@ ifdef CONFIG_DARWIN $(call quiet-command,SetFile -a C $@,"SETFILE","$(TARGET_DIR)$@") endif -gdbstub-xml.c: $(TARGET_XML_FILES) $(SRC_PATH)/scripts/feature_to_c.sh - $(call quiet-command,rm -f $@ && $(SHELL) $(SRC_PATH)/scripts/feature_to_c.sh $@ $(TARGET_XML_FILES),"GEN","$(TARGET_DIR)$@") - clean: clean-target rm -f *.a *~ $(PROGS) rm -f $(shell find . -name '*.[od]') diff --git a/configure b/configure index 0c73c5f877..2f5dfbc5b0 100755 --- a/configure +++ b/configure @@ -5478,9 +5478,13 @@ case "$capstone" in LIBCAPSTONE=libcapstone.a fi libs_cpu="-L$PWD/capstone -lcapstone $libs_cpu" + capstone_libs="-L$PWD/capstone -lcapstone" + capstone_cflags="-I${source_path}/capstone/include" ;; system) + capstone_libs="$($pkg_config --libs capstone)" + capstone_cflags="$($pkg_config --cflags capstone)" QEMU_CFLAGS="$QEMU_CFLAGS $($pkg_config --cflags capstone)" libs_cpu="$($pkg_config --libs capstone) $libs_cpu" ;; @@ -7712,6 +7716,8 @@ if test "$ivshmem" = "yes" ; then fi if test "$capstone" != "no" ; then echo "CONFIG_CAPSTONE=y" >> $config_host_mak + echo "CAPSTONE_CFLAGS=$capstone_cflags" >> $config_host_mak + echo "CAPSTONE_LIBS=$capstone_libs" >> $config_host_mak fi if test "$debug_mutex" = "yes" ; then echo "CONFIG_DEBUG_MUTEX=y" >> $config_host_mak @@ -7732,6 +7738,8 @@ fi if test "$libpmem" = "yes" ; then echo "CONFIG_LIBPMEM=y" >> $config_host_mak + echo "LIBPMEM_LIBS=$libpmem_libs" >> $config_host_mak + echo "LIBPMEM_CFLAGS=$libpmem_cflags" >> $config_host_mak fi if test "$libdaxctl" = "yes" ; then @@ -8230,7 +8238,7 @@ fi list="" if test ! -z "$gdb_xml_files" ; then for x in $gdb_xml_files; do - list="$list $source_path/gdb-xml/$x" + list="$list gdb-xml/$x" done echo "TARGET_XML_FILES=$list" >> $config_target_mak fi diff --git a/meson.build b/meson.build index df63f15ee7..5b1608df09 100644 --- a/meson.build +++ b/meson.build @@ -345,6 +345,16 @@ if 'CONFIG_USB_LIBUSB' in config_host libusb = declare_dependency(compile_args: config_host['LIBUSB_CFLAGS'].split(), link_args: config_host['LIBUSB_LIBS'].split()) endif +capstone = not_found +if 'CONFIG_CAPSTONE' in config_host + capstone = declare_dependency(compile_args: config_host['CAPSTONE_CFLAGS'].split(), + link_args: config_host['CAPSTONE_LIBS'].split()) +endif +libpmem = not_found +if 'CONFIG_LIBPMEM' in config_host + libpmem = declare_dependency(compile_args: config_host['LIBPMEM_CFLAGS'].split(), + link_args: config_host['LIBPMEM_LIBS'].split()) +endif create_config = find_program('scripts/create_config') minikconf = find_program('scripts/minikconf.py') @@ -529,6 +539,8 @@ target_softmmu_arch = {} # Trace files # ############### +# TODO: add each directory to the subdirs from its own meson.build, once +# we have those trace_events_subdirs = [ 'accel/kvm', 'accel/tcg', @@ -697,6 +709,20 @@ softmmu_ss.add(when: ['CONFIG_FDT', fdt], if_true: [files('device_tree.c')]) common_ss.add(files('cpus-common.c')) subdir('softmmu') + +specific_ss.add(files('disas.c', 'exec.c', 'gdbstub.c'), capstone, libpmem) +specific_ss.add(files('exec-vary.c')) +specific_ss.add(when: 'CONFIG_TCG', if_true: files( + 'fpu/softfloat.c', + 'tcg/optimize.c', + 'tcg/tcg-common.c', + 'tcg/tcg-op-gvec.c', + 'tcg/tcg-op-vec.c', + 'tcg/tcg-op.c', + 'tcg/tcg.c', +)) +specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.c', 'tcg/tci.c')) + subdir('backends') subdir('disas') subdir('migration') @@ -788,6 +814,8 @@ common_all = static_library('common', dependencies: common_all.dependencies(), name_suffix: 'fa') +feature_to_c = find_program('scripts/feature_to_c.sh') + foreach target : target_dirs config_target = config_target_mak[target] target_name = config_target['TARGET_NAME'] @@ -834,6 +862,15 @@ foreach target : target_dirs endif endif + if 'TARGET_XML_FILES' in config_target + gdbstub_xml = custom_target(target + '-gdbstub-xml.c', + output: target + '-gdbstub-xml.c', + input: files(config_target['TARGET_XML_FILES'].split()), + command: [feature_to_c, '@INPUT@'], + capture: true) + arch_srcs += gdbstub_xml + endif + t = target_arch[arch].apply(config_target, strict: false) arch_srcs += t.sources() diff --git a/scripts/feature_to_c.sh b/scripts/feature_to_c.sh index c8ce9b88f6..b1169899c1 100644 --- a/scripts/feature_to_c.sh +++ b/scripts/feature_to_c.sh @@ -19,16 +19,8 @@ # You should have received a copy of the GNU General Public License # along with this program; if not, see . -output=$1 -shift - -if test -z "$output" || test -z "$1"; then - echo "Usage: $0 OUTPUTFILE INPUTFILE..." - exit 1 -fi - -if test -e "$output"; then - echo "Output file \"$output\" already exists; refusing to overwrite." +if test -z "$1"; then + echo "Usage: $0 INPUTFILE..." exit 1 fi @@ -60,17 +52,17 @@ for input; do printf "'\''\\n'\'', \n" } END { print " 0 };" - }' < $input >> $output + }' < $input done -echo >> $output -echo "const char *const xml_builtin[][2] = {" >> $output +echo +echo "const char *const xml_builtin[][2] = {" for input; do basename=$(echo $input | sed 's,.*/,,') arrayname=xml_feature_$(echo $input | sed 's,.*/,,; s/[-.]/_/g') - echo " { \"$basename\", $arrayname }," >> $output + echo " { \"$basename\", $arrayname }," done -echo " { (char *)0, (char *)0 }" >> $output -echo "};" >> $output +echo " { (char *)0, (char *)0 }" +echo "};" -- cgit v1.2.3-55-g7522 From f556b4a10d3ccd6cad01f704e4ccb2252520d61e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Jan 2020 13:08:01 +0100 Subject: meson: plugins For now link arguments end up in Makefile.target, they will move to the right place soon. Signed-off-by: Paolo Bonzini --- Makefile | 8 +------- Makefile.target | 12 ++++++++++-- meson.build | 5 +++++ plugins/Makefile.objs | 21 --------------------- plugins/meson.build | 5 +++++ 5 files changed, 21 insertions(+), 30 deletions(-) delete mode 100644 plugins/Makefile.objs create mode 100644 plugins/meson.build diff --git a/Makefile b/Makefile index ca51abfd8c..ae0aa62082 100644 --- a/Makefile +++ b/Makefile @@ -433,13 +433,10 @@ endif ICON_SIZES=16x16 24x24 32x32 48x48 64x64 128x128 256x256 512x512 -install-includedir: - $(INSTALL_DIR) "$(DESTDIR)$(includedir)" - # Needed by "meson install" export DESTDIR install: all $(if $(BUILD_DOCS),install-doc) \ - install-datadir install-localstatedir install-includedir \ + install-datadir install-localstatedir \ recurse-install ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_PROG) "scripts/qemu-trace-stap" $(DESTDIR)$(bindir) @@ -465,9 +462,6 @@ endif "$(DESTDIR)$(qemu_desktopdir)/qemu.desktop" ifdef CONFIG_GTK $(MAKE) -C po $@ -endif -ifeq ($(CONFIG_PLUGIN),y) - $(INSTALL_DATA) $(SRC_PATH)/include/qemu/qemu-plugin.h "$(DESTDIR)$(includedir)/qemu-plugin.h" endif $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/keymaps" set -e; for x in $(KEYMAPS); do \ diff --git a/Makefile.target b/Makefile.target index c180b4cb38..2b7280b272 100644 --- a/Makefile.target +++ b/Makefile.target @@ -110,8 +110,6 @@ obj-y += trace/ ######################################################### LIBS := $(libs_cpu) $(LIBS) -obj-$(CONFIG_PLUGIN) += plugins/ - ######################################################### # Linux user emulator target @@ -153,6 +151,16 @@ LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) LIBS := $(LIBS) $(VIRGL_LIBS) $(CURSES_LIBS) +ifeq ($(CONFIG_PLUGIN),y) +ifdef CONFIG_HAS_LD_DYNAMIC_LIST +LIBS += -Wl,--dynamic-list=$(BUILD_DIR)/qemu-plugins-ld.symbols +else +ifdef CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST +LIBS += -Wl,-exported_symbols_list,$(BUILD_DIR)/qemu-plugins-ld64.symbols +endif +endif +endif + generated-files-y += hmp-commands.h hmp-commands-info.h endif # CONFIG_SOFTMMU diff --git a/meson.build b/meson.build index 5b1608df09..fa47410c29 100644 --- a/meson.build +++ b/meson.build @@ -731,6 +731,7 @@ subdir('net') subdir('replay') subdir('hw') subdir('accel') +subdir('plugins') subdir('bsd-user') subdir('linux-user') @@ -899,6 +900,10 @@ endforeach # Other build targets +if 'CONFIG_PLUGIN' in config_host + install_headers('include/qemu/qemu-plugin.h') +endif + if 'CONFIG_GUEST_AGENT' in config_host subdir('qga') endif diff --git a/plugins/Makefile.objs b/plugins/Makefile.objs deleted file mode 100644 index 6f14d91ccb..0000000000 --- a/plugins/Makefile.objs +++ /dev/null @@ -1,21 +0,0 @@ -# -# Plugin Support -# - -obj-y += loader.o -obj-y += core.o -obj-y += api.o - -# Abuse -libs suffix to only link with --dynamic-list/-exported_symbols_list -# when the final binary includes the plugin object. -# -# Note that simply setting LDFLAGS is not enough: we build binaries that -# never link plugin.o, and the linker might fail (at least ld64 does) -# if the symbols in the list are not in the output binary. -ifdef CONFIG_HAS_LD_DYNAMIC_LIST -api.o-libs := -Wl,--dynamic-list=$(BUILD_DIR)/qemu-plugins-ld.symbols -else -ifdef CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST -api.o-libs := -Wl,-exported_symbols_list,$(BUILD_DIR)/qemu-plugins-ld64.symbols -endif -endif diff --git a/plugins/meson.build b/plugins/meson.build new file mode 100644 index 0000000000..9608e5293f --- /dev/null +++ b/plugins/meson.build @@ -0,0 +1,5 @@ +specific_ss.add(when: 'CONFIG_PLUGIN', if_true: [files( + 'loader.c', + 'core.c', + 'api.c', +)]) -- cgit v1.2.3-55-g7522 From 64ed6f92ffebb419ba71ef61e7bdb5f165c5043a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 3 Aug 2020 17:04:25 +0200 Subject: meson: link emulators without Makefile.target The binaries move to the root directory, e.g. qemu-system-i386 or qemu-arm. This requires changes to qtests, CI, etc. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- .gitlab-ci.yml | 6 +- Makefile | 35 +------ Makefile.objs | 32 ------- Makefile.target | 153 +----------------------------- configure | 43 +-------- docs/devel/blkverify.txt | 4 +- docs/devel/testing.rst | 4 +- docs/interop/live-block-operations.rst | 4 +- meson.build | 73 +++++++++++++- os-posix.c | 4 +- plugins/meson.build | 10 +- rules.mak | 1 - scripts/device-crash-test | 2 +- scripts/oss-fuzz/build.sh | 20 ++-- softmmu/Makefile.objs | 2 - target/s390x/meson.build | 13 +++ tests/Makefile.include | 4 +- tests/acceptance/avocado_qemu/__init__.py | 3 +- tests/data/acpi/rebuild-expected-aml.sh | 2 +- tests/multiboot/run_test.sh | 2 +- tests/qemu-iotests/check | 6 +- tests/qtest/fuzz/Makefile.include | 39 -------- tests/qtest/fuzz/i440fx_fuzz.c | 4 +- tests/qtest/fuzz/meson.build | 35 +++++++ tests/qtest/fuzz/qtest_wrappers.c | 2 +- tests/qtest/fuzz/virtio_net_fuzz.c | 3 +- tests/qtest/fuzz/virtio_scsi_fuzz.c | 8 +- tests/qtest/libqos/qgraph.h | 2 +- tests/qtest/meson.build | 2 +- tests/qtest/rtas-test.c | 2 +- tests/tcg/configure.sh | 4 +- util/module.c | 1 - 32 files changed, 181 insertions(+), 344 deletions(-) delete mode 100644 softmmu/Makefile.objs delete mode 100644 tests/qtest/fuzz/Makefile.include create mode 100644 tests/qtest/fuzz/meson.build diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9820066379..b7967b9a13 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -265,9 +265,9 @@ build-tci: - make run-tcg-tests-x86_64-softmmu - make tests/qtest/boot-serial-test tests/qtest/cdrom-test tests/qtest/pxe-test - for tg in $TARGETS ; do - export QTEST_QEMU_BINARY="${tg}-softmmu/qemu-system-${tg}" ; + export QTEST_QEMU_BINARY="./qemu-system-${tg}" ; ./tests/qtest/boot-serial-test || exit 1 ; ./tests/qtest/cdrom-test || exit 1 ; done - - QTEST_QEMU_BINARY="x86_64-softmmu/qemu-system-x86_64" ./tests/qtest/pxe-test - - QTEST_QEMU_BINARY="s390x-softmmu/qemu-system-s390x" ./tests/qtest/pxe-test -m slow + - QTEST_QEMU_BINARY="./qemu-system-x86_64" ./tests/qtest/pxe-test + - QTEST_QEMU_BINARY="./qemu-system-s390x" ./tests/qtest/pxe-test -m slow diff --git a/Makefile b/Makefile index ae0aa62082..fe8c63acad 100644 --- a/Makefile +++ b/Makefile @@ -121,9 +121,6 @@ include $(SRC_PATH)/rules.mak # lor is defined in rules.mak CONFIG_BLOCK := $(call lor,$(CONFIG_SOFTMMU),$(CONFIG_TOOLS)) -generated-files-y += target/s390x/gen-features.h -target/s390x/gen-features.h: Makefile.ninja - generated-files-y += .git-submodule-status # Don't try to regenerate Makefile or configure @@ -187,29 +184,6 @@ config-host.h-timestamp: config-host.mak TARGET_DIRS_RULES := $(foreach t, all fuzz clean install, $(addsuffix /$(t), $(TARGET_DIRS))) -SOFTMMU_ALL_RULES=$(filter %-softmmu/all, $(TARGET_DIRS_RULES)) -$(SOFTMMU_ALL_RULES): $(authz-obj-y) -$(SOFTMMU_ALL_RULES): $(block-obj-y) -$(SOFTMMU_ALL_RULES): $(chardev-obj-y) -$(SOFTMMU_ALL_RULES): $(crypto-obj-y) -$(SOFTMMU_ALL_RULES): $(io-obj-y) -$(SOFTMMU_ALL_RULES): $(qom-obj-y) -$(SOFTMMU_ALL_RULES): config-all-devices.mak - -SOFTMMU_FUZZ_RULES=$(filter %-softmmu/fuzz, $(TARGET_DIRS_RULES)) -$(SOFTMMU_FUZZ_RULES): $(authz-obj-y) -$(SOFTMMU_FUZZ_RULES): $(block-obj-y) -$(SOFTMMU_FUZZ_RULES): $(chardev-obj-y) -$(SOFTMMU_FUZZ_RULES): $(crypto-obj-y) -$(SOFTMMU_FUZZ_RULES): $(io-obj-y) -$(SOFTMMU_FUZZ_RULES): config-all-devices.mak -$(SOFTMMU_FUZZ_RULES): $(edk2-decompressed) - -# meson: this is sub-optimal but going away after conversion -TARGET_DEPS = $(patsubst %,%-config-target.h, $(TARGET_DIRS)) -TARGET_DEPS += $(patsubst %,%-config-devices.h, $(filter %-softmmu,$(TARGET_DIRS))) -TARGET_DEPS += $(patsubst %,libqemu-%.fa, $(TARGET_DIRS)) - .PHONY: $(TARGET_DIRS_RULES) # The $(TARGET_DIRS_RULES) are of the form SUBDIR/GOAL, so that # $(dir $@) yields the sub-directory, and $(notdir $@) yields the sub-goal @@ -252,11 +226,7 @@ slirp/all: .git-submodule-status CC="$(CC)" AR="$(AR)" LD="$(LD)" RANLIB="$(RANLIB)" \ CFLAGS="$(QEMU_CFLAGS) $(CFLAGS)" LDFLAGS="$(QEMU_LDFLAGS)") -$(filter %/all, $(TARGET_DIRS_RULES)): libqemuutil.a $(common-obj-y) \ - $(qom-obj-y) block.syms qemu.syms - -$(filter %/fuzz, $(TARGET_DIRS_RULES)): libqemuutil.a $(common-obj-y) \ - $(qom-obj-y) $(crypto-user-obj-$(CONFIG_USER_ONLY)) +$(filter %/all, $(TARGET_DIRS_RULES)): ROM_DIRS = $(addprefix pc-bios/, $(ROMS)) ROM_DIRS_RULES=$(foreach t, all clean, $(addsuffix /$(t), $(ROM_DIRS))) @@ -278,8 +248,6 @@ Makefile: $(version-obj-y) ###################################################################### -COMMON_LDADDS = libqemuutil.a - clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files @@ -313,6 +281,7 @@ distclean: clean ninja-distclean rm -f po/*.mo tests/qemu-iotests/common.env rm -f roms/seabios/config.mak roms/vgabios/config.mak rm -f qemu-plugins-ld.symbols qemu-plugins-ld64.symbols + rm -f *-config-target.h *-config-devices.mak *-config-devices.h rm -rf meson-private meson-logs meson-info compile_commands.json rm -f Makefile.ninja ninjatool ninjatool.stamp Makefile.mtest rm -f config.log diff --git a/Makefile.objs b/Makefile.objs index 83622c58a5..5295c3a623 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -33,38 +33,6 @@ io-obj-y = io/libio.fa endif # CONFIG_SOFTMMU or CONFIG_TOOLS -###################################################################### -# Target independent part of system emulation. The long term path is to -# suppress *all* target specific code in case of system emulation, i.e. a -# single QEMU executable should support all CPUs and machines. - -ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = - -common-obj-$(CONFIG_AUDIO_ALSA) += audio-alsa$(DSOSUF) -common-obj-$(CONFIG_AUDIO_OSS) += audio-oss$(DSOSUF) -common-obj-$(CONFIG_AUDIO_PA) += audio-pa$(DSOSUF) -common-obj-$(CONFIG_AUDIO_SDL) += audio-sdl$(DSOSUF) - -common-obj-$(if $(CONFIG_CURSES),m) += ui-curses$(DSOSUF) -common-obj-$(if $(CONFIG_GTK),m) += ui-gtk$(DSOSUF) -common-obj-$(if $(CONFIG_SDL),m) += ui-sdl$(DSOSUF) -common-obj-$(if $(CONFIG_SPICE),m) += ui-spice-app$(DSOSUF) - -common-obj-$(if $(CONFIG_CURL),m) += block-curl$(DSOSUF) -common-obj-$(if $(CONFIG_GLUSTERFS),m) += block-gluster$(DSOSUF) -common-obj-$(if $(CONFIG_LIBISCSI),m) += block-iscsi$(DSOSUF) -common-obj-$(if $(CONFIG_LIBNFS),m) += block-nfs$(DSOSUF) -common-obj-$(if $(CONFIG_LIBSSH),m) += block-ssh$(DSOSUF) -common-obj-$(if $(CONFIG_RBD),m) += block-rbd$(DSOSUF) - -common-obj-$(if $(CONFIG_LZFSE),m) += block-dmg-lzfse$(DSOSUF) -common-obj-$(if $(and $(CONFIG_BZIP2),$(CONFIG_DMG)),m) += block-dmg-bz2$(DSOSUF) - -common-obj-y += libqmp.fa - -endif # CONFIG_SOFTMMU - ###################################################################### # Resource file for Windows executables version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o diff --git a/Makefile.target b/Makefile.target index 2b7280b272..8ee4c78b3f 100644 --- a/Makefile.target +++ b/Makefile.target @@ -6,43 +6,16 @@ include ../config-host.mak include config-target.mak include $(SRC_PATH)/rules.mak -FULL_TARGET_NAME=$(TARGET_NAME)-$(if $(CONFIG_SOFTMMU),softmmu,linux-user) - -ifdef CONFIG_SOFTMMU -include ../$(FULL_TARGET_NAME)-config-devices.mak -endif - $(call set-vpath, $(SRC_PATH):$(BUILD_DIR)) -ifdef CONFIG_LINUX -QEMU_CFLAGS += -isystem ../linux-headers -endif -QEMU_CFLAGS += -iquote .. -iquote $(SRC_PATH)/target/$(TARGET_BASE_ARCH) -DNEED_CPU_H - -QEMU_CFLAGS+=-iquote $(SRC_PATH)/include - -QEMU_CFLAGS += -DCONFIG_TARGET=\"../$(FULL_TARGET_NAME)-config-target.h\" -QEMU_CFLAGS += -DCONFIG_DEVICES=\"../$(FULL_TARGET_NAME)-config-devices.h\" ifdef CONFIG_USER_ONLY # user emulator name QEMU_PROG=qemu-$(TARGET_NAME) -QEMU_PROG_BUILD = $(QEMU_PROG) else # system emulator name QEMU_PROG=qemu-system-$(TARGET_NAME)$(EXESUF) -ifneq (,$(findstring -mwindows,$(SDL_LIBS))) -# Terminate program name with a 'w' because the linker builds a windows executable. -QEMU_PROGW=qemu-system-$(TARGET_NAME)w$(EXESUF) -$(QEMU_PROG): $(QEMU_PROGW) - $(call quiet-command,$(OBJCOPY) --subsystem console $(QEMU_PROGW) $(QEMU_PROG),"GEN","$(TARGET_DIR)$(QEMU_PROG)") -QEMU_PROG_BUILD = $(QEMU_PROGW) -else -QEMU_PROG_BUILD = $(QEMU_PROG) -endif endif -LIBQEMU = ../libqemu-$(FULL_TARGET_NAME).fa -PROGS=$(QEMU_PROG) $(QEMU_PROGW) STPFILES= ifdef CONFIG_TRACE_SYSTEMTAP @@ -98,109 +71,10 @@ stap: endif .PHONY: stap -all: $(PROGS) stap - -# Dummy command so that make thinks it has done something - @true - -obj-y += $(LIBQEMU) - -obj-y += trace/ - -######################################################### -LIBS := $(libs_cpu) $(LIBS) - -######################################################### -# Linux user emulator target - -ifdef CONFIG_LINUX_USER - -QEMU_CFLAGS+=-I$(SRC_PATH)/linux-user/$(TARGET_ABI_DIR) \ - -I$(SRC_PATH)/linux-user/host/$(ARCH) \ - -I$(SRC_PATH)/linux-user \ - -Ilinux-user/$(TARGET_ABI_DIR) - -endif #CONFIG_LINUX_USER - -######################################################### -# BSD user emulator target - -ifdef CONFIG_BSD_USER - -QEMU_CFLAGS+=-I$(SRC_PATH)/bsd-user -I$(SRC_PATH)/bsd-user/$(TARGET_ABI_DIR) \ - -I$(SRC_PATH)/bsd-user/$(HOST_VARIANT_DIR) - -endif #CONFIG_BSD_USER - -######################################################### -# System emulator target -ifdef CONFIG_SOFTMMU -obj-y += softmmu/ -obj-y += gdbstub.o -LIBS := $(libs_softmmu) $(LIBS) - -# Temporary until emulators are linked by Meson -LIBS := $(LIBS) @../block.syms @../qemu.syms -ifneq ($(CONFIG_MODULES),y) -LIBS := $(LIBS) $(ALSA_LIBS) $(OSS_LIBS) $(PULSE_LIBS) $(SDL_LIBS) -LIBS := $(LIBS) $(GTK_LIBS) $(VTE_LIBS) $(X11_LIBS) $(CURSES_LIBS) $(ICONV_LIBS) $(GIO_LIBS) -endif -LIBS := $(LIBS) $(BRLAPI_LIBS) $(SDL_LIBS) $(SPICE_LIBS) $(OPENGL_LIBS) $(SECCOMP_LIBS) -LIBS := $(LIBS) $(COREAUDIO_LIBS) $(DSOUND_LIBS) -LIBS := $(LIBS) $(VDE_LIBS) $(SLIRP_LIBS) -LIBS := $(LIBS) $(LIBUSB_LIBS) $(SMARTCARD_LIBS) $(USB_REDIR_LIBS) -LIBS := $(LIBS) $(VIRGL_LIBS) $(CURSES_LIBS) - -ifeq ($(CONFIG_PLUGIN),y) -ifdef CONFIG_HAS_LD_DYNAMIC_LIST -LIBS += -Wl,--dynamic-list=$(BUILD_DIR)/qemu-plugins-ld.symbols -else -ifdef CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST -LIBS += -Wl,-exported_symbols_list,$(BUILD_DIR)/qemu-plugins-ld64.symbols -endif -endif -endif - -generated-files-y += hmp-commands.h hmp-commands-info.h - -endif # CONFIG_SOFTMMU - -dummy := $(call unnest-vars,,obj-y) -all-obj-y := $(obj-y) - -include $(SRC_PATH)/Makefile.objs -dummy := $(call fix-paths,../,, \ - authz-obj-y \ - block-obj-y \ - chardev-obj-y \ - crypto-obj-y \ - io-obj-y \ - qom-obj-y) -dummy := $(call unnest-vars,..,common-obj-y) - -all-obj-y += $(common-obj-y) -all-obj-y += $(qom-obj-y) -all-obj-$(CONFIG_SOFTMMU) += $(authz-obj-y) -all-obj-$(CONFIG_SOFTMMU) += $(block-obj-y) $(chardev-obj-y) -all-obj-$(CONFIG_SOFTMMU) += $(crypto-obj-y) -all-obj-$(CONFIG_SOFTMMU) += $(io-obj-y) - -ifdef CONFIG_SOFTMMU -$(QEMU_PROG_BUILD): ../$(FULL_TARGET_NAME)-config-devices.mak -endif - -COMMON_LDADDS = ../libqemuutil.a - -# build either PROG or PROGW -$(QEMU_PROG_BUILD): $(all-obj-y) $(COMMON_LDADDS) $(softmmu-main-y) - $(call LINK, $(filter-out %.mak, $^)) -ifdef CONFIG_DARWIN - $(call quiet-command,Rez -append $(SRC_PATH)/pc-bios/qemu.rsrc -o $@,"REZ","$(TARGET_DIR)$@") - $(call quiet-command,SetFile -a C $@,"SETFILE","$(TARGET_DIR)$@") -endif +all: stap -clean: clean-target - rm -f *.a *~ $(PROGS) +clean: + rm -f *.a *~ rm -f $(shell find . -name '*.[od]') rm -f hmp-commands.h gdbstub-xml.c rm -f trace/generated-helpers.c trace/generated-helpers.c-timestamp @@ -208,26 +82,7 @@ ifdef CONFIG_TRACE_SYSTEMTAP rm -f *.stp endif -ifdef CONFIG_FUZZ -include $(SRC_PATH)/tests/qtest/fuzz/Makefile.include -include $(SRC_PATH)/tests/qtest/Makefile.include - -fuzz: fuzz-vars -fuzz-vars: QEMU_CFLAGS := $(FUZZ_CFLAGS) $(QEMU_CFLAGS) -fuzz-vars: QEMU_LDFLAGS := $(FUZZ_LDFLAGS) $(QEMU_LDFLAGS) -fuzz-vars: $(QEMU_PROG_FUZZ) -dummy := $(call unnest-vars,, fuzz-obj-y) - - -$(QEMU_PROG_FUZZ): config-devices.mak $(all-obj-y) $(COMMON_LDADDS) $(fuzz-obj-y) - $(call LINK, $(filter-out %.mak, $^)) - -endif - install: all -ifneq ($(PROGS),) - $(call install-prog,$(PROGS),$(DESTDIR)$(bindir)) -endif ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset" $(INSTALL_DATA) $(QEMU_PROG).stp-installed "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG).stp" @@ -235,4 +90,4 @@ ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DATA) $(QEMU_PROG)-log.stp "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG)-log.stp" endif -Makefile: $(generated-files-y) +.PHONY: all clean install diff --git a/configure b/configure index 2f5dfbc5b0..74113e0e9f 100755 --- a/configure +++ b/configure @@ -362,7 +362,6 @@ audio_drv_list="" block_drv_rw_whitelist="" block_drv_ro_whitelist="" host_cc="cc" -libs_cpu="" libs_softmmu="" libs_tools="" audio_win_int="" @@ -5477,7 +5476,6 @@ case "$capstone" in else LIBCAPSTONE=libcapstone.a fi - libs_cpu="-L$PWD/capstone -lcapstone $libs_cpu" capstone_libs="-L$PWD/capstone -lcapstone" capstone_cflags="-I${source_path}/capstone/include" ;; @@ -5486,7 +5484,6 @@ case "$capstone" in capstone_libs="$($pkg_config --libs capstone)" capstone_cflags="$($pkg_config --cflags capstone)" QEMU_CFLAGS="$QEMU_CFLAGS $($pkg_config --cflags capstone)" - libs_cpu="$($pkg_config --libs capstone) $libs_cpu" ;; no) @@ -6403,7 +6400,10 @@ fi if test "$fuzzing" = "yes" ; then write_c_fuzzer_skeleton if compile_prog "$CPU_CFLAGS -Werror -fsanitize=fuzzer" ""; then - have_fuzzer=yes + have_fuzzer=yes + else + error_exit "Your compiler doesn't support -fsanitize=fuzzer" + exit 1 fi fi @@ -6915,7 +6915,6 @@ echo "qemu_helperdir=$libexecdir" >> $config_host_mak echo "qemu_localedir=$qemu_localedir" >> $config_host_mak echo "qemu_icondir=$qemu_icondir" >> $config_host_mak echo "qemu_desktopdir=$qemu_desktopdir" >> $config_host_mak -echo "libs_cpu=$libs_cpu" >> $config_host_mak echo "libs_softmmu=$libs_softmmu" >> $config_host_mak echo "GIT=$git" >> $config_host_mak echo "GIT_SUBMODULES=$git_submodules" >> $config_host_mak @@ -7780,14 +7779,7 @@ if test "$have_mlockall" = "yes" ; then echo "HAVE_MLOCKALL=y" >> $config_host_mak fi if test "$fuzzing" = "yes" ; then - if test "$have_fuzzer" = "yes"; then - FUZZ_LDFLAGS=" -fsanitize=fuzzer" - FUZZ_CFLAGS=" -fsanitize=fuzzer" - QEMU_CFLAGS="$QEMU_CFLAGS -fsanitize=fuzzer-no-link" - else - error_exit "Your compiler doesn't support -fsanitize=fuzzer" - exit 1 - fi + QEMU_CFLAGS="$QEMU_CFLAGS -fsanitize=fuzzer-no-link" fi if test "$plugins" = "yes" ; then @@ -7902,8 +7894,6 @@ if test "$libudev" != "no"; then fi if test "$fuzzing" != "no"; then echo "CONFIG_FUZZ=y" >> $config_host_mak - echo "FUZZ_CFLAGS=$FUZZ_CFLAGS" >> $config_host_mak - echo "FUZZ_LDFLAGS=$FUZZ_LDFLAGS" >> $config_host_mak fi if test "$edk2_blobs" = "yes" ; then @@ -8176,8 +8166,6 @@ if [ "$TARGET_SYSTBL_ABI" != "" ] && [ "$TARGET_SYSTBL" = "" ]; then TARGET_SYSTBL=syscall.tbl fi -symlink "$source_path/Makefile.target" "$target_dir/Makefile" - upper() { echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]' } @@ -8253,9 +8241,6 @@ fi # generate QEMU_CFLAGS/QEMU_LDFLAGS for targets -cflags="" -ldflags="" - disas_config() { echo "CONFIG_${1}_DIS=y" >> $config_target_mak echo "CONFIG_${1}_DIS=y" >> config-all-disas.mak @@ -8340,24 +8325,6 @@ if test "$tcg_interpreter" = "yes" ; then disas_config "TCI" fi -# Newer kernels on s390 check for an S390_PGSTE program header and -# enable the pgste page table extensions in that case. This makes -# the vm.allocate_pgste sysctl unnecessary. We enable this program -# header if -# - we build on s390x -# - we build the system emulation for s390x (qemu-system-s390x) -# - KVM is enabled -# - the linker supports --s390-pgste -if test "$TARGET_ARCH" = "s390x" && test "$target_softmmu" = "yes" && \ - test "$ARCH" = "s390x" && test "$kvm" = "yes"; then - if ld_has --s390-pgste ; then - ldflags="-Wl,--s390-pgste $ldflags" - fi -fi - -echo "QEMU_LDFLAGS+=$ldflags" >> $config_target_mak -echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak - done # for target in $targets echo "PIXMAN_CFLAGS=$pixman_cflags" >> $config_host_mak diff --git a/docs/devel/blkverify.txt b/docs/devel/blkverify.txt index d556dc4e6d..aca826c51c 100644 --- a/docs/devel/blkverify.txt +++ b/docs/devel/blkverify.txt @@ -62,8 +62,8 @@ A more realistic scenario is verifying the installation of a guest OS: $ ./qemu-img create raw.img 16G $ ./qemu-img create -f qcow2 test.qcow2 16G - $ x86_64-softmmu/qemu-system-x86_64 -cdrom debian.iso \ - -drive file=blkverify:raw.img:test.qcow2 + $ ./qemu-system-x86_64 -cdrom debian.iso \ + -drive file=blkverify:raw.img:test.qcow2 If the installation is aborted when blkverify detects corruption, use qemu-io to explore the contents of the disk image at the sector in question. diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index a4264691be..196e3bc35e 100644 --- a/docs/devel/testing.rst +++ b/docs/devel/testing.rst @@ -819,7 +819,7 @@ the following approaches: 1) Set ``qemu_bin``, and use the given binary 2) Do not set ``qemu_bin``, and use a QEMU binary named like - "${arch}-softmmu/qemu-system-${arch}", either in the current + "qemu-system-${arch}", either in the current working directory, or in the current source tree. The resulting ``qemu_bin`` value will be preserved in the @@ -886,7 +886,7 @@ like the following: .. code:: - PARAMS (key=qemu_bin, path=*, default=x86_64-softmmu/qemu-system-x86_64) => 'x86_64-softmmu/qemu-system-x86_64 + PARAMS (key=qemu_bin, path=*, default=./qemu-system-x86_64) => './qemu-system-x86_64 arch ~~~~ diff --git a/docs/interop/live-block-operations.rst b/docs/interop/live-block-operations.rst index 48afdc7927..e13f5a21f8 100644 --- a/docs/interop/live-block-operations.rst +++ b/docs/interop/live-block-operations.rst @@ -129,7 +129,7 @@ To show some example invocations of command-line, we will use the following invocation of QEMU, with a QMP server running over UNIX socket:: - $ ./x86_64-softmmu/qemu-system-x86_64 -display none -no-user-config \ + $ ./qemu-system-x86_64 -display none -no-user-config \ -M q35 -nodefaults -m 512 \ -blockdev node-name=node-A,driver=qcow2,file.driver=file,file.node-name=file,file.filename=./a.qcow2 \ -device virtio-blk,drive=node-A,id=virtio0 \ @@ -694,7 +694,7 @@ instance, with the following invocation. (As noted earlier, for simplicity's sake, the destination QEMU is started on the same host, but it could be located elsewhere):: - $ ./x86_64-softmmu/qemu-system-x86_64 -display none -no-user-config \ + $ ./qemu-system-x86_64 -display none -no-user-config \ -M q35 -nodefaults -m 512 \ -blockdev node-name=node-TargetDisk,driver=qcow2,file.driver=file,file.node-name=file,file.filename=./target-disk.qcow2 \ -device virtio-blk,drive=node-TargetDisk,id=virtio0 \ diff --git a/meson.build b/meson.build index fa47410c29..9db1b7b705 100644 --- a/meson.build +++ b/meson.build @@ -215,10 +215,12 @@ brlapi = not_found if 'CONFIG_BRLAPI' in config_host brlapi = declare_dependency(link_args: config_host['BRLAPI_LIBS'].split()) endif +sdlwindows = false sdl = not_found if 'CONFIG_SDL' in config_host sdl = declare_dependency(compile_args: config_host['SDL_CFLAGS'].split(), link_args: config_host['SDL_LIBS'].split()) + sdlwindows = config_host['SDL_LIBS'].contains('-mwindows') endif rbd = not_found if 'CONFIG_RBD' in config_host @@ -529,6 +531,7 @@ user_ss = ss.source_set() bsd_user_ss = ss.source_set() linux_user_ss = ss.source_set() specific_ss = ss.source_set() +specific_fuzz_ss = ss.source_set() modules = {} hw_arch = {} @@ -743,6 +746,7 @@ specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) # needed for fuzzing binaries subdir('tests/qtest/libqos') +subdir('tests/qtest/fuzz') block_mods = [] softmmu_mods = [] @@ -805,7 +809,10 @@ foreach m : block_mods + softmmu_mods install_dir: config_host['qemu_moddir']) endforeach -common_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: softmmu_ss) +softmmu_ss.add(authz, block, chardev, crypto, io, qmp) +common_ss.add(qom, qemuutil) + +common_ss.add_all(when: 'CONFIG_SOFTMMU', if_true: [softmmu_ss]) common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: user_ss) common_all = common_ss.apply(config_all, strict: false) @@ -817,11 +824,17 @@ common_all = static_library('common', feature_to_c = find_program('scripts/feature_to_c.sh') +emulators = [] foreach target : target_dirs config_target = config_target_mak[target] target_name = config_target['TARGET_NAME'] arch = config_target['TARGET_BASE_ARCH'] arch_srcs = [] + arch_deps = [] + c_args = ['-DNEED_CPU_H', + '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), + '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)] + link_args = [] target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])] if targetos == 'linux' @@ -832,12 +845,15 @@ foreach target : target_dirs target_type='system' t = target_softmmu_arch[arch].apply(config_target, strict: false) arch_srcs += t.sources() + arch_deps += t.dependencies() hw_dir = target_name == 'sparc64' ? 'sparc64' : arch hw = hw_arch[hw_dir].apply(config_target, strict: false) arch_srcs += hw.sources() + arch_deps += hw.dependencies() arch_srcs += config_devices_h[target] + link_args += ['@block.syms', '@qemu.syms'] else abi = config_target['TARGET_ABI_DIR'] target_type='user' @@ -874,9 +890,11 @@ foreach target : target_dirs t = target_arch[arch].apply(config_target, strict: false) arch_srcs += t.sources() + arch_deps += t.dependencies() target_common = common_ss.apply(config_target, strict: false) objects = common_all.extract_objects(target_common.sources()) + deps = target_common.dependencies() # TODO: Change to generator once obj-y goes away config_target_h = custom_target(target + '-config-target.h', @@ -887,15 +905,60 @@ foreach target : target_dirs target_specific = specific_ss.apply(config_target, strict: false) arch_srcs += target_specific.sources() + arch_deps += target_specific.dependencies() - static_library('qemu-' + target, + lib = static_library('qemu-' + target, sources: arch_srcs + [config_target_h] + genh, objects: objects, include_directories: target_inc, - c_args: ['-DNEED_CPU_H', - '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), - '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)], + c_args: c_args, + build_by_default: false, name_suffix: 'fa') + + if target.endswith('-softmmu') + execs = [{ + 'name': 'qemu-system-' + target_name, + 'gui': false, + 'sources': files('softmmu/main.c'), + 'dependencies': [] + }] + if sdlwindows + execs += [{ + 'name': 'qemu-system-' + target_name + 'w', + 'gui': true, + 'sources': files('softmmu/main.c'), + 'dependencies': [] + }] + endif + if config_host.has_key('CONFIG_FUZZ') + specific_fuzz = specific_fuzz_ss.apply(config_target, strict: false) + execs += [{ + 'name': 'qemu-fuzz-' + target_name, + 'gui': false, + 'sources': specific_fuzz.sources(), + 'dependencies': specific_fuzz.dependencies(), + 'link_depends': [files('tests/qtest/fuzz/fork_fuzz.ld')], + }] + endif + else + execs = [{ + 'name': 'qemu-' + target_name, + 'gui': false, + 'sources': [], + 'dependencies': [] + }] + endif + foreach exe: execs + emulators += executable(exe['name'], exe['sources'], + install: true, + c_args: c_args, + dependencies: arch_deps + deps + exe['dependencies'], + objects: lib.extract_all_objects(recursive: true), + link_language: link_language, + link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []), + link_args: link_args, + gui_app: exe['gui']) + endforeach endforeach # Other build targets diff --git a/os-posix.c b/os-posix.c index 3572db3f44..bf98508b6d 100644 --- a/os-posix.c +++ b/os-posix.c @@ -82,7 +82,7 @@ void os_setup_signal_handling(void) /* * Find a likely location for support files using the location of the binary. - * When running from the build tree this will be "$bindir/../pc-bios". + * When running from the build tree this will be "$bindir/pc-bios". * Otherwise, this is CONFIG_QEMU_DATADIR. * * The caller must use g_free() to free the returned data when it is @@ -96,7 +96,7 @@ char *os_find_datadir(void) exec_dir = qemu_get_exec_dir(); g_return_val_if_fail(exec_dir != NULL, NULL); - dir = g_build_filename(exec_dir, "..", "pc-bios", NULL); + dir = g_build_filename(exec_dir, "pc-bios", NULL); if (g_file_test(dir, G_FILE_TEST_IS_DIR)) { return g_steal_pointer(&dir); } diff --git a/plugins/meson.build b/plugins/meson.build index 9608e5293f..e77723010e 100644 --- a/plugins/meson.build +++ b/plugins/meson.build @@ -1,5 +1,13 @@ +if 'CONFIG_HAS_LD_DYNAMIC_LIST' in config_host + plugin_ldflags = ['-Wl,--dynamic-list=' + (meson.build_root() / 'qemu-plugins-ld.symbols')] +elif 'CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST' in config_host + plugin_ldflags = ['-Wl,-exported_symbols_list,' + (meson.build_root() / 'qemu-plugins-ld64.symbols')] +else + plugin_ldflags = [] +endif + specific_ss.add(when: 'CONFIG_PLUGIN', if_true: [files( 'loader.c', 'core.c', 'api.c', -)]) +), declare_dependency(link_args: plugin_ldflags)]) diff --git a/rules.mak b/rules.mak index 8285fe529a..6488dc3dc6 100644 --- a/rules.mak +++ b/rules.mak @@ -21,7 +21,6 @@ MAKEFLAGS += -rR %.cpp: %.m: %.mak: -clean-target: # Flags for dependency generation QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d diff --git a/scripts/device-crash-test b/scripts/device-crash-test index 305d0427af..866baf7058 100755 --- a/scripts/device-crash-test +++ b/scripts/device-crash-test @@ -383,7 +383,7 @@ def binariesToTest(args, testcase): if args.qemu: r = args.qemu else: - r = glob.glob('./*-softmmu/qemu-system-*') + r = glob.glob('./qemu-system-*') return r diff --git a/scripts/oss-fuzz/build.sh b/scripts/oss-fuzz/build.sh index 52430cb620..f0b7442c96 100755 --- a/scripts/oss-fuzz/build.sh +++ b/scripts/oss-fuzz/build.sh @@ -64,24 +64,26 @@ mkdir -p "$DEST_DIR/lib/" # Copy the shared libraries here # Build once to get the list of dynamic lib paths, and copy them over ../configure --disable-werror --cc="$CC" --cxx="$CXX" --enable-fuzzing \ + --prefix="$DEST_DIR" --bindir="$DEST_DIR" --datadir="$DEST_DIR/data/" \ --extra-cflags="$EXTRA_CFLAGS" --target-list="i386-softmmu" -if ! make "-j$(nproc)" i386-softmmu/fuzz; then +if ! make "-j$(nproc)" qemu-fuzz-i386; then fatal "Build failed. Please specify a compiler with fuzzing support"\ "using the \$CC and \$CXX environemnt variables"\ "\nFor example: CC=clang CXX=clang++ $0" fi -for i in $(ldd ./i386-softmmu/qemu-fuzz-i386 | cut -f3 -d' '); do +for i in $(ldd ./qemu-fuzz-i386 | cut -f3 -d' '); do cp "$i" "$DEST_DIR/lib/" done -rm ./i386-softmmu/qemu-fuzz-i386 +rm qemu-fuzz-i386 # Build a second time to build the final binary with correct rpath -../configure --bindir="$DEST_DIR" --datadir="$DEST_DIR/data/" --disable-werror \ - --cc="$CC" --cxx="$CXX" --extra-cflags="$EXTRA_CFLAGS" \ - --extra-ldflags="-Wl,-rpath,'\$\$ORIGIN/lib'" -make "-j$(nproc)" i386-softmmu/fuzz +../configure --disable-werror --cc="$CC" --cxx="$CXX" --enable-fuzzing \ + --prefix="$DEST_DIR" --bindir="$DEST_DIR" --datadir="$DEST_DIR/data/" \ + --extra-cflags="$EXTRA_CFLAGS" --extra-ldflags="-Wl,-rpath,'\$\$ORIGIN/lib'" \ + --target-list="i386-softmmu" +make "-j$(nproc)" qemu-fuzz-i386 V=1 # Copy over the datadir cp -r ../pc-bios/ "$DEST_DIR/pc-bios" @@ -90,9 +92,9 @@ cp -r ../pc-bios/ "$DEST_DIR/pc-bios" # of available fuzz-targets. Copy over the qemu-fuzz-i386, naming it according # to each available fuzz target (See 05509c8e6d fuzz: select fuzz target using # executable name) -for target in $(./i386-softmmu/qemu-fuzz-i386 | awk '$1 ~ /\*/ {print $2}'); +for target in $(./qemu-fuzz-i386 | awk '$1 ~ /\*/ {print $2}'); do - cp ./i386-softmmu/qemu-fuzz-i386 "$DEST_DIR/qemu-fuzz-i386-target-$target" + cp qemu-fuzz-i386 "$DEST_DIR/qemu-fuzz-i386-target-$target" done echo "Done. The fuzzers are located in $DEST_DIR" diff --git a/softmmu/Makefile.objs b/softmmu/Makefile.objs deleted file mode 100644 index ec74d8a9fa..0000000000 --- a/softmmu/Makefile.objs +++ /dev/null @@ -1,2 +0,0 @@ -softmmu-main-y = softmmu/main.o -main.o-cflags := $(SDL_CFLAGS) diff --git a/target/s390x/meson.build b/target/s390x/meson.build index 27d248ef6e..d2a3315903 100644 --- a/target/s390x/meson.build +++ b/target/s390x/meson.build @@ -45,5 +45,18 @@ s390x_softmmu_ss.add(files( 'sigp.c', )) +# Newer kernels on s390 check for an S390_PGSTE program header and +# enable the pgste page table extensions in that case. This makes +# the vm.allocate_pgste sysctl unnecessary. We enable this program +# header if +# - we build on s390x +# - we build the system emulation for s390x (qemu-system-s390x) +# - KVM is enabled +# - the linker supports --s390-pgste +if host_machine.cpu_family() == 's390x' and cc.has_link_argument('-Wl,--s390-pgste') + s390x_softmmu_ss.add(when: 'CONFIG_KVM', + if_true: declare_dependency(link_args: ['-Wl,--s390-pgste'])) +endif + target_arch += {'s390x': s390x_ss} target_softmmu_arch += {'s390x': s390x_softmmu_ss} diff --git a/tests/Makefile.include b/tests/Makefile.include index 609a40c6e5..4a2435342a 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -457,7 +457,7 @@ build-tcg-tests-%: $(if $(CONFIG_PLUGIN),plugins) V="$(V)" TARGET="$*" guest-tests, \ "BUILD", "TCG tests for $*") -run-tcg-tests-%: build-tcg-tests-% %/all +run-tcg-tests-%: build-tcg-tests-% all $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ SRC_PATH=$(SRC_PATH) SPEED="$(SPEED)" \ @@ -485,7 +485,7 @@ QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu .PHONY: check-tests/check-block.sh check-tests/check-block.sh: tests/check-block.sh qemu-img$(EXESUF) \ qemu-io$(EXESUF) qemu-nbd$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) \ - $(patsubst %,%/all,$(filter %-softmmu,$(TARGET_DIRS))) + $(patsubst %-softmmu,qemu-system-%,$(filter %-softmmu,$(TARGET_DIRS))) @$< # Python venv for running tests diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py index 77d1c1d9ff..db9c0f5d79 100644 --- a/tests/acceptance/avocado_qemu/__init__.py +++ b/tests/acceptance/avocado_qemu/__init__.py @@ -57,8 +57,7 @@ def pick_default_qemu_bin(arch=None): # qemu binary path does not match arch for powerpc, handle it if 'ppc64le' in arch: arch = 'ppc64' - qemu_bin_relative_path = os.path.join("%s-softmmu" % arch, - "qemu-system-%s" % arch) + qemu_bin_relative_path = "./qemu-system-%s" % arch if is_readable_executable_file(qemu_bin_relative_path): return qemu_bin_relative_path diff --git a/tests/data/acpi/rebuild-expected-aml.sh b/tests/data/acpi/rebuild-expected-aml.sh index 76cd797d1e..fc78770544 100755 --- a/tests/data/acpi/rebuild-expected-aml.sh +++ b/tests/data/acpi/rebuild-expected-aml.sh @@ -12,7 +12,7 @@ # This work is licensed under the terms of the GNU GPLv2. # See the COPYING.LIB file in the top-level directory. -qemu_bins="x86_64-softmmu/qemu-system-x86_64 aarch64-softmmu/qemu-system-aarch64" +qemu_bins="./qemu-system-x86_64 ./qemu-system-aarch64" if [ ! -e "tests/qtest/bios-tables-test" ]; then echo "Test: bios-tables-test is required! Run make check before this script." diff --git a/tests/multiboot/run_test.sh b/tests/multiboot/run_test.sh index 98df91e6af..f968bf797e 100755 --- a/tests/multiboot/run_test.sh +++ b/tests/multiboot/run_test.sh @@ -20,7 +20,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. -QEMU=${QEMU:-"../../x86_64-softmmu/qemu-system-x86_64"} +QEMU=${QEMU:-"../../qemu-system-x86_64"} run_qemu() { local kernel=$1 diff --git a/tests/qemu-iotests/check b/tests/qemu-iotests/check index 0657f7286c..3ab859ac1a 100755 --- a/tests/qemu-iotests/check +++ b/tests/qemu-iotests/check @@ -577,11 +577,11 @@ if [ -z "$QEMU_PROG" ] then if [ -x "$build_iotests/qemu" ]; then export QEMU_PROG="$build_iotests/qemu" - elif [ -x "$build_root/${qemu_arch}-softmmu/qemu-system-${qemu_arch}" ]; then - export QEMU_PROG="$build_root/${qemu_arch}-softmmu/qemu-system-${qemu_arch}" + elif [ -x "$build_root/qemu-system-${qemu_arch}" ]; then + export QEMU_PROG="$build_root/qemu-system-${qemu_arch}" else pushd "$build_root" > /dev/null - for binary in *-softmmu/qemu-system-* + for binary in qemu-system-* do if [ -x "$binary" ] then diff --git a/tests/qtest/fuzz/Makefile.include b/tests/qtest/fuzz/Makefile.include deleted file mode 100644 index 5bde793bf2..0000000000 --- a/tests/qtest/fuzz/Makefile.include +++ /dev/null @@ -1,39 +0,0 @@ -QEMU_PROG_FUZZ=qemu-fuzz-$(TARGET_NAME)$(EXESUF) - -fuzz-obj-y += tests/qtest/libqtest.o -fuzz-obj-y += $(libqos-obj-y) -fuzz-obj-y += tests/qtest/fuzz/fuzz.o # Fuzzer skeleton -fuzz-obj-y += tests/qtest/fuzz/fork_fuzz.o -fuzz-obj-y += tests/qtest/fuzz/qos_fuzz.o -fuzz-obj-y += tests/qtest/fuzz/qtest_wrappers.o - -# Targets -fuzz-obj-$(CONFIG_PCI_I440FX) += tests/qtest/fuzz/i440fx_fuzz.o -fuzz-obj-$(CONFIG_VIRTIO_NET) += tests/qtest/fuzz/virtio_net_fuzz.o -fuzz-obj-$(CONFIG_SCSI) += tests/qtest/fuzz/virtio_scsi_fuzz.o - -FUZZ_CFLAGS += -I$(SRC_PATH)/tests -I$(SRC_PATH)/tests/qtest - -# Linker Script to force coverage-counters into known regions which we can mark -# shared -FUZZ_LDFLAGS += -Xlinker -T$(SRC_PATH)/tests/qtest/fuzz/fork_fuzz.ld - -FUZZ_LDFLAGS += -Wl,-wrap,qtest_inb -FUZZ_LDFLAGS += -Wl,-wrap,qtest_inw -FUZZ_LDFLAGS += -Wl,-wrap,qtest_inl -FUZZ_LDFLAGS += -Wl,-wrap,qtest_outb -FUZZ_LDFLAGS += -Wl,-wrap,qtest_outw -FUZZ_LDFLAGS += -Wl,-wrap,qtest_outl -FUZZ_LDFLAGS += -Wl,-wrap,qtest_readb -FUZZ_LDFLAGS += -Wl,-wrap,qtest_readw -FUZZ_LDFLAGS += -Wl,-wrap,qtest_readl -FUZZ_LDFLAGS += -Wl,-wrap,qtest_readq -FUZZ_LDFLAGS += -Wl,-wrap,qtest_writeb -FUZZ_LDFLAGS += -Wl,-wrap,qtest_writew -FUZZ_LDFLAGS += -Wl,-wrap,qtest_writel -FUZZ_LDFLAGS += -Wl,-wrap,qtest_writeq -FUZZ_LDFLAGS += -Wl,-wrap,qtest_memread -FUZZ_LDFLAGS += -Wl,-wrap,qtest_bufread -FUZZ_LDFLAGS += -Wl,-wrap,qtest_memwrite -FUZZ_LDFLAGS += -Wl,-wrap,qtest_bufwrite -FUZZ_LDFLAGS += -Wl,-wrap,qtest_memset diff --git a/tests/qtest/fuzz/i440fx_fuzz.c b/tests/qtest/fuzz/i440fx_fuzz.c index f45373f5d3..86796bff2b 100644 --- a/tests/qtest/fuzz/i440fx_fuzz.c +++ b/tests/qtest/fuzz/i440fx_fuzz.c @@ -17,8 +17,8 @@ #include "tests/qtest/libqos/pci.h" #include "tests/qtest/libqos/pci-pc.h" #include "fuzz.h" -#include "fuzz/qos_fuzz.h" -#include "fuzz/fork_fuzz.h" +#include "qos_fuzz.h" +#include "fork_fuzz.h" #define I440FX_PCI_HOST_BRIDGE_CFG 0xcf8 diff --git a/tests/qtest/fuzz/meson.build b/tests/qtest/fuzz/meson.build new file mode 100644 index 0000000000..bb0a3f271d --- /dev/null +++ b/tests/qtest/fuzz/meson.build @@ -0,0 +1,35 @@ +specific_fuzz_ss.add(files('fuzz.c', 'fork_fuzz.c', 'qos_fuzz.c', + 'qtest_wrappers.c'), qos) + +# Targets +specific_fuzz_ss.add(when: 'CONFIG_I440FX', if_true: files('i440fx_fuzz.c')) +specific_fuzz_ss.add(when: 'CONFIG_VIRTIO_NET', if_true: files('virtio_net_fuzz.c')) +specific_fuzz_ss.add(when: 'CONFIG_VIRTIO_SCSI', if_true: files('virtio_scsi_fuzz.c')) + +# unfortunately declare_dependency does not support link_depends, so +# this will be duplicated in meson.build +fork_fuzz = declare_dependency( + link_args: ['-fsanitize=fuzzer', + '-Wl,-T,' + (meson.current_source_dir() / 'fork_fuzz.ld'), + '-Wl,-wrap,qtest_inb', + '-Wl,-wrap,qtest_inw', + '-Wl,-wrap,qtest_inl', + '-Wl,-wrap,qtest_outb', + '-Wl,-wrap,qtest_outw', + '-Wl,-wrap,qtest_outl', + '-Wl,-wrap,qtest_readb', + '-Wl,-wrap,qtest_readw', + '-Wl,-wrap,qtest_readl', + '-Wl,-wrap,qtest_readq', + '-Wl,-wrap,qtest_writeb', + '-Wl,-wrap,qtest_writew', + '-Wl,-wrap,qtest_writel', + '-Wl,-wrap,qtest_writeq', + '-Wl,-wrap,qtest_memread', + '-Wl,-wrap,qtest_bufread', + '-Wl,-wrap,qtest_memwrite', + '-Wl,-wrap,qtest_bufwrite', + '-Wl,-wrap,qtest_memset'] +) + +specific_fuzz_ss.add(fork_fuzz) diff --git a/tests/qtest/fuzz/qtest_wrappers.c b/tests/qtest/fuzz/qtest_wrappers.c index 713c830cdb..0580f8df86 100644 --- a/tests/qtest/fuzz/qtest_wrappers.c +++ b/tests/qtest/fuzz/qtest_wrappers.c @@ -12,7 +12,7 @@ */ #include "qemu/osdep.h" -#include "cpu.h" +#include "hw/core/cpu.h" #include "exec/ioport.h" #include "fuzz.h" diff --git a/tests/qtest/fuzz/virtio_net_fuzz.c b/tests/qtest/fuzz/virtio_net_fuzz.c index 277a9e2b64..0e873ab8e2 100644 --- a/tests/qtest/fuzz/virtio_net_fuzz.c +++ b/tests/qtest/fuzz/virtio_net_fuzz.c @@ -61,7 +61,8 @@ static void virtio_net_fuzz_multi(QTestState *s, * backend. Otherwise, always place the input on a virtqueue. */ if (vqa.rx && sockfds_initialized) { - write(sockfds[0], Data, vqa.length); + int ignored = write(sockfds[0], Data, vqa.length); + (void) ignored; } else { vqa.rx = 0; uint64_t req_addr = guest_alloc(t_alloc, vqa.length); diff --git a/tests/qtest/fuzz/virtio_scsi_fuzz.c b/tests/qtest/fuzz/virtio_scsi_fuzz.c index 3a9ea13736..6ff6fabe4a 100644 --- a/tests/qtest/fuzz/virtio_scsi_fuzz.c +++ b/tests/qtest/fuzz/virtio_scsi_fuzz.c @@ -12,10 +12,10 @@ #include "qemu/osdep.h" -#include "tests/qtest/libqtest.h" -#include "libqos/virtio-scsi.h" -#include "libqos/virtio.h" -#include "libqos/virtio-pci.h" +#include "tests/qtest/libqos/libqtest.h" +#include "tests/qtest/libqos/virtio-scsi.h" +#include "tests/qtest/libqos/virtio.h" +#include "tests/qtest/libqos/virtio-pci.h" #include "standard-headers/linux/virtio_ids.h" #include "standard-headers/linux/virtio_pci.h" #include "standard-headers/linux/virtio_scsi.h" diff --git a/tests/qtest/libqos/qgraph.h b/tests/qtest/libqos/qgraph.h index 10543269ce..5f63d352ca 100644 --- a/tests/qtest/libqos/qgraph.h +++ b/tests/qtest/libqos/qgraph.h @@ -226,7 +226,7 @@ typedef void *(*QOSBeforeTest) (GString *cmd_line, void *arg); * my_test <--consumed_by-- my_interface <--produces--+ * * Assuming there the binary is - * QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 + * QTEST_QEMU_BINARY=./qemu-system-x86_64 * a valid test path will be: * "/x86_64/pc/other_node/my_driver/my_interface/my_test". * diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 30cb88d919..8f8fdb1336 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -234,7 +234,7 @@ foreach dir : target_dirs qtest_env = environment() qtest_env.set('QTEST_QEMU_IMG', './qemu-img') qtest_env.set('G_TEST_DBUS_DAEMON', meson.source_root() / 'tests/dbus-vmstate-daemon.sh') - qtest_env.set('QTEST_QEMU_BINARY', '@0@-softmmu/qemu-system-@0@'.format(target_base)) + qtest_env.set('QTEST_QEMU_BINARY', './qemu-system-' + target_base) foreach test : qtests # Executables are shared across targets, declare them only the first time we diff --git a/tests/qtest/rtas-test.c b/tests/qtest/rtas-test.c index a7e83e7d40..16751dbd2f 100644 --- a/tests/qtest/rtas-test.c +++ b/tests/qtest/rtas-test.c @@ -31,7 +31,7 @@ int main(int argc, char *argv[]) g_test_init(&argc, &argv, NULL); if (strcmp(arch, "ppc64")) { - g_printerr("RTAS requires ppc64-softmmu/qemu-system-ppc64\n"); + g_printerr("RTAS requires qemu-system-ppc64\n"); exit(EXIT_FAILURE); } qtest_add_func("rtas/get-time-of-day", test_rtas_get_time_of_day); diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 102578caa5..7d714f902a 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -193,11 +193,11 @@ for target in $target_list; do case $target in *-linux-user | *-bsd-user) echo "CONFIG_USER_ONLY=y" >> $config_target_mak - echo "QEMU=\$(BUILD_DIR)/$target/qemu-$arch" >> $config_target_mak + echo "QEMU=\$(BUILD_DIR)/qemu-$arch" >> $config_target_mak ;; *-softmmu) echo "CONFIG_SOFTMMU=y" >> $config_target_mak - echo "QEMU=\$(BUILD_DIR)/$target/qemu-system-$arch" >> $config_target_mak + echo "QEMU=\$(BUILD_DIR)/qemu-system-$arch" >> $config_target_mak ;; esac diff --git a/util/module.c b/util/module.c index 0ab00851f0..c956ef096b 100644 --- a/util/module.c +++ b/util/module.c @@ -205,7 +205,6 @@ bool module_load_one(const char *prefix, const char *lib_name) dirs[n_dirs++] = g_strdup_printf("%s", search_dir); } dirs[n_dirs++] = g_strdup_printf("%s", CONFIG_QEMU_MODDIR); - dirs[n_dirs++] = g_strdup_printf("%s/..", exec_dir ? : ""); dirs[n_dirs++] = g_strdup_printf("%s", exec_dir ? : ""); #ifdef CONFIG_MODULE_UPGRADES -- cgit v1.2.3-55-g7522 From 2898503c03369fcac64645210517e9d83a406eb6 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 19 Aug 2020 15:36:59 -0400 Subject: configure: place compatibility symlinks in target directories Signed-off-by: Paolo Bonzini --- configure | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configure b/configure index 74113e0e9f..4b941a3b61 100755 --- a/configure +++ b/configure @@ -8219,6 +8219,9 @@ fi if test "$target_user_only" = "yes" ; then echo "CONFIG_USER_ONLY=y" >> $config_target_mak echo "CONFIG_QEMU_INTERP_PREFIX=\"$interp_prefix1\"" >> $config_target_mak + symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" +else + symlink "../qemu-system-$target_name" "$target_dir/qemu-system-$target_name" fi if test "$target_linux_user" = "yes" ; then echo "CONFIG_LINUX_USER=y" >> $config_target_mak -- cgit v1.2.3-55-g7522 From 10e1d2636dc607eaf0aa3f534e834cd2bf018750 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Tue, 20 Aug 2019 12:29:52 +0400 Subject: meson: convert systemtap files Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile.target | 85 ++----------------------------------------------------- meson.build | 24 ++++++++++++++++ rules.mak | 3 -- trace/meson.build | 14 ++++----- 4 files changed, 33 insertions(+), 93 deletions(-) diff --git a/Makefile.target b/Makefile.target index 8ee4c78b3f..a07149c0a6 100644 --- a/Makefile.target +++ b/Makefile.target @@ -6,88 +6,7 @@ include ../config-host.mak include config-target.mak include $(SRC_PATH)/rules.mak -$(call set-vpath, $(SRC_PATH):$(BUILD_DIR)) - -ifdef CONFIG_USER_ONLY -# user emulator name -QEMU_PROG=qemu-$(TARGET_NAME) -else -# system emulator name -QEMU_PROG=qemu-system-$(TARGET_NAME)$(EXESUF) -endif - -STPFILES= - -ifdef CONFIG_TRACE_SYSTEMTAP -stap: $(QEMU_PROG).stp-installed $(QEMU_PROG).stp $(QEMU_PROG)-simpletrace.stp $(QEMU_PROG)-log.stp - -ifdef CONFIG_USER_ONLY -TARGET_TYPE=user -else -TARGET_TYPE=system -endif - -tracetool-y = $(SRC_PATH)/scripts/tracetool.py -tracetool-y += $(shell find $(SRC_PATH)/scripts/tracetool -name "*.py") - -$(QEMU_PROG).stp-installed: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=stap \ - --backends=$(TRACE_BACKENDS) \ - --binary=$(bindir)/$(QEMU_PROG) \ - --target-name=$(TARGET_NAME) \ - --target-type=$(TARGET_TYPE) \ - $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG).stp-installed") - -$(QEMU_PROG).stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=stap \ - --backends=$(TRACE_BACKENDS) \ - --binary=$(realpath .)/$(QEMU_PROG) \ - --target-name=$(TARGET_NAME) \ - --target-type=$(TARGET_TYPE) \ - $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG).stp") - -$(QEMU_PROG)-simpletrace.stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=simpletrace-stap \ - --backends=$(TRACE_BACKENDS) \ - --probe-prefix=qemu.$(TARGET_TYPE).$(TARGET_NAME) \ - $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG)-simpletrace.stp") - -$(QEMU_PROG)-log.stp: $(BUILD_DIR)/trace/trace-events-all $(tracetool-y) - $(call quiet-command,$(TRACETOOL) \ - --group=all \ - --format=log-stap \ - --backends=$(TRACE_BACKENDS) \ - --probe-prefix=qemu.$(TARGET_TYPE).$(TARGET_NAME) \ - $< > $@,"GEN","$(TARGET_DIR)$(QEMU_PROG)-log.stp") - -else -stap: -endif -.PHONY: stap - -all: stap - -clean: - rm -f *.a *~ - rm -f $(shell find . -name '*.[od]') - rm -f hmp-commands.h gdbstub-xml.c - rm -f trace/generated-helpers.c trace/generated-helpers.c-timestamp -ifdef CONFIG_TRACE_SYSTEMTAP - rm -f *.stp -endif - +all: install: all -ifdef CONFIG_TRACE_SYSTEMTAP - $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset" - $(INSTALL_DATA) $(QEMU_PROG).stp-installed "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG).stp" - $(INSTALL_DATA) $(QEMU_PROG)-simpletrace.stp "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG)-simpletrace.stp" - $(INSTALL_DATA) $(QEMU_PROG)-log.stp "$(DESTDIR)$(qemu_datadir)/../systemtap/tapset/$(QEMU_PROG)-log.stp" -endif - + .PHONY: all clean install diff --git a/meson.build b/meson.build index 9db1b7b705..108706f7e5 100644 --- a/meson.build +++ b/meson.build @@ -958,6 +958,30 @@ foreach target : target_dirs link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []), link_args: link_args, gui_app: exe['gui']) + + if 'CONFIG_TRACE_SYSTEMTAP' in config_host + foreach stp: [ + {'ext': '.stp-build', 'fmt': 'stap', 'bin': meson.current_build_dir() / exe_name, 'install': false}, + {'ext': '.stp', 'fmt': 'stap', 'bin': get_option('prefix') / get_option('bindir') / exe_name, 'install': true}, + {'ext': '-simpletrace.stp', 'fmt': 'simpletrace-stap', 'bin': '', 'install': true}, + {'ext': '-log.stp', 'fmt': 'log-stap', 'bin': '', 'install': true}, + ] + custom_target(exe_name + stp['ext'], + input: trace_events_all, + output: exe_name + stp['ext'], + capture: true, + install: stp['install'], + install_dir: config_host['qemu_datadir'] / '../systemtap/tapset', + command: [ + tracetool, '--group=all', '--format=' + stp['fmt'], + '--binary=' + stp['bin'], + '--target-name=' + target_name, + '--target-type=' + target_type, + '--probe-prefix=qemu.' + target_type + '.' + target_name, + '@INPUT@', + ]) + endforeach + endif endforeach endforeach diff --git a/rules.mak b/rules.mak index 6488dc3dc6..b983c7f83f 100644 --- a/rules.mak +++ b/rules.mak @@ -199,9 +199,6 @@ ne = $(if $(subst $2,,$1)$(subst $1,,$2),y,n) isempty = $(if $1,n,y) notempty = $(if $1,y,n) -# Generate files with tracetool -TRACETOOL=$(PYTHON) $(SRC_PATH)/scripts/tracetool.py - .PHONY: clean-timestamp clean-timestamp: rm -f *.timestamp diff --git a/trace/meson.build b/trace/meson.build index 9c3c128164..56e870848e 100644 --- a/trace/meson.build +++ b/trace/meson.build @@ -49,13 +49,13 @@ foreach dir : [ '.' ] + trace_events_subdirs endif endforeach -custom_target('trace-events-all', - output: 'trace-events-all', - input: trace_events_files, - command: [ 'cat', '@INPUT@' ], - capture: true, - install: true, - install_dir: config_host['qemu_datadir']) +trace_events_all = custom_target('trace-events-all', + output: 'trace-events-all', + input: trace_events_files, + command: [ 'cat', '@INPUT@' ], + capture: true, + install: true, + install_dir: config_host['qemu_datadir']) foreach d : [ ['generated-tcg-tracers.h', 'tcg-h'], -- cgit v1.2.3-55-g7522 From 8000047e992c2d6f9984c525e8617ec5f94f4cc8 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Wed, 4 Sep 2019 16:51:52 +0400 Subject: rules.mak: remove version.o Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 5 ----- Makefile.objs | 4 ---- rules.mak | 4 +--- 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/Makefile b/Makefile index fe8c63acad..1bd6106f87 100644 --- a/Makefile +++ b/Makefile @@ -241,11 +241,6 @@ recurse-clean: $(addsuffix /clean, $(TARGET_DIRS) $(ROM_DIRS)) recurse-install: $(addsuffix /install, $(TARGET_DIRS)) $(addsuffix /install, $(TARGET_DIRS)): all -$(BUILD_DIR)/version.o: $(SRC_PATH)/version.rc config-host.h - $(call quiet-command,$(WINDRES) -I$(BUILD_DIR) -o $@ $<,"RC","version.o") - -Makefile: $(version-obj-y) - ###################################################################### clean: recurse-clean ninja-clean clean-ctlist diff --git a/Makefile.objs b/Makefile.objs index 5295c3a623..c351b59641 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -32,7 +32,3 @@ crypto-obj-y = crypto/libcrypto.fa io-obj-y = io/libio.fa endif # CONFIG_SOFTMMU or CONFIG_TOOLS - -###################################################################### -# Resource file for Windows executables -version-obj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.o diff --git a/rules.mak b/rules.mak index b983c7f83f..6d89001f0a 100644 --- a/rules.mak +++ b/rules.mak @@ -77,8 +77,6 @@ expand-objs = $(strip $(sort $(filter %.o,$1)) \ $(call quiet-command,$(CC) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) \ -c -o $@ $<,"CC","$(TARGET_DIR)$@") -%.o: %.rc - $(call quiet-command,$(WINDRES) -I. -o $@ $<,"RC","$(TARGET_DIR)$@") # If we have a CXX we might have some C++ objects, in which case we # must link with the C++ compiler, not the plain C compiler. @@ -86,7 +84,7 @@ LINKPROG = $(or $(CXX),$(CC)) LINK = $(call quiet-command, $(LINKPROG) $(CFLAGS) $(QEMU_LDFLAGS) -o $@ \ $(call process-archive-undefs, $1) \ - $(version-obj-y) $(call extract-libs,$1) $(LIBS),"LINK","$(TARGET_DIR)$@") + $(call extract-libs,$1) $(LIBS),"LINK","$(TARGET_DIR)$@") %.o: %.S $(call quiet-command,$(CCAS) $(QEMU_LOCAL_INCLUDES) $(QEMU_INCLUDES) \ -- cgit v1.2.3-55-g7522 From 5e6d1573b493a0ec4982a0fecd5169d38d997e4e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 5 Aug 2020 13:05:13 +0200 Subject: remove Makefile.target Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 53 ++++------------------------------------------------- Makefile.target | 12 ------------ configure | 15 --------------- 3 files changed, 4 insertions(+), 76 deletions(-) delete mode 100644 Makefile.target diff --git a/Makefile b/Makefile index 1bd6106f87..07b7ae4036 100644 --- a/Makefile +++ b/Makefile @@ -179,17 +179,6 @@ include $(SRC_PATH)/tests/Makefile.include all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) recurse-all modules -config-host.h: config-host.h-timestamp -config-host.h-timestamp: config-host.mak - -TARGET_DIRS_RULES := $(foreach t, all fuzz clean install, $(addsuffix /$(t), $(TARGET_DIRS))) - -.PHONY: $(TARGET_DIRS_RULES) -# The $(TARGET_DIRS_RULES) are of the form SUBDIR/GOAL, so that -# $(dir $@) yields the sub-directory, and $(notdir $@) yields the sub-goal -$(TARGET_DIRS_RULES): $(TARGET_DEPS) - $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $(dir $@) V="$(V)" TARGET_DIR="$(dir $@)" $(notdir $@),) - # LIBFDT_lib="": avoid breaking existing trees with objects requiring -fPIC DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" LIBFDT_lib="" DTC_CFLAGS=$(CFLAGS) $(QEMU_CFLAGS) @@ -226,8 +215,6 @@ slirp/all: .git-submodule-status CC="$(CC)" AR="$(AR)" LD="$(LD)" RANLIB="$(RANLIB)" \ CFLAGS="$(QEMU_CFLAGS) $(CFLAGS)" LDFLAGS="$(QEMU_LDFLAGS)") -$(filter %/all, $(TARGET_DIRS_RULES)): - ROM_DIRS = $(addprefix pc-bios/, $(ROMS)) ROM_DIRS_RULES=$(foreach t, all clean, $(addsuffix /$(t), $(ROM_DIRS))) # Only keep -O and -g cflags @@ -235,11 +222,9 @@ ROM_DIRS_RULES=$(foreach t, all clean, $(addsuffix /$(t), $(ROM_DIRS))) $(ROM_DIRS_RULES): $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $(dir $@) V="$(V)" TARGET_DIR="$(dir $@)" CFLAGS="$(filter -O% -g%,$(CFLAGS))" $(notdir $@),) -.PHONY: recurse-all recurse-clean recurse-install -recurse-all: $(addsuffix /all, $(TARGET_DIRS) $(ROM_DIRS)) -recurse-clean: $(addsuffix /clean, $(TARGET_DIRS) $(ROM_DIRS)) -recurse-install: $(addsuffix /install, $(TARGET_DIRS)) -$(addsuffix /install, $(TARGET_DIRS)): all +.PHONY: recurse-all recurse-clean +recurse-all: $(ROM_DIRS) +recurse-clean: $(addsuffix /clean, $(ROM_DIRS)) ###################################################################### @@ -294,9 +279,6 @@ distclean: clean ninja-distclean $(call clean-manual,system) $(call clean-manual,tools) $(call clean-manual,user) - for d in $(TARGET_DIRS); do \ - rm -rf $$d || exit 1 ; \ - done rm -Rf .sdk KEYMAPS=da en-gb et fr fr-ch is lt no pt-br sv \ @@ -400,8 +382,7 @@ ICON_SIZES=16x16 24x24 32x32 48x48 64x64 128x128 256x256 512x512 # Needed by "meson install" export DESTDIR install: all $(if $(BUILD_DOCS),install-doc) \ - install-datadir install-localstatedir \ - recurse-install + install-datadir install-localstatedir ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_PROG) "scripts/qemu-trace-stap" $(DESTDIR)$(bindir) endif @@ -431,9 +412,6 @@ endif set -e; for x in $(KEYMAPS); do \ $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x "$(DESTDIR)$(qemu_datadir)/keymaps"; \ done - for d in $(TARGET_DIRS); do \ - $(MAKE) $(SUBDIR_MAKEFLAGS) TARGET_DIR=$$d/ -C $$d $@ || exit 1 ; \ - done # documentation MAKEINFO=makeinfo @@ -548,20 +526,6 @@ docs/interop/qemu-qmp-ref.dvi docs/interop/qemu-qmp-ref.html \ $(filter %.1 %.7 %.8,$(DOCS)): scripts/texi2pod.pl -# Reports/Analysis - -%/coverage-report.html: - @mkdir -p $* - $(call quiet-command,\ - gcovr -r $(SRC_PATH) \ - $(foreach t, $(TARGET_DIRS), --object-directory $(BUILD_DIR)/$(t)) \ - --object-directory $(BUILD_DIR) \ - -p --html --html-details -o $@, \ - "GEN", "coverage-report.html") - -.PHONY: coverage-report -coverage-report: $(CURDIR)/reports/coverage/coverage-report.html - ifdef CONFIG_WIN32 INSTALLER = qemu-setup-$(VERSION)$(EXESUF) @@ -649,15 +613,6 @@ endif $(call print-help,cscope,Generate cscope index) $(call print-help,sparse,Run sparse on the QEMU source) @echo '' - @$(if $(TARGET_DIRS), \ - echo 'Architecture specific targets:'; \ - $(foreach t, $(TARGET_DIRS), \ - $(call print-help-run,$(t)/all,Build for $(t)); \ - $(if $(CONFIG_FUZZ), \ - $(if $(findstring softmmu,$(t)), \ - $(call print-help-run,$(t)/fuzz,Build fuzzer for $(t)); \ - ))) \ - echo '') @echo 'Cleaning targets:' $(call print-help,clean,Remove most generated files but keep the config) $(call print-help,distclean,Remove all generated files) diff --git a/Makefile.target b/Makefile.target deleted file mode 100644 index a07149c0a6..0000000000 --- a/Makefile.target +++ /dev/null @@ -1,12 +0,0 @@ -# -*- Mode: makefile -*- - -BUILD_DIR?=$(CURDIR)/.. - -include ../config-host.mak -include config-target.mak -include $(SRC_PATH)/rules.mak - -all: -install: all - -.PHONY: all clean install diff --git a/configure b/configure index 4b941a3b61..79d48f8e79 100755 --- a/configure +++ b/configure @@ -362,7 +362,6 @@ audio_drv_list="" block_drv_rw_whitelist="" block_drv_ro_whitelist="" host_cc="cc" -libs_softmmu="" libs_tools="" audio_win_int="" libs_qga="" @@ -911,7 +910,6 @@ Darwin) audio_drv_list="coreaudio try-sdl" audio_possible_drivers="coreaudio sdl" QEMU_LDFLAGS="-framework CoreFoundation -framework IOKit $QEMU_LDFLAGS" - libs_softmmu="-F/System/Library/Frameworks -framework Cocoa -framework IOKit $libs_softmmu" # Disable attempts to use ObjectiveC features in os/object.h since they # won't work when we're compiling with gcc as a C compiler. QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" @@ -2604,7 +2602,6 @@ if test "$lzo" != "no" ; then int main(void) { lzo_version(); return 0; } EOF if compile_prog "" "-llzo2" ; then - libs_softmmu="$libs_softmmu -llzo2" lzo_libs="-llzo2" lzo="yes" else @@ -2624,7 +2621,6 @@ if test "$snappy" != "no" ; then int main(void) { snappy_max_compressed_length(4096); return 0; } EOF if compile_prog "" "-lsnappy" ; then - libs_softmmu="$libs_softmmu -lsnappy" snappy_libs='-lsnappy' snappy="yes" else @@ -2724,7 +2720,6 @@ if test "$xen" != "no" ; then xen_pc="$xen_pc xentoolcore" fi QEMU_CFLAGS="$QEMU_CFLAGS $($pkg_config --cflags $xen_pc)" - libs_softmmu="$($pkg_config --libs $xen_pc) $libs_softmmu" xen_cflags="$($pkg_config --cflags $xen_pc)" xen_libs="$($pkg_config --libs $xen_pc)" else @@ -3469,7 +3464,6 @@ EOF rdma_libs="-lrdmacm -libverbs -libumad" if compile_prog "" "$rdma_libs" ; then rdma="yes" - libs_softmmu="$libs_softmmu $rdma_libs" else if test "$rdma" = "yes" ; then error_exit \ @@ -4500,8 +4494,6 @@ EOF fi fi -libs_softmmu="$libs_softmmu $fdt_libs" - ########################################## # opengl probe (for sdl2, gtk, milkymist-tmu2) @@ -4725,7 +4717,6 @@ EOF if compile_prog "" "-lnuma" ; then numa=yes - libs_softmmu="-lnuma $libs_softmmu" numa_libs="-lnuma" else if test "$numa" = "yes" ; then @@ -5267,7 +5258,6 @@ if compile_prog "" "" ; then have_openpty="yes" else if compile_prog "" "-lutil" ; then - libs_softmmu="-lutil $libs_softmmu" libs_tools="-lutil $libs_tools" have_openpty="yes" fi @@ -5286,7 +5276,6 @@ EOF $pkg_config --atleast-version=0.12.3 spice-protocol && \ compile_prog "$spice_cflags" "$spice_libs" ; then spice="yes" - libs_softmmu="$libs_softmmu $spice_libs" QEMU_CFLAGS="$QEMU_CFLAGS $spice_cflags" else if test "$spice" = "yes" ; then @@ -6439,7 +6428,6 @@ if test "$libpmem" != "no"; then libpmem="yes" libpmem_libs=$($pkg_config --libs libpmem) libpmem_cflags=$($pkg_config --cflags libpmem) - libs_softmmu="$libs_softmmu $libpmem_libs" QEMU_CFLAGS="$QEMU_CFLAGS $libpmem_cflags" else if test "$libpmem" = "yes" ; then @@ -6457,7 +6445,6 @@ if test "$libdaxctl" != "no"; then libdaxctl="yes" libdaxctl_libs=$($pkg_config --libs libdaxctl) libdaxctl_cflags=$($pkg_config --cflags libdaxctl) - libs_softmmu="$libs_softmmu $libdaxctl_libs" QEMU_CFLAGS="$QEMU_CFLAGS $libdaxctl_cflags" else if test "$libdaxctl" = "yes" ; then @@ -6886,7 +6873,6 @@ echo_version() { # prepend pixman and ftd flags after all config tests are done QEMU_CFLAGS="$pixman_cflags $fdt_cflags $QEMU_CFLAGS" QEMU_LDFLAGS="$fdt_ldflags $QEMU_LDFLAGS" -libs_softmmu="$pixman_libs $libs_softmmu" config_host_mak="config-host.mak" @@ -6915,7 +6901,6 @@ echo "qemu_helperdir=$libexecdir" >> $config_host_mak echo "qemu_localedir=$qemu_localedir" >> $config_host_mak echo "qemu_icondir=$qemu_icondir" >> $config_host_mak echo "qemu_desktopdir=$qemu_desktopdir" >> $config_host_mak -echo "libs_softmmu=$libs_softmmu" >> $config_host_mak echo "GIT=$git" >> $config_host_mak echo "GIT_SUBMODULES=$git_submodules" >> $config_host_mak echo "GIT_UPDATE=$git_update" >> $config_host_mak -- cgit v1.2.3-55-g7522 From f8aa24ea9a82da38370470c6bc0eaa393999edfe Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 5 Aug 2020 15:49:10 +0200 Subject: meson: sphinx-build For now, sphinx is run on every invocation of make. The previous mechanism using $(wildcard) is not reproducible in Meson and was also brittle; for example some .rst.inc files were left out. The next patch will introduce a Sphinx extension to emit a depfile. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 142 +++-------------------------------------------------- configure | 1 - docs/index.html.in | 4 +- docs/meson.build | 68 +++++++++++++++++++++++++ meson.build | 2 + rules.mak | 48 ------------------ 6 files changed, 79 insertions(+), 186 deletions(-) create mode 100644 docs/meson.build diff --git a/Makefile b/Makefile index 07b7ae4036..511c7102b1 100644 --- a/Makefile +++ b/Makefile @@ -135,36 +135,9 @@ $(call set-vpath, $(SRC_PATH)) LIBS+=-lz $(LIBS_TOOLS) -# Sphinx does not allow building manuals into the same directory as -# the source files, so if we're doing an in-tree QEMU build we must -# build the manuals into a subdirectory (and then install them from -# there for 'make install'). For an out-of-tree build we can just -# use the docs/ subdirectory in the build tree as normal. -ifeq ($(realpath $(SRC_PATH)),$(realpath .)) -MANUAL_BUILDDIR := docs/built -else -MANUAL_BUILDDIR := docs -endif - ifdef BUILD_DOCS -DOCS+=$(MANUAL_BUILDDIR)/system/qemu.1 -DOCS+=$(MANUAL_BUILDDIR)/tools/qemu-img.1 -DOCS+=$(MANUAL_BUILDDIR)/tools/qemu-nbd.8 -DOCS+=$(MANUAL_BUILDDIR)/interop/qemu-ga.8 -ifeq ($(CONFIG_LINUX)$(CONFIG_SECCOMP)$(CONFIG_LIBCAP_NG),yyy) -DOCS+=$(MANUAL_BUILDDIR)/tools/virtiofsd.1 -endif -DOCS+=$(MANUAL_BUILDDIR)/system/qemu-block-drivers.7 DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7 DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7 -DOCS+=$(MANUAL_BUILDDIR)/system/qemu-cpu-models.7 -DOCS+=$(MANUAL_BUILDDIR)/index.html -ifdef CONFIG_VIRTFS -DOCS+=$(MANUAL_BUILDDIR)/tools/virtfs-proxy-helper.1 -endif -ifdef CONFIG_TRACE_SYSTEMTAP -DOCS+=$(MANUAL_BUILDDIR)/tools/qemu-trace-stap.1 -endif else DOCS= endif @@ -248,11 +221,6 @@ dist: qemu-$(VERSION).tar.bz2 qemu-%.tar.bz2: $(SRC_PATH)/scripts/make-release "$(SRC_PATH)" "$(patsubst qemu-%.tar.bz2,%,$@)" -define clean-manual = -rm -rf $(MANUAL_BUILDDIR)/$1/_static -rm -f $(MANUAL_BUILDDIR)/$1/objects.inv $(MANUAL_BUILDDIR)/$1/searchindex.js $(MANUAL_BUILDDIR)/$1/*.html -endef - distclean: clean ninja-distclean -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean -g rm -f config-host.mak config-host.h* $(DOCS) @@ -272,13 +240,6 @@ distclean: clean ninja-distclean rm -f docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html - rm -rf .doctrees - $(call clean-manual,devel) - $(call clean-manual,interop) - $(call clean-manual,specs) - $(call clean-manual,system) - $(call clean-manual,tools) - $(call clean-manual,user) rm -Rf .sdk KEYMAPS=da en-gb et fr fr-ch is lt no pt-br sv \ @@ -312,28 +273,8 @@ else BLOBS= endif -# Note that we manually filter-out the non-Sphinx documentation which -# is currently built into the docs/interop directory in the build tree, -# and also any sphinx-built manpages. -define install-manual = -for d in $$(cd $(MANUAL_BUILDDIR) && find $1 -type d); do $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)/$$d"; done -for f in $$(cd $(MANUAL_BUILDDIR) && find $1 -type f -a '!' '(' -name '*.[0-9]' -o -name 'qemu-*-qapi.*' -o -name 'qemu-*-ref.*' ')' ); do $(INSTALL_DATA) "$(MANUAL_BUILDDIR)/$$f" "$(DESTDIR)$(qemu_docdir)/$$f"; done -endef - -# Note that we deliberately do not install the "devel" manual: it is -# for QEMU developers, and not interesting to our users. -.PHONY: install-sphinxdocs -install-sphinxdocs: sphinxdocs - $(call install-manual,interop) - $(call install-manual,specs) - $(call install-manual,system) - $(call install-manual,tools) - $(call install-manual,user) - -install-doc: $(DOCS) install-sphinxdocs +install-doc: $(DOCS) $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/index.html "$(DESTDIR)$(qemu_docdir)" - $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-qmp-ref.html "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-qmp-ref.txt "$(DESTDIR)$(qemu_docdir)/interop" ifdef CONFIG_POSIX @@ -341,19 +282,7 @@ ifdef CONFIG_POSIX $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu.1 "$(DESTDIR)$(mandir)/man1" $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7" $(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu-block-drivers.7 "$(DESTDIR)$(mandir)/man7" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu-cpu-models.7 "$(DESTDIR)$(mandir)/man7" -ifeq ($(CONFIG_TOOLS),y) - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/qemu-img.1 "$(DESTDIR)$(mandir)/man1" - $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man8" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/qemu-nbd.8 "$(DESTDIR)$(mandir)/man8" -endif -ifdef CONFIG_TRACE_SYSTEMTAP - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/qemu-trace-stap.1 "$(DESTDIR)$(mandir)/man1" -endif ifeq ($(CONFIG_GUEST_AGENT),y) - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/interop/qemu-ga.8 "$(DESTDIR)$(mandir)/man8" - $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-ga-ref.html "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-ga-ref.txt "$(DESTDIR)$(qemu_docdir)/interop" $(INSTALL_DATA) docs/interop/qemu-ga-ref.7 "$(DESTDIR)$(mandir)/man7" @@ -440,69 +369,6 @@ docs/version.texi: $(SRC_PATH)/VERSION config-host.mak %.pdf: %.texi docs/version.texi $(call quiet-command,texi2pdf $(TEXI2PDFFLAGS) $< -o $@,"GEN","$@") -# Sphinx builds all its documentation at once in one invocation -# and handles "don't rebuild things unless necessary" itself. -# The '.doctrees' files are cached information to speed this up. -.PHONY: sphinxdocs -sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html \ - $(MANUAL_BUILDDIR)/interop/index.html \ - $(MANUAL_BUILDDIR)/specs/index.html \ - $(MANUAL_BUILDDIR)/system/index.html \ - $(MANUAL_BUILDDIR)/tools/index.html \ - $(MANUAL_BUILDDIR)/user/index.html - -# Canned command to build a single manual -# Arguments: $1 = manual name, $2 = Sphinx builder ('html' or 'man') -# Note the use of different doctree for each (manual, builder) tuple; -# this works around Sphinx not handling parallel invocation on -# a single doctree: https://github.com/sphinx-doc/sphinx/issues/2946 -build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" $(SPHINX_BUILD) $(if $(V),,-q) $(SPHINX_WERROR) -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1-$2 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1") -# We assume all RST files in the manual's directory are used in it -manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst $(SRC_PATH)/docs/$1/*/*.rst) \ - $(SRC_PATH)/docs/defs.rst.inc \ - $(SRC_PATH)/docs/$1/conf.py $(SRC_PATH)/docs/conf.py \ - $(SRC_PATH)/docs/sphinx/*.py -# Macro to write out the rule and dependencies for building manpages -# Usage: $(call define-manpage-rule,manualname,manpage1 manpage2...[,extradeps]) -# 'extradeps' is optional, and specifies extra files (eg .hx files) that -# the manual page depends on. -define define-manpage-rule -$(call atomic,$(foreach manpage,$2,$(MANUAL_BUILDDIR)/$1/$(manpage)),$(call manual-deps,$1) $3) - $(call build-manual,$1,man) -endef - -$(MANUAL_BUILDDIR)/devel/index.html: $(call manual-deps,devel) - $(call build-manual,devel,html) - -$(MANUAL_BUILDDIR)/interop/index.html: $(call manual-deps,interop) - $(call build-manual,interop,html) - -$(MANUAL_BUILDDIR)/specs/index.html: $(call manual-deps,specs) - $(call build-manual,specs,html) - -$(MANUAL_BUILDDIR)/system/index.html: $(call manual-deps,system) $(SRC_PATH)/hmp-commands.hx $(SRC_PATH)/hmp-commands-info.hx $(SRC_PATH)/qemu-options.hx - $(call build-manual,system,html) - -$(MANUAL_BUILDDIR)/tools/index.html: $(call manual-deps,tools) $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/docs/qemu-option-trace.rst.inc - $(call build-manual,tools,html) - -$(MANUAL_BUILDDIR)/user/index.html: $(call manual-deps,user) - $(call build-manual,user,html) - -$(call define-manpage-rule,interop,qemu-ga.8) - -$(call define-manpage-rule,system,qemu.1 qemu-block-drivers.7 qemu-cpu-models.7) - -$(call define-manpage-rule,tools,\ - qemu-img.1 qemu-nbd.8 qemu-trace-stap.1\ - virtiofsd.1 virtfs-proxy-helper.1,\ - $(SRC_PATH)/qemu-img-cmds.hx $(SRC_PATH)/docs/qemu-option-trace.rst.inc) - -$(MANUAL_BUILDDIR)/index.html: $(SRC_PATH)/docs/index.html.in qemu-version.h - @mkdir -p "$(MANUAL_BUILDDIR)" - $(call quiet-command, sed "s|@@VERSION@@|${VERSION}|g" $< >$@, \ - "GEN","$@") - docs/interop/qemu-qmp-qapi.texi: qapi/qapi-doc.texi @cp -p $< $@ @@ -525,6 +391,12 @@ docs/interop/qemu-qmp-ref.dvi docs/interop/qemu-qmp-ref.html \ docs/interop/qemu-qmp-ref.texi docs/interop/qemu-qmp-qapi.texi $(filter %.1 %.7 %.8,$(DOCS)): scripts/texi2pod.pl + $(call quiet-command, \ + perl -Ww -- $(SRC_PATH)/scripts/texi2pod.pl $(TEXI2PODFLAGS) $< $@.pod && \ + $(POD2MAN) --section=$(subst .,,$(suffix $@)) --center=" " --release=" " $@.pod > $@, \ + "GEN","$@") + +man: $(filter %.1 %.7 %.8,$(DOCS)) ifdef CONFIG_WIN32 diff --git a/configure b/configure index 79d48f8e79..77f2616e61 100755 --- a/configure +++ b/configure @@ -7824,7 +7824,6 @@ echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak echo "PYTHON=$python" >> $config_host_mak echo "SPHINX_BUILD=$sphinx_build" >> $config_host_mak -echo "SPHINX_WERROR=$sphinx_werror" >> $config_host_mak echo "GENISOIMAGE=$genisoimage" >> $config_host_mak echo "MESON=$meson" >> $config_host_mak echo "CC=$cc" >> $config_host_mak diff --git a/docs/index.html.in b/docs/index.html.in index 6736fa4360..ca28047881 100644 --- a/docs/index.html.in +++ b/docs/index.html.in @@ -2,10 +2,10 @@ - QEMU @@VERSION@@ Documentation + QEMU @VERSION@ Documentation -

QEMU @@VERSION@@ Documentation

+

QEMU @VERSION@ Documentation

  • System Emulation User's Guide
  • User Mode Emulation User's Guide
    • diff --git a/docs/meson.build b/docs/meson.build new file mode 100644 index 0000000000..20fc92e2fe --- /dev/null +++ b/docs/meson.build @@ -0,0 +1,68 @@ +SPHINX_ARGS = [config_host['SPHINX_BUILD'], + '-Dversion=' + meson.project_version(), + '-Drelease=' + config_host['PKGVERSION']] + +if get_option('werror') + SPHINX_ARGS += [ '-W' ] +endif + +if build_docs + configure_file(output: 'index.html', + input: files('index.html.in'), + configuration: {'VERSION': meson.project_version()}, + install_dir: config_host['qemu_docdir']) + manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ] + man_pages = { + 'interop' : { + 'qemu-ga.8': (have_tools ? 'man8' : ''), + }, + 'tools': { + 'qemu-img.1': (have_tools ? 'man1' : ''), + 'qemu-nbd.8': (have_tools ? 'man8' : ''), + 'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''), + 'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''), + 'virtiofsd.1': (have_virtiofsd ? 'man1' : ''), + }, + 'system': { + 'qemu.1': 'man1', + 'qemu-block-drivers.7': 'man7', + 'qemu-cpu-models.7': 'man7' + }, + } + + sphinxdocs = [] + sphinxmans = [] + foreach manual : manuals + private_dir = meson.current_build_dir() / (manual + '.p') + input_dir = meson.current_source_dir() / manual + sphinxdocs += custom_target(manual + ' manual', + build_always_stale: true, + build_by_default: build_docs, + output: manual, + command: [SPHINX_ARGS, '-b', 'html', '-d', private_dir, + input_dir, meson.current_build_dir() / manual]) + if build_docs and manual != 'devel' + install_subdir(meson.current_build_dir() / manual, + install_dir: config_host['qemu_docdir']) + endif + + these_man_pages = [] + install_dirs = [] + foreach page, section : man_pages.get(manual, {}) + these_man_pages += page + install_dirs += section == '' ? false : get_option('mandir') / section + endforeach + if these_man_pages.length() > 0 + sphinxmans += custom_target(manual + ' man pages', + build_always_stale: true, + build_by_default: build_docs, + output: these_man_pages, + install: build_docs, + install_dir: install_dirs, + command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, + input_dir, meson.current_build_dir()]) + endif + endforeach + alias_target('sphinxdocs', sphinxdocs) + alias_target('man', sphinxmans) +endif diff --git a/meson.build b/meson.build index 108706f7e5..e270569f4d 100644 --- a/meson.build +++ b/meson.build @@ -11,6 +11,7 @@ cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') config_all_disas = keyval.load(meson.current_build_dir() / 'config-all-disas.mak') enable_modules = 'CONFIG_MODULES' in config_host +build_docs = 'BUILD_DOCS' in config_host add_project_arguments(config_host['QEMU_CFLAGS'].split(), native: false, language: ['c', 'objc']) @@ -1049,6 +1050,7 @@ endif subdir('tools') subdir('pc-bios') subdir('tests') +subdir('docs') summary_info = {} summary_info += {'Install prefix': config_host['prefix']} diff --git a/rules.mak b/rules.mak index 6d89001f0a..6cab0b9cbd 100644 --- a/rules.mak +++ b/rules.mak @@ -375,53 +375,5 @@ define unnest-vars $(eval $v := $(filter-out %/,$($v)))) endef -TEXI2MAN = $(call quiet-command, \ - perl -Ww -- $(SRC_PATH)/scripts/texi2pod.pl $(TEXI2PODFLAGS) $< $@.pod && \ - $(POD2MAN) --section=$(subst .,,$(suffix $@)) --center=" " --release=" " $@.pod > $@, \ - "GEN","$@") - -%.1: - $(call TEXI2MAN) -%.7: - $(call TEXI2MAN) -%.8: - $(call TEXI2MAN) - -# Support for building multiple output files by atomically executing -# a single rule which depends on several input files (so the rule -# will be executed exactly once, not once per output file, and -# not multiple times in parallel.) For more explanation see: -# https://www.cmcrossroads.com/article/atomic-rules-gnu-make - -# Given a space-separated list of filenames, create the name of -# a 'sentinel' file to use to indicate that they have been built. -# We use fixed text on the end to avoid accidentally triggering -# automatic pattern rules, and . on the start to make the file -# not show up in ls output. -sentinel = .$(subst $(SPACE),_,$(subst /,_,$1)).sentinel. - -# Define an atomic rule that builds multiple outputs from multiple inputs. -# To use: -# $(call atomic,out1 out2 ...,in1 in2 ...) -# rule to do the operation -# -# Make 4.3 will have native support for this, and you would be able -# to instead write: -# out1 out2 ... &: in1 in2 ... -# rule to do the operation -# -# The way this works is that it creates a make rule -# "out1 out2 ... : sentinel-file ; @:" which says that the sentinel -# depends on the dependencies, and the rule to do that is "do nothing". -# Then we have a rule -# "sentinel-file : in1 in2 ..." -# whose commands start with "touch sentinel-file" and then continue -# with the rule text provided by the user of this 'atomic' function. -# The foreach... is there to delete the sentinel file if any of the -# output files don't exist, so that we correctly rebuild in that situation. -atomic = $(eval $1: $(call sentinel,$1) ; @:) \ - $(call sentinel,$1) : $2 ; @touch $$@ \ - $(foreach t,$1,$(if $(wildcard $t),,$(shell rm -f $(call sentinel,$1)))) - print-%: @echo '$*=$($*)' -- cgit v1.2.3-55-g7522 From bac35bf5175fb16470a73492c23161e80361eeeb Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 11 Aug 2020 09:07:04 +0200 Subject: docs: automatically track manual dependencies Signed-off-by: Paolo Bonzini --- docs/conf.py | 2 +- docs/meson.build | 21 +++++++++++++-------- docs/sphinx/depfile.py | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 9 deletions(-) create mode 100644 docs/sphinx/depfile.py diff --git a/docs/conf.py b/docs/conf.py index d6e173ef77..0dbd90dc11 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -67,7 +67,7 @@ needs_sphinx = '1.6' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = ['kerneldoc', 'qmp_lexer', 'hxtool'] +extensions = ['kerneldoc', 'qmp_lexer', 'hxtool', 'depfile'] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] diff --git a/docs/meson.build b/docs/meson.build index 20fc92e2fe..8b059a8e39 100644 --- a/docs/meson.build +++ b/docs/meson.build @@ -34,16 +34,21 @@ if build_docs sphinxmans = [] foreach manual : manuals private_dir = meson.current_build_dir() / (manual + '.p') + output_dir = meson.current_build_dir() / manual input_dir = meson.current_source_dir() / manual - sphinxdocs += custom_target(manual + ' manual', - build_always_stale: true, + + this_manual = custom_target(manual + ' manual', build_by_default: build_docs, - output: manual, - command: [SPHINX_ARGS, '-b', 'html', '-d', private_dir, - input_dir, meson.current_build_dir() / manual]) + output: [manual + '.stamp'], + input: [files('conf.py'), files(manual / 'conf.py')], + depfile: manual + '.d', + command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@', + '-Ddepfile_stamp=@OUTPUT0@', + '-b', 'html', '-d', private_dir, + input_dir, output_dir]) + sphinxdocs += this_manual if build_docs and manual != 'devel' - install_subdir(meson.current_build_dir() / manual, - install_dir: config_host['qemu_docdir']) + install_subdir(output_dir, install_dir: config_host['qemu_docdir']) endif these_man_pages = [] @@ -54,9 +59,9 @@ if build_docs endforeach if these_man_pages.length() > 0 sphinxmans += custom_target(manual + ' man pages', - build_always_stale: true, build_by_default: build_docs, output: these_man_pages, + input: this_manual, install: build_docs, install_dir: install_dirs, command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir, diff --git a/docs/sphinx/depfile.py b/docs/sphinx/depfile.py new file mode 100644 index 0000000000..277fdf0f56 --- /dev/null +++ b/docs/sphinx/depfile.py @@ -0,0 +1,51 @@ +# coding=utf-8 +# +# QEMU depfile generation extension +# +# Copyright (c) 2020 Red Hat, Inc. +# +# This work is licensed under the terms of the GNU GPLv2 or later. +# See the COPYING file in the top-level directory. + +"""depfile is a Sphinx extension that writes a dependency file for + an external build system""" + +import os +import sphinx + +__version__ = '1.0' + +def get_infiles(env): + for x in env.found_docs: + yield env.doc2path(x) + yield from ((os.path.join(env.srcdir, dep) + for dep in env.dependencies[x])) + +def write_depfile(app, env): + if not env.config.depfile: + return + + # Using a directory as the output file does not work great because + # its timestamp does not necessarily change when the contents change. + # So create a timestamp file. + if env.config.depfile_stamp: + with open(env.config.depfile_stamp, 'w') as f: + pass + + with open(env.config.depfile, 'w') as f: + print((env.config.depfile_stamp or app.outdir) + ": \\", file=f) + print(*get_infiles(env), file=f) + for x in get_infiles(env): + print(x + ":", file=f) + + +def setup(app): + app.add_config_value('depfile', None, 'env') + app.add_config_value('depfile_stamp', None, 'env') + app.connect('env-updated', write_depfile) + + return dict( + version = __version__, + parallel_read_safe = True, + parallel_write_safe = True + ) -- cgit v1.2.3-55-g7522 From acfdaac577130e86ebefe5564cfd121c16dbc3c4 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 5 Aug 2020 13:07:48 +0200 Subject: meson: build texi doc Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 106 +++-------------------------------------- docs/interop/qemu-ga-ref.texi | 2 +- docs/interop/qemu-qmp-ref.texi | 2 +- meson.build | 85 +++++++++++++++++++++++++++++++++ qga/meson.build | 12 +++-- version.texi.in | 2 + 6 files changed, 104 insertions(+), 105 deletions(-) create mode 100644 version.texi.in diff --git a/Makefile b/Makefile index 511c7102b1..f442895309 100644 --- a/Makefile +++ b/Makefile @@ -11,7 +11,6 @@ BUILD_DIR=$(CURDIR) SRC_PATH=. UNCHECKED_GOALS := %clean TAGS cscope ctags dist \ - html info pdf txt \ help check-help print-% \ docker docker-% vm-help vm-test vm-build-% @@ -128,20 +127,13 @@ generated-files-y += .git-submodule-status Makefile: ; configure: ; -.PHONY: all clean cscope distclean html info install install-doc \ - pdf txt recurse-all dist msi FORCE +.PHONY: all clean cscope distclean install \ + recurse-all dist msi FORCE $(call set-vpath, $(SRC_PATH)) LIBS+=-lz $(LIBS_TOOLS) -ifdef BUILD_DOCS -DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7 -DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7 -else -DOCS= -endif - SUBDIR_MAKEFLAGS=$(if $(V),,--no-print-directory --quiet) BUILD_DIR=$(BUILD_DIR) ifneq ($(wildcard config-host.mak),) @@ -150,7 +142,7 @@ endif include $(SRC_PATH)/tests/Makefile.include -all: $(DOCS) $(if $(BUILD_DOCS),sphinxdocs) recurse-all modules +all: recurse-all modules # LIBFDT_lib="": avoid breaking existing trees with objects requiring -fPIC DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" LIBFDT_lib="" @@ -223,7 +215,7 @@ qemu-%.tar.bz2: distclean: clean ninja-distclean -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean -g - rm -f config-host.mak config-host.h* $(DOCS) + rm -f config-host.mak config-host.h* rm -f tests/tcg/config-*.mak rm -f config-all-disas.mak config.status rm -f po/*.mo tests/qemu-iotests/common.env @@ -234,12 +226,6 @@ distclean: clean ninja-distclean rm -f Makefile.ninja ninjatool ninjatool.stamp Makefile.mtest rm -f config.log rm -f linux-headers/asm - rm -f docs/version.texi - rm -f docs/interop/qemu-ga-qapi.texi docs/interop/qemu-qmp-qapi.texi - rm -f docs/interop/qemu-qmp-ref.7 docs/interop/qemu-ga-ref.7 - rm -f docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt - rm -f docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf - rm -f docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html rm -Rf .sdk KEYMAPS=da en-gb et fr fr-ch is lt no pt-br sv \ @@ -273,29 +259,6 @@ else BLOBS= endif -install-doc: $(DOCS) - $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)" - $(INSTALL_DATA) docs/interop/qemu-qmp-ref.html "$(DESTDIR)$(qemu_docdir)/interop" - $(INSTALL_DATA) docs/interop/qemu-qmp-ref.txt "$(DESTDIR)$(qemu_docdir)/interop" -ifdef CONFIG_POSIX - $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man1" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/system/qemu.1 "$(DESTDIR)$(mandir)/man1" - $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man7" - $(INSTALL_DATA) docs/interop/qemu-qmp-ref.7 "$(DESTDIR)$(mandir)/man7" -ifeq ($(CONFIG_GUEST_AGENT),y) - $(INSTALL_DATA) docs/interop/qemu-ga-ref.html "$(DESTDIR)$(qemu_docdir)/interop" - $(INSTALL_DATA) docs/interop/qemu-ga-ref.txt "$(DESTDIR)$(qemu_docdir)/interop" - $(INSTALL_DATA) docs/interop/qemu-ga-ref.7 "$(DESTDIR)$(mandir)/man7" -endif -endif -ifdef CONFIG_VIRTFS - $(INSTALL_DIR) "$(DESTDIR)$(mandir)/man1" - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/virtfs-proxy-helper.1 "$(DESTDIR)$(mandir)/man1" -endif -ifeq ($(CONFIG_LINUX)$(CONFIG_SECCOMP)$(CONFIG_LIBCAP_NG),yyy) - $(INSTALL_DATA) $(MANUAL_BUILDDIR)/tools/virtiofsd.1 "$(DESTDIR)$(mandir)/man1" -endif - install-datadir: $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)" @@ -310,8 +273,7 @@ ICON_SIZES=16x16 24x24 32x32 48x48 64x64 128x128 256x256 512x512 # Needed by "meson install" export DESTDIR -install: all $(if $(BUILD_DOCS),install-doc) \ - install-datadir install-localstatedir +install: all install-datadir install-localstatedir ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_PROG) "scripts/qemu-trace-stap" $(DESTDIR)$(bindir) endif @@ -342,62 +304,6 @@ endif $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x "$(DESTDIR)$(qemu_datadir)/keymaps"; \ done -# documentation -MAKEINFO=makeinfo -MAKEINFOINCLUDES= -I docs -I $( $@,"GEN","$@") - -%.html: %.texi docs/version.texi - $(call quiet-command,LC_ALL=C $(MAKEINFO) $(MAKEINFOFLAGS) --no-headers \ - --html $< -o $@,"GEN","$@") - -%.info: %.texi docs/version.texi - $(call quiet-command,$(MAKEINFO) $(MAKEINFOFLAGS) $< -o $@,"GEN","$@") - -%.txt: %.texi docs/version.texi - $(call quiet-command,LC_ALL=C $(MAKEINFO) $(MAKEINFOFLAGS) --no-headers \ - --plaintext $< -o $@,"GEN","$@") - -%.pdf: %.texi docs/version.texi - $(call quiet-command,texi2pdf $(TEXI2PDFFLAGS) $< -o $@,"GEN","$@") - -docs/interop/qemu-qmp-qapi.texi: qapi/qapi-doc.texi - @cp -p $< $@ - -docs/interop/qemu-ga-qapi.texi: qga/qga-qapi-doc.texi - @cp -p $< $@ - -html: docs/interop/qemu-qmp-ref.html docs/interop/qemu-ga-ref.html sphinxdocs -info: docs/interop/qemu-qmp-ref.info docs/interop/qemu-ga-ref.info -pdf: docs/interop/qemu-qmp-ref.pdf docs/interop/qemu-ga-ref.pdf -txt: docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt - -docs/interop/qemu-ga-ref.dvi docs/interop/qemu-ga-ref.html \ - docs/interop/qemu-ga-ref.info docs/interop/qemu-ga-ref.pdf \ - docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7: \ - docs/interop/qemu-ga-ref.texi docs/interop/qemu-ga-qapi.texi - -docs/interop/qemu-qmp-ref.dvi docs/interop/qemu-qmp-ref.html \ - docs/interop/qemu-qmp-ref.info docs/interop/qemu-qmp-ref.pdf \ - docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7: \ - docs/interop/qemu-qmp-ref.texi docs/interop/qemu-qmp-qapi.texi - -$(filter %.1 %.7 %.8,$(DOCS)): scripts/texi2pod.pl - $(call quiet-command, \ - perl -Ww -- $(SRC_PATH)/scripts/texi2pod.pl $(TEXI2PODFLAGS) $< $@.pod && \ - $(POD2MAN) --section=$(subst .,,$(suffix $@)) --center=" " --release=" " $@.pod > $@, \ - "GEN","$@") - -man: $(filter %.1 %.7 %.8,$(DOCS)) - ifdef CONFIG_WIN32 INSTALLER = qemu-setup-$(VERSION)$(EXESUF) @@ -496,7 +402,7 @@ endif $(call print-help,vm-help,Help about targets running tests inside VM) @echo '' @echo 'Documentation targets:' - $(call print-help,html info pdf txt,Build documentation in specified format) + $(call print-help,html info pdf txt man,Build documentation in specified format) @echo '' ifdef CONFIG_WIN32 @echo 'Windows targets:' diff --git a/docs/interop/qemu-ga-ref.texi b/docs/interop/qemu-ga-ref.texi index ddb76ce1c2..a23cc2ed7f 100644 --- a/docs/interop/qemu-ga-ref.texi +++ b/docs/interop/qemu-ga-ref.texi @@ -65,7 +65,7 @@ along with this manual. If not, see http://www.gnu.org/licenses/. @c for texi2pod: @c man begin DESCRIPTION -@include qemu-ga-qapi.texi +@include qga/qga-qapi-doc.texi @c man end diff --git a/docs/interop/qemu-qmp-ref.texi b/docs/interop/qemu-qmp-ref.texi index bb25758bd0..ea1d7fe6c2 100644 --- a/docs/interop/qemu-qmp-ref.texi +++ b/docs/interop/qemu-qmp-ref.texi @@ -65,7 +65,7 @@ along with this manual. If not, see http://www.gnu.org/licenses/. @c for texi2pod: @c man begin DESCRIPTION -@include qemu-qmp-qapi.texi +@include qapi/qapi-doc.texi @c man end diff --git a/meson.build b/meson.build index e270569f4d..fd7b362fb7 100644 --- a/meson.build +++ b/meson.build @@ -1052,6 +1052,91 @@ subdir('pc-bios') subdir('tests') subdir('docs') +if build_docs + makeinfo = find_program('makeinfo', required: build_docs) + + docs_inc = [ + '-I', meson.current_source_dir(), + '-I', meson.current_build_dir() / 'docs', + '-I', '@OUTDIR@', + ] + + version_texi = configure_file(output: 'version.texi', + input: 'version.texi.in', + configuration: {'VERSION': meson.project_version(), + 'qemu_confdir': config_host['qemu_confdir']}) + + texi = { + 'qemu-qmp-ref': ['docs/interop/qemu-qmp-ref.texi', qapi_doc_texi, version_texi], + } + if 'CONFIG_GUEST_AGENT' in config_host + texi += {'qemu-ga-ref': ['docs/interop/qemu-ga-ref.texi', qga_qapi_doc_texi, version_texi]} + endif + + if makeinfo.found() + cmd = [ + 'env', 'LC_ALL=C', makeinfo, '--no-split', '--number-sections', docs_inc, + '@INPUT0@', '-o', '@OUTPUT@', + ] + foreach ext, args: { + 'info': [], + 'html': ['--no-headers', '--html'], + 'txt': ['--no-headers', '--plaintext'], + } + t = [] + foreach doc, input: texi + output = doc + '.' + ext + t += custom_target(output, + input: input, + output: output, + install: true, + install_dir: config_host['qemu_docdir'] / 'interop', + command: cmd + args) + endforeach + alias_target(ext, t) + endforeach + endif + + texi2pdf = find_program('texi2pdf', required: false) + + if texi2pdf.found() + pdfs = [] + foreach doc, input: texi + output = doc + '.pdf' + pdfs += custom_target(output, + input: input, + output: output, + command: [texi2pdf, '-q', docs_inc, '@INPUT0@', '-o', '@OUTPUT@'], + build_by_default: false) + endforeach + alias_target('pdf', pdfs) + endif + + texi2pod = find_program('scripts/texi2pod.pl') + pod2man = find_program('pod2man', required: build_docs) + + if pod2man.found() + foreach doc, input: texi + man = doc + '.7' + pod = custom_target(man + '.pod', + input: input, + output: man + '.pod', + command: [texi2pod, + '-DVERSION="' + meson.project_version() + '"', + '-DCONFDIR="' + config_host['qemu_confdir'] + '"', + '@INPUT0@', '@OUTPUT@']) + man = custom_target(man, + input: pod, + output: man, + capture: true, + install: true, + install_dir: config_host['mandir'] / 'man7', + command: [pod2man, '--utf8', '--section=7', '--center=" "', + '--release=" "', '@INPUT@']) + endforeach + endif +endif + summary_info = {} summary_info += {'Install prefix': config_host['prefix']} summary_info += {'BIOS directory': config_host['qemu_datadir']} diff --git a/qga/meson.build b/qga/meson.build index 2b91261427..3f28f74b52 100644 --- a/qga/meson.build +++ b/qga/meson.build @@ -1,7 +1,6 @@ qga_qapi_outputs = [ 'qga-qapi-commands.c', 'qga-qapi-commands.h', - 'qga-qapi-doc.texi', 'qga-qapi-emit-events.c', 'qga-qapi-emit-events.h', 'qga-qapi-events.c', @@ -17,12 +16,19 @@ qga_qapi_outputs = [ ] qga_qapi_files = custom_target('QGA QAPI files', - output: qga_qapi_outputs, + output: qga_qapi_outputs + ['qga-qapi-doc.texi'], input: 'qapi-schema.json', command: [ qapi_gen, '-o', 'qga', '-p', 'qga-', '@INPUT0@' ], depend_files: qapi_gen_depends) + qga_ss = ss.source_set() -qga_ss.add(qga_qapi_files) +i = 0 +foreach output: qga_qapi_outputs + qga_ss.add(qga_qapi_files[i]) + i = i + 1 +endforeach +qga_qapi_doc_texi = qga_qapi_files[i] + qga_ss.add(files( 'commands.c', 'guest-agent-command-state.c', diff --git a/version.texi.in b/version.texi.in new file mode 100644 index 0000000000..0a723b8be6 --- /dev/null +++ b/version.texi.in @@ -0,0 +1,2 @@ +@set VERSION @VERSION@ +@set CONFDIR @qemu_confdir@ -- cgit v1.2.3-55-g7522 From d3ca592b3c10ba3d340e28f68a9a155dacdf4446 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 28 Jan 2020 14:49:18 +0100 Subject: meson: convert check-block Signed-off-by: Paolo Bonzini --- meson.build | 2 ++ tests/Makefile.include | 18 ++---------------- tests/meson.build | 4 ++++ tests/qemu-iotests/meson.build | 10 ++++++++++ 4 files changed, 18 insertions(+), 16 deletions(-) create mode 100644 tests/qemu-iotests/meson.build diff --git a/meson.build b/meson.build index fd7b362fb7..02a8bd5a63 100644 --- a/meson.build +++ b/meson.build @@ -1001,9 +1001,11 @@ if have_tools dependencies: [authz, block, crypto, io, qom, qemuutil], install: true) qemu_io = executable('qemu-io', files('qemu-io.c'), dependencies: [block, qemuutil], install: true) + qemu_block_tools = [qemu_img, qemu_io] if targetos == 'linux' or targetos == 'sunos' or targetos.endswith('bsd') qemu_nbd = executable('qemu-nbd', files('qemu-nbd.c'), dependencies: [block, qemuutil], install: true) + qemu_block_tools += [qemu_nbd] endif subdir('storage-daemon') diff --git a/tests/Makefile.include b/tests/Makefile.include index 4a2435342a..1f07a36f32 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -160,8 +160,6 @@ check-unit-y += tests/test-uuid$(EXESUF) check-unit-y += tests/ptimer-test$(EXESUF) check-unit-y += tests/test-qapi-util$(EXESUF) -check-block-$(call land,$(CONFIG_POSIX),$(CONFIG_SOFTMMU)) += tests/check-block.sh - generated-files-y += tests/test-qapi-types.h generated-files-y += tests/include/test-qapi-types-sub-module.h generated-files-y += tests/test-qapi-types-sub-sub-module.h @@ -480,14 +478,6 @@ check-tcg: $(RUN_TCG_TARGET_RULES) clean-tcg: $(CLEAN_TCG_TARGET_RULES) -QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu-iotests/socket_scm_helper$(EXESUF) - -.PHONY: check-tests/check-block.sh -check-tests/check-block.sh: tests/check-block.sh qemu-img$(EXESUF) \ - qemu-io$(EXESUF) qemu-nbd$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) \ - $(patsubst %-softmmu,qemu-system-%,$(filter %-softmmu,$(TARGET_DIRS))) - @$< - # Python venv for running tests .PHONY: check-venv check-acceptance @@ -542,9 +532,7 @@ check-acceptance: check-venv $(TESTS_RESULTS_DIR) get-vm-images # Consolidated targets .PHONY: check-block check-unit check check-clean get-vm-images -ifeq ($(CONFIG_TOOLS),y) -check-block: $(patsubst %,check-%, $(check-block-y)) -endif +check-block: check-build: build-unit check-clean: @@ -552,14 +540,12 @@ check-clean: rm -f tests/test-qapi-gen-timestamp rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) -check: check-block check-unit +check: check-unit clean: check-clean # Build the help program automatically -all: $(QEMU_IOTESTS_HELPERS-y) - -include $(wildcard tests/*.d) endif diff --git a/tests/meson.build b/tests/meson.build index d724402cf4..f834c272e8 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -1,3 +1,7 @@ +if have_system and 'CONFIG_POSIX' in config_host + subdir('qemu-iotests') +endif + test('decodetree', sh, args: [ files('decode/check.sh'), config_host['PYTHON'], files('../scripts/decodetree.py') ], workdir: meson.current_source_dir() / 'decode', diff --git a/tests/qemu-iotests/meson.build b/tests/qemu-iotests/meson.build new file mode 100644 index 0000000000..3de09fb8fa --- /dev/null +++ b/tests/qemu-iotests/meson.build @@ -0,0 +1,10 @@ +if 'CONFIG_LINUX' in config_host + socket_scm_helper = executable('socket_scm_helper', 'socket_scm_helper.c', + build_by_default: false) +else + socket_scm_helper = [] +endif +test('qemu-iotests', sh, args: [files('../check-block.sh')], + depends: [qemu_block_tools, emulators, socket_scm_helper], + suite: 'block', timeout: 10000) + -- cgit v1.2.3-55-g7522 From 484e2cc730a86f7066b3e29c5bb8440747b61f01 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 12 Dec 2019 13:30:36 +0100 Subject: rules.mak: drop unneeded macros Signed-off-by: Paolo Bonzini --- .gitignore | 1 - Makefile | 7 +- configure | 55 +++-------- docs/devel/build-system.txt | 5 +- rules.mak | 231 +------------------------------------------- scripts/create_config | 6 +- 6 files changed, 23 insertions(+), 282 deletions(-) diff --git a/.gitignore b/.gitignore index d1e5e06242..4ccb9ed975 100644 --- a/.gitignore +++ b/.gitignore @@ -80,7 +80,6 @@ *.msi *.dll *.so -*.mo *.fn *.ky *.log diff --git a/Makefile b/Makefile index f442895309..f33ec16a81 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ endif include $(SRC_PATH)/tests/Makefile.include -all: recurse-all modules +all: recurse-all # LIBFDT_lib="": avoid breaking existing trees with objects requiring -fPIC DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" LIBFDT_lib="" @@ -197,7 +197,7 @@ clean: recurse-clean ninja-clean clean-ctlist -test -f ninjatool && ./ninjatool $(if $(V),-v,) -t clean # avoid old build problems by removing potentially incorrect old files rm -f config.mak op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h - find . \( -name '*.so' -o -name '*.dll' -o -name '*.mo' -o -name '*.[oda]' \) -type f \ + find . \( -name '*.so' -o -name '*.dll' -o -name '*.[oda]' \) -type f \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-aarch64.a \ ! -path ./roms/edk2/ArmPkg/Library/GccLto/liblto-arm.a \ ! -path ./roms/edk2/BaseTools/Source/Python/UPT/Dll/sqlite3.dll \ @@ -382,9 +382,6 @@ print-help = $(quiet-@)$(call print-help-run,$1,$2) help: @echo 'Generic targets:' $(call print-help,all,Build all) -ifdef CONFIG_MODULES - $(call print-help,modules,Build all modules) -endif $(call print-help,dir/file.o,Build specified target only) $(call print-help,install,Install QEMU, documentation and tools) $(call print-help,ctags/TAGS,Generate tags file for editors) diff --git a/configure b/configure index 77f2616e61..2186d10255 100755 --- a/configure +++ b/configure @@ -78,7 +78,6 @@ TMPC="${TMPDIR1}/${TMPB}.c" TMPO="${TMPDIR1}/${TMPB}.o" TMPCXX="${TMPDIR1}/${TMPB}.cxx" TMPE="${TMPDIR1}/${TMPB}.exe" -TMPMO="${TMPDIR1}/${TMPB}.mo" TMPTXT="${TMPDIR1}/${TMPB}.txt" rm -f config.log @@ -469,7 +468,7 @@ bigendian="no" mingw32="no" gcov="no" EXESUF="" -DSOSUF=".so" +HOST_DSOSUF=".so" LDFLAGS_SHARED="-shared" modules="no" module_upgrades="no" @@ -1001,7 +1000,7 @@ fi if test "$mingw32" = "yes" ; then EXESUF=".exe" - DSOSUF=".dll" + HOST_DSOSUF=".dll" # MinGW needs -mthreads for TLS and macro _MT. CFLAGS="-mthreads $CFLAGS" LIBS="-lwinmm -lws2_32 $LIBS" @@ -6255,31 +6254,6 @@ EOF fi fi -################################################# -# Sparc implicitly links with --relax, which is -# incompatible with -r, so --no-relax should be -# given. It does no harm to give it on other -# platforms too. - -# Note: the prototype is needed since QEMU_CFLAGS -# contains -Wmissing-prototypes -cat > $TMPC << EOF -extern int foo(void); -int foo(void) { return 0; } -EOF -if ! compile_object ""; then - error_exit "Failed to compile object file for LD_REL_FLAGS test" -fi -for i in '-Wl,-r -Wl,--no-relax' -Wl,-r -r; do - if do_cc -nostdlib $i -o $TMPMO $TMPO; then - LD_REL_FLAGS=$i - break - fi -done -if test "$modules" = "yes" && test "$LD_REL_FLAGS" = ""; then - feature_not_found "modules" "Cannot find how to build relocatable objects" -fi - ########################################## # check for sysmacros.h @@ -7011,12 +6985,7 @@ fi echo "CONFIG_AUDIO_DRIVERS=$audio_drv_list" >> $config_host_mak for drv in $audio_drv_list; do def=CONFIG_AUDIO_$(echo $drv | LC_ALL=C tr '[a-z]' '[A-Z]') - case "$drv" in - alsa | oss | pa | sdl) - echo "$def=m" >> $config_host_mak ;; - *) - echo "$def=y" >> $config_host_mak ;; - esac + echo "$def=y" >> $config_host_mak done if test "$alsa" = "yes" ; then echo "CONFIG_ALSA=y" >> $config_host_mak @@ -7105,7 +7074,7 @@ if test "$iconv" = "yes" ; then echo "ICONV_LIBS=$iconv_lib" >> $config_host_mak fi if test "$curses" = "yes" ; then - echo "CONFIG_CURSES=m" >> $config_host_mak + echo "CONFIG_CURSES=y" >> $config_host_mak echo "CURSES_CFLAGS=$curses_inc" >> $config_host_mak echo "CURSES_LIBS=$curses_lib" >> $config_host_mak fi @@ -7200,7 +7169,7 @@ if test "$bswap_h" = "yes" ; then echo "CONFIG_MACHINE_BSWAP_H=y" >> $config_host_mak fi if test "$curl" = "yes" ; then - echo "CONFIG_CURL=m" >> $config_host_mak + echo "CONFIG_CURL=y" >> $config_host_mak echo "CURL_CFLAGS=$curl_cflags" >> $config_host_mak echo "CURL_LIBS=$curl_libs" >> $config_host_mak fi @@ -7209,7 +7178,7 @@ if test "$brlapi" = "yes" ; then echo "BRLAPI_LIBS=$brlapi_libs" >> $config_host_mak fi if test "$gtk" = "yes" ; then - echo "CONFIG_GTK=m" >> $config_host_mak + echo "CONFIG_GTK=y" >> $config_host_mak echo "GTK_CFLAGS=$gtk_cflags" >> $config_host_mak echo "GTK_LIBS=$gtk_libs" >> $config_host_mak if test "$gtk_gl" = "yes" ; then @@ -7472,13 +7441,13 @@ if test "$zstd" = "yes" ; then fi if test "$libiscsi" = "yes" ; then - echo "CONFIG_LIBISCSI=m" >> $config_host_mak + echo "CONFIG_LIBISCSI=y" >> $config_host_mak echo "LIBISCSI_CFLAGS=$libiscsi_cflags" >> $config_host_mak echo "LIBISCSI_LIBS=$libiscsi_libs" >> $config_host_mak fi if test "$libnfs" = "yes" ; then - echo "CONFIG_LIBNFS=m" >> $config_host_mak + echo "CONFIG_LIBNFS=y" >> $config_host_mak echo "LIBNFS_LIBS=$libnfs_libs" >> $config_host_mak fi @@ -7500,7 +7469,7 @@ if test "$qom_cast_debug" = "yes" ; then echo "CONFIG_QOM_CAST_DEBUG=y" >> $config_host_mak fi if test "$rbd" = "yes" ; then - echo "CONFIG_RBD=m" >> $config_host_mak + echo "CONFIG_RBD=y" >> $config_host_mak echo "RBD_LIBS=$rbd_libs" >> $config_host_mak fi @@ -7572,7 +7541,7 @@ if test "$getauxval" = "yes" ; then fi if test "$glusterfs" = "yes" ; then - echo "CONFIG_GLUSTERFS=m" >> $config_host_mak + echo "CONFIG_GLUSTERFS=y" >> $config_host_mak echo "GLUSTERFS_CFLAGS=$glusterfs_cflags" >> $config_host_mak echo "GLUSTERFS_LIBS=$glusterfs_libs" >> $config_host_mak fi @@ -7602,7 +7571,7 @@ if test "$glusterfs_iocb_has_stat" = "yes" ; then fi if test "$libssh" = "yes" ; then - echo "CONFIG_LIBSSH=m" >> $config_host_mak + echo "CONFIG_LIBSSH=y" >> $config_host_mak echo "LIBSSH_CFLAGS=$libssh_cflags" >> $config_host_mak echo "LIBSSH_LIBS=$libssh_libs" >> $config_host_mak fi @@ -7862,7 +7831,7 @@ echo "LIBS+=$LIBS" >> $config_host_mak echo "LIBS_TOOLS+=$libs_tools" >> $config_host_mak echo "PTHREAD_LIB=$PTHREAD_LIB" >> $config_host_mak echo "EXESUF=$EXESUF" >> $config_host_mak -echo "DSOSUF=$DSOSUF" >> $config_host_mak +echo "HOST_DSOSUF=$HOST_DSOSUF" >> $config_host_mak echo "LDFLAGS_SHARED=$LDFLAGS_SHARED" >> $config_host_mak echo "LIBS_QGA=$libs_qga" >> $config_host_mak echo "TASN1_LIBS=$tasn1_libs" >> $config_host_mak diff --git a/docs/devel/build-system.txt b/docs/devel/build-system.txt index 41bd08ea3a..fea67b207c 100644 --- a/docs/devel/build-system.txt +++ b/docs/devel/build-system.txt @@ -404,10 +404,7 @@ using Makefile.target for the build rules. - rules.mak This file provides the generic helper rules for invoking build tools, in -particular the compiler and linker. This also contains the magic (hairy) -'unnest-vars' function which is used to merge the variable definitions -from all Makefile.objs in the source tree down into the main Makefile -context. +particular the compiler and linker. - default-configs/*.mak diff --git a/rules.mak b/rules.mak index 6cab0b9cbd..c66c8218f0 100644 --- a/rules.mak +++ b/rules.mak @@ -33,11 +33,6 @@ QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d # different for target-dependent ones. QEMU_LOCAL_INCLUDES = -iquote $(BUILD_DIR) -iquote $(BUILD_DIR)/$(@D) -iquote $(@D) -WL_U := -Wl,-u, -find-symbols = $(if $1, $(sort $(shell $(NM) -P -g $1 | $2))) -defined-symbols = $(call find-symbols,$1,awk '$$2!="U"{print $$1}') -undefined-symbols = $(call find-symbols,$1,awk '$$2=="U"{print $$1}') - WL := -Wl, ifdef CONFIG_DARWIN whole-archive = $(WL)-force_load,$1 @@ -45,32 +40,7 @@ else whole-archive = $(WL)--whole-archive $1 $(WL)--no-whole-archive endif -# All the .mo objects in -m variables are also added into corresponding -y -# variable in unnest-vars, but filtered out here, when LINK is called. -# -# The .mo objects are supposed to be linked as a DSO, for module build. So here -# they are only used as a placeholders to generate those "archive undefined" -# symbol options (-Wl,-u,$symbol_name), which are the archive functions -# referenced by the code in the DSO. -# -# Also the presence in -y variables will also guarantee they are built before -# linking executables that will load them. So we can look up symbol reference -# in LINK. -# -# This is necessary because the exectuable itself may not use the function, in -# which case the function would not be linked in. Then the DSO loading will -# fail because of the missing symbol. -process-archive-undefs = $(filter-out %.a %.fa %.mo %$(DSOSUF),$1) \ - $(addprefix $(WL_U), \ - $(filter $(call defined-symbols,$(filter %.a %.fa, $1)), \ - $(call undefined-symbols,$(filter %.mo %$(DSOSUF),$1)))) \ - $(foreach l,$(filter %.fa,$1),$(call whole-archive,$l)) \ - $(filter %.a,$1) - -extract-libs = $(strip $(foreach o,$(filter-out %.mo %$(DSOSUF),$1),$($o-libs))) -expand-objs = $(strip $(sort $(filter %.o,$1)) \ - $(foreach o,$(filter %.mo %$(DSOSUF),$1),$($o-objs)) \ - $(filter-out %.o %.mo %$(DSOSUF),$1)) +extract-libs = $(strip $(foreach o,$1,$($o-libs))) %.o: %.c @mkdir -p $(dir $@) @@ -83,7 +53,9 @@ expand-objs = $(strip $(sort $(filter %.o,$1)) \ LINKPROG = $(or $(CXX),$(CC)) LINK = $(call quiet-command, $(LINKPROG) $(CFLAGS) $(QEMU_LDFLAGS) -o $@ \ - $(call process-archive-undefs, $1) \ + $(filter-out %.a %.fa,$1) \ + $(foreach l,$(filter %.fa,$1),$(call whole-archive,$l)) \ + $(filter %.a,$1) \ $(call extract-libs,$1) $(LIBS),"LINK","$(TARGET_DIR)$@") %.o: %.S @@ -109,25 +81,11 @@ LINK = $(call quiet-command, $(LINKPROG) $(CFLAGS) $(QEMU_LDFLAGS) -o $@ \ %.o: %.dtrace $(call quiet-command,dtrace -o $@ -G -s $<,"GEN","$(TARGET_DIR)$@") -DSO_OBJ_CFLAGS := -fPIC -DBUILD_DSO -module-common.o: CFLAGS += $(DSO_OBJ_CFLAGS) -%$(DSOSUF): QEMU_LDFLAGS += $(LDFLAGS_SHARED) -%$(DSOSUF): %.mo - $(call LINK,$^) - @# Copy to build root so modules can be loaded when program started without install - $(if $(findstring /,$@),$(call quiet-command,cp $@ $(subst /,-,$@),"CP","$(subst /,-,$@)")) - - -LD_REL := $(CC) -nostdlib $(LD_REL_FLAGS) - -%.mo: - $(call quiet-command,$(LD_REL) -o $@ $^,"LD","$(TARGET_DIR)$@") - .PHONY: modules modules: %$(EXESUF): %.o - $(call LINK,$(filter %.o %.a %.mo %.fa, $^)) + $(call LINK,$(filter %.o %.a %.fa, $^)) %.a: $(call quiet-command,rm -f $@ && $(AR) rcs $@ $^,"AR","$(TARGET_DIR)$@") @@ -160,15 +118,6 @@ define install-prog $(if $(STRIP),$(STRIP) $(foreach T,$1,"$2/$(notdir $T)"),) endef -# find-in-path -# Usage: $(call find-in-path, prog) -# Looks in the PATH if the argument contains no slash, else only considers one -# specific directory. Returns an # empty string if the program doesn't exist -# there. -find-in-path = $(if $(findstring /, $1), \ - $(wildcard $1), \ - $(wildcard $(patsubst %, %/$1, $(subst :, ,$(PATH))))) - # Logical functions (for operating on y/n values like CONFIG_FOO vars) # Inputs to these must be either "y" (true) or "n" or "" (both false) # Output is always either "y" or "n". @@ -205,175 +154,5 @@ clean: clean-timestamp # will delete the target of a rule if commands exit with a nonzero exit status .DELETE_ON_ERROR: -# save-vars -# Usage: $(call save-vars, vars) -# Save each variable $v in $vars as save-vars-$v, save their object's -# variables, then clear $v. saved-vars-$v contains the variables that -# where saved for the objects, in order to speedup load-vars. -define save-vars - $(foreach v,$1, - $(eval save-vars-$v := $(value $v)) - $(eval saved-vars-$v := $(foreach o,$($v), \ - $(if $($o-cflags), $o-cflags $(eval save-vars-$o-cflags := $($o-cflags))$(eval $o-cflags := )) \ - $(if $($o-libs), $o-libs $(eval save-vars-$o-libs := $($o-libs))$(eval $o-libs := )) \ - $(if $($o-objs), $o-objs $(eval save-vars-$o-objs := $($o-objs))$(eval $o-objs := )))) - $(eval $v := )) -endef - -# load-vars -# Usage: $(call load-vars, vars, add_var) -# Load the saved value for each variable in @vars, and the per object -# variables. -# Append @add_var's current value to the loaded value. -define load-vars - $(eval $2-new-value := $(value $2)) - $(foreach v,$1, - $(eval $v := $(value save-vars-$v)) - $(foreach o,$(saved-vars-$v), - $(eval $o := $(save-vars-$o)) $(eval save-vars-$o := )) - $(eval save-vars-$v := ) - $(eval saved-vars-$v := )) - $(eval $2 := $(value $2) $($2-new-value)) -endef - -# fix-paths -# Usage: $(call fix-paths, obj_path, src_path, vars) -# Add prefix @obj_path to all objects in @vars, and add prefix @src_path to all -# directories in @vars. -define fix-paths - $(foreach v,$3, - $(foreach o,$($v), - $(if $($o-libs), - $(eval $1$o-libs := $($o-libs))) - $(if $($o-cflags), - $(eval $1$o-cflags := $($o-cflags))) - $(if $($o-objs), - $(eval $1$o-objs := $(addprefix $1,$($o-objs))))) - $(eval $v := $(addprefix $1,$(filter-out %/,$($v))) \ - $(addprefix $2,$(filter %/,$($v))))) -endef - -# unnest-var-recursive -# Usage: $(call unnest-var-recursive, obj_prefix, vars, var) -# -# Unnest @var by including subdir Makefile.objs, while protect others in @vars -# unchanged. -# -# @obj_prefix is the starting point of object path prefix. -# -define unnest-var-recursive - $(eval dirs := $(sort $(filter %/,$($3)))) - $(eval $3 := $(filter-out %/,$($3))) - $(foreach d,$(dirs:%/=%), - $(call save-vars,$2) - $(eval obj := $(if $1,$1/)$d) - $(eval -include $(SRC_PATH)/$d/Makefile.objs) - $(call fix-paths,$(if $1,$1/)$d/,$d/,$2) - $(call load-vars,$2,$3) - $(call unnest-var-recursive,$1,$2,$3)) -endef - -# unnest-vars -# Usage: $(call unnest-vars, obj_prefix, vars) -# -# @obj_prefix: object path prefix, can be empty, or '..', etc. Don't include -# ending '/'. -# -# @vars: the list of variable names to unnest. -# -# This macro will scan subdirectories's Makefile.objs, include them, to build -# up each variable listed in @vars. -# -# Per object and per module cflags and libs are saved with relative path fixed -# as well, those variables include -libs, -cflags and -objs. Items in -objs are -# also fixed to relative path against SRC_PATH plus the prefix @obj_prefix. -# -# All nested variables postfixed by -m in names are treated as DSO variables, -# and will be built as modules, if enabled. -# -# A simple example of the unnest: -# -# obj_prefix = .. -# vars = hot cold -# hot = fire.o sun.o season/ -# cold = snow.o water/ season/ -# -# Unnest through a faked source directory structure: -# -# SRC_PATH -# ├── water -# │ └── Makefile.objs──────────────────┐ -# │ │ hot += steam.o │ -# │ │ cold += ice.mo │ -# │ │ ice.mo-libs := -licemaker │ -# │ │ ice.mo-objs := ice1.o ice2.o │ -# │ └──────────────────────────────┘ -# │ -# └── season -# └── Makefile.objs──────┐ -# │ hot += summer.o │ -# │ cold += winter.o │ -# └──────────────────┘ -# -# In the end, the result will be: -# -# hot = ../fire.o ../sun.o ../season/summer.o -# cold = ../snow.o ../water/ice.mo ../season/winter.o -# ../water/ice.mo-libs = -licemaker -# ../water/ice.mo-objs = ../water/ice1.o ../water/ice2.o -# -# Note that 'hot' didn't include 'water/' in the input, so 'steam.o' is not -# included. -# -define unnest-vars - # In the case of target build (i.e. $1 == ..), fix path for top level - # Makefile.objs objects - $(if $1,$(call fix-paths,$1/,,$2)) - - # Descend and include every subdir Makefile.objs - $(foreach v, $2, - $(call unnest-var-recursive,$1,$2,$v) - # Pass the .mo-cflags and .mo-libs along to its member objects - $(foreach o, $(filter %.mo,$($v)), - $(foreach p,$($o-objs), - $(if $($o-cflags), $(eval $p-cflags += $($o-cflags))) - $(if $($o-libs), $(eval $p-libs += $($o-libs)))))) - - # For all %.mo objects that are directly added into -y, just expand them - $(foreach v,$(filter %-y,$2), - $(eval $v := $(foreach o,$($v),$(if $($o-objs),$($o-objs),$o)))) - - $(foreach v,$(filter %-m,$2), - # All .o found in *-m variables are single object modules, create .mo - # for them - $(foreach o,$(filter %.o,$($v)), - $(eval $(o:%.o=%.mo)-objs := $o)) - # Now unify .o in -m variable to .mo - $(eval $v := $($v:%.o=%.mo)) - $(eval modules-m += $($v)) - - # For module build, build shared libraries during "make modules" - # For non-module build, add -m to -y - $(if $(CONFIG_MODULES), - $(foreach o,$($v), - $(eval $($o-objs): CFLAGS += $(DSO_OBJ_CFLAGS)) - $(eval $o: $($o-objs))) - $(eval $(patsubst %-m,%-y,$v) += $($v)) - $(eval modules: $($v:%.mo=%$(DSOSUF))), - $(eval $(patsubst %-m,%-y,$v) += $(call expand-objs, $($v))))) - - # Post-process all the unnested vars - $(foreach v,$2, - $(foreach o, $(filter %.mo,$($v)), - # Find all the .mo objects in variables and add dependency rules - # according to .mo-objs. Report error if not set - $(if $($o-objs), - $(eval $(o:%.mo=%$(DSOSUF)): module-common.o $($o-objs)))) - $(shell mkdir -p ./ $(sort $(dir $($v)))) - # Include all the .d files - $(eval -include $(patsubst %.o,%.d,$(patsubst %.mo,%.d,$(filter %.o,$($v))))) - $(eval $v := $(filter-out %/,$($v)))) -endef - print-%: @echo '$*=$($*)' diff --git a/scripts/create_config b/scripts/create_config index bc82661041..ec5c0b4124 100755 --- a/scripts/create_config +++ b/scripts/create_config @@ -91,6 +91,9 @@ case $line in name=${line%=*} echo "#define $name 1" ;; + HOST_DSOSUF=*) + echo "#define HOST_DSOSUF \"${line#*=}\"" + ;; HOST_*=*) # configuration name=${line%=*} value=${line#*=} @@ -123,9 +126,6 @@ case $line in value=${line#*=} echo "#define $name $value" ;; - DSOSUF=*) - echo "#define HOST_DSOSUF \"${line#*=}\"" - ;; esac done # read -- cgit v1.2.3-55-g7522 From 859aef026e51a4959d1ab535f0b7a00d63ed32ba Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Aug 2020 18:14:26 +0200 Subject: meson: replace create-config with meson configure_file Move the create-config logic to meson.build; create a configuration_data object and let meson handle the quoting and output. Signed-off-by: Paolo Bonzini --- Makefile | 3 +- block.c | 2 + configure | 11 ++-- meson.build | 96 +++++++++++++++++++++--------- scripts/create_config | 131 ----------------------------------------- tests/qtest/bios-tables-test.c | 2 +- util/module.c | 4 +- 7 files changed, 81 insertions(+), 168 deletions(-) delete mode 100755 scripts/create_config diff --git a/Makefile b/Makefile index f33ec16a81..aa582d6554 100644 --- a/Makefile +++ b/Makefile @@ -143,6 +143,7 @@ endif include $(SRC_PATH)/tests/Makefile.include all: recurse-all +Makefile: $(addsuffix /all, $(SUBDIRS)) # LIBFDT_lib="": avoid breaking existing trees with objects requiring -fPIC DTC_MAKE_ARGS=-I$(SRC_PATH)/dtc VPATH=$(SRC_PATH)/dtc -C dtc V="$(V)" LIBFDT_lib="" @@ -206,7 +207,7 @@ clean: recurse-clean ninja-clean clean-ctlist rm -f fsdev/*.pod scsi/*.pod rm -f $(foreach f,$(generated-files-y),$(f) $(f)-timestamp) -VERSION ?= $(shell cat VERSION) +VERSION = $(shell cat $(SRC_PATH)/VERSION) dist: qemu-$(VERSION).tar.bz2 diff --git a/block.c b/block.c index 67c5028dd8..2ba76b2c36 100644 --- a/block.c +++ b/block.c @@ -433,9 +433,11 @@ static int bdrv_format_is_whitelisted(const char *format_name, bool read_only) { static const char *whitelist_rw[] = { CONFIG_BDRV_RW_WHITELIST + NULL }; static const char *whitelist_ro[] = { CONFIG_BDRV_RO_WHITELIST + NULL }; const char **p; diff --git a/configure b/configure index 2186d10255..b1889bd001 100755 --- a/configure +++ b/configure @@ -6962,8 +6962,9 @@ if test "$slirp" != "no"; then echo "SLIRP_CFLAGS=$slirp_cflags" >> $config_host_mak echo "SLIRP_LIBS=$slirp_libs" >> $config_host_mak fi +subdirs= if [ "$slirp" = "git" -o "$slirp" = "internal" ]; then - echo "config-host.h: slirp/all" >> $config_host_mak + subdirs="$subdirs slirp" fi if test "$vde" = "yes" ; then echo "CONFIG_VDE=y" >> $config_host_mak @@ -7036,7 +7037,6 @@ if test "$xfs" = "yes" ; then echo "CONFIG_XFS=y" >> $config_host_mak fi qemu_version=$(head $source_path/VERSION) -echo "VERSION=$qemu_version" >>$config_host_mak echo "PKGVERSION=$pkgversion" >>$config_host_mak echo "SRC_PATH=$source_path" >> $config_host_mak echo "TARGET_DIRS=$target_list" >> $config_host_mak @@ -7797,7 +7797,7 @@ echo "GENISOIMAGE=$genisoimage" >> $config_host_mak echo "MESON=$meson" >> $config_host_mak echo "CC=$cc" >> $config_host_mak if $iasl -h > /dev/null 2>&1; then - echo "IASL=$iasl" >> $config_host_mak + echo "CONFIG_IASL=$iasl" >> $config_host_mak fi echo "CXX=$cxx" >> $config_host_mak echo "OBJCC=$objcc" >> $config_host_mak @@ -8287,11 +8287,12 @@ echo "PIXMAN_CFLAGS=$pixman_cflags" >> $config_host_mak echo "PIXMAN_LIBS=$pixman_libs" >> $config_host_mak if [ "$fdt" = "git" ]; then - echo "config-host.h: dtc/all" >> $config_host_mak + subdirs="$subdirs dtc" fi if [ "$capstone" = "git" -o "$capstone" = "internal" ]; then - echo "config-host.h: capstone/all" >> $config_host_mak + subdirs="$subdirs capstone" fi +echo "SUBDIRS=$subdirs" >> $config_host_mak if test -n "$LIBCAPSTONE"; then echo "LIBCAPSTONE=$LIBCAPSTONE" >> $config_host_mak fi diff --git a/meson.build b/meson.build index 02a8bd5a63..0b03726ad3 100644 --- a/meson.build +++ b/meson.build @@ -12,6 +12,8 @@ config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') config_all_disas = keyval.load(meson.current_build_dir() / 'config-all-disas.mak') enable_modules = 'CONFIG_MODULES' in config_host build_docs = 'BUILD_DOCS' in config_host +config_host_data = configuration_data() +genh = [] add_project_arguments(config_host['QEMU_CFLAGS'].split(), native: false, language: ['c', 'objc']) @@ -359,13 +361,43 @@ if 'CONFIG_LIBPMEM' in config_host link_args: config_host['LIBPMEM_LIBS'].split()) endif -create_config = find_program('scripts/create_config') +# Create config-host.h + +config_host_data.set('QEMU_VERSION', '"@0@"'.format(meson.project_version())) +config_host_data.set('QEMU_VERSION_MAJOR', meson.project_version().split('.')[0]) +config_host_data.set('QEMU_VERSION_MINOR', meson.project_version().split('.')[1]) +config_host_data.set('QEMU_VERSION_MICRO', meson.project_version().split('.')[2]) + +arrays = ['CONFIG_AUDIO_DRIVERS', 'CONFIG_BDRV_RW_WHITELIST', 'CONFIG_BDRV_RO_WHITELIST'] +strings = ['HOST_DSOSUF', 'CONFIG_IASL', 'qemu_confdir', 'qemu_datadir', + 'qemu_moddir', 'qemu_localstatedir', 'qemu_helperdir', 'qemu_localedir', + 'qemu_icondir', 'qemu_desktopdir', 'qemu_firmwarepath'] +foreach k, v: config_host + if arrays.contains(k) + if v != '' + v = '"' + '", "'.join(v.split()) + '", ' + endif + config_host_data.set(k, v) + elif k == 'ARCH' + config_host_data.set('HOST_' + v.to_upper(), 1) + elif strings.contains(k) + if not k.startswith('CONFIG_') + k = 'CONFIG_' + k.to_upper() + endif + config_host_data.set_quoted(k, v) + elif k.startswith('CONFIG_') or k.startswith('HAVE_') or k.startswith('HOST_') + config_host_data.set(k, v == 'y' ? 1 : v) + endif +endforeach +genh += configure_file(output: 'config-host.h', configuration: config_host_data) + minikconf = find_program('scripts/minikconf.py') target_dirs = config_host['TARGET_DIRS'].split() have_user = false have_system = false config_devices_mak_list = [] config_devices_h = {} +config_target_h = {} config_target_mak = {} kconfig_external_symbols = [ 'CONFIG_KVM', @@ -381,16 +413,36 @@ kconfig_external_symbols = [ 'CONFIG_LINUX', 'CONFIG_PVRDMA', ] +ignored = ['TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_DIRS'] foreach target : target_dirs have_user = have_user or target.endswith('-user') - config_target = keyval.load(meson.current_build_dir() / target / 'config-target.mak') + config_host + config_target = keyval.load(meson.current_build_dir() / target / 'config-target.mak') + + config_target_data = configuration_data() + foreach k, v: config_target + if not k.startswith('TARGET_') and not k.startswith('CONFIG_') + # do nothing + elif ignored.contains(k) + # do nothing + elif k == 'TARGET_BASE_ARCH' + config_target_data.set('TARGET_' + v.to_upper(), 1) + elif k == 'TARGET_NAME' + config_target_data.set_quoted(k, v) + elif v == 'y' + config_target_data.set(k, 1) + else + config_target_data.set(k, v) + endif + endforeach + config_target_h += {target: configure_file(output: target + '-config-target.h', + configuration: config_target_data)} if target.endswith('-softmmu') have_system = true base_kconfig = [] foreach sym : kconfig_external_symbols - if sym in config_target + if sym in config_target or sym in config_host base_kconfig += '@0@=y'.format(sym) endif endforeach @@ -404,14 +456,16 @@ foreach target : target_dirs command: [minikconf, config_host['CONFIG_MINIKCONF_MODE'], config_devices_mak, '@DEPFILE@', '@INPUT@', base_kconfig]) - config_devices_h += {target: custom_target( - target + '-config-devices.h', - input: config_devices_mak, - output: target + '-config-devices.h', - capture: true, - command: [create_config, '@INPUT@'])} + + config_devices_data = configuration_data() + config_devices = keyval.load(config_devices_mak) + foreach k, v: config_devices + config_devices_data.set(k, 1) + endforeach config_devices_mak_list += config_devices_mak - config_target += keyval.load(config_devices_mak) + config_devices_h += {target: configure_file(output: target + '-config-devices.h', + configuration: config_devices_data)} + config_target += config_devices endif config_target_mak += {target: config_target} endforeach @@ -451,7 +505,6 @@ config_all += { # Generators -genh = [] hxtool = find_program('scripts/hxtool') shaderinclude = find_program('scripts/shaderinclude.pl') qapi_gen = find_program('scripts/qapi-gen.py') @@ -481,7 +534,7 @@ tracetool = [ qemu_version_cmd = [find_program('scripts/qemu-version.sh'), meson.current_source_dir(), - config_host['PKGVERSION'], config_host['VERSION']] + config_host['PKGVERSION'], meson.project_version()] qemu_version = custom_target('qemu-version.h', output: 'qemu-version.h', command: qemu_version_cmd, @@ -490,13 +543,6 @@ qemu_version = custom_target('qemu-version.h', build_always_stale: true) genh += qemu_version -config_host_h = custom_target('config-host.h', - input: meson.current_build_dir() / 'config-host.mak', - output: 'config-host.h', - capture: true, - command: [create_config, '@INPUT@']) -genh += config_host_h - hxdep = [] hx_headers = [ ['qemu-options.hx', 'qemu-options.def'], @@ -830,13 +876,14 @@ foreach target : target_dirs config_target = config_target_mak[target] target_name = config_target['TARGET_NAME'] arch = config_target['TARGET_BASE_ARCH'] - arch_srcs = [] + arch_srcs = [config_target_h[target]] arch_deps = [] c_args = ['-DNEED_CPU_H', '-DCONFIG_TARGET="@0@-config-target.h"'.format(target), '-DCONFIG_DEVICES="@0@-config-devices.h"'.format(target)] link_args = [] + config_target += config_host target_inc = [include_directories('target' / config_target['TARGET_BASE_ARCH'])] if targetos == 'linux' target_inc += include_directories('linux-headers', is_system: true) @@ -897,19 +944,12 @@ foreach target : target_dirs objects = common_all.extract_objects(target_common.sources()) deps = target_common.dependencies() - # TODO: Change to generator once obj-y goes away - config_target_h = custom_target(target + '-config-target.h', - input: meson.current_build_dir() / target / 'config-target.mak', - output: target + '-config-target.h', - capture: true, - command: [create_config, '@INPUT@']) - target_specific = specific_ss.apply(config_target, strict: false) arch_srcs += target_specific.sources() arch_deps += target_specific.dependencies() lib = static_library('qemu-' + target, - sources: arch_srcs + [config_target_h] + genh, + sources: arch_srcs + genh, objects: objects, include_directories: target_inc, c_args: c_args, diff --git a/scripts/create_config b/scripts/create_config deleted file mode 100755 index ec5c0b4124..0000000000 --- a/scripts/create_config +++ /dev/null @@ -1,131 +0,0 @@ -#!/bin/sh - -test $# -gt 0 && exec < $1 - -echo "/* Automatically generated by create_config - do not modify */" - -while read line; do - -case $line in - VERSION=*) # configuration - version=${line#*=} - major=$(echo "$version" | cut -d. -f1) - minor=$(echo "$version" | cut -d. -f2) - micro=$(echo "$version" | cut -d. -f3) - echo "#define QEMU_VERSION \"$version\"" - echo "#define QEMU_VERSION_MAJOR $major" - echo "#define QEMU_VERSION_MINOR $minor" - echo "#define QEMU_VERSION_MICRO $micro" - ;; - qemu_*dir=* | qemu_*path=*) # qemu-specific directory configuration - name=${line%=*} - value=${line#*=} - define_name=$(echo $name | LC_ALL=C tr '[a-z]' '[A-Z]') - eval "define_value=\"$value\"" - echo "#define CONFIG_$define_name \"$define_value\"" - # save for the next definitions - eval "$name=\$define_value" - ;; - prefix=*) - # save for the next definitions - prefix=${line#*=} - ;; - IASL=*) # iasl executable - value=${line#*=} - echo "#define CONFIG_IASL $value" - ;; - CONFIG_AUDIO_DRIVERS=*) - drivers=${line#*=} - echo "#define CONFIG_AUDIO_DRIVERS \\" - for drv in $drivers; do - echo " \"${drv}\",\\" - done - echo "" - ;; - CONFIG_BDRV_RW_WHITELIST=*) - echo "#define CONFIG_BDRV_RW_WHITELIST\\" - for drv in ${line#*=}; do - echo " \"${drv}\",\\" - done - echo " NULL" - ;; - CONFIG_BDRV_RO_WHITELIST=*) - echo "#define CONFIG_BDRV_RO_WHITELIST\\" - for drv in ${line#*=}; do - echo " \"${drv}\",\\" - done - echo " NULL" - ;; - CONFIG_*=y) # configuration - name=${line%=*} - echo "#define $name 1" - ;; - CONFIG_*=n) # configuration - ;; - CONFIG_*=*) # configuration - name=${line%=*} - value=${line#*=} - echo "#define $name $value" - ;; - HAVE_*=y) # configuration - name=${line%=*} - echo "#define $name 1" - ;; - HAVE_*=*) # configuration - name=${line%=*} - value=${line#*=} - echo "#define $name $value" - ;; - ARCH=*) # configuration - arch=${line#*=} - arch_name=$(echo $arch | LC_ALL=C tr '[a-z]' '[A-Z]') - echo "#define HOST_$arch_name 1" - ;; - HOST_USB=*) - # do nothing - ;; - HOST_CC=*) - # do nothing - ;; - HOST_*=y) # configuration - name=${line%=*} - echo "#define $name 1" - ;; - HOST_DSOSUF=*) - echo "#define HOST_DSOSUF \"${line#*=}\"" - ;; - HOST_*=*) # configuration - name=${line%=*} - value=${line#*=} - echo "#define $name $value" - ;; - TARGET_BASE_ARCH=*) # configuration - target_base_arch=${line#*=} - base_arch_name=$(echo $target_base_arch | LC_ALL=C tr '[a-z]' '[A-Z]') - echo "#define TARGET_$base_arch_name 1" - ;; - TARGET_XML_FILES=*) - # do nothing - ;; - TARGET_ABI_DIR=*) - # do nothing - ;; - TARGET_NAME=*) - target_name=${line#*=} - echo "#define TARGET_NAME \"$target_name\"" - ;; - TARGET_DIRS=*) - # do nothing - ;; - TARGET_*=y) # configuration - name=${line%=*} - echo "#define $name 1" - ;; - TARGET_*=*) # configuration - name=${line%=*} - value=${line#*=} - echo "#define $name $value" - ;; -esac - -done # read diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index d49b3988ec..d25ff35492 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -88,7 +88,7 @@ typedef struct { static char disk[] = "tests/acpi-test-disk-XXXXXX"; static const char *data_dir = "tests/data/acpi"; #ifdef CONFIG_IASL -static const char *iasl = stringify(CONFIG_IASL); +static const char *iasl = CONFIG_IASL; #else static const char *iasl; #endif diff --git a/util/module.c b/util/module.c index c956ef096b..6e63006a8f 100644 --- a/util/module.c +++ b/util/module.c @@ -113,7 +113,7 @@ static int module_load_file(const char *fname) { GModule *g_module; void (*sym)(void); - const char *dsosuf = HOST_DSOSUF; + const char *dsosuf = CONFIG_HOST_DSOSUF; int len = strlen(fname); int suf_len = strlen(dsosuf); ModuleEntry *e, *next; @@ -221,7 +221,7 @@ bool module_load_one(const char *prefix, const char *lib_name) for (i = 0; i < n_dirs; i++) { fname = g_strdup_printf("%s/%s%s", - dirs[i], module_name, HOST_DSOSUF); + dirs[i], module_name, CONFIG_HOST_DSOSUF); ret = module_load_file(fname); g_free(fname); fname = NULL; -- cgit v1.2.3-55-g7522 From ffac93df19d33387645376c32a4a789d204e6fcd Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Feb 2020 16:09:05 +0100 Subject: meson: convert sample plugins Signed-off-by: Paolo Bonzini --- configure | 4 ---- tests/Makefile.include | 9 --------- tests/meson.build | 3 +++ tests/plugin/Makefile | 46 ---------------------------------------------- tests/plugin/meson.build | 7 +++++++ 5 files changed, 10 insertions(+), 59 deletions(-) delete mode 100644 tests/plugin/Makefile create mode 100644 tests/plugin/meson.build diff --git a/configure b/configure index b1889bd001..f47eedba81 100755 --- a/configure +++ b/configure @@ -6881,9 +6881,6 @@ echo "GIT_UPDATE=$git_update" >> $config_host_mak echo "ARCH=$ARCH" >> $config_host_mak -echo "GLIB_CFLAGS=$glib_cflags" >> $config_host_mak -echo "GLIB_LDFLAGS=$glib_ldflags" >> $config_host_mak - if test "$default_devices" = "yes" ; then echo "CONFIG_MINIKCONF_MODE=--defconfig" >> $config_host_mak else @@ -8328,7 +8325,6 @@ DIRS="$DIRS roms/seabios" LINKS="Makefile" LINKS="$LINKS tests/tcg/lm32/Makefile po/Makefile" LINKS="$LINKS tests/tcg/Makefile.target" -LINKS="$LINKS tests/plugin/Makefile" LINKS="$LINKS pc-bios/optionrom/Makefile pc-bios/keymaps" LINKS="$LINKS pc-bios/s390-ccw/Makefile" LINKS="$LINKS roms/seabios/Makefile" diff --git a/tests/Makefile.include b/tests/Makefile.include index 1f07a36f32..9ac8f5b86a 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -429,15 +429,6 @@ check-speed: $(check-speed-y) check-report-unit.tap: $(check-unit-y) $(call do_test_tap,$^) -# Plugins -ifeq ($(CONFIG_PLUGIN),y) -.PHONY: plugins -plugins: - $(call quiet-command,\ - $(MAKE) $(SUBDIR_MAKEFLAGS) -C tests/plugin V="$(V)", \ - "BUILD", "plugins") -endif - # Per guest TCG tests BUILD_TCG_TARGET_RULES=$(patsubst %,build-tcg-tests-%, $(TARGET_DIRS)) diff --git a/tests/meson.build b/tests/meson.build index f834c272e8..fe2c6d8e6b 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -9,6 +9,9 @@ test('decodetree', sh, if 'CONFIG_TCG' in config_host subdir('fp') + if 'CONFIG_PLUGIN' in config_host + subdir('plugin') + endif endif subdir('qapi-schema') diff --git a/tests/plugin/Makefile b/tests/plugin/Makefile deleted file mode 100644 index e9348fde4a..0000000000 --- a/tests/plugin/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -*- Mode: makefile -*- -# -# This Makefile example is fairly independent from the main makefile -# so users can take and adapt it for their build. We only really -# include config-host.mak so we don't have to repeat probing for -# cflags that the main configure has already done for us. -# - -BUILD_DIR := $(CURDIR)/../.. - -include $(BUILD_DIR)/config-host.mak - -VPATH += $(SRC_PATH)/tests/plugin - -NAMES := -NAMES += bb -NAMES += empty -NAMES += insn -NAMES += mem -NAMES += hotblocks -NAMES += howvec -NAMES += hotpages -NAMES += lockstep - -SONAMES := $(addsuffix .so,$(addprefix lib,$(NAMES))) - -# The main QEMU uses Glib extensively so it's perfectly fine to use it -# in plugins (which many example do). -CFLAGS = $(GLIB_CFLAGS) -CFLAGS += -fPIC -CFLAGS += $(if $(findstring no-psabi,$(QEMU_CFLAGS)),-Wpsabi) -CFLAGS += -I$(SRC_PATH)/include/qemu - -all: $(SONAMES) - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -lib%.so: %.o - $(CC) -shared -Wl,-soname,$@ -o $@ $^ $(LDLIBS) - -clean: - rm -f *.o *.so *.d - rm -Rf .libs - -.PHONY: all clean diff --git a/tests/plugin/meson.build b/tests/plugin/meson.build new file mode 100644 index 0000000000..dbbdcbaa67 --- /dev/null +++ b/tests/plugin/meson.build @@ -0,0 +1,7 @@ +t = [] +foreach i : ['bb', 'empty', 'insn', 'mem', 'hotblocks', 'howvec', 'hotpages', 'lockstep'] + t += shared_module(i, files(i + '.c'), + include_directories: '../../include/qemu', + dependencies: glib) +endforeach +alias_target('plugins', t) -- cgit v1.2.3-55-g7522 From 35be72ba729d0fcd85c929597edb692c1d0f3bdc Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Feb 2020 14:17:15 +0100 Subject: meson: move SDL and SDL-image detection to meson Signed-off-by: Paolo Bonzini --- chardev/meson.build | 2 +- configure | 142 +++------------------------------------------------- meson.build | 32 ++++++++---- meson_options.txt | 2 + softmmu/main.c | 1 + ui/meson.build | 4 +- 6 files changed, 37 insertions(+), 146 deletions(-) create mode 100644 meson_options.txt diff --git a/chardev/meson.build b/chardev/meson.build index 02f914d6c0..a46a6237be 100644 --- a/chardev/meson.build +++ b/chardev/meson.build @@ -36,7 +36,7 @@ softmmu_ss.add(when: ['CONFIG_SPICE', spice], if_true: files('spice.c')) chardev_modules = {} -if config_host.has_key('CONFIG_BRLAPI') and config_host.has_key('CONFIG_SDL') +if config_host.has_key('CONFIG_BRLAPI') and sdl.found() module_ss = ss.source_set() module_ss.add(when: [sdl, brlapi], if_true: files('baum.c')) chardev_modules += { 'brlapi': module_ss } diff --git a/configure b/configure index f47eedba81..5b7b932e8d 100755 --- a/configure +++ b/configure @@ -422,8 +422,8 @@ curses="" docs="" fdt="" netmap="no" -sdl="" -sdl_image="" +sdl="auto" +sdl_image="auto" virtfs="" mpath="" vnc="yes" @@ -1137,13 +1137,13 @@ for opt do # configure to be used by RPM and similar macros that set # lots of directory switches by default. ;; - --disable-sdl) sdl="no" + --disable-sdl) sdl="disabled" ;; - --enable-sdl) sdl="yes" + --enable-sdl) sdl="enabled" ;; - --disable-sdl-image) sdl_image="no" + --disable-sdl-image) sdl_image="disabled" ;; - --enable-sdl-image) sdl_image="yes" + --enable-sdl-image) sdl_image="enabled" ;; --disable-qom-cast-debug) qom_cast_debug="no" ;; @@ -2435,7 +2435,7 @@ if test "$cocoa" = "yes"; then error_exit "Cocoa and GTK UIs cannot both be enabled at once" fi gtk=no - sdl=no + sdl=disabled fi # Some versions of Mac OS X incorrectly define SIZE_MAX @@ -3334,125 +3334,6 @@ if test "$vte" != "no"; then fi fi -########################################## -# SDL probe - -# Look for sdl configuration program (pkg-config or sdl2-config). Try -# sdl2-config even without cross prefix, and favour pkg-config over sdl2-config. - -sdl_probe () -{ - if $pkg_config sdl2 --exists; then - sdlconfig="$pkg_config sdl2" - sdlversion=$($sdlconfig --modversion 2>/dev/null) - elif has "$sdl2_config"; then - sdlconfig="$sdl2_config" - sdlversion=$($sdlconfig --version) - else - if test "$sdl" = "yes" ; then - feature_not_found "sdl" "Install SDL2-devel" - fi - sdl=no - # no need to do the rest - return - fi - if test -n "$cross_prefix" && test "$(basename "$sdlconfig")" = sdl2-config; then - echo warning: using "\"$sdlconfig\"" to detect cross-compiled sdl >&2 - fi - - cat > $TMPC << EOF -#include -#undef main /* We don't want SDL to override our main() */ -int main( void ) { return SDL_Init (SDL_INIT_VIDEO); } -EOF - sdl_cflags=$($sdlconfig --cflags 2>/dev/null) - sdl_cflags="$sdl_cflags -Wno-undef" # workaround 2.0.8 bug - if test "$static" = "yes" ; then - if $pkg_config sdl2 --exists; then - sdl_libs=$($pkg_config sdl2 --static --libs 2>/dev/null) - else - sdl_libs=$($sdlconfig --static-libs 2>/dev/null) - fi - else - sdl_libs=$($sdlconfig --libs 2>/dev/null) - fi - if compile_prog "$sdl_cflags" "$sdl_libs" ; then - sdl=yes - - # static link with sdl ? (note: sdl.pc's --static --libs is broken) - if test "$sdl" = "yes" && test "$static" = "yes" ; then - if test $? = 0 && echo $sdl_libs | grep -- -laa > /dev/null; then - sdl_libs="$sdl_libs $(aalib-config --static-libs 2>/dev/null)" - sdl_cflags="$sdl_cflags $(aalib-config --cflags 2>/dev/null)" - fi - if compile_prog "$sdl_cflags" "$sdl_libs" ; then - : - else - sdl=no - fi - fi # static link - else # sdl not found - if test "$sdl" = "yes" ; then - feature_not_found "sdl" "Install SDL2 devel" - fi - sdl=no - fi # sdl compile test -} - -sdl_image_probe () -{ - if test "$sdl_image" != "no" ; then - if $pkg_config SDL2_image --exists; then - if test "$static" = "yes"; then - sdl_image_libs=$($pkg_config SDL2_image --libs --static 2>/dev/null) - else - sdl_image_libs=$($pkg_config SDL2_image --libs 2>/dev/null) - fi - sdl_image_cflags=$($pkg_config SDL2_image --cflags 2>/dev/null) - sdl_image=yes - - sdl_cflags="$sdl_cflags $sdl_image_cflags" - sdl_libs="$sdl_libs $sdl_image_libs" - else - if test "$sdl_image" = "yes" ; then - feature_not_found "sdl_image" "Install SDL Image devel" - else - sdl_image=no - fi - fi - fi -} - -if test "$sdl" != "no" ; then - sdl_probe -fi - -if test "$sdl" = "yes" ; then - sdl_image_probe -else - if test "$sdl_image" = "yes"; then - echo "warning: SDL Image requested, but SDL is not available, disabling" - fi - sdl_image=no -fi - -if test "$sdl" = "yes" ; then - cat > $TMPC < -#if defined(SDL_VIDEO_DRIVER_X11) -#include -#else -#error No x11 support -#endif -int main(void) { return 0; } -EOF - if compile_prog "$sdl_cflags $x11_cflags" "$sdl_libs $x11_libs" ; then - need_x11=yes - sdl_cflags="$sdl_cflags $x11_cflags" - sdl_libs="$sdl_libs $x11_libs" - fi -fi - ########################################## # RDMA needs OpenFabrics libraries if test "$rdma" != "no" ; then @@ -7054,14 +6935,6 @@ if test "$have_x11" = "yes" && test "$need_x11" = "yes"; then echo "X11_CFLAGS=$x11_cflags" >> $config_host_mak echo "X11_LIBS=$x11_libs" >> $config_host_mak fi -if test "$sdl" = "yes" ; then - echo "CONFIG_SDL=m" >> $config_host_mak - echo "SDL_CFLAGS=$sdl_cflags" >> $config_host_mak - echo "SDL_LIBS=$sdl_libs" >> $config_host_mak - if test "$sdl_image" = "yes" ; then - echo "CONFIG_SDL_IMAGE=y" >> $config_host_mak - fi -fi if test "$cocoa" = "yes" ; then echo "CONFIG_COCOA=y" >> $config_host_mak fi @@ -8453,6 +8326,7 @@ NINJA=$PWD/ninjatool $meson setup \ -Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \ -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \ -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; fi) \ + -Dsdl=$sdl -Dsdl_image=$sdl_image \ $cross_arg \ "$PWD" "$source_path" diff --git a/meson.build b/meson.build index 0b03726ad3..f0374e8508 100644 --- a/meson.build +++ b/meson.build @@ -11,6 +11,7 @@ cc = meson.get_compiler('c') config_host = keyval.load(meson.current_build_dir() / 'config-host.mak') config_all_disas = keyval.load(meson.current_build_dir() / 'config-all-disas.mak') enable_modules = 'CONFIG_MODULES' in config_host +enable_static = 'CONFIG_STATIC' in config_host build_docs = 'BUILD_DOCS' in config_host config_host_data = configuration_data() genh = [] @@ -218,13 +219,24 @@ brlapi = not_found if 'CONFIG_BRLAPI' in config_host brlapi = declare_dependency(link_args: config_host['BRLAPI_LIBS'].split()) endif -sdlwindows = false -sdl = not_found -if 'CONFIG_SDL' in config_host - sdl = declare_dependency(compile_args: config_host['SDL_CFLAGS'].split(), - link_args: config_host['SDL_LIBS'].split()) - sdlwindows = config_host['SDL_LIBS'].contains('-mwindows') + +sdl = dependency('sdl2', required: get_option('sdl'), static: enable_static, + include_type: 'system') +sdl_image = not_found +if sdl.found() + # work around 2.0.8 bug + sdl = declare_dependency(compile_args: '-Wno-undef', + dependencies: sdl) + sdl_image = dependency('sdl-image', required: get_option('sdl_image'), + static: enable_static) +else + if get_option('sdl_image').enabled() + error('sdl-image required, but SDL was @0@', + get_option('sdl').disabled() ? 'disabled' : 'not found') + endif + sdl_image = not_found endif + rbd = not_found if 'CONFIG_RBD' in config_host rbd = declare_dependency(link_args: config_host['RBD_LIBS'].split()) @@ -363,6 +375,8 @@ endif # Create config-host.h +config_host_data.set('CONFIG_SDL', sdl.found()) +config_host_data.set('CONFIG_SDL_IMAGE', sdl_image.found()) config_host_data.set('QEMU_VERSION', '"@0@"'.format(meson.project_version())) config_host_data.set('QEMU_VERSION_MAJOR', meson.project_version().split('.')[0]) config_host_data.set('QEMU_VERSION_MINOR', meson.project_version().split('.')[1]) @@ -963,7 +977,7 @@ foreach target : target_dirs 'sources': files('softmmu/main.c'), 'dependencies': [] }] - if sdlwindows + if targetos == 'windows' and (sdl.found() or gtk.found()) execs += [{ 'name': 'qemu-system-' + target_name + 'w', 'gui': true, @@ -1239,8 +1253,8 @@ if targetos == 'darwin' summary_info += {'Cocoa support': config_host.has_key('CONFIG_COCOA')} endif # TODO: add back version -summary_info += {'SDL support': config_host.has_key('CONFIG_SDL')} -summary_info += {'SDL image support': config_host.has_key('CONFIG_SDL_IMAGE')} +summary_info += {'SDL support': sdl.found()} +summary_info += {'SDL image support': sdl_image.found()} # TODO: add back version summary_info += {'GTK support': config_host.has_key('CONFIG_GTK')} summary_info += {'GTK GL support': config_host.has_key('CONFIG_GTK_GL')} diff --git a/meson_options.txt b/meson_options.txt new file mode 100644 index 0000000000..e548211f34 --- /dev/null +++ b/meson_options.txt @@ -0,0 +1,2 @@ +option('sdl', type : 'feature', value : 'auto') +option('sdl_image', type : 'feature', value : 'auto') diff --git a/softmmu/main.c b/softmmu/main.c index 7adc530c73..639c67ff48 100644 --- a/softmmu/main.c +++ b/softmmu/main.c @@ -29,6 +29,7 @@ #ifdef CONFIG_SDL #if defined(__APPLE__) || defined(main) #include +static int qemu_main(int argc, char **argv, char **envp); int main(int argc, char **argv) { return qemu_main(argc, argv, NULL); diff --git a/ui/meson.build b/ui/meson.build index 66282c398d..daec6c405e 100644 --- a/ui/meson.build +++ b/ui/meson.build @@ -55,11 +55,11 @@ if config_host.has_key('CONFIG_GTK') and config_host.has_key('CONFIG_VTE') ui_modules += {'gtk' : gtk_ss} endif -if config_host.has_key('CONFIG_SDL') +if sdl.found() softmmu_ss.add(when: 'CONFIG_WIN32', if_true: files('win32-kbd-hook.c')) sdl_ss = ss.source_set() - sdl_ss.add(pixman, glib, files( + sdl_ss.add(sdl, sdl_image, pixman, glib, files( 'sdl2-2d.c', 'sdl2-input.c', 'sdl2.c', -- cgit v1.2.3-55-g7522 From a0b93237d82bed836842a75f9927ec72ebba280b Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 6 Feb 2020 15:48:52 +0100 Subject: meson: convert VNC and dependent libraries to meson Signed-off-by: Paolo Bonzini --- configure | 122 ++++++------------------------------------------------ meson.build | 40 +++++++++++------- meson_options.txt | 4 ++ ui/meson.build | 10 ++--- 4 files changed, 45 insertions(+), 131 deletions(-) diff --git a/configure b/configure index 5b7b932e8d..916bd5085a 100755 --- a/configure +++ b/configure @@ -426,12 +426,12 @@ sdl="auto" sdl_image="auto" virtfs="" mpath="" -vnc="yes" +vnc="enabled" sparse="no" vde="" -vnc_sasl="" -vnc_jpeg="" -vnc_png="" +vnc_sasl="auto" +vnc_jpeg="auto" +vnc_png="auto" xkbcommon="" xen="" xen_ctrl_version="" @@ -1157,9 +1157,9 @@ for opt do ;; --enable-mpath) mpath="yes" ;; - --disable-vnc) vnc="no" + --disable-vnc) vnc="disabled" ;; - --enable-vnc) vnc="yes" + --enable-vnc) vnc="enabled" ;; --oss-lib=*) oss_lib="$optarg" ;; @@ -1195,17 +1195,17 @@ for opt do ;; --disable-strip) strip_opt="no" ;; - --disable-vnc-sasl) vnc_sasl="no" + --disable-vnc-sasl) vnc_sasl="disabled" ;; - --enable-vnc-sasl) vnc_sasl="yes" + --enable-vnc-sasl) vnc_sasl="enabled" ;; - --disable-vnc-jpeg) vnc_jpeg="no" + --disable-vnc-jpeg) vnc_jpeg="disabled" ;; - --enable-vnc-jpeg) vnc_jpeg="yes" + --enable-vnc-jpeg) vnc_jpeg="enabled" ;; - --disable-vnc-png) vnc_png="no" + --disable-vnc-png) vnc_png="disabled" ;; - --enable-vnc-png) vnc_png="yes" + --enable-vnc-png) vnc_png="enabled" ;; --disable-slirp) slirp="no" ;; @@ -3428,85 +3428,6 @@ EOF fi fi -########################################## -# VNC SASL detection -if test "$vnc" = "yes" && test "$vnc_sasl" != "no" ; then - cat > $TMPC < -#include -int main(void) { sasl_server_init(NULL, "qemu"); return 0; } -EOF - # Assuming Cyrus-SASL installed in /usr prefix - # QEMU defines struct iovec in "qemu/osdep.h", - # we don't want libsasl to redefine it in . - vnc_sasl_cflags="-DSTRUCT_IOVEC_DEFINED" - vnc_sasl_libs="-lsasl2" - if compile_prog "$vnc_sasl_cflags" "$vnc_sasl_libs" ; then - vnc_sasl=yes - libs_softmmu="$vnc_sasl_libs $libs_softmmu" - QEMU_CFLAGS="$QEMU_CFLAGS $vnc_sasl_cflags" - else - if test "$vnc_sasl" = "yes" ; then - feature_not_found "vnc-sasl" "Install Cyrus SASL devel" - fi - vnc_sasl=no - fi -fi - -########################################## -# VNC JPEG detection -if test "$vnc" = "yes" && test "$vnc_jpeg" != "no" ; then -cat > $TMPC < -#include -int main(void) { struct jpeg_compress_struct s; jpeg_create_compress(&s); return 0; } -EOF - vnc_jpeg_cflags="" - vnc_jpeg_libs="-ljpeg" - if compile_prog "$vnc_jpeg_cflags" "$vnc_jpeg_libs" ; then - vnc_jpeg=yes - libs_softmmu="$vnc_jpeg_libs $libs_softmmu" - QEMU_CFLAGS="$QEMU_CFLAGS $vnc_jpeg_cflags" - else - if test "$vnc_jpeg" = "yes" ; then - feature_not_found "vnc-jpeg" "Install libjpeg-turbo devel" - fi - vnc_jpeg=no - fi -fi - -########################################## -# VNC PNG detection -if test "$vnc" = "yes" && test "$vnc_png" != "no" ; then -cat > $TMPC < -#include -#include -int main(void) { - png_structp png_ptr; - png_ptr = png_create_write_struct(PNG_LIBPNG_VER_STRING, NULL, NULL, NULL); - return png_ptr != 0; -} -EOF - if $pkg_config libpng --exists; then - vnc_png_cflags=$($pkg_config libpng --cflags) - vnc_png_libs=$($pkg_config libpng --libs) - else - vnc_png_cflags="" - vnc_png_libs="-lpng" - fi - if compile_prog "$vnc_png_cflags" "$vnc_png_libs" ; then - vnc_png=yes - libs_softmmu="$vnc_png_libs $libs_softmmu" - QEMU_CFLAGS="$QEMU_CFLAGS $vnc_png_cflags" - else - if test "$vnc_png" = "yes" ; then - feature_not_found "vnc-png" "Install libpng devel" - fi - vnc_png=no - fi -fi - ########################################## # xkbcommon probe if test "$xkbcommon" != "no" ; then @@ -6888,24 +6809,6 @@ if test "$audio_win_int" = "yes" ; then fi echo "CONFIG_BDRV_RW_WHITELIST=$block_drv_rw_whitelist" >> $config_host_mak echo "CONFIG_BDRV_RO_WHITELIST=$block_drv_ro_whitelist" >> $config_host_mak -if test "$vnc" = "yes" ; then - echo "CONFIG_VNC=y" >> $config_host_mak -fi -if test "$vnc_sasl" = "yes" ; then - echo "CONFIG_VNC_SASL=y" >> $config_host_mak -fi -echo "SASL_CFLAGS=$vnc_sasl_cflags" >> $config_host_mak -echo "SASL_LIBS=$vnc_sasl_libs" >> $config_host_mak -if test "$vnc_jpeg" = "yes" ; then - echo "CONFIG_VNC_JPEG=y" >> $config_host_mak -fi -echo "JPEG_CFLAGS=$vnc_jpeg_cflags" >> $config_host_mak -echo "JPEG_LIBS=$vnc_jpeg_libs" >> $config_host_mak -if test "$vnc_png" = "yes" ; then - echo "CONFIG_VNC_PNG=y" >> $config_host_mak -fi -echo "PNG_CFLAGS=$vnc_png_cflags" >> $config_host_mak -echo "PNG_LIBS=$vnc_png_libs" >> $config_host_mak if test "$xkbcommon" = "yes" ; then echo "CONFIG_XKBCOMMON=y" >> $config_host_mak echo "XKBCOMMON_CFLAGS=$xkbcommon_cflags" >> $config_host_mak @@ -8327,6 +8230,7 @@ NINJA=$PWD/ninjatool $meson setup \ -Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \ -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; fi) \ -Dsdl=$sdl -Dsdl_image=$sdl_image \ + -Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png \ $cross_arg \ "$PWD" "$source_path" diff --git a/meson.build b/meson.build index f0374e8508..1ae9d42868 100644 --- a/meson.build +++ b/meson.build @@ -306,20 +306,24 @@ if 'CONFIG_GIO' in config_host gio = declare_dependency(compile_args: config_host['GIO_CFLAGS'].split(), link_args: config_host['GIO_LIBS'].split()) endif +vnc = not_found png = not_found -if 'CONFIG_VNC_PNG' in config_host - png = declare_dependency(compile_args: config_host['PNG_CFLAGS'].split(), - link_args: config_host['PNG_LIBS'].split()) -endif jpeg = not_found -if 'CONFIG_VNC_JPEG' in config_host - jpeg = declare_dependency(compile_args: config_host['JPEG_CFLAGS'].split(), - link_args: config_host['JPEG_LIBS'].split()) -endif sasl = not_found -if 'CONFIG_VNC_SASL' in config_host - sasl = declare_dependency(compile_args: config_host['SASL_CFLAGS'].split(), - link_args: config_host['SASL_LIBS'].split()) +if get_option('vnc').enabled() + vnc = declare_dependency() # dummy dependency + png = dependency('libpng', required: get_option('vnc_png'), + static: enable_static) + jpeg = cc.find_library('jpeg', has_headers: ['jpeglib.h'], + required: get_option('vnc_jpeg'), + static: enable_static) + sasl = cc.find_library('sasl2', has_headers: ['sasl/sasl.h'], + required: get_option('vnc_sasl'), + static: enable_static) + if sasl.found() + sasl = declare_dependency(dependencies: sasl, + compile_args: '-DSTRUCT_IOVEC_DEFINED') + endif endif fdt = not_found if 'CONFIG_FDT' in config_host @@ -377,6 +381,10 @@ endif config_host_data.set('CONFIG_SDL', sdl.found()) config_host_data.set('CONFIG_SDL_IMAGE', sdl_image.found()) +config_host_data.set('CONFIG_VNC', vnc.found()) +config_host_data.set('CONFIG_VNC_JPEG', jpeg.found()) +config_host_data.set('CONFIG_VNC_PNG', png.found()) +config_host_data.set('CONFIG_VNC_SASL', sasl.found()) config_host_data.set('QEMU_VERSION', '"@0@"'.format(meson.project_version())) config_host_data.set('QEMU_VERSION_MAJOR', meson.project_version().split('.')[0]) config_host_data.set('QEMU_VERSION_MINOR', meson.project_version().split('.')[1]) @@ -1286,11 +1294,11 @@ summary_info += {'Block whitelist (rw)': config_host['CONFIG_BDRV_RW_WHITELIST'] summary_info += {'Block whitelist (ro)': config_host['CONFIG_BDRV_RO_WHITELIST']} summary_info += {'VirtFS support': config_host.has_key('CONFIG_VIRTFS')} summary_info += {'Multipath support': config_host.has_key('CONFIG_MPATH')} -summary_info += {'VNC support': config_host.has_key('CONFIG_VNC')} -if config_host.has_key('CONFIG_VNC') - summary_info += {'VNC SASL support': config_host.has_key('CONFIG_VNC_SASL')} - summary_info += {'VNC JPEG support': config_host.has_key('CONFIG_VNC_JPEG')} - summary_info += {'VNC PNG support': config_host.has_key('CONFIG_VNC_PNG')} +summary_info += {'VNC support': vnc.found()} +if vnc.found() + summary_info += {'VNC SASL support': sasl.found()} + summary_info += {'VNC JPEG support': jpeg.found()} + summary_info += {'VNC PNG support': png.found()} endif summary_info += {'xen support': config_host.has_key('CONFIG_XEN_BACKEND')} if config_host.has_key('CONFIG_XEN_BACKEND') diff --git a/meson_options.txt b/meson_options.txt index e548211f34..67455c57bc 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -1,2 +1,6 @@ option('sdl', type : 'feature', value : 'auto') option('sdl_image', type : 'feature', value : 'auto') +option('vnc', type : 'feature', value : 'enabled') +option('vnc_jpeg', type : 'feature', value : 'auto') +option('vnc_png', type : 'feature', value : 'auto') +option('vnc_sasl', type : 'feature', value : 'auto') diff --git a/ui/meson.build b/ui/meson.build index daec6c405e..6f74d30ea0 100644 --- a/ui/meson.build +++ b/ui/meson.build @@ -27,14 +27,12 @@ vnc_ss.add(files( 'vnc-ws.c', 'vnc-jobs.c', )) -vnc_ss.add(zlib) -vnc_ss.add(when: 'CONFIG_VNC_SASL', if_true: [files('vnc-auth-sasl.c'), sasl]) -softmmu_ss.add_all(when: 'CONFIG_VNC', if_true: vnc_ss) -softmmu_ss.add(when: 'CONFIG_VNC', if_false: files('vnc-stubs.c')) +vnc_ss.add(zlib, png, jpeg) +vnc_ss.add(when: sasl, if_true: files('vnc-auth-sasl.c')) +softmmu_ss.add_all(when: vnc, if_true: vnc_ss) +softmmu_ss.add(when: vnc, if_false: files('vnc-stubs.c')) softmmu_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true: files('shader.c', 'console-gl.c', 'egl-helpers.c', 'egl-context.c')) softmmu_ss.add(when: [opengl, 'CONFIG_OPENGL_DMABUF'], if_true: files('egl-headless.c')) -softmmu_ss.add(when: 'CONFIG_VNC_PNG', if_true: png) -softmmu_ss.add(when: 'CONFIG_VNC_JPEG', if_true: jpeg) ui_modules = {} -- cgit v1.2.3-55-g7522 From e8f3bd71d830f986c950439c0d125f4bab8e0313 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Thu, 19 Sep 2019 21:02:09 +0400 Subject: meson: convert po/ Meson warns if xgettext is not found. In the future we may want to add a required argument to i18n.gettext(); in the meanwhile, I am adding a --enable-gettext/--disable-gettext option and feature detection in configure. This preserves QEMU's default behavior of detecting system features, without any warning, if neither --enable-* nor --disable-* is requested. Signed-off-by: Marc-André Lureau Signed-off-by: Paolo Bonzini --- Makefile | 5 +--- configure | 21 +++++++++++++++- meson.build | 3 +++ meson_options.txt | 1 + po/LINGUAS | 8 ++++++ po/Makefile | 52 -------------------------------------- po/POTFILES | 1 + po/meson.build | 7 ++++++ po/messages.po | 74 ------------------------------------------------------- tests/vm/freebsd | 1 + tests/vm/netbsd | 1 + tests/vm/openbsd | 1 + 12 files changed, 44 insertions(+), 131 deletions(-) create mode 100644 po/LINGUAS delete mode 100644 po/Makefile create mode 100644 po/POTFILES create mode 100644 po/meson.build delete mode 100644 po/messages.po diff --git a/Makefile b/Makefile index aa582d6554..8373ddccc9 100644 --- a/Makefile +++ b/Makefile @@ -219,7 +219,7 @@ distclean: clean ninja-distclean rm -f config-host.mak config-host.h* rm -f tests/tcg/config-*.mak rm -f config-all-disas.mak config.status - rm -f po/*.mo tests/qemu-iotests/common.env + rm -f tests/qemu-iotests/common.env rm -f roms/seabios/config.mak roms/vgabios/config.mak rm -f qemu-plugins-ld.symbols qemu-plugins-ld64.symbols rm -f *-config-target.h *-config-devices.mak *-config-devices.h @@ -297,9 +297,6 @@ endif mkdir -p "$(DESTDIR)$(qemu_desktopdir)" $(INSTALL_DATA) $(SRC_PATH)/ui/qemu.desktop \ "$(DESTDIR)$(qemu_desktopdir)/qemu.desktop" -ifdef CONFIG_GTK - $(MAKE) -C po $@ -endif $(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)/keymaps" set -e; for x in $(KEYMAPS); do \ $(INSTALL_DATA) $(SRC_PATH)/pc-bios/keymaps/$$x "$(DESTDIR)$(qemu_datadir)/keymaps"; \ diff --git a/configure b/configure index 916bd5085a..4e5fe33211 100755 --- a/configure +++ b/configure @@ -569,6 +569,7 @@ secret_keyring="" libdaxctl="" meson="" skip_meson=no +gettext="" bogus_os="no" malloc_trim="" @@ -1161,6 +1162,10 @@ for opt do ;; --enable-vnc) vnc="enabled" ;; + --disable-gettext) gettext="false" + ;; + --enable-gettext) gettext="true" + ;; --oss-lib=*) oss_lib="$optarg" ;; --audio-drv-list=*) audio_drv_list="$optarg" @@ -3032,6 +3037,19 @@ if test "$whpx" != "no" ; then fi fi +########################################## +# gettext probe +if test "$gettext" != "false" ; then + if has xgettext; then + gettext=true + else + if test "$gettext" = "true" ; then + feature_not_found "gettext" "Install xgettext binary" + fi + gettext=false + fi +fi + ########################################## # Sparse probe if test "$sparse" != "no" ; then @@ -8099,7 +8117,7 @@ DIRS="$DIRS docs docs/interop fsdev scsi" DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw" DIRS="$DIRS roms/seabios" LINKS="Makefile" -LINKS="$LINKS tests/tcg/lm32/Makefile po/Makefile" +LINKS="$LINKS tests/tcg/lm32/Makefile" LINKS="$LINKS tests/tcg/Makefile.target" LINKS="$LINKS pc-bios/optionrom/Makefile pc-bios/keymaps" LINKS="$LINKS pc-bios/s390-ccw/Makefile" @@ -8231,6 +8249,7 @@ NINJA=$PWD/ninjatool $meson setup \ -Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; fi) \ -Dsdl=$sdl -Dsdl_image=$sdl_image \ -Dvnc=$vnc -Dvnc_sasl=$vnc_sasl -Dvnc_jpeg=$vnc_jpeg -Dvnc_png=$vnc_png \ + -Dgettext=$gettext \ $cross_arg \ "$PWD" "$source_path" diff --git a/meson.build b/meson.build index 1ae9d42868..62bf8a51c2 100644 --- a/meson.build +++ b/meson.build @@ -1115,6 +1115,9 @@ subdir('tools') subdir('pc-bios') subdir('tests') subdir('docs') +if 'CONFIG_GTK' in config_host + subdir('po') +endif if build_docs makeinfo = find_program('makeinfo', required: build_docs) diff --git a/meson_options.txt b/meson_options.txt index 67455c57bc..e5f45243ce 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -1,3 +1,4 @@ +option('gettext', type : 'boolean', value : true) option('sdl', type : 'feature', value : 'auto') option('sdl_image', type : 'feature', value : 'auto') option('vnc', type : 'feature', value : 'enabled') diff --git a/po/LINGUAS b/po/LINGUAS new file mode 100644 index 0000000000..cc4b5c3b36 --- /dev/null +++ b/po/LINGUAS @@ -0,0 +1,8 @@ +bg +de_DE +fr_FR +hu +it +sv +tr +zh_CN diff --git a/po/Makefile b/po/Makefile deleted file mode 100644 index c041f4c858..0000000000 --- a/po/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# This makefile is very special as it's meant to build as part of the build -# process and also within the source tree to update the translation files. - -# Set SRC_PATH for in-tree builds without configuration. -SRC_PATH=.. - -# The default target must come before any include statements. -all: - -.PHONY: all build clean install update - -%.mo: %.po - $(call quiet-command, msgfmt -o $@ $<,"GEN","$@") - --include ../config-host.mak -include $(SRC_PATH)/rules.mak - -PO_PATH=$(SRC_PATH)/po - -VERSION=$(shell cat $(SRC_PATH)/VERSION) -SRCS=$(filter-out $(PO_PATH)/messages.po,$(wildcard $(PO_PATH)/*.po)) -OBJS=$(patsubst $(PO_PATH)/%.po,%.mo,$(SRCS)) - -vpath %.po $(PO_PATH) - -all: - @echo "Use 'make update' to update translation files or use 'make build'" - @echo "or 'make install' to build and install the translation files." - -update: $(SRCS) - -build: $(OBJS) - -clean: - rm -f $(OBJS) - -install: $(OBJS) - for obj in $(OBJS); do \ - base=$$(basename $$obj .mo); \ - $(INSTALL) -d $(DESTDIR)$(prefix)/share/locale/$$base/LC_MESSAGES; \ - $(INSTALL) -m644 $$obj $(DESTDIR)$(prefix)/share/locale/$$base/LC_MESSAGES/qemu.mo; \ - done - -$(PO_PATH)/messages.po: $(SRC_PATH)/ui/gtk.c - $(call quiet-command, ( cd $(SRC_PATH) && \ - xgettext -o - --from-code=UTF-8 --foreign-user --no-location \ - --package-name=QEMU --package-version=$(VERSION) \ - --msgid-bugs-address=qemu-devel@nongnu.org -k_ -C ui/gtk.c | \ - sed -e s/CHARSET/UTF-8/) >$@,"GEN","$@") - -$(PO_PATH)/%.po: $(PO_PATH)/messages.po - $(call quiet-command, msgmerge -q $@ $< > $@.bak && mv $@.bak $@,"GEN","$@") diff --git a/po/POTFILES b/po/POTFILES new file mode 100644 index 0000000000..d34d5ed9aa --- /dev/null +++ b/po/POTFILES @@ -0,0 +1 @@ +ui/gtk.c diff --git a/po/meson.build b/po/meson.build new file mode 100644 index 0000000000..1387fd979a --- /dev/null +++ b/po/meson.build @@ -0,0 +1,7 @@ +i18n = import('i18n') + +if get_option('gettext') + i18n.gettext(meson.project_name(), + args: '--msgid-bugs-address=qemu-devel@nongnu.org', + preset: 'glib') +endif diff --git a/po/messages.po b/po/messages.po deleted file mode 100644 index 065bd459a0..0000000000 --- a/po/messages.po +++ /dev/null @@ -1,74 +0,0 @@ -# SOME DESCRIPTIVE TITLE. -# This file is put in the public domain. -# FIRST AUTHOR , YEAR. -# -#, fuzzy -msgid "" -msgstr "" -"Project-Id-Version: QEMU 2.12.91\n" -"Report-Msgid-Bugs-To: qemu-devel@nongnu.org\n" -"POT-Creation-Date: 2018-07-18 07:56+0200\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME \n" -"Language-Team: LANGUAGE \n" -"Language: \n" -"MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=UTF-8\n" -"Content-Transfer-Encoding: 8bit\n" - -msgid " - Press Ctrl+Alt+G to release grab" -msgstr "" - -msgid " [Paused]" -msgstr "" - -msgid "_Pause" -msgstr "" - -msgid "_Reset" -msgstr "" - -msgid "Power _Down" -msgstr "" - -msgid "_Quit" -msgstr "" - -msgid "_Fullscreen" -msgstr "" - -msgid "_Copy" -msgstr "" - -msgid "Zoom _In" -msgstr "" - -msgid "Zoom _Out" -msgstr "" - -msgid "Best _Fit" -msgstr "" - -msgid "Zoom To _Fit" -msgstr "" - -msgid "Grab On _Hover" -msgstr "" - -msgid "_Grab Input" -msgstr "" - -msgid "Show _Tabs" -msgstr "" - -msgid "Detach Tab" -msgstr "" - -msgid "Show Menubar" -msgstr "" - -msgid "_Machine" -msgstr "" - -msgid "_View" -msgstr "" diff --git a/tests/vm/freebsd b/tests/vm/freebsd index b34b14fc53..5f866e09c4 100755 --- a/tests/vm/freebsd +++ b/tests/vm/freebsd @@ -39,6 +39,7 @@ class FreeBSDVM(basevm.BaseVM): "bash", "gmake", "gsed", + "gettext", # libs: crypto "gnutls", diff --git a/tests/vm/netbsd b/tests/vm/netbsd index 93d48b6fdd..ffb65a89be 100755 --- a/tests/vm/netbsd +++ b/tests/vm/netbsd @@ -37,6 +37,7 @@ class NetBSDVM(basevm.BaseVM): "bash", "gmake", "gsed", + "gettext", # libs: crypto "gnutls", diff --git a/tests/vm/openbsd b/tests/vm/openbsd index 7e27fda642..8356646f21 100755 --- a/tests/vm/openbsd +++ b/tests/vm/openbsd @@ -36,6 +36,7 @@ class OpenBSDVM(basevm.BaseVM): "bash", "gmake", "gsed", + "gettext", # libs: usb "libusb1", -- cgit v1.2.3-55-g7522 From b29b40f4abefa789111a6063b19dde9b276662ff Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 10 Aug 2020 18:04:43 +0200 Subject: meson: avoid unstable module warning with Meson 0.56.0 or newer Signed-off-by: Paolo Bonzini --- meson.build | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 62bf8a51c2..808f50b07e 100644 --- a/meson.build +++ b/meson.build @@ -3,7 +3,11 @@ project('qemu', ['c'], meson_version: '>=0.55.0', version: run_command('head', meson.source_root() / 'VERSION').stdout().strip()) not_found = dependency('', required: false) -keyval = import('unstable-keyval') +if meson.version().version_compare('>=0.56.0') + keyval = import('keyval') +else + keyval = import('unstable-keyval') +endif ss = import('sourceset') sh = find_program('sh') -- cgit v1.2.3-55-g7522 From 77d27b9271bed903c85463a5518c28929a88a676 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 4 Feb 2020 11:43:54 +0100 Subject: meson: update build-system documentation Signed-off-by: Paolo Bonzini --- docs/devel/build-system.txt | 468 +++++++++++++++++++++++--------------------- 1 file changed, 240 insertions(+), 228 deletions(-) diff --git a/docs/devel/build-system.txt b/docs/devel/build-system.txt index fea67b207c..2ced8ca474 100644 --- a/docs/devel/build-system.txt +++ b/docs/devel/build-system.txt @@ -22,15 +22,34 @@ silent while it is checking for features. It will only display output when an error occurs, or to show the final feature enablement summary on completion. -Adding new checks to the configure script usually comprises the -following tasks: +Because QEMU uses the Meson build system under the hood, only VPATH +builds are supported. There are two general ways to invoke configure & +perform a build: + + - VPATH, build artifacts outside of QEMU source tree entirely + + cd ../ + mkdir build + cd build + ../qemu/configure + make + + - VPATH, build artifacts in a subdir of QEMU source tree + + mkdir build + cd build + ../configure + make + +For now, checks on the compilation environment are found in configure +rather than meson.build, though this is expected to change. The command +line is parsed in the configure script and, whenever needed, converted +into the appropriate options to Meson. - - Initialize one or more variables with the default feature state. +New checks should be added to Meson, which usually comprises the +following tasks: - Ideally features should auto-detect whether they are present, - so try to avoid hardcoding the initial state to either enabled - or disabled, as that forces the user to pass a --enable-XXX - / --disable-XXX flag on every invocation of configure. + - Add a Meson build option to meson_options.txt. - Add support to the command line arg parser to handle any new --enable-XXX / --disable-XXX flags required by the feature XXX. @@ -38,63 +57,55 @@ following tasks: - Add information to the help output message to report on the new feature flag. - - Add code to perform the actual feature check. As noted above, try to - be fully dynamic in checking enablement/disablement. + - Add code to perform the actual feature check. + + - Add code to include the feature status in config-host.h - Add code to print out the feature status in the configure summary upon completion. - - Add any new makefile variables to $config_host_mak on completion. - -Taking (a simplified version of) the probe for gnutls from configure, -we have the following pieces: +Taking the probe for SDL as an example, we have the following pieces +in configure: # Initial variable state - gnutls="" + sdl=auto ..snip.. # Configure flag processing - --disable-gnutls) gnutls="no" + --disable-gnutls) sdl=disabled ;; - --enable-gnutls) gnutls="yes" + --enable-gnutls) sdl=enabled ;; ..snip.. # Help output feature message - gnutls GNUTLS cryptography support + sdl SDL UI ..snip.. - # Test for gnutls - if test "$gnutls" != "no"; then - if ! $pkg_config --exists "gnutls"; then - gnutls_cflags=`$pkg_config --cflags gnutls` - gnutls_libs=`$pkg_config --libs gnutls` - libs_softmmu="$gnutls_libs $libs_softmmu" - libs_tools="$gnutls_libs $libs_tools" - QEMU_CFLAGS="$QEMU_CFLAGS $gnutls_cflags" - gnutls="yes" - elif test "$gnutls" = "yes"; then - feature_not_found "gnutls" "Install gnutls devel" - else - gnutls="no" - fi - fi + # Meson invocation + -Dsdl=$sdl - ..snip.. +In meson_options.txt: - # Completion feature summary - echo "GNUTLS support $gnutls" + option('sdl', type : 'feature', value : 'auto') - ..snip.. +In meson.build: + + # Detect dependency + sdl = dependency('sdl2', + required: get_option('sdl'), + static: enable_static) + + # Create config-host.h + config_host_data.set('CONFIG_SDL', sdl.found()) + + # Summary + summary_info += {'SDL support': sdl.found()} - # Define make variables - if test "$gnutls" = "yes" ; then - echo "CONFIG_GNUTLS=y" >> $config_host_mak - fi Helper functions @@ -164,145 +175,189 @@ developers in checking for system features: then --static will be automatically added to $ARGS -Stage 2: makefiles -================== +Stage 2: Meson +============== -The use of GNU make is required with the QEMU build system. +The Meson build system is currently used to describe the build +process for: -Although the source code is spread across multiple subdirectories, the -build system should be considered largely non-recursive in nature, in -contrast to common practices seen with automake. There is some recursive -invocation of make, but this is related to the things being built, -rather than the source directory structure. +1) executables, which include: + - Tools - qemu-img, qemu-nbd, qga (guest agent), etc + - System emulators - qemu-system-$ARCH + - Userspace emulators - qemu-$ARCH + - Some (but not all) unit tests -QEMU currently supports both VPATH and non-VPATH builds, so there are -three general ways to invoke configure & perform a build. +2) documentation - - VPATH, build artifacts outside of QEMU source tree entirely +3) ROMs, which can be either installed as binary blobs or compiled - cd ../ - mkdir build - cd build - ../qemu/configure - make +4) other data files, such as icons or desktop files - - VPATH, build artifacts in a subdir of QEMU source tree - - mkdir build - cd build - ../configure - make - - - non-VPATH, build artifacts everywhere - - ./configure - make - -The QEMU maintainers generally recommend that a VPATH build is used by -developers. Patches to QEMU are expected to ensure VPATH build still -works. +The source code is highly modularized, split across many files to +facilitate building of all of these components with as little duplicated +compilation as possible. The Meson "sourceset" functionality is used +to list the files and their dependency on various configuration +symbols. +Various subsystems that are common to both tools and emulators have +their own sourceset, for example block_ss for the block device subsystem, +chardev_ss for the character device subsystem, etc. These sourcesets +are then turned into static libraries as follows: -Module structure ----------------- + libchardev = static_library('chardev', chardev_ss.sources(), + name_suffix: 'fa', + build_by_default: false) -There are a number of key outputs of the QEMU build system: + chardev = declare_dependency(link_whole: libchardev) - - Tools - qemu-img, qemu-nbd, qga (guest agent), etc - - System emulators - qemu-system-$ARCH - - Userspace emulators - qemu-$ARCH - - Unit tests +The special ".fa" suffix is needed as long as unit tests are built with +the older Makefile infrastructure, and will go away later. -The source code is highly modularized, split across many files to -facilitate building of all of these components with as little duplicated -compilation as possible. There can be considered to be two distinct -groups of files, those which are independent of the QEMU emulation -target and those which are dependent on the QEMU emulation target. +Files linked into emulator targets there can be split into two distinct groups +of files, those which are independent of the QEMU emulation target and +those which are dependent on the QEMU emulation target. In the target-independent set lives various general purpose helper code, such as error handling infrastructure, standard data structures, platform portability wrapper functions, etc. This code can be compiled once only and the .o files linked into all output binaries. +Target-independent code lives in the common_ss, softmmu_ss and user_ss +sourcesets. common_ss is linked into all emulators, softmmu_ss only +in system emulators, user_ss only in user-mode emulators. In the target-dependent set lives CPU emulation, device emulation and much glue code. This sometimes also has to be compiled multiple times, once for each target being built. -The utility code that is used by all binaries is built into a -static archive called libqemuutil.a, which is then linked to all the -binaries. In order to provide hooks that are only needed by some of the -binaries, code in libqemuutil.a may depend on other functions that are -not fully implemented by all QEMU binaries. Dummy stubs for all these -functions are also provided by this library, and will only be linked +All binaries link with a static library libqemuutil.a, which is then +linked to all the binaries. libqemuutil.a is built from several +sourcesets; most of them however host generated code, and the only two +of general interest are util_ss and stub_ss. + +The separation between these two is purely for documentation purposes. +util_ss contains generic utility files. Even though this code is only +linked in some binaries, sometimes it requires hooks only in some of +these and depend on other functions that are not fully implemented by +all QEMU binaries. stub_ss links dummy stubs that will only be linked into the binary if the real implementation is not present. In a way, the stubs can be thought of as a portable implementation of the weak symbols concept. -All binaries should link to libqemuutil.a, e.g.: +The following files concur in the definition of which files are linked +into each emulator: - qemu-img$(EXESUF): qemu-img.o ..snip.. libqemuutil.a +- default-configs/*.mak +The files under default-configs/ control what emulated hardware is built +into each QEMU system and userspace emulator targets. They merely contain +a list of config variable definitions like the machines that should be +included. For example, default-configs/aarch64-softmmu.mak has: -Windows platform portability ----------------------------- + include arm-softmmu.mak + CONFIG_XLNX_ZYNQMP_ARM=y + CONFIG_XLNX_VERSAL=y -On Windows, all binaries have the suffix '.exe', so all Makefile rules -which create binaries must include the $(EXESUF) variable on the binary -name. e.g. +These files rarely need changing unless new devices / hardware need to +be enabled for a particular system/userspace emulation target - qemu-img$(EXESUF): qemu-img.o ..snip.. +- */Kconfig -This expands to '.exe' on Windows, or '' on other platforms. +These files are processed together with default-configs/*.mak and +describe the dependencies between various features, subsystems and +device models. They are described in kconfig.rst. + + +Support scripts +--------------- + +Meson has a special convention for invoking Python scripts: if their +first line is "#! /usr/bin/env python3" and the file is *not* executable, +find_program() arranges to invoke the script under the same Python +interpreter that was used to invoke Meson. This is the most common +and preferred way to invoke support scripts from Meson build files, +because it automatically uses the value of configure's --python= option. -A further complication for the system emulator binaries is that -two separate binaries need to be generated. +In case the script is not written in Python, use a "#! /usr/bin/env ..." +line and make the script executable. -The main binary (e.g. qemu-system-x86_64.exe) is linked against the -Windows console runtime subsystem. These are expected to be run from a -command prompt window, and so will print stderr to the console that -launched them. +Scripts written in Python, where it is desirable to make the script +executable (for example for test scripts that developers may want to +invoke from the command line, such as tests/qapi-schema/test-qapi.py), +should be invoked through the "python" variable in meson.build. For +example: -The second binary generated has a 'w' on the end of its name (e.g. -qemu-system-x86_64w.exe) and is linked against the Windows graphical -runtime subsystem. These are expected to be run directly from the -desktop and will open up a dedicated console window for stderr output. + test('QAPI schema regression tests', python, + args: files('test-qapi.py'), + env: test_env, suite: ['qapi-schema', 'qapi-frontend']) -The Makefile.target will generate the binary for the graphical subsystem -first, and then use objcopy to relink it against the console subsystem -to generate the second binary. +This is needed to obey the --python= option passed to the configure +script, which may point to something other than the first python3 +binary on the path. -Object variable naming ----------------------- +Stage 3: makefiles +================== + +The use of GNU make is required with the QEMU build system. + +The output of Meson is a build.ninja file, which is used with the Ninja +build system. QEMU uses a different approach, where Makefile rules are +synthesized from the build.ninja file. The main Makefile includes these +rules and wraps them so that e.g. submodules are built before QEMU. +The resulting build system is largely non-recursive in nature, in +contrast to common practices seen with automake. + +Tests are also ran by the Makefile with the traditional "make check" +phony target. Meson test suites such as "unit" can be ran with "make +check-unit" too. It is also possible to run tests defined in meson.build +with "meson test". + +The following text is only relevant for unit tests which still have to +be converted to Meson. + +All binaries should link to libqemuutil.a, e.g.: + + qemu-img$(EXESUF): qemu-img.o ..snip.. libqemuutil.a + +On Windows, all binaries have the suffix '.exe', so all Makefile rules +which create binaries must include the $(EXESUF) variable on the binary +name. e.g. + + qemu-img$(EXESUF): qemu-img.o ..snip.. + +This expands to '.exe' on Windows, or '' on other platforms. + +Variable naming +--------------- The QEMU convention is to define variables to list different groups of -object files. These are named with the convention $PREFIX-obj-y. For -example the libqemuutil.a file will be linked with all objects listed -in a variable 'util-obj-y'. So, for example, util/Makefile.obj will -contain a set of definitions looking like +object files. These are named with the convention $PREFIX-obj-y. The +Meson "chardev" variable in the previous example corresponds to a +variable 'chardev-obj-y'. - util-obj-y += bitmap.o bitops.o hbitmap.o - util-obj-y += fifo8.o - util-obj-y += acl.o - util-obj-y += error.o qemu-error.o +Likewise, tests that are executed by "make check-unit" are grouped into +a variable check-unit-y, like this: -When there is an object file which needs to be conditionally built based + check-unit-y += tests/test-visitor-serialization$(EXESUF) + check-unit-y += tests/test-iov$(EXESUF) + check-unit-y += tests/test-bitmap$(EXESUF) + +When a test or object file which needs to be conditionally built based on some characteristic of the host system, the configure script will define a variable for the conditional. For example, on Windows it will define $(CONFIG_POSIX) with a value of 'n' and $(CONFIG_WIN32) with a value of 'y'. It is now possible to use the config variables when listing object files. For example, - util-obj-$(CONFIG_WIN32) += oslib-win32.o qemu-thread-win32.o - util-obj-$(CONFIG_POSIX) += oslib-posix.o qemu-thread-posix.o + check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) On Windows this expands to - util-obj-y += oslib-win32.o qemu-thread-win32.o - util-obj-n += oslib-posix.o qemu-thread-posix.o + check-unit-n += tests/vmstate.exe -Since libqemutil.a links in $(util-obj-y), the POSIX specific files -listed against $(util-obj-n) are ignored on the Windows platform builds. +Since the "check-unit" target only runs tests included in "$(check-unit-y)", +POSIX specific tests listed in $(util-obj-n) are ignored on the Windows +platform builds. CFLAGS / LDFLAGS / LIBS handling @@ -316,27 +371,25 @@ avoided in QEMU, since it would apply to too many build targets. Flags that are needed by any QEMU code (i.e. everything *except* GIT submodule projects) are put in $(QEMU_CFLAGS) variable. For linker flags the $(LIBS) variable is sometimes used, but a couple of more -targeted variables are preferred. $(libs_softmmu) is used for -libraries that must be linked to system emulator targets, $(LIBS_TOOLS) -is used for tools like qemu-img, qemu-nbd, etc and $(LIBS_QGA) is used -for the QEMU guest agent. There is currently no specific variable for -the userspace emulator targets as the global $(LIBS), or more targeted -variables shown below, are sufficient. +targeted variables are preferred. In addition to these variables, it is possible to provide cflags and libs against individual source code files, by defining variables of the -form $FILENAME-cflags and $FILENAME-libs. For example, the curl block -driver needs to link to the libcurl library, so block/Makefile defines -some variables: +form $FILENAME-cflags and $FILENAME-libs. For example, the test +test-crypto-tlscredsx509 needs to link to the libtasn1 library, +so tests/Makefile.include defines some variables: - curl.o-cflags := $(CURL_CFLAGS) - curl.o-libs := $(CURL_LIBS) + tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS) + tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS) The scope is a little different between the two variables. The libs get used when linking any target binary that includes the curl.o object file, while the cflags get used when compiling the curl.c file only. +Important files for the build system +==================================== + Statically defined files ------------------------ @@ -348,81 +401,26 @@ number of dynamically created files listed later. The main entry point used when invoking make to build all the components of QEMU. The default 'all' target will naturally result in the build of -every component. The various tools and helper binaries are built +every component. Makefile takes care of recursively building submodules directly via a non-recursive set of rules. -Each system/userspace emulation target needs to have a slightly -different set of make rules / variables. Thus, make will be recursively -invoked for each of the emulation targets. - -The recursive invocation will end up processing the toplevel -Makefile.target file (more on that later). - - -- */Makefile.objs - -Since the source code is spread across multiple directories, the rules -for each file are similarly modularized. Thus each subdirectory -containing .c files will usually also contain a Makefile.objs file. -These files are not directly invoked by a recursive make, but instead -they are imported by the top level Makefile and/or Makefile.target - -Each Makefile.objs usually just declares a set of variables listing the -.o files that need building from the source files in the directory. They -will also define any custom linker or compiler flags. For example in -block/Makefile.objs - - block-obj-$(CONFIG_LIBISCSI) += iscsi.o - block-obj-$(CONFIG_CURL) += curl.o - - ..snip... +- Makefile.objs - iscsi.o-cflags := $(LIBISCSI_CFLAGS) - iscsi.o-libs := $(LIBISCSI_LIBS) - curl.o-cflags := $(CURL_CFLAGS) - curl.o-libs := $(CURL_LIBS) +Defines *-obj-y files corresponding to -If there are any rules defined in the Makefile.objs file, they should -all use $(obj) as a prefix to the target, e.g. - - $(obj)/generated-tcg-tracers.h: $(obj)/generated-tcg-tracers.h-timestamp - - -- Makefile.target - -This file provides the entry point used to build each individual system -or userspace emulator target. Each enabled target has its own -subdirectory. For example if configure is run with the argument -'--target-list=x86_64-softmmu', then a sub-directory 'x86_64-softmmu' -will be created, containing a 'Makefile' which symlinks back to -Makefile.target - -So when the recursive '$(MAKE) -C x86_64-softmmu' is invoked, it ends up -using Makefile.target for the build rules. +- */meson.build +The meson.build file in the root directory is the main entry point for the +Meson build system, and it coordinates the configuration and build of all +executables. Build rules for various subdirectories are included in +other meson.build files spread throughout the QEMU source tree. - rules.mak This file provides the generic helper rules for invoking build tools, in particular the compiler and linker. - -- default-configs/*.mak - -The files under default-configs/ control what emulated hardware is built -into each QEMU system and userspace emulator targets. They merely contain -a list of config variable definitions like the machines that should be -included. For example, default-configs/aarch64-softmmu.mak has: - - include arm-softmmu.mak - CONFIG_XLNX_ZYNQMP_ARM=y - CONFIG_XLNX_VERSAL=y - -These files rarely need changing unless new devices / hardware need to -be enabled for a particular system/userspace emulation target - - -- tests/Makefile +- tests/Makefile.include Rules for building the unit tests. This file is included directly by the top level Makefile, so anything defined in this file will influence the @@ -435,11 +433,11 @@ Rules for Docker tests. Like tests/Makefile, this file is included directly by the top level Makefile, anything defined in this file will influence the entire build system. -- po/Makefile - -Rules for building and installing the binary message catalogs from the -text .po file sources. This almost never needs changing for any reason. +- tests/vm/Makefile.include +Rules for VM-based tests. Like tests/Makefile, this file is included +directly by the top level Makefile, anything defined in this file will +influence the entire build system. Dynamically created files ------------------------- @@ -450,6 +448,7 @@ the need for QEMU makefiles to go through any pre-processing as seen with autotools, where Makefile.am generates Makefile.in which generates Makefile. +Built by configure: - config-host.mak @@ -457,27 +456,17 @@ When configure has determined the characteristics of the build host it will write a long list of variables to config-host.mak file. This provides the various install directories, compiler / linker flags and a variety of CONFIG_* variables related to optionally enabled features. -This is imported by the top level Makefile in order to tailor the build -output. +This is imported by the top level Makefile and meson.build in order to +tailor the build output. + +config-host.mak is also used as a dependency checking mechanism. If make +sees that the modification timestamp on configure is newer than that on +config-host.mak, then configure will be re-run. The variables defined here are those which are applicable to all QEMU build outputs. Variables which are potentially different for each emulator target are defined by the next file... -It is also used as a dependency checking mechanism. If make sees that -the modification timestamp on configure is newer than that on -config-host.mak, then configure will be re-run. - - -- config-host.h - -The config-host.h file is used by source code to determine what features -are enabled. It is generated from the contents of config-host.mak using -the scripts/create_config program. This extracts all the CONFIG_* variables, -most of the HOST_* variables and a few other misc variables from -config-host.mak, formatting them as C preprocessor macros. - - - $TARGET-NAME/config-target.mak TARGET-NAME is the name of a system or userspace emulator, for example, @@ -488,19 +477,42 @@ the target and any other potential custom libraries needed for linking the target. -- $TARGET-NAME/config-devices.mak +Built by Meson: + +- ${TARGET-NAME}-config-devices.mak TARGET-NAME is again the name of a system or userspace emulator. The config-devices.mak file is automatically generated by make using the scripts/make_device_config.sh program, feeding it the default-configs/$TARGET-NAME file as input. +- config-host.h +- $TARGET-NAME/config-target.h +- $TARGET-NAME/config-devices.h + +These files are used by source code to determine what features +are enabled. They are generated from the contents of the corresponding +*.h files using the scripts/create_config program. This extracts +relevant variables and formats them as C preprocessor macros. + +- build.ninja + + +Built by Makefile: + +- Makefile.ninja: + +A Makefile conversion of the build rules in build.ninja. The conversion +is straightforward and, were it necessary to debug the rules produced +by Meson, it should be enough to look at build.ninja. The conversion +is performed by scripts/ninjatool.py. -- $TARGET-NAME/Makefile +- Makefile.mtest: -This is the entrypoint used when make recurses to build a single system -or userspace emulator target. It is merely a symlink back to the -Makefile.target in the top level. +The Makefile definitions that let "make check" run tests defined in +meson.build. The rules are produced from Meson's JSON description of +tests (obtained with "meson introspect --tests") through the script +scripts/mtest2make.py. Useful make targets -- cgit v1.2.3-55-g7522 From a14f0bf1657adef0328a3a756637b93f53ec0220 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 11 Aug 2020 18:34:40 +0200 Subject: docs: convert build system documentation to rST Signed-off-by: Paolo Bonzini --- docs/devel/build-system.rst | 500 +++++++++++++++++++++++++++++++++++++++++ docs/devel/build-system.txt | 528 -------------------------------------------- docs/devel/index.rst | 1 + 3 files changed, 501 insertions(+), 528 deletions(-) create mode 100644 docs/devel/build-system.rst delete mode 100644 docs/devel/build-system.txt diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst new file mode 100644 index 0000000000..58bf392430 --- /dev/null +++ b/docs/devel/build-system.rst @@ -0,0 +1,500 @@ +================================== +The QEMU build system architecture +================================== + +This document aims to help developers understand the architecture of the +QEMU build system. As with projects using GNU autotools, the QEMU build +system has two stages, first the developer runs the "configure" script +to determine the local build environment characteristics, then they run +"make" to build the project. There is about where the similarities with +GNU autotools end, so try to forget what you know about them. + + +Stage 1: configure +================== + +The QEMU configure script is written directly in shell, and should be +compatible with any POSIX shell, hence it uses #!/bin/sh. An important +implication of this is that it is important to avoid using bash-isms on +development platforms where bash is the primary host. + +In contrast to autoconf scripts, QEMU's configure is expected to be +silent while it is checking for features. It will only display output +when an error occurs, or to show the final feature enablement summary +on completion. + +Because QEMU uses the Meson build system under the hood, only VPATH +builds are supported. There are two general ways to invoke configure & +perform a build: + + - VPATH, build artifacts outside of QEMU source tree entirely:: + + cd ../ + mkdir build + cd build + ../qemu/configure + make + + - VPATH, build artifacts in a subdir of QEMU source tree:: + + mkdir build + cd build + ../configure + make + +For now, checks on the compilation environment are found in configure +rather than meson.build, though this is expected to change. The command +line is parsed in the configure script and, whenever needed, converted +into the appropriate options to Meson. + +New checks should be added to Meson, which usually comprises the +following tasks: + + - Add a Meson build option to meson_options.txt. + + - Add support to the command line arg parser to handle any new + `--enable-XXX`/`--disable-XXX` flags required by the feature. + + - Add information to the help output message to report on the new + feature flag. + + - Add code to perform the actual feature check. + + - Add code to include the feature status in `config-host.h` + + - Add code to print out the feature status in the configure summary + upon completion. + + +Taking the probe for SDL as an example, we have the following pieces +in configure:: + + # Initial variable state + sdl=auto + + ..snip.. + + # Configure flag processing + --disable-gnutls) sdl=disabled + ;; + --enable-gnutls) sdl=enabled + ;; + + ..snip.. + + # Help output feature message + sdl SDL UI + + ..snip.. + + # Meson invocation + -Dsdl=$sdl + +In meson_options.txt:: + + option('sdl', type : 'feature', value : 'auto') + +In meson.build:: + + # Detect dependency + sdl = dependency('sdl2', + required: get_option('sdl'), + static: enable_static) + + # Create config-host.h + config_host_data.set('CONFIG_SDL', sdl.found()) + + # Summary + summary_info += {'SDL support': sdl.found()} + + + +Helper functions +---------------- + +The configure script provides a variety of helper functions to assist +developers in checking for system features: + +`do_cc $ARGS...` + Attempt to run the system C compiler passing it $ARGS... + +`do_cxx $ARGS...` + Attempt to run the system C++ compiler passing it $ARGS... + +`compile_object $CFLAGS` + Attempt to compile a test program with the system C compiler using + $CFLAGS. The test program must have been previously written to a file + called $TMPC. + +`compile_prog $CFLAGS $LDFLAGS` + Attempt to compile a test program with the system C compiler using + $CFLAGS and link it with the system linker using $LDFLAGS. The test + program must have been previously written to a file called $TMPC. + +`has $COMMAND` + Determine if $COMMAND exists in the current environment, either as a + shell builtin, or executable binary, returning 0 on success. + +`path_of $COMMAND` + Return the fully qualified path of $COMMAND, printing it to stdout, + and returning 0 on success. + +`check_define $NAME` + Determine if the macro $NAME is defined by the system C compiler + +`check_include $NAME` + Determine if the include $NAME file is available to the system C + compiler + +`write_c_skeleton` + Write a minimal C program main() function to the temporary file + indicated by $TMPC + +`feature_not_found $NAME $REMEDY` + Print a message to stderr that the feature $NAME was not available + on the system, suggesting the user try $REMEDY to address the + problem. + +`error_exit $MESSAGE $MORE...` + Print $MESSAGE to stderr, followed by $MORE... and then exit from the + configure script with non-zero status + +`query_pkg_config $ARGS...` + Run pkg-config passing it $ARGS. If QEMU is doing a static build, + then --static will be automatically added to $ARGS + + +Stage 2: Meson +============== + +The Meson build system is currently used to describe the build +process for: + +1) executables, which include: + + - Tools - qemu-img, qemu-nbd, qga (guest agent), etc + + - System emulators - qemu-system-$ARCH + + - Userspace emulators - qemu-$ARCH + + - Some (but not all) unit tests + +2) documentation + +3) ROMs, which can be either installed as binary blobs or compiled + +4) other data files, such as icons or desktop files + +The source code is highly modularized, split across many files to +facilitate building of all of these components with as little duplicated +compilation as possible. The Meson "sourceset" functionality is used +to list the files and their dependency on various configuration +symbols. + +Various subsystems that are common to both tools and emulators have +their own sourceset, for example `block_ss` for the block device subsystem, +`chardev_ss` for the character device subsystem, etc. These sourcesets +are then turned into static libraries as follows:: + + libchardev = static_library('chardev', chardev_ss.sources(), + name_suffix: 'fa', + build_by_default: false) + + chardev = declare_dependency(link_whole: libchardev) + +The special `.fa` suffix is needed as long as unit tests are built with +the older Makefile infrastructure, and will go away later. + +Files linked into emulator targets there can be split into two distinct groups +of files, those which are independent of the QEMU emulation target and +those which are dependent on the QEMU emulation target. + +In the target-independent set lives various general purpose helper code, +such as error handling infrastructure, standard data structures, +platform portability wrapper functions, etc. This code can be compiled +once only and the .o files linked into all output binaries. +Target-independent code lives in the `common_ss`, `softmmu_ss` and +`user_ss` sourcesets. `common_ss` is linked into all emulators, `softmmu_ss` +only in system emulators, `user_ss` only in user-mode emulators. + +In the target-dependent set lives CPU emulation, device emulation and +much glue code. This sometimes also has to be compiled multiple times, +once for each target being built. + +All binaries link with a static library `libqemuutil.a`, which is then +linked to all the binaries. `libqemuutil.a` is built from several +sourcesets; most of them however host generated code, and the only two +of general interest are `util_ss` and `stub_ss`. + +The separation between these two is purely for documentation purposes. +`util_ss` contains generic utility files. Even though this code is only +linked in some binaries, sometimes it requires hooks only in some of +these and depend on other functions that are not fully implemented by +all QEMU binaries. `stub_ss` links dummy stubs that will only be linked +into the binary if the real implementation is not present. In a way, +the stubs can be thought of as a portable implementation of the weak +symbols concept. + +The following files concur in the definition of which files are linked +into each emulator: + +`default-configs/*.mak` + The files under default-configs/ control what emulated hardware is built + into each QEMU system and userspace emulator targets. They merely contain + a list of config variable definitions like the machines that should be + included. For example, default-configs/aarch64-softmmu.mak has:: + + include arm-softmmu.mak + CONFIG_XLNX_ZYNQMP_ARM=y + CONFIG_XLNX_VERSAL=y + +`*/Kconfig` + These files are processed together with `default-configs/*.mak` and + describe the dependencies between various features, subsystems and + device models. They are described in kconfig.rst. + +These files rarely need changing unless new devices / hardware need to +be enabled for a particular system/userspace emulation target + + +Support scripts +--------------- + +Meson has a special convention for invoking Python scripts: if their +first line is `#! /usr/bin/env python3` and the file is *not* executable, +find_program() arranges to invoke the script under the same Python +interpreter that was used to invoke Meson. This is the most common +and preferred way to invoke support scripts from Meson build files, +because it automatically uses the value of configure's --python= option. + +In case the script is not written in Python, use a `#! /usr/bin/env ...` +line and make the script executable. + +Scripts written in Python, where it is desirable to make the script +executable (for example for test scripts that developers may want to +invoke from the command line, such as tests/qapi-schema/test-qapi.py), +should be invoked through the `python` variable in meson.build. For +example:: + + test('QAPI schema regression tests', python, + args: files('test-qapi.py'), + env: test_env, suite: ['qapi-schema', 'qapi-frontend']) + +This is needed to obey the --python= option passed to the configure +script, which may point to something other than the first python3 +binary on the path. + + +Stage 3: makefiles +================== + +The use of GNU make is required with the QEMU build system. + +The output of Meson is a build.ninja file, which is used with the Ninja +build system. QEMU uses a different approach, where Makefile rules are +synthesized from the build.ninja file. The main Makefile includes these +rules and wraps them so that e.g. submodules are built before QEMU. +The resulting build system is largely non-recursive in nature, in +contrast to common practices seen with automake. + +Tests are also ran by the Makefile with the traditional `make check` +phony target. Meson test suites such as `unit` can be ran with `make +check-unit` too. It is also possible to run tests defined in meson.build +with `meson test`. + +The following text is only relevant for unit tests which still have to +be converted to Meson. + +All binaries should link to `libqemuutil.a`, e.g.: + + qemu-img$(EXESUF): qemu-img.o ..snip.. libqemuutil.a + +On Windows, all binaries have the suffix `.exe`, so all Makefile rules +which create binaries must include the $(EXESUF) variable on the binary +name. e.g. + + qemu-img$(EXESUF): qemu-img.o ..snip.. + +This expands to `.exe` on Windows, or an empty string on other platforms. + +Variable naming +--------------- + +The QEMU convention is to define variables to list different groups of +object files. These are named with the convention $PREFIX-obj-y. The +Meson `chardev` variable in the previous example corresponds to a +variable 'chardev-obj-y'. + +Likewise, tests that are executed by `make check-unit` are grouped into +a variable check-unit-y, like this: + + check-unit-y += tests/test-visitor-serialization$(EXESUF) + check-unit-y += tests/test-iov$(EXESUF) + check-unit-y += tests/test-bitmap$(EXESUF) + +When a test or object file which needs to be conditionally built based +on some characteristic of the host system, the configure script will +define a variable for the conditional. For example, on Windows it will +define $(CONFIG_POSIX) with a value of 'n' and $(CONFIG_WIN32) with a +value of 'y'. It is now possible to use the config variables when +listing object files. For example, + + check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) + +On Windows this expands to + + check-unit-n += tests/vmstate.exe + +Since the `check-unit` target only runs tests included in `$(check-unit-y)`, +POSIX specific tests listed in `$(util-obj-n)` are ignored on the Windows +platform builds. + + +CFLAGS / LDFLAGS / LIBS handling +-------------------------------- + +There are many different binaries being built with differing purposes, +and some of them might even be 3rd party libraries pulled in via git +submodules. As such the use of the global CFLAGS variable is generally +avoided in QEMU, since it would apply to too many build targets. + +Flags that are needed by any QEMU code (i.e. everything *except* GIT +submodule projects) are put in $(QEMU_CFLAGS) variable. For linker +flags the $(LIBS) variable is sometimes used, but a couple of more +targeted variables are preferred. + +In addition to these variables, it is possible to provide cflags and +libs against individual source code files, by defining variables of the +form $FILENAME-cflags and $FILENAME-libs. For example, the test +test-crypto-tlscredsx509 needs to link to the libtasn1 library, +so tests/Makefile.include defines some variables: + + tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS) + tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS) + +The scope is a little different between the two variables. The libs get +used when linking any target binary that includes the curl.o object +file, while the cflags get used when compiling the curl.c file only. + + +Important files for the build system +==================================== + +Statically defined files +------------------------ + +The following key files are statically defined in the source tree, with +the rules needed to build QEMU. Their behaviour is influenced by a +number of dynamically created files listed later. + +`Makefile` + The main entry point used when invoking make to build all the components + of QEMU. The default 'all' target will naturally result in the build of + every component. Makefile takes care of recursively building submodules + directly via a non-recursive set of rules. + +`*/meson.build` + The meson.build file in the root directory is the main entry point for the + Meson build system, and it coordinates the configuration and build of all + executables. Build rules for various subdirectories are included in + other meson.build files spread throughout the QEMU source tree. + +`rules.mak` + This file provides the generic helper rules for invoking build tools, in + particular the compiler and linker. + +`tests/Makefile.include` + Rules for building the unit tests. This file is included directly by the + top level Makefile, so anything defined in this file will influence the + entire build system. Care needs to be taken when writing rules for tests + to ensure they only apply to the unit test execution / build. + +`tests/docker/Makefile.include` + Rules for Docker tests. Like tests/Makefile, this file is included + directly by the top level Makefile, anything defined in this file will + influence the entire build system. + +`tests/vm/Makefile.include` + Rules for VM-based tests. Like tests/Makefile, this file is included + directly by the top level Makefile, anything defined in this file will + influence the entire build system. + +Dynamically created files +------------------------- + +The following files are generated dynamically by configure in order to +control the behaviour of the statically defined makefiles. This avoids +the need for QEMU makefiles to go through any pre-processing as seen +with autotools, where Makefile.am generates Makefile.in which generates +Makefile. + +Built by configure: + +`config-host.mak` + When configure has determined the characteristics of the build host it + will write a long list of variables to config-host.mak file. This + provides the various install directories, compiler / linker flags and a + variety of `CONFIG_*` variables related to optionally enabled features. + This is imported by the top level Makefile and meson.build in order to + tailor the build output. + + config-host.mak is also used as a dependency checking mechanism. If make + sees that the modification timestamp on configure is newer than that on + config-host.mak, then configure will be re-run. + + The variables defined here are those which are applicable to all QEMU + build outputs. Variables which are potentially different for each + emulator target are defined by the next file... + +`$TARGET-NAME/config-target.mak` + TARGET-NAME is the name of a system or userspace emulator, for example, + x86_64-softmmu denotes the system emulator for the x86_64 architecture. + This file contains the variables which need to vary on a per-target + basis. For example, it will indicate whether KVM or Xen are enabled for + the target and any other potential custom libraries needed for linking + the target. + + +Built by Meson: + +`${TARGET-NAME}-config-devices.mak` + TARGET-NAME is again the name of a system or userspace emulator. The + config-devices.mak file is automatically generated by make using the + scripts/make_device_config.sh program, feeding it the + default-configs/$TARGET-NAME file as input. + +`config-host.h`, `$TARGET-NAME/config-target.h`, `$TARGET-NAME/config-devices.h` + These files are used by source code to determine what features + are enabled. They are generated from the contents of the corresponding + `*.h` files using the scripts/create_config program. This extracts + relevant variables and formats them as C preprocessor macros. + +`build.ninja` + The build rules. + + +Built by Makefile: + +`Makefile.ninja` + A Makefile conversion of the build rules in build.ninja. The conversion + is straightforward and, were it necessary to debug the rules produced + by Meson, it should be enough to look at build.ninja. The conversion + is performed by scripts/ninjatool.py. + +`Makefile.mtest` + The Makefile definitions that let "make check" run tests defined in + meson.build. The rules are produced from Meson's JSON description of + tests (obtained with "meson introspect --tests") through the script + scripts/mtest2make.py. + + +Useful make targets +------------------- + +`help` + Print a help message for the most common build targets. + +`print-VAR` + Print the value of the variable VAR. Useful for debugging the build + system. diff --git a/docs/devel/build-system.txt b/docs/devel/build-system.txt deleted file mode 100644 index 2ced8ca474..0000000000 --- a/docs/devel/build-system.txt +++ /dev/null @@ -1,528 +0,0 @@ - The QEMU build system architecture - ================================== - -This document aims to help developers understand the architecture of the -QEMU build system. As with projects using GNU autotools, the QEMU build -system has two stages, first the developer runs the "configure" script -to determine the local build environment characteristics, then they run -"make" to build the project. There is about where the similarities with -GNU autotools end, so try to forget what you know about them. - - -Stage 1: configure -================== - -The QEMU configure script is written directly in shell, and should be -compatible with any POSIX shell, hence it uses #!/bin/sh. An important -implication of this is that it is important to avoid using bash-isms on -development platforms where bash is the primary host. - -In contrast to autoconf scripts, QEMU's configure is expected to be -silent while it is checking for features. It will only display output -when an error occurs, or to show the final feature enablement summary -on completion. - -Because QEMU uses the Meson build system under the hood, only VPATH -builds are supported. There are two general ways to invoke configure & -perform a build: - - - VPATH, build artifacts outside of QEMU source tree entirely - - cd ../ - mkdir build - cd build - ../qemu/configure - make - - - VPATH, build artifacts in a subdir of QEMU source tree - - mkdir build - cd build - ../configure - make - -For now, checks on the compilation environment are found in configure -rather than meson.build, though this is expected to change. The command -line is parsed in the configure script and, whenever needed, converted -into the appropriate options to Meson. - -New checks should be added to Meson, which usually comprises the -following tasks: - - - Add a Meson build option to meson_options.txt. - - - Add support to the command line arg parser to handle any new - --enable-XXX / --disable-XXX flags required by the feature XXX. - - - Add information to the help output message to report on the new - feature flag. - - - Add code to perform the actual feature check. - - - Add code to include the feature status in config-host.h - - - Add code to print out the feature status in the configure summary - upon completion. - - -Taking the probe for SDL as an example, we have the following pieces -in configure: - - # Initial variable state - sdl=auto - - ..snip.. - - # Configure flag processing - --disable-gnutls) sdl=disabled - ;; - --enable-gnutls) sdl=enabled - ;; - - ..snip.. - - # Help output feature message - sdl SDL UI - - ..snip.. - - # Meson invocation - -Dsdl=$sdl - -In meson_options.txt: - - option('sdl', type : 'feature', value : 'auto') - -In meson.build: - - # Detect dependency - sdl = dependency('sdl2', - required: get_option('sdl'), - static: enable_static) - - # Create config-host.h - config_host_data.set('CONFIG_SDL', sdl.found()) - - # Summary - summary_info += {'SDL support': sdl.found()} - - - -Helper functions ----------------- - -The configure script provides a variety of helper functions to assist -developers in checking for system features: - - - do_cc $ARGS... - - Attempt to run the system C compiler passing it $ARGS... - - - do_cxx $ARGS... - - Attempt to run the system C++ compiler passing it $ARGS... - - - compile_object $CFLAGS - - Attempt to compile a test program with the system C compiler using - $CFLAGS. The test program must have been previously written to a file - called $TMPC. - - - compile_prog $CFLAGS $LDFLAGS - - Attempt to compile a test program with the system C compiler using - $CFLAGS and link it with the system linker using $LDFLAGS. The test - program must have been previously written to a file called $TMPC. - - - has $COMMAND - - Determine if $COMMAND exists in the current environment, either as a - shell builtin, or executable binary, returning 0 on success. - - - path_of $COMMAND - - Return the fully qualified path of $COMMAND, printing it to stdout, - and returning 0 on success. - - - check_define $NAME - - Determine if the macro $NAME is defined by the system C compiler - - - check_include $NAME - - Determine if the include $NAME file is available to the system C - compiler - - - write_c_skeleton - - Write a minimal C program main() function to the temporary file - indicated by $TMPC - - - feature_not_found $NAME $REMEDY - - Print a message to stderr that the feature $NAME was not available - on the system, suggesting the user try $REMEDY to address the - problem. - - - error_exit $MESSAGE $MORE... - - Print $MESSAGE to stderr, followed by $MORE... and then exit from the - configure script with non-zero status - - - query_pkg_config $ARGS... - - Run pkg-config passing it $ARGS. If QEMU is doing a static build, - then --static will be automatically added to $ARGS - - -Stage 2: Meson -============== - -The Meson build system is currently used to describe the build -process for: - -1) executables, which include: - - Tools - qemu-img, qemu-nbd, qga (guest agent), etc - - System emulators - qemu-system-$ARCH - - Userspace emulators - qemu-$ARCH - - Some (but not all) unit tests - -2) documentation - -3) ROMs, which can be either installed as binary blobs or compiled - -4) other data files, such as icons or desktop files - -The source code is highly modularized, split across many files to -facilitate building of all of these components with as little duplicated -compilation as possible. The Meson "sourceset" functionality is used -to list the files and their dependency on various configuration -symbols. - -Various subsystems that are common to both tools and emulators have -their own sourceset, for example block_ss for the block device subsystem, -chardev_ss for the character device subsystem, etc. These sourcesets -are then turned into static libraries as follows: - - libchardev = static_library('chardev', chardev_ss.sources(), - name_suffix: 'fa', - build_by_default: false) - - chardev = declare_dependency(link_whole: libchardev) - -The special ".fa" suffix is needed as long as unit tests are built with -the older Makefile infrastructure, and will go away later. - -Files linked into emulator targets there can be split into two distinct groups -of files, those which are independent of the QEMU emulation target and -those which are dependent on the QEMU emulation target. - -In the target-independent set lives various general purpose helper code, -such as error handling infrastructure, standard data structures, -platform portability wrapper functions, etc. This code can be compiled -once only and the .o files linked into all output binaries. -Target-independent code lives in the common_ss, softmmu_ss and user_ss -sourcesets. common_ss is linked into all emulators, softmmu_ss only -in system emulators, user_ss only in user-mode emulators. - -In the target-dependent set lives CPU emulation, device emulation and -much glue code. This sometimes also has to be compiled multiple times, -once for each target being built. - -All binaries link with a static library libqemuutil.a, which is then -linked to all the binaries. libqemuutil.a is built from several -sourcesets; most of them however host generated code, and the only two -of general interest are util_ss and stub_ss. - -The separation between these two is purely for documentation purposes. -util_ss contains generic utility files. Even though this code is only -linked in some binaries, sometimes it requires hooks only in some of -these and depend on other functions that are not fully implemented by -all QEMU binaries. stub_ss links dummy stubs that will only be linked -into the binary if the real implementation is not present. In a way, -the stubs can be thought of as a portable implementation of the weak -symbols concept. - -The following files concur in the definition of which files are linked -into each emulator: - -- default-configs/*.mak - -The files under default-configs/ control what emulated hardware is built -into each QEMU system and userspace emulator targets. They merely contain -a list of config variable definitions like the machines that should be -included. For example, default-configs/aarch64-softmmu.mak has: - - include arm-softmmu.mak - CONFIG_XLNX_ZYNQMP_ARM=y - CONFIG_XLNX_VERSAL=y - -These files rarely need changing unless new devices / hardware need to -be enabled for a particular system/userspace emulation target - -- */Kconfig - -These files are processed together with default-configs/*.mak and -describe the dependencies between various features, subsystems and -device models. They are described in kconfig.rst. - - -Support scripts ---------------- - -Meson has a special convention for invoking Python scripts: if their -first line is "#! /usr/bin/env python3" and the file is *not* executable, -find_program() arranges to invoke the script under the same Python -interpreter that was used to invoke Meson. This is the most common -and preferred way to invoke support scripts from Meson build files, -because it automatically uses the value of configure's --python= option. - -In case the script is not written in Python, use a "#! /usr/bin/env ..." -line and make the script executable. - -Scripts written in Python, where it is desirable to make the script -executable (for example for test scripts that developers may want to -invoke from the command line, such as tests/qapi-schema/test-qapi.py), -should be invoked through the "python" variable in meson.build. For -example: - - test('QAPI schema regression tests', python, - args: files('test-qapi.py'), - env: test_env, suite: ['qapi-schema', 'qapi-frontend']) - -This is needed to obey the --python= option passed to the configure -script, which may point to something other than the first python3 -binary on the path. - - -Stage 3: makefiles -================== - -The use of GNU make is required with the QEMU build system. - -The output of Meson is a build.ninja file, which is used with the Ninja -build system. QEMU uses a different approach, where Makefile rules are -synthesized from the build.ninja file. The main Makefile includes these -rules and wraps them so that e.g. submodules are built before QEMU. -The resulting build system is largely non-recursive in nature, in -contrast to common practices seen with automake. - -Tests are also ran by the Makefile with the traditional "make check" -phony target. Meson test suites such as "unit" can be ran with "make -check-unit" too. It is also possible to run tests defined in meson.build -with "meson test". - -The following text is only relevant for unit tests which still have to -be converted to Meson. - -All binaries should link to libqemuutil.a, e.g.: - - qemu-img$(EXESUF): qemu-img.o ..snip.. libqemuutil.a - -On Windows, all binaries have the suffix '.exe', so all Makefile rules -which create binaries must include the $(EXESUF) variable on the binary -name. e.g. - - qemu-img$(EXESUF): qemu-img.o ..snip.. - -This expands to '.exe' on Windows, or '' on other platforms. - -Variable naming ---------------- - -The QEMU convention is to define variables to list different groups of -object files. These are named with the convention $PREFIX-obj-y. The -Meson "chardev" variable in the previous example corresponds to a -variable 'chardev-obj-y'. - -Likewise, tests that are executed by "make check-unit" are grouped into -a variable check-unit-y, like this: - - check-unit-y += tests/test-visitor-serialization$(EXESUF) - check-unit-y += tests/test-iov$(EXESUF) - check-unit-y += tests/test-bitmap$(EXESUF) - -When a test or object file which needs to be conditionally built based -on some characteristic of the host system, the configure script will -define a variable for the conditional. For example, on Windows it will -define $(CONFIG_POSIX) with a value of 'n' and $(CONFIG_WIN32) with a -value of 'y'. It is now possible to use the config variables when -listing object files. For example, - - check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) - -On Windows this expands to - - check-unit-n += tests/vmstate.exe - -Since the "check-unit" target only runs tests included in "$(check-unit-y)", -POSIX specific tests listed in $(util-obj-n) are ignored on the Windows -platform builds. - - -CFLAGS / LDFLAGS / LIBS handling --------------------------------- - -There are many different binaries being built with differing purposes, -and some of them might even be 3rd party libraries pulled in via git -submodules. As such the use of the global CFLAGS variable is generally -avoided in QEMU, since it would apply to too many build targets. - -Flags that are needed by any QEMU code (i.e. everything *except* GIT -submodule projects) are put in $(QEMU_CFLAGS) variable. For linker -flags the $(LIBS) variable is sometimes used, but a couple of more -targeted variables are preferred. - -In addition to these variables, it is possible to provide cflags and -libs against individual source code files, by defining variables of the -form $FILENAME-cflags and $FILENAME-libs. For example, the test -test-crypto-tlscredsx509 needs to link to the libtasn1 library, -so tests/Makefile.include defines some variables: - - tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS) - tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS) - -The scope is a little different between the two variables. The libs get -used when linking any target binary that includes the curl.o object -file, while the cflags get used when compiling the curl.c file only. - - -Important files for the build system -==================================== - -Statically defined files ------------------------- - -The following key files are statically defined in the source tree, with -the rules needed to build QEMU. Their behaviour is influenced by a -number of dynamically created files listed later. - -- Makefile - -The main entry point used when invoking make to build all the components -of QEMU. The default 'all' target will naturally result in the build of -every component. Makefile takes care of recursively building submodules -directly via a non-recursive set of rules. - -- Makefile.objs - -Defines *-obj-y files corresponding to - -- */meson.build - -The meson.build file in the root directory is the main entry point for the -Meson build system, and it coordinates the configuration and build of all -executables. Build rules for various subdirectories are included in -other meson.build files spread throughout the QEMU source tree. - -- rules.mak - -This file provides the generic helper rules for invoking build tools, in -particular the compiler and linker. - -- tests/Makefile.include - -Rules for building the unit tests. This file is included directly by the -top level Makefile, so anything defined in this file will influence the -entire build system. Care needs to be taken when writing rules for tests -to ensure they only apply to the unit test execution / build. - -- tests/docker/Makefile.include - -Rules for Docker tests. Like tests/Makefile, this file is included -directly by the top level Makefile, anything defined in this file will -influence the entire build system. - -- tests/vm/Makefile.include - -Rules for VM-based tests. Like tests/Makefile, this file is included -directly by the top level Makefile, anything defined in this file will -influence the entire build system. - -Dynamically created files -------------------------- - -The following files are generated dynamically by configure in order to -control the behaviour of the statically defined makefiles. This avoids -the need for QEMU makefiles to go through any pre-processing as seen -with autotools, where Makefile.am generates Makefile.in which generates -Makefile. - -Built by configure: - -- config-host.mak - -When configure has determined the characteristics of the build host it -will write a long list of variables to config-host.mak file. This -provides the various install directories, compiler / linker flags and a -variety of CONFIG_* variables related to optionally enabled features. -This is imported by the top level Makefile and meson.build in order to -tailor the build output. - -config-host.mak is also used as a dependency checking mechanism. If make -sees that the modification timestamp on configure is newer than that on -config-host.mak, then configure will be re-run. - -The variables defined here are those which are applicable to all QEMU -build outputs. Variables which are potentially different for each -emulator target are defined by the next file... - -- $TARGET-NAME/config-target.mak - -TARGET-NAME is the name of a system or userspace emulator, for example, -x86_64-softmmu denotes the system emulator for the x86_64 architecture. -This file contains the variables which need to vary on a per-target -basis. For example, it will indicate whether KVM or Xen are enabled for -the target and any other potential custom libraries needed for linking -the target. - - -Built by Meson: - -- ${TARGET-NAME}-config-devices.mak - -TARGET-NAME is again the name of a system or userspace emulator. The -config-devices.mak file is automatically generated by make using the -scripts/make_device_config.sh program, feeding it the -default-configs/$TARGET-NAME file as input. - -- config-host.h -- $TARGET-NAME/config-target.h -- $TARGET-NAME/config-devices.h - -These files are used by source code to determine what features -are enabled. They are generated from the contents of the corresponding -*.h files using the scripts/create_config program. This extracts -relevant variables and formats them as C preprocessor macros. - -- build.ninja - - -Built by Makefile: - -- Makefile.ninja: - -A Makefile conversion of the build rules in build.ninja. The conversion -is straightforward and, were it necessary to debug the rules produced -by Meson, it should be enough to look at build.ninja. The conversion -is performed by scripts/ninjatool.py. - -- Makefile.mtest: - -The Makefile definitions that let "make check" run tests defined in -meson.build. The rules are produced from Meson's JSON description of -tests (obtained with "meson introspect --tests") through the script -scripts/mtest2make.py. - - -Useful make targets -=================== - -- help - - Print a help message for the most common build targets. - -- print-VAR - - Print the value of the variable VAR. Useful for debugging the build - system. diff --git a/docs/devel/index.rst b/docs/devel/index.rst index ae6eac7c9c..04773ce076 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -13,6 +13,7 @@ Contents: .. toctree:: :maxdepth: 2 + build-system kconfig loads-stores memory -- cgit v1.2.3-55-g7522